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UBUNTU: Ubuntu-5.4.0-117.132
[mirror_ubuntu-focal-kernel.git] / drivers / gpu / drm / tegra / dc.c
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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2012 Avionic Design GmbH
4 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
5 */
6
7#include <linux/clk.h>
8#include <linux/debugfs.h>
9#include <linux/delay.h>
10#include <linux/iommu.h>
11#include <linux/module.h>
12#include <linux/of_device.h>
13#include <linux/pm_runtime.h>
14#include <linux/reset.h>
15
16#include <soc/tegra/pmc.h>
17
18#include <drm/drm_atomic.h>
19#include <drm/drm_atomic_helper.h>
20#include <drm/drm_debugfs.h>
21#include <drm/drm_fourcc.h>
22#include <drm/drm_plane_helper.h>
23#include <drm/drm_vblank.h>
24
25#include "dc.h"
26#include "drm.h"
27#include "gem.h"
28#include "hub.h"
29#include "plane.h"
30
31static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc,
32 struct drm_crtc_state *state);
33
34static void tegra_dc_stats_reset(struct tegra_dc_stats *stats)
35{
36 stats->frames = 0;
37 stats->vblank = 0;
38 stats->underflow = 0;
39 stats->overflow = 0;
40}
41
42/* Reads the active copy of a register. */
43static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset)
44{
45 u32 value;
46
47 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
48 value = tegra_dc_readl(dc, offset);
49 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
50
51 return value;
52}
53
54static inline unsigned int tegra_plane_offset(struct tegra_plane *plane,
55 unsigned int offset)
56{
57 if (offset >= 0x500 && offset <= 0x638) {
58 offset = 0x000 + (offset - 0x500);
59 return plane->offset + offset;
60 }
61
62 if (offset >= 0x700 && offset <= 0x719) {
63 offset = 0x180 + (offset - 0x700);
64 return plane->offset + offset;
65 }
66
67 if (offset >= 0x800 && offset <= 0x839) {
68 offset = 0x1c0 + (offset - 0x800);
69 return plane->offset + offset;
70 }
71
72 dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset);
73
74 return plane->offset + offset;
75}
76
77static inline u32 tegra_plane_readl(struct tegra_plane *plane,
78 unsigned int offset)
79{
80 return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset));
81}
82
83static inline void tegra_plane_writel(struct tegra_plane *plane, u32 value,
84 unsigned int offset)
85{
86 tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset));
87}
88
89bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev)
90{
91 struct device_node *np = dc->dev->of_node;
92 struct of_phandle_iterator it;
93 int err;
94
95 of_for_each_phandle(&it, err, np, "nvidia,outputs", NULL, 0)
96 if (it.node == dev->of_node)
97 return true;
98
99 return false;
100}
101
102/*
103 * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the
104 * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy.
105 * Latching happens mmediately if the display controller is in STOP mode or
106 * on the next frame boundary otherwise.
107 *
108 * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The
109 * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits
110 * are written. When the *_ACT_REQ bits are written, the ARM copy is latched
111 * into the ACTIVE copy, either immediately if the display controller is in
112 * STOP mode, or at the next frame boundary otherwise.
113 */
114void tegra_dc_commit(struct tegra_dc *dc)
115{
116 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
117 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
118}
119
120static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
121 unsigned int bpp)
122{
123 fixed20_12 outf = dfixed_init(out);
124 fixed20_12 inf = dfixed_init(in);
125 u32 dda_inc;
126 int max;
127
128 if (v)
129 max = 15;
130 else {
131 switch (bpp) {
132 case 2:
133 max = 8;
134 break;
135
136 default:
137 WARN_ON_ONCE(1);
138 /* fallthrough */
139 case 4:
140 max = 4;
141 break;
142 }
143 }
144
145 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
146 inf.full -= dfixed_const(1);
147
148 dda_inc = dfixed_div(inf, outf);
149 dda_inc = min_t(u32, dda_inc, dfixed_const(max));
150
151 return dda_inc;
152}
153
154static inline u32 compute_initial_dda(unsigned int in)
155{
156 fixed20_12 inf = dfixed_init(in);
157 return dfixed_frac(inf);
158}
159
160static void tegra_plane_setup_blending_legacy(struct tegra_plane *plane)
161{
162 u32 background[3] = {
163 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
164 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
165 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
166 };
167 u32 foreground = BLEND_WEIGHT1(255) | BLEND_WEIGHT0(255) |
168 BLEND_COLOR_KEY_NONE;
169 u32 blendnokey = BLEND_WEIGHT1(255) | BLEND_WEIGHT0(255);
170 struct tegra_plane_state *state;
171 u32 blending[2];
172 unsigned int i;
173
174 /* disable blending for non-overlapping case */
175 tegra_plane_writel(plane, blendnokey, DC_WIN_BLEND_NOKEY);
176 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_1WIN);
177
178 state = to_tegra_plane_state(plane->base.state);
179
180 if (state->opaque) {
181 /*
182 * Since custom fix-weight blending isn't utilized and weight
183 * of top window is set to max, we can enforce dependent
184 * blending which in this case results in transparent bottom
185 * window if top window is opaque and if top window enables
186 * alpha blending, then bottom window is getting alpha value
187 * of 1 minus the sum of alpha components of the overlapping
188 * plane.
189 */
190 background[0] |= BLEND_CONTROL_DEPENDENT;
191 background[1] |= BLEND_CONTROL_DEPENDENT;
192
193 /*
194 * The region where three windows overlap is the intersection
195 * of the two regions where two windows overlap. It contributes
196 * to the area if all of the windows on top of it have an alpha
197 * component.
198 */
199 switch (state->base.normalized_zpos) {
200 case 0:
201 if (state->blending[0].alpha &&
202 state->blending[1].alpha)
203 background[2] |= BLEND_CONTROL_DEPENDENT;
204 break;
205
206 case 1:
207 background[2] |= BLEND_CONTROL_DEPENDENT;
208 break;
209 }
210 } else {
211 /*
212 * Enable alpha blending if pixel format has an alpha
213 * component.
214 */
215 foreground |= BLEND_CONTROL_ALPHA;
216
217 /*
218 * If any of the windows on top of this window is opaque, it
219 * will completely conceal this window within that area. If
220 * top window has an alpha component, it is blended over the
221 * bottom window.
222 */
223 for (i = 0; i < 2; i++) {
224 if (state->blending[i].alpha &&
225 state->blending[i].top)
226 background[i] |= BLEND_CONTROL_DEPENDENT;
227 }
228
229 switch (state->base.normalized_zpos) {
230 case 0:
231 if (state->blending[0].alpha &&
232 state->blending[1].alpha)
233 background[2] |= BLEND_CONTROL_DEPENDENT;
234 break;
235
236 case 1:
237 /*
238 * When both middle and topmost windows have an alpha,
239 * these windows a mixed together and then the result
240 * is blended over the bottom window.
241 */
242 if (state->blending[0].alpha &&
243 state->blending[0].top)
244 background[2] |= BLEND_CONTROL_ALPHA;
245
246 if (state->blending[1].alpha &&
247 state->blending[1].top)
248 background[2] |= BLEND_CONTROL_ALPHA;
249 break;
250 }
251 }
252
253 switch (state->base.normalized_zpos) {
254 case 0:
255 tegra_plane_writel(plane, background[0], DC_WIN_BLEND_2WIN_X);
256 tegra_plane_writel(plane, background[1], DC_WIN_BLEND_2WIN_Y);
257 tegra_plane_writel(plane, background[2], DC_WIN_BLEND_3WIN_XY);
258 break;
259
260 case 1:
261 /*
262 * If window B / C is topmost, then X / Y registers are
263 * matching the order of blending[...] state indices,
264 * otherwise a swap is required.
265 */
266 if (!state->blending[0].top && state->blending[1].top) {
267 blending[0] = foreground;
268 blending[1] = background[1];
269 } else {
270 blending[0] = background[0];
271 blending[1] = foreground;
272 }
273
274 tegra_plane_writel(plane, blending[0], DC_WIN_BLEND_2WIN_X);
275 tegra_plane_writel(plane, blending[1], DC_WIN_BLEND_2WIN_Y);
276 tegra_plane_writel(plane, background[2], DC_WIN_BLEND_3WIN_XY);
277 break;
278
279 case 2:
280 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_X);
281 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_Y);
282 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_3WIN_XY);
283 break;
284 }
285}
286
287static void tegra_plane_setup_blending(struct tegra_plane *plane,
288 const struct tegra_dc_window *window)
289{
290 u32 value;
291
292 value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 |
293 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC |
294 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC;
295 tegra_plane_writel(plane, value, DC_WIN_BLEND_MATCH_SELECT);
296
297 value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 |
298 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC |
299 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC;
300 tegra_plane_writel(plane, value, DC_WIN_BLEND_NOMATCH_SELECT);
301
302 value = K2(255) | K1(255) | WINDOW_LAYER_DEPTH(255 - window->zpos);
303 tegra_plane_writel(plane, value, DC_WIN_BLEND_LAYER_CONTROL);
304}
305
306static bool
307tegra_plane_use_horizontal_filtering(struct tegra_plane *plane,
308 const struct tegra_dc_window *window)
309{
310 struct tegra_dc *dc = plane->dc;
311
312 if (window->src.w == window->dst.w)
313 return false;
314
315 if (plane->index == 0 && dc->soc->has_win_a_without_filters)
316 return false;
317
318 return true;
319}
320
321static bool
322tegra_plane_use_vertical_filtering(struct tegra_plane *plane,
323 const struct tegra_dc_window *window)
324{
325 struct tegra_dc *dc = plane->dc;
326
327 if (window->src.h == window->dst.h)
328 return false;
329
330 if (plane->index == 0 && dc->soc->has_win_a_without_filters)
331 return false;
332
333 if (plane->index == 2 && dc->soc->has_win_c_without_vert_filter)
334 return false;
335
336 return true;
337}
338
339static void tegra_dc_setup_window(struct tegra_plane *plane,
340 const struct tegra_dc_window *window)
341{
342 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
343 struct tegra_dc *dc = plane->dc;
344 bool yuv, planar;
345 u32 value;
346
347 /*
348 * For YUV planar modes, the number of bytes per pixel takes into
349 * account only the luma component and therefore is 1.
350 */
351 yuv = tegra_plane_format_is_yuv(window->format, &planar);
352 if (!yuv)
353 bpp = window->bits_per_pixel / 8;
354 else
355 bpp = planar ? 1 : 2;
356
357 tegra_plane_writel(plane, window->format, DC_WIN_COLOR_DEPTH);
358 tegra_plane_writel(plane, window->swap, DC_WIN_BYTE_SWAP);
359
360 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
361 tegra_plane_writel(plane, value, DC_WIN_POSITION);
362
363 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
364 tegra_plane_writel(plane, value, DC_WIN_SIZE);
365
366 h_offset = window->src.x * bpp;
367 v_offset = window->src.y;
368 h_size = window->src.w * bpp;
369 v_size = window->src.h;
370
371 value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
372 tegra_plane_writel(plane, value, DC_WIN_PRESCALED_SIZE);
373
374 /*
375 * For DDA computations the number of bytes per pixel for YUV planar
376 * modes needs to take into account all Y, U and V components.
377 */
378 if (yuv && planar)
379 bpp = 2;
380
381 h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
382 v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
383
384 value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
385 tegra_plane_writel(plane, value, DC_WIN_DDA_INC);
386
387 h_dda = compute_initial_dda(window->src.x);
388 v_dda = compute_initial_dda(window->src.y);
389
390 tegra_plane_writel(plane, h_dda, DC_WIN_H_INITIAL_DDA);
391 tegra_plane_writel(plane, v_dda, DC_WIN_V_INITIAL_DDA);
392
393 tegra_plane_writel(plane, 0, DC_WIN_UV_BUF_STRIDE);
394 tegra_plane_writel(plane, 0, DC_WIN_BUF_STRIDE);
395
396 tegra_plane_writel(plane, window->base[0], DC_WINBUF_START_ADDR);
397
398 if (yuv && planar) {
399 tegra_plane_writel(plane, window->base[1], DC_WINBUF_START_ADDR_U);
400 tegra_plane_writel(plane, window->base[2], DC_WINBUF_START_ADDR_V);
401 value = window->stride[1] << 16 | window->stride[0];
402 tegra_plane_writel(plane, value, DC_WIN_LINE_STRIDE);
403 } else {
404 tegra_plane_writel(plane, window->stride[0], DC_WIN_LINE_STRIDE);
405 }
406
407 if (window->bottom_up)
408 v_offset += window->src.h - 1;
409
410 tegra_plane_writel(plane, h_offset, DC_WINBUF_ADDR_H_OFFSET);
411 tegra_plane_writel(plane, v_offset, DC_WINBUF_ADDR_V_OFFSET);
412
413 if (dc->soc->supports_block_linear) {
414 unsigned long height = window->tiling.value;
415
416 switch (window->tiling.mode) {
417 case TEGRA_BO_TILING_MODE_PITCH:
418 value = DC_WINBUF_SURFACE_KIND_PITCH;
419 break;
420
421 case TEGRA_BO_TILING_MODE_TILED:
422 value = DC_WINBUF_SURFACE_KIND_TILED;
423 break;
424
425 case TEGRA_BO_TILING_MODE_BLOCK:
426 value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
427 DC_WINBUF_SURFACE_KIND_BLOCK;
428 break;
429 }
430
431 tegra_plane_writel(plane, value, DC_WINBUF_SURFACE_KIND);
432 } else {
433 switch (window->tiling.mode) {
434 case TEGRA_BO_TILING_MODE_PITCH:
435 value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
436 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
437 break;
438
439 case TEGRA_BO_TILING_MODE_TILED:
440 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
441 DC_WIN_BUFFER_ADDR_MODE_TILE;
442 break;
443
444 case TEGRA_BO_TILING_MODE_BLOCK:
445 /*
446 * No need to handle this here because ->atomic_check
447 * will already have filtered it out.
448 */
449 break;
450 }
451
452 tegra_plane_writel(plane, value, DC_WIN_BUFFER_ADDR_MODE);
453 }
454
455 value = WIN_ENABLE;
456
457 if (yuv) {
458 /* setup default colorspace conversion coefficients */
459 tegra_plane_writel(plane, 0x00f0, DC_WIN_CSC_YOF);
460 tegra_plane_writel(plane, 0x012a, DC_WIN_CSC_KYRGB);
461 tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KUR);
462 tegra_plane_writel(plane, 0x0198, DC_WIN_CSC_KVR);
463 tegra_plane_writel(plane, 0x039b, DC_WIN_CSC_KUG);
464 tegra_plane_writel(plane, 0x032f, DC_WIN_CSC_KVG);
465 tegra_plane_writel(plane, 0x0204, DC_WIN_CSC_KUB);
466 tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KVB);
467
468 value |= CSC_ENABLE;
469 } else if (window->bits_per_pixel < 24) {
470 value |= COLOR_EXPAND;
471 }
472
473 if (window->bottom_up)
474 value |= V_DIRECTION;
475
476 if (tegra_plane_use_horizontal_filtering(plane, window)) {
477 /*
478 * Enable horizontal 6-tap filter and set filtering
479 * coefficients to the default values defined in TRM.
480 */
481 tegra_plane_writel(plane, 0x00008000, DC_WIN_H_FILTER_P(0));
482 tegra_plane_writel(plane, 0x3e087ce1, DC_WIN_H_FILTER_P(1));
483 tegra_plane_writel(plane, 0x3b117ac1, DC_WIN_H_FILTER_P(2));
484 tegra_plane_writel(plane, 0x591b73aa, DC_WIN_H_FILTER_P(3));
485 tegra_plane_writel(plane, 0x57256d9a, DC_WIN_H_FILTER_P(4));
486 tegra_plane_writel(plane, 0x552f668b, DC_WIN_H_FILTER_P(5));
487 tegra_plane_writel(plane, 0x73385e8b, DC_WIN_H_FILTER_P(6));
488 tegra_plane_writel(plane, 0x72435583, DC_WIN_H_FILTER_P(7));
489 tegra_plane_writel(plane, 0x714c4c8b, DC_WIN_H_FILTER_P(8));
490 tegra_plane_writel(plane, 0x70554393, DC_WIN_H_FILTER_P(9));
491 tegra_plane_writel(plane, 0x715e389b, DC_WIN_H_FILTER_P(10));
492 tegra_plane_writel(plane, 0x71662faa, DC_WIN_H_FILTER_P(11));
493 tegra_plane_writel(plane, 0x536d25ba, DC_WIN_H_FILTER_P(12));
494 tegra_plane_writel(plane, 0x55731bca, DC_WIN_H_FILTER_P(13));
495 tegra_plane_writel(plane, 0x387a11d9, DC_WIN_H_FILTER_P(14));
496 tegra_plane_writel(plane, 0x3c7c08f1, DC_WIN_H_FILTER_P(15));
497
498 value |= H_FILTER;
499 }
500
501 if (tegra_plane_use_vertical_filtering(plane, window)) {
502 unsigned int i, k;
503
504 /*
505 * Enable vertical 2-tap filter and set filtering
506 * coefficients to the default values defined in TRM.
507 */
508 for (i = 0, k = 128; i < 16; i++, k -= 8)
509 tegra_plane_writel(plane, k, DC_WIN_V_FILTER_P(i));
510
511 value |= V_FILTER;
512 }
513
514 tegra_plane_writel(plane, value, DC_WIN_WIN_OPTIONS);
515
516 if (dc->soc->has_legacy_blending)
517 tegra_plane_setup_blending_legacy(plane);
518 else
519 tegra_plane_setup_blending(plane, window);
520}
521
522static const u32 tegra20_primary_formats[] = {
523 DRM_FORMAT_ARGB4444,
524 DRM_FORMAT_ARGB1555,
525 DRM_FORMAT_RGB565,
526 DRM_FORMAT_RGBA5551,
527 DRM_FORMAT_ABGR8888,
528 DRM_FORMAT_ARGB8888,
529 /* non-native formats */
530 DRM_FORMAT_XRGB1555,
531 DRM_FORMAT_RGBX5551,
532 DRM_FORMAT_XBGR8888,
533 DRM_FORMAT_XRGB8888,
534};
535
536static const u64 tegra20_modifiers[] = {
537 DRM_FORMAT_MOD_LINEAR,
538 DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED,
539 DRM_FORMAT_MOD_INVALID
540};
541
542static const u32 tegra114_primary_formats[] = {
543 DRM_FORMAT_ARGB4444,
544 DRM_FORMAT_ARGB1555,
545 DRM_FORMAT_RGB565,
546 DRM_FORMAT_RGBA5551,
547 DRM_FORMAT_ABGR8888,
548 DRM_FORMAT_ARGB8888,
549 /* new on Tegra114 */
550 DRM_FORMAT_ABGR4444,
551 DRM_FORMAT_ABGR1555,
552 DRM_FORMAT_BGRA5551,
553 DRM_FORMAT_XRGB1555,
554 DRM_FORMAT_RGBX5551,
555 DRM_FORMAT_XBGR1555,
556 DRM_FORMAT_BGRX5551,
557 DRM_FORMAT_BGR565,
558 DRM_FORMAT_BGRA8888,
559 DRM_FORMAT_RGBA8888,
560 DRM_FORMAT_XRGB8888,
561 DRM_FORMAT_XBGR8888,
562};
563
564static const u32 tegra124_primary_formats[] = {
565 DRM_FORMAT_ARGB4444,
566 DRM_FORMAT_ARGB1555,
567 DRM_FORMAT_RGB565,
568 DRM_FORMAT_RGBA5551,
569 DRM_FORMAT_ABGR8888,
570 DRM_FORMAT_ARGB8888,
571 /* new on Tegra114 */
572 DRM_FORMAT_ABGR4444,
573 DRM_FORMAT_ABGR1555,
574 DRM_FORMAT_BGRA5551,
575 DRM_FORMAT_XRGB1555,
576 DRM_FORMAT_RGBX5551,
577 DRM_FORMAT_XBGR1555,
578 DRM_FORMAT_BGRX5551,
579 DRM_FORMAT_BGR565,
580 DRM_FORMAT_BGRA8888,
581 DRM_FORMAT_RGBA8888,
582 DRM_FORMAT_XRGB8888,
583 DRM_FORMAT_XBGR8888,
584 /* new on Tegra124 */
585 DRM_FORMAT_RGBX8888,
586 DRM_FORMAT_BGRX8888,
587};
588
589static const u64 tegra124_modifiers[] = {
590 DRM_FORMAT_MOD_LINEAR,
591 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0),
592 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1),
593 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2),
594 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3),
595 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4),
596 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5),
597 DRM_FORMAT_MOD_INVALID
598};
599
600static int tegra_plane_atomic_check(struct drm_plane *plane,
601 struct drm_plane_state *state)
602{
603 struct tegra_plane_state *plane_state = to_tegra_plane_state(state);
604 unsigned int rotation = DRM_MODE_ROTATE_0 | DRM_MODE_REFLECT_Y;
605 struct tegra_bo_tiling *tiling = &plane_state->tiling;
606 struct tegra_plane *tegra = to_tegra_plane(plane);
607 struct tegra_dc *dc = to_tegra_dc(state->crtc);
608 int err;
609
610 /* no need for further checks if the plane is being disabled */
611 if (!state->crtc)
612 return 0;
613
614 err = tegra_plane_format(state->fb->format->format,
615 &plane_state->format,
616 &plane_state->swap);
617 if (err < 0)
618 return err;
619
620 /*
621 * Tegra20 and Tegra30 are special cases here because they support
622 * only variants of specific formats with an alpha component, but not
623 * the corresponding opaque formats. However, the opaque formats can
624 * be emulated by disabling alpha blending for the plane.
625 */
626 if (dc->soc->has_legacy_blending) {
627 err = tegra_plane_setup_legacy_state(tegra, plane_state);
628 if (err < 0)
629 return err;
630 }
631
632 err = tegra_fb_get_tiling(state->fb, tiling);
633 if (err < 0)
634 return err;
635
636 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK &&
637 !dc->soc->supports_block_linear) {
638 DRM_ERROR("hardware doesn't support block linear mode\n");
639 return -EINVAL;
640 }
641
642 rotation = drm_rotation_simplify(state->rotation, rotation);
643
644 if (rotation & DRM_MODE_REFLECT_Y)
645 plane_state->bottom_up = true;
646 else
647 plane_state->bottom_up = false;
648
649 /*
650 * Tegra doesn't support different strides for U and V planes so we
651 * error out if the user tries to display a framebuffer with such a
652 * configuration.
653 */
654 if (state->fb->format->num_planes > 2) {
655 if (state->fb->pitches[2] != state->fb->pitches[1]) {
656 DRM_ERROR("unsupported UV-plane configuration\n");
657 return -EINVAL;
658 }
659 }
660
661 err = tegra_plane_state_add(tegra, state);
662 if (err < 0)
663 return err;
664
665 return 0;
666}
667
668static void tegra_plane_atomic_disable(struct drm_plane *plane,
669 struct drm_plane_state *old_state)
670{
671 struct tegra_plane *p = to_tegra_plane(plane);
672 u32 value;
673
674 /* rien ne va plus */
675 if (!old_state || !old_state->crtc)
676 return;
677
678 value = tegra_plane_readl(p, DC_WIN_WIN_OPTIONS);
679 value &= ~WIN_ENABLE;
680 tegra_plane_writel(p, value, DC_WIN_WIN_OPTIONS);
681}
682
683static void tegra_plane_atomic_update(struct drm_plane *plane,
684 struct drm_plane_state *old_state)
685{
686 struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
687 struct drm_framebuffer *fb = plane->state->fb;
688 struct tegra_plane *p = to_tegra_plane(plane);
689 struct tegra_dc_window window;
690 unsigned int i;
691
692 /* rien ne va plus */
693 if (!plane->state->crtc || !plane->state->fb)
694 return;
695
696 if (!plane->state->visible)
697 return tegra_plane_atomic_disable(plane, old_state);
698
699 memset(&window, 0, sizeof(window));
700 window.src.x = plane->state->src.x1 >> 16;
701 window.src.y = plane->state->src.y1 >> 16;
702 window.src.w = drm_rect_width(&plane->state->src) >> 16;
703 window.src.h = drm_rect_height(&plane->state->src) >> 16;
704 window.dst.x = plane->state->dst.x1;
705 window.dst.y = plane->state->dst.y1;
706 window.dst.w = drm_rect_width(&plane->state->dst);
707 window.dst.h = drm_rect_height(&plane->state->dst);
708 window.bits_per_pixel = fb->format->cpp[0] * 8;
709 window.bottom_up = tegra_fb_is_bottom_up(fb) || state->bottom_up;
710
711 /* copy from state */
712 window.zpos = plane->state->normalized_zpos;
713 window.tiling = state->tiling;
714 window.format = state->format;
715 window.swap = state->swap;
716
717 for (i = 0; i < fb->format->num_planes; i++) {
718 struct tegra_bo *bo = tegra_fb_get_plane(fb, i);
719
720 window.base[i] = bo->paddr + fb->offsets[i];
721
722 /*
723 * Tegra uses a shared stride for UV planes. Framebuffers are
724 * already checked for this in the tegra_plane_atomic_check()
725 * function, so it's safe to ignore the V-plane pitch here.
726 */
727 if (i < 2)
728 window.stride[i] = fb->pitches[i];
729 }
730
731 tegra_dc_setup_window(p, &window);
732}
733
734static const struct drm_plane_helper_funcs tegra_plane_helper_funcs = {
735 .atomic_check = tegra_plane_atomic_check,
736 .atomic_disable = tegra_plane_atomic_disable,
737 .atomic_update = tegra_plane_atomic_update,
738};
739
740static unsigned long tegra_plane_get_possible_crtcs(struct drm_device *drm)
741{
742 /*
743 * Ideally this would use drm_crtc_mask(), but that would require the
744 * CRTC to already be in the mode_config's list of CRTCs. However, it
745 * will only be added to that list in the drm_crtc_init_with_planes()
746 * (in tegra_dc_init()), which in turn requires registration of these
747 * planes. So we have ourselves a nice little chicken and egg problem
748 * here.
749 *
750 * We work around this by manually creating the mask from the number
751 * of CRTCs that have been registered, and should therefore always be
752 * the same as drm_crtc_index() after registration.
753 */
754 return 1 << drm->mode_config.num_crtc;
755}
756
757static struct drm_plane *tegra_primary_plane_create(struct drm_device *drm,
758 struct tegra_dc *dc)
759{
760 unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
761 enum drm_plane_type type = DRM_PLANE_TYPE_PRIMARY;
762 struct tegra_plane *plane;
763 unsigned int num_formats;
764 const u64 *modifiers;
765 const u32 *formats;
766 int err;
767
768 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
769 if (!plane)
770 return ERR_PTR(-ENOMEM);
771
772 /* Always use window A as primary window */
773 plane->offset = 0xa00;
774 plane->index = 0;
775 plane->dc = dc;
776
777 num_formats = dc->soc->num_primary_formats;
778 formats = dc->soc->primary_formats;
779 modifiers = dc->soc->modifiers;
780
781 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
782 &tegra_plane_funcs, formats,
783 num_formats, modifiers, type, NULL);
784 if (err < 0) {
785 kfree(plane);
786 return ERR_PTR(err);
787 }
788
789 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs);
790 drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255);
791
792 err = drm_plane_create_rotation_property(&plane->base,
793 DRM_MODE_ROTATE_0,
794 DRM_MODE_ROTATE_0 |
795 DRM_MODE_REFLECT_Y);
796 if (err < 0)
797 dev_err(dc->dev, "failed to create rotation property: %d\n",
798 err);
799
800 return &plane->base;
801}
802
803static const u32 tegra_cursor_plane_formats[] = {
804 DRM_FORMAT_RGBA8888,
805};
806
807static int tegra_cursor_atomic_check(struct drm_plane *plane,
808 struct drm_plane_state *state)
809{
810 struct tegra_plane *tegra = to_tegra_plane(plane);
811 int err;
812
813 /* no need for further checks if the plane is being disabled */
814 if (!state->crtc)
815 return 0;
816
817 /* scaling not supported for cursor */
818 if ((state->src_w >> 16 != state->crtc_w) ||
819 (state->src_h >> 16 != state->crtc_h))
820 return -EINVAL;
821
822 /* only square cursors supported */
823 if (state->src_w != state->src_h)
824 return -EINVAL;
825
826 if (state->crtc_w != 32 && state->crtc_w != 64 &&
827 state->crtc_w != 128 && state->crtc_w != 256)
828 return -EINVAL;
829
830 err = tegra_plane_state_add(tegra, state);
831 if (err < 0)
832 return err;
833
834 return 0;
835}
836
837static void tegra_cursor_atomic_update(struct drm_plane *plane,
838 struct drm_plane_state *old_state)
839{
840 struct tegra_bo *bo = tegra_fb_get_plane(plane->state->fb, 0);
841 struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
842 struct drm_plane_state *state = plane->state;
843 u32 value = CURSOR_CLIP_DISPLAY;
844
845 /* rien ne va plus */
846 if (!plane->state->crtc || !plane->state->fb)
847 return;
848
849 switch (state->crtc_w) {
850 case 32:
851 value |= CURSOR_SIZE_32x32;
852 break;
853
854 case 64:
855 value |= CURSOR_SIZE_64x64;
856 break;
857
858 case 128:
859 value |= CURSOR_SIZE_128x128;
860 break;
861
862 case 256:
863 value |= CURSOR_SIZE_256x256;
864 break;
865
866 default:
867 WARN(1, "cursor size %ux%u not supported\n", state->crtc_w,
868 state->crtc_h);
869 return;
870 }
871
872 value |= (bo->paddr >> 10) & 0x3fffff;
873 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR);
874
875#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
876 value = (bo->paddr >> 32) & 0x3;
877 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI);
878#endif
879
880 /* enable cursor and set blend mode */
881 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
882 value |= CURSOR_ENABLE;
883 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
884
885 value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL);
886 value &= ~CURSOR_DST_BLEND_MASK;
887 value &= ~CURSOR_SRC_BLEND_MASK;
888 value |= CURSOR_MODE_NORMAL;
889 value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC;
890 value |= CURSOR_SRC_BLEND_K1_TIMES_SRC;
891 value |= CURSOR_ALPHA;
892 tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);
893
894 /* position the cursor */
895 value = (state->crtc_y & 0x3fff) << 16 | (state->crtc_x & 0x3fff);
896 tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);
897}
898
899static void tegra_cursor_atomic_disable(struct drm_plane *plane,
900 struct drm_plane_state *old_state)
901{
902 struct tegra_dc *dc;
903 u32 value;
904
905 /* rien ne va plus */
906 if (!old_state || !old_state->crtc)
907 return;
908
909 dc = to_tegra_dc(old_state->crtc);
910
911 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
912 value &= ~CURSOR_ENABLE;
913 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
914}
915
916static const struct drm_plane_helper_funcs tegra_cursor_plane_helper_funcs = {
917 .atomic_check = tegra_cursor_atomic_check,
918 .atomic_update = tegra_cursor_atomic_update,
919 .atomic_disable = tegra_cursor_atomic_disable,
920};
921
922static const uint64_t linear_modifiers[] = {
923 DRM_FORMAT_MOD_LINEAR,
924 DRM_FORMAT_MOD_INVALID
925};
926
927static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm,
928 struct tegra_dc *dc)
929{
930 unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
931 struct tegra_plane *plane;
932 unsigned int num_formats;
933 const u32 *formats;
934 int err;
935
936 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
937 if (!plane)
938 return ERR_PTR(-ENOMEM);
939
940 /*
941 * This index is kind of fake. The cursor isn't a regular plane, but
942 * its update and activation request bits in DC_CMD_STATE_CONTROL do
943 * use the same programming. Setting this fake index here allows the
944 * code in tegra_add_plane_state() to do the right thing without the
945 * need to special-casing the cursor plane.
946 */
947 plane->index = 6;
948 plane->dc = dc;
949
950 num_formats = ARRAY_SIZE(tegra_cursor_plane_formats);
951 formats = tegra_cursor_plane_formats;
952
953 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
954 &tegra_plane_funcs, formats,
955 num_formats, linear_modifiers,
956 DRM_PLANE_TYPE_CURSOR, NULL);
957 if (err < 0) {
958 kfree(plane);
959 return ERR_PTR(err);
960 }
961
962 drm_plane_helper_add(&plane->base, &tegra_cursor_plane_helper_funcs);
963
964 return &plane->base;
965}
966
967static const u32 tegra20_overlay_formats[] = {
968 DRM_FORMAT_ARGB4444,
969 DRM_FORMAT_ARGB1555,
970 DRM_FORMAT_RGB565,
971 DRM_FORMAT_RGBA5551,
972 DRM_FORMAT_ABGR8888,
973 DRM_FORMAT_ARGB8888,
974 /* non-native formats */
975 DRM_FORMAT_XRGB1555,
976 DRM_FORMAT_RGBX5551,
977 DRM_FORMAT_XBGR8888,
978 DRM_FORMAT_XRGB8888,
979 /* planar formats */
980 DRM_FORMAT_UYVY,
981 DRM_FORMAT_YUYV,
982 DRM_FORMAT_YUV420,
983 DRM_FORMAT_YUV422,
984};
985
986static const u32 tegra114_overlay_formats[] = {
987 DRM_FORMAT_ARGB4444,
988 DRM_FORMAT_ARGB1555,
989 DRM_FORMAT_RGB565,
990 DRM_FORMAT_RGBA5551,
991 DRM_FORMAT_ABGR8888,
992 DRM_FORMAT_ARGB8888,
993 /* new on Tegra114 */
994 DRM_FORMAT_ABGR4444,
995 DRM_FORMAT_ABGR1555,
996 DRM_FORMAT_BGRA5551,
997 DRM_FORMAT_XRGB1555,
998 DRM_FORMAT_RGBX5551,
999 DRM_FORMAT_XBGR1555,
1000 DRM_FORMAT_BGRX5551,
1001 DRM_FORMAT_BGR565,
1002 DRM_FORMAT_BGRA8888,
1003 DRM_FORMAT_RGBA8888,
1004 DRM_FORMAT_XRGB8888,
1005 DRM_FORMAT_XBGR8888,
1006 /* planar formats */
1007 DRM_FORMAT_UYVY,
1008 DRM_FORMAT_YUYV,
1009 DRM_FORMAT_YUV420,
1010 DRM_FORMAT_YUV422,
1011};
1012
1013static const u32 tegra124_overlay_formats[] = {
1014 DRM_FORMAT_ARGB4444,
1015 DRM_FORMAT_ARGB1555,
1016 DRM_FORMAT_RGB565,
1017 DRM_FORMAT_RGBA5551,
1018 DRM_FORMAT_ABGR8888,
1019 DRM_FORMAT_ARGB8888,
1020 /* new on Tegra114 */
1021 DRM_FORMAT_ABGR4444,
1022 DRM_FORMAT_ABGR1555,
1023 DRM_FORMAT_BGRA5551,
1024 DRM_FORMAT_XRGB1555,
1025 DRM_FORMAT_RGBX5551,
1026 DRM_FORMAT_XBGR1555,
1027 DRM_FORMAT_BGRX5551,
1028 DRM_FORMAT_BGR565,
1029 DRM_FORMAT_BGRA8888,
1030 DRM_FORMAT_RGBA8888,
1031 DRM_FORMAT_XRGB8888,
1032 DRM_FORMAT_XBGR8888,
1033 /* new on Tegra124 */
1034 DRM_FORMAT_RGBX8888,
1035 DRM_FORMAT_BGRX8888,
1036 /* planar formats */
1037 DRM_FORMAT_UYVY,
1038 DRM_FORMAT_YUYV,
1039 DRM_FORMAT_YUV420,
1040 DRM_FORMAT_YUV422,
1041};
1042
1043static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm,
1044 struct tegra_dc *dc,
1045 unsigned int index,
1046 bool cursor)
1047{
1048 unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
1049 struct tegra_plane *plane;
1050 unsigned int num_formats;
1051 enum drm_plane_type type;
1052 const u32 *formats;
1053 int err;
1054
1055 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
1056 if (!plane)
1057 return ERR_PTR(-ENOMEM);
1058
1059 plane->offset = 0xa00 + 0x200 * index;
1060 plane->index = index;
1061 plane->dc = dc;
1062
1063 num_formats = dc->soc->num_overlay_formats;
1064 formats = dc->soc->overlay_formats;
1065
1066 if (!cursor)
1067 type = DRM_PLANE_TYPE_OVERLAY;
1068 else
1069 type = DRM_PLANE_TYPE_CURSOR;
1070
1071 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
1072 &tegra_plane_funcs, formats,
1073 num_formats, linear_modifiers,
1074 type, NULL);
1075 if (err < 0) {
1076 kfree(plane);
1077 return ERR_PTR(err);
1078 }
1079
1080 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs);
1081 drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255);
1082
1083 err = drm_plane_create_rotation_property(&plane->base,
1084 DRM_MODE_ROTATE_0,
1085 DRM_MODE_ROTATE_0 |
1086 DRM_MODE_REFLECT_Y);
1087 if (err < 0)
1088 dev_err(dc->dev, "failed to create rotation property: %d\n",
1089 err);
1090
1091 return &plane->base;
1092}
1093
1094static struct drm_plane *tegra_dc_add_shared_planes(struct drm_device *drm,
1095 struct tegra_dc *dc)
1096{
1097 struct drm_plane *plane, *primary = NULL;
1098 unsigned int i, j;
1099
1100 for (i = 0; i < dc->soc->num_wgrps; i++) {
1101 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i];
1102
1103 if (wgrp->dc == dc->pipe) {
1104 for (j = 0; j < wgrp->num_windows; j++) {
1105 unsigned int index = wgrp->windows[j];
1106
1107 plane = tegra_shared_plane_create(drm, dc,
1108 wgrp->index,
1109 index);
1110 if (IS_ERR(plane))
1111 return plane;
1112
1113 /*
1114 * Choose the first shared plane owned by this
1115 * head as the primary plane.
1116 */
1117 if (!primary) {
1118 plane->type = DRM_PLANE_TYPE_PRIMARY;
1119 primary = plane;
1120 }
1121 }
1122 }
1123 }
1124
1125 return primary;
1126}
1127
1128static struct drm_plane *tegra_dc_add_planes(struct drm_device *drm,
1129 struct tegra_dc *dc)
1130{
1131 struct drm_plane *planes[2], *primary;
1132 unsigned int planes_num;
1133 unsigned int i;
1134 int err;
1135
1136 primary = tegra_primary_plane_create(drm, dc);
1137 if (IS_ERR(primary))
1138 return primary;
1139
1140 if (dc->soc->supports_cursor)
1141 planes_num = 2;
1142 else
1143 planes_num = 1;
1144
1145 for (i = 0; i < planes_num; i++) {
1146 planes[i] = tegra_dc_overlay_plane_create(drm, dc, 1 + i,
1147 false);
1148 if (IS_ERR(planes[i])) {
1149 err = PTR_ERR(planes[i]);
1150
1151 while (i--)
1152 tegra_plane_funcs.destroy(planes[i]);
1153
1154 tegra_plane_funcs.destroy(primary);
1155 return ERR_PTR(err);
1156 }
1157 }
1158
1159 return primary;
1160}
1161
1162static void tegra_dc_destroy(struct drm_crtc *crtc)
1163{
1164 drm_crtc_cleanup(crtc);
1165}
1166
1167static void tegra_crtc_reset(struct drm_crtc *crtc)
1168{
1169 struct tegra_dc_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
1170
1171 if (crtc->state)
1172 tegra_crtc_atomic_destroy_state(crtc, crtc->state);
1173
1174 __drm_atomic_helper_crtc_reset(crtc, &state->base);
1175 drm_crtc_vblank_reset(crtc);
1176}
1177
1178static struct drm_crtc_state *
1179tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
1180{
1181 struct tegra_dc_state *state = to_dc_state(crtc->state);
1182 struct tegra_dc_state *copy;
1183
1184 copy = kmalloc(sizeof(*copy), GFP_KERNEL);
1185 if (!copy)
1186 return NULL;
1187
1188 __drm_atomic_helper_crtc_duplicate_state(crtc, &copy->base);
1189 copy->clk = state->clk;
1190 copy->pclk = state->pclk;
1191 copy->div = state->div;
1192 copy->planes = state->planes;
1193
1194 return &copy->base;
1195}
1196
1197static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc,
1198 struct drm_crtc_state *state)
1199{
1200 __drm_atomic_helper_crtc_destroy_state(state);
1201 kfree(state);
1202}
1203
1204#define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
1205
1206static const struct debugfs_reg32 tegra_dc_regs[] = {
1207 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT),
1208 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL),
1209 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_ERROR),
1210 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT),
1211 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL),
1212 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_ERROR),
1213 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT),
1214 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL),
1215 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_ERROR),
1216 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT),
1217 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL),
1218 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_ERROR),
1219 DEBUGFS_REG32(DC_CMD_CONT_SYNCPT_VSYNC),
1220 DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND_OPTION0),
1221 DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND),
1222 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE),
1223 DEBUGFS_REG32(DC_CMD_DISPLAY_POWER_CONTROL),
1224 DEBUGFS_REG32(DC_CMD_INT_STATUS),
1225 DEBUGFS_REG32(DC_CMD_INT_MASK),
1226 DEBUGFS_REG32(DC_CMD_INT_ENABLE),
1227 DEBUGFS_REG32(DC_CMD_INT_TYPE),
1228 DEBUGFS_REG32(DC_CMD_INT_POLARITY),
1229 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE1),
1230 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE2),
1231 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE3),
1232 DEBUGFS_REG32(DC_CMD_STATE_ACCESS),
1233 DEBUGFS_REG32(DC_CMD_STATE_CONTROL),
1234 DEBUGFS_REG32(DC_CMD_DISPLAY_WINDOW_HEADER),
1235 DEBUGFS_REG32(DC_CMD_REG_ACT_CONTROL),
1236 DEBUGFS_REG32(DC_COM_CRC_CONTROL),
1237 DEBUGFS_REG32(DC_COM_CRC_CHECKSUM),
1238 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(0)),
1239 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(1)),
1240 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(2)),
1241 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(3)),
1242 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(0)),
1243 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(1)),
1244 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(2)),
1245 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(3)),
1246 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(0)),
1247 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(1)),
1248 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(2)),
1249 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(3)),
1250 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(0)),
1251 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(1)),
1252 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(2)),
1253 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(3)),
1254 DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(0)),
1255 DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(1)),
1256 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(0)),
1257 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(1)),
1258 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(2)),
1259 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(3)),
1260 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(4)),
1261 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(5)),
1262 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(6)),
1263 DEBUGFS_REG32(DC_COM_PIN_MISC_CONTROL),
1264 DEBUGFS_REG32(DC_COM_PIN_PM0_CONTROL),
1265 DEBUGFS_REG32(DC_COM_PIN_PM0_DUTY_CYCLE),
1266 DEBUGFS_REG32(DC_COM_PIN_PM1_CONTROL),
1267 DEBUGFS_REG32(DC_COM_PIN_PM1_DUTY_CYCLE),
1268 DEBUGFS_REG32(DC_COM_SPI_CONTROL),
1269 DEBUGFS_REG32(DC_COM_SPI_START_BYTE),
1270 DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_AB),
1271 DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_CD),
1272 DEBUGFS_REG32(DC_COM_HSPI_CS_DC),
1273 DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_A),
1274 DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_B),
1275 DEBUGFS_REG32(DC_COM_GPIO_CTRL),
1276 DEBUGFS_REG32(DC_COM_GPIO_DEBOUNCE_COUNTER),
1277 DEBUGFS_REG32(DC_COM_CRC_CHECKSUM_LATCHED),
1278 DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS0),
1279 DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS1),
1280 DEBUGFS_REG32(DC_DISP_DISP_WIN_OPTIONS),
1281 DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY),
1282 DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER),
1283 DEBUGFS_REG32(DC_DISP_DISP_TIMING_OPTIONS),
1284 DEBUGFS_REG32(DC_DISP_REF_TO_SYNC),
1285 DEBUGFS_REG32(DC_DISP_SYNC_WIDTH),
1286 DEBUGFS_REG32(DC_DISP_BACK_PORCH),
1287 DEBUGFS_REG32(DC_DISP_ACTIVE),
1288 DEBUGFS_REG32(DC_DISP_FRONT_PORCH),
1289 DEBUGFS_REG32(DC_DISP_H_PULSE0_CONTROL),
1290 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_A),
1291 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_B),
1292 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_C),
1293 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_D),
1294 DEBUGFS_REG32(DC_DISP_H_PULSE1_CONTROL),
1295 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_A),
1296 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_B),
1297 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_C),
1298 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_D),
1299 DEBUGFS_REG32(DC_DISP_H_PULSE2_CONTROL),
1300 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_A),
1301 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_B),
1302 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_C),
1303 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_D),
1304 DEBUGFS_REG32(DC_DISP_V_PULSE0_CONTROL),
1305 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_A),
1306 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_B),
1307 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_C),
1308 DEBUGFS_REG32(DC_DISP_V_PULSE1_CONTROL),
1309 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_A),
1310 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_B),
1311 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_C),
1312 DEBUGFS_REG32(DC_DISP_V_PULSE2_CONTROL),
1313 DEBUGFS_REG32(DC_DISP_V_PULSE2_POSITION_A),
1314 DEBUGFS_REG32(DC_DISP_V_PULSE3_CONTROL),
1315 DEBUGFS_REG32(DC_DISP_V_PULSE3_POSITION_A),
1316 DEBUGFS_REG32(DC_DISP_M0_CONTROL),
1317 DEBUGFS_REG32(DC_DISP_M1_CONTROL),
1318 DEBUGFS_REG32(DC_DISP_DI_CONTROL),
1319 DEBUGFS_REG32(DC_DISP_PP_CONTROL),
1320 DEBUGFS_REG32(DC_DISP_PP_SELECT_A),
1321 DEBUGFS_REG32(DC_DISP_PP_SELECT_B),
1322 DEBUGFS_REG32(DC_DISP_PP_SELECT_C),
1323 DEBUGFS_REG32(DC_DISP_PP_SELECT_D),
1324 DEBUGFS_REG32(DC_DISP_DISP_CLOCK_CONTROL),
1325 DEBUGFS_REG32(DC_DISP_DISP_INTERFACE_CONTROL),
1326 DEBUGFS_REG32(DC_DISP_DISP_COLOR_CONTROL),
1327 DEBUGFS_REG32(DC_DISP_SHIFT_CLOCK_OPTIONS),
1328 DEBUGFS_REG32(DC_DISP_DATA_ENABLE_OPTIONS),
1329 DEBUGFS_REG32(DC_DISP_SERIAL_INTERFACE_OPTIONS),
1330 DEBUGFS_REG32(DC_DISP_LCD_SPI_OPTIONS),
1331 DEBUGFS_REG32(DC_DISP_BORDER_COLOR),
1332 DEBUGFS_REG32(DC_DISP_COLOR_KEY0_LOWER),
1333 DEBUGFS_REG32(DC_DISP_COLOR_KEY0_UPPER),
1334 DEBUGFS_REG32(DC_DISP_COLOR_KEY1_LOWER),
1335 DEBUGFS_REG32(DC_DISP_COLOR_KEY1_UPPER),
1336 DEBUGFS_REG32(DC_DISP_CURSOR_FOREGROUND),
1337 DEBUGFS_REG32(DC_DISP_CURSOR_BACKGROUND),
1338 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR),
1339 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_NS),
1340 DEBUGFS_REG32(DC_DISP_CURSOR_POSITION),
1341 DEBUGFS_REG32(DC_DISP_CURSOR_POSITION_NS),
1342 DEBUGFS_REG32(DC_DISP_INIT_SEQ_CONTROL),
1343 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_A),
1344 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_B),
1345 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_C),
1346 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_D),
1347 DEBUGFS_REG32(DC_DISP_DC_MCCIF_FIFOCTRL),
1348 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0A_HYST),
1349 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0B_HYST),
1350 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1A_HYST),
1351 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1B_HYST),
1352 DEBUGFS_REG32(DC_DISP_DAC_CRT_CTRL),
1353 DEBUGFS_REG32(DC_DISP_DISP_MISC_CONTROL),
1354 DEBUGFS_REG32(DC_DISP_SD_CONTROL),
1355 DEBUGFS_REG32(DC_DISP_SD_CSC_COEFF),
1356 DEBUGFS_REG32(DC_DISP_SD_LUT(0)),
1357 DEBUGFS_REG32(DC_DISP_SD_LUT(1)),
1358 DEBUGFS_REG32(DC_DISP_SD_LUT(2)),
1359 DEBUGFS_REG32(DC_DISP_SD_LUT(3)),
1360 DEBUGFS_REG32(DC_DISP_SD_LUT(4)),
1361 DEBUGFS_REG32(DC_DISP_SD_LUT(5)),
1362 DEBUGFS_REG32(DC_DISP_SD_LUT(6)),
1363 DEBUGFS_REG32(DC_DISP_SD_LUT(7)),
1364 DEBUGFS_REG32(DC_DISP_SD_LUT(8)),
1365 DEBUGFS_REG32(DC_DISP_SD_FLICKER_CONTROL),
1366 DEBUGFS_REG32(DC_DISP_DC_PIXEL_COUNT),
1367 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(0)),
1368 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(1)),
1369 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(2)),
1370 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(3)),
1371 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(4)),
1372 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(5)),
1373 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(6)),
1374 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(7)),
1375 DEBUGFS_REG32(DC_DISP_SD_BL_TF(0)),
1376 DEBUGFS_REG32(DC_DISP_SD_BL_TF(1)),
1377 DEBUGFS_REG32(DC_DISP_SD_BL_TF(2)),
1378 DEBUGFS_REG32(DC_DISP_SD_BL_TF(3)),
1379 DEBUGFS_REG32(DC_DISP_SD_BL_CONTROL),
1380 DEBUGFS_REG32(DC_DISP_SD_HW_K_VALUES),
1381 DEBUGFS_REG32(DC_DISP_SD_MAN_K_VALUES),
1382 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_HI),
1383 DEBUGFS_REG32(DC_DISP_BLEND_CURSOR_CONTROL),
1384 DEBUGFS_REG32(DC_WIN_WIN_OPTIONS),
1385 DEBUGFS_REG32(DC_WIN_BYTE_SWAP),
1386 DEBUGFS_REG32(DC_WIN_BUFFER_CONTROL),
1387 DEBUGFS_REG32(DC_WIN_COLOR_DEPTH),
1388 DEBUGFS_REG32(DC_WIN_POSITION),
1389 DEBUGFS_REG32(DC_WIN_SIZE),
1390 DEBUGFS_REG32(DC_WIN_PRESCALED_SIZE),
1391 DEBUGFS_REG32(DC_WIN_H_INITIAL_DDA),
1392 DEBUGFS_REG32(DC_WIN_V_INITIAL_DDA),
1393 DEBUGFS_REG32(DC_WIN_DDA_INC),
1394 DEBUGFS_REG32(DC_WIN_LINE_STRIDE),
1395 DEBUGFS_REG32(DC_WIN_BUF_STRIDE),
1396 DEBUGFS_REG32(DC_WIN_UV_BUF_STRIDE),
1397 DEBUGFS_REG32(DC_WIN_BUFFER_ADDR_MODE),
1398 DEBUGFS_REG32(DC_WIN_DV_CONTROL),
1399 DEBUGFS_REG32(DC_WIN_BLEND_NOKEY),
1400 DEBUGFS_REG32(DC_WIN_BLEND_1WIN),
1401 DEBUGFS_REG32(DC_WIN_BLEND_2WIN_X),
1402 DEBUGFS_REG32(DC_WIN_BLEND_2WIN_Y),
1403 DEBUGFS_REG32(DC_WIN_BLEND_3WIN_XY),
1404 DEBUGFS_REG32(DC_WIN_HP_FETCH_CONTROL),
1405 DEBUGFS_REG32(DC_WINBUF_START_ADDR),
1406 DEBUGFS_REG32(DC_WINBUF_START_ADDR_NS),
1407 DEBUGFS_REG32(DC_WINBUF_START_ADDR_U),
1408 DEBUGFS_REG32(DC_WINBUF_START_ADDR_U_NS),
1409 DEBUGFS_REG32(DC_WINBUF_START_ADDR_V),
1410 DEBUGFS_REG32(DC_WINBUF_START_ADDR_V_NS),
1411 DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET),
1412 DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET_NS),
1413 DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET),
1414 DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET_NS),
1415 DEBUGFS_REG32(DC_WINBUF_UFLOW_STATUS),
1416 DEBUGFS_REG32(DC_WINBUF_AD_UFLOW_STATUS),
1417 DEBUGFS_REG32(DC_WINBUF_BD_UFLOW_STATUS),
1418 DEBUGFS_REG32(DC_WINBUF_CD_UFLOW_STATUS),
1419};
1420
1421static int tegra_dc_show_regs(struct seq_file *s, void *data)
1422{
1423 struct drm_info_node *node = s->private;
1424 struct tegra_dc *dc = node->info_ent->data;
1425 unsigned int i;
1426 int err = 0;
1427
1428 drm_modeset_lock(&dc->base.mutex, NULL);
1429
1430 if (!dc->base.state->active) {
1431 err = -EBUSY;
1432 goto unlock;
1433 }
1434
1435 for (i = 0; i < ARRAY_SIZE(tegra_dc_regs); i++) {
1436 unsigned int offset = tegra_dc_regs[i].offset;
1437
1438 seq_printf(s, "%-40s %#05x %08x\n", tegra_dc_regs[i].name,
1439 offset, tegra_dc_readl(dc, offset));
1440 }
1441
1442unlock:
1443 drm_modeset_unlock(&dc->base.mutex);
1444 return err;
1445}
1446
1447static int tegra_dc_show_crc(struct seq_file *s, void *data)
1448{
1449 struct drm_info_node *node = s->private;
1450 struct tegra_dc *dc = node->info_ent->data;
1451 int err = 0;
1452 u32 value;
1453
1454 drm_modeset_lock(&dc->base.mutex, NULL);
1455
1456 if (!dc->base.state->active) {
1457 err = -EBUSY;
1458 goto unlock;
1459 }
1460
1461 value = DC_COM_CRC_CONTROL_ACTIVE_DATA | DC_COM_CRC_CONTROL_ENABLE;
1462 tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL);
1463 tegra_dc_commit(dc);
1464
1465 drm_crtc_wait_one_vblank(&dc->base);
1466 drm_crtc_wait_one_vblank(&dc->base);
1467
1468 value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM);
1469 seq_printf(s, "%08x\n", value);
1470
1471 tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL);
1472
1473unlock:
1474 drm_modeset_unlock(&dc->base.mutex);
1475 return err;
1476}
1477
1478static int tegra_dc_show_stats(struct seq_file *s, void *data)
1479{
1480 struct drm_info_node *node = s->private;
1481 struct tegra_dc *dc = node->info_ent->data;
1482
1483 seq_printf(s, "frames: %lu\n", dc->stats.frames);
1484 seq_printf(s, "vblank: %lu\n", dc->stats.vblank);
1485 seq_printf(s, "underflow: %lu\n", dc->stats.underflow);
1486 seq_printf(s, "overflow: %lu\n", dc->stats.overflow);
1487
1488 return 0;
1489}
1490
1491static struct drm_info_list debugfs_files[] = {
1492 { "regs", tegra_dc_show_regs, 0, NULL },
1493 { "crc", tegra_dc_show_crc, 0, NULL },
1494 { "stats", tegra_dc_show_stats, 0, NULL },
1495};
1496
1497static int tegra_dc_late_register(struct drm_crtc *crtc)
1498{
1499 unsigned int i, count = ARRAY_SIZE(debugfs_files);
1500 struct drm_minor *minor = crtc->dev->primary;
1501 struct dentry *root;
1502 struct tegra_dc *dc = to_tegra_dc(crtc);
1503 int err;
1504
1505#ifdef CONFIG_DEBUG_FS
1506 root = crtc->debugfs_entry;
1507#else
1508 root = NULL;
1509#endif
1510
1511 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1512 GFP_KERNEL);
1513 if (!dc->debugfs_files)
1514 return -ENOMEM;
1515
1516 for (i = 0; i < count; i++)
1517 dc->debugfs_files[i].data = dc;
1518
1519 err = drm_debugfs_create_files(dc->debugfs_files, count, root, minor);
1520 if (err < 0)
1521 goto free;
1522
1523 return 0;
1524
1525free:
1526 kfree(dc->debugfs_files);
1527 dc->debugfs_files = NULL;
1528
1529 return err;
1530}
1531
1532static void tegra_dc_early_unregister(struct drm_crtc *crtc)
1533{
1534 unsigned int count = ARRAY_SIZE(debugfs_files);
1535 struct drm_minor *minor = crtc->dev->primary;
1536 struct tegra_dc *dc = to_tegra_dc(crtc);
1537
1538 drm_debugfs_remove_files(dc->debugfs_files, count, minor);
1539 kfree(dc->debugfs_files);
1540 dc->debugfs_files = NULL;
1541}
1542
1543static u32 tegra_dc_get_vblank_counter(struct drm_crtc *crtc)
1544{
1545 struct tegra_dc *dc = to_tegra_dc(crtc);
1546
1547 /* XXX vblank syncpoints don't work with nvdisplay yet */
1548 if (dc->syncpt && !dc->soc->has_nvdisplay)
1549 return host1x_syncpt_read(dc->syncpt);
1550
1551 /* fallback to software emulated VBLANK counter */
1552 return (u32)drm_crtc_vblank_count(&dc->base);
1553}
1554
1555static int tegra_dc_enable_vblank(struct drm_crtc *crtc)
1556{
1557 struct tegra_dc *dc = to_tegra_dc(crtc);
1558 u32 value;
1559
1560 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1561 value |= VBLANK_INT;
1562 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1563
1564 return 0;
1565}
1566
1567static void tegra_dc_disable_vblank(struct drm_crtc *crtc)
1568{
1569 struct tegra_dc *dc = to_tegra_dc(crtc);
1570 u32 value;
1571
1572 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1573 value &= ~VBLANK_INT;
1574 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1575}
1576
1577static const struct drm_crtc_funcs tegra_crtc_funcs = {
1578 .page_flip = drm_atomic_helper_page_flip,
1579 .set_config = drm_atomic_helper_set_config,
1580 .destroy = tegra_dc_destroy,
1581 .reset = tegra_crtc_reset,
1582 .atomic_duplicate_state = tegra_crtc_atomic_duplicate_state,
1583 .atomic_destroy_state = tegra_crtc_atomic_destroy_state,
1584 .late_register = tegra_dc_late_register,
1585 .early_unregister = tegra_dc_early_unregister,
1586 .get_vblank_counter = tegra_dc_get_vblank_counter,
1587 .enable_vblank = tegra_dc_enable_vblank,
1588 .disable_vblank = tegra_dc_disable_vblank,
1589};
1590
1591static int tegra_dc_set_timings(struct tegra_dc *dc,
1592 struct drm_display_mode *mode)
1593{
1594 unsigned int h_ref_to_sync = 1;
1595 unsigned int v_ref_to_sync = 1;
1596 unsigned long value;
1597
1598 if (!dc->soc->has_nvdisplay) {
1599 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1600
1601 value = (v_ref_to_sync << 16) | h_ref_to_sync;
1602 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
1603 }
1604
1605 value = ((mode->vsync_end - mode->vsync_start) << 16) |
1606 ((mode->hsync_end - mode->hsync_start) << 0);
1607 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
1608
1609 value = ((mode->vtotal - mode->vsync_end) << 16) |
1610 ((mode->htotal - mode->hsync_end) << 0);
1611 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
1612
1613 value = ((mode->vsync_start - mode->vdisplay) << 16) |
1614 ((mode->hsync_start - mode->hdisplay) << 0);
1615 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
1616
1617 value = (mode->vdisplay << 16) | mode->hdisplay;
1618 tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
1619
1620 return 0;
1621}
1622
1623/**
1624 * tegra_dc_state_setup_clock - check clock settings and store them in atomic
1625 * state
1626 * @dc: display controller
1627 * @crtc_state: CRTC atomic state
1628 * @clk: parent clock for display controller
1629 * @pclk: pixel clock
1630 * @div: shift clock divider
1631 *
1632 * Returns:
1633 * 0 on success or a negative error-code on failure.
1634 */
1635int tegra_dc_state_setup_clock(struct tegra_dc *dc,
1636 struct drm_crtc_state *crtc_state,
1637 struct clk *clk, unsigned long pclk,
1638 unsigned int div)
1639{
1640 struct tegra_dc_state *state = to_dc_state(crtc_state);
1641
1642 if (!clk_has_parent(dc->clk, clk))
1643 return -EINVAL;
1644
1645 state->clk = clk;
1646 state->pclk = pclk;
1647 state->div = div;
1648
1649 return 0;
1650}
1651
1652static void tegra_dc_commit_state(struct tegra_dc *dc,
1653 struct tegra_dc_state *state)
1654{
1655 u32 value;
1656 int err;
1657
1658 err = clk_set_parent(dc->clk, state->clk);
1659 if (err < 0)
1660 dev_err(dc->dev, "failed to set parent clock: %d\n", err);
1661
1662 /*
1663 * Outputs may not want to change the parent clock rate. This is only
1664 * relevant to Tegra20 where only a single display PLL is available.
1665 * Since that PLL would typically be used for HDMI, an internal LVDS
1666 * panel would need to be driven by some other clock such as PLL_P
1667 * which is shared with other peripherals. Changing the clock rate
1668 * should therefore be avoided.
1669 */
1670 if (state->pclk > 0) {
1671 err = clk_set_rate(state->clk, state->pclk);
1672 if (err < 0)
1673 dev_err(dc->dev,
1674 "failed to set clock rate to %lu Hz\n",
1675 state->pclk);
1676
1677 err = clk_set_rate(dc->clk, state->pclk);
1678 if (err < 0)
1679 dev_err(dc->dev, "failed to set clock %pC to %lu Hz: %d\n",
1680 dc->clk, state->pclk, err);
1681 }
1682
1683 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk),
1684 state->div);
1685 DRM_DEBUG_KMS("pclk: %lu\n", state->pclk);
1686
1687 if (!dc->soc->has_nvdisplay) {
1688 value = SHIFT_CLK_DIVIDER(state->div) | PIXEL_CLK_DIVIDER_PCD1;
1689 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
1690 }
1691}
1692
1693static void tegra_dc_stop(struct tegra_dc *dc)
1694{
1695 u32 value;
1696
1697 /* stop the display controller */
1698 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1699 value &= ~DISP_CTRL_MODE_MASK;
1700 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1701
1702 tegra_dc_commit(dc);
1703}
1704
1705static bool tegra_dc_idle(struct tegra_dc *dc)
1706{
1707 u32 value;
1708
1709 value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND);
1710
1711 return (value & DISP_CTRL_MODE_MASK) == 0;
1712}
1713
1714static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout)
1715{
1716 timeout = jiffies + msecs_to_jiffies(timeout);
1717
1718 while (time_before(jiffies, timeout)) {
1719 if (tegra_dc_idle(dc))
1720 return 0;
1721
1722 usleep_range(1000, 2000);
1723 }
1724
1725 dev_dbg(dc->dev, "timeout waiting for DC to become idle\n");
1726 return -ETIMEDOUT;
1727}
1728
1729static void tegra_crtc_atomic_disable(struct drm_crtc *crtc,
1730 struct drm_crtc_state *old_state)
1731{
1732 struct tegra_dc *dc = to_tegra_dc(crtc);
1733 u32 value;
1734
1735 if (!tegra_dc_idle(dc)) {
1736 tegra_dc_stop(dc);
1737
1738 /*
1739 * Ignore the return value, there isn't anything useful to do
1740 * in case this fails.
1741 */
1742 tegra_dc_wait_idle(dc, 100);
1743 }
1744
1745 /*
1746 * This should really be part of the RGB encoder driver, but clearing
1747 * these bits has the side-effect of stopping the display controller.
1748 * When that happens no VBLANK interrupts will be raised. At the same
1749 * time the encoder is disabled before the display controller, so the
1750 * above code is always going to timeout waiting for the controller
1751 * to go idle.
1752 *
1753 * Given the close coupling between the RGB encoder and the display
1754 * controller doing it here is still kind of okay. None of the other
1755 * encoder drivers require these bits to be cleared.
1756 *
1757 * XXX: Perhaps given that the display controller is switched off at
1758 * this point anyway maybe clearing these bits isn't even useful for
1759 * the RGB encoder?
1760 */
1761 if (dc->rgb) {
1762 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1763 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1764 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
1765 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1766 }
1767
1768 tegra_dc_stats_reset(&dc->stats);
1769 drm_crtc_vblank_off(crtc);
1770
1771 spin_lock_irq(&crtc->dev->event_lock);
1772
1773 if (crtc->state->event) {
1774 drm_crtc_send_vblank_event(crtc, crtc->state->event);
1775 crtc->state->event = NULL;
1776 }
1777
1778 spin_unlock_irq(&crtc->dev->event_lock);
1779
1780 pm_runtime_put_sync(dc->dev);
1781}
1782
1783static void tegra_crtc_atomic_enable(struct drm_crtc *crtc,
1784 struct drm_crtc_state *old_state)
1785{
1786 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1787 struct tegra_dc_state *state = to_dc_state(crtc->state);
1788 struct tegra_dc *dc = to_tegra_dc(crtc);
1789 u32 value;
1790
1791 pm_runtime_get_sync(dc->dev);
1792
1793 /* initialize display controller */
1794 if (dc->syncpt) {
1795 u32 syncpt = host1x_syncpt_id(dc->syncpt), enable;
1796
1797 if (dc->soc->has_nvdisplay)
1798 enable = 1 << 31;
1799 else
1800 enable = 1 << 8;
1801
1802 value = SYNCPT_CNTRL_NO_STALL;
1803 tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1804
1805 value = enable | syncpt;
1806 tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC);
1807 }
1808
1809 if (dc->soc->has_nvdisplay) {
1810 value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT |
1811 DSC_OBUF_UF_INT;
1812 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
1813
1814 value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT |
1815 DSC_OBUF_UF_INT | SD3_BUCKET_WALK_DONE_INT |
1816 HEAD_UF_INT | MSF_INT | REG_TMOUT_INT |
1817 REGION_CRC_INT | V_PULSE2_INT | V_PULSE3_INT |
1818 VBLANK_INT | FRAME_END_INT;
1819 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
1820
1821 value = SD3_BUCKET_WALK_DONE_INT | HEAD_UF_INT | VBLANK_INT |
1822 FRAME_END_INT;
1823 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
1824
1825 value = HEAD_UF_INT | REG_TMOUT_INT | FRAME_END_INT;
1826 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1827
1828 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
1829 } else {
1830 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1831 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1832 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
1833
1834 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1835 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1836 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
1837
1838 /* initialize timer */
1839 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
1840 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
1841 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
1842
1843 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
1844 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
1845 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1846
1847 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1848 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1849 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
1850
1851 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1852 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1853 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1854 }
1855
1856 if (dc->soc->supports_background_color)
1857 tegra_dc_writel(dc, 0, DC_DISP_BLEND_BACKGROUND_COLOR);
1858 else
1859 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
1860
1861 /* apply PLL and pixel clock changes */
1862 tegra_dc_commit_state(dc, state);
1863
1864 /* program display mode */
1865 tegra_dc_set_timings(dc, mode);
1866
1867 /* interlacing isn't supported yet, so disable it */
1868 if (dc->soc->supports_interlacing) {
1869 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);
1870 value &= ~INTERLACE_ENABLE;
1871 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);
1872 }
1873
1874 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1875 value &= ~DISP_CTRL_MODE_MASK;
1876 value |= DISP_CTRL_MODE_C_DISPLAY;
1877 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1878
1879 if (!dc->soc->has_nvdisplay) {
1880 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1881 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1882 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
1883 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1884 }
1885
1886 /* enable underflow reporting and display red for missing pixels */
1887 if (dc->soc->has_nvdisplay) {
1888 value = UNDERFLOW_MODE_RED | UNDERFLOW_REPORT_ENABLE;
1889 tegra_dc_writel(dc, value, DC_COM_RG_UNDERFLOW);
1890 }
1891
1892 tegra_dc_commit(dc);
1893
1894 drm_crtc_vblank_on(crtc);
1895}
1896
1897static void tegra_crtc_atomic_begin(struct drm_crtc *crtc,
1898 struct drm_crtc_state *old_crtc_state)
1899{
1900 unsigned long flags;
1901
1902 if (crtc->state->event) {
1903 spin_lock_irqsave(&crtc->dev->event_lock, flags);
1904
1905 if (drm_crtc_vblank_get(crtc) != 0)
1906 drm_crtc_send_vblank_event(crtc, crtc->state->event);
1907 else
1908 drm_crtc_arm_vblank_event(crtc, crtc->state->event);
1909
1910 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
1911
1912 crtc->state->event = NULL;
1913 }
1914}
1915
1916static void tegra_crtc_atomic_flush(struct drm_crtc *crtc,
1917 struct drm_crtc_state *old_crtc_state)
1918{
1919 struct tegra_dc_state *state = to_dc_state(crtc->state);
1920 struct tegra_dc *dc = to_tegra_dc(crtc);
1921 u32 value;
1922
1923 value = state->planes << 8 | GENERAL_UPDATE;
1924 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
1925 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1926
1927 value = state->planes | GENERAL_ACT_REQ;
1928 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
1929 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1930}
1931
1932static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
1933 .atomic_begin = tegra_crtc_atomic_begin,
1934 .atomic_flush = tegra_crtc_atomic_flush,
1935 .atomic_enable = tegra_crtc_atomic_enable,
1936 .atomic_disable = tegra_crtc_atomic_disable,
1937};
1938
1939static irqreturn_t tegra_dc_irq(int irq, void *data)
1940{
1941 struct tegra_dc *dc = data;
1942 unsigned long status;
1943
1944 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1945 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1946
1947 if (status & FRAME_END_INT) {
1948 /*
1949 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
1950 */
1951 dc->stats.frames++;
1952 }
1953
1954 if (status & VBLANK_INT) {
1955 /*
1956 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
1957 */
1958 drm_crtc_handle_vblank(&dc->base);
1959 dc->stats.vblank++;
1960 }
1961
1962 if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
1963 /*
1964 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
1965 */
1966 dc->stats.underflow++;
1967 }
1968
1969 if (status & (WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT)) {
1970 /*
1971 dev_dbg(dc->dev, "%s(): overflow\n", __func__);
1972 */
1973 dc->stats.overflow++;
1974 }
1975
1976 if (status & HEAD_UF_INT) {
1977 dev_dbg_ratelimited(dc->dev, "%s(): head underflow\n", __func__);
1978 dc->stats.underflow++;
1979 }
1980
1981 return IRQ_HANDLED;
1982}
1983
1984static bool tegra_dc_has_window_groups(struct tegra_dc *dc)
1985{
1986 unsigned int i;
1987
1988 if (!dc->soc->wgrps)
1989 return true;
1990
1991 for (i = 0; i < dc->soc->num_wgrps; i++) {
1992 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i];
1993
1994 if (wgrp->dc == dc->pipe && wgrp->num_windows > 0)
1995 return true;
1996 }
1997
1998 return false;
1999}
2000
2001static int tegra_dc_init(struct host1x_client *client)
2002{
2003 struct drm_device *drm = dev_get_drvdata(client->parent);
2004 unsigned long flags = HOST1X_SYNCPT_CLIENT_MANAGED;
2005 struct tegra_dc *dc = host1x_client_to_dc(client);
2006 struct tegra_drm *tegra = drm->dev_private;
2007 struct drm_plane *primary = NULL;
2008 struct drm_plane *cursor = NULL;
2009 int err;
2010
2011 /*
2012 * XXX do not register DCs with no window groups because we cannot
2013 * assign a primary plane to them, which in turn will cause KMS to
2014 * crash.
2015 */
2016 if (!tegra_dc_has_window_groups(dc))
2017 return 0;
2018
2019 dc->syncpt = host1x_syncpt_request(client, flags);
2020 if (!dc->syncpt)
2021 dev_warn(dc->dev, "failed to allocate syncpoint\n");
2022
2023 dc->group = host1x_client_iommu_attach(client, true);
2024 if (IS_ERR(dc->group)) {
2025 err = PTR_ERR(dc->group);
2026 dev_err(client->dev, "failed to attach to domain: %d\n", err);
2027 return err;
2028 }
2029
2030 if (dc->soc->wgrps)
2031 primary = tegra_dc_add_shared_planes(drm, dc);
2032 else
2033 primary = tegra_dc_add_planes(drm, dc);
2034
2035 if (IS_ERR(primary)) {
2036 err = PTR_ERR(primary);
2037 goto cleanup;
2038 }
2039
2040 if (dc->soc->supports_cursor) {
2041 cursor = tegra_dc_cursor_plane_create(drm, dc);
2042 if (IS_ERR(cursor)) {
2043 err = PTR_ERR(cursor);
2044 goto cleanup;
2045 }
2046 } else {
2047 /* dedicate one overlay to mouse cursor */
2048 cursor = tegra_dc_overlay_plane_create(drm, dc, 2, true);
2049 if (IS_ERR(cursor)) {
2050 err = PTR_ERR(cursor);
2051 goto cleanup;
2052 }
2053 }
2054
2055 err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor,
2056 &tegra_crtc_funcs, NULL);
2057 if (err < 0)
2058 goto cleanup;
2059
2060 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
2061
2062 /*
2063 * Keep track of the minimum pitch alignment across all display
2064 * controllers.
2065 */
2066 if (dc->soc->pitch_align > tegra->pitch_align)
2067 tegra->pitch_align = dc->soc->pitch_align;
2068
2069 err = tegra_dc_rgb_init(drm, dc);
2070 if (err < 0 && err != -ENODEV) {
2071 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
2072 goto cleanup;
2073 }
2074
2075 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
2076 dev_name(dc->dev), dc);
2077 if (err < 0) {
2078 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
2079 err);
2080 goto cleanup;
2081 }
2082
2083 return 0;
2084
2085cleanup:
2086 if (!IS_ERR_OR_NULL(cursor))
2087 drm_plane_cleanup(cursor);
2088
2089 if (!IS_ERR(primary))
2090 drm_plane_cleanup(primary);
2091
2092 host1x_client_iommu_detach(client, dc->group);
2093 host1x_syncpt_free(dc->syncpt);
2094
2095 return err;
2096}
2097
2098static int tegra_dc_exit(struct host1x_client *client)
2099{
2100 struct tegra_dc *dc = host1x_client_to_dc(client);
2101 int err;
2102
2103 if (!tegra_dc_has_window_groups(dc))
2104 return 0;
2105
2106 devm_free_irq(dc->dev, dc->irq, dc);
2107
2108 err = tegra_dc_rgb_exit(dc);
2109 if (err) {
2110 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
2111 return err;
2112 }
2113
2114 host1x_client_iommu_detach(client, dc->group);
2115 host1x_syncpt_free(dc->syncpt);
2116
2117 return 0;
2118}
2119
2120static const struct host1x_client_ops dc_client_ops = {
2121 .init = tegra_dc_init,
2122 .exit = tegra_dc_exit,
2123};
2124
2125static const struct tegra_dc_soc_info tegra20_dc_soc_info = {
2126 .supports_background_color = false,
2127 .supports_interlacing = false,
2128 .supports_cursor = false,
2129 .supports_block_linear = false,
2130 .has_legacy_blending = true,
2131 .pitch_align = 8,
2132 .has_powergate = false,
2133 .coupled_pm = true,
2134 .has_nvdisplay = false,
2135 .num_primary_formats = ARRAY_SIZE(tegra20_primary_formats),
2136 .primary_formats = tegra20_primary_formats,
2137 .num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats),
2138 .overlay_formats = tegra20_overlay_formats,
2139 .modifiers = tegra20_modifiers,
2140 .has_win_a_without_filters = true,
2141 .has_win_c_without_vert_filter = true,
2142};
2143
2144static const struct tegra_dc_soc_info tegra30_dc_soc_info = {
2145 .supports_background_color = false,
2146 .supports_interlacing = false,
2147 .supports_cursor = false,
2148 .supports_block_linear = false,
2149 .has_legacy_blending = true,
2150 .pitch_align = 8,
2151 .has_powergate = false,
2152 .coupled_pm = false,
2153 .has_nvdisplay = false,
2154 .num_primary_formats = ARRAY_SIZE(tegra20_primary_formats),
2155 .primary_formats = tegra20_primary_formats,
2156 .num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats),
2157 .overlay_formats = tegra20_overlay_formats,
2158 .modifiers = tegra20_modifiers,
2159 .has_win_a_without_filters = false,
2160 .has_win_c_without_vert_filter = false,
2161};
2162
2163static const struct tegra_dc_soc_info tegra114_dc_soc_info = {
2164 .supports_background_color = false,
2165 .supports_interlacing = false,
2166 .supports_cursor = false,
2167 .supports_block_linear = false,
2168 .has_legacy_blending = true,
2169 .pitch_align = 64,
2170 .has_powergate = true,
2171 .coupled_pm = false,
2172 .has_nvdisplay = false,
2173 .num_primary_formats = ARRAY_SIZE(tegra114_primary_formats),
2174 .primary_formats = tegra114_primary_formats,
2175 .num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats),
2176 .overlay_formats = tegra114_overlay_formats,
2177 .modifiers = tegra20_modifiers,
2178 .has_win_a_without_filters = false,
2179 .has_win_c_without_vert_filter = false,
2180};
2181
2182static const struct tegra_dc_soc_info tegra124_dc_soc_info = {
2183 .supports_background_color = true,
2184 .supports_interlacing = true,
2185 .supports_cursor = true,
2186 .supports_block_linear = true,
2187 .has_legacy_blending = false,
2188 .pitch_align = 64,
2189 .has_powergate = true,
2190 .coupled_pm = false,
2191 .has_nvdisplay = false,
2192 .num_primary_formats = ARRAY_SIZE(tegra124_primary_formats),
2193 .primary_formats = tegra124_primary_formats,
2194 .num_overlay_formats = ARRAY_SIZE(tegra124_overlay_formats),
2195 .overlay_formats = tegra124_overlay_formats,
2196 .modifiers = tegra124_modifiers,
2197 .has_win_a_without_filters = false,
2198 .has_win_c_without_vert_filter = false,
2199};
2200
2201static const struct tegra_dc_soc_info tegra210_dc_soc_info = {
2202 .supports_background_color = true,
2203 .supports_interlacing = true,
2204 .supports_cursor = true,
2205 .supports_block_linear = true,
2206 .has_legacy_blending = false,
2207 .pitch_align = 64,
2208 .has_powergate = true,
2209 .coupled_pm = false,
2210 .has_nvdisplay = false,
2211 .num_primary_formats = ARRAY_SIZE(tegra114_primary_formats),
2212 .primary_formats = tegra114_primary_formats,
2213 .num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats),
2214 .overlay_formats = tegra114_overlay_formats,
2215 .modifiers = tegra124_modifiers,
2216 .has_win_a_without_filters = false,
2217 .has_win_c_without_vert_filter = false,
2218};
2219
2220static const struct tegra_windowgroup_soc tegra186_dc_wgrps[] = {
2221 {
2222 .index = 0,
2223 .dc = 0,
2224 .windows = (const unsigned int[]) { 0 },
2225 .num_windows = 1,
2226 }, {
2227 .index = 1,
2228 .dc = 1,
2229 .windows = (const unsigned int[]) { 1 },
2230 .num_windows = 1,
2231 }, {
2232 .index = 2,
2233 .dc = 1,
2234 .windows = (const unsigned int[]) { 2 },
2235 .num_windows = 1,
2236 }, {
2237 .index = 3,
2238 .dc = 2,
2239 .windows = (const unsigned int[]) { 3 },
2240 .num_windows = 1,
2241 }, {
2242 .index = 4,
2243 .dc = 2,
2244 .windows = (const unsigned int[]) { 4 },
2245 .num_windows = 1,
2246 }, {
2247 .index = 5,
2248 .dc = 2,
2249 .windows = (const unsigned int[]) { 5 },
2250 .num_windows = 1,
2251 },
2252};
2253
2254static const struct tegra_dc_soc_info tegra186_dc_soc_info = {
2255 .supports_background_color = true,
2256 .supports_interlacing = true,
2257 .supports_cursor = true,
2258 .supports_block_linear = true,
2259 .has_legacy_blending = false,
2260 .pitch_align = 64,
2261 .has_powergate = false,
2262 .coupled_pm = false,
2263 .has_nvdisplay = true,
2264 .wgrps = tegra186_dc_wgrps,
2265 .num_wgrps = ARRAY_SIZE(tegra186_dc_wgrps),
2266};
2267
2268static const struct tegra_windowgroup_soc tegra194_dc_wgrps[] = {
2269 {
2270 .index = 0,
2271 .dc = 0,
2272 .windows = (const unsigned int[]) { 0 },
2273 .num_windows = 1,
2274 }, {
2275 .index = 1,
2276 .dc = 1,
2277 .windows = (const unsigned int[]) { 1 },
2278 .num_windows = 1,
2279 }, {
2280 .index = 2,
2281 .dc = 1,
2282 .windows = (const unsigned int[]) { 2 },
2283 .num_windows = 1,
2284 }, {
2285 .index = 3,
2286 .dc = 2,
2287 .windows = (const unsigned int[]) { 3 },
2288 .num_windows = 1,
2289 }, {
2290 .index = 4,
2291 .dc = 2,
2292 .windows = (const unsigned int[]) { 4 },
2293 .num_windows = 1,
2294 }, {
2295 .index = 5,
2296 .dc = 2,
2297 .windows = (const unsigned int[]) { 5 },
2298 .num_windows = 1,
2299 },
2300};
2301
2302static const struct tegra_dc_soc_info tegra194_dc_soc_info = {
2303 .supports_background_color = true,
2304 .supports_interlacing = true,
2305 .supports_cursor = true,
2306 .supports_block_linear = true,
2307 .has_legacy_blending = false,
2308 .pitch_align = 64,
2309 .has_powergate = false,
2310 .coupled_pm = false,
2311 .has_nvdisplay = true,
2312 .wgrps = tegra194_dc_wgrps,
2313 .num_wgrps = ARRAY_SIZE(tegra194_dc_wgrps),
2314};
2315
2316static const struct of_device_id tegra_dc_of_match[] = {
2317 {
2318 .compatible = "nvidia,tegra194-dc",
2319 .data = &tegra194_dc_soc_info,
2320 }, {
2321 .compatible = "nvidia,tegra186-dc",
2322 .data = &tegra186_dc_soc_info,
2323 }, {
2324 .compatible = "nvidia,tegra210-dc",
2325 .data = &tegra210_dc_soc_info,
2326 }, {
2327 .compatible = "nvidia,tegra124-dc",
2328 .data = &tegra124_dc_soc_info,
2329 }, {
2330 .compatible = "nvidia,tegra114-dc",
2331 .data = &tegra114_dc_soc_info,
2332 }, {
2333 .compatible = "nvidia,tegra30-dc",
2334 .data = &tegra30_dc_soc_info,
2335 }, {
2336 .compatible = "nvidia,tegra20-dc",
2337 .data = &tegra20_dc_soc_info,
2338 }, {
2339 /* sentinel */
2340 }
2341};
2342MODULE_DEVICE_TABLE(of, tegra_dc_of_match);
2343
2344static int tegra_dc_parse_dt(struct tegra_dc *dc)
2345{
2346 struct device_node *np;
2347 u32 value = 0;
2348 int err;
2349
2350 err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value);
2351 if (err < 0) {
2352 dev_err(dc->dev, "missing \"nvidia,head\" property\n");
2353
2354 /*
2355 * If the nvidia,head property isn't present, try to find the
2356 * correct head number by looking up the position of this
2357 * display controller's node within the device tree. Assuming
2358 * that the nodes are ordered properly in the DTS file and
2359 * that the translation into a flattened device tree blob
2360 * preserves that ordering this will actually yield the right
2361 * head number.
2362 *
2363 * If those assumptions don't hold, this will still work for
2364 * cases where only a single display controller is used.
2365 */
2366 for_each_matching_node(np, tegra_dc_of_match) {
2367 if (np == dc->dev->of_node) {
2368 of_node_put(np);
2369 break;
2370 }
2371
2372 value++;
2373 }
2374 }
2375
2376 dc->pipe = value;
2377
2378 return 0;
2379}
2380
2381static int tegra_dc_match_by_pipe(struct device *dev, const void *data)
2382{
2383 struct tegra_dc *dc = dev_get_drvdata(dev);
2384 unsigned int pipe = (unsigned long)(void *)data;
2385
2386 return dc->pipe == pipe;
2387}
2388
2389static int tegra_dc_couple(struct tegra_dc *dc)
2390{
2391 /*
2392 * On Tegra20, DC1 requires DC0 to be taken out of reset in order to
2393 * be enabled, otherwise CPU hangs on writing to CMD_DISPLAY_COMMAND /
2394 * POWER_CONTROL registers during CRTC enabling.
2395 */
2396 if (dc->soc->coupled_pm && dc->pipe == 1) {
2397 u32 flags = DL_FLAG_PM_RUNTIME | DL_FLAG_AUTOREMOVE_CONSUMER;
2398 struct device_link *link;
2399 struct device *partner;
2400
2401 partner = driver_find_device(dc->dev->driver, NULL, NULL,
2402 tegra_dc_match_by_pipe);
2403 if (!partner)
2404 return -EPROBE_DEFER;
2405
2406 link = device_link_add(dc->dev, partner, flags);
2407 if (!link) {
2408 dev_err(dc->dev, "failed to link controllers\n");
2409 return -EINVAL;
2410 }
2411
2412 dev_dbg(dc->dev, "coupled to %s\n", dev_name(partner));
2413 }
2414
2415 return 0;
2416}
2417
2418static int tegra_dc_probe(struct platform_device *pdev)
2419{
2420 struct resource *regs;
2421 struct tegra_dc *dc;
2422 int err;
2423
2424 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
2425 if (!dc)
2426 return -ENOMEM;
2427
2428 dc->soc = of_device_get_match_data(&pdev->dev);
2429
2430 INIT_LIST_HEAD(&dc->list);
2431 dc->dev = &pdev->dev;
2432
2433 err = tegra_dc_parse_dt(dc);
2434 if (err < 0)
2435 return err;
2436
2437 err = tegra_dc_couple(dc);
2438 if (err < 0)
2439 return err;
2440
2441 dc->clk = devm_clk_get(&pdev->dev, NULL);
2442 if (IS_ERR(dc->clk)) {
2443 dev_err(&pdev->dev, "failed to get clock\n");
2444 return PTR_ERR(dc->clk);
2445 }
2446
2447 dc->rst = devm_reset_control_get(&pdev->dev, "dc");
2448 if (IS_ERR(dc->rst)) {
2449 dev_err(&pdev->dev, "failed to get reset\n");
2450 return PTR_ERR(dc->rst);
2451 }
2452
2453 /* assert reset and disable clock */
2454 err = clk_prepare_enable(dc->clk);
2455 if (err < 0)
2456 return err;
2457
2458 usleep_range(2000, 4000);
2459
2460 err = reset_control_assert(dc->rst);
2461 if (err < 0)
2462 return err;
2463
2464 usleep_range(2000, 4000);
2465
2466 clk_disable_unprepare(dc->clk);
2467
2468 if (dc->soc->has_powergate) {
2469 if (dc->pipe == 0)
2470 dc->powergate = TEGRA_POWERGATE_DIS;
2471 else
2472 dc->powergate = TEGRA_POWERGATE_DISB;
2473
2474 tegra_powergate_power_off(dc->powergate);
2475 }
2476
2477 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2478 dc->regs = devm_ioremap_resource(&pdev->dev, regs);
2479 if (IS_ERR(dc->regs))
2480 return PTR_ERR(dc->regs);
2481
2482 dc->irq = platform_get_irq(pdev, 0);
2483 if (dc->irq < 0) {
2484 dev_err(&pdev->dev, "failed to get IRQ\n");
2485 return -ENXIO;
2486 }
2487
2488 err = tegra_dc_rgb_probe(dc);
2489 if (err < 0 && err != -ENODEV) {
2490 dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err);
2491 return err;
2492 }
2493
2494 platform_set_drvdata(pdev, dc);
2495 pm_runtime_enable(&pdev->dev);
2496
2497 INIT_LIST_HEAD(&dc->client.list);
2498 dc->client.ops = &dc_client_ops;
2499 dc->client.dev = &pdev->dev;
2500
2501 err = host1x_client_register(&dc->client);
2502 if (err < 0) {
2503 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
2504 err);
2505 return err;
2506 }
2507
2508 return 0;
2509}
2510
2511static int tegra_dc_remove(struct platform_device *pdev)
2512{
2513 struct tegra_dc *dc = platform_get_drvdata(pdev);
2514 int err;
2515
2516 err = host1x_client_unregister(&dc->client);
2517 if (err < 0) {
2518 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
2519 err);
2520 return err;
2521 }
2522
2523 err = tegra_dc_rgb_remove(dc);
2524 if (err < 0) {
2525 dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err);
2526 return err;
2527 }
2528
2529 pm_runtime_disable(&pdev->dev);
2530
2531 return 0;
2532}
2533
2534#ifdef CONFIG_PM
2535static int tegra_dc_suspend(struct device *dev)
2536{
2537 struct tegra_dc *dc = dev_get_drvdata(dev);
2538 int err;
2539
2540 err = reset_control_assert(dc->rst);
2541 if (err < 0) {
2542 dev_err(dev, "failed to assert reset: %d\n", err);
2543 return err;
2544 }
2545
2546 if (dc->soc->has_powergate)
2547 tegra_powergate_power_off(dc->powergate);
2548
2549 clk_disable_unprepare(dc->clk);
2550
2551 return 0;
2552}
2553
2554static int tegra_dc_resume(struct device *dev)
2555{
2556 struct tegra_dc *dc = dev_get_drvdata(dev);
2557 int err;
2558
2559 if (dc->soc->has_powergate) {
2560 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk,
2561 dc->rst);
2562 if (err < 0) {
2563 dev_err(dev, "failed to power partition: %d\n", err);
2564 return err;
2565 }
2566 } else {
2567 err = clk_prepare_enable(dc->clk);
2568 if (err < 0) {
2569 dev_err(dev, "failed to enable clock: %d\n", err);
2570 return err;
2571 }
2572
2573 err = reset_control_deassert(dc->rst);
2574 if (err < 0) {
2575 dev_err(dev, "failed to deassert reset: %d\n", err);
2576 return err;
2577 }
2578 }
2579
2580 return 0;
2581}
2582#endif
2583
2584static const struct dev_pm_ops tegra_dc_pm_ops = {
2585 SET_RUNTIME_PM_OPS(tegra_dc_suspend, tegra_dc_resume, NULL)
2586};
2587
2588struct platform_driver tegra_dc_driver = {
2589 .driver = {
2590 .name = "tegra-dc",
2591 .of_match_table = tegra_dc_of_match,
2592 .pm = &tegra_dc_pm_ops,
2593 },
2594 .probe = tegra_dc_probe,
2595 .remove = tegra_dc_remove,
2596};
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