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1/*
2 w83627hf.c - Part of lm_sensors, Linux kernel modules for hardware
3 monitoring
4 Copyright (c) 1998 - 2003 Frodo Looijaard <frodol@dds.nl>,
5 Philip Edelbrock <phil@netroedge.com>,
6 and Mark Studebaker <mdsxyz123@yahoo.com>
7 Ported to 2.6 by Bernhard C. Schrenk <clemy@clemy.org>
8 Copyright (c) 2007 Jean Delvare <khali@linux-fr.org>
9
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2 of the License, or
13 (at your option) any later version.
14
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23*/
24
25/*
26 Supports following chips:
27
28 Chip #vin #fanin #pwm #temp wchipid vendid i2c ISA
29 w83627hf 9 3 2 3 0x20 0x5ca3 no yes(LPC)
30 w83627thf 7 3 3 3 0x90 0x5ca3 no yes(LPC)
31 w83637hf 7 3 3 3 0x80 0x5ca3 no yes(LPC)
32 w83687thf 7 3 3 3 0x90 0x5ca3 no yes(LPC)
33 w83697hf 8 2 2 2 0x60 0x5ca3 no yes(LPC)
34
35 For other winbond chips, and for i2c support in the above chips,
36 use w83781d.c.
37
38 Note: automatic ("cruise") fan control for 697, 637 & 627thf not
39 supported yet.
40*/
41
42#include <linux/module.h>
43#include <linux/init.h>
44#include <linux/slab.h>
45#include <linux/jiffies.h>
46#include <linux/platform_device.h>
47#include <linux/hwmon.h>
48#include <linux/hwmon-vid.h>
49#include <linux/err.h>
50#include <linux/mutex.h>
51#include <linux/ioport.h>
52#include <asm/io.h>
53#include "lm75.h"
54
55static struct platform_device *pdev;
56
57#define DRVNAME "w83627hf"
58enum chips { w83627hf, w83627thf, w83697hf, w83637hf, w83687thf };
59
60static u16 force_addr;
61module_param(force_addr, ushort, 0);
62MODULE_PARM_DESC(force_addr,
63 "Initialize the base address of the sensors");
64static u8 force_i2c = 0x1f;
65module_param(force_i2c, byte, 0);
66MODULE_PARM_DESC(force_i2c,
67 "Initialize the i2c address of the sensors");
68
69static int reset;
70module_param(reset, bool, 0);
71MODULE_PARM_DESC(reset, "Set to one to reset chip on load");
72
73static int init = 1;
74module_param(init, bool, 0);
75MODULE_PARM_DESC(init, "Set to zero to bypass chip initialization");
76
77/* modified from kernel/include/traps.c */
78static int REG; /* The register to read/write */
79#define DEV 0x07 /* Register: Logical device select */
80static int VAL; /* The value to read/write */
81
82/* logical device numbers for superio_select (below) */
83#define W83627HF_LD_FDC 0x00
84#define W83627HF_LD_PRT 0x01
85#define W83627HF_LD_UART1 0x02
86#define W83627HF_LD_UART2 0x03
87#define W83627HF_LD_KBC 0x05
88#define W83627HF_LD_CIR 0x06 /* w83627hf only */
89#define W83627HF_LD_GAME 0x07
90#define W83627HF_LD_MIDI 0x07
91#define W83627HF_LD_GPIO1 0x07
92#define W83627HF_LD_GPIO5 0x07 /* w83627thf only */
93#define W83627HF_LD_GPIO2 0x08
94#define W83627HF_LD_GPIO3 0x09
95#define W83627HF_LD_GPIO4 0x09 /* w83627thf only */
96#define W83627HF_LD_ACPI 0x0a
97#define W83627HF_LD_HWM 0x0b
98
99#define DEVID 0x20 /* Register: Device ID */
100
101#define W83627THF_GPIO5_EN 0x30 /* w83627thf only */
102#define W83627THF_GPIO5_IOSR 0xf3 /* w83627thf only */
103#define W83627THF_GPIO5_DR 0xf4 /* w83627thf only */
104
105#define W83687THF_VID_EN 0x29 /* w83687thf only */
106#define W83687THF_VID_CFG 0xF0 /* w83687thf only */
107#define W83687THF_VID_DATA 0xF1 /* w83687thf only */
108
109static inline void
110superio_outb(int reg, int val)
111{
112 outb(reg, REG);
113 outb(val, VAL);
114}
115
116static inline int
117superio_inb(int reg)
118{
119 outb(reg, REG);
120 return inb(VAL);
121}
122
123static inline void
124superio_select(int ld)
125{
126 outb(DEV, REG);
127 outb(ld, VAL);
128}
129
130static inline void
131superio_enter(void)
132{
133 outb(0x87, REG);
134 outb(0x87, REG);
135}
136
137static inline void
138superio_exit(void)
139{
140 outb(0xAA, REG);
141}
142
143#define W627_DEVID 0x52
144#define W627THF_DEVID 0x82
145#define W697_DEVID 0x60
146#define W637_DEVID 0x70
147#define W687THF_DEVID 0x85
148#define WINB_ACT_REG 0x30
149#define WINB_BASE_REG 0x60
150/* Constants specified below */
151
152/* Alignment of the base address */
153#define WINB_ALIGNMENT ~7
154
155/* Offset & size of I/O region we are interested in */
156#define WINB_REGION_OFFSET 5
157#define WINB_REGION_SIZE 2
158
159/* Where are the sensors address/data registers relative to the region offset */
160#define W83781D_ADDR_REG_OFFSET 0
161#define W83781D_DATA_REG_OFFSET 1
162
163/* The W83781D registers */
164/* The W83782D registers for nr=7,8 are in bank 5 */
165#define W83781D_REG_IN_MAX(nr) ((nr < 7) ? (0x2b + (nr) * 2) : \
166 (0x554 + (((nr) - 7) * 2)))
167#define W83781D_REG_IN_MIN(nr) ((nr < 7) ? (0x2c + (nr) * 2) : \
168 (0x555 + (((nr) - 7) * 2)))
169#define W83781D_REG_IN(nr) ((nr < 7) ? (0x20 + (nr)) : \
170 (0x550 + (nr) - 7))
171
172#define W83781D_REG_FAN_MIN(nr) (0x3a + (nr))
173#define W83781D_REG_FAN(nr) (0x27 + (nr))
174
175#define W83781D_REG_TEMP2_CONFIG 0x152
176#define W83781D_REG_TEMP3_CONFIG 0x252
177#define W83781D_REG_TEMP(nr) ((nr == 3) ? (0x0250) : \
178 ((nr == 2) ? (0x0150) : \
179 (0x27)))
180#define W83781D_REG_TEMP_HYST(nr) ((nr == 3) ? (0x253) : \
181 ((nr == 2) ? (0x153) : \
182 (0x3A)))
183#define W83781D_REG_TEMP_OVER(nr) ((nr == 3) ? (0x255) : \
184 ((nr == 2) ? (0x155) : \
185 (0x39)))
186
187#define W83781D_REG_BANK 0x4E
188
189#define W83781D_REG_CONFIG 0x40
190#define W83781D_REG_ALARM1 0x459
191#define W83781D_REG_ALARM2 0x45A
192#define W83781D_REG_ALARM3 0x45B
193
194#define W83781D_REG_BEEP_CONFIG 0x4D
195#define W83781D_REG_BEEP_INTS1 0x56
196#define W83781D_REG_BEEP_INTS2 0x57
197#define W83781D_REG_BEEP_INTS3 0x453
198
199#define W83781D_REG_VID_FANDIV 0x47
200
201#define W83781D_REG_CHIPID 0x49
202#define W83781D_REG_WCHIPID 0x58
203#define W83781D_REG_CHIPMAN 0x4F
204#define W83781D_REG_PIN 0x4B
205
206#define W83781D_REG_VBAT 0x5D
207
208#define W83627HF_REG_PWM1 0x5A
209#define W83627HF_REG_PWM2 0x5B
210
211#define W83627THF_REG_PWM1 0x01 /* 697HF/637HF/687THF too */
212#define W83627THF_REG_PWM2 0x03 /* 697HF/637HF/687THF too */
213#define W83627THF_REG_PWM3 0x11 /* 637HF/687THF too */
214
215#define W83627THF_REG_VRM_OVT_CFG 0x18 /* 637HF/687THF too */
216
217static const u8 regpwm_627hf[] = { W83627HF_REG_PWM1, W83627HF_REG_PWM2 };
218static const u8 regpwm[] = { W83627THF_REG_PWM1, W83627THF_REG_PWM2,
219 W83627THF_REG_PWM3 };
220#define W836X7HF_REG_PWM(type, nr) (((type) == w83627hf) ? \
221 regpwm_627hf[(nr) - 1] : regpwm[(nr) - 1])
222
223#define W83781D_REG_I2C_ADDR 0x48
224#define W83781D_REG_I2C_SUBADDR 0x4A
225
226/* Sensor selection */
227#define W83781D_REG_SCFG1 0x5D
228static const u8 BIT_SCFG1[] = { 0x02, 0x04, 0x08 };
229#define W83781D_REG_SCFG2 0x59
230static const u8 BIT_SCFG2[] = { 0x10, 0x20, 0x40 };
231#define W83781D_DEFAULT_BETA 3435
232
233/* Conversions. Limit checking is only done on the TO_REG
234 variants. Note that you should be a bit careful with which arguments
235 these macros are called: arguments may be evaluated more than once.
236 Fixing this is just not worth it. */
237#define IN_TO_REG(val) (SENSORS_LIMIT((((val) + 8)/16),0,255))
238#define IN_FROM_REG(val) ((val) * 16)
239
240static inline u8 FAN_TO_REG(long rpm, int div)
241{
242 if (rpm == 0)
243 return 255;
244 rpm = SENSORS_LIMIT(rpm, 1, 1000000);
245 return SENSORS_LIMIT((1350000 + rpm * div / 2) / (rpm * div), 1,
246 254);
247}
248
249#define TEMP_MIN (-128000)
250#define TEMP_MAX ( 127000)
251
252/* TEMP: 0.001C/bit (-128C to +127C)
253 REG: 1C/bit, two's complement */
254static u8 TEMP_TO_REG(int temp)
255{
256 int ntemp = SENSORS_LIMIT(temp, TEMP_MIN, TEMP_MAX);
257 ntemp += (ntemp<0 ? -500 : 500);
258 return (u8)(ntemp / 1000);
259}
260
261static int TEMP_FROM_REG(u8 reg)
262{
263 return (s8)reg * 1000;
264}
265
266#define FAN_FROM_REG(val,div) ((val)==0?-1:(val)==255?0:1350000/((val)*(div)))
267
268#define PWM_TO_REG(val) (SENSORS_LIMIT((val),0,255))
269
270#define BEEP_MASK_FROM_REG(val) (val)
271#define BEEP_MASK_TO_REG(val) ((val) & 0xffffff)
272#define BEEP_ENABLE_TO_REG(val) ((val)?1:0)
273#define BEEP_ENABLE_FROM_REG(val) ((val)?1:0)
274
275#define DIV_FROM_REG(val) (1 << (val))
276
277static inline u8 DIV_TO_REG(long val)
278{
279 int i;
280 val = SENSORS_LIMIT(val, 1, 128) >> 1;
281 for (i = 0; i < 7; i++) {
282 if (val == 0)
283 break;
284 val >>= 1;
285 }
286 return ((u8) i);
287}
288
289/* For each registered chip, we need to keep some data in memory.
290 The structure is dynamically allocated. */
291struct w83627hf_data {
292 unsigned short addr;
293 const char *name;
294 struct class_device *class_dev;
295 struct mutex lock;
296 enum chips type;
297
298 struct mutex update_lock;
299 char valid; /* !=0 if following fields are valid */
300 unsigned long last_updated; /* In jiffies */
301
302 u8 in[9]; /* Register value */
303 u8 in_max[9]; /* Register value */
304 u8 in_min[9]; /* Register value */
305 u8 fan[3]; /* Register value */
306 u8 fan_min[3]; /* Register value */
307 u8 temp;
308 u8 temp_max; /* Register value */
309 u8 temp_max_hyst; /* Register value */
310 u16 temp_add[2]; /* Register value */
311 u16 temp_max_add[2]; /* Register value */
312 u16 temp_max_hyst_add[2]; /* Register value */
313 u8 fan_div[3]; /* Register encoding, shifted right */
314 u8 vid; /* Register encoding, combined */
315 u32 alarms; /* Register encoding, combined */
316 u32 beep_mask; /* Register encoding, combined */
317 u8 beep_enable; /* Boolean */
318 u8 pwm[3]; /* Register value */
319 u16 sens[3]; /* 782D/783S only.
320 1 = pentium diode; 2 = 3904 diode;
321 3000-5000 = thermistor beta.
322 Default = 3435.
323 Other Betas unimplemented */
324 u8 vrm;
325 u8 vrm_ovt; /* Register value, 627THF/637HF/687THF only */
326};
327
328struct w83627hf_sio_data {
329 enum chips type;
330};
331
332
333static int w83627hf_probe(struct platform_device *pdev);
334static int w83627hf_remove(struct platform_device *pdev);
335
336static int w83627hf_read_value(struct w83627hf_data *data, u16 reg);
337static int w83627hf_write_value(struct w83627hf_data *data, u16 reg, u16 value);
338static struct w83627hf_data *w83627hf_update_device(struct device *dev);
339static void w83627hf_init_device(struct platform_device *pdev);
340
341static struct platform_driver w83627hf_driver = {
342 .driver = {
343 .owner = THIS_MODULE,
344 .name = DRVNAME,
345 },
346 .probe = w83627hf_probe,
347 .remove = __devexit_p(w83627hf_remove),
348};
349
350/* following are the sysfs callback functions */
351#define show_in_reg(reg) \
352static ssize_t show_##reg (struct device *dev, char *buf, int nr) \
353{ \
354 struct w83627hf_data *data = w83627hf_update_device(dev); \
355 return sprintf(buf,"%ld\n", (long)IN_FROM_REG(data->reg[nr])); \
356}
357show_in_reg(in)
358show_in_reg(in_min)
359show_in_reg(in_max)
360
361#define store_in_reg(REG, reg) \
362static ssize_t \
363store_in_##reg (struct device *dev, const char *buf, size_t count, int nr) \
364{ \
365 struct w83627hf_data *data = dev_get_drvdata(dev); \
366 u32 val; \
367 \
368 val = simple_strtoul(buf, NULL, 10); \
369 \
370 mutex_lock(&data->update_lock); \
371 data->in_##reg[nr] = IN_TO_REG(val); \
372 w83627hf_write_value(data, W83781D_REG_IN_##REG(nr), \
373 data->in_##reg[nr]); \
374 \
375 mutex_unlock(&data->update_lock); \
376 return count; \
377}
378store_in_reg(MIN, min)
379store_in_reg(MAX, max)
380
381#define sysfs_in_offset(offset) \
382static ssize_t \
383show_regs_in_##offset (struct device *dev, struct device_attribute *attr, char *buf) \
384{ \
385 return show_in(dev, buf, offset); \
386} \
387static DEVICE_ATTR(in##offset##_input, S_IRUGO, show_regs_in_##offset, NULL);
388
389#define sysfs_in_reg_offset(reg, offset) \
390static ssize_t show_regs_in_##reg##offset (struct device *dev, struct device_attribute *attr, char *buf) \
391{ \
392 return show_in_##reg (dev, buf, offset); \
393} \
394static ssize_t \
395store_regs_in_##reg##offset (struct device *dev, struct device_attribute *attr, \
396 const char *buf, size_t count) \
397{ \
398 return store_in_##reg (dev, buf, count, offset); \
399} \
400static DEVICE_ATTR(in##offset##_##reg, S_IRUGO| S_IWUSR, \
401 show_regs_in_##reg##offset, store_regs_in_##reg##offset);
402
403#define sysfs_in_offsets(offset) \
404sysfs_in_offset(offset) \
405sysfs_in_reg_offset(min, offset) \
406sysfs_in_reg_offset(max, offset)
407
408sysfs_in_offsets(1);
409sysfs_in_offsets(2);
410sysfs_in_offsets(3);
411sysfs_in_offsets(4);
412sysfs_in_offsets(5);
413sysfs_in_offsets(6);
414sysfs_in_offsets(7);
415sysfs_in_offsets(8);
416
417/* use a different set of functions for in0 */
418static ssize_t show_in_0(struct w83627hf_data *data, char *buf, u8 reg)
419{
420 long in0;
421
422 if ((data->vrm_ovt & 0x01) &&
423 (w83627thf == data->type || w83637hf == data->type
424 || w83687thf == data->type))
425
426 /* use VRM9 calculation */
427 in0 = (long)((reg * 488 + 70000 + 50) / 100);
428 else
429 /* use VRM8 (standard) calculation */
430 in0 = (long)IN_FROM_REG(reg);
431
432 return sprintf(buf,"%ld\n", in0);
433}
434
435static ssize_t show_regs_in_0(struct device *dev, struct device_attribute *attr, char *buf)
436{
437 struct w83627hf_data *data = w83627hf_update_device(dev);
438 return show_in_0(data, buf, data->in[0]);
439}
440
441static ssize_t show_regs_in_min0(struct device *dev, struct device_attribute *attr, char *buf)
442{
443 struct w83627hf_data *data = w83627hf_update_device(dev);
444 return show_in_0(data, buf, data->in_min[0]);
445}
446
447static ssize_t show_regs_in_max0(struct device *dev, struct device_attribute *attr, char *buf)
448{
449 struct w83627hf_data *data = w83627hf_update_device(dev);
450 return show_in_0(data, buf, data->in_max[0]);
451}
452
453static ssize_t store_regs_in_min0(struct device *dev, struct device_attribute *attr,
454 const char *buf, size_t count)
455{
456 struct w83627hf_data *data = dev_get_drvdata(dev);
457 u32 val;
458
459 val = simple_strtoul(buf, NULL, 10);
460
461 mutex_lock(&data->update_lock);
462
463 if ((data->vrm_ovt & 0x01) &&
464 (w83627thf == data->type || w83637hf == data->type
465 || w83687thf == data->type))
466
467 /* use VRM9 calculation */
468 data->in_min[0] =
469 SENSORS_LIMIT(((val * 100) - 70000 + 244) / 488, 0,
470 255);
471 else
472 /* use VRM8 (standard) calculation */
473 data->in_min[0] = IN_TO_REG(val);
474
475 w83627hf_write_value(data, W83781D_REG_IN_MIN(0), data->in_min[0]);
476 mutex_unlock(&data->update_lock);
477 return count;
478}
479
480static ssize_t store_regs_in_max0(struct device *dev, struct device_attribute *attr,
481 const char *buf, size_t count)
482{
483 struct w83627hf_data *data = dev_get_drvdata(dev);
484 u32 val;
485
486 val = simple_strtoul(buf, NULL, 10);
487
488 mutex_lock(&data->update_lock);
489
490 if ((data->vrm_ovt & 0x01) &&
491 (w83627thf == data->type || w83637hf == data->type
492 || w83687thf == data->type))
493
494 /* use VRM9 calculation */
495 data->in_max[0] =
496 SENSORS_LIMIT(((val * 100) - 70000 + 244) / 488, 0,
497 255);
498 else
499 /* use VRM8 (standard) calculation */
500 data->in_max[0] = IN_TO_REG(val);
501
502 w83627hf_write_value(data, W83781D_REG_IN_MAX(0), data->in_max[0]);
503 mutex_unlock(&data->update_lock);
504 return count;
505}
506
507static DEVICE_ATTR(in0_input, S_IRUGO, show_regs_in_0, NULL);
508static DEVICE_ATTR(in0_min, S_IRUGO | S_IWUSR,
509 show_regs_in_min0, store_regs_in_min0);
510static DEVICE_ATTR(in0_max, S_IRUGO | S_IWUSR,
511 show_regs_in_max0, store_regs_in_max0);
512
513#define show_fan_reg(reg) \
514static ssize_t show_##reg (struct device *dev, char *buf, int nr) \
515{ \
516 struct w83627hf_data *data = w83627hf_update_device(dev); \
517 return sprintf(buf,"%ld\n", \
518 FAN_FROM_REG(data->reg[nr-1], \
519 (long)DIV_FROM_REG(data->fan_div[nr-1]))); \
520}
521show_fan_reg(fan);
522show_fan_reg(fan_min);
523
524static ssize_t
525store_fan_min(struct device *dev, const char *buf, size_t count, int nr)
526{
527 struct w83627hf_data *data = dev_get_drvdata(dev);
528 u32 val;
529
530 val = simple_strtoul(buf, NULL, 10);
531
532 mutex_lock(&data->update_lock);
533 data->fan_min[nr - 1] =
534 FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr - 1]));
535 w83627hf_write_value(data, W83781D_REG_FAN_MIN(nr),
536 data->fan_min[nr - 1]);
537
538 mutex_unlock(&data->update_lock);
539 return count;
540}
541
542#define sysfs_fan_offset(offset) \
543static ssize_t show_regs_fan_##offset (struct device *dev, struct device_attribute *attr, char *buf) \
544{ \
545 return show_fan(dev, buf, offset); \
546} \
547static DEVICE_ATTR(fan##offset##_input, S_IRUGO, show_regs_fan_##offset, NULL);
548
549#define sysfs_fan_min_offset(offset) \
550static ssize_t show_regs_fan_min##offset (struct device *dev, struct device_attribute *attr, char *buf) \
551{ \
552 return show_fan_min(dev, buf, offset); \
553} \
554static ssize_t \
555store_regs_fan_min##offset (struct device *dev, struct device_attribute *attr, const char *buf, size_t count) \
556{ \
557 return store_fan_min(dev, buf, count, offset); \
558} \
559static DEVICE_ATTR(fan##offset##_min, S_IRUGO | S_IWUSR, \
560 show_regs_fan_min##offset, store_regs_fan_min##offset);
561
562sysfs_fan_offset(1);
563sysfs_fan_min_offset(1);
564sysfs_fan_offset(2);
565sysfs_fan_min_offset(2);
566sysfs_fan_offset(3);
567sysfs_fan_min_offset(3);
568
569#define show_temp_reg(reg) \
570static ssize_t show_##reg (struct device *dev, char *buf, int nr) \
571{ \
572 struct w83627hf_data *data = w83627hf_update_device(dev); \
573 if (nr >= 2) { /* TEMP2 and TEMP3 */ \
574 return sprintf(buf,"%ld\n", \
575 (long)LM75_TEMP_FROM_REG(data->reg##_add[nr-2])); \
576 } else { /* TEMP1 */ \
577 return sprintf(buf,"%ld\n", (long)TEMP_FROM_REG(data->reg)); \
578 } \
579}
580show_temp_reg(temp);
581show_temp_reg(temp_max);
582show_temp_reg(temp_max_hyst);
583
584#define store_temp_reg(REG, reg) \
585static ssize_t \
586store_temp_##reg (struct device *dev, const char *buf, size_t count, int nr) \
587{ \
588 struct w83627hf_data *data = dev_get_drvdata(dev); \
589 u32 val; \
590 \
591 val = simple_strtoul(buf, NULL, 10); \
592 \
593 mutex_lock(&data->update_lock); \
594 \
595 if (nr >= 2) { /* TEMP2 and TEMP3 */ \
596 data->temp_##reg##_add[nr-2] = LM75_TEMP_TO_REG(val); \
597 w83627hf_write_value(data, W83781D_REG_TEMP_##REG(nr), \
598 data->temp_##reg##_add[nr-2]); \
599 } else { /* TEMP1 */ \
600 data->temp_##reg = TEMP_TO_REG(val); \
601 w83627hf_write_value(data, W83781D_REG_TEMP_##REG(nr), \
602 data->temp_##reg); \
603 } \
604 \
605 mutex_unlock(&data->update_lock); \
606 return count; \
607}
608store_temp_reg(OVER, max);
609store_temp_reg(HYST, max_hyst);
610
611#define sysfs_temp_offset(offset) \
612static ssize_t \
613show_regs_temp_##offset (struct device *dev, struct device_attribute *attr, char *buf) \
614{ \
615 return show_temp(dev, buf, offset); \
616} \
617static DEVICE_ATTR(temp##offset##_input, S_IRUGO, show_regs_temp_##offset, NULL);
618
619#define sysfs_temp_reg_offset(reg, offset) \
620static ssize_t show_regs_temp_##reg##offset (struct device *dev, struct device_attribute *attr, char *buf) \
621{ \
622 return show_temp_##reg (dev, buf, offset); \
623} \
624static ssize_t \
625store_regs_temp_##reg##offset (struct device *dev, struct device_attribute *attr, \
626 const char *buf, size_t count) \
627{ \
628 return store_temp_##reg (dev, buf, count, offset); \
629} \
630static DEVICE_ATTR(temp##offset##_##reg, S_IRUGO| S_IWUSR, \
631 show_regs_temp_##reg##offset, store_regs_temp_##reg##offset);
632
633#define sysfs_temp_offsets(offset) \
634sysfs_temp_offset(offset) \
635sysfs_temp_reg_offset(max, offset) \
636sysfs_temp_reg_offset(max_hyst, offset)
637
638sysfs_temp_offsets(1);
639sysfs_temp_offsets(2);
640sysfs_temp_offsets(3);
641
642static ssize_t
643show_vid_reg(struct device *dev, struct device_attribute *attr, char *buf)
644{
645 struct w83627hf_data *data = w83627hf_update_device(dev);
646 return sprintf(buf, "%ld\n", (long) vid_from_reg(data->vid, data->vrm));
647}
648static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid_reg, NULL);
649
650static ssize_t
651show_vrm_reg(struct device *dev, struct device_attribute *attr, char *buf)
652{
653 struct w83627hf_data *data = w83627hf_update_device(dev);
654 return sprintf(buf, "%ld\n", (long) data->vrm);
655}
656static ssize_t
657store_vrm_reg(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
658{
659 struct w83627hf_data *data = dev_get_drvdata(dev);
660 u32 val;
661
662 val = simple_strtoul(buf, NULL, 10);
663 data->vrm = val;
664
665 return count;
666}
667static DEVICE_ATTR(vrm, S_IRUGO | S_IWUSR, show_vrm_reg, store_vrm_reg);
668
669static ssize_t
670show_alarms_reg(struct device *dev, struct device_attribute *attr, char *buf)
671{
672 struct w83627hf_data *data = w83627hf_update_device(dev);
673 return sprintf(buf, "%ld\n", (long) data->alarms);
674}
675static DEVICE_ATTR(alarms, S_IRUGO, show_alarms_reg, NULL);
676
677#define show_beep_reg(REG, reg) \
678static ssize_t show_beep_##reg (struct device *dev, struct device_attribute *attr, char *buf) \
679{ \
680 struct w83627hf_data *data = w83627hf_update_device(dev); \
681 return sprintf(buf,"%ld\n", \
682 (long)BEEP_##REG##_FROM_REG(data->beep_##reg)); \
683}
684show_beep_reg(ENABLE, enable)
685show_beep_reg(MASK, mask)
686
687#define BEEP_ENABLE 0 /* Store beep_enable */
688#define BEEP_MASK 1 /* Store beep_mask */
689
690static ssize_t
691store_beep_reg(struct device *dev, const char *buf, size_t count,
692 int update_mask)
693{
694 struct w83627hf_data *data = dev_get_drvdata(dev);
695 u32 val, val2;
696
697 val = simple_strtoul(buf, NULL, 10);
698
699 mutex_lock(&data->update_lock);
700
701 if (update_mask == BEEP_MASK) { /* We are storing beep_mask */
702 data->beep_mask = BEEP_MASK_TO_REG(val);
703 w83627hf_write_value(data, W83781D_REG_BEEP_INTS1,
704 data->beep_mask & 0xff);
705 w83627hf_write_value(data, W83781D_REG_BEEP_INTS3,
706 ((data->beep_mask) >> 16) & 0xff);
707 val2 = (data->beep_mask >> 8) & 0x7f;
708 } else { /* We are storing beep_enable */
709 val2 =
710 w83627hf_read_value(data, W83781D_REG_BEEP_INTS2) & 0x7f;
711 data->beep_enable = BEEP_ENABLE_TO_REG(val);
712 }
713
714 w83627hf_write_value(data, W83781D_REG_BEEP_INTS2,
715 val2 | data->beep_enable << 7);
716
717 mutex_unlock(&data->update_lock);
718 return count;
719}
720
721#define sysfs_beep(REG, reg) \
722static ssize_t show_regs_beep_##reg (struct device *dev, struct device_attribute *attr, char *buf) \
723{ \
724 return show_beep_##reg(dev, attr, buf); \
725} \
726static ssize_t \
727store_regs_beep_##reg (struct device *dev, struct device_attribute *attr, const char *buf, size_t count) \
728{ \
729 return store_beep_reg(dev, buf, count, BEEP_##REG); \
730} \
731static DEVICE_ATTR(beep_##reg, S_IRUGO | S_IWUSR, \
732 show_regs_beep_##reg, store_regs_beep_##reg);
733
734sysfs_beep(ENABLE, enable);
735sysfs_beep(MASK, mask);
736
737static ssize_t
738show_fan_div_reg(struct device *dev, char *buf, int nr)
739{
740 struct w83627hf_data *data = w83627hf_update_device(dev);
741 return sprintf(buf, "%ld\n",
742 (long) DIV_FROM_REG(data->fan_div[nr - 1]));
743}
744
745/* Note: we save and restore the fan minimum here, because its value is
746 determined in part by the fan divisor. This follows the principle of
747 least surprise; the user doesn't expect the fan minimum to change just
748 because the divisor changed. */
749static ssize_t
750store_fan_div_reg(struct device *dev, const char *buf, size_t count, int nr)
751{
752 struct w83627hf_data *data = dev_get_drvdata(dev);
753 unsigned long min;
754 u8 reg;
755 unsigned long val = simple_strtoul(buf, NULL, 10);
756
757 mutex_lock(&data->update_lock);
758
759 /* Save fan_min */
760 min = FAN_FROM_REG(data->fan_min[nr],
761 DIV_FROM_REG(data->fan_div[nr]));
762
763 data->fan_div[nr] = DIV_TO_REG(val);
764
765 reg = (w83627hf_read_value(data, nr==2 ? W83781D_REG_PIN : W83781D_REG_VID_FANDIV)
766 & (nr==0 ? 0xcf : 0x3f))
767 | ((data->fan_div[nr] & 0x03) << (nr==0 ? 4 : 6));
768 w83627hf_write_value(data, nr==2 ? W83781D_REG_PIN : W83781D_REG_VID_FANDIV, reg);
769
770 reg = (w83627hf_read_value(data, W83781D_REG_VBAT)
771 & ~(1 << (5 + nr)))
772 | ((data->fan_div[nr] & 0x04) << (3 + nr));
773 w83627hf_write_value(data, W83781D_REG_VBAT, reg);
774
775 /* Restore fan_min */
776 data->fan_min[nr] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr]));
777 w83627hf_write_value(data, W83781D_REG_FAN_MIN(nr+1), data->fan_min[nr]);
778
779 mutex_unlock(&data->update_lock);
780 return count;
781}
782
783#define sysfs_fan_div(offset) \
784static ssize_t show_regs_fan_div_##offset (struct device *dev, struct device_attribute *attr, char *buf) \
785{ \
786 return show_fan_div_reg(dev, buf, offset); \
787} \
788static ssize_t \
789store_regs_fan_div_##offset (struct device *dev, struct device_attribute *attr, \
790 const char *buf, size_t count) \
791{ \
792 return store_fan_div_reg(dev, buf, count, offset - 1); \
793} \
794static DEVICE_ATTR(fan##offset##_div, S_IRUGO | S_IWUSR, \
795 show_regs_fan_div_##offset, store_regs_fan_div_##offset);
796
797sysfs_fan_div(1);
798sysfs_fan_div(2);
799sysfs_fan_div(3);
800
801static ssize_t
802show_pwm_reg(struct device *dev, char *buf, int nr)
803{
804 struct w83627hf_data *data = w83627hf_update_device(dev);
805 return sprintf(buf, "%ld\n", (long) data->pwm[nr - 1]);
806}
807
808static ssize_t
809store_pwm_reg(struct device *dev, const char *buf, size_t count, int nr)
810{
811 struct w83627hf_data *data = dev_get_drvdata(dev);
812 u32 val;
813
814 val = simple_strtoul(buf, NULL, 10);
815
816 mutex_lock(&data->update_lock);
817
818 if (data->type == w83627thf) {
819 /* bits 0-3 are reserved in 627THF */
820 data->pwm[nr - 1] = PWM_TO_REG(val) & 0xf0;
821 w83627hf_write_value(data,
822 W836X7HF_REG_PWM(data->type, nr),
823 data->pwm[nr - 1] |
824 (w83627hf_read_value(data,
825 W836X7HF_REG_PWM(data->type, nr)) & 0x0f));
826 } else {
827 data->pwm[nr - 1] = PWM_TO_REG(val);
828 w83627hf_write_value(data,
829 W836X7HF_REG_PWM(data->type, nr),
830 data->pwm[nr - 1]);
831 }
832
833 mutex_unlock(&data->update_lock);
834 return count;
835}
836
837#define sysfs_pwm(offset) \
838static ssize_t show_regs_pwm_##offset (struct device *dev, struct device_attribute *attr, char *buf) \
839{ \
840 return show_pwm_reg(dev, buf, offset); \
841} \
842static ssize_t \
843store_regs_pwm_##offset (struct device *dev, struct device_attribute *attr, const char *buf, size_t count) \
844{ \
845 return store_pwm_reg(dev, buf, count, offset); \
846} \
847static DEVICE_ATTR(pwm##offset, S_IRUGO | S_IWUSR, \
848 show_regs_pwm_##offset, store_regs_pwm_##offset);
849
850sysfs_pwm(1);
851sysfs_pwm(2);
852sysfs_pwm(3);
853
854static ssize_t
855show_sensor_reg(struct device *dev, char *buf, int nr)
856{
857 struct w83627hf_data *data = w83627hf_update_device(dev);
858 return sprintf(buf, "%ld\n", (long) data->sens[nr - 1]);
859}
860
861static ssize_t
862store_sensor_reg(struct device *dev, const char *buf, size_t count, int nr)
863{
864 struct w83627hf_data *data = dev_get_drvdata(dev);
865 u32 val, tmp;
866
867 val = simple_strtoul(buf, NULL, 10);
868
869 mutex_lock(&data->update_lock);
870
871 switch (val) {
872 case 1: /* PII/Celeron diode */
873 tmp = w83627hf_read_value(data, W83781D_REG_SCFG1);
874 w83627hf_write_value(data, W83781D_REG_SCFG1,
875 tmp | BIT_SCFG1[nr - 1]);
876 tmp = w83627hf_read_value(data, W83781D_REG_SCFG2);
877 w83627hf_write_value(data, W83781D_REG_SCFG2,
878 tmp | BIT_SCFG2[nr - 1]);
879 data->sens[nr - 1] = val;
880 break;
881 case 2: /* 3904 */
882 tmp = w83627hf_read_value(data, W83781D_REG_SCFG1);
883 w83627hf_write_value(data, W83781D_REG_SCFG1,
884 tmp | BIT_SCFG1[nr - 1]);
885 tmp = w83627hf_read_value(data, W83781D_REG_SCFG2);
886 w83627hf_write_value(data, W83781D_REG_SCFG2,
887 tmp & ~BIT_SCFG2[nr - 1]);
888 data->sens[nr - 1] = val;
889 break;
890 case W83781D_DEFAULT_BETA: /* thermistor */
891 tmp = w83627hf_read_value(data, W83781D_REG_SCFG1);
892 w83627hf_write_value(data, W83781D_REG_SCFG1,
893 tmp & ~BIT_SCFG1[nr - 1]);
894 data->sens[nr - 1] = val;
895 break;
896 default:
897 dev_err(dev,
898 "Invalid sensor type %ld; must be 1, 2, or %d\n",
899 (long) val, W83781D_DEFAULT_BETA);
900 break;
901 }
902
903 mutex_unlock(&data->update_lock);
904 return count;
905}
906
907#define sysfs_sensor(offset) \
908static ssize_t show_regs_sensor_##offset (struct device *dev, struct device_attribute *attr, char *buf) \
909{ \
910 return show_sensor_reg(dev, buf, offset); \
911} \
912static ssize_t \
913store_regs_sensor_##offset (struct device *dev, struct device_attribute *attr, const char *buf, size_t count) \
914{ \
915 return store_sensor_reg(dev, buf, count, offset); \
916} \
917static DEVICE_ATTR(temp##offset##_type, S_IRUGO | S_IWUSR, \
918 show_regs_sensor_##offset, store_regs_sensor_##offset);
919
920sysfs_sensor(1);
921sysfs_sensor(2);
922sysfs_sensor(3);
923
924static ssize_t show_name(struct device *dev, struct device_attribute
925 *devattr, char *buf)
926{
927 struct w83627hf_data *data = dev_get_drvdata(dev);
928
929 return sprintf(buf, "%s\n", data->name);
930}
931static DEVICE_ATTR(name, S_IRUGO, show_name, NULL);
932
933static int __init w83627hf_find(int sioaddr, unsigned short *addr,
934 struct w83627hf_sio_data *sio_data)
935{
936 int err = -ENODEV;
937 u16 val;
938
939 static const __initdata char *names[] = {
940 "W83627HF",
941 "W83627THF",
942 "W83697HF",
943 "W83637HF",
944 "W83687THF",
945 };
946
947 REG = sioaddr;
948 VAL = sioaddr + 1;
949
950 superio_enter();
951 val= superio_inb(DEVID);
952 switch (val) {
953 case W627_DEVID:
954 sio_data->type = w83627hf;
955 break;
956 case W627THF_DEVID:
957 sio_data->type = w83627thf;
958 break;
959 case W697_DEVID:
960 sio_data->type = w83697hf;
961 break;
962 case W637_DEVID:
963 sio_data->type = w83637hf;
964 break;
965 case W687THF_DEVID:
966 sio_data->type = w83687thf;
967 break;
968 case 0xff: /* No device at all */
969 goto exit;
970 default:
971 pr_debug(DRVNAME ": Unsupported chip (DEVID=0x%02x)\n", val);
972 goto exit;
973 }
974
975 superio_select(W83627HF_LD_HWM);
976 force_addr &= WINB_ALIGNMENT;
977 if (force_addr) {
978 printk(KERN_WARNING DRVNAME ": Forcing address 0x%x\n",
979 force_addr);
980 superio_outb(WINB_BASE_REG, force_addr >> 8);
981 superio_outb(WINB_BASE_REG + 1, force_addr & 0xff);
982 }
983 val = (superio_inb(WINB_BASE_REG) << 8) |
984 superio_inb(WINB_BASE_REG + 1);
985 *addr = val & WINB_ALIGNMENT;
986 if (*addr == 0) {
987 printk(KERN_WARNING DRVNAME ": Base address not set, "
988 "skipping\n");
989 goto exit;
990 }
991
992 val = superio_inb(WINB_ACT_REG);
993 if (!(val & 0x01)) {
994 printk(KERN_WARNING DRVNAME ": Enabling HWM logical device\n");
995 superio_outb(WINB_ACT_REG, val | 0x01);
996 }
997
998 err = 0;
999 pr_info(DRVNAME ": Found %s chip at %#x\n",
1000 names[sio_data->type], *addr);
1001
1002 exit:
1003 superio_exit();
1004 return err;
1005}
1006
1007static struct attribute *w83627hf_attributes[] = {
1008 &dev_attr_in0_input.attr,
1009 &dev_attr_in0_min.attr,
1010 &dev_attr_in0_max.attr,
1011 &dev_attr_in2_input.attr,
1012 &dev_attr_in2_min.attr,
1013 &dev_attr_in2_max.attr,
1014 &dev_attr_in3_input.attr,
1015 &dev_attr_in3_min.attr,
1016 &dev_attr_in3_max.attr,
1017 &dev_attr_in4_input.attr,
1018 &dev_attr_in4_min.attr,
1019 &dev_attr_in4_max.attr,
1020 &dev_attr_in7_input.attr,
1021 &dev_attr_in7_min.attr,
1022 &dev_attr_in7_max.attr,
1023 &dev_attr_in8_input.attr,
1024 &dev_attr_in8_min.attr,
1025 &dev_attr_in8_max.attr,
1026
1027 &dev_attr_fan1_input.attr,
1028 &dev_attr_fan1_min.attr,
1029 &dev_attr_fan1_div.attr,
1030 &dev_attr_fan2_input.attr,
1031 &dev_attr_fan2_min.attr,
1032 &dev_attr_fan2_div.attr,
1033
1034 &dev_attr_temp1_input.attr,
1035 &dev_attr_temp1_max.attr,
1036 &dev_attr_temp1_max_hyst.attr,
1037 &dev_attr_temp1_type.attr,
1038 &dev_attr_temp2_input.attr,
1039 &dev_attr_temp2_max.attr,
1040 &dev_attr_temp2_max_hyst.attr,
1041 &dev_attr_temp2_type.attr,
1042
1043 &dev_attr_alarms.attr,
1044 &dev_attr_beep_enable.attr,
1045 &dev_attr_beep_mask.attr,
1046
1047 &dev_attr_pwm1.attr,
1048 &dev_attr_pwm2.attr,
1049
1050 &dev_attr_name.attr,
1051 NULL
1052};
1053
1054static const struct attribute_group w83627hf_group = {
1055 .attrs = w83627hf_attributes,
1056};
1057
1058static struct attribute *w83627hf_attributes_opt[] = {
1059 &dev_attr_in1_input.attr,
1060 &dev_attr_in1_min.attr,
1061 &dev_attr_in1_max.attr,
1062 &dev_attr_in5_input.attr,
1063 &dev_attr_in5_min.attr,
1064 &dev_attr_in5_max.attr,
1065 &dev_attr_in6_input.attr,
1066 &dev_attr_in6_min.attr,
1067 &dev_attr_in6_max.attr,
1068
1069 &dev_attr_fan3_input.attr,
1070 &dev_attr_fan3_min.attr,
1071 &dev_attr_fan3_div.attr,
1072
1073 &dev_attr_temp3_input.attr,
1074 &dev_attr_temp3_max.attr,
1075 &dev_attr_temp3_max_hyst.attr,
1076 &dev_attr_temp3_type.attr,
1077
1078 &dev_attr_pwm3.attr,
1079
1080 NULL
1081};
1082
1083static const struct attribute_group w83627hf_group_opt = {
1084 .attrs = w83627hf_attributes_opt,
1085};
1086
1087static int __devinit w83627hf_probe(struct platform_device *pdev)
1088{
1089 struct device *dev = &pdev->dev;
1090 struct w83627hf_sio_data *sio_data = dev->platform_data;
1091 struct w83627hf_data *data;
1092 struct resource *res;
1093 int err;
1094
1095 static const char *names[] = {
1096 "w83627hf",
1097 "w83627thf",
1098 "w83697hf",
1099 "w83637hf",
1100 "w83687thf",
1101 };
1102
1103 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
1104 if (!request_region(res->start, WINB_REGION_SIZE, DRVNAME)) {
1105 dev_err(dev, "Failed to request region 0x%lx-0x%lx\n",
1106 (unsigned long)res->start,
1107 (unsigned long)(res->start + WINB_REGION_SIZE - 1));
1108 err = -EBUSY;
1109 goto ERROR0;
1110 }
1111
1112 if (!(data = kzalloc(sizeof(struct w83627hf_data), GFP_KERNEL))) {
1113 err = -ENOMEM;
1114 goto ERROR1;
1115 }
1116 data->addr = res->start;
1117 data->type = sio_data->type;
1118 data->name = names[sio_data->type];
1119 mutex_init(&data->lock);
1120 mutex_init(&data->update_lock);
1121 platform_set_drvdata(pdev, data);
1122
1123 /* Initialize the chip */
1124 w83627hf_init_device(pdev);
1125
1126 /* A few vars need to be filled upon startup */
1127 data->fan_min[0] = w83627hf_read_value(data, W83781D_REG_FAN_MIN(1));
1128 data->fan_min[1] = w83627hf_read_value(data, W83781D_REG_FAN_MIN(2));
1129 data->fan_min[2] = w83627hf_read_value(data, W83781D_REG_FAN_MIN(3));
1130
1131 /* Register common device attributes */
1132 if ((err = sysfs_create_group(&dev->kobj, &w83627hf_group)))
1133 goto ERROR3;
1134
1135 /* Register chip-specific device attributes */
1136 if (data->type == w83627hf || data->type == w83697hf)
1137 if ((err = device_create_file(dev, &dev_attr_in5_input))
1138 || (err = device_create_file(dev, &dev_attr_in5_min))
1139 || (err = device_create_file(dev, &dev_attr_in5_max))
1140 || (err = device_create_file(dev, &dev_attr_in6_input))
1141 || (err = device_create_file(dev, &dev_attr_in6_min))
1142 || (err = device_create_file(dev, &dev_attr_in6_max)))
1143 goto ERROR4;
1144
1145 if (data->type != w83697hf)
1146 if ((err = device_create_file(dev, &dev_attr_in1_input))
1147 || (err = device_create_file(dev, &dev_attr_in1_min))
1148 || (err = device_create_file(dev, &dev_attr_in1_max))
1149 || (err = device_create_file(dev, &dev_attr_fan3_input))
1150 || (err = device_create_file(dev, &dev_attr_fan3_min))
1151 || (err = device_create_file(dev, &dev_attr_fan3_div))
1152 || (err = device_create_file(dev, &dev_attr_temp3_input))
1153 || (err = device_create_file(dev, &dev_attr_temp3_max))
1154 || (err = device_create_file(dev, &dev_attr_temp3_max_hyst))
1155 || (err = device_create_file(dev, &dev_attr_temp3_type)))
1156 goto ERROR4;
1157
1158 if (data->type != w83697hf && data->vid != 0xff) {
1159 /* Convert VID to voltage based on VRM */
1160 data->vrm = vid_which_vrm();
1161
1162 if ((err = device_create_file(dev, &dev_attr_cpu0_vid))
1163 || (err = device_create_file(dev, &dev_attr_vrm)))
1164 goto ERROR4;
1165 }
1166
1167 if (data->type == w83627thf || data->type == w83637hf
1168 || data->type == w83687thf)
1169 if ((err = device_create_file(dev, &dev_attr_pwm3)))
1170 goto ERROR4;
1171
1172 data->class_dev = hwmon_device_register(dev);
1173 if (IS_ERR(data->class_dev)) {
1174 err = PTR_ERR(data->class_dev);
1175 goto ERROR4;
1176 }
1177
1178 return 0;
1179
1180 ERROR4:
1181 sysfs_remove_group(&dev->kobj, &w83627hf_group);
1182 sysfs_remove_group(&dev->kobj, &w83627hf_group_opt);
1183 ERROR3:
1184 kfree(data);
1185 ERROR1:
1186 release_region(res->start, WINB_REGION_SIZE);
1187 ERROR0:
1188 return err;
1189}
1190
1191static int __devexit w83627hf_remove(struct platform_device *pdev)
1192{
1193 struct w83627hf_data *data = platform_get_drvdata(pdev);
1194 struct resource *res;
1195
1196 platform_set_drvdata(pdev, NULL);
1197 hwmon_device_unregister(data->class_dev);
1198
1199 sysfs_remove_group(&pdev->dev.kobj, &w83627hf_group);
1200 sysfs_remove_group(&pdev->dev.kobj, &w83627hf_group_opt);
1201 kfree(data);
1202
1203 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
1204 release_region(res->start, WINB_REGION_SIZE);
1205
1206 return 0;
1207}
1208
1209
1210static int w83627hf_read_value(struct w83627hf_data *data, u16 reg)
1211{
1212 int res, word_sized;
1213
1214 mutex_lock(&data->lock);
1215 word_sized = (((reg & 0xff00) == 0x100)
1216 || ((reg & 0xff00) == 0x200))
1217 && (((reg & 0x00ff) == 0x50)
1218 || ((reg & 0x00ff) == 0x53)
1219 || ((reg & 0x00ff) == 0x55));
1220 if (reg & 0xff00) {
1221 outb_p(W83781D_REG_BANK,
1222 data->addr + W83781D_ADDR_REG_OFFSET);
1223 outb_p(reg >> 8,
1224 data->addr + W83781D_DATA_REG_OFFSET);
1225 }
1226 outb_p(reg & 0xff, data->addr + W83781D_ADDR_REG_OFFSET);
1227 res = inb_p(data->addr + W83781D_DATA_REG_OFFSET);
1228 if (word_sized) {
1229 outb_p((reg & 0xff) + 1,
1230 data->addr + W83781D_ADDR_REG_OFFSET);
1231 res =
1232 (res << 8) + inb_p(data->addr +
1233 W83781D_DATA_REG_OFFSET);
1234 }
1235 if (reg & 0xff00) {
1236 outb_p(W83781D_REG_BANK,
1237 data->addr + W83781D_ADDR_REG_OFFSET);
1238 outb_p(0, data->addr + W83781D_DATA_REG_OFFSET);
1239 }
1240 mutex_unlock(&data->lock);
1241 return res;
1242}
1243
1244static int __devinit w83627thf_read_gpio5(struct platform_device *pdev)
1245{
1246 int res = 0xff, sel;
1247
1248 superio_enter();
1249 superio_select(W83627HF_LD_GPIO5);
1250
1251 /* Make sure these GPIO pins are enabled */
1252 if (!(superio_inb(W83627THF_GPIO5_EN) & (1<<3))) {
1253 dev_dbg(&pdev->dev, "GPIO5 disabled, no VID function\n");
1254 goto exit;
1255 }
1256
1257 /* Make sure the pins are configured for input
1258 There must be at least five (VRM 9), and possibly 6 (VRM 10) */
1259 sel = superio_inb(W83627THF_GPIO5_IOSR) & 0x3f;
1260 if ((sel & 0x1f) != 0x1f) {
1261 dev_dbg(&pdev->dev, "GPIO5 not configured for VID "
1262 "function\n");
1263 goto exit;
1264 }
1265
1266 dev_info(&pdev->dev, "Reading VID from GPIO5\n");
1267 res = superio_inb(W83627THF_GPIO5_DR) & sel;
1268
1269exit:
1270 superio_exit();
1271 return res;
1272}
1273
1274static int __devinit w83687thf_read_vid(struct platform_device *pdev)
1275{
1276 int res = 0xff;
1277
1278 superio_enter();
1279 superio_select(W83627HF_LD_HWM);
1280
1281 /* Make sure these GPIO pins are enabled */
1282 if (!(superio_inb(W83687THF_VID_EN) & (1 << 2))) {
1283 dev_dbg(&pdev->dev, "VID disabled, no VID function\n");
1284 goto exit;
1285 }
1286
1287 /* Make sure the pins are configured for input */
1288 if (!(superio_inb(W83687THF_VID_CFG) & (1 << 4))) {
1289 dev_dbg(&pdev->dev, "VID configured as output, "
1290 "no VID function\n");
1291 goto exit;
1292 }
1293
1294 res = superio_inb(W83687THF_VID_DATA) & 0x3f;
1295
1296exit:
1297 superio_exit();
1298 return res;
1299}
1300
1301static int w83627hf_write_value(struct w83627hf_data *data, u16 reg, u16 value)
1302{
1303 int word_sized;
1304
1305 mutex_lock(&data->lock);
1306 word_sized = (((reg & 0xff00) == 0x100)
1307 || ((reg & 0xff00) == 0x200))
1308 && (((reg & 0x00ff) == 0x53)
1309 || ((reg & 0x00ff) == 0x55));
1310 if (reg & 0xff00) {
1311 outb_p(W83781D_REG_BANK,
1312 data->addr + W83781D_ADDR_REG_OFFSET);
1313 outb_p(reg >> 8,
1314 data->addr + W83781D_DATA_REG_OFFSET);
1315 }
1316 outb_p(reg & 0xff, data->addr + W83781D_ADDR_REG_OFFSET);
1317 if (word_sized) {
1318 outb_p(value >> 8,
1319 data->addr + W83781D_DATA_REG_OFFSET);
1320 outb_p((reg & 0xff) + 1,
1321 data->addr + W83781D_ADDR_REG_OFFSET);
1322 }
1323 outb_p(value & 0xff,
1324 data->addr + W83781D_DATA_REG_OFFSET);
1325 if (reg & 0xff00) {
1326 outb_p(W83781D_REG_BANK,
1327 data->addr + W83781D_ADDR_REG_OFFSET);
1328 outb_p(0, data->addr + W83781D_DATA_REG_OFFSET);
1329 }
1330 mutex_unlock(&data->lock);
1331 return 0;
1332}
1333
1334static void __devinit w83627hf_init_device(struct platform_device *pdev)
1335{
1336 struct w83627hf_data *data = platform_get_drvdata(pdev);
1337 int i;
1338 enum chips type = data->type;
1339 u8 tmp;
1340
1341 if (reset) {
1342 /* Resetting the chip has been the default for a long time,
1343 but repeatedly caused problems (fans going to full
1344 speed...) so it is now optional. It might even go away if
1345 nobody reports it as being useful, as I see very little
1346 reason why this would be needed at all. */
1347 dev_info(&pdev->dev, "If reset=1 solved a problem you were "
1348 "having, please report!\n");
1349
1350 /* save this register */
1351 i = w83627hf_read_value(data, W83781D_REG_BEEP_CONFIG);
1352 /* Reset all except Watchdog values and last conversion values
1353 This sets fan-divs to 2, among others */
1354 w83627hf_write_value(data, W83781D_REG_CONFIG, 0x80);
1355 /* Restore the register and disable power-on abnormal beep.
1356 This saves FAN 1/2/3 input/output values set by BIOS. */
1357 w83627hf_write_value(data, W83781D_REG_BEEP_CONFIG, i | 0x80);
1358 /* Disable master beep-enable (reset turns it on).
1359 Individual beeps should be reset to off but for some reason
1360 disabling this bit helps some people not get beeped */
1361 w83627hf_write_value(data, W83781D_REG_BEEP_INTS2, 0);
1362 }
1363
1364 /* Minimize conflicts with other winbond i2c-only clients... */
1365 /* disable i2c subclients... how to disable main i2c client?? */
1366 /* force i2c address to relatively uncommon address */
1367 w83627hf_write_value(data, W83781D_REG_I2C_SUBADDR, 0x89);
1368 w83627hf_write_value(data, W83781D_REG_I2C_ADDR, force_i2c);
1369
1370 /* Read VID only once */
1371 if (type == w83627hf || type == w83637hf) {
1372 int lo = w83627hf_read_value(data, W83781D_REG_VID_FANDIV);
1373 int hi = w83627hf_read_value(data, W83781D_REG_CHIPID);
1374 data->vid = (lo & 0x0f) | ((hi & 0x01) << 4);
1375 } else if (type == w83627thf) {
1376 data->vid = w83627thf_read_gpio5(pdev);
1377 } else if (type == w83687thf) {
1378 data->vid = w83687thf_read_vid(pdev);
1379 }
1380
1381 /* Read VRM & OVT Config only once */
1382 if (type == w83627thf || type == w83637hf || type == w83687thf) {
1383 data->vrm_ovt =
1384 w83627hf_read_value(data, W83627THF_REG_VRM_OVT_CFG);
1385 }
1386
1387 tmp = w83627hf_read_value(data, W83781D_REG_SCFG1);
1388 for (i = 1; i <= 3; i++) {
1389 if (!(tmp & BIT_SCFG1[i - 1])) {
1390 data->sens[i - 1] = W83781D_DEFAULT_BETA;
1391 } else {
1392 if (w83627hf_read_value
1393 (data,
1394 W83781D_REG_SCFG2) & BIT_SCFG2[i - 1])
1395 data->sens[i - 1] = 1;
1396 else
1397 data->sens[i - 1] = 2;
1398 }
1399 if ((type == w83697hf) && (i == 2))
1400 break;
1401 }
1402
1403 if(init) {
1404 /* Enable temp2 */
1405 tmp = w83627hf_read_value(data, W83781D_REG_TEMP2_CONFIG);
1406 if (tmp & 0x01) {
1407 dev_warn(&pdev->dev, "Enabling temp2, readings "
1408 "might not make sense\n");
1409 w83627hf_write_value(data, W83781D_REG_TEMP2_CONFIG,
1410 tmp & 0xfe);
1411 }
1412
1413 /* Enable temp3 */
1414 if (type != w83697hf) {
1415 tmp = w83627hf_read_value(data,
1416 W83781D_REG_TEMP3_CONFIG);
1417 if (tmp & 0x01) {
1418 dev_warn(&pdev->dev, "Enabling temp3, "
1419 "readings might not make sense\n");
1420 w83627hf_write_value(data,
1421 W83781D_REG_TEMP3_CONFIG, tmp & 0xfe);
1422 }
1423 }
1424 }
1425
1426 /* Start monitoring */
1427 w83627hf_write_value(data, W83781D_REG_CONFIG,
1428 (w83627hf_read_value(data,
1429 W83781D_REG_CONFIG) & 0xf7)
1430 | 0x01);
1431}
1432
1433static struct w83627hf_data *w83627hf_update_device(struct device *dev)
1434{
1435 struct w83627hf_data *data = dev_get_drvdata(dev);
1436 int i;
1437
1438 mutex_lock(&data->update_lock);
1439
1440 if (time_after(jiffies, data->last_updated + HZ + HZ / 2)
1441 || !data->valid) {
1442 for (i = 0; i <= 8; i++) {
1443 /* skip missing sensors */
1444 if (((data->type == w83697hf) && (i == 1)) ||
1445 ((data->type != w83627hf && data->type != w83697hf)
1446 && (i == 5 || i == 6)))
1447 continue;
1448 data->in[i] =
1449 w83627hf_read_value(data, W83781D_REG_IN(i));
1450 data->in_min[i] =
1451 w83627hf_read_value(data,
1452 W83781D_REG_IN_MIN(i));
1453 data->in_max[i] =
1454 w83627hf_read_value(data,
1455 W83781D_REG_IN_MAX(i));
1456 }
1457 for (i = 1; i <= 3; i++) {
1458 data->fan[i - 1] =
1459 w83627hf_read_value(data, W83781D_REG_FAN(i));
1460 data->fan_min[i - 1] =
1461 w83627hf_read_value(data,
1462 W83781D_REG_FAN_MIN(i));
1463 }
1464 for (i = 1; i <= 3; i++) {
1465 u8 tmp = w83627hf_read_value(data,
1466 W836X7HF_REG_PWM(data->type, i));
1467 /* bits 0-3 are reserved in 627THF */
1468 if (data->type == w83627thf)
1469 tmp &= 0xf0;
1470 data->pwm[i - 1] = tmp;
1471 if(i == 2 &&
1472 (data->type == w83627hf || data->type == w83697hf))
1473 break;
1474 }
1475
1476 data->temp = w83627hf_read_value(data, W83781D_REG_TEMP(1));
1477 data->temp_max =
1478 w83627hf_read_value(data, W83781D_REG_TEMP_OVER(1));
1479 data->temp_max_hyst =
1480 w83627hf_read_value(data, W83781D_REG_TEMP_HYST(1));
1481 data->temp_add[0] =
1482 w83627hf_read_value(data, W83781D_REG_TEMP(2));
1483 data->temp_max_add[0] =
1484 w83627hf_read_value(data, W83781D_REG_TEMP_OVER(2));
1485 data->temp_max_hyst_add[0] =
1486 w83627hf_read_value(data, W83781D_REG_TEMP_HYST(2));
1487 if (data->type != w83697hf) {
1488 data->temp_add[1] =
1489 w83627hf_read_value(data, W83781D_REG_TEMP(3));
1490 data->temp_max_add[1] =
1491 w83627hf_read_value(data, W83781D_REG_TEMP_OVER(3));
1492 data->temp_max_hyst_add[1] =
1493 w83627hf_read_value(data, W83781D_REG_TEMP_HYST(3));
1494 }
1495
1496 i = w83627hf_read_value(data, W83781D_REG_VID_FANDIV);
1497 data->fan_div[0] = (i >> 4) & 0x03;
1498 data->fan_div[1] = (i >> 6) & 0x03;
1499 if (data->type != w83697hf) {
1500 data->fan_div[2] = (w83627hf_read_value(data,
1501 W83781D_REG_PIN) >> 6) & 0x03;
1502 }
1503 i = w83627hf_read_value(data, W83781D_REG_VBAT);
1504 data->fan_div[0] |= (i >> 3) & 0x04;
1505 data->fan_div[1] |= (i >> 4) & 0x04;
1506 if (data->type != w83697hf)
1507 data->fan_div[2] |= (i >> 5) & 0x04;
1508 data->alarms =
1509 w83627hf_read_value(data, W83781D_REG_ALARM1) |
1510 (w83627hf_read_value(data, W83781D_REG_ALARM2) << 8) |
1511 (w83627hf_read_value(data, W83781D_REG_ALARM3) << 16);
1512 i = w83627hf_read_value(data, W83781D_REG_BEEP_INTS2);
1513 data->beep_enable = i >> 7;
1514 data->beep_mask = ((i & 0x7f) << 8) |
1515 w83627hf_read_value(data, W83781D_REG_BEEP_INTS1) |
1516 w83627hf_read_value(data, W83781D_REG_BEEP_INTS3) << 16;
1517 data->last_updated = jiffies;
1518 data->valid = 1;
1519 }
1520
1521 mutex_unlock(&data->update_lock);
1522
1523 return data;
1524}
1525
1526static int __init w83627hf_device_add(unsigned short address,
1527 const struct w83627hf_sio_data *sio_data)
1528{
1529 struct resource res = {
1530 .start = address + WINB_REGION_OFFSET,
1531 .end = address + WINB_REGION_OFFSET + WINB_REGION_SIZE - 1,
1532 .name = DRVNAME,
1533 .flags = IORESOURCE_IO,
1534 };
1535 int err;
1536
1537 pdev = platform_device_alloc(DRVNAME, address);
1538 if (!pdev) {
1539 err = -ENOMEM;
1540 printk(KERN_ERR DRVNAME ": Device allocation failed\n");
1541 goto exit;
1542 }
1543
1544 err = platform_device_add_resources(pdev, &res, 1);
1545 if (err) {
1546 printk(KERN_ERR DRVNAME ": Device resource addition failed "
1547 "(%d)\n", err);
1548 goto exit_device_put;
1549 }
1550
1551 pdev->dev.platform_data = kmalloc(sizeof(struct w83627hf_sio_data),
1552 GFP_KERNEL);
1553 if (!pdev->dev.platform_data) {
1554 err = -ENOMEM;
1555 printk(KERN_ERR DRVNAME ": Platform data allocation failed\n");
1556 goto exit_device_put;
1557 }
1558 memcpy(pdev->dev.platform_data, sio_data,
1559 sizeof(struct w83627hf_sio_data));
1560
1561 err = platform_device_add(pdev);
1562 if (err) {
1563 printk(KERN_ERR DRVNAME ": Device addition failed (%d)\n",
1564 err);
1565 goto exit_device_put;
1566 }
1567
1568 return 0;
1569
1570exit_device_put:
1571 platform_device_put(pdev);
1572exit:
1573 return err;
1574}
1575
1576static int __init sensors_w83627hf_init(void)
1577{
1578 int err;
1579 unsigned short address;
1580 struct w83627hf_sio_data sio_data;
1581
1582 if (w83627hf_find(0x2e, &address, &sio_data)
1583 && w83627hf_find(0x4e, &address, &sio_data))
1584 return -ENODEV;
1585
1586 err = platform_driver_register(&w83627hf_driver);
1587 if (err)
1588 goto exit;
1589
1590 /* Sets global pdev as a side effect */
1591 err = w83627hf_device_add(address, &sio_data);
1592 if (err)
1593 goto exit_driver;
1594
1595 return 0;
1596
1597exit_driver:
1598 platform_driver_unregister(&w83627hf_driver);
1599exit:
1600 return err;
1601}
1602
1603static void __exit sensors_w83627hf_exit(void)
1604{
1605 platform_device_unregister(pdev);
1606 platform_driver_unregister(&w83627hf_driver);
1607}
1608
1609MODULE_AUTHOR("Frodo Looijaard <frodol@dds.nl>, "
1610 "Philip Edelbrock <phil@netroedge.com>, "
1611 "and Mark Studebaker <mdsxyz123@yahoo.com>");
1612MODULE_DESCRIPTION("W83627HF driver");
1613MODULE_LICENSE("GPL");
1614
1615module_init(sensors_w83627hf_init);
1616module_exit(sensors_w83627hf_exit);
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