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1 | /* | |
2 | * linux/drivers/ide/pci/cmd64x.c Version 1.50 May 10, 2007 | |
3 | * | |
4 | * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines. | |
5 | * Due to massive hardware bugs, UltraDMA is only supported | |
6 | * on the 646U2 and not on the 646U. | |
7 | * | |
8 | * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be) | |
9 | * Copyright (C) 1998 David S. Miller (davem@redhat.com) | |
10 | * | |
11 | * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org> | |
12 | * Copyright (C) 2007 MontaVista Software, Inc. <source@mvista.com> | |
13 | */ | |
14 | ||
15 | #include <linux/module.h> | |
16 | #include <linux/types.h> | |
17 | #include <linux/pci.h> | |
18 | #include <linux/delay.h> | |
19 | #include <linux/hdreg.h> | |
20 | #include <linux/ide.h> | |
21 | #include <linux/init.h> | |
22 | ||
23 | #include <asm/io.h> | |
24 | ||
25 | #define DISPLAY_CMD64X_TIMINGS | |
26 | ||
27 | #define CMD_DEBUG 0 | |
28 | ||
29 | #if CMD_DEBUG | |
30 | #define cmdprintk(x...) printk(x) | |
31 | #else | |
32 | #define cmdprintk(x...) | |
33 | #endif | |
34 | ||
35 | /* | |
36 | * CMD64x specific registers definition. | |
37 | */ | |
38 | #define CFR 0x50 | |
39 | #define CFR_INTR_CH0 0x04 | |
40 | #define CNTRL 0x51 | |
41 | #define CNTRL_ENA_1ST 0x04 | |
42 | #define CNTRL_ENA_2ND 0x08 | |
43 | #define CNTRL_DIS_RA0 0x40 | |
44 | #define CNTRL_DIS_RA1 0x80 | |
45 | ||
46 | #define CMDTIM 0x52 | |
47 | #define ARTTIM0 0x53 | |
48 | #define DRWTIM0 0x54 | |
49 | #define ARTTIM1 0x55 | |
50 | #define DRWTIM1 0x56 | |
51 | #define ARTTIM23 0x57 | |
52 | #define ARTTIM23_DIS_RA2 0x04 | |
53 | #define ARTTIM23_DIS_RA3 0x08 | |
54 | #define ARTTIM23_INTR_CH1 0x10 | |
55 | #define DRWTIM2 0x58 | |
56 | #define BRST 0x59 | |
57 | #define DRWTIM3 0x5b | |
58 | ||
59 | #define BMIDECR0 0x70 | |
60 | #define MRDMODE 0x71 | |
61 | #define MRDMODE_INTR_CH0 0x04 | |
62 | #define MRDMODE_INTR_CH1 0x08 | |
63 | #define MRDMODE_BLK_CH0 0x10 | |
64 | #define MRDMODE_BLK_CH1 0x20 | |
65 | #define BMIDESR0 0x72 | |
66 | #define UDIDETCR0 0x73 | |
67 | #define DTPR0 0x74 | |
68 | #define BMIDECR1 0x78 | |
69 | #define BMIDECSR 0x79 | |
70 | #define BMIDESR1 0x7A | |
71 | #define UDIDETCR1 0x7B | |
72 | #define DTPR1 0x7C | |
73 | ||
74 | #if defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_IDE_PROC_FS) | |
75 | #include <linux/stat.h> | |
76 | #include <linux/proc_fs.h> | |
77 | ||
78 | static u8 cmd64x_proc = 0; | |
79 | ||
80 | #define CMD_MAX_DEVS 5 | |
81 | ||
82 | static struct pci_dev *cmd_devs[CMD_MAX_DEVS]; | |
83 | static int n_cmd_devs; | |
84 | ||
85 | static char * print_cmd64x_get_info (char *buf, struct pci_dev *dev, int index) | |
86 | { | |
87 | char *p = buf; | |
88 | u8 reg72 = 0, reg73 = 0; /* primary */ | |
89 | u8 reg7a = 0, reg7b = 0; /* secondary */ | |
90 | u8 reg50 = 1, reg51 = 1, reg57 = 0, reg71 = 0; /* extra */ | |
91 | ||
92 | p += sprintf(p, "\nController: %d\n", index); | |
93 | p += sprintf(p, "PCI-%x Chipset.\n", dev->device); | |
94 | ||
95 | (void) pci_read_config_byte(dev, CFR, ®50); | |
96 | (void) pci_read_config_byte(dev, CNTRL, ®51); | |
97 | (void) pci_read_config_byte(dev, ARTTIM23, ®57); | |
98 | (void) pci_read_config_byte(dev, MRDMODE, ®71); | |
99 | (void) pci_read_config_byte(dev, BMIDESR0, ®72); | |
100 | (void) pci_read_config_byte(dev, UDIDETCR0, ®73); | |
101 | (void) pci_read_config_byte(dev, BMIDESR1, ®7a); | |
102 | (void) pci_read_config_byte(dev, UDIDETCR1, ®7b); | |
103 | ||
104 | /* PCI0643/6 originally didn't have the primary channel enable bit */ | |
105 | if ((dev->device == PCI_DEVICE_ID_CMD_643) || | |
106 | (dev->device == PCI_DEVICE_ID_CMD_646 && dev->revision < 3)) | |
107 | reg51 |= CNTRL_ENA_1ST; | |
108 | ||
109 | p += sprintf(p, "---------------- Primary Channel " | |
110 | "---------------- Secondary Channel ------------\n"); | |
111 | p += sprintf(p, " %s %s\n", | |
112 | (reg51 & CNTRL_ENA_1ST) ? "enabled " : "disabled", | |
113 | (reg51 & CNTRL_ENA_2ND) ? "enabled " : "disabled"); | |
114 | p += sprintf(p, "---------------- drive0 --------- drive1 " | |
115 | "-------- drive0 --------- drive1 ------\n"); | |
116 | p += sprintf(p, "DMA enabled: %s %s" | |
117 | " %s %s\n", | |
118 | (reg72 & 0x20) ? "yes" : "no ", (reg72 & 0x40) ? "yes" : "no ", | |
119 | (reg7a & 0x20) ? "yes" : "no ", (reg7a & 0x40) ? "yes" : "no "); | |
120 | p += sprintf(p, "UltraDMA mode: %s (%c) %s (%c)", | |
121 | ( reg73 & 0x01) ? " on" : "off", | |
122 | ((reg73 & 0x30) == 0x30) ? ((reg73 & 0x04) ? '3' : '0') : | |
123 | ((reg73 & 0x30) == 0x20) ? ((reg73 & 0x04) ? '3' : '1') : | |
124 | ((reg73 & 0x30) == 0x10) ? ((reg73 & 0x04) ? '4' : '2') : | |
125 | ((reg73 & 0x30) == 0x00) ? ((reg73 & 0x04) ? '5' : '2') : '?', | |
126 | ( reg73 & 0x02) ? " on" : "off", | |
127 | ((reg73 & 0xC0) == 0xC0) ? ((reg73 & 0x08) ? '3' : '0') : | |
128 | ((reg73 & 0xC0) == 0x80) ? ((reg73 & 0x08) ? '3' : '1') : | |
129 | ((reg73 & 0xC0) == 0x40) ? ((reg73 & 0x08) ? '4' : '2') : | |
130 | ((reg73 & 0xC0) == 0x00) ? ((reg73 & 0x08) ? '5' : '2') : '?'); | |
131 | p += sprintf(p, " %s (%c) %s (%c)\n", | |
132 | ( reg7b & 0x01) ? " on" : "off", | |
133 | ((reg7b & 0x30) == 0x30) ? ((reg7b & 0x04) ? '3' : '0') : | |
134 | ((reg7b & 0x30) == 0x20) ? ((reg7b & 0x04) ? '3' : '1') : | |
135 | ((reg7b & 0x30) == 0x10) ? ((reg7b & 0x04) ? '4' : '2') : | |
136 | ((reg7b & 0x30) == 0x00) ? ((reg7b & 0x04) ? '5' : '2') : '?', | |
137 | ( reg7b & 0x02) ? " on" : "off", | |
138 | ((reg7b & 0xC0) == 0xC0) ? ((reg7b & 0x08) ? '3' : '0') : | |
139 | ((reg7b & 0xC0) == 0x80) ? ((reg7b & 0x08) ? '3' : '1') : | |
140 | ((reg7b & 0xC0) == 0x40) ? ((reg7b & 0x08) ? '4' : '2') : | |
141 | ((reg7b & 0xC0) == 0x00) ? ((reg7b & 0x08) ? '5' : '2') : '?'); | |
142 | p += sprintf(p, "Interrupt: %s, %s %s, %s\n", | |
143 | (reg71 & MRDMODE_BLK_CH0 ) ? "blocked" : "enabled", | |
144 | (reg50 & CFR_INTR_CH0 ) ? "pending" : "clear ", | |
145 | (reg71 & MRDMODE_BLK_CH1 ) ? "blocked" : "enabled", | |
146 | (reg57 & ARTTIM23_INTR_CH1) ? "pending" : "clear "); | |
147 | ||
148 | return (char *)p; | |
149 | } | |
150 | ||
151 | static int cmd64x_get_info (char *buffer, char **addr, off_t offset, int count) | |
152 | { | |
153 | char *p = buffer; | |
154 | int i; | |
155 | ||
156 | for (i = 0; i < n_cmd_devs; i++) { | |
157 | struct pci_dev *dev = cmd_devs[i]; | |
158 | p = print_cmd64x_get_info(p, dev, i); | |
159 | } | |
160 | return p-buffer; /* => must be less than 4k! */ | |
161 | } | |
162 | ||
163 | #endif /* defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_IDE_PROC_FS) */ | |
164 | ||
165 | static u8 quantize_timing(int timing, int quant) | |
166 | { | |
167 | return (timing + quant - 1) / quant; | |
168 | } | |
169 | ||
170 | /* | |
171 | * This routine calculates active/recovery counts and then writes them into | |
172 | * the chipset registers. | |
173 | */ | |
174 | static void program_cycle_times (ide_drive_t *drive, int cycle_time, int active_time) | |
175 | { | |
176 | struct pci_dev *dev = HWIF(drive)->pci_dev; | |
177 | int clock_time = 1000 / system_bus_clock(); | |
178 | u8 cycle_count, active_count, recovery_count, drwtim; | |
179 | static const u8 recovery_values[] = | |
180 | {15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0}; | |
181 | static const u8 drwtim_regs[4] = {DRWTIM0, DRWTIM1, DRWTIM2, DRWTIM3}; | |
182 | ||
183 | cmdprintk("program_cycle_times parameters: total=%d, active=%d\n", | |
184 | cycle_time, active_time); | |
185 | ||
186 | cycle_count = quantize_timing( cycle_time, clock_time); | |
187 | active_count = quantize_timing(active_time, clock_time); | |
188 | recovery_count = cycle_count - active_count; | |
189 | ||
190 | /* | |
191 | * In case we've got too long recovery phase, try to lengthen | |
192 | * the active phase | |
193 | */ | |
194 | if (recovery_count > 16) { | |
195 | active_count += recovery_count - 16; | |
196 | recovery_count = 16; | |
197 | } | |
198 | if (active_count > 16) /* shouldn't actually happen... */ | |
199 | active_count = 16; | |
200 | ||
201 | cmdprintk("Final counts: total=%d, active=%d, recovery=%d\n", | |
202 | cycle_count, active_count, recovery_count); | |
203 | ||
204 | /* | |
205 | * Convert values to internal chipset representation | |
206 | */ | |
207 | recovery_count = recovery_values[recovery_count]; | |
208 | active_count &= 0x0f; | |
209 | ||
210 | /* Program the active/recovery counts into the DRWTIM register */ | |
211 | drwtim = (active_count << 4) | recovery_count; | |
212 | (void) pci_write_config_byte(dev, drwtim_regs[drive->dn], drwtim); | |
213 | cmdprintk("Write 0x%02x to reg 0x%x\n", drwtim, drwtim_regs[drive->dn]); | |
214 | } | |
215 | ||
216 | /* | |
217 | * This routine selects drive's best PIO mode and writes into the chipset | |
218 | * registers setup/active/recovery timings. | |
219 | */ | |
220 | static u8 cmd64x_tune_pio (ide_drive_t *drive, u8 mode_wanted) | |
221 | { | |
222 | ide_hwif_t *hwif = HWIF(drive); | |
223 | struct pci_dev *dev = hwif->pci_dev; | |
224 | unsigned int cycle_time; | |
225 | u8 pio_mode, setup_count, arttim = 0; | |
226 | static const u8 setup_values[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0}; | |
227 | static const u8 arttim_regs[4] = {ARTTIM0, ARTTIM1, ARTTIM23, ARTTIM23}; | |
228 | ||
229 | pio_mode = ide_get_best_pio_mode(drive, mode_wanted, 5); | |
230 | cycle_time = ide_pio_cycle_time(drive, pio_mode); | |
231 | ||
232 | cmdprintk("%s: PIO mode wanted %d, selected %d (%d ns)\n", | |
233 | drive->name, mode_wanted, pio_mode, cycle_time); | |
234 | ||
235 | program_cycle_times(drive, cycle_time, | |
236 | ide_pio_timings[pio_mode].active_time); | |
237 | ||
238 | setup_count = quantize_timing(ide_pio_timings[pio_mode].setup_time, | |
239 | 1000 / system_bus_clock()); | |
240 | ||
241 | /* | |
242 | * The primary channel has individual address setup timing registers | |
243 | * for each drive and the hardware selects the slowest timing itself. | |
244 | * The secondary channel has one common register and we have to select | |
245 | * the slowest address setup timing ourselves. | |
246 | */ | |
247 | if (hwif->channel) { | |
248 | ide_drive_t *drives = hwif->drives; | |
249 | ||
250 | drive->drive_data = setup_count; | |
251 | setup_count = max(drives[0].drive_data, drives[1].drive_data); | |
252 | } | |
253 | ||
254 | if (setup_count > 5) /* shouldn't actually happen... */ | |
255 | setup_count = 5; | |
256 | cmdprintk("Final address setup count: %d\n", setup_count); | |
257 | ||
258 | /* | |
259 | * Program the address setup clocks into the ARTTIM registers. | |
260 | * Avoid clearing the secondary channel's interrupt bit. | |
261 | */ | |
262 | (void) pci_read_config_byte (dev, arttim_regs[drive->dn], &arttim); | |
263 | if (hwif->channel) | |
264 | arttim &= ~ARTTIM23_INTR_CH1; | |
265 | arttim &= ~0xc0; | |
266 | arttim |= setup_values[setup_count]; | |
267 | (void) pci_write_config_byte(dev, arttim_regs[drive->dn], arttim); | |
268 | cmdprintk("Write 0x%02x to reg 0x%x\n", arttim, arttim_regs[drive->dn]); | |
269 | ||
270 | return pio_mode; | |
271 | } | |
272 | ||
273 | /* | |
274 | * Attempts to set drive's PIO mode. | |
275 | * Special cases are 8: prefetch off, 9: prefetch on (both never worked), | |
276 | * and 255: auto-select best mode (used at boot time). | |
277 | */ | |
278 | static void cmd64x_tune_drive (ide_drive_t *drive, u8 pio) | |
279 | { | |
280 | /* | |
281 | * Filter out the prefetch control values | |
282 | * to prevent PIO5 from being programmed | |
283 | */ | |
284 | if (pio == 8 || pio == 9) | |
285 | return; | |
286 | ||
287 | pio = cmd64x_tune_pio(drive, pio); | |
288 | (void) ide_config_drive_speed(drive, XFER_PIO_0 + pio); | |
289 | } | |
290 | ||
291 | static int cmd64x_tune_chipset (ide_drive_t *drive, u8 speed) | |
292 | { | |
293 | ide_hwif_t *hwif = HWIF(drive); | |
294 | struct pci_dev *dev = hwif->pci_dev; | |
295 | u8 unit = drive->dn & 0x01; | |
296 | u8 regU = 0, pciU = hwif->channel ? UDIDETCR1 : UDIDETCR0; | |
297 | ||
298 | speed = ide_rate_filter(drive, speed); | |
299 | ||
300 | if (speed >= XFER_SW_DMA_0) { | |
301 | (void) pci_read_config_byte(dev, pciU, ®U); | |
302 | regU &= ~(unit ? 0xCA : 0x35); | |
303 | } | |
304 | ||
305 | switch(speed) { | |
306 | case XFER_UDMA_5: | |
307 | regU |= unit ? 0x0A : 0x05; | |
308 | break; | |
309 | case XFER_UDMA_4: | |
310 | regU |= unit ? 0x4A : 0x15; | |
311 | break; | |
312 | case XFER_UDMA_3: | |
313 | regU |= unit ? 0x8A : 0x25; | |
314 | break; | |
315 | case XFER_UDMA_2: | |
316 | regU |= unit ? 0x42 : 0x11; | |
317 | break; | |
318 | case XFER_UDMA_1: | |
319 | regU |= unit ? 0x82 : 0x21; | |
320 | break; | |
321 | case XFER_UDMA_0: | |
322 | regU |= unit ? 0xC2 : 0x31; | |
323 | break; | |
324 | case XFER_MW_DMA_2: | |
325 | program_cycle_times(drive, 120, 70); | |
326 | break; | |
327 | case XFER_MW_DMA_1: | |
328 | program_cycle_times(drive, 150, 80); | |
329 | break; | |
330 | case XFER_MW_DMA_0: | |
331 | program_cycle_times(drive, 480, 215); | |
332 | break; | |
333 | case XFER_PIO_5: | |
334 | case XFER_PIO_4: | |
335 | case XFER_PIO_3: | |
336 | case XFER_PIO_2: | |
337 | case XFER_PIO_1: | |
338 | case XFER_PIO_0: | |
339 | (void) cmd64x_tune_pio(drive, speed - XFER_PIO_0); | |
340 | break; | |
341 | default: | |
342 | return 1; | |
343 | } | |
344 | ||
345 | if (speed >= XFER_SW_DMA_0) | |
346 | (void) pci_write_config_byte(dev, pciU, regU); | |
347 | ||
348 | return ide_config_drive_speed(drive, speed); | |
349 | } | |
350 | ||
351 | static int cmd64x_config_drive_for_dma (ide_drive_t *drive) | |
352 | { | |
353 | if (ide_tune_dma(drive)) | |
354 | return 0; | |
355 | ||
356 | if (ide_use_fast_pio(drive)) | |
357 | cmd64x_tune_drive(drive, 255); | |
358 | ||
359 | return -1; | |
360 | } | |
361 | ||
362 | static int cmd648_ide_dma_end (ide_drive_t *drive) | |
363 | { | |
364 | ide_hwif_t *hwif = HWIF(drive); | |
365 | int err = __ide_dma_end(drive); | |
366 | u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 : | |
367 | MRDMODE_INTR_CH0; | |
368 | u8 mrdmode = inb(hwif->dma_master + 0x01); | |
369 | ||
370 | /* clear the interrupt bit */ | |
371 | outb(mrdmode | irq_mask, hwif->dma_master + 0x01); | |
372 | ||
373 | return err; | |
374 | } | |
375 | ||
376 | static int cmd64x_ide_dma_end (ide_drive_t *drive) | |
377 | { | |
378 | ide_hwif_t *hwif = HWIF(drive); | |
379 | struct pci_dev *dev = hwif->pci_dev; | |
380 | int irq_reg = hwif->channel ? ARTTIM23 : CFR; | |
381 | u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 : | |
382 | CFR_INTR_CH0; | |
383 | u8 irq_stat = 0; | |
384 | int err = __ide_dma_end(drive); | |
385 | ||
386 | (void) pci_read_config_byte(dev, irq_reg, &irq_stat); | |
387 | /* clear the interrupt bit */ | |
388 | (void) pci_write_config_byte(dev, irq_reg, irq_stat | irq_mask); | |
389 | ||
390 | return err; | |
391 | } | |
392 | ||
393 | static int cmd648_ide_dma_test_irq (ide_drive_t *drive) | |
394 | { | |
395 | ide_hwif_t *hwif = HWIF(drive); | |
396 | u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 : | |
397 | MRDMODE_INTR_CH0; | |
398 | u8 dma_stat = inb(hwif->dma_status); | |
399 | u8 mrdmode = inb(hwif->dma_master + 0x01); | |
400 | ||
401 | #ifdef DEBUG | |
402 | printk("%s: dma_stat: 0x%02x mrdmode: 0x%02x irq_mask: 0x%02x\n", | |
403 | drive->name, dma_stat, mrdmode, irq_mask); | |
404 | #endif | |
405 | if (!(mrdmode & irq_mask)) | |
406 | return 0; | |
407 | ||
408 | /* return 1 if INTR asserted */ | |
409 | if (dma_stat & 4) | |
410 | return 1; | |
411 | ||
412 | return 0; | |
413 | } | |
414 | ||
415 | static int cmd64x_ide_dma_test_irq (ide_drive_t *drive) | |
416 | { | |
417 | ide_hwif_t *hwif = HWIF(drive); | |
418 | struct pci_dev *dev = hwif->pci_dev; | |
419 | int irq_reg = hwif->channel ? ARTTIM23 : CFR; | |
420 | u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 : | |
421 | CFR_INTR_CH0; | |
422 | u8 dma_stat = inb(hwif->dma_status); | |
423 | u8 irq_stat = 0; | |
424 | ||
425 | (void) pci_read_config_byte(dev, irq_reg, &irq_stat); | |
426 | ||
427 | #ifdef DEBUG | |
428 | printk("%s: dma_stat: 0x%02x irq_stat: 0x%02x irq_mask: 0x%02x\n", | |
429 | drive->name, dma_stat, irq_stat, irq_mask); | |
430 | #endif | |
431 | if (!(irq_stat & irq_mask)) | |
432 | return 0; | |
433 | ||
434 | /* return 1 if INTR asserted */ | |
435 | if (dma_stat & 4) | |
436 | return 1; | |
437 | ||
438 | return 0; | |
439 | } | |
440 | ||
441 | /* | |
442 | * ASUS P55T2P4D with CMD646 chipset revision 0x01 requires the old | |
443 | * event order for DMA transfers. | |
444 | */ | |
445 | ||
446 | static int cmd646_1_ide_dma_end (ide_drive_t *drive) | |
447 | { | |
448 | ide_hwif_t *hwif = HWIF(drive); | |
449 | u8 dma_stat = 0, dma_cmd = 0; | |
450 | ||
451 | drive->waiting_for_dma = 0; | |
452 | /* get DMA status */ | |
453 | dma_stat = inb(hwif->dma_status); | |
454 | /* read DMA command state */ | |
455 | dma_cmd = inb(hwif->dma_command); | |
456 | /* stop DMA */ | |
457 | outb(dma_cmd & ~1, hwif->dma_command); | |
458 | /* clear the INTR & ERROR bits */ | |
459 | outb(dma_stat | 6, hwif->dma_status); | |
460 | /* and free any DMA resources */ | |
461 | ide_destroy_dmatable(drive); | |
462 | /* verify good DMA status */ | |
463 | return (dma_stat & 7) != 4; | |
464 | } | |
465 | ||
466 | static unsigned int __devinit init_chipset_cmd64x(struct pci_dev *dev, const char *name) | |
467 | { | |
468 | u8 mrdmode = 0; | |
469 | ||
470 | if (dev->device == PCI_DEVICE_ID_CMD_646) { | |
471 | u8 rev = 0; | |
472 | ||
473 | pci_read_config_byte(dev, PCI_REVISION_ID, &rev); | |
474 | ||
475 | switch (rev) { | |
476 | case 0x07: | |
477 | case 0x05: | |
478 | printk("%s: UltraDMA capable", name); | |
479 | break; | |
480 | case 0x03: | |
481 | default: | |
482 | printk("%s: MultiWord DMA force limited", name); | |
483 | break; | |
484 | case 0x01: | |
485 | printk("%s: MultiWord DMA limited, " | |
486 | "IRQ workaround enabled\n", name); | |
487 | break; | |
488 | } | |
489 | } | |
490 | ||
491 | /* Set a good latency timer and cache line size value. */ | |
492 | (void) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64); | |
493 | /* FIXME: pci_set_master() to ensure a good latency timer value */ | |
494 | ||
495 | /* | |
496 | * Enable interrupts, select MEMORY READ LINE for reads. | |
497 | * | |
498 | * NOTE: although not mentioned in the PCI0646U specs, | |
499 | * bits 0-1 are write only and won't be read back as | |
500 | * set or not -- PCI0646U2 specs clarify this point. | |
501 | */ | |
502 | (void) pci_read_config_byte (dev, MRDMODE, &mrdmode); | |
503 | mrdmode &= ~0x30; | |
504 | (void) pci_write_config_byte(dev, MRDMODE, (mrdmode | 0x02)); | |
505 | ||
506 | #if defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_IDE_PROC_FS) | |
507 | ||
508 | cmd_devs[n_cmd_devs++] = dev; | |
509 | ||
510 | if (!cmd64x_proc) { | |
511 | cmd64x_proc = 1; | |
512 | ide_pci_create_host_proc("cmd64x", cmd64x_get_info); | |
513 | } | |
514 | #endif /* DISPLAY_CMD64X_TIMINGS && CONFIG_IDE_PROC_FS */ | |
515 | ||
516 | return 0; | |
517 | } | |
518 | ||
519 | static u8 __devinit ata66_cmd64x(ide_hwif_t *hwif) | |
520 | { | |
521 | struct pci_dev *dev = hwif->pci_dev; | |
522 | u8 bmidecsr = 0, mask = hwif->channel ? 0x02 : 0x01; | |
523 | ||
524 | switch (dev->device) { | |
525 | case PCI_DEVICE_ID_CMD_648: | |
526 | case PCI_DEVICE_ID_CMD_649: | |
527 | pci_read_config_byte(dev, BMIDECSR, &bmidecsr); | |
528 | return (bmidecsr & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40; | |
529 | default: | |
530 | return ATA_CBL_PATA40; | |
531 | } | |
532 | } | |
533 | ||
534 | static void __devinit init_hwif_cmd64x(ide_hwif_t *hwif) | |
535 | { | |
536 | struct pci_dev *dev = hwif->pci_dev; | |
537 | u8 rev = 0; | |
538 | ||
539 | pci_read_config_byte(dev, PCI_REVISION_ID, &rev); | |
540 | ||
541 | hwif->tuneproc = &cmd64x_tune_drive; | |
542 | hwif->speedproc = &cmd64x_tune_chipset; | |
543 | ||
544 | hwif->drives[0].autotune = hwif->drives[1].autotune = 1; | |
545 | ||
546 | if (!hwif->dma_base) | |
547 | return; | |
548 | ||
549 | hwif->atapi_dma = 1; | |
550 | hwif->mwdma_mask = 0x07; | |
551 | hwif->ultra_mask = hwif->cds->udma_mask; | |
552 | ||
553 | /* | |
554 | * UltraDMA only supported on PCI646U and PCI646U2, which | |
555 | * correspond to revisions 0x03, 0x05 and 0x07 respectively. | |
556 | * Actually, although the CMD tech support people won't | |
557 | * tell me the details, the 0x03 revision cannot support | |
558 | * UDMA correctly without hardware modifications, and even | |
559 | * then it only works with Quantum disks due to some | |
560 | * hold time assumptions in the 646U part which are fixed | |
561 | * in the 646U2. | |
562 | * | |
563 | * So we only do UltraDMA on revision 0x05 and 0x07 chipsets. | |
564 | */ | |
565 | if (dev->device == PCI_DEVICE_ID_CMD_646 && rev < 5) | |
566 | hwif->ultra_mask = 0x00; | |
567 | ||
568 | hwif->ide_dma_check = &cmd64x_config_drive_for_dma; | |
569 | ||
570 | if (hwif->cbl != ATA_CBL_PATA40_SHORT) | |
571 | hwif->cbl = ata66_cmd64x(hwif); | |
572 | ||
573 | switch (dev->device) { | |
574 | case PCI_DEVICE_ID_CMD_648: | |
575 | case PCI_DEVICE_ID_CMD_649: | |
576 | alt_irq_bits: | |
577 | hwif->ide_dma_end = &cmd648_ide_dma_end; | |
578 | hwif->ide_dma_test_irq = &cmd648_ide_dma_test_irq; | |
579 | break; | |
580 | case PCI_DEVICE_ID_CMD_646: | |
581 | hwif->chipset = ide_cmd646; | |
582 | if (rev == 0x01) { | |
583 | hwif->ide_dma_end = &cmd646_1_ide_dma_end; | |
584 | break; | |
585 | } else if (rev >= 0x03) | |
586 | goto alt_irq_bits; | |
587 | /* fall thru */ | |
588 | default: | |
589 | hwif->ide_dma_end = &cmd64x_ide_dma_end; | |
590 | hwif->ide_dma_test_irq = &cmd64x_ide_dma_test_irq; | |
591 | break; | |
592 | } | |
593 | ||
594 | if (!noautodma) | |
595 | hwif->autodma = 1; | |
596 | hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma; | |
597 | } | |
598 | ||
599 | static int __devinit init_setup_cmd64x(struct pci_dev *dev, ide_pci_device_t *d) | |
600 | { | |
601 | return ide_setup_pci_device(dev, d); | |
602 | } | |
603 | ||
604 | static int __devinit init_setup_cmd646(struct pci_dev *dev, ide_pci_device_t *d) | |
605 | { | |
606 | /* | |
607 | * The original PCI0646 didn't have the primary channel enable bit, | |
608 | * it appeared starting with PCI0646U (i.e. revision ID 3). | |
609 | */ | |
610 | if (dev->revision < 3) | |
611 | d->enablebits[0].reg = 0; | |
612 | ||
613 | return ide_setup_pci_device(dev, d); | |
614 | } | |
615 | ||
616 | static ide_pci_device_t cmd64x_chipsets[] __devinitdata = { | |
617 | { /* 0 */ | |
618 | .name = "CMD643", | |
619 | .init_setup = init_setup_cmd64x, | |
620 | .init_chipset = init_chipset_cmd64x, | |
621 | .init_hwif = init_hwif_cmd64x, | |
622 | .autodma = AUTODMA, | |
623 | .enablebits = {{0x00,0x00,0x00}, {0x51,0x08,0x08}}, | |
624 | .bootable = ON_BOARD, | |
625 | .pio_mask = ATA_PIO5, | |
626 | .udma_mask = 0x00, /* no udma */ | |
627 | },{ /* 1 */ | |
628 | .name = "CMD646", | |
629 | .init_setup = init_setup_cmd646, | |
630 | .init_chipset = init_chipset_cmd64x, | |
631 | .init_hwif = init_hwif_cmd64x, | |
632 | .autodma = AUTODMA, | |
633 | .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}}, | |
634 | .bootable = ON_BOARD, | |
635 | .pio_mask = ATA_PIO5, | |
636 | .udma_mask = 0x07, /* udma0-2 */ | |
637 | },{ /* 2 */ | |
638 | .name = "CMD648", | |
639 | .init_setup = init_setup_cmd64x, | |
640 | .init_chipset = init_chipset_cmd64x, | |
641 | .init_hwif = init_hwif_cmd64x, | |
642 | .autodma = AUTODMA, | |
643 | .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}}, | |
644 | .bootable = ON_BOARD, | |
645 | .pio_mask = ATA_PIO5, | |
646 | .udma_mask = 0x1f, /* udma0-4 */ | |
647 | },{ /* 3 */ | |
648 | .name = "CMD649", | |
649 | .init_setup = init_setup_cmd64x, | |
650 | .init_chipset = init_chipset_cmd64x, | |
651 | .init_hwif = init_hwif_cmd64x, | |
652 | .autodma = AUTODMA, | |
653 | .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}}, | |
654 | .bootable = ON_BOARD, | |
655 | .pio_mask = ATA_PIO5, | |
656 | .udma_mask = 0x3f, /* udma0-5 */ | |
657 | } | |
658 | }; | |
659 | ||
660 | /* | |
661 | * We may have to modify enablebits for PCI0646, so we'd better pass | |
662 | * a local copy of the ide_pci_device_t structure down the call chain... | |
663 | */ | |
664 | static int __devinit cmd64x_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
665 | { | |
666 | ide_pci_device_t d = cmd64x_chipsets[id->driver_data]; | |
667 | ||
668 | return d.init_setup(dev, &d); | |
669 | } | |
670 | ||
671 | static struct pci_device_id cmd64x_pci_tbl[] = { | |
672 | { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_643, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
673 | { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1}, | |
674 | { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_648, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2}, | |
675 | { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3}, | |
676 | { 0, }, | |
677 | }; | |
678 | MODULE_DEVICE_TABLE(pci, cmd64x_pci_tbl); | |
679 | ||
680 | static struct pci_driver driver = { | |
681 | .name = "CMD64x_IDE", | |
682 | .id_table = cmd64x_pci_tbl, | |
683 | .probe = cmd64x_init_one, | |
684 | }; | |
685 | ||
686 | static int __init cmd64x_ide_init(void) | |
687 | { | |
688 | return ide_pci_register_driver(&driver); | |
689 | } | |
690 | ||
691 | module_init(cmd64x_ide_init); | |
692 | ||
693 | MODULE_AUTHOR("Eddie Dost, David Miller, Andre Hedrick"); | |
694 | MODULE_DESCRIPTION("PCI driver module for CMD64x IDE"); | |
695 | MODULE_LICENSE("GPL"); |