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1 | /* | |
2 | * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. | |
3 | * Author: Joerg Roedel <jroedel@suse.de> | |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/ratelimit.h> | |
21 | #include <linux/pci.h> | |
22 | #include <linux/acpi.h> | |
23 | #include <linux/amba/bus.h> | |
24 | #include <linux/platform_device.h> | |
25 | #include <linux/pci-ats.h> | |
26 | #include <linux/bitmap.h> | |
27 | #include <linux/slab.h> | |
28 | #include <linux/debugfs.h> | |
29 | #include <linux/scatterlist.h> | |
30 | #include <linux/dma-mapping.h> | |
31 | #include <linux/iommu-helper.h> | |
32 | #include <linux/iommu.h> | |
33 | #include <linux/delay.h> | |
34 | #include <linux/amd-iommu.h> | |
35 | #include <linux/notifier.h> | |
36 | #include <linux/export.h> | |
37 | #include <linux/irq.h> | |
38 | #include <linux/msi.h> | |
39 | #include <linux/dma-contiguous.h> | |
40 | #include <linux/irqdomain.h> | |
41 | #include <linux/percpu.h> | |
42 | #include <linux/iova.h> | |
43 | #include <asm/irq_remapping.h> | |
44 | #include <asm/io_apic.h> | |
45 | #include <asm/apic.h> | |
46 | #include <asm/hw_irq.h> | |
47 | #include <asm/msidef.h> | |
48 | #include <asm/proto.h> | |
49 | #include <asm/iommu.h> | |
50 | #include <asm/gart.h> | |
51 | #include <asm/dma.h> | |
52 | ||
53 | #include "amd_iommu_proto.h" | |
54 | #include "amd_iommu_types.h" | |
55 | #include "irq_remapping.h" | |
56 | ||
57 | #define AMD_IOMMU_MAPPING_ERROR 0 | |
58 | ||
59 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
60 | ||
61 | #define LOOP_TIMEOUT 100000 | |
62 | ||
63 | /* IO virtual address start page frame number */ | |
64 | #define IOVA_START_PFN (1) | |
65 | #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT) | |
66 | #define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32)) | |
67 | ||
68 | /* Reserved IOVA ranges */ | |
69 | #define MSI_RANGE_START (0xfee00000) | |
70 | #define MSI_RANGE_END (0xfeefffff) | |
71 | #define HT_RANGE_START (0xfd00000000ULL) | |
72 | #define HT_RANGE_END (0xffffffffffULL) | |
73 | ||
74 | /* | |
75 | * This bitmap is used to advertise the page sizes our hardware support | |
76 | * to the IOMMU core, which will then use this information to split | |
77 | * physically contiguous memory regions it is mapping into page sizes | |
78 | * that we support. | |
79 | * | |
80 | * 512GB Pages are not supported due to a hardware bug | |
81 | */ | |
82 | #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38)) | |
83 | ||
84 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); | |
85 | ||
86 | /* List of all available dev_data structures */ | |
87 | static LIST_HEAD(dev_data_list); | |
88 | static DEFINE_SPINLOCK(dev_data_list_lock); | |
89 | ||
90 | LIST_HEAD(ioapic_map); | |
91 | LIST_HEAD(hpet_map); | |
92 | LIST_HEAD(acpihid_map); | |
93 | ||
94 | /* | |
95 | * Domain for untranslated devices - only allocated | |
96 | * if iommu=pt passed on kernel cmd line. | |
97 | */ | |
98 | const struct iommu_ops amd_iommu_ops; | |
99 | ||
100 | static ATOMIC_NOTIFIER_HEAD(ppr_notifier); | |
101 | int amd_iommu_max_glx_val = -1; | |
102 | ||
103 | static const struct dma_map_ops amd_iommu_dma_ops; | |
104 | ||
105 | /* | |
106 | * This struct contains device specific data for the IOMMU | |
107 | */ | |
108 | struct iommu_dev_data { | |
109 | struct list_head list; /* For domain->dev_list */ | |
110 | struct list_head dev_data_list; /* For global dev_data_list */ | |
111 | struct protection_domain *domain; /* Domain the device is bound to */ | |
112 | u16 devid; /* PCI Device ID */ | |
113 | u16 alias; /* Alias Device ID */ | |
114 | bool iommu_v2; /* Device can make use of IOMMUv2 */ | |
115 | bool passthrough; /* Device is identity mapped */ | |
116 | struct { | |
117 | bool enabled; | |
118 | int qdep; | |
119 | } ats; /* ATS state */ | |
120 | bool pri_tlp; /* PASID TLB required for | |
121 | PPR completions */ | |
122 | u32 errata; /* Bitmap for errata to apply */ | |
123 | bool use_vapic; /* Enable device to use vapic mode */ | |
124 | ||
125 | struct ratelimit_state rs; /* Ratelimit IOPF messages */ | |
126 | }; | |
127 | ||
128 | /* | |
129 | * general struct to manage commands send to an IOMMU | |
130 | */ | |
131 | struct iommu_cmd { | |
132 | u32 data[4]; | |
133 | }; | |
134 | ||
135 | struct kmem_cache *amd_iommu_irq_cache; | |
136 | ||
137 | static void update_domain(struct protection_domain *domain); | |
138 | static int protection_domain_init(struct protection_domain *domain); | |
139 | static void detach_device(struct device *dev); | |
140 | ||
141 | #define FLUSH_QUEUE_SIZE 256 | |
142 | ||
143 | struct flush_queue_entry { | |
144 | unsigned long iova_pfn; | |
145 | unsigned long pages; | |
146 | u64 counter; /* Flush counter when this entry was added to the queue */ | |
147 | }; | |
148 | ||
149 | struct flush_queue { | |
150 | struct flush_queue_entry *entries; | |
151 | unsigned head, tail; | |
152 | spinlock_t lock; | |
153 | }; | |
154 | ||
155 | /* | |
156 | * Data container for a dma_ops specific protection domain | |
157 | */ | |
158 | struct dma_ops_domain { | |
159 | /* generic protection domain information */ | |
160 | struct protection_domain domain; | |
161 | ||
162 | /* IOVA RB-Tree */ | |
163 | struct iova_domain iovad; | |
164 | ||
165 | struct flush_queue __percpu *flush_queue; | |
166 | ||
167 | /* | |
168 | * We need two counter here to be race-free wrt. IOTLB flushing and | |
169 | * adding entries to the flush queue. | |
170 | * | |
171 | * The flush_start_cnt is incremented _before_ the IOTLB flush starts. | |
172 | * New entries added to the flush ring-buffer get their 'counter' value | |
173 | * from here. This way we can make sure that entries added to the queue | |
174 | * (or other per-cpu queues of the same domain) while the TLB is about | |
175 | * to be flushed are not considered to be flushed already. | |
176 | */ | |
177 | atomic64_t flush_start_cnt; | |
178 | ||
179 | /* | |
180 | * The flush_finish_cnt is incremented when an IOTLB flush is complete. | |
181 | * This value is always smaller than flush_start_cnt. The queue_add | |
182 | * function frees all IOVAs that have a counter value smaller than | |
183 | * flush_finish_cnt. This makes sure that we only free IOVAs that are | |
184 | * flushed out of the IOTLB of the domain. | |
185 | */ | |
186 | atomic64_t flush_finish_cnt; | |
187 | ||
188 | /* | |
189 | * Timer to make sure we don't keep IOVAs around unflushed | |
190 | * for too long | |
191 | */ | |
192 | struct timer_list flush_timer; | |
193 | atomic_t flush_timer_on; | |
194 | }; | |
195 | ||
196 | static struct iova_domain reserved_iova_ranges; | |
197 | static struct lock_class_key reserved_rbtree_key; | |
198 | ||
199 | /**************************************************************************** | |
200 | * | |
201 | * Helper functions | |
202 | * | |
203 | ****************************************************************************/ | |
204 | ||
205 | static inline int match_hid_uid(struct device *dev, | |
206 | struct acpihid_map_entry *entry) | |
207 | { | |
208 | const char *hid, *uid; | |
209 | ||
210 | hid = acpi_device_hid(ACPI_COMPANION(dev)); | |
211 | uid = acpi_device_uid(ACPI_COMPANION(dev)); | |
212 | ||
213 | if (!hid || !(*hid)) | |
214 | return -ENODEV; | |
215 | ||
216 | if (!uid || !(*uid)) | |
217 | return strcmp(hid, entry->hid); | |
218 | ||
219 | if (!(*entry->uid)) | |
220 | return strcmp(hid, entry->hid); | |
221 | ||
222 | return (strcmp(hid, entry->hid) || strcmp(uid, entry->uid)); | |
223 | } | |
224 | ||
225 | static inline u16 get_pci_device_id(struct device *dev) | |
226 | { | |
227 | struct pci_dev *pdev = to_pci_dev(dev); | |
228 | ||
229 | return PCI_DEVID(pdev->bus->number, pdev->devfn); | |
230 | } | |
231 | ||
232 | static inline int get_acpihid_device_id(struct device *dev, | |
233 | struct acpihid_map_entry **entry) | |
234 | { | |
235 | struct acpihid_map_entry *p; | |
236 | ||
237 | list_for_each_entry(p, &acpihid_map, list) { | |
238 | if (!match_hid_uid(dev, p)) { | |
239 | if (entry) | |
240 | *entry = p; | |
241 | return p->devid; | |
242 | } | |
243 | } | |
244 | return -EINVAL; | |
245 | } | |
246 | ||
247 | static inline int get_device_id(struct device *dev) | |
248 | { | |
249 | int devid; | |
250 | ||
251 | if (dev_is_pci(dev)) | |
252 | devid = get_pci_device_id(dev); | |
253 | else | |
254 | devid = get_acpihid_device_id(dev, NULL); | |
255 | ||
256 | return devid; | |
257 | } | |
258 | ||
259 | static struct protection_domain *to_pdomain(struct iommu_domain *dom) | |
260 | { | |
261 | return container_of(dom, struct protection_domain, domain); | |
262 | } | |
263 | ||
264 | static struct dma_ops_domain* to_dma_ops_domain(struct protection_domain *domain) | |
265 | { | |
266 | BUG_ON(domain->flags != PD_DMA_OPS_MASK); | |
267 | return container_of(domain, struct dma_ops_domain, domain); | |
268 | } | |
269 | ||
270 | static struct iommu_dev_data *alloc_dev_data(u16 devid) | |
271 | { | |
272 | struct iommu_dev_data *dev_data; | |
273 | unsigned long flags; | |
274 | ||
275 | dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL); | |
276 | if (!dev_data) | |
277 | return NULL; | |
278 | ||
279 | dev_data->devid = devid; | |
280 | ||
281 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
282 | list_add_tail(&dev_data->dev_data_list, &dev_data_list); | |
283 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
284 | ||
285 | ratelimit_default_init(&dev_data->rs); | |
286 | ||
287 | return dev_data; | |
288 | } | |
289 | ||
290 | static struct iommu_dev_data *search_dev_data(u16 devid) | |
291 | { | |
292 | struct iommu_dev_data *dev_data; | |
293 | unsigned long flags; | |
294 | ||
295 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
296 | list_for_each_entry(dev_data, &dev_data_list, dev_data_list) { | |
297 | if (dev_data->devid == devid) | |
298 | goto out_unlock; | |
299 | } | |
300 | ||
301 | dev_data = NULL; | |
302 | ||
303 | out_unlock: | |
304 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
305 | ||
306 | return dev_data; | |
307 | } | |
308 | ||
309 | static int __last_alias(struct pci_dev *pdev, u16 alias, void *data) | |
310 | { | |
311 | *(u16 *)data = alias; | |
312 | return 0; | |
313 | } | |
314 | ||
315 | static u16 get_alias(struct device *dev) | |
316 | { | |
317 | struct pci_dev *pdev = to_pci_dev(dev); | |
318 | u16 devid, ivrs_alias, pci_alias; | |
319 | ||
320 | /* The callers make sure that get_device_id() does not fail here */ | |
321 | devid = get_device_id(dev); | |
322 | ivrs_alias = amd_iommu_alias_table[devid]; | |
323 | pci_for_each_dma_alias(pdev, __last_alias, &pci_alias); | |
324 | ||
325 | if (ivrs_alias == pci_alias) | |
326 | return ivrs_alias; | |
327 | ||
328 | /* | |
329 | * DMA alias showdown | |
330 | * | |
331 | * The IVRS is fairly reliable in telling us about aliases, but it | |
332 | * can't know about every screwy device. If we don't have an IVRS | |
333 | * reported alias, use the PCI reported alias. In that case we may | |
334 | * still need to initialize the rlookup and dev_table entries if the | |
335 | * alias is to a non-existent device. | |
336 | */ | |
337 | if (ivrs_alias == devid) { | |
338 | if (!amd_iommu_rlookup_table[pci_alias]) { | |
339 | amd_iommu_rlookup_table[pci_alias] = | |
340 | amd_iommu_rlookup_table[devid]; | |
341 | memcpy(amd_iommu_dev_table[pci_alias].data, | |
342 | amd_iommu_dev_table[devid].data, | |
343 | sizeof(amd_iommu_dev_table[pci_alias].data)); | |
344 | } | |
345 | ||
346 | return pci_alias; | |
347 | } | |
348 | ||
349 | pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d " | |
350 | "for device %s[%04x:%04x], kernel reported alias " | |
351 | "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias), | |
352 | PCI_FUNC(ivrs_alias), dev_name(dev), pdev->vendor, pdev->device, | |
353 | PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias), | |
354 | PCI_FUNC(pci_alias)); | |
355 | ||
356 | /* | |
357 | * If we don't have a PCI DMA alias and the IVRS alias is on the same | |
358 | * bus, then the IVRS table may know about a quirk that we don't. | |
359 | */ | |
360 | if (pci_alias == devid && | |
361 | PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) { | |
362 | pci_add_dma_alias(pdev, ivrs_alias & 0xff); | |
363 | pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n", | |
364 | PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias), | |
365 | dev_name(dev)); | |
366 | } | |
367 | ||
368 | return ivrs_alias; | |
369 | } | |
370 | ||
371 | static struct iommu_dev_data *find_dev_data(u16 devid) | |
372 | { | |
373 | struct iommu_dev_data *dev_data; | |
374 | ||
375 | dev_data = search_dev_data(devid); | |
376 | ||
377 | if (dev_data == NULL) | |
378 | dev_data = alloc_dev_data(devid); | |
379 | ||
380 | return dev_data; | |
381 | } | |
382 | ||
383 | static struct iommu_dev_data *get_dev_data(struct device *dev) | |
384 | { | |
385 | return dev->archdata.iommu; | |
386 | } | |
387 | ||
388 | /* | |
389 | * Find or create an IOMMU group for a acpihid device. | |
390 | */ | |
391 | static struct iommu_group *acpihid_device_group(struct device *dev) | |
392 | { | |
393 | struct acpihid_map_entry *p, *entry = NULL; | |
394 | int devid; | |
395 | ||
396 | devid = get_acpihid_device_id(dev, &entry); | |
397 | if (devid < 0) | |
398 | return ERR_PTR(devid); | |
399 | ||
400 | list_for_each_entry(p, &acpihid_map, list) { | |
401 | if ((devid == p->devid) && p->group) | |
402 | entry->group = p->group; | |
403 | } | |
404 | ||
405 | if (!entry->group) | |
406 | entry->group = generic_device_group(dev); | |
407 | else | |
408 | iommu_group_ref_get(entry->group); | |
409 | ||
410 | return entry->group; | |
411 | } | |
412 | ||
413 | static bool pci_iommuv2_capable(struct pci_dev *pdev) | |
414 | { | |
415 | static const int caps[] = { | |
416 | PCI_EXT_CAP_ID_ATS, | |
417 | PCI_EXT_CAP_ID_PRI, | |
418 | PCI_EXT_CAP_ID_PASID, | |
419 | }; | |
420 | int i, pos; | |
421 | ||
422 | for (i = 0; i < 3; ++i) { | |
423 | pos = pci_find_ext_capability(pdev, caps[i]); | |
424 | if (pos == 0) | |
425 | return false; | |
426 | } | |
427 | ||
428 | return true; | |
429 | } | |
430 | ||
431 | static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum) | |
432 | { | |
433 | struct iommu_dev_data *dev_data; | |
434 | ||
435 | dev_data = get_dev_data(&pdev->dev); | |
436 | ||
437 | return dev_data->errata & (1 << erratum) ? true : false; | |
438 | } | |
439 | ||
440 | /* | |
441 | * This function checks if the driver got a valid device from the caller to | |
442 | * avoid dereferencing invalid pointers. | |
443 | */ | |
444 | static bool check_device(struct device *dev) | |
445 | { | |
446 | int devid; | |
447 | ||
448 | if (!dev || !dev->dma_mask) | |
449 | return false; | |
450 | ||
451 | devid = get_device_id(dev); | |
452 | if (devid < 0) | |
453 | return false; | |
454 | ||
455 | /* Out of our scope? */ | |
456 | if (devid > amd_iommu_last_bdf) | |
457 | return false; | |
458 | ||
459 | if (amd_iommu_rlookup_table[devid] == NULL) | |
460 | return false; | |
461 | ||
462 | return true; | |
463 | } | |
464 | ||
465 | static void init_iommu_group(struct device *dev) | |
466 | { | |
467 | struct iommu_group *group; | |
468 | ||
469 | group = iommu_group_get_for_dev(dev); | |
470 | if (IS_ERR(group)) | |
471 | return; | |
472 | ||
473 | iommu_group_put(group); | |
474 | } | |
475 | ||
476 | static int iommu_init_device(struct device *dev) | |
477 | { | |
478 | struct iommu_dev_data *dev_data; | |
479 | struct amd_iommu *iommu; | |
480 | int devid; | |
481 | ||
482 | if (dev->archdata.iommu) | |
483 | return 0; | |
484 | ||
485 | devid = get_device_id(dev); | |
486 | if (devid < 0) | |
487 | return devid; | |
488 | ||
489 | iommu = amd_iommu_rlookup_table[devid]; | |
490 | ||
491 | dev_data = find_dev_data(devid); | |
492 | if (!dev_data) | |
493 | return -ENOMEM; | |
494 | ||
495 | dev_data->alias = get_alias(dev); | |
496 | ||
497 | if (dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) { | |
498 | struct amd_iommu *iommu; | |
499 | ||
500 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
501 | dev_data->iommu_v2 = iommu->is_iommu_v2; | |
502 | } | |
503 | ||
504 | dev->archdata.iommu = dev_data; | |
505 | ||
506 | iommu_device_link(&iommu->iommu, dev); | |
507 | ||
508 | return 0; | |
509 | } | |
510 | ||
511 | static void iommu_ignore_device(struct device *dev) | |
512 | { | |
513 | u16 alias; | |
514 | int devid; | |
515 | ||
516 | devid = get_device_id(dev); | |
517 | if (devid < 0) | |
518 | return; | |
519 | ||
520 | alias = get_alias(dev); | |
521 | ||
522 | memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry)); | |
523 | memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry)); | |
524 | ||
525 | amd_iommu_rlookup_table[devid] = NULL; | |
526 | amd_iommu_rlookup_table[alias] = NULL; | |
527 | } | |
528 | ||
529 | static void iommu_uninit_device(struct device *dev) | |
530 | { | |
531 | struct iommu_dev_data *dev_data; | |
532 | struct amd_iommu *iommu; | |
533 | int devid; | |
534 | ||
535 | devid = get_device_id(dev); | |
536 | if (devid < 0) | |
537 | return; | |
538 | ||
539 | iommu = amd_iommu_rlookup_table[devid]; | |
540 | ||
541 | dev_data = search_dev_data(devid); | |
542 | if (!dev_data) | |
543 | return; | |
544 | ||
545 | if (dev_data->domain) | |
546 | detach_device(dev); | |
547 | ||
548 | iommu_device_unlink(&iommu->iommu, dev); | |
549 | ||
550 | iommu_group_remove_device(dev); | |
551 | ||
552 | /* Remove dma-ops */ | |
553 | dev->dma_ops = NULL; | |
554 | ||
555 | /* | |
556 | * We keep dev_data around for unplugged devices and reuse it when the | |
557 | * device is re-plugged - not doing so would introduce a ton of races. | |
558 | */ | |
559 | } | |
560 | ||
561 | /**************************************************************************** | |
562 | * | |
563 | * Interrupt handling functions | |
564 | * | |
565 | ****************************************************************************/ | |
566 | ||
567 | static void dump_dte_entry(u16 devid) | |
568 | { | |
569 | int i; | |
570 | ||
571 | for (i = 0; i < 4; ++i) | |
572 | pr_err("AMD-Vi: DTE[%d]: %016llx\n", i, | |
573 | amd_iommu_dev_table[devid].data[i]); | |
574 | } | |
575 | ||
576 | static void dump_command(unsigned long phys_addr) | |
577 | { | |
578 | struct iommu_cmd *cmd = phys_to_virt(phys_addr); | |
579 | int i; | |
580 | ||
581 | for (i = 0; i < 4; ++i) | |
582 | pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]); | |
583 | } | |
584 | ||
585 | static void amd_iommu_report_page_fault(u16 devid, u16 domain_id, | |
586 | u64 address, int flags) | |
587 | { | |
588 | struct iommu_dev_data *dev_data = NULL; | |
589 | struct pci_dev *pdev; | |
590 | ||
591 | pdev = pci_get_bus_and_slot(PCI_BUS_NUM(devid), devid & 0xff); | |
592 | if (pdev) | |
593 | dev_data = get_dev_data(&pdev->dev); | |
594 | ||
595 | if (dev_data && __ratelimit(&dev_data->rs)) { | |
596 | dev_err(&pdev->dev, "AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
597 | domain_id, address, flags); | |
598 | } else if (printk_ratelimit()) { | |
599 | pr_err("AMD-Vi: Event logged [IO_PAGE_FAULT device=%02x:%02x.%x domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
600 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
601 | domain_id, address, flags); | |
602 | } | |
603 | ||
604 | if (pdev) | |
605 | pci_dev_put(pdev); | |
606 | } | |
607 | ||
608 | static void iommu_print_event(struct amd_iommu *iommu, void *__evt) | |
609 | { | |
610 | int type, devid, domid, flags; | |
611 | volatile u32 *event = __evt; | |
612 | int count = 0; | |
613 | u64 address; | |
614 | ||
615 | retry: | |
616 | type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
617 | devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
618 | domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
619 | flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
620 | address = (u64)(((u64)event[3]) << 32) | event[2]; | |
621 | ||
622 | if (type == 0) { | |
623 | /* Did we hit the erratum? */ | |
624 | if (++count == LOOP_TIMEOUT) { | |
625 | pr_err("AMD-Vi: No event written to event log\n"); | |
626 | return; | |
627 | } | |
628 | udelay(1); | |
629 | goto retry; | |
630 | } | |
631 | ||
632 | if (type == EVENT_TYPE_IO_FAULT) { | |
633 | amd_iommu_report_page_fault(devid, domid, address, flags); | |
634 | return; | |
635 | } else { | |
636 | printk(KERN_ERR "AMD-Vi: Event logged ["); | |
637 | } | |
638 | ||
639 | switch (type) { | |
640 | case EVENT_TYPE_ILL_DEV: | |
641 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
642 | "address=0x%016llx flags=0x%04x]\n", | |
643 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
644 | address, flags); | |
645 | dump_dte_entry(devid); | |
646 | break; | |
647 | case EVENT_TYPE_DEV_TAB_ERR: | |
648 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
649 | "address=0x%016llx flags=0x%04x]\n", | |
650 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
651 | address, flags); | |
652 | break; | |
653 | case EVENT_TYPE_PAGE_TAB_ERR: | |
654 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
655 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
656 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
657 | domid, address, flags); | |
658 | break; | |
659 | case EVENT_TYPE_ILL_CMD: | |
660 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
661 | dump_command(address); | |
662 | break; | |
663 | case EVENT_TYPE_CMD_HARD_ERR: | |
664 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
665 | "flags=0x%04x]\n", address, flags); | |
666 | break; | |
667 | case EVENT_TYPE_IOTLB_INV_TO: | |
668 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
669 | "address=0x%016llx]\n", | |
670 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
671 | address); | |
672 | break; | |
673 | case EVENT_TYPE_INV_DEV_REQ: | |
674 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
675 | "address=0x%016llx flags=0x%04x]\n", | |
676 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
677 | address, flags); | |
678 | break; | |
679 | default: | |
680 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
681 | } | |
682 | ||
683 | memset(__evt, 0, 4 * sizeof(u32)); | |
684 | } | |
685 | ||
686 | static void iommu_poll_events(struct amd_iommu *iommu) | |
687 | { | |
688 | u32 head, tail; | |
689 | ||
690 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
691 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
692 | ||
693 | while (head != tail) { | |
694 | iommu_print_event(iommu, iommu->evt_buf + head); | |
695 | head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE; | |
696 | } | |
697 | ||
698 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
699 | } | |
700 | ||
701 | static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw) | |
702 | { | |
703 | struct amd_iommu_fault fault; | |
704 | ||
705 | if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) { | |
706 | pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n"); | |
707 | return; | |
708 | } | |
709 | ||
710 | fault.address = raw[1]; | |
711 | fault.pasid = PPR_PASID(raw[0]); | |
712 | fault.device_id = PPR_DEVID(raw[0]); | |
713 | fault.tag = PPR_TAG(raw[0]); | |
714 | fault.flags = PPR_FLAGS(raw[0]); | |
715 | ||
716 | atomic_notifier_call_chain(&ppr_notifier, 0, &fault); | |
717 | } | |
718 | ||
719 | static void iommu_poll_ppr_log(struct amd_iommu *iommu) | |
720 | { | |
721 | u32 head, tail; | |
722 | ||
723 | if (iommu->ppr_log == NULL) | |
724 | return; | |
725 | ||
726 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
727 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); | |
728 | ||
729 | while (head != tail) { | |
730 | volatile u64 *raw; | |
731 | u64 entry[2]; | |
732 | int i; | |
733 | ||
734 | raw = (u64 *)(iommu->ppr_log + head); | |
735 | ||
736 | /* | |
737 | * Hardware bug: Interrupt may arrive before the entry is | |
738 | * written to memory. If this happens we need to wait for the | |
739 | * entry to arrive. | |
740 | */ | |
741 | for (i = 0; i < LOOP_TIMEOUT; ++i) { | |
742 | if (PPR_REQ_TYPE(raw[0]) != 0) | |
743 | break; | |
744 | udelay(1); | |
745 | } | |
746 | ||
747 | /* Avoid memcpy function-call overhead */ | |
748 | entry[0] = raw[0]; | |
749 | entry[1] = raw[1]; | |
750 | ||
751 | /* | |
752 | * To detect the hardware bug we need to clear the entry | |
753 | * back to zero. | |
754 | */ | |
755 | raw[0] = raw[1] = 0UL; | |
756 | ||
757 | /* Update head pointer of hardware ring-buffer */ | |
758 | head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE; | |
759 | writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
760 | ||
761 | /* Handle PPR entry */ | |
762 | iommu_handle_ppr_entry(iommu, entry); | |
763 | ||
764 | /* Refresh ring-buffer information */ | |
765 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
766 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); | |
767 | } | |
768 | } | |
769 | ||
770 | #ifdef CONFIG_IRQ_REMAP | |
771 | static int (*iommu_ga_log_notifier)(u32); | |
772 | ||
773 | int amd_iommu_register_ga_log_notifier(int (*notifier)(u32)) | |
774 | { | |
775 | iommu_ga_log_notifier = notifier; | |
776 | ||
777 | return 0; | |
778 | } | |
779 | EXPORT_SYMBOL(amd_iommu_register_ga_log_notifier); | |
780 | ||
781 | static void iommu_poll_ga_log(struct amd_iommu *iommu) | |
782 | { | |
783 | u32 head, tail, cnt = 0; | |
784 | ||
785 | if (iommu->ga_log == NULL) | |
786 | return; | |
787 | ||
788 | head = readl(iommu->mmio_base + MMIO_GA_HEAD_OFFSET); | |
789 | tail = readl(iommu->mmio_base + MMIO_GA_TAIL_OFFSET); | |
790 | ||
791 | while (head != tail) { | |
792 | volatile u64 *raw; | |
793 | u64 log_entry; | |
794 | ||
795 | raw = (u64 *)(iommu->ga_log + head); | |
796 | cnt++; | |
797 | ||
798 | /* Avoid memcpy function-call overhead */ | |
799 | log_entry = *raw; | |
800 | ||
801 | /* Update head pointer of hardware ring-buffer */ | |
802 | head = (head + GA_ENTRY_SIZE) % GA_LOG_SIZE; | |
803 | writel(head, iommu->mmio_base + MMIO_GA_HEAD_OFFSET); | |
804 | ||
805 | /* Handle GA entry */ | |
806 | switch (GA_REQ_TYPE(log_entry)) { | |
807 | case GA_GUEST_NR: | |
808 | if (!iommu_ga_log_notifier) | |
809 | break; | |
810 | ||
811 | pr_debug("AMD-Vi: %s: devid=%#x, ga_tag=%#x\n", | |
812 | __func__, GA_DEVID(log_entry), | |
813 | GA_TAG(log_entry)); | |
814 | ||
815 | if (iommu_ga_log_notifier(GA_TAG(log_entry)) != 0) | |
816 | pr_err("AMD-Vi: GA log notifier failed.\n"); | |
817 | break; | |
818 | default: | |
819 | break; | |
820 | } | |
821 | } | |
822 | } | |
823 | #endif /* CONFIG_IRQ_REMAP */ | |
824 | ||
825 | #define AMD_IOMMU_INT_MASK \ | |
826 | (MMIO_STATUS_EVT_INT_MASK | \ | |
827 | MMIO_STATUS_PPR_INT_MASK | \ | |
828 | MMIO_STATUS_GALOG_INT_MASK) | |
829 | ||
830 | irqreturn_t amd_iommu_int_thread(int irq, void *data) | |
831 | { | |
832 | struct amd_iommu *iommu = (struct amd_iommu *) data; | |
833 | u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
834 | ||
835 | while (status & AMD_IOMMU_INT_MASK) { | |
836 | /* Enable EVT and PPR and GA interrupts again */ | |
837 | writel(AMD_IOMMU_INT_MASK, | |
838 | iommu->mmio_base + MMIO_STATUS_OFFSET); | |
839 | ||
840 | if (status & MMIO_STATUS_EVT_INT_MASK) { | |
841 | pr_devel("AMD-Vi: Processing IOMMU Event Log\n"); | |
842 | iommu_poll_events(iommu); | |
843 | } | |
844 | ||
845 | if (status & MMIO_STATUS_PPR_INT_MASK) { | |
846 | pr_devel("AMD-Vi: Processing IOMMU PPR Log\n"); | |
847 | iommu_poll_ppr_log(iommu); | |
848 | } | |
849 | ||
850 | #ifdef CONFIG_IRQ_REMAP | |
851 | if (status & MMIO_STATUS_GALOG_INT_MASK) { | |
852 | pr_devel("AMD-Vi: Processing IOMMU GA Log\n"); | |
853 | iommu_poll_ga_log(iommu); | |
854 | } | |
855 | #endif | |
856 | ||
857 | /* | |
858 | * Hardware bug: ERBT1312 | |
859 | * When re-enabling interrupt (by writing 1 | |
860 | * to clear the bit), the hardware might also try to set | |
861 | * the interrupt bit in the event status register. | |
862 | * In this scenario, the bit will be set, and disable | |
863 | * subsequent interrupts. | |
864 | * | |
865 | * Workaround: The IOMMU driver should read back the | |
866 | * status register and check if the interrupt bits are cleared. | |
867 | * If not, driver will need to go through the interrupt handler | |
868 | * again and re-clear the bits | |
869 | */ | |
870 | status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
871 | } | |
872 | return IRQ_HANDLED; | |
873 | } | |
874 | ||
875 | irqreturn_t amd_iommu_int_handler(int irq, void *data) | |
876 | { | |
877 | return IRQ_WAKE_THREAD; | |
878 | } | |
879 | ||
880 | /**************************************************************************** | |
881 | * | |
882 | * IOMMU command queuing functions | |
883 | * | |
884 | ****************************************************************************/ | |
885 | ||
886 | static int wait_on_sem(volatile u64 *sem) | |
887 | { | |
888 | int i = 0; | |
889 | ||
890 | while (*sem == 0 && i < LOOP_TIMEOUT) { | |
891 | udelay(1); | |
892 | i += 1; | |
893 | } | |
894 | ||
895 | if (i == LOOP_TIMEOUT) { | |
896 | pr_alert("AMD-Vi: Completion-Wait loop timed out\n"); | |
897 | return -EIO; | |
898 | } | |
899 | ||
900 | return 0; | |
901 | } | |
902 | ||
903 | static void copy_cmd_to_buffer(struct amd_iommu *iommu, | |
904 | struct iommu_cmd *cmd) | |
905 | { | |
906 | u8 *target; | |
907 | ||
908 | target = iommu->cmd_buf + iommu->cmd_buf_tail; | |
909 | ||
910 | iommu->cmd_buf_tail += sizeof(*cmd); | |
911 | iommu->cmd_buf_tail %= CMD_BUFFER_SIZE; | |
912 | ||
913 | /* Copy command to buffer */ | |
914 | memcpy(target, cmd, sizeof(*cmd)); | |
915 | ||
916 | /* Tell the IOMMU about it */ | |
917 | writel(iommu->cmd_buf_tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
918 | } | |
919 | ||
920 | static void build_completion_wait(struct iommu_cmd *cmd, u64 address) | |
921 | { | |
922 | WARN_ON(address & 0x7ULL); | |
923 | ||
924 | memset(cmd, 0, sizeof(*cmd)); | |
925 | cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK; | |
926 | cmd->data[1] = upper_32_bits(__pa(address)); | |
927 | cmd->data[2] = 1; | |
928 | CMD_SET_TYPE(cmd, CMD_COMPL_WAIT); | |
929 | } | |
930 | ||
931 | static void build_inv_dte(struct iommu_cmd *cmd, u16 devid) | |
932 | { | |
933 | memset(cmd, 0, sizeof(*cmd)); | |
934 | cmd->data[0] = devid; | |
935 | CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY); | |
936 | } | |
937 | ||
938 | static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, | |
939 | size_t size, u16 domid, int pde) | |
940 | { | |
941 | u64 pages; | |
942 | bool s; | |
943 | ||
944 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
945 | s = false; | |
946 | ||
947 | if (pages > 1) { | |
948 | /* | |
949 | * If we have to flush more than one page, flush all | |
950 | * TLB entries for this domain | |
951 | */ | |
952 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
953 | s = true; | |
954 | } | |
955 | ||
956 | address &= PAGE_MASK; | |
957 | ||
958 | memset(cmd, 0, sizeof(*cmd)); | |
959 | cmd->data[1] |= domid; | |
960 | cmd->data[2] = lower_32_bits(address); | |
961 | cmd->data[3] = upper_32_bits(address); | |
962 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
963 | if (s) /* size bit - we flush more than one 4kb page */ | |
964 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
965 | if (pde) /* PDE bit - we want to flush everything, not only the PTEs */ | |
966 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
967 | } | |
968 | ||
969 | static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep, | |
970 | u64 address, size_t size) | |
971 | { | |
972 | u64 pages; | |
973 | bool s; | |
974 | ||
975 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
976 | s = false; | |
977 | ||
978 | if (pages > 1) { | |
979 | /* | |
980 | * If we have to flush more than one page, flush all | |
981 | * TLB entries for this domain | |
982 | */ | |
983 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
984 | s = true; | |
985 | } | |
986 | ||
987 | address &= PAGE_MASK; | |
988 | ||
989 | memset(cmd, 0, sizeof(*cmd)); | |
990 | cmd->data[0] = devid; | |
991 | cmd->data[0] |= (qdep & 0xff) << 24; | |
992 | cmd->data[1] = devid; | |
993 | cmd->data[2] = lower_32_bits(address); | |
994 | cmd->data[3] = upper_32_bits(address); | |
995 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
996 | if (s) | |
997 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
998 | } | |
999 | ||
1000 | static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid, | |
1001 | u64 address, bool size) | |
1002 | { | |
1003 | memset(cmd, 0, sizeof(*cmd)); | |
1004 | ||
1005 | address &= ~(0xfffULL); | |
1006 | ||
1007 | cmd->data[0] = pasid; | |
1008 | cmd->data[1] = domid; | |
1009 | cmd->data[2] = lower_32_bits(address); | |
1010 | cmd->data[3] = upper_32_bits(address); | |
1011 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
1012 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; | |
1013 | if (size) | |
1014 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
1015 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
1016 | } | |
1017 | ||
1018 | static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid, | |
1019 | int qdep, u64 address, bool size) | |
1020 | { | |
1021 | memset(cmd, 0, sizeof(*cmd)); | |
1022 | ||
1023 | address &= ~(0xfffULL); | |
1024 | ||
1025 | cmd->data[0] = devid; | |
1026 | cmd->data[0] |= ((pasid >> 8) & 0xff) << 16; | |
1027 | cmd->data[0] |= (qdep & 0xff) << 24; | |
1028 | cmd->data[1] = devid; | |
1029 | cmd->data[1] |= (pasid & 0xff) << 16; | |
1030 | cmd->data[2] = lower_32_bits(address); | |
1031 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; | |
1032 | cmd->data[3] = upper_32_bits(address); | |
1033 | if (size) | |
1034 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
1035 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
1036 | } | |
1037 | ||
1038 | static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid, | |
1039 | int status, int tag, bool gn) | |
1040 | { | |
1041 | memset(cmd, 0, sizeof(*cmd)); | |
1042 | ||
1043 | cmd->data[0] = devid; | |
1044 | if (gn) { | |
1045 | cmd->data[1] = pasid; | |
1046 | cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK; | |
1047 | } | |
1048 | cmd->data[3] = tag & 0x1ff; | |
1049 | cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT; | |
1050 | ||
1051 | CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR); | |
1052 | } | |
1053 | ||
1054 | static void build_inv_all(struct iommu_cmd *cmd) | |
1055 | { | |
1056 | memset(cmd, 0, sizeof(*cmd)); | |
1057 | CMD_SET_TYPE(cmd, CMD_INV_ALL); | |
1058 | } | |
1059 | ||
1060 | static void build_inv_irt(struct iommu_cmd *cmd, u16 devid) | |
1061 | { | |
1062 | memset(cmd, 0, sizeof(*cmd)); | |
1063 | cmd->data[0] = devid; | |
1064 | CMD_SET_TYPE(cmd, CMD_INV_IRT); | |
1065 | } | |
1066 | ||
1067 | /* | |
1068 | * Writes the command to the IOMMUs command buffer and informs the | |
1069 | * hardware about the new command. | |
1070 | */ | |
1071 | static int __iommu_queue_command_sync(struct amd_iommu *iommu, | |
1072 | struct iommu_cmd *cmd, | |
1073 | bool sync) | |
1074 | { | |
1075 | unsigned int count = 0; | |
1076 | u32 left, next_tail; | |
1077 | ||
1078 | next_tail = (iommu->cmd_buf_tail + sizeof(*cmd)) % CMD_BUFFER_SIZE; | |
1079 | again: | |
1080 | left = (iommu->cmd_buf_head - next_tail) % CMD_BUFFER_SIZE; | |
1081 | ||
1082 | if (left <= 0x20) { | |
1083 | /* Skip udelay() the first time around */ | |
1084 | if (count++) { | |
1085 | if (count == LOOP_TIMEOUT) { | |
1086 | pr_err("AMD-Vi: Command buffer timeout\n"); | |
1087 | return -EIO; | |
1088 | } | |
1089 | ||
1090 | udelay(1); | |
1091 | } | |
1092 | ||
1093 | /* Update head and recheck remaining space */ | |
1094 | iommu->cmd_buf_head = readl(iommu->mmio_base + | |
1095 | MMIO_CMD_HEAD_OFFSET); | |
1096 | ||
1097 | goto again; | |
1098 | } | |
1099 | ||
1100 | copy_cmd_to_buffer(iommu, cmd); | |
1101 | ||
1102 | /* Do we need to make sure all commands are processed? */ | |
1103 | iommu->need_sync = sync; | |
1104 | ||
1105 | return 0; | |
1106 | } | |
1107 | ||
1108 | static int iommu_queue_command_sync(struct amd_iommu *iommu, | |
1109 | struct iommu_cmd *cmd, | |
1110 | bool sync) | |
1111 | { | |
1112 | unsigned long flags; | |
1113 | int ret; | |
1114 | ||
1115 | spin_lock_irqsave(&iommu->lock, flags); | |
1116 | ret = __iommu_queue_command_sync(iommu, cmd, sync); | |
1117 | spin_unlock_irqrestore(&iommu->lock, flags); | |
1118 | ||
1119 | return ret; | |
1120 | } | |
1121 | ||
1122 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) | |
1123 | { | |
1124 | return iommu_queue_command_sync(iommu, cmd, true); | |
1125 | } | |
1126 | ||
1127 | /* | |
1128 | * This function queues a completion wait command into the command | |
1129 | * buffer of an IOMMU | |
1130 | */ | |
1131 | static int iommu_completion_wait(struct amd_iommu *iommu) | |
1132 | { | |
1133 | struct iommu_cmd cmd; | |
1134 | unsigned long flags; | |
1135 | int ret; | |
1136 | ||
1137 | if (!iommu->need_sync) | |
1138 | return 0; | |
1139 | ||
1140 | ||
1141 | build_completion_wait(&cmd, (u64)&iommu->cmd_sem); | |
1142 | ||
1143 | spin_lock_irqsave(&iommu->lock, flags); | |
1144 | ||
1145 | iommu->cmd_sem = 0; | |
1146 | ||
1147 | ret = __iommu_queue_command_sync(iommu, &cmd, false); | |
1148 | if (ret) | |
1149 | goto out_unlock; | |
1150 | ||
1151 | ret = wait_on_sem(&iommu->cmd_sem); | |
1152 | ||
1153 | out_unlock: | |
1154 | spin_unlock_irqrestore(&iommu->lock, flags); | |
1155 | ||
1156 | return ret; | |
1157 | } | |
1158 | ||
1159 | static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid) | |
1160 | { | |
1161 | struct iommu_cmd cmd; | |
1162 | ||
1163 | build_inv_dte(&cmd, devid); | |
1164 | ||
1165 | return iommu_queue_command(iommu, &cmd); | |
1166 | } | |
1167 | ||
1168 | static void iommu_flush_dte_all(struct amd_iommu *iommu) | |
1169 | { | |
1170 | u32 devid; | |
1171 | ||
1172 | for (devid = 0; devid <= 0xffff; ++devid) | |
1173 | iommu_flush_dte(iommu, devid); | |
1174 | ||
1175 | iommu_completion_wait(iommu); | |
1176 | } | |
1177 | ||
1178 | /* | |
1179 | * This function uses heavy locking and may disable irqs for some time. But | |
1180 | * this is no issue because it is only called during resume. | |
1181 | */ | |
1182 | static void iommu_flush_tlb_all(struct amd_iommu *iommu) | |
1183 | { | |
1184 | u32 dom_id; | |
1185 | ||
1186 | for (dom_id = 0; dom_id <= 0xffff; ++dom_id) { | |
1187 | struct iommu_cmd cmd; | |
1188 | build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
1189 | dom_id, 1); | |
1190 | iommu_queue_command(iommu, &cmd); | |
1191 | } | |
1192 | ||
1193 | iommu_completion_wait(iommu); | |
1194 | } | |
1195 | ||
1196 | static void iommu_flush_all(struct amd_iommu *iommu) | |
1197 | { | |
1198 | struct iommu_cmd cmd; | |
1199 | ||
1200 | build_inv_all(&cmd); | |
1201 | ||
1202 | iommu_queue_command(iommu, &cmd); | |
1203 | iommu_completion_wait(iommu); | |
1204 | } | |
1205 | ||
1206 | static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid) | |
1207 | { | |
1208 | struct iommu_cmd cmd; | |
1209 | ||
1210 | build_inv_irt(&cmd, devid); | |
1211 | ||
1212 | iommu_queue_command(iommu, &cmd); | |
1213 | } | |
1214 | ||
1215 | static void iommu_flush_irt_all(struct amd_iommu *iommu) | |
1216 | { | |
1217 | u32 devid; | |
1218 | ||
1219 | for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++) | |
1220 | iommu_flush_irt(iommu, devid); | |
1221 | ||
1222 | iommu_completion_wait(iommu); | |
1223 | } | |
1224 | ||
1225 | void iommu_flush_all_caches(struct amd_iommu *iommu) | |
1226 | { | |
1227 | if (iommu_feature(iommu, FEATURE_IA)) { | |
1228 | iommu_flush_all(iommu); | |
1229 | } else { | |
1230 | iommu_flush_dte_all(iommu); | |
1231 | iommu_flush_irt_all(iommu); | |
1232 | iommu_flush_tlb_all(iommu); | |
1233 | } | |
1234 | } | |
1235 | ||
1236 | /* | |
1237 | * Command send function for flushing on-device TLB | |
1238 | */ | |
1239 | static int device_flush_iotlb(struct iommu_dev_data *dev_data, | |
1240 | u64 address, size_t size) | |
1241 | { | |
1242 | struct amd_iommu *iommu; | |
1243 | struct iommu_cmd cmd; | |
1244 | int qdep; | |
1245 | ||
1246 | qdep = dev_data->ats.qdep; | |
1247 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
1248 | ||
1249 | build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size); | |
1250 | ||
1251 | return iommu_queue_command(iommu, &cmd); | |
1252 | } | |
1253 | ||
1254 | /* | |
1255 | * Command send function for invalidating a device table entry | |
1256 | */ | |
1257 | static int device_flush_dte(struct iommu_dev_data *dev_data) | |
1258 | { | |
1259 | struct amd_iommu *iommu; | |
1260 | u16 alias; | |
1261 | int ret; | |
1262 | ||
1263 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
1264 | alias = dev_data->alias; | |
1265 | ||
1266 | ret = iommu_flush_dte(iommu, dev_data->devid); | |
1267 | if (!ret && alias != dev_data->devid) | |
1268 | ret = iommu_flush_dte(iommu, alias); | |
1269 | if (ret) | |
1270 | return ret; | |
1271 | ||
1272 | if (dev_data->ats.enabled) | |
1273 | ret = device_flush_iotlb(dev_data, 0, ~0UL); | |
1274 | ||
1275 | return ret; | |
1276 | } | |
1277 | ||
1278 | /* | |
1279 | * TLB invalidation function which is called from the mapping functions. | |
1280 | * It invalidates a single PTE if the range to flush is within a single | |
1281 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
1282 | */ | |
1283 | static void __domain_flush_pages(struct protection_domain *domain, | |
1284 | u64 address, size_t size, int pde) | |
1285 | { | |
1286 | struct iommu_dev_data *dev_data; | |
1287 | struct iommu_cmd cmd; | |
1288 | int ret = 0, i; | |
1289 | ||
1290 | build_inv_iommu_pages(&cmd, address, size, domain->id, pde); | |
1291 | ||
1292 | for (i = 0; i < amd_iommu_get_num_iommus(); ++i) { | |
1293 | if (!domain->dev_iommu[i]) | |
1294 | continue; | |
1295 | ||
1296 | /* | |
1297 | * Devices of this domain are behind this IOMMU | |
1298 | * We need a TLB flush | |
1299 | */ | |
1300 | ret |= iommu_queue_command(amd_iommus[i], &cmd); | |
1301 | } | |
1302 | ||
1303 | list_for_each_entry(dev_data, &domain->dev_list, list) { | |
1304 | ||
1305 | if (!dev_data->ats.enabled) | |
1306 | continue; | |
1307 | ||
1308 | ret |= device_flush_iotlb(dev_data, address, size); | |
1309 | } | |
1310 | ||
1311 | WARN_ON(ret); | |
1312 | } | |
1313 | ||
1314 | static void domain_flush_pages(struct protection_domain *domain, | |
1315 | u64 address, size_t size) | |
1316 | { | |
1317 | __domain_flush_pages(domain, address, size, 0); | |
1318 | } | |
1319 | ||
1320 | /* Flush the whole IO/TLB for a given protection domain */ | |
1321 | static void domain_flush_tlb(struct protection_domain *domain) | |
1322 | { | |
1323 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0); | |
1324 | } | |
1325 | ||
1326 | /* Flush the whole IO/TLB for a given protection domain - including PDE */ | |
1327 | static void domain_flush_tlb_pde(struct protection_domain *domain) | |
1328 | { | |
1329 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1); | |
1330 | } | |
1331 | ||
1332 | static void domain_flush_complete(struct protection_domain *domain) | |
1333 | { | |
1334 | int i; | |
1335 | ||
1336 | for (i = 0; i < amd_iommu_get_num_iommus(); ++i) { | |
1337 | if (domain && !domain->dev_iommu[i]) | |
1338 | continue; | |
1339 | ||
1340 | /* | |
1341 | * Devices of this domain are behind this IOMMU | |
1342 | * We need to wait for completion of all commands. | |
1343 | */ | |
1344 | iommu_completion_wait(amd_iommus[i]); | |
1345 | } | |
1346 | } | |
1347 | ||
1348 | ||
1349 | /* | |
1350 | * This function flushes the DTEs for all devices in domain | |
1351 | */ | |
1352 | static void domain_flush_devices(struct protection_domain *domain) | |
1353 | { | |
1354 | struct iommu_dev_data *dev_data; | |
1355 | ||
1356 | list_for_each_entry(dev_data, &domain->dev_list, list) | |
1357 | device_flush_dte(dev_data); | |
1358 | } | |
1359 | ||
1360 | /**************************************************************************** | |
1361 | * | |
1362 | * The functions below are used the create the page table mappings for | |
1363 | * unity mapped regions. | |
1364 | * | |
1365 | ****************************************************************************/ | |
1366 | ||
1367 | /* | |
1368 | * This function is used to add another level to an IO page table. Adding | |
1369 | * another level increases the size of the address space by 9 bits to a size up | |
1370 | * to 64 bits. | |
1371 | */ | |
1372 | static bool increase_address_space(struct protection_domain *domain, | |
1373 | gfp_t gfp) | |
1374 | { | |
1375 | u64 *pte; | |
1376 | ||
1377 | if (domain->mode == PAGE_MODE_6_LEVEL) | |
1378 | /* address space already 64 bit large */ | |
1379 | return false; | |
1380 | ||
1381 | pte = (void *)get_zeroed_page(gfp); | |
1382 | if (!pte) | |
1383 | return false; | |
1384 | ||
1385 | *pte = PM_LEVEL_PDE(domain->mode, | |
1386 | virt_to_phys(domain->pt_root)); | |
1387 | domain->pt_root = pte; | |
1388 | domain->mode += 1; | |
1389 | domain->updated = true; | |
1390 | ||
1391 | return true; | |
1392 | } | |
1393 | ||
1394 | static u64 *alloc_pte(struct protection_domain *domain, | |
1395 | unsigned long address, | |
1396 | unsigned long page_size, | |
1397 | u64 **pte_page, | |
1398 | gfp_t gfp) | |
1399 | { | |
1400 | int level, end_lvl; | |
1401 | u64 *pte, *page; | |
1402 | ||
1403 | BUG_ON(!is_power_of_2(page_size)); | |
1404 | ||
1405 | while (address > PM_LEVEL_SIZE(domain->mode)) | |
1406 | increase_address_space(domain, gfp); | |
1407 | ||
1408 | level = domain->mode - 1; | |
1409 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
1410 | address = PAGE_SIZE_ALIGN(address, page_size); | |
1411 | end_lvl = PAGE_SIZE_LEVEL(page_size); | |
1412 | ||
1413 | while (level > end_lvl) { | |
1414 | u64 __pte, __npte; | |
1415 | ||
1416 | __pte = *pte; | |
1417 | ||
1418 | if (!IOMMU_PTE_PRESENT(__pte)) { | |
1419 | page = (u64 *)get_zeroed_page(gfp); | |
1420 | if (!page) | |
1421 | return NULL; | |
1422 | ||
1423 | __npte = PM_LEVEL_PDE(level, virt_to_phys(page)); | |
1424 | ||
1425 | /* pte could have been changed somewhere. */ | |
1426 | if (cmpxchg64(pte, __pte, __npte) != __pte) { | |
1427 | free_page((unsigned long)page); | |
1428 | continue; | |
1429 | } | |
1430 | } | |
1431 | ||
1432 | /* No level skipping support yet */ | |
1433 | if (PM_PTE_LEVEL(*pte) != level) | |
1434 | return NULL; | |
1435 | ||
1436 | level -= 1; | |
1437 | ||
1438 | pte = IOMMU_PTE_PAGE(*pte); | |
1439 | ||
1440 | if (pte_page && level == end_lvl) | |
1441 | *pte_page = pte; | |
1442 | ||
1443 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
1444 | } | |
1445 | ||
1446 | return pte; | |
1447 | } | |
1448 | ||
1449 | /* | |
1450 | * This function checks if there is a PTE for a given dma address. If | |
1451 | * there is one, it returns the pointer to it. | |
1452 | */ | |
1453 | static u64 *fetch_pte(struct protection_domain *domain, | |
1454 | unsigned long address, | |
1455 | unsigned long *page_size) | |
1456 | { | |
1457 | int level; | |
1458 | u64 *pte; | |
1459 | ||
1460 | if (address > PM_LEVEL_SIZE(domain->mode)) | |
1461 | return NULL; | |
1462 | ||
1463 | level = domain->mode - 1; | |
1464 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
1465 | *page_size = PTE_LEVEL_PAGE_SIZE(level); | |
1466 | ||
1467 | while (level > 0) { | |
1468 | ||
1469 | /* Not Present */ | |
1470 | if (!IOMMU_PTE_PRESENT(*pte)) | |
1471 | return NULL; | |
1472 | ||
1473 | /* Large PTE */ | |
1474 | if (PM_PTE_LEVEL(*pte) == 7 || | |
1475 | PM_PTE_LEVEL(*pte) == 0) | |
1476 | break; | |
1477 | ||
1478 | /* No level skipping support yet */ | |
1479 | if (PM_PTE_LEVEL(*pte) != level) | |
1480 | return NULL; | |
1481 | ||
1482 | level -= 1; | |
1483 | ||
1484 | /* Walk to the next level */ | |
1485 | pte = IOMMU_PTE_PAGE(*pte); | |
1486 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
1487 | *page_size = PTE_LEVEL_PAGE_SIZE(level); | |
1488 | } | |
1489 | ||
1490 | if (PM_PTE_LEVEL(*pte) == 0x07) { | |
1491 | unsigned long pte_mask; | |
1492 | ||
1493 | /* | |
1494 | * If we have a series of large PTEs, make | |
1495 | * sure to return a pointer to the first one. | |
1496 | */ | |
1497 | *page_size = pte_mask = PTE_PAGE_SIZE(*pte); | |
1498 | pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1); | |
1499 | pte = (u64 *)(((unsigned long)pte) & pte_mask); | |
1500 | } | |
1501 | ||
1502 | return pte; | |
1503 | } | |
1504 | ||
1505 | /* | |
1506 | * Generic mapping functions. It maps a physical address into a DMA | |
1507 | * address space. It allocates the page table pages if necessary. | |
1508 | * In the future it can be extended to a generic mapping function | |
1509 | * supporting all features of AMD IOMMU page tables like level skipping | |
1510 | * and full 64 bit address spaces. | |
1511 | */ | |
1512 | static int iommu_map_page(struct protection_domain *dom, | |
1513 | unsigned long bus_addr, | |
1514 | unsigned long phys_addr, | |
1515 | unsigned long page_size, | |
1516 | int prot, | |
1517 | gfp_t gfp) | |
1518 | { | |
1519 | u64 __pte, *pte; | |
1520 | int i, count; | |
1521 | ||
1522 | BUG_ON(!IS_ALIGNED(bus_addr, page_size)); | |
1523 | BUG_ON(!IS_ALIGNED(phys_addr, page_size)); | |
1524 | ||
1525 | if (!(prot & IOMMU_PROT_MASK)) | |
1526 | return -EINVAL; | |
1527 | ||
1528 | count = PAGE_SIZE_PTE_COUNT(page_size); | |
1529 | pte = alloc_pte(dom, bus_addr, page_size, NULL, gfp); | |
1530 | ||
1531 | if (!pte) | |
1532 | return -ENOMEM; | |
1533 | ||
1534 | for (i = 0; i < count; ++i) | |
1535 | if (IOMMU_PTE_PRESENT(pte[i])) | |
1536 | return -EBUSY; | |
1537 | ||
1538 | if (count > 1) { | |
1539 | __pte = PAGE_SIZE_PTE(phys_addr, page_size); | |
1540 | __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1541 | } else | |
1542 | __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1543 | ||
1544 | if (prot & IOMMU_PROT_IR) | |
1545 | __pte |= IOMMU_PTE_IR; | |
1546 | if (prot & IOMMU_PROT_IW) | |
1547 | __pte |= IOMMU_PTE_IW; | |
1548 | ||
1549 | for (i = 0; i < count; ++i) | |
1550 | pte[i] = __pte; | |
1551 | ||
1552 | update_domain(dom); | |
1553 | ||
1554 | return 0; | |
1555 | } | |
1556 | ||
1557 | static unsigned long iommu_unmap_page(struct protection_domain *dom, | |
1558 | unsigned long bus_addr, | |
1559 | unsigned long page_size) | |
1560 | { | |
1561 | unsigned long long unmapped; | |
1562 | unsigned long unmap_size; | |
1563 | u64 *pte; | |
1564 | ||
1565 | BUG_ON(!is_power_of_2(page_size)); | |
1566 | ||
1567 | unmapped = 0; | |
1568 | ||
1569 | while (unmapped < page_size) { | |
1570 | ||
1571 | pte = fetch_pte(dom, bus_addr, &unmap_size); | |
1572 | ||
1573 | if (pte) { | |
1574 | int i, count; | |
1575 | ||
1576 | count = PAGE_SIZE_PTE_COUNT(unmap_size); | |
1577 | for (i = 0; i < count; i++) | |
1578 | pte[i] = 0ULL; | |
1579 | } | |
1580 | ||
1581 | bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size; | |
1582 | unmapped += unmap_size; | |
1583 | } | |
1584 | ||
1585 | BUG_ON(unmapped && !is_power_of_2(unmapped)); | |
1586 | ||
1587 | return unmapped; | |
1588 | } | |
1589 | ||
1590 | /**************************************************************************** | |
1591 | * | |
1592 | * The next functions belong to the address allocator for the dma_ops | |
1593 | * interface functions. | |
1594 | * | |
1595 | ****************************************************************************/ | |
1596 | ||
1597 | ||
1598 | static unsigned long dma_ops_alloc_iova(struct device *dev, | |
1599 | struct dma_ops_domain *dma_dom, | |
1600 | unsigned int pages, u64 dma_mask) | |
1601 | { | |
1602 | unsigned long pfn = 0; | |
1603 | ||
1604 | pages = __roundup_pow_of_two(pages); | |
1605 | ||
1606 | if (dma_mask > DMA_BIT_MASK(32)) | |
1607 | pfn = alloc_iova_fast(&dma_dom->iovad, pages, | |
1608 | IOVA_PFN(DMA_BIT_MASK(32))); | |
1609 | ||
1610 | if (!pfn) | |
1611 | pfn = alloc_iova_fast(&dma_dom->iovad, pages, IOVA_PFN(dma_mask)); | |
1612 | ||
1613 | return (pfn << PAGE_SHIFT); | |
1614 | } | |
1615 | ||
1616 | static void dma_ops_free_iova(struct dma_ops_domain *dma_dom, | |
1617 | unsigned long address, | |
1618 | unsigned int pages) | |
1619 | { | |
1620 | pages = __roundup_pow_of_two(pages); | |
1621 | address >>= PAGE_SHIFT; | |
1622 | ||
1623 | free_iova_fast(&dma_dom->iovad, address, pages); | |
1624 | } | |
1625 | ||
1626 | /**************************************************************************** | |
1627 | * | |
1628 | * The next functions belong to the domain allocation. A domain is | |
1629 | * allocated for every IOMMU as the default domain. If device isolation | |
1630 | * is enabled, every device get its own domain. The most important thing | |
1631 | * about domains is the page table mapping the DMA address space they | |
1632 | * contain. | |
1633 | * | |
1634 | ****************************************************************************/ | |
1635 | ||
1636 | /* | |
1637 | * This function adds a protection domain to the global protection domain list | |
1638 | */ | |
1639 | static void add_domain_to_list(struct protection_domain *domain) | |
1640 | { | |
1641 | unsigned long flags; | |
1642 | ||
1643 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1644 | list_add(&domain->list, &amd_iommu_pd_list); | |
1645 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1646 | } | |
1647 | ||
1648 | /* | |
1649 | * This function removes a protection domain to the global | |
1650 | * protection domain list | |
1651 | */ | |
1652 | static void del_domain_from_list(struct protection_domain *domain) | |
1653 | { | |
1654 | unsigned long flags; | |
1655 | ||
1656 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1657 | list_del(&domain->list); | |
1658 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1659 | } | |
1660 | ||
1661 | static u16 domain_id_alloc(void) | |
1662 | { | |
1663 | unsigned long flags; | |
1664 | int id; | |
1665 | ||
1666 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1667 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
1668 | BUG_ON(id == 0); | |
1669 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1670 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
1671 | else | |
1672 | id = 0; | |
1673 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1674 | ||
1675 | return id; | |
1676 | } | |
1677 | ||
1678 | static void domain_id_free(int id) | |
1679 | { | |
1680 | unsigned long flags; | |
1681 | ||
1682 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1683 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1684 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
1685 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1686 | } | |
1687 | ||
1688 | #define DEFINE_FREE_PT_FN(LVL, FN) \ | |
1689 | static void free_pt_##LVL (unsigned long __pt) \ | |
1690 | { \ | |
1691 | unsigned long p; \ | |
1692 | u64 *pt; \ | |
1693 | int i; \ | |
1694 | \ | |
1695 | pt = (u64 *)__pt; \ | |
1696 | \ | |
1697 | for (i = 0; i < 512; ++i) { \ | |
1698 | /* PTE present? */ \ | |
1699 | if (!IOMMU_PTE_PRESENT(pt[i])) \ | |
1700 | continue; \ | |
1701 | \ | |
1702 | /* Large PTE? */ \ | |
1703 | if (PM_PTE_LEVEL(pt[i]) == 0 || \ | |
1704 | PM_PTE_LEVEL(pt[i]) == 7) \ | |
1705 | continue; \ | |
1706 | \ | |
1707 | p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \ | |
1708 | FN(p); \ | |
1709 | } \ | |
1710 | free_page((unsigned long)pt); \ | |
1711 | } | |
1712 | ||
1713 | DEFINE_FREE_PT_FN(l2, free_page) | |
1714 | DEFINE_FREE_PT_FN(l3, free_pt_l2) | |
1715 | DEFINE_FREE_PT_FN(l4, free_pt_l3) | |
1716 | DEFINE_FREE_PT_FN(l5, free_pt_l4) | |
1717 | DEFINE_FREE_PT_FN(l6, free_pt_l5) | |
1718 | ||
1719 | static void free_pagetable(struct protection_domain *domain) | |
1720 | { | |
1721 | unsigned long root = (unsigned long)domain->pt_root; | |
1722 | ||
1723 | switch (domain->mode) { | |
1724 | case PAGE_MODE_NONE: | |
1725 | break; | |
1726 | case PAGE_MODE_1_LEVEL: | |
1727 | free_page(root); | |
1728 | break; | |
1729 | case PAGE_MODE_2_LEVEL: | |
1730 | free_pt_l2(root); | |
1731 | break; | |
1732 | case PAGE_MODE_3_LEVEL: | |
1733 | free_pt_l3(root); | |
1734 | break; | |
1735 | case PAGE_MODE_4_LEVEL: | |
1736 | free_pt_l4(root); | |
1737 | break; | |
1738 | case PAGE_MODE_5_LEVEL: | |
1739 | free_pt_l5(root); | |
1740 | break; | |
1741 | case PAGE_MODE_6_LEVEL: | |
1742 | free_pt_l6(root); | |
1743 | break; | |
1744 | default: | |
1745 | BUG(); | |
1746 | } | |
1747 | } | |
1748 | ||
1749 | static void free_gcr3_tbl_level1(u64 *tbl) | |
1750 | { | |
1751 | u64 *ptr; | |
1752 | int i; | |
1753 | ||
1754 | for (i = 0; i < 512; ++i) { | |
1755 | if (!(tbl[i] & GCR3_VALID)) | |
1756 | continue; | |
1757 | ||
1758 | ptr = __va(tbl[i] & PAGE_MASK); | |
1759 | ||
1760 | free_page((unsigned long)ptr); | |
1761 | } | |
1762 | } | |
1763 | ||
1764 | static void free_gcr3_tbl_level2(u64 *tbl) | |
1765 | { | |
1766 | u64 *ptr; | |
1767 | int i; | |
1768 | ||
1769 | for (i = 0; i < 512; ++i) { | |
1770 | if (!(tbl[i] & GCR3_VALID)) | |
1771 | continue; | |
1772 | ||
1773 | ptr = __va(tbl[i] & PAGE_MASK); | |
1774 | ||
1775 | free_gcr3_tbl_level1(ptr); | |
1776 | } | |
1777 | } | |
1778 | ||
1779 | static void free_gcr3_table(struct protection_domain *domain) | |
1780 | { | |
1781 | if (domain->glx == 2) | |
1782 | free_gcr3_tbl_level2(domain->gcr3_tbl); | |
1783 | else if (domain->glx == 1) | |
1784 | free_gcr3_tbl_level1(domain->gcr3_tbl); | |
1785 | else | |
1786 | BUG_ON(domain->glx != 0); | |
1787 | ||
1788 | free_page((unsigned long)domain->gcr3_tbl); | |
1789 | } | |
1790 | ||
1791 | static void dma_ops_domain_free_flush_queue(struct dma_ops_domain *dom) | |
1792 | { | |
1793 | int cpu; | |
1794 | ||
1795 | for_each_possible_cpu(cpu) { | |
1796 | struct flush_queue *queue; | |
1797 | ||
1798 | queue = per_cpu_ptr(dom->flush_queue, cpu); | |
1799 | kfree(queue->entries); | |
1800 | } | |
1801 | ||
1802 | free_percpu(dom->flush_queue); | |
1803 | ||
1804 | dom->flush_queue = NULL; | |
1805 | } | |
1806 | ||
1807 | static int dma_ops_domain_alloc_flush_queue(struct dma_ops_domain *dom) | |
1808 | { | |
1809 | int cpu; | |
1810 | ||
1811 | atomic64_set(&dom->flush_start_cnt, 0); | |
1812 | atomic64_set(&dom->flush_finish_cnt, 0); | |
1813 | ||
1814 | dom->flush_queue = alloc_percpu(struct flush_queue); | |
1815 | if (!dom->flush_queue) | |
1816 | return -ENOMEM; | |
1817 | ||
1818 | /* First make sure everything is cleared */ | |
1819 | for_each_possible_cpu(cpu) { | |
1820 | struct flush_queue *queue; | |
1821 | ||
1822 | queue = per_cpu_ptr(dom->flush_queue, cpu); | |
1823 | queue->head = 0; | |
1824 | queue->tail = 0; | |
1825 | queue->entries = NULL; | |
1826 | } | |
1827 | ||
1828 | /* Now start doing the allocation */ | |
1829 | for_each_possible_cpu(cpu) { | |
1830 | struct flush_queue *queue; | |
1831 | ||
1832 | queue = per_cpu_ptr(dom->flush_queue, cpu); | |
1833 | queue->entries = kzalloc(FLUSH_QUEUE_SIZE * sizeof(*queue->entries), | |
1834 | GFP_KERNEL); | |
1835 | if (!queue->entries) { | |
1836 | dma_ops_domain_free_flush_queue(dom); | |
1837 | return -ENOMEM; | |
1838 | } | |
1839 | ||
1840 | spin_lock_init(&queue->lock); | |
1841 | } | |
1842 | ||
1843 | return 0; | |
1844 | } | |
1845 | ||
1846 | static void dma_ops_domain_flush_tlb(struct dma_ops_domain *dom) | |
1847 | { | |
1848 | atomic64_inc(&dom->flush_start_cnt); | |
1849 | domain_flush_tlb(&dom->domain); | |
1850 | domain_flush_complete(&dom->domain); | |
1851 | atomic64_inc(&dom->flush_finish_cnt); | |
1852 | } | |
1853 | ||
1854 | static inline bool queue_ring_full(struct flush_queue *queue) | |
1855 | { | |
1856 | assert_spin_locked(&queue->lock); | |
1857 | ||
1858 | return (((queue->tail + 1) % FLUSH_QUEUE_SIZE) == queue->head); | |
1859 | } | |
1860 | ||
1861 | #define queue_ring_for_each(i, q) \ | |
1862 | for (i = (q)->head; i != (q)->tail; i = (i + 1) % FLUSH_QUEUE_SIZE) | |
1863 | ||
1864 | static inline unsigned queue_ring_add(struct flush_queue *queue) | |
1865 | { | |
1866 | unsigned idx = queue->tail; | |
1867 | ||
1868 | assert_spin_locked(&queue->lock); | |
1869 | queue->tail = (idx + 1) % FLUSH_QUEUE_SIZE; | |
1870 | ||
1871 | return idx; | |
1872 | } | |
1873 | ||
1874 | static inline void queue_ring_remove_head(struct flush_queue *queue) | |
1875 | { | |
1876 | assert_spin_locked(&queue->lock); | |
1877 | queue->head = (queue->head + 1) % FLUSH_QUEUE_SIZE; | |
1878 | } | |
1879 | ||
1880 | static void queue_ring_free_flushed(struct dma_ops_domain *dom, | |
1881 | struct flush_queue *queue) | |
1882 | { | |
1883 | u64 counter = atomic64_read(&dom->flush_finish_cnt); | |
1884 | int idx; | |
1885 | ||
1886 | queue_ring_for_each(idx, queue) { | |
1887 | /* | |
1888 | * This assumes that counter values in the ring-buffer are | |
1889 | * monotonously rising. | |
1890 | */ | |
1891 | if (queue->entries[idx].counter >= counter) | |
1892 | break; | |
1893 | ||
1894 | free_iova_fast(&dom->iovad, | |
1895 | queue->entries[idx].iova_pfn, | |
1896 | queue->entries[idx].pages); | |
1897 | ||
1898 | queue_ring_remove_head(queue); | |
1899 | } | |
1900 | } | |
1901 | ||
1902 | static void queue_add(struct dma_ops_domain *dom, | |
1903 | unsigned long address, unsigned long pages) | |
1904 | { | |
1905 | struct flush_queue *queue; | |
1906 | unsigned long flags; | |
1907 | int idx; | |
1908 | ||
1909 | pages = __roundup_pow_of_two(pages); | |
1910 | address >>= PAGE_SHIFT; | |
1911 | ||
1912 | queue = get_cpu_ptr(dom->flush_queue); | |
1913 | spin_lock_irqsave(&queue->lock, flags); | |
1914 | ||
1915 | /* | |
1916 | * First remove the enries from the ring-buffer that are already | |
1917 | * flushed to make the below queue_ring_full() check less likely | |
1918 | */ | |
1919 | queue_ring_free_flushed(dom, queue); | |
1920 | ||
1921 | /* | |
1922 | * When ring-queue is full, flush the entries from the IOTLB so | |
1923 | * that we can free all entries with queue_ring_free_flushed() | |
1924 | * below. | |
1925 | */ | |
1926 | if (queue_ring_full(queue)) { | |
1927 | dma_ops_domain_flush_tlb(dom); | |
1928 | queue_ring_free_flushed(dom, queue); | |
1929 | } | |
1930 | ||
1931 | idx = queue_ring_add(queue); | |
1932 | ||
1933 | queue->entries[idx].iova_pfn = address; | |
1934 | queue->entries[idx].pages = pages; | |
1935 | queue->entries[idx].counter = atomic64_read(&dom->flush_start_cnt); | |
1936 | ||
1937 | spin_unlock_irqrestore(&queue->lock, flags); | |
1938 | ||
1939 | if (atomic_cmpxchg(&dom->flush_timer_on, 0, 1) == 0) | |
1940 | mod_timer(&dom->flush_timer, jiffies + msecs_to_jiffies(10)); | |
1941 | ||
1942 | put_cpu_ptr(dom->flush_queue); | |
1943 | } | |
1944 | ||
1945 | static void queue_flush_timeout(unsigned long data) | |
1946 | { | |
1947 | struct dma_ops_domain *dom = (struct dma_ops_domain *)data; | |
1948 | int cpu; | |
1949 | ||
1950 | atomic_set(&dom->flush_timer_on, 0); | |
1951 | ||
1952 | dma_ops_domain_flush_tlb(dom); | |
1953 | ||
1954 | for_each_possible_cpu(cpu) { | |
1955 | struct flush_queue *queue; | |
1956 | unsigned long flags; | |
1957 | ||
1958 | queue = per_cpu_ptr(dom->flush_queue, cpu); | |
1959 | spin_lock_irqsave(&queue->lock, flags); | |
1960 | queue_ring_free_flushed(dom, queue); | |
1961 | spin_unlock_irqrestore(&queue->lock, flags); | |
1962 | } | |
1963 | } | |
1964 | ||
1965 | /* | |
1966 | * Free a domain, only used if something went wrong in the | |
1967 | * allocation path and we need to free an already allocated page table | |
1968 | */ | |
1969 | static void dma_ops_domain_free(struct dma_ops_domain *dom) | |
1970 | { | |
1971 | if (!dom) | |
1972 | return; | |
1973 | ||
1974 | del_domain_from_list(&dom->domain); | |
1975 | ||
1976 | if (timer_pending(&dom->flush_timer)) | |
1977 | del_timer(&dom->flush_timer); | |
1978 | ||
1979 | dma_ops_domain_free_flush_queue(dom); | |
1980 | ||
1981 | put_iova_domain(&dom->iovad); | |
1982 | ||
1983 | free_pagetable(&dom->domain); | |
1984 | ||
1985 | if (dom->domain.id) | |
1986 | domain_id_free(dom->domain.id); | |
1987 | ||
1988 | kfree(dom); | |
1989 | } | |
1990 | ||
1991 | /* | |
1992 | * Allocates a new protection domain usable for the dma_ops functions. | |
1993 | * It also initializes the page table and the address allocator data | |
1994 | * structures required for the dma_ops interface | |
1995 | */ | |
1996 | static struct dma_ops_domain *dma_ops_domain_alloc(void) | |
1997 | { | |
1998 | struct dma_ops_domain *dma_dom; | |
1999 | ||
2000 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
2001 | if (!dma_dom) | |
2002 | return NULL; | |
2003 | ||
2004 | if (protection_domain_init(&dma_dom->domain)) | |
2005 | goto free_dma_dom; | |
2006 | ||
2007 | dma_dom->domain.mode = PAGE_MODE_3_LEVEL; | |
2008 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
2009 | dma_dom->domain.flags = PD_DMA_OPS_MASK; | |
2010 | if (!dma_dom->domain.pt_root) | |
2011 | goto free_dma_dom; | |
2012 | ||
2013 | init_iova_domain(&dma_dom->iovad, PAGE_SIZE, | |
2014 | IOVA_START_PFN, DMA_32BIT_PFN); | |
2015 | ||
2016 | /* Initialize reserved ranges */ | |
2017 | copy_reserved_iova(&reserved_iova_ranges, &dma_dom->iovad); | |
2018 | ||
2019 | if (dma_ops_domain_alloc_flush_queue(dma_dom)) | |
2020 | goto free_dma_dom; | |
2021 | ||
2022 | setup_timer(&dma_dom->flush_timer, queue_flush_timeout, | |
2023 | (unsigned long)dma_dom); | |
2024 | ||
2025 | atomic_set(&dma_dom->flush_timer_on, 0); | |
2026 | ||
2027 | add_domain_to_list(&dma_dom->domain); | |
2028 | ||
2029 | return dma_dom; | |
2030 | ||
2031 | free_dma_dom: | |
2032 | dma_ops_domain_free(dma_dom); | |
2033 | ||
2034 | return NULL; | |
2035 | } | |
2036 | ||
2037 | /* | |
2038 | * little helper function to check whether a given protection domain is a | |
2039 | * dma_ops domain | |
2040 | */ | |
2041 | static bool dma_ops_domain(struct protection_domain *domain) | |
2042 | { | |
2043 | return domain->flags & PD_DMA_OPS_MASK; | |
2044 | } | |
2045 | ||
2046 | static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats) | |
2047 | { | |
2048 | u64 pte_root = 0; | |
2049 | u64 flags = 0; | |
2050 | ||
2051 | if (domain->mode != PAGE_MODE_NONE) | |
2052 | pte_root = virt_to_phys(domain->pt_root); | |
2053 | ||
2054 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) | |
2055 | << DEV_ENTRY_MODE_SHIFT; | |
2056 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
2057 | ||
2058 | flags = amd_iommu_dev_table[devid].data[1]; | |
2059 | ||
2060 | if (ats) | |
2061 | flags |= DTE_FLAG_IOTLB; | |
2062 | ||
2063 | if (domain->flags & PD_IOMMUV2_MASK) { | |
2064 | u64 gcr3 = __pa(domain->gcr3_tbl); | |
2065 | u64 glx = domain->glx; | |
2066 | u64 tmp; | |
2067 | ||
2068 | pte_root |= DTE_FLAG_GV; | |
2069 | pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT; | |
2070 | ||
2071 | /* First mask out possible old values for GCR3 table */ | |
2072 | tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B; | |
2073 | flags &= ~tmp; | |
2074 | ||
2075 | tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C; | |
2076 | flags &= ~tmp; | |
2077 | ||
2078 | /* Encode GCR3 table into DTE */ | |
2079 | tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A; | |
2080 | pte_root |= tmp; | |
2081 | ||
2082 | tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B; | |
2083 | flags |= tmp; | |
2084 | ||
2085 | tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C; | |
2086 | flags |= tmp; | |
2087 | } | |
2088 | ||
2089 | ||
2090 | flags &= ~(DTE_FLAG_SA | 0xffffULL); | |
2091 | flags |= domain->id; | |
2092 | ||
2093 | amd_iommu_dev_table[devid].data[1] = flags; | |
2094 | amd_iommu_dev_table[devid].data[0] = pte_root; | |
2095 | } | |
2096 | ||
2097 | static void clear_dte_entry(u16 devid) | |
2098 | { | |
2099 | /* remove entry from the device table seen by the hardware */ | |
2100 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; | |
2101 | amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK; | |
2102 | ||
2103 | amd_iommu_apply_erratum_63(devid); | |
2104 | } | |
2105 | ||
2106 | static void do_attach(struct iommu_dev_data *dev_data, | |
2107 | struct protection_domain *domain) | |
2108 | { | |
2109 | struct amd_iommu *iommu; | |
2110 | u16 alias; | |
2111 | bool ats; | |
2112 | ||
2113 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
2114 | alias = dev_data->alias; | |
2115 | ats = dev_data->ats.enabled; | |
2116 | ||
2117 | /* Update data structures */ | |
2118 | dev_data->domain = domain; | |
2119 | list_add(&dev_data->list, &domain->dev_list); | |
2120 | ||
2121 | /* Do reference counting */ | |
2122 | domain->dev_iommu[iommu->index] += 1; | |
2123 | domain->dev_cnt += 1; | |
2124 | ||
2125 | /* Update device table */ | |
2126 | set_dte_entry(dev_data->devid, domain, ats); | |
2127 | if (alias != dev_data->devid) | |
2128 | set_dte_entry(alias, domain, ats); | |
2129 | ||
2130 | device_flush_dte(dev_data); | |
2131 | } | |
2132 | ||
2133 | static void do_detach(struct iommu_dev_data *dev_data) | |
2134 | { | |
2135 | struct amd_iommu *iommu; | |
2136 | u16 alias; | |
2137 | ||
2138 | /* | |
2139 | * First check if the device is still attached. It might already | |
2140 | * be detached from its domain because the generic | |
2141 | * iommu_detach_group code detached it and we try again here in | |
2142 | * our alias handling. | |
2143 | */ | |
2144 | if (!dev_data->domain) | |
2145 | return; | |
2146 | ||
2147 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
2148 | alias = dev_data->alias; | |
2149 | ||
2150 | /* decrease reference counters */ | |
2151 | dev_data->domain->dev_iommu[iommu->index] -= 1; | |
2152 | dev_data->domain->dev_cnt -= 1; | |
2153 | ||
2154 | /* Update data structures */ | |
2155 | dev_data->domain = NULL; | |
2156 | list_del(&dev_data->list); | |
2157 | clear_dte_entry(dev_data->devid); | |
2158 | if (alias != dev_data->devid) | |
2159 | clear_dte_entry(alias); | |
2160 | ||
2161 | /* Flush the DTE entry */ | |
2162 | device_flush_dte(dev_data); | |
2163 | } | |
2164 | ||
2165 | /* | |
2166 | * If a device is not yet associated with a domain, this function does | |
2167 | * assigns it visible for the hardware | |
2168 | */ | |
2169 | static int __attach_device(struct iommu_dev_data *dev_data, | |
2170 | struct protection_domain *domain) | |
2171 | { | |
2172 | int ret; | |
2173 | ||
2174 | /* | |
2175 | * Must be called with IRQs disabled. Warn here to detect early | |
2176 | * when its not. | |
2177 | */ | |
2178 | WARN_ON(!irqs_disabled()); | |
2179 | ||
2180 | /* lock domain */ | |
2181 | spin_lock(&domain->lock); | |
2182 | ||
2183 | ret = -EBUSY; | |
2184 | if (dev_data->domain != NULL) | |
2185 | goto out_unlock; | |
2186 | ||
2187 | /* Attach alias group root */ | |
2188 | do_attach(dev_data, domain); | |
2189 | ||
2190 | ret = 0; | |
2191 | ||
2192 | out_unlock: | |
2193 | ||
2194 | /* ready */ | |
2195 | spin_unlock(&domain->lock); | |
2196 | ||
2197 | return ret; | |
2198 | } | |
2199 | ||
2200 | ||
2201 | static void pdev_iommuv2_disable(struct pci_dev *pdev) | |
2202 | { | |
2203 | pci_disable_ats(pdev); | |
2204 | pci_disable_pri(pdev); | |
2205 | pci_disable_pasid(pdev); | |
2206 | } | |
2207 | ||
2208 | /* FIXME: Change generic reset-function to do the same */ | |
2209 | static int pri_reset_while_enabled(struct pci_dev *pdev) | |
2210 | { | |
2211 | u16 control; | |
2212 | int pos; | |
2213 | ||
2214 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); | |
2215 | if (!pos) | |
2216 | return -EINVAL; | |
2217 | ||
2218 | pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control); | |
2219 | control |= PCI_PRI_CTRL_RESET; | |
2220 | pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control); | |
2221 | ||
2222 | return 0; | |
2223 | } | |
2224 | ||
2225 | static int pdev_iommuv2_enable(struct pci_dev *pdev) | |
2226 | { | |
2227 | bool reset_enable; | |
2228 | int reqs, ret; | |
2229 | ||
2230 | /* FIXME: Hardcode number of outstanding requests for now */ | |
2231 | reqs = 32; | |
2232 | if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE)) | |
2233 | reqs = 1; | |
2234 | reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET); | |
2235 | ||
2236 | /* Only allow access to user-accessible pages */ | |
2237 | ret = pci_enable_pasid(pdev, 0); | |
2238 | if (ret) | |
2239 | goto out_err; | |
2240 | ||
2241 | /* First reset the PRI state of the device */ | |
2242 | ret = pci_reset_pri(pdev); | |
2243 | if (ret) | |
2244 | goto out_err; | |
2245 | ||
2246 | /* Enable PRI */ | |
2247 | ret = pci_enable_pri(pdev, reqs); | |
2248 | if (ret) | |
2249 | goto out_err; | |
2250 | ||
2251 | if (reset_enable) { | |
2252 | ret = pri_reset_while_enabled(pdev); | |
2253 | if (ret) | |
2254 | goto out_err; | |
2255 | } | |
2256 | ||
2257 | ret = pci_enable_ats(pdev, PAGE_SHIFT); | |
2258 | if (ret) | |
2259 | goto out_err; | |
2260 | ||
2261 | return 0; | |
2262 | ||
2263 | out_err: | |
2264 | pci_disable_pri(pdev); | |
2265 | pci_disable_pasid(pdev); | |
2266 | ||
2267 | return ret; | |
2268 | } | |
2269 | ||
2270 | /* FIXME: Move this to PCI code */ | |
2271 | #define PCI_PRI_TLP_OFF (1 << 15) | |
2272 | ||
2273 | static bool pci_pri_tlp_required(struct pci_dev *pdev) | |
2274 | { | |
2275 | u16 status; | |
2276 | int pos; | |
2277 | ||
2278 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); | |
2279 | if (!pos) | |
2280 | return false; | |
2281 | ||
2282 | pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status); | |
2283 | ||
2284 | return (status & PCI_PRI_TLP_OFF) ? true : false; | |
2285 | } | |
2286 | ||
2287 | /* | |
2288 | * If a device is not yet associated with a domain, this function | |
2289 | * assigns it visible for the hardware | |
2290 | */ | |
2291 | static int attach_device(struct device *dev, | |
2292 | struct protection_domain *domain) | |
2293 | { | |
2294 | struct pci_dev *pdev; | |
2295 | struct iommu_dev_data *dev_data; | |
2296 | unsigned long flags; | |
2297 | int ret; | |
2298 | ||
2299 | dev_data = get_dev_data(dev); | |
2300 | ||
2301 | if (!dev_is_pci(dev)) | |
2302 | goto skip_ats_check; | |
2303 | ||
2304 | pdev = to_pci_dev(dev); | |
2305 | if (domain->flags & PD_IOMMUV2_MASK) { | |
2306 | if (!dev_data->passthrough) | |
2307 | return -EINVAL; | |
2308 | ||
2309 | if (dev_data->iommu_v2) { | |
2310 | if (pdev_iommuv2_enable(pdev) != 0) | |
2311 | return -EINVAL; | |
2312 | ||
2313 | dev_data->ats.enabled = true; | |
2314 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
2315 | dev_data->pri_tlp = pci_pri_tlp_required(pdev); | |
2316 | } | |
2317 | } else if (amd_iommu_iotlb_sup && | |
2318 | pci_enable_ats(pdev, PAGE_SHIFT) == 0) { | |
2319 | dev_data->ats.enabled = true; | |
2320 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
2321 | } | |
2322 | ||
2323 | skip_ats_check: | |
2324 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
2325 | ret = __attach_device(dev_data, domain); | |
2326 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
2327 | ||
2328 | /* | |
2329 | * We might boot into a crash-kernel here. The crashed kernel | |
2330 | * left the caches in the IOMMU dirty. So we have to flush | |
2331 | * here to evict all dirty stuff. | |
2332 | */ | |
2333 | domain_flush_tlb_pde(domain); | |
2334 | ||
2335 | return ret; | |
2336 | } | |
2337 | ||
2338 | /* | |
2339 | * Removes a device from a protection domain (unlocked) | |
2340 | */ | |
2341 | static void __detach_device(struct iommu_dev_data *dev_data) | |
2342 | { | |
2343 | struct protection_domain *domain; | |
2344 | ||
2345 | /* | |
2346 | * Must be called with IRQs disabled. Warn here to detect early | |
2347 | * when its not. | |
2348 | */ | |
2349 | WARN_ON(!irqs_disabled()); | |
2350 | ||
2351 | if (WARN_ON(!dev_data->domain)) | |
2352 | return; | |
2353 | ||
2354 | domain = dev_data->domain; | |
2355 | ||
2356 | spin_lock(&domain->lock); | |
2357 | ||
2358 | do_detach(dev_data); | |
2359 | ||
2360 | spin_unlock(&domain->lock); | |
2361 | } | |
2362 | ||
2363 | /* | |
2364 | * Removes a device from a protection domain (with devtable_lock held) | |
2365 | */ | |
2366 | static void detach_device(struct device *dev) | |
2367 | { | |
2368 | struct protection_domain *domain; | |
2369 | struct iommu_dev_data *dev_data; | |
2370 | unsigned long flags; | |
2371 | ||
2372 | dev_data = get_dev_data(dev); | |
2373 | domain = dev_data->domain; | |
2374 | ||
2375 | /* lock device table */ | |
2376 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
2377 | __detach_device(dev_data); | |
2378 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
2379 | ||
2380 | if (!dev_is_pci(dev)) | |
2381 | return; | |
2382 | ||
2383 | if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2) | |
2384 | pdev_iommuv2_disable(to_pci_dev(dev)); | |
2385 | else if (dev_data->ats.enabled) | |
2386 | pci_disable_ats(to_pci_dev(dev)); | |
2387 | ||
2388 | dev_data->ats.enabled = false; | |
2389 | } | |
2390 | ||
2391 | static int amd_iommu_add_device(struct device *dev) | |
2392 | { | |
2393 | struct iommu_dev_data *dev_data; | |
2394 | struct iommu_domain *domain; | |
2395 | struct amd_iommu *iommu; | |
2396 | int ret, devid; | |
2397 | ||
2398 | if (!check_device(dev) || get_dev_data(dev)) | |
2399 | return 0; | |
2400 | ||
2401 | devid = get_device_id(dev); | |
2402 | if (devid < 0) | |
2403 | return devid; | |
2404 | ||
2405 | iommu = amd_iommu_rlookup_table[devid]; | |
2406 | ||
2407 | ret = iommu_init_device(dev); | |
2408 | if (ret) { | |
2409 | if (ret != -ENOTSUPP) | |
2410 | pr_err("Failed to initialize device %s - trying to proceed anyway\n", | |
2411 | dev_name(dev)); | |
2412 | ||
2413 | iommu_ignore_device(dev); | |
2414 | dev->dma_ops = &nommu_dma_ops; | |
2415 | goto out; | |
2416 | } | |
2417 | init_iommu_group(dev); | |
2418 | ||
2419 | dev_data = get_dev_data(dev); | |
2420 | ||
2421 | BUG_ON(!dev_data); | |
2422 | ||
2423 | if (iommu_pass_through || dev_data->iommu_v2) | |
2424 | iommu_request_dm_for_dev(dev); | |
2425 | ||
2426 | /* Domains are initialized for this device - have a look what we ended up with */ | |
2427 | domain = iommu_get_domain_for_dev(dev); | |
2428 | if (domain->type == IOMMU_DOMAIN_IDENTITY) | |
2429 | dev_data->passthrough = true; | |
2430 | else | |
2431 | dev->dma_ops = &amd_iommu_dma_ops; | |
2432 | ||
2433 | out: | |
2434 | iommu_completion_wait(iommu); | |
2435 | ||
2436 | return 0; | |
2437 | } | |
2438 | ||
2439 | static void amd_iommu_remove_device(struct device *dev) | |
2440 | { | |
2441 | struct amd_iommu *iommu; | |
2442 | int devid; | |
2443 | ||
2444 | if (!check_device(dev)) | |
2445 | return; | |
2446 | ||
2447 | devid = get_device_id(dev); | |
2448 | if (devid < 0) | |
2449 | return; | |
2450 | ||
2451 | iommu = amd_iommu_rlookup_table[devid]; | |
2452 | ||
2453 | iommu_uninit_device(dev); | |
2454 | iommu_completion_wait(iommu); | |
2455 | } | |
2456 | ||
2457 | static struct iommu_group *amd_iommu_device_group(struct device *dev) | |
2458 | { | |
2459 | if (dev_is_pci(dev)) | |
2460 | return pci_device_group(dev); | |
2461 | ||
2462 | return acpihid_device_group(dev); | |
2463 | } | |
2464 | ||
2465 | /***************************************************************************** | |
2466 | * | |
2467 | * The next functions belong to the dma_ops mapping/unmapping code. | |
2468 | * | |
2469 | *****************************************************************************/ | |
2470 | ||
2471 | /* | |
2472 | * In the dma_ops path we only have the struct device. This function | |
2473 | * finds the corresponding IOMMU, the protection domain and the | |
2474 | * requestor id for a given device. | |
2475 | * If the device is not yet associated with a domain this is also done | |
2476 | * in this function. | |
2477 | */ | |
2478 | static struct protection_domain *get_domain(struct device *dev) | |
2479 | { | |
2480 | struct protection_domain *domain; | |
2481 | ||
2482 | if (!check_device(dev)) | |
2483 | return ERR_PTR(-EINVAL); | |
2484 | ||
2485 | domain = get_dev_data(dev)->domain; | |
2486 | if (!dma_ops_domain(domain)) | |
2487 | return ERR_PTR(-EBUSY); | |
2488 | ||
2489 | return domain; | |
2490 | } | |
2491 | ||
2492 | static void update_device_table(struct protection_domain *domain) | |
2493 | { | |
2494 | struct iommu_dev_data *dev_data; | |
2495 | ||
2496 | list_for_each_entry(dev_data, &domain->dev_list, list) { | |
2497 | set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled); | |
2498 | ||
2499 | if (dev_data->devid == dev_data->alias) | |
2500 | continue; | |
2501 | ||
2502 | /* There is an alias, update device table entry for it */ | |
2503 | set_dte_entry(dev_data->alias, domain, dev_data->ats.enabled); | |
2504 | } | |
2505 | } | |
2506 | ||
2507 | static void update_domain(struct protection_domain *domain) | |
2508 | { | |
2509 | if (!domain->updated) | |
2510 | return; | |
2511 | ||
2512 | update_device_table(domain); | |
2513 | ||
2514 | domain_flush_devices(domain); | |
2515 | domain_flush_tlb_pde(domain); | |
2516 | ||
2517 | domain->updated = false; | |
2518 | } | |
2519 | ||
2520 | static int dir2prot(enum dma_data_direction direction) | |
2521 | { | |
2522 | if (direction == DMA_TO_DEVICE) | |
2523 | return IOMMU_PROT_IR; | |
2524 | else if (direction == DMA_FROM_DEVICE) | |
2525 | return IOMMU_PROT_IW; | |
2526 | else if (direction == DMA_BIDIRECTIONAL) | |
2527 | return IOMMU_PROT_IW | IOMMU_PROT_IR; | |
2528 | else | |
2529 | return 0; | |
2530 | } | |
2531 | /* | |
2532 | * This function contains common code for mapping of a physically | |
2533 | * contiguous memory region into DMA address space. It is used by all | |
2534 | * mapping functions provided with this IOMMU driver. | |
2535 | * Must be called with the domain lock held. | |
2536 | */ | |
2537 | static dma_addr_t __map_single(struct device *dev, | |
2538 | struct dma_ops_domain *dma_dom, | |
2539 | phys_addr_t paddr, | |
2540 | size_t size, | |
2541 | enum dma_data_direction direction, | |
2542 | u64 dma_mask) | |
2543 | { | |
2544 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
2545 | dma_addr_t address, start, ret; | |
2546 | unsigned int pages; | |
2547 | int prot = 0; | |
2548 | int i; | |
2549 | ||
2550 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); | |
2551 | paddr &= PAGE_MASK; | |
2552 | ||
2553 | address = dma_ops_alloc_iova(dev, dma_dom, pages, dma_mask); | |
2554 | if (address == AMD_IOMMU_MAPPING_ERROR) | |
2555 | goto out; | |
2556 | ||
2557 | prot = dir2prot(direction); | |
2558 | ||
2559 | start = address; | |
2560 | for (i = 0; i < pages; ++i) { | |
2561 | ret = iommu_map_page(&dma_dom->domain, start, paddr, | |
2562 | PAGE_SIZE, prot, GFP_ATOMIC); | |
2563 | if (ret) | |
2564 | goto out_unmap; | |
2565 | ||
2566 | paddr += PAGE_SIZE; | |
2567 | start += PAGE_SIZE; | |
2568 | } | |
2569 | address += offset; | |
2570 | ||
2571 | if (unlikely(amd_iommu_np_cache)) { | |
2572 | domain_flush_pages(&dma_dom->domain, address, size); | |
2573 | domain_flush_complete(&dma_dom->domain); | |
2574 | } | |
2575 | ||
2576 | out: | |
2577 | return address; | |
2578 | ||
2579 | out_unmap: | |
2580 | ||
2581 | for (--i; i >= 0; --i) { | |
2582 | start -= PAGE_SIZE; | |
2583 | iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE); | |
2584 | } | |
2585 | ||
2586 | domain_flush_tlb(&dma_dom->domain); | |
2587 | domain_flush_complete(&dma_dom->domain); | |
2588 | ||
2589 | dma_ops_free_iova(dma_dom, address, pages); | |
2590 | ||
2591 | return AMD_IOMMU_MAPPING_ERROR; | |
2592 | } | |
2593 | ||
2594 | /* | |
2595 | * Does the reverse of the __map_single function. Must be called with | |
2596 | * the domain lock held too | |
2597 | */ | |
2598 | static void __unmap_single(struct dma_ops_domain *dma_dom, | |
2599 | dma_addr_t dma_addr, | |
2600 | size_t size, | |
2601 | int dir) | |
2602 | { | |
2603 | dma_addr_t flush_addr; | |
2604 | dma_addr_t i, start; | |
2605 | unsigned int pages; | |
2606 | ||
2607 | flush_addr = dma_addr; | |
2608 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); | |
2609 | dma_addr &= PAGE_MASK; | |
2610 | start = dma_addr; | |
2611 | ||
2612 | for (i = 0; i < pages; ++i) { | |
2613 | iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE); | |
2614 | start += PAGE_SIZE; | |
2615 | } | |
2616 | ||
2617 | if (amd_iommu_unmap_flush) { | |
2618 | dma_ops_free_iova(dma_dom, dma_addr, pages); | |
2619 | domain_flush_tlb(&dma_dom->domain); | |
2620 | domain_flush_complete(&dma_dom->domain); | |
2621 | } else { | |
2622 | queue_add(dma_dom, dma_addr, pages); | |
2623 | } | |
2624 | } | |
2625 | ||
2626 | /* | |
2627 | * The exported map_single function for dma_ops. | |
2628 | */ | |
2629 | static dma_addr_t map_page(struct device *dev, struct page *page, | |
2630 | unsigned long offset, size_t size, | |
2631 | enum dma_data_direction dir, | |
2632 | unsigned long attrs) | |
2633 | { | |
2634 | phys_addr_t paddr = page_to_phys(page) + offset; | |
2635 | struct protection_domain *domain; | |
2636 | struct dma_ops_domain *dma_dom; | |
2637 | u64 dma_mask; | |
2638 | ||
2639 | domain = get_domain(dev); | |
2640 | if (PTR_ERR(domain) == -EINVAL) | |
2641 | return (dma_addr_t)paddr; | |
2642 | else if (IS_ERR(domain)) | |
2643 | return AMD_IOMMU_MAPPING_ERROR; | |
2644 | ||
2645 | dma_mask = *dev->dma_mask; | |
2646 | dma_dom = to_dma_ops_domain(domain); | |
2647 | ||
2648 | return __map_single(dev, dma_dom, paddr, size, dir, dma_mask); | |
2649 | } | |
2650 | ||
2651 | /* | |
2652 | * The exported unmap_single function for dma_ops. | |
2653 | */ | |
2654 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, | |
2655 | enum dma_data_direction dir, unsigned long attrs) | |
2656 | { | |
2657 | struct protection_domain *domain; | |
2658 | struct dma_ops_domain *dma_dom; | |
2659 | ||
2660 | domain = get_domain(dev); | |
2661 | if (IS_ERR(domain)) | |
2662 | return; | |
2663 | ||
2664 | dma_dom = to_dma_ops_domain(domain); | |
2665 | ||
2666 | __unmap_single(dma_dom, dma_addr, size, dir); | |
2667 | } | |
2668 | ||
2669 | static int sg_num_pages(struct device *dev, | |
2670 | struct scatterlist *sglist, | |
2671 | int nelems) | |
2672 | { | |
2673 | unsigned long mask, boundary_size; | |
2674 | struct scatterlist *s; | |
2675 | int i, npages = 0; | |
2676 | ||
2677 | mask = dma_get_seg_boundary(dev); | |
2678 | boundary_size = mask + 1 ? ALIGN(mask + 1, PAGE_SIZE) >> PAGE_SHIFT : | |
2679 | 1UL << (BITS_PER_LONG - PAGE_SHIFT); | |
2680 | ||
2681 | for_each_sg(sglist, s, nelems, i) { | |
2682 | int p, n; | |
2683 | ||
2684 | s->dma_address = npages << PAGE_SHIFT; | |
2685 | p = npages % boundary_size; | |
2686 | n = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE); | |
2687 | if (p + n > boundary_size) | |
2688 | npages += boundary_size - p; | |
2689 | npages += n; | |
2690 | } | |
2691 | ||
2692 | return npages; | |
2693 | } | |
2694 | ||
2695 | /* | |
2696 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2697 | * lists). | |
2698 | */ | |
2699 | static int map_sg(struct device *dev, struct scatterlist *sglist, | |
2700 | int nelems, enum dma_data_direction direction, | |
2701 | unsigned long attrs) | |
2702 | { | |
2703 | int mapped_pages = 0, npages = 0, prot = 0, i; | |
2704 | struct protection_domain *domain; | |
2705 | struct dma_ops_domain *dma_dom; | |
2706 | struct scatterlist *s; | |
2707 | unsigned long address; | |
2708 | u64 dma_mask; | |
2709 | ||
2710 | domain = get_domain(dev); | |
2711 | if (IS_ERR(domain)) | |
2712 | return 0; | |
2713 | ||
2714 | dma_dom = to_dma_ops_domain(domain); | |
2715 | dma_mask = *dev->dma_mask; | |
2716 | ||
2717 | npages = sg_num_pages(dev, sglist, nelems); | |
2718 | ||
2719 | address = dma_ops_alloc_iova(dev, dma_dom, npages, dma_mask); | |
2720 | if (address == AMD_IOMMU_MAPPING_ERROR) | |
2721 | goto out_err; | |
2722 | ||
2723 | prot = dir2prot(direction); | |
2724 | ||
2725 | /* Map all sg entries */ | |
2726 | for_each_sg(sglist, s, nelems, i) { | |
2727 | int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE); | |
2728 | ||
2729 | for (j = 0; j < pages; ++j) { | |
2730 | unsigned long bus_addr, phys_addr; | |
2731 | int ret; | |
2732 | ||
2733 | bus_addr = address + s->dma_address + (j << PAGE_SHIFT); | |
2734 | phys_addr = (sg_phys(s) & PAGE_MASK) + (j << PAGE_SHIFT); | |
2735 | ret = iommu_map_page(domain, bus_addr, phys_addr, PAGE_SIZE, prot, GFP_ATOMIC); | |
2736 | if (ret) | |
2737 | goto out_unmap; | |
2738 | ||
2739 | mapped_pages += 1; | |
2740 | } | |
2741 | } | |
2742 | ||
2743 | /* Everything is mapped - write the right values into s->dma_address */ | |
2744 | for_each_sg(sglist, s, nelems, i) { | |
2745 | s->dma_address += address + s->offset; | |
2746 | s->dma_length = s->length; | |
2747 | } | |
2748 | ||
2749 | return nelems; | |
2750 | ||
2751 | out_unmap: | |
2752 | pr_err("%s: IOMMU mapping error in map_sg (io-pages: %d)\n", | |
2753 | dev_name(dev), npages); | |
2754 | ||
2755 | for_each_sg(sglist, s, nelems, i) { | |
2756 | int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE); | |
2757 | ||
2758 | for (j = 0; j < pages; ++j) { | |
2759 | unsigned long bus_addr; | |
2760 | ||
2761 | bus_addr = address + s->dma_address + (j << PAGE_SHIFT); | |
2762 | iommu_unmap_page(domain, bus_addr, PAGE_SIZE); | |
2763 | ||
2764 | if (--mapped_pages) | |
2765 | goto out_free_iova; | |
2766 | } | |
2767 | } | |
2768 | ||
2769 | out_free_iova: | |
2770 | free_iova_fast(&dma_dom->iovad, address, npages); | |
2771 | ||
2772 | out_err: | |
2773 | return 0; | |
2774 | } | |
2775 | ||
2776 | /* | |
2777 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2778 | * lists). | |
2779 | */ | |
2780 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, | |
2781 | int nelems, enum dma_data_direction dir, | |
2782 | unsigned long attrs) | |
2783 | { | |
2784 | struct protection_domain *domain; | |
2785 | struct dma_ops_domain *dma_dom; | |
2786 | unsigned long startaddr; | |
2787 | int npages = 2; | |
2788 | ||
2789 | domain = get_domain(dev); | |
2790 | if (IS_ERR(domain)) | |
2791 | return; | |
2792 | ||
2793 | startaddr = sg_dma_address(sglist) & PAGE_MASK; | |
2794 | dma_dom = to_dma_ops_domain(domain); | |
2795 | npages = sg_num_pages(dev, sglist, nelems); | |
2796 | ||
2797 | __unmap_single(dma_dom, startaddr, npages << PAGE_SHIFT, dir); | |
2798 | } | |
2799 | ||
2800 | /* | |
2801 | * The exported alloc_coherent function for dma_ops. | |
2802 | */ | |
2803 | static void *alloc_coherent(struct device *dev, size_t size, | |
2804 | dma_addr_t *dma_addr, gfp_t flag, | |
2805 | unsigned long attrs) | |
2806 | { | |
2807 | u64 dma_mask = dev->coherent_dma_mask; | |
2808 | struct protection_domain *domain; | |
2809 | struct dma_ops_domain *dma_dom; | |
2810 | struct page *page; | |
2811 | ||
2812 | domain = get_domain(dev); | |
2813 | if (PTR_ERR(domain) == -EINVAL) { | |
2814 | page = alloc_pages(flag, get_order(size)); | |
2815 | *dma_addr = page_to_phys(page); | |
2816 | return page_address(page); | |
2817 | } else if (IS_ERR(domain)) | |
2818 | return NULL; | |
2819 | ||
2820 | dma_dom = to_dma_ops_domain(domain); | |
2821 | size = PAGE_ALIGN(size); | |
2822 | dma_mask = dev->coherent_dma_mask; | |
2823 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
2824 | flag |= __GFP_ZERO; | |
2825 | ||
2826 | page = alloc_pages(flag | __GFP_NOWARN, get_order(size)); | |
2827 | if (!page) { | |
2828 | if (!gfpflags_allow_blocking(flag)) | |
2829 | return NULL; | |
2830 | ||
2831 | page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT, | |
2832 | get_order(size), flag); | |
2833 | if (!page) | |
2834 | return NULL; | |
2835 | } | |
2836 | ||
2837 | if (!dma_mask) | |
2838 | dma_mask = *dev->dma_mask; | |
2839 | ||
2840 | *dma_addr = __map_single(dev, dma_dom, page_to_phys(page), | |
2841 | size, DMA_BIDIRECTIONAL, dma_mask); | |
2842 | ||
2843 | if (*dma_addr == AMD_IOMMU_MAPPING_ERROR) | |
2844 | goto out_free; | |
2845 | ||
2846 | return page_address(page); | |
2847 | ||
2848 | out_free: | |
2849 | ||
2850 | if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT)) | |
2851 | __free_pages(page, get_order(size)); | |
2852 | ||
2853 | return NULL; | |
2854 | } | |
2855 | ||
2856 | /* | |
2857 | * The exported free_coherent function for dma_ops. | |
2858 | */ | |
2859 | static void free_coherent(struct device *dev, size_t size, | |
2860 | void *virt_addr, dma_addr_t dma_addr, | |
2861 | unsigned long attrs) | |
2862 | { | |
2863 | struct protection_domain *domain; | |
2864 | struct dma_ops_domain *dma_dom; | |
2865 | struct page *page; | |
2866 | ||
2867 | page = virt_to_page(virt_addr); | |
2868 | size = PAGE_ALIGN(size); | |
2869 | ||
2870 | domain = get_domain(dev); | |
2871 | if (IS_ERR(domain)) | |
2872 | goto free_mem; | |
2873 | ||
2874 | dma_dom = to_dma_ops_domain(domain); | |
2875 | ||
2876 | __unmap_single(dma_dom, dma_addr, size, DMA_BIDIRECTIONAL); | |
2877 | ||
2878 | free_mem: | |
2879 | if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT)) | |
2880 | __free_pages(page, get_order(size)); | |
2881 | } | |
2882 | ||
2883 | /* | |
2884 | * This function is called by the DMA layer to find out if we can handle a | |
2885 | * particular device. It is part of the dma_ops. | |
2886 | */ | |
2887 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
2888 | { | |
2889 | if (!x86_dma_supported(dev, mask)) | |
2890 | return 0; | |
2891 | return check_device(dev); | |
2892 | } | |
2893 | ||
2894 | static int amd_iommu_mapping_error(struct device *dev, dma_addr_t dma_addr) | |
2895 | { | |
2896 | return dma_addr == AMD_IOMMU_MAPPING_ERROR; | |
2897 | } | |
2898 | ||
2899 | static const struct dma_map_ops amd_iommu_dma_ops = { | |
2900 | .alloc = alloc_coherent, | |
2901 | .free = free_coherent, | |
2902 | .map_page = map_page, | |
2903 | .unmap_page = unmap_page, | |
2904 | .map_sg = map_sg, | |
2905 | .unmap_sg = unmap_sg, | |
2906 | .dma_supported = amd_iommu_dma_supported, | |
2907 | .mapping_error = amd_iommu_mapping_error, | |
2908 | }; | |
2909 | ||
2910 | static int init_reserved_iova_ranges(void) | |
2911 | { | |
2912 | struct pci_dev *pdev = NULL; | |
2913 | struct iova *val; | |
2914 | ||
2915 | init_iova_domain(&reserved_iova_ranges, PAGE_SIZE, | |
2916 | IOVA_START_PFN, DMA_32BIT_PFN); | |
2917 | ||
2918 | lockdep_set_class(&reserved_iova_ranges.iova_rbtree_lock, | |
2919 | &reserved_rbtree_key); | |
2920 | ||
2921 | /* MSI memory range */ | |
2922 | val = reserve_iova(&reserved_iova_ranges, | |
2923 | IOVA_PFN(MSI_RANGE_START), IOVA_PFN(MSI_RANGE_END)); | |
2924 | if (!val) { | |
2925 | pr_err("Reserving MSI range failed\n"); | |
2926 | return -ENOMEM; | |
2927 | } | |
2928 | ||
2929 | /* HT memory range */ | |
2930 | val = reserve_iova(&reserved_iova_ranges, | |
2931 | IOVA_PFN(HT_RANGE_START), IOVA_PFN(HT_RANGE_END)); | |
2932 | if (!val) { | |
2933 | pr_err("Reserving HT range failed\n"); | |
2934 | return -ENOMEM; | |
2935 | } | |
2936 | ||
2937 | /* | |
2938 | * Memory used for PCI resources | |
2939 | * FIXME: Check whether we can reserve the PCI-hole completly | |
2940 | */ | |
2941 | for_each_pci_dev(pdev) { | |
2942 | int i; | |
2943 | ||
2944 | for (i = 0; i < PCI_NUM_RESOURCES; ++i) { | |
2945 | struct resource *r = &pdev->resource[i]; | |
2946 | ||
2947 | if (!(r->flags & IORESOURCE_MEM)) | |
2948 | continue; | |
2949 | ||
2950 | val = reserve_iova(&reserved_iova_ranges, | |
2951 | IOVA_PFN(r->start), | |
2952 | IOVA_PFN(r->end)); | |
2953 | if (!val) { | |
2954 | pr_err("Reserve pci-resource range failed\n"); | |
2955 | return -ENOMEM; | |
2956 | } | |
2957 | } | |
2958 | } | |
2959 | ||
2960 | return 0; | |
2961 | } | |
2962 | ||
2963 | int __init amd_iommu_init_api(void) | |
2964 | { | |
2965 | int ret, err = 0; | |
2966 | ||
2967 | ret = iova_cache_get(); | |
2968 | if (ret) | |
2969 | return ret; | |
2970 | ||
2971 | ret = init_reserved_iova_ranges(); | |
2972 | if (ret) | |
2973 | return ret; | |
2974 | ||
2975 | err = bus_set_iommu(&pci_bus_type, &amd_iommu_ops); | |
2976 | if (err) | |
2977 | return err; | |
2978 | #ifdef CONFIG_ARM_AMBA | |
2979 | err = bus_set_iommu(&amba_bustype, &amd_iommu_ops); | |
2980 | if (err) | |
2981 | return err; | |
2982 | #endif | |
2983 | err = bus_set_iommu(&platform_bus_type, &amd_iommu_ops); | |
2984 | if (err) | |
2985 | return err; | |
2986 | ||
2987 | return 0; | |
2988 | } | |
2989 | ||
2990 | int __init amd_iommu_init_dma_ops(void) | |
2991 | { | |
2992 | swiotlb = iommu_pass_through ? 1 : 0; | |
2993 | iommu_detected = 1; | |
2994 | ||
2995 | /* | |
2996 | * In case we don't initialize SWIOTLB (actually the common case | |
2997 | * when AMD IOMMU is enabled), make sure there are global | |
2998 | * dma_ops set as a fall-back for devices not handled by this | |
2999 | * driver (for example non-PCI devices). | |
3000 | */ | |
3001 | if (!swiotlb) | |
3002 | dma_ops = &nommu_dma_ops; | |
3003 | ||
3004 | if (amd_iommu_unmap_flush) | |
3005 | pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n"); | |
3006 | else | |
3007 | pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n"); | |
3008 | ||
3009 | return 0; | |
3010 | ||
3011 | } | |
3012 | ||
3013 | /***************************************************************************** | |
3014 | * | |
3015 | * The following functions belong to the exported interface of AMD IOMMU | |
3016 | * | |
3017 | * This interface allows access to lower level functions of the IOMMU | |
3018 | * like protection domain handling and assignement of devices to domains | |
3019 | * which is not possible with the dma_ops interface. | |
3020 | * | |
3021 | *****************************************************************************/ | |
3022 | ||
3023 | static void cleanup_domain(struct protection_domain *domain) | |
3024 | { | |
3025 | struct iommu_dev_data *entry; | |
3026 | unsigned long flags; | |
3027 | ||
3028 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
3029 | ||
3030 | while (!list_empty(&domain->dev_list)) { | |
3031 | entry = list_first_entry(&domain->dev_list, | |
3032 | struct iommu_dev_data, list); | |
3033 | __detach_device(entry); | |
3034 | } | |
3035 | ||
3036 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
3037 | } | |
3038 | ||
3039 | static void protection_domain_free(struct protection_domain *domain) | |
3040 | { | |
3041 | if (!domain) | |
3042 | return; | |
3043 | ||
3044 | del_domain_from_list(domain); | |
3045 | ||
3046 | if (domain->id) | |
3047 | domain_id_free(domain->id); | |
3048 | ||
3049 | kfree(domain); | |
3050 | } | |
3051 | ||
3052 | static int protection_domain_init(struct protection_domain *domain) | |
3053 | { | |
3054 | spin_lock_init(&domain->lock); | |
3055 | mutex_init(&domain->api_lock); | |
3056 | domain->id = domain_id_alloc(); | |
3057 | if (!domain->id) | |
3058 | return -ENOMEM; | |
3059 | INIT_LIST_HEAD(&domain->dev_list); | |
3060 | ||
3061 | return 0; | |
3062 | } | |
3063 | ||
3064 | static struct protection_domain *protection_domain_alloc(void) | |
3065 | { | |
3066 | struct protection_domain *domain; | |
3067 | ||
3068 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
3069 | if (!domain) | |
3070 | return NULL; | |
3071 | ||
3072 | if (protection_domain_init(domain)) | |
3073 | goto out_err; | |
3074 | ||
3075 | add_domain_to_list(domain); | |
3076 | ||
3077 | return domain; | |
3078 | ||
3079 | out_err: | |
3080 | kfree(domain); | |
3081 | ||
3082 | return NULL; | |
3083 | } | |
3084 | ||
3085 | static struct iommu_domain *amd_iommu_domain_alloc(unsigned type) | |
3086 | { | |
3087 | struct protection_domain *pdomain; | |
3088 | struct dma_ops_domain *dma_domain; | |
3089 | ||
3090 | switch (type) { | |
3091 | case IOMMU_DOMAIN_UNMANAGED: | |
3092 | pdomain = protection_domain_alloc(); | |
3093 | if (!pdomain) | |
3094 | return NULL; | |
3095 | ||
3096 | pdomain->mode = PAGE_MODE_3_LEVEL; | |
3097 | pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
3098 | if (!pdomain->pt_root) { | |
3099 | protection_domain_free(pdomain); | |
3100 | return NULL; | |
3101 | } | |
3102 | ||
3103 | pdomain->domain.geometry.aperture_start = 0; | |
3104 | pdomain->domain.geometry.aperture_end = ~0ULL; | |
3105 | pdomain->domain.geometry.force_aperture = true; | |
3106 | ||
3107 | break; | |
3108 | case IOMMU_DOMAIN_DMA: | |
3109 | dma_domain = dma_ops_domain_alloc(); | |
3110 | if (!dma_domain) { | |
3111 | pr_err("AMD-Vi: Failed to allocate\n"); | |
3112 | return NULL; | |
3113 | } | |
3114 | pdomain = &dma_domain->domain; | |
3115 | break; | |
3116 | case IOMMU_DOMAIN_IDENTITY: | |
3117 | pdomain = protection_domain_alloc(); | |
3118 | if (!pdomain) | |
3119 | return NULL; | |
3120 | ||
3121 | pdomain->mode = PAGE_MODE_NONE; | |
3122 | break; | |
3123 | default: | |
3124 | return NULL; | |
3125 | } | |
3126 | ||
3127 | return &pdomain->domain; | |
3128 | } | |
3129 | ||
3130 | static void amd_iommu_domain_free(struct iommu_domain *dom) | |
3131 | { | |
3132 | struct protection_domain *domain; | |
3133 | struct dma_ops_domain *dma_dom; | |
3134 | ||
3135 | domain = to_pdomain(dom); | |
3136 | ||
3137 | if (domain->dev_cnt > 0) | |
3138 | cleanup_domain(domain); | |
3139 | ||
3140 | BUG_ON(domain->dev_cnt != 0); | |
3141 | ||
3142 | if (!dom) | |
3143 | return; | |
3144 | ||
3145 | switch (dom->type) { | |
3146 | case IOMMU_DOMAIN_DMA: | |
3147 | /* Now release the domain */ | |
3148 | dma_dom = to_dma_ops_domain(domain); | |
3149 | dma_ops_domain_free(dma_dom); | |
3150 | break; | |
3151 | default: | |
3152 | if (domain->mode != PAGE_MODE_NONE) | |
3153 | free_pagetable(domain); | |
3154 | ||
3155 | if (domain->flags & PD_IOMMUV2_MASK) | |
3156 | free_gcr3_table(domain); | |
3157 | ||
3158 | protection_domain_free(domain); | |
3159 | break; | |
3160 | } | |
3161 | } | |
3162 | ||
3163 | static void amd_iommu_detach_device(struct iommu_domain *dom, | |
3164 | struct device *dev) | |
3165 | { | |
3166 | struct iommu_dev_data *dev_data = dev->archdata.iommu; | |
3167 | struct amd_iommu *iommu; | |
3168 | int devid; | |
3169 | ||
3170 | if (!check_device(dev)) | |
3171 | return; | |
3172 | ||
3173 | devid = get_device_id(dev); | |
3174 | if (devid < 0) | |
3175 | return; | |
3176 | ||
3177 | if (dev_data->domain != NULL) | |
3178 | detach_device(dev); | |
3179 | ||
3180 | iommu = amd_iommu_rlookup_table[devid]; | |
3181 | if (!iommu) | |
3182 | return; | |
3183 | ||
3184 | #ifdef CONFIG_IRQ_REMAP | |
3185 | if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) && | |
3186 | (dom->type == IOMMU_DOMAIN_UNMANAGED)) | |
3187 | dev_data->use_vapic = 0; | |
3188 | #endif | |
3189 | ||
3190 | iommu_completion_wait(iommu); | |
3191 | } | |
3192 | ||
3193 | static int amd_iommu_attach_device(struct iommu_domain *dom, | |
3194 | struct device *dev) | |
3195 | { | |
3196 | struct protection_domain *domain = to_pdomain(dom); | |
3197 | struct iommu_dev_data *dev_data; | |
3198 | struct amd_iommu *iommu; | |
3199 | int ret; | |
3200 | ||
3201 | if (!check_device(dev)) | |
3202 | return -EINVAL; | |
3203 | ||
3204 | dev_data = dev->archdata.iommu; | |
3205 | ||
3206 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3207 | if (!iommu) | |
3208 | return -EINVAL; | |
3209 | ||
3210 | if (dev_data->domain) | |
3211 | detach_device(dev); | |
3212 | ||
3213 | ret = attach_device(dev, domain); | |
3214 | ||
3215 | #ifdef CONFIG_IRQ_REMAP | |
3216 | if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) { | |
3217 | if (dom->type == IOMMU_DOMAIN_UNMANAGED) | |
3218 | dev_data->use_vapic = 1; | |
3219 | else | |
3220 | dev_data->use_vapic = 0; | |
3221 | } | |
3222 | #endif | |
3223 | ||
3224 | iommu_completion_wait(iommu); | |
3225 | ||
3226 | return ret; | |
3227 | } | |
3228 | ||
3229 | static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova, | |
3230 | phys_addr_t paddr, size_t page_size, int iommu_prot) | |
3231 | { | |
3232 | struct protection_domain *domain = to_pdomain(dom); | |
3233 | int prot = 0; | |
3234 | int ret; | |
3235 | ||
3236 | if (domain->mode == PAGE_MODE_NONE) | |
3237 | return -EINVAL; | |
3238 | ||
3239 | if (iommu_prot & IOMMU_READ) | |
3240 | prot |= IOMMU_PROT_IR; | |
3241 | if (iommu_prot & IOMMU_WRITE) | |
3242 | prot |= IOMMU_PROT_IW; | |
3243 | ||
3244 | mutex_lock(&domain->api_lock); | |
3245 | ret = iommu_map_page(domain, iova, paddr, page_size, prot, GFP_KERNEL); | |
3246 | mutex_unlock(&domain->api_lock); | |
3247 | ||
3248 | return ret; | |
3249 | } | |
3250 | ||
3251 | static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova, | |
3252 | size_t page_size) | |
3253 | { | |
3254 | struct protection_domain *domain = to_pdomain(dom); | |
3255 | size_t unmap_size; | |
3256 | ||
3257 | if (domain->mode == PAGE_MODE_NONE) | |
3258 | return -EINVAL; | |
3259 | ||
3260 | mutex_lock(&domain->api_lock); | |
3261 | unmap_size = iommu_unmap_page(domain, iova, page_size); | |
3262 | mutex_unlock(&domain->api_lock); | |
3263 | ||
3264 | domain_flush_tlb_pde(domain); | |
3265 | ||
3266 | return unmap_size; | |
3267 | } | |
3268 | ||
3269 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, | |
3270 | dma_addr_t iova) | |
3271 | { | |
3272 | struct protection_domain *domain = to_pdomain(dom); | |
3273 | unsigned long offset_mask, pte_pgsize; | |
3274 | u64 *pte, __pte; | |
3275 | ||
3276 | if (domain->mode == PAGE_MODE_NONE) | |
3277 | return iova; | |
3278 | ||
3279 | pte = fetch_pte(domain, iova, &pte_pgsize); | |
3280 | ||
3281 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) | |
3282 | return 0; | |
3283 | ||
3284 | offset_mask = pte_pgsize - 1; | |
3285 | __pte = *pte & PM_ADDR_MASK; | |
3286 | ||
3287 | return (__pte & ~offset_mask) | (iova & offset_mask); | |
3288 | } | |
3289 | ||
3290 | static bool amd_iommu_capable(enum iommu_cap cap) | |
3291 | { | |
3292 | switch (cap) { | |
3293 | case IOMMU_CAP_CACHE_COHERENCY: | |
3294 | return true; | |
3295 | case IOMMU_CAP_INTR_REMAP: | |
3296 | return (irq_remapping_enabled == 1); | |
3297 | case IOMMU_CAP_NOEXEC: | |
3298 | return false; | |
3299 | } | |
3300 | ||
3301 | return false; | |
3302 | } | |
3303 | ||
3304 | static void amd_iommu_get_resv_regions(struct device *dev, | |
3305 | struct list_head *head) | |
3306 | { | |
3307 | struct iommu_resv_region *region; | |
3308 | struct unity_map_entry *entry; | |
3309 | int devid; | |
3310 | ||
3311 | devid = get_device_id(dev); | |
3312 | if (devid < 0) | |
3313 | return; | |
3314 | ||
3315 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
3316 | size_t length; | |
3317 | int prot = 0; | |
3318 | ||
3319 | if (devid < entry->devid_start || devid > entry->devid_end) | |
3320 | continue; | |
3321 | ||
3322 | length = entry->address_end - entry->address_start; | |
3323 | if (entry->prot & IOMMU_PROT_IR) | |
3324 | prot |= IOMMU_READ; | |
3325 | if (entry->prot & IOMMU_PROT_IW) | |
3326 | prot |= IOMMU_WRITE; | |
3327 | ||
3328 | region = iommu_alloc_resv_region(entry->address_start, | |
3329 | length, prot, | |
3330 | IOMMU_RESV_DIRECT); | |
3331 | if (!region) { | |
3332 | pr_err("Out of memory allocating dm-regions for %s\n", | |
3333 | dev_name(dev)); | |
3334 | return; | |
3335 | } | |
3336 | list_add_tail(®ion->list, head); | |
3337 | } | |
3338 | ||
3339 | region = iommu_alloc_resv_region(MSI_RANGE_START, | |
3340 | MSI_RANGE_END - MSI_RANGE_START + 1, | |
3341 | 0, IOMMU_RESV_MSI); | |
3342 | if (!region) | |
3343 | return; | |
3344 | list_add_tail(®ion->list, head); | |
3345 | ||
3346 | region = iommu_alloc_resv_region(HT_RANGE_START, | |
3347 | HT_RANGE_END - HT_RANGE_START + 1, | |
3348 | 0, IOMMU_RESV_RESERVED); | |
3349 | if (!region) | |
3350 | return; | |
3351 | list_add_tail(®ion->list, head); | |
3352 | } | |
3353 | ||
3354 | static void amd_iommu_put_resv_regions(struct device *dev, | |
3355 | struct list_head *head) | |
3356 | { | |
3357 | struct iommu_resv_region *entry, *next; | |
3358 | ||
3359 | list_for_each_entry_safe(entry, next, head, list) | |
3360 | kfree(entry); | |
3361 | } | |
3362 | ||
3363 | static void amd_iommu_apply_resv_region(struct device *dev, | |
3364 | struct iommu_domain *domain, | |
3365 | struct iommu_resv_region *region) | |
3366 | { | |
3367 | struct dma_ops_domain *dma_dom = to_dma_ops_domain(to_pdomain(domain)); | |
3368 | unsigned long start, end; | |
3369 | ||
3370 | start = IOVA_PFN(region->start); | |
3371 | end = IOVA_PFN(region->start + region->length); | |
3372 | ||
3373 | WARN_ON_ONCE(reserve_iova(&dma_dom->iovad, start, end) == NULL); | |
3374 | } | |
3375 | ||
3376 | const struct iommu_ops amd_iommu_ops = { | |
3377 | .capable = amd_iommu_capable, | |
3378 | .domain_alloc = amd_iommu_domain_alloc, | |
3379 | .domain_free = amd_iommu_domain_free, | |
3380 | .attach_dev = amd_iommu_attach_device, | |
3381 | .detach_dev = amd_iommu_detach_device, | |
3382 | .map = amd_iommu_map, | |
3383 | .unmap = amd_iommu_unmap, | |
3384 | .map_sg = default_iommu_map_sg, | |
3385 | .iova_to_phys = amd_iommu_iova_to_phys, | |
3386 | .add_device = amd_iommu_add_device, | |
3387 | .remove_device = amd_iommu_remove_device, | |
3388 | .device_group = amd_iommu_device_group, | |
3389 | .get_resv_regions = amd_iommu_get_resv_regions, | |
3390 | .put_resv_regions = amd_iommu_put_resv_regions, | |
3391 | .apply_resv_region = amd_iommu_apply_resv_region, | |
3392 | .pgsize_bitmap = AMD_IOMMU_PGSIZES, | |
3393 | }; | |
3394 | ||
3395 | /***************************************************************************** | |
3396 | * | |
3397 | * The next functions do a basic initialization of IOMMU for pass through | |
3398 | * mode | |
3399 | * | |
3400 | * In passthrough mode the IOMMU is initialized and enabled but not used for | |
3401 | * DMA-API translation. | |
3402 | * | |
3403 | *****************************************************************************/ | |
3404 | ||
3405 | /* IOMMUv2 specific functions */ | |
3406 | int amd_iommu_register_ppr_notifier(struct notifier_block *nb) | |
3407 | { | |
3408 | return atomic_notifier_chain_register(&ppr_notifier, nb); | |
3409 | } | |
3410 | EXPORT_SYMBOL(amd_iommu_register_ppr_notifier); | |
3411 | ||
3412 | int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb) | |
3413 | { | |
3414 | return atomic_notifier_chain_unregister(&ppr_notifier, nb); | |
3415 | } | |
3416 | EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier); | |
3417 | ||
3418 | void amd_iommu_domain_direct_map(struct iommu_domain *dom) | |
3419 | { | |
3420 | struct protection_domain *domain = to_pdomain(dom); | |
3421 | unsigned long flags; | |
3422 | ||
3423 | spin_lock_irqsave(&domain->lock, flags); | |
3424 | ||
3425 | /* Update data structure */ | |
3426 | domain->mode = PAGE_MODE_NONE; | |
3427 | domain->updated = true; | |
3428 | ||
3429 | /* Make changes visible to IOMMUs */ | |
3430 | update_domain(domain); | |
3431 | ||
3432 | /* Page-table is not visible to IOMMU anymore, so free it */ | |
3433 | free_pagetable(domain); | |
3434 | ||
3435 | spin_unlock_irqrestore(&domain->lock, flags); | |
3436 | } | |
3437 | EXPORT_SYMBOL(amd_iommu_domain_direct_map); | |
3438 | ||
3439 | int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids) | |
3440 | { | |
3441 | struct protection_domain *domain = to_pdomain(dom); | |
3442 | unsigned long flags; | |
3443 | int levels, ret; | |
3444 | ||
3445 | if (pasids <= 0 || pasids > (PASID_MASK + 1)) | |
3446 | return -EINVAL; | |
3447 | ||
3448 | /* Number of GCR3 table levels required */ | |
3449 | for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9) | |
3450 | levels += 1; | |
3451 | ||
3452 | if (levels > amd_iommu_max_glx_val) | |
3453 | return -EINVAL; | |
3454 | ||
3455 | spin_lock_irqsave(&domain->lock, flags); | |
3456 | ||
3457 | /* | |
3458 | * Save us all sanity checks whether devices already in the | |
3459 | * domain support IOMMUv2. Just force that the domain has no | |
3460 | * devices attached when it is switched into IOMMUv2 mode. | |
3461 | */ | |
3462 | ret = -EBUSY; | |
3463 | if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK) | |
3464 | goto out; | |
3465 | ||
3466 | ret = -ENOMEM; | |
3467 | domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC); | |
3468 | if (domain->gcr3_tbl == NULL) | |
3469 | goto out; | |
3470 | ||
3471 | domain->glx = levels; | |
3472 | domain->flags |= PD_IOMMUV2_MASK; | |
3473 | domain->updated = true; | |
3474 | ||
3475 | update_domain(domain); | |
3476 | ||
3477 | ret = 0; | |
3478 | ||
3479 | out: | |
3480 | spin_unlock_irqrestore(&domain->lock, flags); | |
3481 | ||
3482 | return ret; | |
3483 | } | |
3484 | EXPORT_SYMBOL(amd_iommu_domain_enable_v2); | |
3485 | ||
3486 | static int __flush_pasid(struct protection_domain *domain, int pasid, | |
3487 | u64 address, bool size) | |
3488 | { | |
3489 | struct iommu_dev_data *dev_data; | |
3490 | struct iommu_cmd cmd; | |
3491 | int i, ret; | |
3492 | ||
3493 | if (!(domain->flags & PD_IOMMUV2_MASK)) | |
3494 | return -EINVAL; | |
3495 | ||
3496 | build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size); | |
3497 | ||
3498 | /* | |
3499 | * IOMMU TLB needs to be flushed before Device TLB to | |
3500 | * prevent device TLB refill from IOMMU TLB | |
3501 | */ | |
3502 | for (i = 0; i < amd_iommu_get_num_iommus(); ++i) { | |
3503 | if (domain->dev_iommu[i] == 0) | |
3504 | continue; | |
3505 | ||
3506 | ret = iommu_queue_command(amd_iommus[i], &cmd); | |
3507 | if (ret != 0) | |
3508 | goto out; | |
3509 | } | |
3510 | ||
3511 | /* Wait until IOMMU TLB flushes are complete */ | |
3512 | domain_flush_complete(domain); | |
3513 | ||
3514 | /* Now flush device TLBs */ | |
3515 | list_for_each_entry(dev_data, &domain->dev_list, list) { | |
3516 | struct amd_iommu *iommu; | |
3517 | int qdep; | |
3518 | ||
3519 | /* | |
3520 | There might be non-IOMMUv2 capable devices in an IOMMUv2 | |
3521 | * domain. | |
3522 | */ | |
3523 | if (!dev_data->ats.enabled) | |
3524 | continue; | |
3525 | ||
3526 | qdep = dev_data->ats.qdep; | |
3527 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3528 | ||
3529 | build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid, | |
3530 | qdep, address, size); | |
3531 | ||
3532 | ret = iommu_queue_command(iommu, &cmd); | |
3533 | if (ret != 0) | |
3534 | goto out; | |
3535 | } | |
3536 | ||
3537 | /* Wait until all device TLBs are flushed */ | |
3538 | domain_flush_complete(domain); | |
3539 | ||
3540 | ret = 0; | |
3541 | ||
3542 | out: | |
3543 | ||
3544 | return ret; | |
3545 | } | |
3546 | ||
3547 | static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid, | |
3548 | u64 address) | |
3549 | { | |
3550 | return __flush_pasid(domain, pasid, address, false); | |
3551 | } | |
3552 | ||
3553 | int amd_iommu_flush_page(struct iommu_domain *dom, int pasid, | |
3554 | u64 address) | |
3555 | { | |
3556 | struct protection_domain *domain = to_pdomain(dom); | |
3557 | unsigned long flags; | |
3558 | int ret; | |
3559 | ||
3560 | spin_lock_irqsave(&domain->lock, flags); | |
3561 | ret = __amd_iommu_flush_page(domain, pasid, address); | |
3562 | spin_unlock_irqrestore(&domain->lock, flags); | |
3563 | ||
3564 | return ret; | |
3565 | } | |
3566 | EXPORT_SYMBOL(amd_iommu_flush_page); | |
3567 | ||
3568 | static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid) | |
3569 | { | |
3570 | return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
3571 | true); | |
3572 | } | |
3573 | ||
3574 | int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid) | |
3575 | { | |
3576 | struct protection_domain *domain = to_pdomain(dom); | |
3577 | unsigned long flags; | |
3578 | int ret; | |
3579 | ||
3580 | spin_lock_irqsave(&domain->lock, flags); | |
3581 | ret = __amd_iommu_flush_tlb(domain, pasid); | |
3582 | spin_unlock_irqrestore(&domain->lock, flags); | |
3583 | ||
3584 | return ret; | |
3585 | } | |
3586 | EXPORT_SYMBOL(amd_iommu_flush_tlb); | |
3587 | ||
3588 | static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc) | |
3589 | { | |
3590 | int index; | |
3591 | u64 *pte; | |
3592 | ||
3593 | while (true) { | |
3594 | ||
3595 | index = (pasid >> (9 * level)) & 0x1ff; | |
3596 | pte = &root[index]; | |
3597 | ||
3598 | if (level == 0) | |
3599 | break; | |
3600 | ||
3601 | if (!(*pte & GCR3_VALID)) { | |
3602 | if (!alloc) | |
3603 | return NULL; | |
3604 | ||
3605 | root = (void *)get_zeroed_page(GFP_ATOMIC); | |
3606 | if (root == NULL) | |
3607 | return NULL; | |
3608 | ||
3609 | *pte = __pa(root) | GCR3_VALID; | |
3610 | } | |
3611 | ||
3612 | root = __va(*pte & PAGE_MASK); | |
3613 | ||
3614 | level -= 1; | |
3615 | } | |
3616 | ||
3617 | return pte; | |
3618 | } | |
3619 | ||
3620 | static int __set_gcr3(struct protection_domain *domain, int pasid, | |
3621 | unsigned long cr3) | |
3622 | { | |
3623 | u64 *pte; | |
3624 | ||
3625 | if (domain->mode != PAGE_MODE_NONE) | |
3626 | return -EINVAL; | |
3627 | ||
3628 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true); | |
3629 | if (pte == NULL) | |
3630 | return -ENOMEM; | |
3631 | ||
3632 | *pte = (cr3 & PAGE_MASK) | GCR3_VALID; | |
3633 | ||
3634 | return __amd_iommu_flush_tlb(domain, pasid); | |
3635 | } | |
3636 | ||
3637 | static int __clear_gcr3(struct protection_domain *domain, int pasid) | |
3638 | { | |
3639 | u64 *pte; | |
3640 | ||
3641 | if (domain->mode != PAGE_MODE_NONE) | |
3642 | return -EINVAL; | |
3643 | ||
3644 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false); | |
3645 | if (pte == NULL) | |
3646 | return 0; | |
3647 | ||
3648 | *pte = 0; | |
3649 | ||
3650 | return __amd_iommu_flush_tlb(domain, pasid); | |
3651 | } | |
3652 | ||
3653 | int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid, | |
3654 | unsigned long cr3) | |
3655 | { | |
3656 | struct protection_domain *domain = to_pdomain(dom); | |
3657 | unsigned long flags; | |
3658 | int ret; | |
3659 | ||
3660 | spin_lock_irqsave(&domain->lock, flags); | |
3661 | ret = __set_gcr3(domain, pasid, cr3); | |
3662 | spin_unlock_irqrestore(&domain->lock, flags); | |
3663 | ||
3664 | return ret; | |
3665 | } | |
3666 | EXPORT_SYMBOL(amd_iommu_domain_set_gcr3); | |
3667 | ||
3668 | int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid) | |
3669 | { | |
3670 | struct protection_domain *domain = to_pdomain(dom); | |
3671 | unsigned long flags; | |
3672 | int ret; | |
3673 | ||
3674 | spin_lock_irqsave(&domain->lock, flags); | |
3675 | ret = __clear_gcr3(domain, pasid); | |
3676 | spin_unlock_irqrestore(&domain->lock, flags); | |
3677 | ||
3678 | return ret; | |
3679 | } | |
3680 | EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3); | |
3681 | ||
3682 | int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid, | |
3683 | int status, int tag) | |
3684 | { | |
3685 | struct iommu_dev_data *dev_data; | |
3686 | struct amd_iommu *iommu; | |
3687 | struct iommu_cmd cmd; | |
3688 | ||
3689 | dev_data = get_dev_data(&pdev->dev); | |
3690 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3691 | ||
3692 | build_complete_ppr(&cmd, dev_data->devid, pasid, status, | |
3693 | tag, dev_data->pri_tlp); | |
3694 | ||
3695 | return iommu_queue_command(iommu, &cmd); | |
3696 | } | |
3697 | EXPORT_SYMBOL(amd_iommu_complete_ppr); | |
3698 | ||
3699 | struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev) | |
3700 | { | |
3701 | struct protection_domain *pdomain; | |
3702 | ||
3703 | pdomain = get_domain(&pdev->dev); | |
3704 | if (IS_ERR(pdomain)) | |
3705 | return NULL; | |
3706 | ||
3707 | /* Only return IOMMUv2 domains */ | |
3708 | if (!(pdomain->flags & PD_IOMMUV2_MASK)) | |
3709 | return NULL; | |
3710 | ||
3711 | return &pdomain->domain; | |
3712 | } | |
3713 | EXPORT_SYMBOL(amd_iommu_get_v2_domain); | |
3714 | ||
3715 | void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum) | |
3716 | { | |
3717 | struct iommu_dev_data *dev_data; | |
3718 | ||
3719 | if (!amd_iommu_v2_supported()) | |
3720 | return; | |
3721 | ||
3722 | dev_data = get_dev_data(&pdev->dev); | |
3723 | dev_data->errata |= (1 << erratum); | |
3724 | } | |
3725 | EXPORT_SYMBOL(amd_iommu_enable_device_erratum); | |
3726 | ||
3727 | int amd_iommu_device_info(struct pci_dev *pdev, | |
3728 | struct amd_iommu_device_info *info) | |
3729 | { | |
3730 | int max_pasids; | |
3731 | int pos; | |
3732 | ||
3733 | if (pdev == NULL || info == NULL) | |
3734 | return -EINVAL; | |
3735 | ||
3736 | if (!amd_iommu_v2_supported()) | |
3737 | return -EINVAL; | |
3738 | ||
3739 | memset(info, 0, sizeof(*info)); | |
3740 | ||
3741 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS); | |
3742 | if (pos) | |
3743 | info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP; | |
3744 | ||
3745 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); | |
3746 | if (pos) | |
3747 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP; | |
3748 | ||
3749 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID); | |
3750 | if (pos) { | |
3751 | int features; | |
3752 | ||
3753 | max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1)); | |
3754 | max_pasids = min(max_pasids, (1 << 20)); | |
3755 | ||
3756 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP; | |
3757 | info->max_pasids = min(pci_max_pasids(pdev), max_pasids); | |
3758 | ||
3759 | features = pci_pasid_features(pdev); | |
3760 | if (features & PCI_PASID_CAP_EXEC) | |
3761 | info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP; | |
3762 | if (features & PCI_PASID_CAP_PRIV) | |
3763 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP; | |
3764 | } | |
3765 | ||
3766 | return 0; | |
3767 | } | |
3768 | EXPORT_SYMBOL(amd_iommu_device_info); | |
3769 | ||
3770 | #ifdef CONFIG_IRQ_REMAP | |
3771 | ||
3772 | /***************************************************************************** | |
3773 | * | |
3774 | * Interrupt Remapping Implementation | |
3775 | * | |
3776 | *****************************************************************************/ | |
3777 | ||
3778 | static struct irq_chip amd_ir_chip; | |
3779 | ||
3780 | #define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6) | |
3781 | #define DTE_IRQ_REMAP_INTCTL (2ULL << 60) | |
3782 | #define DTE_IRQ_TABLE_LEN (8ULL << 1) | |
3783 | #define DTE_IRQ_REMAP_ENABLE 1ULL | |
3784 | ||
3785 | static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table) | |
3786 | { | |
3787 | u64 dte; | |
3788 | ||
3789 | dte = amd_iommu_dev_table[devid].data[2]; | |
3790 | dte &= ~DTE_IRQ_PHYS_ADDR_MASK; | |
3791 | dte |= virt_to_phys(table->table); | |
3792 | dte |= DTE_IRQ_REMAP_INTCTL; | |
3793 | dte |= DTE_IRQ_TABLE_LEN; | |
3794 | dte |= DTE_IRQ_REMAP_ENABLE; | |
3795 | ||
3796 | amd_iommu_dev_table[devid].data[2] = dte; | |
3797 | } | |
3798 | ||
3799 | static struct irq_remap_table *get_irq_table(u16 devid, bool ioapic) | |
3800 | { | |
3801 | struct irq_remap_table *table = NULL; | |
3802 | struct amd_iommu *iommu; | |
3803 | unsigned long flags; | |
3804 | u16 alias; | |
3805 | ||
3806 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
3807 | ||
3808 | iommu = amd_iommu_rlookup_table[devid]; | |
3809 | if (!iommu) | |
3810 | goto out_unlock; | |
3811 | ||
3812 | table = irq_lookup_table[devid]; | |
3813 | if (table) | |
3814 | goto out_unlock; | |
3815 | ||
3816 | alias = amd_iommu_alias_table[devid]; | |
3817 | table = irq_lookup_table[alias]; | |
3818 | if (table) { | |
3819 | irq_lookup_table[devid] = table; | |
3820 | set_dte_irq_entry(devid, table); | |
3821 | iommu_flush_dte(iommu, devid); | |
3822 | goto out; | |
3823 | } | |
3824 | ||
3825 | /* Nothing there yet, allocate new irq remapping table */ | |
3826 | table = kzalloc(sizeof(*table), GFP_ATOMIC); | |
3827 | if (!table) | |
3828 | goto out_unlock; | |
3829 | ||
3830 | /* Initialize table spin-lock */ | |
3831 | spin_lock_init(&table->lock); | |
3832 | ||
3833 | if (ioapic) | |
3834 | /* Keep the first 32 indexes free for IOAPIC interrupts */ | |
3835 | table->min_index = 32; | |
3836 | ||
3837 | table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_ATOMIC); | |
3838 | if (!table->table) { | |
3839 | kfree(table); | |
3840 | table = NULL; | |
3841 | goto out_unlock; | |
3842 | } | |
3843 | ||
3844 | if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir)) | |
3845 | memset(table->table, 0, | |
3846 | MAX_IRQS_PER_TABLE * sizeof(u32)); | |
3847 | else | |
3848 | memset(table->table, 0, | |
3849 | (MAX_IRQS_PER_TABLE * (sizeof(u64) * 2))); | |
3850 | ||
3851 | if (ioapic) { | |
3852 | int i; | |
3853 | ||
3854 | for (i = 0; i < 32; ++i) | |
3855 | iommu->irte_ops->set_allocated(table, i); | |
3856 | } | |
3857 | ||
3858 | irq_lookup_table[devid] = table; | |
3859 | set_dte_irq_entry(devid, table); | |
3860 | iommu_flush_dte(iommu, devid); | |
3861 | if (devid != alias) { | |
3862 | irq_lookup_table[alias] = table; | |
3863 | set_dte_irq_entry(alias, table); | |
3864 | iommu_flush_dte(iommu, alias); | |
3865 | } | |
3866 | ||
3867 | out: | |
3868 | iommu_completion_wait(iommu); | |
3869 | ||
3870 | out_unlock: | |
3871 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
3872 | ||
3873 | return table; | |
3874 | } | |
3875 | ||
3876 | static int alloc_irq_index(u16 devid, int count) | |
3877 | { | |
3878 | struct irq_remap_table *table; | |
3879 | unsigned long flags; | |
3880 | int index, c; | |
3881 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; | |
3882 | ||
3883 | if (!iommu) | |
3884 | return -ENODEV; | |
3885 | ||
3886 | table = get_irq_table(devid, false); | |
3887 | if (!table) | |
3888 | return -ENODEV; | |
3889 | ||
3890 | spin_lock_irqsave(&table->lock, flags); | |
3891 | ||
3892 | /* Scan table for free entries */ | |
3893 | for (c = 0, index = table->min_index; | |
3894 | index < MAX_IRQS_PER_TABLE; | |
3895 | ++index) { | |
3896 | if (!iommu->irte_ops->is_allocated(table, index)) | |
3897 | c += 1; | |
3898 | else | |
3899 | c = 0; | |
3900 | ||
3901 | if (c == count) { | |
3902 | for (; c != 0; --c) | |
3903 | iommu->irte_ops->set_allocated(table, index - c + 1); | |
3904 | ||
3905 | index -= count - 1; | |
3906 | goto out; | |
3907 | } | |
3908 | } | |
3909 | ||
3910 | index = -ENOSPC; | |
3911 | ||
3912 | out: | |
3913 | spin_unlock_irqrestore(&table->lock, flags); | |
3914 | ||
3915 | return index; | |
3916 | } | |
3917 | ||
3918 | static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte, | |
3919 | struct amd_ir_data *data) | |
3920 | { | |
3921 | struct irq_remap_table *table; | |
3922 | struct amd_iommu *iommu; | |
3923 | unsigned long flags; | |
3924 | struct irte_ga *entry; | |
3925 | ||
3926 | iommu = amd_iommu_rlookup_table[devid]; | |
3927 | if (iommu == NULL) | |
3928 | return -EINVAL; | |
3929 | ||
3930 | table = get_irq_table(devid, false); | |
3931 | if (!table) | |
3932 | return -ENOMEM; | |
3933 | ||
3934 | spin_lock_irqsave(&table->lock, flags); | |
3935 | ||
3936 | entry = (struct irte_ga *)table->table; | |
3937 | entry = &entry[index]; | |
3938 | entry->lo.fields_remap.valid = 0; | |
3939 | entry->hi.val = irte->hi.val; | |
3940 | entry->lo.val = irte->lo.val; | |
3941 | entry->lo.fields_remap.valid = 1; | |
3942 | if (data) | |
3943 | data->ref = entry; | |
3944 | ||
3945 | spin_unlock_irqrestore(&table->lock, flags); | |
3946 | ||
3947 | iommu_flush_irt(iommu, devid); | |
3948 | iommu_completion_wait(iommu); | |
3949 | ||
3950 | return 0; | |
3951 | } | |
3952 | ||
3953 | static int modify_irte(u16 devid, int index, union irte *irte) | |
3954 | { | |
3955 | struct irq_remap_table *table; | |
3956 | struct amd_iommu *iommu; | |
3957 | unsigned long flags; | |
3958 | ||
3959 | iommu = amd_iommu_rlookup_table[devid]; | |
3960 | if (iommu == NULL) | |
3961 | return -EINVAL; | |
3962 | ||
3963 | table = get_irq_table(devid, false); | |
3964 | if (!table) | |
3965 | return -ENOMEM; | |
3966 | ||
3967 | spin_lock_irqsave(&table->lock, flags); | |
3968 | table->table[index] = irte->val; | |
3969 | spin_unlock_irqrestore(&table->lock, flags); | |
3970 | ||
3971 | iommu_flush_irt(iommu, devid); | |
3972 | iommu_completion_wait(iommu); | |
3973 | ||
3974 | return 0; | |
3975 | } | |
3976 | ||
3977 | static void free_irte(u16 devid, int index) | |
3978 | { | |
3979 | struct irq_remap_table *table; | |
3980 | struct amd_iommu *iommu; | |
3981 | unsigned long flags; | |
3982 | ||
3983 | iommu = amd_iommu_rlookup_table[devid]; | |
3984 | if (iommu == NULL) | |
3985 | return; | |
3986 | ||
3987 | table = get_irq_table(devid, false); | |
3988 | if (!table) | |
3989 | return; | |
3990 | ||
3991 | spin_lock_irqsave(&table->lock, flags); | |
3992 | iommu->irte_ops->clear_allocated(table, index); | |
3993 | spin_unlock_irqrestore(&table->lock, flags); | |
3994 | ||
3995 | iommu_flush_irt(iommu, devid); | |
3996 | iommu_completion_wait(iommu); | |
3997 | } | |
3998 | ||
3999 | static void irte_prepare(void *entry, | |
4000 | u32 delivery_mode, u32 dest_mode, | |
4001 | u8 vector, u32 dest_apicid, int devid) | |
4002 | { | |
4003 | union irte *irte = (union irte *) entry; | |
4004 | ||
4005 | irte->val = 0; | |
4006 | irte->fields.vector = vector; | |
4007 | irte->fields.int_type = delivery_mode; | |
4008 | irte->fields.destination = dest_apicid; | |
4009 | irte->fields.dm = dest_mode; | |
4010 | irte->fields.valid = 1; | |
4011 | } | |
4012 | ||
4013 | static void irte_ga_prepare(void *entry, | |
4014 | u32 delivery_mode, u32 dest_mode, | |
4015 | u8 vector, u32 dest_apicid, int devid) | |
4016 | { | |
4017 | struct irte_ga *irte = (struct irte_ga *) entry; | |
4018 | ||
4019 | irte->lo.val = 0; | |
4020 | irte->hi.val = 0; | |
4021 | irte->lo.fields_remap.int_type = delivery_mode; | |
4022 | irte->lo.fields_remap.dm = dest_mode; | |
4023 | irte->hi.fields.vector = vector; | |
4024 | irte->lo.fields_remap.destination = dest_apicid; | |
4025 | irte->lo.fields_remap.valid = 1; | |
4026 | } | |
4027 | ||
4028 | static void irte_activate(void *entry, u16 devid, u16 index) | |
4029 | { | |
4030 | union irte *irte = (union irte *) entry; | |
4031 | ||
4032 | irte->fields.valid = 1; | |
4033 | modify_irte(devid, index, irte); | |
4034 | } | |
4035 | ||
4036 | static void irte_ga_activate(void *entry, u16 devid, u16 index) | |
4037 | { | |
4038 | struct irte_ga *irte = (struct irte_ga *) entry; | |
4039 | ||
4040 | irte->lo.fields_remap.valid = 1; | |
4041 | modify_irte_ga(devid, index, irte, NULL); | |
4042 | } | |
4043 | ||
4044 | static void irte_deactivate(void *entry, u16 devid, u16 index) | |
4045 | { | |
4046 | union irte *irte = (union irte *) entry; | |
4047 | ||
4048 | irte->fields.valid = 0; | |
4049 | modify_irte(devid, index, irte); | |
4050 | } | |
4051 | ||
4052 | static void irte_ga_deactivate(void *entry, u16 devid, u16 index) | |
4053 | { | |
4054 | struct irte_ga *irte = (struct irte_ga *) entry; | |
4055 | ||
4056 | irte->lo.fields_remap.valid = 0; | |
4057 | modify_irte_ga(devid, index, irte, NULL); | |
4058 | } | |
4059 | ||
4060 | static void irte_set_affinity(void *entry, u16 devid, u16 index, | |
4061 | u8 vector, u32 dest_apicid) | |
4062 | { | |
4063 | union irte *irte = (union irte *) entry; | |
4064 | ||
4065 | irte->fields.vector = vector; | |
4066 | irte->fields.destination = dest_apicid; | |
4067 | modify_irte(devid, index, irte); | |
4068 | } | |
4069 | ||
4070 | static void irte_ga_set_affinity(void *entry, u16 devid, u16 index, | |
4071 | u8 vector, u32 dest_apicid) | |
4072 | { | |
4073 | struct irte_ga *irte = (struct irte_ga *) entry; | |
4074 | struct iommu_dev_data *dev_data = search_dev_data(devid); | |
4075 | ||
4076 | if (!dev_data || !dev_data->use_vapic || | |
4077 | !irte->lo.fields_remap.guest_mode) { | |
4078 | irte->hi.fields.vector = vector; | |
4079 | irte->lo.fields_remap.destination = dest_apicid; | |
4080 | modify_irte_ga(devid, index, irte, NULL); | |
4081 | } | |
4082 | } | |
4083 | ||
4084 | #define IRTE_ALLOCATED (~1U) | |
4085 | static void irte_set_allocated(struct irq_remap_table *table, int index) | |
4086 | { | |
4087 | table->table[index] = IRTE_ALLOCATED; | |
4088 | } | |
4089 | ||
4090 | static void irte_ga_set_allocated(struct irq_remap_table *table, int index) | |
4091 | { | |
4092 | struct irte_ga *ptr = (struct irte_ga *)table->table; | |
4093 | struct irte_ga *irte = &ptr[index]; | |
4094 | ||
4095 | memset(&irte->lo.val, 0, sizeof(u64)); | |
4096 | memset(&irte->hi.val, 0, sizeof(u64)); | |
4097 | irte->hi.fields.vector = 0xff; | |
4098 | } | |
4099 | ||
4100 | static bool irte_is_allocated(struct irq_remap_table *table, int index) | |
4101 | { | |
4102 | union irte *ptr = (union irte *)table->table; | |
4103 | union irte *irte = &ptr[index]; | |
4104 | ||
4105 | return irte->val != 0; | |
4106 | } | |
4107 | ||
4108 | static bool irte_ga_is_allocated(struct irq_remap_table *table, int index) | |
4109 | { | |
4110 | struct irte_ga *ptr = (struct irte_ga *)table->table; | |
4111 | struct irte_ga *irte = &ptr[index]; | |
4112 | ||
4113 | return irte->hi.fields.vector != 0; | |
4114 | } | |
4115 | ||
4116 | static void irte_clear_allocated(struct irq_remap_table *table, int index) | |
4117 | { | |
4118 | table->table[index] = 0; | |
4119 | } | |
4120 | ||
4121 | static void irte_ga_clear_allocated(struct irq_remap_table *table, int index) | |
4122 | { | |
4123 | struct irte_ga *ptr = (struct irte_ga *)table->table; | |
4124 | struct irte_ga *irte = &ptr[index]; | |
4125 | ||
4126 | memset(&irte->lo.val, 0, sizeof(u64)); | |
4127 | memset(&irte->hi.val, 0, sizeof(u64)); | |
4128 | } | |
4129 | ||
4130 | static int get_devid(struct irq_alloc_info *info) | |
4131 | { | |
4132 | int devid = -1; | |
4133 | ||
4134 | switch (info->type) { | |
4135 | case X86_IRQ_ALLOC_TYPE_IOAPIC: | |
4136 | devid = get_ioapic_devid(info->ioapic_id); | |
4137 | break; | |
4138 | case X86_IRQ_ALLOC_TYPE_HPET: | |
4139 | devid = get_hpet_devid(info->hpet_id); | |
4140 | break; | |
4141 | case X86_IRQ_ALLOC_TYPE_MSI: | |
4142 | case X86_IRQ_ALLOC_TYPE_MSIX: | |
4143 | devid = get_device_id(&info->msi_dev->dev); | |
4144 | break; | |
4145 | default: | |
4146 | BUG_ON(1); | |
4147 | break; | |
4148 | } | |
4149 | ||
4150 | return devid; | |
4151 | } | |
4152 | ||
4153 | static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info) | |
4154 | { | |
4155 | struct amd_iommu *iommu; | |
4156 | int devid; | |
4157 | ||
4158 | if (!info) | |
4159 | return NULL; | |
4160 | ||
4161 | devid = get_devid(info); | |
4162 | if (devid >= 0) { | |
4163 | iommu = amd_iommu_rlookup_table[devid]; | |
4164 | if (iommu) | |
4165 | return iommu->ir_domain; | |
4166 | } | |
4167 | ||
4168 | return NULL; | |
4169 | } | |
4170 | ||
4171 | static struct irq_domain *get_irq_domain(struct irq_alloc_info *info) | |
4172 | { | |
4173 | struct amd_iommu *iommu; | |
4174 | int devid; | |
4175 | ||
4176 | if (!info) | |
4177 | return NULL; | |
4178 | ||
4179 | switch (info->type) { | |
4180 | case X86_IRQ_ALLOC_TYPE_MSI: | |
4181 | case X86_IRQ_ALLOC_TYPE_MSIX: | |
4182 | devid = get_device_id(&info->msi_dev->dev); | |
4183 | if (devid < 0) | |
4184 | return NULL; | |
4185 | ||
4186 | iommu = amd_iommu_rlookup_table[devid]; | |
4187 | if (iommu) | |
4188 | return iommu->msi_domain; | |
4189 | break; | |
4190 | default: | |
4191 | break; | |
4192 | } | |
4193 | ||
4194 | return NULL; | |
4195 | } | |
4196 | ||
4197 | struct irq_remap_ops amd_iommu_irq_ops = { | |
4198 | .prepare = amd_iommu_prepare, | |
4199 | .enable = amd_iommu_enable, | |
4200 | .disable = amd_iommu_disable, | |
4201 | .reenable = amd_iommu_reenable, | |
4202 | .enable_faulting = amd_iommu_enable_faulting, | |
4203 | .get_ir_irq_domain = get_ir_irq_domain, | |
4204 | .get_irq_domain = get_irq_domain, | |
4205 | }; | |
4206 | ||
4207 | static void irq_remapping_prepare_irte(struct amd_ir_data *data, | |
4208 | struct irq_cfg *irq_cfg, | |
4209 | struct irq_alloc_info *info, | |
4210 | int devid, int index, int sub_handle) | |
4211 | { | |
4212 | struct irq_2_irte *irte_info = &data->irq_2_irte; | |
4213 | struct msi_msg *msg = &data->msi_entry; | |
4214 | struct IO_APIC_route_entry *entry; | |
4215 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; | |
4216 | ||
4217 | if (!iommu) | |
4218 | return; | |
4219 | ||
4220 | data->irq_2_irte.devid = devid; | |
4221 | data->irq_2_irte.index = index + sub_handle; | |
4222 | iommu->irte_ops->prepare(data->entry, apic->irq_delivery_mode, | |
4223 | apic->irq_dest_mode, irq_cfg->vector, | |
4224 | irq_cfg->dest_apicid, devid); | |
4225 | ||
4226 | switch (info->type) { | |
4227 | case X86_IRQ_ALLOC_TYPE_IOAPIC: | |
4228 | /* Setup IOAPIC entry */ | |
4229 | entry = info->ioapic_entry; | |
4230 | info->ioapic_entry = NULL; | |
4231 | memset(entry, 0, sizeof(*entry)); | |
4232 | entry->vector = index; | |
4233 | entry->mask = 0; | |
4234 | entry->trigger = info->ioapic_trigger; | |
4235 | entry->polarity = info->ioapic_polarity; | |
4236 | /* Mask level triggered irqs. */ | |
4237 | if (info->ioapic_trigger) | |
4238 | entry->mask = 1; | |
4239 | break; | |
4240 | ||
4241 | case X86_IRQ_ALLOC_TYPE_HPET: | |
4242 | case X86_IRQ_ALLOC_TYPE_MSI: | |
4243 | case X86_IRQ_ALLOC_TYPE_MSIX: | |
4244 | msg->address_hi = MSI_ADDR_BASE_HI; | |
4245 | msg->address_lo = MSI_ADDR_BASE_LO; | |
4246 | msg->data = irte_info->index; | |
4247 | break; | |
4248 | ||
4249 | default: | |
4250 | BUG_ON(1); | |
4251 | break; | |
4252 | } | |
4253 | } | |
4254 | ||
4255 | struct amd_irte_ops irte_32_ops = { | |
4256 | .prepare = irte_prepare, | |
4257 | .activate = irte_activate, | |
4258 | .deactivate = irte_deactivate, | |
4259 | .set_affinity = irte_set_affinity, | |
4260 | .set_allocated = irte_set_allocated, | |
4261 | .is_allocated = irte_is_allocated, | |
4262 | .clear_allocated = irte_clear_allocated, | |
4263 | }; | |
4264 | ||
4265 | struct amd_irte_ops irte_128_ops = { | |
4266 | .prepare = irte_ga_prepare, | |
4267 | .activate = irte_ga_activate, | |
4268 | .deactivate = irte_ga_deactivate, | |
4269 | .set_affinity = irte_ga_set_affinity, | |
4270 | .set_allocated = irte_ga_set_allocated, | |
4271 | .is_allocated = irte_ga_is_allocated, | |
4272 | .clear_allocated = irte_ga_clear_allocated, | |
4273 | }; | |
4274 | ||
4275 | static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq, | |
4276 | unsigned int nr_irqs, void *arg) | |
4277 | { | |
4278 | struct irq_alloc_info *info = arg; | |
4279 | struct irq_data *irq_data; | |
4280 | struct amd_ir_data *data = NULL; | |
4281 | struct irq_cfg *cfg; | |
4282 | int i, ret, devid; | |
4283 | int index = -1; | |
4284 | ||
4285 | if (!info) | |
4286 | return -EINVAL; | |
4287 | if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI && | |
4288 | info->type != X86_IRQ_ALLOC_TYPE_MSIX) | |
4289 | return -EINVAL; | |
4290 | ||
4291 | /* | |
4292 | * With IRQ remapping enabled, don't need contiguous CPU vectors | |
4293 | * to support multiple MSI interrupts. | |
4294 | */ | |
4295 | if (info->type == X86_IRQ_ALLOC_TYPE_MSI) | |
4296 | info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS; | |
4297 | ||
4298 | devid = get_devid(info); | |
4299 | if (devid < 0) | |
4300 | return -EINVAL; | |
4301 | ||
4302 | ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg); | |
4303 | if (ret < 0) | |
4304 | return ret; | |
4305 | ||
4306 | if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) { | |
4307 | if (get_irq_table(devid, true)) | |
4308 | index = info->ioapic_pin; | |
4309 | else | |
4310 | ret = -ENOMEM; | |
4311 | } else { | |
4312 | index = alloc_irq_index(devid, nr_irqs); | |
4313 | } | |
4314 | if (index < 0) { | |
4315 | pr_warn("Failed to allocate IRTE\n"); | |
4316 | ret = index; | |
4317 | goto out_free_parent; | |
4318 | } | |
4319 | ||
4320 | for (i = 0; i < nr_irqs; i++) { | |
4321 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
4322 | cfg = irqd_cfg(irq_data); | |
4323 | if (!irq_data || !cfg) { | |
4324 | ret = -EINVAL; | |
4325 | goto out_free_data; | |
4326 | } | |
4327 | ||
4328 | ret = -ENOMEM; | |
4329 | data = kzalloc(sizeof(*data), GFP_KERNEL); | |
4330 | if (!data) | |
4331 | goto out_free_data; | |
4332 | ||
4333 | if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir)) | |
4334 | data->entry = kzalloc(sizeof(union irte), GFP_KERNEL); | |
4335 | else | |
4336 | data->entry = kzalloc(sizeof(struct irte_ga), | |
4337 | GFP_KERNEL); | |
4338 | if (!data->entry) { | |
4339 | kfree(data); | |
4340 | goto out_free_data; | |
4341 | } | |
4342 | ||
4343 | irq_data->hwirq = (devid << 16) + i; | |
4344 | irq_data->chip_data = data; | |
4345 | irq_data->chip = &amd_ir_chip; | |
4346 | irq_remapping_prepare_irte(data, cfg, info, devid, index, i); | |
4347 | irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT); | |
4348 | } | |
4349 | ||
4350 | return 0; | |
4351 | ||
4352 | out_free_data: | |
4353 | for (i--; i >= 0; i--) { | |
4354 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
4355 | if (irq_data) | |
4356 | kfree(irq_data->chip_data); | |
4357 | } | |
4358 | for (i = 0; i < nr_irqs; i++) | |
4359 | free_irte(devid, index + i); | |
4360 | out_free_parent: | |
4361 | irq_domain_free_irqs_common(domain, virq, nr_irqs); | |
4362 | return ret; | |
4363 | } | |
4364 | ||
4365 | static void irq_remapping_free(struct irq_domain *domain, unsigned int virq, | |
4366 | unsigned int nr_irqs) | |
4367 | { | |
4368 | struct irq_2_irte *irte_info; | |
4369 | struct irq_data *irq_data; | |
4370 | struct amd_ir_data *data; | |
4371 | int i; | |
4372 | ||
4373 | for (i = 0; i < nr_irqs; i++) { | |
4374 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
4375 | if (irq_data && irq_data->chip_data) { | |
4376 | data = irq_data->chip_data; | |
4377 | irte_info = &data->irq_2_irte; | |
4378 | free_irte(irte_info->devid, irte_info->index); | |
4379 | kfree(data->entry); | |
4380 | kfree(data); | |
4381 | } | |
4382 | } | |
4383 | irq_domain_free_irqs_common(domain, virq, nr_irqs); | |
4384 | } | |
4385 | ||
4386 | static void irq_remapping_activate(struct irq_domain *domain, | |
4387 | struct irq_data *irq_data) | |
4388 | { | |
4389 | struct amd_ir_data *data = irq_data->chip_data; | |
4390 | struct irq_2_irte *irte_info = &data->irq_2_irte; | |
4391 | struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid]; | |
4392 | ||
4393 | if (iommu) | |
4394 | iommu->irte_ops->activate(data->entry, irte_info->devid, | |
4395 | irte_info->index); | |
4396 | } | |
4397 | ||
4398 | static void irq_remapping_deactivate(struct irq_domain *domain, | |
4399 | struct irq_data *irq_data) | |
4400 | { | |
4401 | struct amd_ir_data *data = irq_data->chip_data; | |
4402 | struct irq_2_irte *irte_info = &data->irq_2_irte; | |
4403 | struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid]; | |
4404 | ||
4405 | if (iommu) | |
4406 | iommu->irte_ops->deactivate(data->entry, irte_info->devid, | |
4407 | irte_info->index); | |
4408 | } | |
4409 | ||
4410 | static const struct irq_domain_ops amd_ir_domain_ops = { | |
4411 | .alloc = irq_remapping_alloc, | |
4412 | .free = irq_remapping_free, | |
4413 | .activate = irq_remapping_activate, | |
4414 | .deactivate = irq_remapping_deactivate, | |
4415 | }; | |
4416 | ||
4417 | static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info) | |
4418 | { | |
4419 | struct amd_iommu *iommu; | |
4420 | struct amd_iommu_pi_data *pi_data = vcpu_info; | |
4421 | struct vcpu_data *vcpu_pi_info = pi_data->vcpu_data; | |
4422 | struct amd_ir_data *ir_data = data->chip_data; | |
4423 | struct irte_ga *irte = (struct irte_ga *) ir_data->entry; | |
4424 | struct irq_2_irte *irte_info = &ir_data->irq_2_irte; | |
4425 | struct iommu_dev_data *dev_data = search_dev_data(irte_info->devid); | |
4426 | ||
4427 | /* Note: | |
4428 | * This device has never been set up for guest mode. | |
4429 | * we should not modify the IRTE | |
4430 | */ | |
4431 | if (!dev_data || !dev_data->use_vapic) | |
4432 | return 0; | |
4433 | ||
4434 | pi_data->ir_data = ir_data; | |
4435 | ||
4436 | /* Note: | |
4437 | * SVM tries to set up for VAPIC mode, but we are in | |
4438 | * legacy mode. So, we force legacy mode instead. | |
4439 | */ | |
4440 | if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) { | |
4441 | pr_debug("AMD-Vi: %s: Fall back to using intr legacy remap\n", | |
4442 | __func__); | |
4443 | pi_data->is_guest_mode = false; | |
4444 | } | |
4445 | ||
4446 | iommu = amd_iommu_rlookup_table[irte_info->devid]; | |
4447 | if (iommu == NULL) | |
4448 | return -EINVAL; | |
4449 | ||
4450 | pi_data->prev_ga_tag = ir_data->cached_ga_tag; | |
4451 | if (pi_data->is_guest_mode) { | |
4452 | /* Setting */ | |
4453 | irte->hi.fields.ga_root_ptr = (pi_data->base >> 12); | |
4454 | irte->hi.fields.vector = vcpu_pi_info->vector; | |
4455 | irte->lo.fields_vapic.ga_log_intr = 1; | |
4456 | irte->lo.fields_vapic.guest_mode = 1; | |
4457 | irte->lo.fields_vapic.ga_tag = pi_data->ga_tag; | |
4458 | ||
4459 | ir_data->cached_ga_tag = pi_data->ga_tag; | |
4460 | } else { | |
4461 | /* Un-Setting */ | |
4462 | struct irq_cfg *cfg = irqd_cfg(data); | |
4463 | ||
4464 | irte->hi.val = 0; | |
4465 | irte->lo.val = 0; | |
4466 | irte->hi.fields.vector = cfg->vector; | |
4467 | irte->lo.fields_remap.guest_mode = 0; | |
4468 | irte->lo.fields_remap.destination = cfg->dest_apicid; | |
4469 | irte->lo.fields_remap.int_type = apic->irq_delivery_mode; | |
4470 | irte->lo.fields_remap.dm = apic->irq_dest_mode; | |
4471 | ||
4472 | /* | |
4473 | * This communicates the ga_tag back to the caller | |
4474 | * so that it can do all the necessary clean up. | |
4475 | */ | |
4476 | ir_data->cached_ga_tag = 0; | |
4477 | } | |
4478 | ||
4479 | return modify_irte_ga(irte_info->devid, irte_info->index, irte, ir_data); | |
4480 | } | |
4481 | ||
4482 | static int amd_ir_set_affinity(struct irq_data *data, | |
4483 | const struct cpumask *mask, bool force) | |
4484 | { | |
4485 | struct amd_ir_data *ir_data = data->chip_data; | |
4486 | struct irq_2_irte *irte_info = &ir_data->irq_2_irte; | |
4487 | struct irq_cfg *cfg = irqd_cfg(data); | |
4488 | struct irq_data *parent = data->parent_data; | |
4489 | struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid]; | |
4490 | int ret; | |
4491 | ||
4492 | if (!iommu) | |
4493 | return -ENODEV; | |
4494 | ||
4495 | ret = parent->chip->irq_set_affinity(parent, mask, force); | |
4496 | if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE) | |
4497 | return ret; | |
4498 | ||
4499 | /* | |
4500 | * Atomically updates the IRTE with the new destination, vector | |
4501 | * and flushes the interrupt entry cache. | |
4502 | */ | |
4503 | iommu->irte_ops->set_affinity(ir_data->entry, irte_info->devid, | |
4504 | irte_info->index, cfg->vector, cfg->dest_apicid); | |
4505 | ||
4506 | /* | |
4507 | * After this point, all the interrupts will start arriving | |
4508 | * at the new destination. So, time to cleanup the previous | |
4509 | * vector allocation. | |
4510 | */ | |
4511 | send_cleanup_vector(cfg); | |
4512 | ||
4513 | return IRQ_SET_MASK_OK_DONE; | |
4514 | } | |
4515 | ||
4516 | static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg) | |
4517 | { | |
4518 | struct amd_ir_data *ir_data = irq_data->chip_data; | |
4519 | ||
4520 | *msg = ir_data->msi_entry; | |
4521 | } | |
4522 | ||
4523 | static struct irq_chip amd_ir_chip = { | |
4524 | .name = "AMD-IR", | |
4525 | .irq_ack = ir_ack_apic_edge, | |
4526 | .irq_set_affinity = amd_ir_set_affinity, | |
4527 | .irq_set_vcpu_affinity = amd_ir_set_vcpu_affinity, | |
4528 | .irq_compose_msi_msg = ir_compose_msi_msg, | |
4529 | }; | |
4530 | ||
4531 | int amd_iommu_create_irq_domain(struct amd_iommu *iommu) | |
4532 | { | |
4533 | struct fwnode_handle *fn; | |
4534 | ||
4535 | fn = irq_domain_alloc_named_id_fwnode("AMD-IR", iommu->index); | |
4536 | if (!fn) | |
4537 | return -ENOMEM; | |
4538 | iommu->ir_domain = irq_domain_create_tree(fn, &amd_ir_domain_ops, iommu); | |
4539 | irq_domain_free_fwnode(fn); | |
4540 | if (!iommu->ir_domain) | |
4541 | return -ENOMEM; | |
4542 | ||
4543 | iommu->ir_domain->parent = arch_get_ir_parent_domain(); | |
4544 | iommu->msi_domain = arch_create_remap_msi_irq_domain(iommu->ir_domain, | |
4545 | "AMD-IR-MSI", | |
4546 | iommu->index); | |
4547 | return 0; | |
4548 | } | |
4549 | ||
4550 | int amd_iommu_update_ga(int cpu, bool is_run, void *data) | |
4551 | { | |
4552 | unsigned long flags; | |
4553 | struct amd_iommu *iommu; | |
4554 | struct irq_remap_table *irt; | |
4555 | struct amd_ir_data *ir_data = (struct amd_ir_data *)data; | |
4556 | int devid = ir_data->irq_2_irte.devid; | |
4557 | struct irte_ga *entry = (struct irte_ga *) ir_data->entry; | |
4558 | struct irte_ga *ref = (struct irte_ga *) ir_data->ref; | |
4559 | ||
4560 | if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) || | |
4561 | !ref || !entry || !entry->lo.fields_vapic.guest_mode) | |
4562 | return 0; | |
4563 | ||
4564 | iommu = amd_iommu_rlookup_table[devid]; | |
4565 | if (!iommu) | |
4566 | return -ENODEV; | |
4567 | ||
4568 | irt = get_irq_table(devid, false); | |
4569 | if (!irt) | |
4570 | return -ENODEV; | |
4571 | ||
4572 | spin_lock_irqsave(&irt->lock, flags); | |
4573 | ||
4574 | if (ref->lo.fields_vapic.guest_mode) { | |
4575 | if (cpu >= 0) | |
4576 | ref->lo.fields_vapic.destination = cpu; | |
4577 | ref->lo.fields_vapic.is_run = is_run; | |
4578 | barrier(); | |
4579 | } | |
4580 | ||
4581 | spin_unlock_irqrestore(&irt->lock, flags); | |
4582 | ||
4583 | iommu_flush_irt(iommu, devid); | |
4584 | iommu_completion_wait(iommu); | |
4585 | return 0; | |
4586 | } | |
4587 | EXPORT_SYMBOL(amd_iommu_update_ga); | |
4588 | #endif |