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1 | /* | |
2 | * adv7604 - Analog Devices ADV7604 video decoder driver | |
3 | * | |
4 | * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved. | |
5 | * | |
6 | * This program is free software; you may redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; version 2 of the License. | |
9 | * | |
10 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
11 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
12 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
13 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
14 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
15 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
16 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
17 | * SOFTWARE. | |
18 | * | |
19 | */ | |
20 | ||
21 | /* | |
22 | * References (c = chapter, p = page): | |
23 | * REF_01 - Analog devices, ADV7604, Register Settings Recommendations, | |
24 | * Revision 2.5, June 2010 | |
25 | * REF_02 - Analog devices, Register map documentation, Documentation of | |
26 | * the register maps, Software manual, Rev. F, June 2010 | |
27 | * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010 | |
28 | */ | |
29 | ||
30 | #include <linux/delay.h> | |
31 | #include <linux/gpio/consumer.h> | |
32 | #include <linux/i2c.h> | |
33 | #include <linux/kernel.h> | |
34 | #include <linux/module.h> | |
35 | #include <linux/slab.h> | |
36 | #include <linux/v4l2-dv-timings.h> | |
37 | #include <linux/videodev2.h> | |
38 | #include <linux/workqueue.h> | |
39 | ||
40 | #include <media/adv7604.h> | |
41 | #include <media/v4l2-ctrls.h> | |
42 | #include <media/v4l2-device.h> | |
43 | #include <media/v4l2-dv-timings.h> | |
44 | ||
45 | static int debug; | |
46 | module_param(debug, int, 0644); | |
47 | MODULE_PARM_DESC(debug, "debug level (0-2)"); | |
48 | ||
49 | MODULE_DESCRIPTION("Analog Devices ADV7604 video decoder driver"); | |
50 | MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>"); | |
51 | MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>"); | |
52 | MODULE_LICENSE("GPL"); | |
53 | ||
54 | /* ADV7604 system clock frequency */ | |
55 | #define ADV7604_fsc (28636360) | |
56 | ||
57 | #define ADV7604_RGB_OUT (1 << 1) | |
58 | ||
59 | #define ADV7604_OP_FORMAT_SEL_8BIT (0 << 0) | |
60 | #define ADV7604_OP_FORMAT_SEL_10BIT (1 << 0) | |
61 | #define ADV7604_OP_FORMAT_SEL_12BIT (2 << 0) | |
62 | ||
63 | #define ADV7604_OP_MODE_SEL_SDR_422 (0 << 5) | |
64 | #define ADV7604_OP_MODE_SEL_DDR_422 (1 << 5) | |
65 | #define ADV7604_OP_MODE_SEL_SDR_444 (2 << 5) | |
66 | #define ADV7604_OP_MODE_SEL_DDR_444 (3 << 5) | |
67 | #define ADV7604_OP_MODE_SEL_SDR_422_2X (4 << 5) | |
68 | #define ADV7604_OP_MODE_SEL_ADI_CM (5 << 5) | |
69 | ||
70 | #define ADV7604_OP_CH_SEL_GBR (0 << 5) | |
71 | #define ADV7604_OP_CH_SEL_GRB (1 << 5) | |
72 | #define ADV7604_OP_CH_SEL_BGR (2 << 5) | |
73 | #define ADV7604_OP_CH_SEL_RGB (3 << 5) | |
74 | #define ADV7604_OP_CH_SEL_BRG (4 << 5) | |
75 | #define ADV7604_OP_CH_SEL_RBG (5 << 5) | |
76 | ||
77 | #define ADV7604_OP_SWAP_CB_CR (1 << 0) | |
78 | ||
79 | enum adv7604_type { | |
80 | ADV7604, | |
81 | ADV7611, | |
82 | }; | |
83 | ||
84 | struct adv7604_reg_seq { | |
85 | unsigned int reg; | |
86 | u8 val; | |
87 | }; | |
88 | ||
89 | struct adv7604_format_info { | |
90 | enum v4l2_mbus_pixelcode code; | |
91 | u8 op_ch_sel; | |
92 | bool rgb_out; | |
93 | bool swap_cb_cr; | |
94 | u8 op_format_sel; | |
95 | }; | |
96 | ||
97 | struct adv7604_chip_info { | |
98 | enum adv7604_type type; | |
99 | ||
100 | bool has_afe; | |
101 | unsigned int max_port; | |
102 | unsigned int num_dv_ports; | |
103 | ||
104 | unsigned int edid_enable_reg; | |
105 | unsigned int edid_status_reg; | |
106 | unsigned int lcf_reg; | |
107 | ||
108 | unsigned int cable_det_mask; | |
109 | unsigned int tdms_lock_mask; | |
110 | unsigned int fmt_change_digital_mask; | |
111 | ||
112 | const struct adv7604_format_info *formats; | |
113 | unsigned int nformats; | |
114 | ||
115 | void (*set_termination)(struct v4l2_subdev *sd, bool enable); | |
116 | void (*setup_irqs)(struct v4l2_subdev *sd); | |
117 | unsigned int (*read_hdmi_pixelclock)(struct v4l2_subdev *sd); | |
118 | unsigned int (*read_cable_det)(struct v4l2_subdev *sd); | |
119 | ||
120 | /* 0 = AFE, 1 = HDMI */ | |
121 | const struct adv7604_reg_seq *recommended_settings[2]; | |
122 | unsigned int num_recommended_settings[2]; | |
123 | ||
124 | unsigned long page_mask; | |
125 | }; | |
126 | ||
127 | /* | |
128 | ********************************************************************** | |
129 | * | |
130 | * Arrays with configuration parameters for the ADV7604 | |
131 | * | |
132 | ********************************************************************** | |
133 | */ | |
134 | ||
135 | struct adv7604_state { | |
136 | const struct adv7604_chip_info *info; | |
137 | struct adv7604_platform_data pdata; | |
138 | ||
139 | struct gpio_desc *hpd_gpio[4]; | |
140 | ||
141 | struct v4l2_subdev sd; | |
142 | struct media_pad pads[ADV7604_PAD_MAX]; | |
143 | unsigned int source_pad; | |
144 | ||
145 | struct v4l2_ctrl_handler hdl; | |
146 | ||
147 | enum adv7604_pad selected_input; | |
148 | ||
149 | struct v4l2_dv_timings timings; | |
150 | const struct adv7604_format_info *format; | |
151 | ||
152 | struct { | |
153 | u8 edid[256]; | |
154 | u32 present; | |
155 | unsigned blocks; | |
156 | } edid; | |
157 | u16 spa_port_a[2]; | |
158 | struct v4l2_fract aspect_ratio; | |
159 | u32 rgb_quantization_range; | |
160 | struct workqueue_struct *work_queues; | |
161 | struct delayed_work delayed_work_enable_hotplug; | |
162 | bool restart_stdi_once; | |
163 | ||
164 | /* i2c clients */ | |
165 | struct i2c_client *i2c_clients[ADV7604_PAGE_MAX]; | |
166 | ||
167 | /* controls */ | |
168 | struct v4l2_ctrl *detect_tx_5v_ctrl; | |
169 | struct v4l2_ctrl *analog_sampling_phase_ctrl; | |
170 | struct v4l2_ctrl *free_run_color_manual_ctrl; | |
171 | struct v4l2_ctrl *free_run_color_ctrl; | |
172 | struct v4l2_ctrl *rgb_quantization_range_ctrl; | |
173 | }; | |
174 | ||
175 | static bool adv7604_has_afe(struct adv7604_state *state) | |
176 | { | |
177 | return state->info->has_afe; | |
178 | } | |
179 | ||
180 | /* Supported CEA and DMT timings */ | |
181 | static const struct v4l2_dv_timings adv7604_timings[] = { | |
182 | V4L2_DV_BT_CEA_720X480P59_94, | |
183 | V4L2_DV_BT_CEA_720X576P50, | |
184 | V4L2_DV_BT_CEA_1280X720P24, | |
185 | V4L2_DV_BT_CEA_1280X720P25, | |
186 | V4L2_DV_BT_CEA_1280X720P50, | |
187 | V4L2_DV_BT_CEA_1280X720P60, | |
188 | V4L2_DV_BT_CEA_1920X1080P24, | |
189 | V4L2_DV_BT_CEA_1920X1080P25, | |
190 | V4L2_DV_BT_CEA_1920X1080P30, | |
191 | V4L2_DV_BT_CEA_1920X1080P50, | |
192 | V4L2_DV_BT_CEA_1920X1080P60, | |
193 | ||
194 | /* sorted by DMT ID */ | |
195 | V4L2_DV_BT_DMT_640X350P85, | |
196 | V4L2_DV_BT_DMT_640X400P85, | |
197 | V4L2_DV_BT_DMT_720X400P85, | |
198 | V4L2_DV_BT_DMT_640X480P60, | |
199 | V4L2_DV_BT_DMT_640X480P72, | |
200 | V4L2_DV_BT_DMT_640X480P75, | |
201 | V4L2_DV_BT_DMT_640X480P85, | |
202 | V4L2_DV_BT_DMT_800X600P56, | |
203 | V4L2_DV_BT_DMT_800X600P60, | |
204 | V4L2_DV_BT_DMT_800X600P72, | |
205 | V4L2_DV_BT_DMT_800X600P75, | |
206 | V4L2_DV_BT_DMT_800X600P85, | |
207 | V4L2_DV_BT_DMT_848X480P60, | |
208 | V4L2_DV_BT_DMT_1024X768P60, | |
209 | V4L2_DV_BT_DMT_1024X768P70, | |
210 | V4L2_DV_BT_DMT_1024X768P75, | |
211 | V4L2_DV_BT_DMT_1024X768P85, | |
212 | V4L2_DV_BT_DMT_1152X864P75, | |
213 | V4L2_DV_BT_DMT_1280X768P60_RB, | |
214 | V4L2_DV_BT_DMT_1280X768P60, | |
215 | V4L2_DV_BT_DMT_1280X768P75, | |
216 | V4L2_DV_BT_DMT_1280X768P85, | |
217 | V4L2_DV_BT_DMT_1280X800P60_RB, | |
218 | V4L2_DV_BT_DMT_1280X800P60, | |
219 | V4L2_DV_BT_DMT_1280X800P75, | |
220 | V4L2_DV_BT_DMT_1280X800P85, | |
221 | V4L2_DV_BT_DMT_1280X960P60, | |
222 | V4L2_DV_BT_DMT_1280X960P85, | |
223 | V4L2_DV_BT_DMT_1280X1024P60, | |
224 | V4L2_DV_BT_DMT_1280X1024P75, | |
225 | V4L2_DV_BT_DMT_1280X1024P85, | |
226 | V4L2_DV_BT_DMT_1360X768P60, | |
227 | V4L2_DV_BT_DMT_1400X1050P60_RB, | |
228 | V4L2_DV_BT_DMT_1400X1050P60, | |
229 | V4L2_DV_BT_DMT_1400X1050P75, | |
230 | V4L2_DV_BT_DMT_1400X1050P85, | |
231 | V4L2_DV_BT_DMT_1440X900P60_RB, | |
232 | V4L2_DV_BT_DMT_1440X900P60, | |
233 | V4L2_DV_BT_DMT_1600X1200P60, | |
234 | V4L2_DV_BT_DMT_1680X1050P60_RB, | |
235 | V4L2_DV_BT_DMT_1680X1050P60, | |
236 | V4L2_DV_BT_DMT_1792X1344P60, | |
237 | V4L2_DV_BT_DMT_1856X1392P60, | |
238 | V4L2_DV_BT_DMT_1920X1200P60_RB, | |
239 | V4L2_DV_BT_DMT_1366X768P60_RB, | |
240 | V4L2_DV_BT_DMT_1366X768P60, | |
241 | V4L2_DV_BT_DMT_1920X1080P60, | |
242 | { }, | |
243 | }; | |
244 | ||
245 | struct adv7604_video_standards { | |
246 | struct v4l2_dv_timings timings; | |
247 | u8 vid_std; | |
248 | u8 v_freq; | |
249 | }; | |
250 | ||
251 | /* sorted by number of lines */ | |
252 | static const struct adv7604_video_standards adv7604_prim_mode_comp[] = { | |
253 | /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */ | |
254 | { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, | |
255 | { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 }, | |
256 | { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 }, | |
257 | { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 }, | |
258 | { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 }, | |
259 | { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 }, | |
260 | { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 }, | |
261 | { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 }, | |
262 | /* TODO add 1920x1080P60_RB (CVT timing) */ | |
263 | { }, | |
264 | }; | |
265 | ||
266 | /* sorted by number of lines */ | |
267 | static const struct adv7604_video_standards adv7604_prim_mode_gr[] = { | |
268 | { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, | |
269 | { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, | |
270 | { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, | |
271 | { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 }, | |
272 | { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 }, | |
273 | { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 }, | |
274 | { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 }, | |
275 | { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 }, | |
276 | { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 }, | |
277 | { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 }, | |
278 | { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 }, | |
279 | { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 }, | |
280 | { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 }, | |
281 | { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 }, | |
282 | { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 }, | |
283 | { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 }, | |
284 | { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 }, | |
285 | { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 }, | |
286 | { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 }, | |
287 | { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */ | |
288 | /* TODO add 1600X1200P60_RB (not a DMT timing) */ | |
289 | { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 }, | |
290 | { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */ | |
291 | { }, | |
292 | }; | |
293 | ||
294 | /* sorted by number of lines */ | |
295 | static const struct adv7604_video_standards adv7604_prim_mode_hdmi_comp[] = { | |
296 | { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, | |
297 | { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, | |
298 | { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 }, | |
299 | { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 }, | |
300 | { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 }, | |
301 | { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 }, | |
302 | { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 }, | |
303 | { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 }, | |
304 | { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 }, | |
305 | { }, | |
306 | }; | |
307 | ||
308 | /* sorted by number of lines */ | |
309 | static const struct adv7604_video_standards adv7604_prim_mode_hdmi_gr[] = { | |
310 | { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, | |
311 | { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, | |
312 | { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, | |
313 | { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 }, | |
314 | { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 }, | |
315 | { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 }, | |
316 | { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 }, | |
317 | { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 }, | |
318 | { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 }, | |
319 | { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 }, | |
320 | { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 }, | |
321 | { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 }, | |
322 | { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 }, | |
323 | { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 }, | |
324 | { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 }, | |
325 | { }, | |
326 | }; | |
327 | ||
328 | /* ----------------------------------------------------------------------- */ | |
329 | ||
330 | static inline struct adv7604_state *to_state(struct v4l2_subdev *sd) | |
331 | { | |
332 | return container_of(sd, struct adv7604_state, sd); | |
333 | } | |
334 | ||
335 | static inline unsigned hblanking(const struct v4l2_bt_timings *t) | |
336 | { | |
337 | return V4L2_DV_BT_BLANKING_WIDTH(t); | |
338 | } | |
339 | ||
340 | static inline unsigned htotal(const struct v4l2_bt_timings *t) | |
341 | { | |
342 | return V4L2_DV_BT_FRAME_WIDTH(t); | |
343 | } | |
344 | ||
345 | static inline unsigned vblanking(const struct v4l2_bt_timings *t) | |
346 | { | |
347 | return V4L2_DV_BT_BLANKING_HEIGHT(t); | |
348 | } | |
349 | ||
350 | static inline unsigned vtotal(const struct v4l2_bt_timings *t) | |
351 | { | |
352 | return V4L2_DV_BT_FRAME_HEIGHT(t); | |
353 | } | |
354 | ||
355 | /* ----------------------------------------------------------------------- */ | |
356 | ||
357 | static s32 adv_smbus_read_byte_data_check(struct i2c_client *client, | |
358 | u8 command, bool check) | |
359 | { | |
360 | union i2c_smbus_data data; | |
361 | ||
362 | if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags, | |
363 | I2C_SMBUS_READ, command, | |
364 | I2C_SMBUS_BYTE_DATA, &data)) | |
365 | return data.byte; | |
366 | if (check) | |
367 | v4l_err(client, "error reading %02x, %02x\n", | |
368 | client->addr, command); | |
369 | return -EIO; | |
370 | } | |
371 | ||
372 | static s32 adv_smbus_read_byte_data(struct adv7604_state *state, | |
373 | enum adv7604_page page, u8 command) | |
374 | { | |
375 | return adv_smbus_read_byte_data_check(state->i2c_clients[page], | |
376 | command, true); | |
377 | } | |
378 | ||
379 | static s32 adv_smbus_write_byte_data(struct adv7604_state *state, | |
380 | enum adv7604_page page, u8 command, | |
381 | u8 value) | |
382 | { | |
383 | struct i2c_client *client = state->i2c_clients[page]; | |
384 | union i2c_smbus_data data; | |
385 | int err; | |
386 | int i; | |
387 | ||
388 | data.byte = value; | |
389 | for (i = 0; i < 3; i++) { | |
390 | err = i2c_smbus_xfer(client->adapter, client->addr, | |
391 | client->flags, | |
392 | I2C_SMBUS_WRITE, command, | |
393 | I2C_SMBUS_BYTE_DATA, &data); | |
394 | if (!err) | |
395 | break; | |
396 | } | |
397 | if (err < 0) | |
398 | v4l_err(client, "error writing %02x, %02x, %02x\n", | |
399 | client->addr, command, value); | |
400 | return err; | |
401 | } | |
402 | ||
403 | static s32 adv_smbus_write_i2c_block_data(struct adv7604_state *state, | |
404 | enum adv7604_page page, u8 command, | |
405 | unsigned length, const u8 *values) | |
406 | { | |
407 | struct i2c_client *client = state->i2c_clients[page]; | |
408 | union i2c_smbus_data data; | |
409 | ||
410 | if (length > I2C_SMBUS_BLOCK_MAX) | |
411 | length = I2C_SMBUS_BLOCK_MAX; | |
412 | data.block[0] = length; | |
413 | memcpy(data.block + 1, values, length); | |
414 | return i2c_smbus_xfer(client->adapter, client->addr, client->flags, | |
415 | I2C_SMBUS_WRITE, command, | |
416 | I2C_SMBUS_I2C_BLOCK_DATA, &data); | |
417 | } | |
418 | ||
419 | /* ----------------------------------------------------------------------- */ | |
420 | ||
421 | static inline int io_read(struct v4l2_subdev *sd, u8 reg) | |
422 | { | |
423 | struct adv7604_state *state = to_state(sd); | |
424 | ||
425 | return adv_smbus_read_byte_data(state, ADV7604_PAGE_IO, reg); | |
426 | } | |
427 | ||
428 | static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
429 | { | |
430 | struct adv7604_state *state = to_state(sd); | |
431 | ||
432 | return adv_smbus_write_byte_data(state, ADV7604_PAGE_IO, reg, val); | |
433 | } | |
434 | ||
435 | static inline int io_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) | |
436 | { | |
437 | return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val); | |
438 | } | |
439 | ||
440 | static inline int avlink_read(struct v4l2_subdev *sd, u8 reg) | |
441 | { | |
442 | struct adv7604_state *state = to_state(sd); | |
443 | ||
444 | return adv_smbus_read_byte_data(state, ADV7604_PAGE_AVLINK, reg); | |
445 | } | |
446 | ||
447 | static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
448 | { | |
449 | struct adv7604_state *state = to_state(sd); | |
450 | ||
451 | return adv_smbus_write_byte_data(state, ADV7604_PAGE_AVLINK, reg, val); | |
452 | } | |
453 | ||
454 | static inline int cec_read(struct v4l2_subdev *sd, u8 reg) | |
455 | { | |
456 | struct adv7604_state *state = to_state(sd); | |
457 | ||
458 | return adv_smbus_read_byte_data(state, ADV7604_PAGE_CEC, reg); | |
459 | } | |
460 | ||
461 | static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
462 | { | |
463 | struct adv7604_state *state = to_state(sd); | |
464 | ||
465 | return adv_smbus_write_byte_data(state, ADV7604_PAGE_CEC, reg, val); | |
466 | } | |
467 | ||
468 | static inline int cec_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) | |
469 | { | |
470 | return cec_write(sd, reg, (cec_read(sd, reg) & ~mask) | val); | |
471 | } | |
472 | ||
473 | static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg) | |
474 | { | |
475 | struct adv7604_state *state = to_state(sd); | |
476 | ||
477 | return adv_smbus_read_byte_data(state, ADV7604_PAGE_INFOFRAME, reg); | |
478 | } | |
479 | ||
480 | static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
481 | { | |
482 | struct adv7604_state *state = to_state(sd); | |
483 | ||
484 | return adv_smbus_write_byte_data(state, ADV7604_PAGE_INFOFRAME, | |
485 | reg, val); | |
486 | } | |
487 | ||
488 | static inline int esdp_read(struct v4l2_subdev *sd, u8 reg) | |
489 | { | |
490 | struct adv7604_state *state = to_state(sd); | |
491 | ||
492 | return adv_smbus_read_byte_data(state, ADV7604_PAGE_ESDP, reg); | |
493 | } | |
494 | ||
495 | static inline int esdp_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
496 | { | |
497 | struct adv7604_state *state = to_state(sd); | |
498 | ||
499 | return adv_smbus_write_byte_data(state, ADV7604_PAGE_ESDP, reg, val); | |
500 | } | |
501 | ||
502 | static inline int dpp_read(struct v4l2_subdev *sd, u8 reg) | |
503 | { | |
504 | struct adv7604_state *state = to_state(sd); | |
505 | ||
506 | return adv_smbus_read_byte_data(state, ADV7604_PAGE_DPP, reg); | |
507 | } | |
508 | ||
509 | static inline int dpp_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
510 | { | |
511 | struct adv7604_state *state = to_state(sd); | |
512 | ||
513 | return adv_smbus_write_byte_data(state, ADV7604_PAGE_DPP, reg, val); | |
514 | } | |
515 | ||
516 | static inline int afe_read(struct v4l2_subdev *sd, u8 reg) | |
517 | { | |
518 | struct adv7604_state *state = to_state(sd); | |
519 | ||
520 | return adv_smbus_read_byte_data(state, ADV7604_PAGE_AFE, reg); | |
521 | } | |
522 | ||
523 | static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
524 | { | |
525 | struct adv7604_state *state = to_state(sd); | |
526 | ||
527 | return adv_smbus_write_byte_data(state, ADV7604_PAGE_AFE, reg, val); | |
528 | } | |
529 | ||
530 | static inline int rep_read(struct v4l2_subdev *sd, u8 reg) | |
531 | { | |
532 | struct adv7604_state *state = to_state(sd); | |
533 | ||
534 | return adv_smbus_read_byte_data(state, ADV7604_PAGE_REP, reg); | |
535 | } | |
536 | ||
537 | static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
538 | { | |
539 | struct adv7604_state *state = to_state(sd); | |
540 | ||
541 | return adv_smbus_write_byte_data(state, ADV7604_PAGE_REP, reg, val); | |
542 | } | |
543 | ||
544 | static inline int rep_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) | |
545 | { | |
546 | return rep_write(sd, reg, (rep_read(sd, reg) & ~mask) | val); | |
547 | } | |
548 | ||
549 | static inline int edid_read(struct v4l2_subdev *sd, u8 reg) | |
550 | { | |
551 | struct adv7604_state *state = to_state(sd); | |
552 | ||
553 | return adv_smbus_read_byte_data(state, ADV7604_PAGE_EDID, reg); | |
554 | } | |
555 | ||
556 | static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
557 | { | |
558 | struct adv7604_state *state = to_state(sd); | |
559 | ||
560 | return adv_smbus_write_byte_data(state, ADV7604_PAGE_EDID, reg, val); | |
561 | } | |
562 | ||
563 | static inline int edid_read_block(struct v4l2_subdev *sd, unsigned len, u8 *val) | |
564 | { | |
565 | struct adv7604_state *state = to_state(sd); | |
566 | struct i2c_client *client = state->i2c_clients[ADV7604_PAGE_EDID]; | |
567 | u8 msgbuf0[1] = { 0 }; | |
568 | u8 msgbuf1[256]; | |
569 | struct i2c_msg msg[2] = { | |
570 | { | |
571 | .addr = client->addr, | |
572 | .len = 1, | |
573 | .buf = msgbuf0 | |
574 | }, | |
575 | { | |
576 | .addr = client->addr, | |
577 | .flags = I2C_M_RD, | |
578 | .len = len, | |
579 | .buf = msgbuf1 | |
580 | }, | |
581 | }; | |
582 | ||
583 | if (i2c_transfer(client->adapter, msg, 2) < 0) | |
584 | return -EIO; | |
585 | memcpy(val, msgbuf1, len); | |
586 | return 0; | |
587 | } | |
588 | ||
589 | static inline int edid_write_block(struct v4l2_subdev *sd, | |
590 | unsigned len, const u8 *val) | |
591 | { | |
592 | struct adv7604_state *state = to_state(sd); | |
593 | int err = 0; | |
594 | int i; | |
595 | ||
596 | v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n", __func__, len); | |
597 | ||
598 | for (i = 0; !err && i < len; i += I2C_SMBUS_BLOCK_MAX) | |
599 | err = adv_smbus_write_i2c_block_data(state, ADV7604_PAGE_EDID, | |
600 | i, I2C_SMBUS_BLOCK_MAX, val + i); | |
601 | return err; | |
602 | } | |
603 | ||
604 | static void adv7604_set_hpd(struct adv7604_state *state, unsigned int hpd) | |
605 | { | |
606 | unsigned int i; | |
607 | ||
608 | for (i = 0; i < state->info->num_dv_ports; ++i) { | |
609 | if (IS_ERR(state->hpd_gpio[i])) | |
610 | continue; | |
611 | ||
612 | gpiod_set_value_cansleep(state->hpd_gpio[i], hpd & BIT(i)); | |
613 | } | |
614 | ||
615 | v4l2_subdev_notify(&state->sd, ADV7604_HOTPLUG, &hpd); | |
616 | } | |
617 | ||
618 | static void adv7604_delayed_work_enable_hotplug(struct work_struct *work) | |
619 | { | |
620 | struct delayed_work *dwork = to_delayed_work(work); | |
621 | struct adv7604_state *state = container_of(dwork, struct adv7604_state, | |
622 | delayed_work_enable_hotplug); | |
623 | struct v4l2_subdev *sd = &state->sd; | |
624 | ||
625 | v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__); | |
626 | ||
627 | adv7604_set_hpd(state, state->edid.present); | |
628 | } | |
629 | ||
630 | static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg) | |
631 | { | |
632 | struct adv7604_state *state = to_state(sd); | |
633 | ||
634 | return adv_smbus_read_byte_data(state, ADV7604_PAGE_HDMI, reg); | |
635 | } | |
636 | ||
637 | static u16 hdmi_read16(struct v4l2_subdev *sd, u8 reg, u16 mask) | |
638 | { | |
639 | return ((hdmi_read(sd, reg) << 8) | hdmi_read(sd, reg + 1)) & mask; | |
640 | } | |
641 | ||
642 | static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
643 | { | |
644 | struct adv7604_state *state = to_state(sd); | |
645 | ||
646 | return adv_smbus_write_byte_data(state, ADV7604_PAGE_HDMI, reg, val); | |
647 | } | |
648 | ||
649 | static inline int hdmi_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) | |
650 | { | |
651 | return hdmi_write(sd, reg, (hdmi_read(sd, reg) & ~mask) | val); | |
652 | } | |
653 | ||
654 | static inline int test_read(struct v4l2_subdev *sd, u8 reg) | |
655 | { | |
656 | struct adv7604_state *state = to_state(sd); | |
657 | ||
658 | return adv_smbus_read_byte_data(state, ADV7604_PAGE_TEST, reg); | |
659 | } | |
660 | ||
661 | static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
662 | { | |
663 | struct adv7604_state *state = to_state(sd); | |
664 | ||
665 | return adv_smbus_write_byte_data(state, ADV7604_PAGE_TEST, reg, val); | |
666 | } | |
667 | ||
668 | static inline int cp_read(struct v4l2_subdev *sd, u8 reg) | |
669 | { | |
670 | struct adv7604_state *state = to_state(sd); | |
671 | ||
672 | return adv_smbus_read_byte_data(state, ADV7604_PAGE_CP, reg); | |
673 | } | |
674 | ||
675 | static u16 cp_read16(struct v4l2_subdev *sd, u8 reg, u16 mask) | |
676 | { | |
677 | return ((cp_read(sd, reg) << 8) | cp_read(sd, reg + 1)) & mask; | |
678 | } | |
679 | ||
680 | static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
681 | { | |
682 | struct adv7604_state *state = to_state(sd); | |
683 | ||
684 | return adv_smbus_write_byte_data(state, ADV7604_PAGE_CP, reg, val); | |
685 | } | |
686 | ||
687 | static inline int cp_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) | |
688 | { | |
689 | return cp_write(sd, reg, (cp_read(sd, reg) & ~mask) | val); | |
690 | } | |
691 | ||
692 | static inline int vdp_read(struct v4l2_subdev *sd, u8 reg) | |
693 | { | |
694 | struct adv7604_state *state = to_state(sd); | |
695 | ||
696 | return adv_smbus_read_byte_data(state, ADV7604_PAGE_VDP, reg); | |
697 | } | |
698 | ||
699 | static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
700 | { | |
701 | struct adv7604_state *state = to_state(sd); | |
702 | ||
703 | return adv_smbus_write_byte_data(state, ADV7604_PAGE_VDP, reg, val); | |
704 | } | |
705 | ||
706 | #define ADV7604_REG(page, offset) (((page) << 8) | (offset)) | |
707 | #define ADV7604_REG_SEQ_TERM 0xffff | |
708 | ||
709 | #ifdef CONFIG_VIDEO_ADV_DEBUG | |
710 | static int adv7604_read_reg(struct v4l2_subdev *sd, unsigned int reg) | |
711 | { | |
712 | struct adv7604_state *state = to_state(sd); | |
713 | unsigned int page = reg >> 8; | |
714 | ||
715 | if (!(BIT(page) & state->info->page_mask)) | |
716 | return -EINVAL; | |
717 | ||
718 | reg &= 0xff; | |
719 | ||
720 | return adv_smbus_read_byte_data(state, page, reg); | |
721 | } | |
722 | #endif | |
723 | ||
724 | static int adv7604_write_reg(struct v4l2_subdev *sd, unsigned int reg, u8 val) | |
725 | { | |
726 | struct adv7604_state *state = to_state(sd); | |
727 | unsigned int page = reg >> 8; | |
728 | ||
729 | if (!(BIT(page) & state->info->page_mask)) | |
730 | return -EINVAL; | |
731 | ||
732 | reg &= 0xff; | |
733 | ||
734 | return adv_smbus_write_byte_data(state, page, reg, val); | |
735 | } | |
736 | ||
737 | static void adv7604_write_reg_seq(struct v4l2_subdev *sd, | |
738 | const struct adv7604_reg_seq *reg_seq) | |
739 | { | |
740 | unsigned int i; | |
741 | ||
742 | for (i = 0; reg_seq[i].reg != ADV7604_REG_SEQ_TERM; i++) | |
743 | adv7604_write_reg(sd, reg_seq[i].reg, reg_seq[i].val); | |
744 | } | |
745 | ||
746 | /* ----------------------------------------------------------------------------- | |
747 | * Format helpers | |
748 | */ | |
749 | ||
750 | static const struct adv7604_format_info adv7604_formats[] = { | |
751 | { V4L2_MBUS_FMT_RGB888_1X24, ADV7604_OP_CH_SEL_RGB, true, false, | |
752 | ADV7604_OP_MODE_SEL_SDR_444 | ADV7604_OP_FORMAT_SEL_8BIT }, | |
753 | { V4L2_MBUS_FMT_YUYV8_2X8, ADV7604_OP_CH_SEL_RGB, false, false, | |
754 | ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT }, | |
755 | { V4L2_MBUS_FMT_YVYU8_2X8, ADV7604_OP_CH_SEL_RGB, false, true, | |
756 | ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT }, | |
757 | { V4L2_MBUS_FMT_YUYV10_2X10, ADV7604_OP_CH_SEL_RGB, false, false, | |
758 | ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT }, | |
759 | { V4L2_MBUS_FMT_YVYU10_2X10, ADV7604_OP_CH_SEL_RGB, false, true, | |
760 | ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT }, | |
761 | { V4L2_MBUS_FMT_YUYV12_2X12, ADV7604_OP_CH_SEL_RGB, false, false, | |
762 | ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT }, | |
763 | { V4L2_MBUS_FMT_YVYU12_2X12, ADV7604_OP_CH_SEL_RGB, false, true, | |
764 | ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT }, | |
765 | { V4L2_MBUS_FMT_UYVY8_1X16, ADV7604_OP_CH_SEL_RBG, false, false, | |
766 | ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, | |
767 | { V4L2_MBUS_FMT_VYUY8_1X16, ADV7604_OP_CH_SEL_RBG, false, true, | |
768 | ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, | |
769 | { V4L2_MBUS_FMT_YUYV8_1X16, ADV7604_OP_CH_SEL_RGB, false, false, | |
770 | ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, | |
771 | { V4L2_MBUS_FMT_YVYU8_1X16, ADV7604_OP_CH_SEL_RGB, false, true, | |
772 | ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, | |
773 | { V4L2_MBUS_FMT_UYVY10_1X20, ADV7604_OP_CH_SEL_RBG, false, false, | |
774 | ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, | |
775 | { V4L2_MBUS_FMT_VYUY10_1X20, ADV7604_OP_CH_SEL_RBG, false, true, | |
776 | ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, | |
777 | { V4L2_MBUS_FMT_YUYV10_1X20, ADV7604_OP_CH_SEL_RGB, false, false, | |
778 | ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, | |
779 | { V4L2_MBUS_FMT_YVYU10_1X20, ADV7604_OP_CH_SEL_RGB, false, true, | |
780 | ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, | |
781 | { V4L2_MBUS_FMT_UYVY12_1X24, ADV7604_OP_CH_SEL_RBG, false, false, | |
782 | ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT }, | |
783 | { V4L2_MBUS_FMT_VYUY12_1X24, ADV7604_OP_CH_SEL_RBG, false, true, | |
784 | ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT }, | |
785 | { V4L2_MBUS_FMT_YUYV12_1X24, ADV7604_OP_CH_SEL_RGB, false, false, | |
786 | ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT }, | |
787 | { V4L2_MBUS_FMT_YVYU12_1X24, ADV7604_OP_CH_SEL_RGB, false, true, | |
788 | ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT }, | |
789 | }; | |
790 | ||
791 | static const struct adv7604_format_info adv7611_formats[] = { | |
792 | { V4L2_MBUS_FMT_RGB888_1X24, ADV7604_OP_CH_SEL_RGB, true, false, | |
793 | ADV7604_OP_MODE_SEL_SDR_444 | ADV7604_OP_FORMAT_SEL_8BIT }, | |
794 | { V4L2_MBUS_FMT_YUYV8_2X8, ADV7604_OP_CH_SEL_RGB, false, false, | |
795 | ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT }, | |
796 | { V4L2_MBUS_FMT_YVYU8_2X8, ADV7604_OP_CH_SEL_RGB, false, true, | |
797 | ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT }, | |
798 | { V4L2_MBUS_FMT_YUYV12_2X12, ADV7604_OP_CH_SEL_RGB, false, false, | |
799 | ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT }, | |
800 | { V4L2_MBUS_FMT_YVYU12_2X12, ADV7604_OP_CH_SEL_RGB, false, true, | |
801 | ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT }, | |
802 | { V4L2_MBUS_FMT_UYVY8_1X16, ADV7604_OP_CH_SEL_RBG, false, false, | |
803 | ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, | |
804 | { V4L2_MBUS_FMT_VYUY8_1X16, ADV7604_OP_CH_SEL_RBG, false, true, | |
805 | ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, | |
806 | { V4L2_MBUS_FMT_YUYV8_1X16, ADV7604_OP_CH_SEL_RGB, false, false, | |
807 | ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, | |
808 | { V4L2_MBUS_FMT_YVYU8_1X16, ADV7604_OP_CH_SEL_RGB, false, true, | |
809 | ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, | |
810 | { V4L2_MBUS_FMT_UYVY12_1X24, ADV7604_OP_CH_SEL_RBG, false, false, | |
811 | ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT }, | |
812 | { V4L2_MBUS_FMT_VYUY12_1X24, ADV7604_OP_CH_SEL_RBG, false, true, | |
813 | ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT }, | |
814 | { V4L2_MBUS_FMT_YUYV12_1X24, ADV7604_OP_CH_SEL_RGB, false, false, | |
815 | ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT }, | |
816 | { V4L2_MBUS_FMT_YVYU12_1X24, ADV7604_OP_CH_SEL_RGB, false, true, | |
817 | ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT }, | |
818 | }; | |
819 | ||
820 | static const struct adv7604_format_info * | |
821 | adv7604_format_info(struct adv7604_state *state, enum v4l2_mbus_pixelcode code) | |
822 | { | |
823 | unsigned int i; | |
824 | ||
825 | for (i = 0; i < state->info->nformats; ++i) { | |
826 | if (state->info->formats[i].code == code) | |
827 | return &state->info->formats[i]; | |
828 | } | |
829 | ||
830 | return NULL; | |
831 | } | |
832 | ||
833 | /* ----------------------------------------------------------------------- */ | |
834 | ||
835 | static inline bool is_analog_input(struct v4l2_subdev *sd) | |
836 | { | |
837 | struct adv7604_state *state = to_state(sd); | |
838 | ||
839 | return state->selected_input == ADV7604_PAD_VGA_RGB || | |
840 | state->selected_input == ADV7604_PAD_VGA_COMP; | |
841 | } | |
842 | ||
843 | static inline bool is_digital_input(struct v4l2_subdev *sd) | |
844 | { | |
845 | struct adv7604_state *state = to_state(sd); | |
846 | ||
847 | return state->selected_input == ADV7604_PAD_HDMI_PORT_A || | |
848 | state->selected_input == ADV7604_PAD_HDMI_PORT_B || | |
849 | state->selected_input == ADV7604_PAD_HDMI_PORT_C || | |
850 | state->selected_input == ADV7604_PAD_HDMI_PORT_D; | |
851 | } | |
852 | ||
853 | /* ----------------------------------------------------------------------- */ | |
854 | ||
855 | #ifdef CONFIG_VIDEO_ADV_DEBUG | |
856 | static void adv7604_inv_register(struct v4l2_subdev *sd) | |
857 | { | |
858 | v4l2_info(sd, "0x000-0x0ff: IO Map\n"); | |
859 | v4l2_info(sd, "0x100-0x1ff: AVLink Map\n"); | |
860 | v4l2_info(sd, "0x200-0x2ff: CEC Map\n"); | |
861 | v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n"); | |
862 | v4l2_info(sd, "0x400-0x4ff: ESDP Map\n"); | |
863 | v4l2_info(sd, "0x500-0x5ff: DPP Map\n"); | |
864 | v4l2_info(sd, "0x600-0x6ff: AFE Map\n"); | |
865 | v4l2_info(sd, "0x700-0x7ff: Repeater Map\n"); | |
866 | v4l2_info(sd, "0x800-0x8ff: EDID Map\n"); | |
867 | v4l2_info(sd, "0x900-0x9ff: HDMI Map\n"); | |
868 | v4l2_info(sd, "0xa00-0xaff: Test Map\n"); | |
869 | v4l2_info(sd, "0xb00-0xbff: CP Map\n"); | |
870 | v4l2_info(sd, "0xc00-0xcff: VDP Map\n"); | |
871 | } | |
872 | ||
873 | static int adv7604_g_register(struct v4l2_subdev *sd, | |
874 | struct v4l2_dbg_register *reg) | |
875 | { | |
876 | int ret; | |
877 | ||
878 | ret = adv7604_read_reg(sd, reg->reg); | |
879 | if (ret < 0) { | |
880 | v4l2_info(sd, "Register %03llx not supported\n", reg->reg); | |
881 | adv7604_inv_register(sd); | |
882 | return ret; | |
883 | } | |
884 | ||
885 | reg->size = 1; | |
886 | reg->val = ret; | |
887 | ||
888 | return 0; | |
889 | } | |
890 | ||
891 | static int adv7604_s_register(struct v4l2_subdev *sd, | |
892 | const struct v4l2_dbg_register *reg) | |
893 | { | |
894 | int ret; | |
895 | ||
896 | ret = adv7604_write_reg(sd, reg->reg, reg->val); | |
897 | if (ret < 0) { | |
898 | v4l2_info(sd, "Register %03llx not supported\n", reg->reg); | |
899 | adv7604_inv_register(sd); | |
900 | return ret; | |
901 | } | |
902 | ||
903 | return 0; | |
904 | } | |
905 | #endif | |
906 | ||
907 | static unsigned int adv7604_read_cable_det(struct v4l2_subdev *sd) | |
908 | { | |
909 | u8 value = io_read(sd, 0x6f); | |
910 | ||
911 | return ((value & 0x10) >> 4) | |
912 | | ((value & 0x08) >> 2) | |
913 | | ((value & 0x04) << 0) | |
914 | | ((value & 0x02) << 2); | |
915 | } | |
916 | ||
917 | static unsigned int adv7611_read_cable_det(struct v4l2_subdev *sd) | |
918 | { | |
919 | u8 value = io_read(sd, 0x6f); | |
920 | ||
921 | return value & 1; | |
922 | } | |
923 | ||
924 | static int adv7604_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd) | |
925 | { | |
926 | struct adv7604_state *state = to_state(sd); | |
927 | const struct adv7604_chip_info *info = state->info; | |
928 | ||
929 | return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, | |
930 | info->read_cable_det(sd)); | |
931 | } | |
932 | ||
933 | static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd, | |
934 | u8 prim_mode, | |
935 | const struct adv7604_video_standards *predef_vid_timings, | |
936 | const struct v4l2_dv_timings *timings) | |
937 | { | |
938 | int i; | |
939 | ||
940 | for (i = 0; predef_vid_timings[i].timings.bt.width; i++) { | |
941 | if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings, | |
942 | is_digital_input(sd) ? 250000 : 1000000)) | |
943 | continue; | |
944 | io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */ | |
945 | io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) + | |
946 | prim_mode); /* v_freq and prim mode */ | |
947 | return 0; | |
948 | } | |
949 | ||
950 | return -1; | |
951 | } | |
952 | ||
953 | static int configure_predefined_video_timings(struct v4l2_subdev *sd, | |
954 | struct v4l2_dv_timings *timings) | |
955 | { | |
956 | struct adv7604_state *state = to_state(sd); | |
957 | int err; | |
958 | ||
959 | v4l2_dbg(1, debug, sd, "%s", __func__); | |
960 | ||
961 | if (adv7604_has_afe(state)) { | |
962 | /* reset to default values */ | |
963 | io_write(sd, 0x16, 0x43); | |
964 | io_write(sd, 0x17, 0x5a); | |
965 | } | |
966 | /* disable embedded syncs for auto graphics mode */ | |
967 | cp_write_clr_set(sd, 0x81, 0x10, 0x00); | |
968 | cp_write(sd, 0x8f, 0x00); | |
969 | cp_write(sd, 0x90, 0x00); | |
970 | cp_write(sd, 0xa2, 0x00); | |
971 | cp_write(sd, 0xa3, 0x00); | |
972 | cp_write(sd, 0xa4, 0x00); | |
973 | cp_write(sd, 0xa5, 0x00); | |
974 | cp_write(sd, 0xa6, 0x00); | |
975 | cp_write(sd, 0xa7, 0x00); | |
976 | cp_write(sd, 0xab, 0x00); | |
977 | cp_write(sd, 0xac, 0x00); | |
978 | ||
979 | if (is_analog_input(sd)) { | |
980 | err = find_and_set_predefined_video_timings(sd, | |
981 | 0x01, adv7604_prim_mode_comp, timings); | |
982 | if (err) | |
983 | err = find_and_set_predefined_video_timings(sd, | |
984 | 0x02, adv7604_prim_mode_gr, timings); | |
985 | } else if (is_digital_input(sd)) { | |
986 | err = find_and_set_predefined_video_timings(sd, | |
987 | 0x05, adv7604_prim_mode_hdmi_comp, timings); | |
988 | if (err) | |
989 | err = find_and_set_predefined_video_timings(sd, | |
990 | 0x06, adv7604_prim_mode_hdmi_gr, timings); | |
991 | } else { | |
992 | v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", | |
993 | __func__, state->selected_input); | |
994 | err = -1; | |
995 | } | |
996 | ||
997 | ||
998 | return err; | |
999 | } | |
1000 | ||
1001 | static void configure_custom_video_timings(struct v4l2_subdev *sd, | |
1002 | const struct v4l2_bt_timings *bt) | |
1003 | { | |
1004 | struct adv7604_state *state = to_state(sd); | |
1005 | u32 width = htotal(bt); | |
1006 | u32 height = vtotal(bt); | |
1007 | u16 cp_start_sav = bt->hsync + bt->hbackporch - 4; | |
1008 | u16 cp_start_eav = width - bt->hfrontporch; | |
1009 | u16 cp_start_vbi = height - bt->vfrontporch; | |
1010 | u16 cp_end_vbi = bt->vsync + bt->vbackporch; | |
1011 | u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ? | |
1012 | ((width * (ADV7604_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0; | |
1013 | const u8 pll[2] = { | |
1014 | 0xc0 | ((width >> 8) & 0x1f), | |
1015 | width & 0xff | |
1016 | }; | |
1017 | ||
1018 | v4l2_dbg(2, debug, sd, "%s\n", __func__); | |
1019 | ||
1020 | if (is_analog_input(sd)) { | |
1021 | /* auto graphics */ | |
1022 | io_write(sd, 0x00, 0x07); /* video std */ | |
1023 | io_write(sd, 0x01, 0x02); /* prim mode */ | |
1024 | /* enable embedded syncs for auto graphics mode */ | |
1025 | cp_write_clr_set(sd, 0x81, 0x10, 0x10); | |
1026 | ||
1027 | /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */ | |
1028 | /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */ | |
1029 | /* IO-map reg. 0x16 and 0x17 should be written in sequence */ | |
1030 | if (adv_smbus_write_i2c_block_data(state, ADV7604_PAGE_IO, | |
1031 | 0x16, 2, pll)) | |
1032 | v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n"); | |
1033 | ||
1034 | /* active video - horizontal timing */ | |
1035 | cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff); | |
1036 | cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) | | |
1037 | ((cp_start_eav >> 8) & 0x0f)); | |
1038 | cp_write(sd, 0xa4, cp_start_eav & 0xff); | |
1039 | ||
1040 | /* active video - vertical timing */ | |
1041 | cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff); | |
1042 | cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) | | |
1043 | ((cp_end_vbi >> 8) & 0xf)); | |
1044 | cp_write(sd, 0xa7, cp_end_vbi & 0xff); | |
1045 | } else if (is_digital_input(sd)) { | |
1046 | /* set default prim_mode/vid_std for HDMI | |
1047 | according to [REF_03, c. 4.2] */ | |
1048 | io_write(sd, 0x00, 0x02); /* video std */ | |
1049 | io_write(sd, 0x01, 0x06); /* prim mode */ | |
1050 | } else { | |
1051 | v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", | |
1052 | __func__, state->selected_input); | |
1053 | } | |
1054 | ||
1055 | cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7); | |
1056 | cp_write(sd, 0x90, ch1_fr_ll & 0xff); | |
1057 | cp_write(sd, 0xab, (height >> 4) & 0xff); | |
1058 | cp_write(sd, 0xac, (height & 0x0f) << 4); | |
1059 | } | |
1060 | ||
1061 | static void adv7604_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c) | |
1062 | { | |
1063 | struct adv7604_state *state = to_state(sd); | |
1064 | u8 offset_buf[4]; | |
1065 | ||
1066 | if (auto_offset) { | |
1067 | offset_a = 0x3ff; | |
1068 | offset_b = 0x3ff; | |
1069 | offset_c = 0x3ff; | |
1070 | } | |
1071 | ||
1072 | v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n", | |
1073 | __func__, auto_offset ? "Auto" : "Manual", | |
1074 | offset_a, offset_b, offset_c); | |
1075 | ||
1076 | offset_buf[0] = (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4); | |
1077 | offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6); | |
1078 | offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8); | |
1079 | offset_buf[3] = offset_c & 0x0ff; | |
1080 | ||
1081 | /* Registers must be written in this order with no i2c access in between */ | |
1082 | if (adv_smbus_write_i2c_block_data(state, ADV7604_PAGE_CP, | |
1083 | 0x77, 4, offset_buf)) | |
1084 | v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__); | |
1085 | } | |
1086 | ||
1087 | static void adv7604_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c) | |
1088 | { | |
1089 | struct adv7604_state *state = to_state(sd); | |
1090 | u8 gain_buf[4]; | |
1091 | u8 gain_man = 1; | |
1092 | u8 agc_mode_man = 1; | |
1093 | ||
1094 | if (auto_gain) { | |
1095 | gain_man = 0; | |
1096 | agc_mode_man = 0; | |
1097 | gain_a = 0x100; | |
1098 | gain_b = 0x100; | |
1099 | gain_c = 0x100; | |
1100 | } | |
1101 | ||
1102 | v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n", | |
1103 | __func__, auto_gain ? "Auto" : "Manual", | |
1104 | gain_a, gain_b, gain_c); | |
1105 | ||
1106 | gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4)); | |
1107 | gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6)); | |
1108 | gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8)); | |
1109 | gain_buf[3] = ((gain_c & 0x0ff)); | |
1110 | ||
1111 | /* Registers must be written in this order with no i2c access in between */ | |
1112 | if (adv_smbus_write_i2c_block_data(state, ADV7604_PAGE_CP, | |
1113 | 0x73, 4, gain_buf)) | |
1114 | v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__); | |
1115 | } | |
1116 | ||
1117 | static void set_rgb_quantization_range(struct v4l2_subdev *sd) | |
1118 | { | |
1119 | struct adv7604_state *state = to_state(sd); | |
1120 | bool rgb_output = io_read(sd, 0x02) & 0x02; | |
1121 | bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80; | |
1122 | ||
1123 | v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n", | |
1124 | __func__, state->rgb_quantization_range, | |
1125 | rgb_output, hdmi_signal); | |
1126 | ||
1127 | adv7604_set_gain(sd, true, 0x0, 0x0, 0x0); | |
1128 | adv7604_set_offset(sd, true, 0x0, 0x0, 0x0); | |
1129 | ||
1130 | switch (state->rgb_quantization_range) { | |
1131 | case V4L2_DV_RGB_RANGE_AUTO: | |
1132 | if (state->selected_input == ADV7604_PAD_VGA_RGB) { | |
1133 | /* Receiving analog RGB signal | |
1134 | * Set RGB full range (0-255) */ | |
1135 | io_write_clr_set(sd, 0x02, 0xf0, 0x10); | |
1136 | break; | |
1137 | } | |
1138 | ||
1139 | if (state->selected_input == ADV7604_PAD_VGA_COMP) { | |
1140 | /* Receiving analog YPbPr signal | |
1141 | * Set automode */ | |
1142 | io_write_clr_set(sd, 0x02, 0xf0, 0xf0); | |
1143 | break; | |
1144 | } | |
1145 | ||
1146 | if (hdmi_signal) { | |
1147 | /* Receiving HDMI signal | |
1148 | * Set automode */ | |
1149 | io_write_clr_set(sd, 0x02, 0xf0, 0xf0); | |
1150 | break; | |
1151 | } | |
1152 | ||
1153 | /* Receiving DVI-D signal | |
1154 | * ADV7604 selects RGB limited range regardless of | |
1155 | * input format (CE/IT) in automatic mode */ | |
1156 | if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) { | |
1157 | /* RGB limited range (16-235) */ | |
1158 | io_write_clr_set(sd, 0x02, 0xf0, 0x00); | |
1159 | } else { | |
1160 | /* RGB full range (0-255) */ | |
1161 | io_write_clr_set(sd, 0x02, 0xf0, 0x10); | |
1162 | ||
1163 | if (is_digital_input(sd) && rgb_output) { | |
1164 | adv7604_set_offset(sd, false, 0x40, 0x40, 0x40); | |
1165 | } else { | |
1166 | adv7604_set_gain(sd, false, 0xe0, 0xe0, 0xe0); | |
1167 | adv7604_set_offset(sd, false, 0x70, 0x70, 0x70); | |
1168 | } | |
1169 | } | |
1170 | break; | |
1171 | case V4L2_DV_RGB_RANGE_LIMITED: | |
1172 | if (state->selected_input == ADV7604_PAD_VGA_COMP) { | |
1173 | /* YCrCb limited range (16-235) */ | |
1174 | io_write_clr_set(sd, 0x02, 0xf0, 0x20); | |
1175 | break; | |
1176 | } | |
1177 | ||
1178 | /* RGB limited range (16-235) */ | |
1179 | io_write_clr_set(sd, 0x02, 0xf0, 0x00); | |
1180 | ||
1181 | break; | |
1182 | case V4L2_DV_RGB_RANGE_FULL: | |
1183 | if (state->selected_input == ADV7604_PAD_VGA_COMP) { | |
1184 | /* YCrCb full range (0-255) */ | |
1185 | io_write_clr_set(sd, 0x02, 0xf0, 0x60); | |
1186 | break; | |
1187 | } | |
1188 | ||
1189 | /* RGB full range (0-255) */ | |
1190 | io_write_clr_set(sd, 0x02, 0xf0, 0x10); | |
1191 | ||
1192 | if (is_analog_input(sd) || hdmi_signal) | |
1193 | break; | |
1194 | ||
1195 | /* Adjust gain/offset for DVI-D signals only */ | |
1196 | if (rgb_output) { | |
1197 | adv7604_set_offset(sd, false, 0x40, 0x40, 0x40); | |
1198 | } else { | |
1199 | adv7604_set_gain(sd, false, 0xe0, 0xe0, 0xe0); | |
1200 | adv7604_set_offset(sd, false, 0x70, 0x70, 0x70); | |
1201 | } | |
1202 | break; | |
1203 | } | |
1204 | } | |
1205 | ||
1206 | static int adv7604_s_ctrl(struct v4l2_ctrl *ctrl) | |
1207 | { | |
1208 | struct v4l2_subdev *sd = | |
1209 | &container_of(ctrl->handler, struct adv7604_state, hdl)->sd; | |
1210 | ||
1211 | struct adv7604_state *state = to_state(sd); | |
1212 | ||
1213 | switch (ctrl->id) { | |
1214 | case V4L2_CID_BRIGHTNESS: | |
1215 | cp_write(sd, 0x3c, ctrl->val); | |
1216 | return 0; | |
1217 | case V4L2_CID_CONTRAST: | |
1218 | cp_write(sd, 0x3a, ctrl->val); | |
1219 | return 0; | |
1220 | case V4L2_CID_SATURATION: | |
1221 | cp_write(sd, 0x3b, ctrl->val); | |
1222 | return 0; | |
1223 | case V4L2_CID_HUE: | |
1224 | cp_write(sd, 0x3d, ctrl->val); | |
1225 | return 0; | |
1226 | case V4L2_CID_DV_RX_RGB_RANGE: | |
1227 | state->rgb_quantization_range = ctrl->val; | |
1228 | set_rgb_quantization_range(sd); | |
1229 | return 0; | |
1230 | case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE: | |
1231 | if (!adv7604_has_afe(state)) | |
1232 | return -EINVAL; | |
1233 | /* Set the analog sampling phase. This is needed to find the | |
1234 | best sampling phase for analog video: an application or | |
1235 | driver has to try a number of phases and analyze the picture | |
1236 | quality before settling on the best performing phase. */ | |
1237 | afe_write(sd, 0xc8, ctrl->val); | |
1238 | return 0; | |
1239 | case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL: | |
1240 | /* Use the default blue color for free running mode, | |
1241 | or supply your own. */ | |
1242 | cp_write_clr_set(sd, 0xbf, 0x04, ctrl->val << 2); | |
1243 | return 0; | |
1244 | case V4L2_CID_ADV_RX_FREE_RUN_COLOR: | |
1245 | cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16); | |
1246 | cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8); | |
1247 | cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff)); | |
1248 | return 0; | |
1249 | } | |
1250 | return -EINVAL; | |
1251 | } | |
1252 | ||
1253 | /* ----------------------------------------------------------------------- */ | |
1254 | ||
1255 | static inline bool no_power(struct v4l2_subdev *sd) | |
1256 | { | |
1257 | /* Entire chip or CP powered off */ | |
1258 | return io_read(sd, 0x0c) & 0x24; | |
1259 | } | |
1260 | ||
1261 | static inline bool no_signal_tmds(struct v4l2_subdev *sd) | |
1262 | { | |
1263 | struct adv7604_state *state = to_state(sd); | |
1264 | ||
1265 | return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input)); | |
1266 | } | |
1267 | ||
1268 | static inline bool no_lock_tmds(struct v4l2_subdev *sd) | |
1269 | { | |
1270 | struct adv7604_state *state = to_state(sd); | |
1271 | const struct adv7604_chip_info *info = state->info; | |
1272 | ||
1273 | return (io_read(sd, 0x6a) & info->tdms_lock_mask) != info->tdms_lock_mask; | |
1274 | } | |
1275 | ||
1276 | static inline bool is_hdmi(struct v4l2_subdev *sd) | |
1277 | { | |
1278 | return hdmi_read(sd, 0x05) & 0x80; | |
1279 | } | |
1280 | ||
1281 | static inline bool no_lock_sspd(struct v4l2_subdev *sd) | |
1282 | { | |
1283 | struct adv7604_state *state = to_state(sd); | |
1284 | ||
1285 | /* | |
1286 | * Chips without a AFE don't expose registers for the SSPD, so just assume | |
1287 | * that we have a lock. | |
1288 | */ | |
1289 | if (adv7604_has_afe(state)) | |
1290 | return false; | |
1291 | ||
1292 | /* TODO channel 2 */ | |
1293 | return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0); | |
1294 | } | |
1295 | ||
1296 | static inline bool no_lock_stdi(struct v4l2_subdev *sd) | |
1297 | { | |
1298 | /* TODO channel 2 */ | |
1299 | return !(cp_read(sd, 0xb1) & 0x80); | |
1300 | } | |
1301 | ||
1302 | static inline bool no_signal(struct v4l2_subdev *sd) | |
1303 | { | |
1304 | bool ret; | |
1305 | ||
1306 | ret = no_power(sd); | |
1307 | ||
1308 | ret |= no_lock_stdi(sd); | |
1309 | ret |= no_lock_sspd(sd); | |
1310 | ||
1311 | if (is_digital_input(sd)) { | |
1312 | ret |= no_lock_tmds(sd); | |
1313 | ret |= no_signal_tmds(sd); | |
1314 | } | |
1315 | ||
1316 | return ret; | |
1317 | } | |
1318 | ||
1319 | static inline bool no_lock_cp(struct v4l2_subdev *sd) | |
1320 | { | |
1321 | struct adv7604_state *state = to_state(sd); | |
1322 | ||
1323 | if (!adv7604_has_afe(state)) | |
1324 | return false; | |
1325 | ||
1326 | /* CP has detected a non standard number of lines on the incoming | |
1327 | video compared to what it is configured to receive by s_dv_timings */ | |
1328 | return io_read(sd, 0x12) & 0x01; | |
1329 | } | |
1330 | ||
1331 | static int adv7604_g_input_status(struct v4l2_subdev *sd, u32 *status) | |
1332 | { | |
1333 | *status = 0; | |
1334 | *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0; | |
1335 | *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0; | |
1336 | if (no_lock_cp(sd)) | |
1337 | *status |= is_digital_input(sd) ? V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK; | |
1338 | ||
1339 | v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status); | |
1340 | ||
1341 | return 0; | |
1342 | } | |
1343 | ||
1344 | /* ----------------------------------------------------------------------- */ | |
1345 | ||
1346 | struct stdi_readback { | |
1347 | u16 bl, lcf, lcvs; | |
1348 | u8 hs_pol, vs_pol; | |
1349 | bool interlaced; | |
1350 | }; | |
1351 | ||
1352 | static int stdi2dv_timings(struct v4l2_subdev *sd, | |
1353 | struct stdi_readback *stdi, | |
1354 | struct v4l2_dv_timings *timings) | |
1355 | { | |
1356 | struct adv7604_state *state = to_state(sd); | |
1357 | u32 hfreq = (ADV7604_fsc * 8) / stdi->bl; | |
1358 | u32 pix_clk; | |
1359 | int i; | |
1360 | ||
1361 | for (i = 0; adv7604_timings[i].bt.height; i++) { | |
1362 | if (vtotal(&adv7604_timings[i].bt) != stdi->lcf + 1) | |
1363 | continue; | |
1364 | if (adv7604_timings[i].bt.vsync != stdi->lcvs) | |
1365 | continue; | |
1366 | ||
1367 | pix_clk = hfreq * htotal(&adv7604_timings[i].bt); | |
1368 | ||
1369 | if ((pix_clk < adv7604_timings[i].bt.pixelclock + 1000000) && | |
1370 | (pix_clk > adv7604_timings[i].bt.pixelclock - 1000000)) { | |
1371 | *timings = adv7604_timings[i]; | |
1372 | return 0; | |
1373 | } | |
1374 | } | |
1375 | ||
1376 | if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs, | |
1377 | (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | | |
1378 | (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), | |
1379 | timings)) | |
1380 | return 0; | |
1381 | if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs, | |
1382 | (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | | |
1383 | (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), | |
1384 | state->aspect_ratio, timings)) | |
1385 | return 0; | |
1386 | ||
1387 | v4l2_dbg(2, debug, sd, | |
1388 | "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n", | |
1389 | __func__, stdi->lcvs, stdi->lcf, stdi->bl, | |
1390 | stdi->hs_pol, stdi->vs_pol); | |
1391 | return -1; | |
1392 | } | |
1393 | ||
1394 | ||
1395 | static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi) | |
1396 | { | |
1397 | struct adv7604_state *state = to_state(sd); | |
1398 | const struct adv7604_chip_info *info = state->info; | |
1399 | u8 polarity; | |
1400 | ||
1401 | if (no_lock_stdi(sd) || no_lock_sspd(sd)) { | |
1402 | v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__); | |
1403 | return -1; | |
1404 | } | |
1405 | ||
1406 | /* read STDI */ | |
1407 | stdi->bl = cp_read16(sd, 0xb1, 0x3fff); | |
1408 | stdi->lcf = cp_read16(sd, info->lcf_reg, 0x7ff); | |
1409 | stdi->lcvs = cp_read(sd, 0xb3) >> 3; | |
1410 | stdi->interlaced = io_read(sd, 0x12) & 0x10; | |
1411 | ||
1412 | if (adv7604_has_afe(state)) { | |
1413 | /* read SSPD */ | |
1414 | polarity = cp_read(sd, 0xb5); | |
1415 | if ((polarity & 0x03) == 0x01) { | |
1416 | stdi->hs_pol = polarity & 0x10 | |
1417 | ? (polarity & 0x08 ? '+' : '-') : 'x'; | |
1418 | stdi->vs_pol = polarity & 0x40 | |
1419 | ? (polarity & 0x20 ? '+' : '-') : 'x'; | |
1420 | } else { | |
1421 | stdi->hs_pol = 'x'; | |
1422 | stdi->vs_pol = 'x'; | |
1423 | } | |
1424 | } else { | |
1425 | polarity = hdmi_read(sd, 0x05); | |
1426 | stdi->hs_pol = polarity & 0x20 ? '+' : '-'; | |
1427 | stdi->vs_pol = polarity & 0x10 ? '+' : '-'; | |
1428 | } | |
1429 | ||
1430 | if (no_lock_stdi(sd) || no_lock_sspd(sd)) { | |
1431 | v4l2_dbg(2, debug, sd, | |
1432 | "%s: signal lost during readout of STDI/SSPD\n", __func__); | |
1433 | return -1; | |
1434 | } | |
1435 | ||
1436 | if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) { | |
1437 | v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__); | |
1438 | memset(stdi, 0, sizeof(struct stdi_readback)); | |
1439 | return -1; | |
1440 | } | |
1441 | ||
1442 | v4l2_dbg(2, debug, sd, | |
1443 | "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n", | |
1444 | __func__, stdi->lcf, stdi->bl, stdi->lcvs, | |
1445 | stdi->hs_pol, stdi->vs_pol, | |
1446 | stdi->interlaced ? "interlaced" : "progressive"); | |
1447 | ||
1448 | return 0; | |
1449 | } | |
1450 | ||
1451 | static int adv7604_enum_dv_timings(struct v4l2_subdev *sd, | |
1452 | struct v4l2_enum_dv_timings *timings) | |
1453 | { | |
1454 | struct adv7604_state *state = to_state(sd); | |
1455 | ||
1456 | if (timings->index >= ARRAY_SIZE(adv7604_timings) - 1) | |
1457 | return -EINVAL; | |
1458 | ||
1459 | if (timings->pad >= state->source_pad) | |
1460 | return -EINVAL; | |
1461 | ||
1462 | memset(timings->reserved, 0, sizeof(timings->reserved)); | |
1463 | timings->timings = adv7604_timings[timings->index]; | |
1464 | return 0; | |
1465 | } | |
1466 | ||
1467 | static int adv7604_dv_timings_cap(struct v4l2_subdev *sd, | |
1468 | struct v4l2_dv_timings_cap *cap) | |
1469 | { | |
1470 | struct adv7604_state *state = to_state(sd); | |
1471 | ||
1472 | if (cap->pad >= state->source_pad) | |
1473 | return -EINVAL; | |
1474 | ||
1475 | cap->type = V4L2_DV_BT_656_1120; | |
1476 | cap->bt.max_width = 1920; | |
1477 | cap->bt.max_height = 1200; | |
1478 | cap->bt.min_pixelclock = 25000000; | |
1479 | ||
1480 | switch (cap->pad) { | |
1481 | case ADV7604_PAD_HDMI_PORT_A: | |
1482 | case ADV7604_PAD_HDMI_PORT_B: | |
1483 | case ADV7604_PAD_HDMI_PORT_C: | |
1484 | case ADV7604_PAD_HDMI_PORT_D: | |
1485 | cap->bt.max_pixelclock = 225000000; | |
1486 | break; | |
1487 | case ADV7604_PAD_VGA_RGB: | |
1488 | case ADV7604_PAD_VGA_COMP: | |
1489 | default: | |
1490 | cap->bt.max_pixelclock = 170000000; | |
1491 | break; | |
1492 | } | |
1493 | ||
1494 | cap->bt.standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | | |
1495 | V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT; | |
1496 | cap->bt.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE | | |
1497 | V4L2_DV_BT_CAP_REDUCED_BLANKING | V4L2_DV_BT_CAP_CUSTOM; | |
1498 | return 0; | |
1499 | } | |
1500 | ||
1501 | /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings | |
1502 | if the format is listed in adv7604_timings[] */ | |
1503 | static void adv7604_fill_optional_dv_timings_fields(struct v4l2_subdev *sd, | |
1504 | struct v4l2_dv_timings *timings) | |
1505 | { | |
1506 | int i; | |
1507 | ||
1508 | for (i = 0; adv7604_timings[i].bt.width; i++) { | |
1509 | if (v4l2_match_dv_timings(timings, &adv7604_timings[i], | |
1510 | is_digital_input(sd) ? 250000 : 1000000)) { | |
1511 | *timings = adv7604_timings[i]; | |
1512 | break; | |
1513 | } | |
1514 | } | |
1515 | } | |
1516 | ||
1517 | static unsigned int adv7604_read_hdmi_pixelclock(struct v4l2_subdev *sd) | |
1518 | { | |
1519 | unsigned int freq; | |
1520 | int a, b; | |
1521 | ||
1522 | a = hdmi_read(sd, 0x06); | |
1523 | b = hdmi_read(sd, 0x3b); | |
1524 | if (a < 0 || b < 0) | |
1525 | return 0; | |
1526 | freq = a * 1000000 + ((b & 0x30) >> 4) * 250000; | |
1527 | ||
1528 | if (is_hdmi(sd)) { | |
1529 | /* adjust for deep color mode */ | |
1530 | unsigned bits_per_channel = ((hdmi_read(sd, 0x0b) & 0x60) >> 4) + 8; | |
1531 | ||
1532 | freq = freq * 8 / bits_per_channel; | |
1533 | } | |
1534 | ||
1535 | return freq; | |
1536 | } | |
1537 | ||
1538 | static unsigned int adv7611_read_hdmi_pixelclock(struct v4l2_subdev *sd) | |
1539 | { | |
1540 | int a, b; | |
1541 | ||
1542 | a = hdmi_read(sd, 0x51); | |
1543 | b = hdmi_read(sd, 0x52); | |
1544 | if (a < 0 || b < 0) | |
1545 | return 0; | |
1546 | return ((a << 1) | (b >> 7)) * 1000000 + (b & 0x7f) * 1000000 / 128; | |
1547 | } | |
1548 | ||
1549 | static int adv7604_query_dv_timings(struct v4l2_subdev *sd, | |
1550 | struct v4l2_dv_timings *timings) | |
1551 | { | |
1552 | struct adv7604_state *state = to_state(sd); | |
1553 | const struct adv7604_chip_info *info = state->info; | |
1554 | struct v4l2_bt_timings *bt = &timings->bt; | |
1555 | struct stdi_readback stdi; | |
1556 | ||
1557 | if (!timings) | |
1558 | return -EINVAL; | |
1559 | ||
1560 | memset(timings, 0, sizeof(struct v4l2_dv_timings)); | |
1561 | ||
1562 | if (no_signal(sd)) { | |
1563 | state->restart_stdi_once = true; | |
1564 | v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__); | |
1565 | return -ENOLINK; | |
1566 | } | |
1567 | ||
1568 | /* read STDI */ | |
1569 | if (read_stdi(sd, &stdi)) { | |
1570 | v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__); | |
1571 | return -ENOLINK; | |
1572 | } | |
1573 | bt->interlaced = stdi.interlaced ? | |
1574 | V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE; | |
1575 | ||
1576 | if (is_digital_input(sd)) { | |
1577 | timings->type = V4L2_DV_BT_656_1120; | |
1578 | ||
1579 | /* FIXME: All masks are incorrect for ADV7611 */ | |
1580 | bt->width = hdmi_read16(sd, 0x07, 0xfff); | |
1581 | bt->height = hdmi_read16(sd, 0x09, 0xfff); | |
1582 | bt->pixelclock = info->read_hdmi_pixelclock(sd); | |
1583 | bt->hfrontporch = hdmi_read16(sd, 0x20, 0x3ff); | |
1584 | bt->hsync = hdmi_read16(sd, 0x22, 0x3ff); | |
1585 | bt->hbackporch = hdmi_read16(sd, 0x24, 0x3ff); | |
1586 | bt->vfrontporch = hdmi_read16(sd, 0x2a, 0x1fff) / 2; | |
1587 | bt->vsync = hdmi_read16(sd, 0x2e, 0x1fff) / 2; | |
1588 | bt->vbackporch = hdmi_read16(sd, 0x32, 0x1fff) / 2; | |
1589 | bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) | | |
1590 | ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0); | |
1591 | if (bt->interlaced == V4L2_DV_INTERLACED) { | |
1592 | bt->height += hdmi_read16(sd, 0x0b, 0xfff); | |
1593 | bt->il_vfrontporch = hdmi_read16(sd, 0x2c, 0x1fff) / 2; | |
1594 | bt->il_vsync = hdmi_read16(sd, 0x30, 0x1fff) / 2; | |
1595 | bt->vbackporch = hdmi_read16(sd, 0x34, 0x1fff) / 2; | |
1596 | } | |
1597 | adv7604_fill_optional_dv_timings_fields(sd, timings); | |
1598 | } else { | |
1599 | /* find format | |
1600 | * Since LCVS values are inaccurate [REF_03, p. 275-276], | |
1601 | * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails. | |
1602 | */ | |
1603 | if (!stdi2dv_timings(sd, &stdi, timings)) | |
1604 | goto found; | |
1605 | stdi.lcvs += 1; | |
1606 | v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs); | |
1607 | if (!stdi2dv_timings(sd, &stdi, timings)) | |
1608 | goto found; | |
1609 | stdi.lcvs -= 2; | |
1610 | v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs); | |
1611 | if (stdi2dv_timings(sd, &stdi, timings)) { | |
1612 | /* | |
1613 | * The STDI block may measure wrong values, especially | |
1614 | * for lcvs and lcf. If the driver can not find any | |
1615 | * valid timing, the STDI block is restarted to measure | |
1616 | * the video timings again. The function will return an | |
1617 | * error, but the restart of STDI will generate a new | |
1618 | * STDI interrupt and the format detection process will | |
1619 | * restart. | |
1620 | */ | |
1621 | if (state->restart_stdi_once) { | |
1622 | v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__); | |
1623 | /* TODO restart STDI for Sync Channel 2 */ | |
1624 | /* enter one-shot mode */ | |
1625 | cp_write_clr_set(sd, 0x86, 0x06, 0x00); | |
1626 | /* trigger STDI restart */ | |
1627 | cp_write_clr_set(sd, 0x86, 0x06, 0x04); | |
1628 | /* reset to continuous mode */ | |
1629 | cp_write_clr_set(sd, 0x86, 0x06, 0x02); | |
1630 | state->restart_stdi_once = false; | |
1631 | return -ENOLINK; | |
1632 | } | |
1633 | v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__); | |
1634 | return -ERANGE; | |
1635 | } | |
1636 | state->restart_stdi_once = true; | |
1637 | } | |
1638 | found: | |
1639 | ||
1640 | if (no_signal(sd)) { | |
1641 | v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__); | |
1642 | memset(timings, 0, sizeof(struct v4l2_dv_timings)); | |
1643 | return -ENOLINK; | |
1644 | } | |
1645 | ||
1646 | if ((is_analog_input(sd) && bt->pixelclock > 170000000) || | |
1647 | (is_digital_input(sd) && bt->pixelclock > 225000000)) { | |
1648 | v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n", | |
1649 | __func__, (u32)bt->pixelclock); | |
1650 | return -ERANGE; | |
1651 | } | |
1652 | ||
1653 | if (debug > 1) | |
1654 | v4l2_print_dv_timings(sd->name, "adv7604_query_dv_timings: ", | |
1655 | timings, true); | |
1656 | ||
1657 | return 0; | |
1658 | } | |
1659 | ||
1660 | static int adv7604_s_dv_timings(struct v4l2_subdev *sd, | |
1661 | struct v4l2_dv_timings *timings) | |
1662 | { | |
1663 | struct adv7604_state *state = to_state(sd); | |
1664 | struct v4l2_bt_timings *bt; | |
1665 | int err; | |
1666 | ||
1667 | if (!timings) | |
1668 | return -EINVAL; | |
1669 | ||
1670 | if (v4l2_match_dv_timings(&state->timings, timings, 0)) { | |
1671 | v4l2_dbg(1, debug, sd, "%s: no change\n", __func__); | |
1672 | return 0; | |
1673 | } | |
1674 | ||
1675 | bt = &timings->bt; | |
1676 | ||
1677 | if ((is_analog_input(sd) && bt->pixelclock > 170000000) || | |
1678 | (is_digital_input(sd) && bt->pixelclock > 225000000)) { | |
1679 | v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n", | |
1680 | __func__, (u32)bt->pixelclock); | |
1681 | return -ERANGE; | |
1682 | } | |
1683 | ||
1684 | adv7604_fill_optional_dv_timings_fields(sd, timings); | |
1685 | ||
1686 | state->timings = *timings; | |
1687 | ||
1688 | cp_write_clr_set(sd, 0x91, 0x40, bt->interlaced ? 0x40 : 0x00); | |
1689 | ||
1690 | /* Use prim_mode and vid_std when available */ | |
1691 | err = configure_predefined_video_timings(sd, timings); | |
1692 | if (err) { | |
1693 | /* custom settings when the video format | |
1694 | does not have prim_mode/vid_std */ | |
1695 | configure_custom_video_timings(sd, bt); | |
1696 | } | |
1697 | ||
1698 | set_rgb_quantization_range(sd); | |
1699 | ||
1700 | if (debug > 1) | |
1701 | v4l2_print_dv_timings(sd->name, "adv7604_s_dv_timings: ", | |
1702 | timings, true); | |
1703 | return 0; | |
1704 | } | |
1705 | ||
1706 | static int adv7604_g_dv_timings(struct v4l2_subdev *sd, | |
1707 | struct v4l2_dv_timings *timings) | |
1708 | { | |
1709 | struct adv7604_state *state = to_state(sd); | |
1710 | ||
1711 | *timings = state->timings; | |
1712 | return 0; | |
1713 | } | |
1714 | ||
1715 | static void adv7604_set_termination(struct v4l2_subdev *sd, bool enable) | |
1716 | { | |
1717 | hdmi_write(sd, 0x01, enable ? 0x00 : 0x78); | |
1718 | } | |
1719 | ||
1720 | static void adv7611_set_termination(struct v4l2_subdev *sd, bool enable) | |
1721 | { | |
1722 | hdmi_write(sd, 0x83, enable ? 0xfe : 0xff); | |
1723 | } | |
1724 | ||
1725 | static void enable_input(struct v4l2_subdev *sd) | |
1726 | { | |
1727 | struct adv7604_state *state = to_state(sd); | |
1728 | ||
1729 | if (is_analog_input(sd)) { | |
1730 | io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */ | |
1731 | } else if (is_digital_input(sd)) { | |
1732 | hdmi_write_clr_set(sd, 0x00, 0x03, state->selected_input); | |
1733 | state->info->set_termination(sd, true); | |
1734 | io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */ | |
1735 | hdmi_write_clr_set(sd, 0x1a, 0x10, 0x00); /* Unmute audio */ | |
1736 | } else { | |
1737 | v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", | |
1738 | __func__, state->selected_input); | |
1739 | } | |
1740 | } | |
1741 | ||
1742 | static void disable_input(struct v4l2_subdev *sd) | |
1743 | { | |
1744 | struct adv7604_state *state = to_state(sd); | |
1745 | ||
1746 | hdmi_write_clr_set(sd, 0x1a, 0x10, 0x10); /* Mute audio */ | |
1747 | msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 7.16.10] */ | |
1748 | io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */ | |
1749 | state->info->set_termination(sd, false); | |
1750 | } | |
1751 | ||
1752 | static void select_input(struct v4l2_subdev *sd) | |
1753 | { | |
1754 | struct adv7604_state *state = to_state(sd); | |
1755 | const struct adv7604_chip_info *info = state->info; | |
1756 | ||
1757 | if (is_analog_input(sd)) { | |
1758 | adv7604_write_reg_seq(sd, info->recommended_settings[0]); | |
1759 | ||
1760 | afe_write(sd, 0x00, 0x08); /* power up ADC */ | |
1761 | afe_write(sd, 0x01, 0x06); /* power up Analog Front End */ | |
1762 | afe_write(sd, 0xc8, 0x00); /* phase control */ | |
1763 | } else if (is_digital_input(sd)) { | |
1764 | hdmi_write(sd, 0x00, state->selected_input & 0x03); | |
1765 | ||
1766 | adv7604_write_reg_seq(sd, info->recommended_settings[1]); | |
1767 | ||
1768 | if (adv7604_has_afe(state)) { | |
1769 | afe_write(sd, 0x00, 0xff); /* power down ADC */ | |
1770 | afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */ | |
1771 | afe_write(sd, 0xc8, 0x40); /* phase control */ | |
1772 | } | |
1773 | ||
1774 | cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */ | |
1775 | cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */ | |
1776 | cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */ | |
1777 | } else { | |
1778 | v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", | |
1779 | __func__, state->selected_input); | |
1780 | } | |
1781 | } | |
1782 | ||
1783 | static int adv7604_s_routing(struct v4l2_subdev *sd, | |
1784 | u32 input, u32 output, u32 config) | |
1785 | { | |
1786 | struct adv7604_state *state = to_state(sd); | |
1787 | ||
1788 | v4l2_dbg(2, debug, sd, "%s: input %d, selected input %d", | |
1789 | __func__, input, state->selected_input); | |
1790 | ||
1791 | if (input == state->selected_input) | |
1792 | return 0; | |
1793 | ||
1794 | if (input > state->info->max_port) | |
1795 | return -EINVAL; | |
1796 | ||
1797 | state->selected_input = input; | |
1798 | ||
1799 | disable_input(sd); | |
1800 | ||
1801 | select_input(sd); | |
1802 | ||
1803 | enable_input(sd); | |
1804 | ||
1805 | return 0; | |
1806 | } | |
1807 | ||
1808 | static int adv7604_enum_mbus_code(struct v4l2_subdev *sd, | |
1809 | struct v4l2_subdev_fh *fh, | |
1810 | struct v4l2_subdev_mbus_code_enum *code) | |
1811 | { | |
1812 | struct adv7604_state *state = to_state(sd); | |
1813 | ||
1814 | if (code->index >= state->info->nformats) | |
1815 | return -EINVAL; | |
1816 | ||
1817 | code->code = state->info->formats[code->index].code; | |
1818 | ||
1819 | return 0; | |
1820 | } | |
1821 | ||
1822 | static void adv7604_fill_format(struct adv7604_state *state, | |
1823 | struct v4l2_mbus_framefmt *format) | |
1824 | { | |
1825 | memset(format, 0, sizeof(*format)); | |
1826 | ||
1827 | format->width = state->timings.bt.width; | |
1828 | format->height = state->timings.bt.height; | |
1829 | format->field = V4L2_FIELD_NONE; | |
1830 | ||
1831 | if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) | |
1832 | format->colorspace = (state->timings.bt.height <= 576) ? | |
1833 | V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709; | |
1834 | } | |
1835 | ||
1836 | /* | |
1837 | * Compute the op_ch_sel value required to obtain on the bus the component order | |
1838 | * corresponding to the selected format taking into account bus reordering | |
1839 | * applied by the board at the output of the device. | |
1840 | * | |
1841 | * The following table gives the op_ch_value from the format component order | |
1842 | * (expressed as op_ch_sel value in column) and the bus reordering (expressed as | |
1843 | * adv7604_bus_order value in row). | |
1844 | * | |
1845 | * | GBR(0) GRB(1) BGR(2) RGB(3) BRG(4) RBG(5) | |
1846 | * ----------+------------------------------------------------- | |
1847 | * RGB (NOP) | GBR GRB BGR RGB BRG RBG | |
1848 | * GRB (1-2) | BGR RGB GBR GRB RBG BRG | |
1849 | * RBG (2-3) | GRB GBR BRG RBG BGR RGB | |
1850 | * BGR (1-3) | RBG BRG RGB BGR GRB GBR | |
1851 | * BRG (ROR) | BRG RBG GRB GBR RGB BGR | |
1852 | * GBR (ROL) | RGB BGR RBG BRG GBR GRB | |
1853 | */ | |
1854 | static unsigned int adv7604_op_ch_sel(struct adv7604_state *state) | |
1855 | { | |
1856 | #define _SEL(a,b,c,d,e,f) { \ | |
1857 | ADV7604_OP_CH_SEL_##a, ADV7604_OP_CH_SEL_##b, ADV7604_OP_CH_SEL_##c, \ | |
1858 | ADV7604_OP_CH_SEL_##d, ADV7604_OP_CH_SEL_##e, ADV7604_OP_CH_SEL_##f } | |
1859 | #define _BUS(x) [ADV7604_BUS_ORDER_##x] | |
1860 | ||
1861 | static const unsigned int op_ch_sel[6][6] = { | |
1862 | _BUS(RGB) /* NOP */ = _SEL(GBR, GRB, BGR, RGB, BRG, RBG), | |
1863 | _BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG), | |
1864 | _BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB), | |
1865 | _BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR), | |
1866 | _BUS(BRG) /* ROR */ = _SEL(BRG, RBG, GRB, GBR, RGB, BGR), | |
1867 | _BUS(GBR) /* ROL */ = _SEL(RGB, BGR, RBG, BRG, GBR, GRB), | |
1868 | }; | |
1869 | ||
1870 | return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5]; | |
1871 | } | |
1872 | ||
1873 | static void adv7604_setup_format(struct adv7604_state *state) | |
1874 | { | |
1875 | struct v4l2_subdev *sd = &state->sd; | |
1876 | ||
1877 | io_write_clr_set(sd, 0x02, 0x02, | |
1878 | state->format->rgb_out ? ADV7604_RGB_OUT : 0); | |
1879 | io_write(sd, 0x03, state->format->op_format_sel | | |
1880 | state->pdata.op_format_mode_sel); | |
1881 | io_write_clr_set(sd, 0x04, 0xe0, adv7604_op_ch_sel(state)); | |
1882 | io_write_clr_set(sd, 0x05, 0x01, | |
1883 | state->format->swap_cb_cr ? ADV7604_OP_SWAP_CB_CR : 0); | |
1884 | } | |
1885 | ||
1886 | static int adv7604_get_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh, | |
1887 | struct v4l2_subdev_format *format) | |
1888 | { | |
1889 | struct adv7604_state *state = to_state(sd); | |
1890 | ||
1891 | if (format->pad != state->source_pad) | |
1892 | return -EINVAL; | |
1893 | ||
1894 | adv7604_fill_format(state, &format->format); | |
1895 | ||
1896 | if (format->which == V4L2_SUBDEV_FORMAT_TRY) { | |
1897 | struct v4l2_mbus_framefmt *fmt; | |
1898 | ||
1899 | fmt = v4l2_subdev_get_try_format(fh, format->pad); | |
1900 | format->format.code = fmt->code; | |
1901 | } else { | |
1902 | format->format.code = state->format->code; | |
1903 | } | |
1904 | ||
1905 | return 0; | |
1906 | } | |
1907 | ||
1908 | static int adv7604_set_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh, | |
1909 | struct v4l2_subdev_format *format) | |
1910 | { | |
1911 | struct adv7604_state *state = to_state(sd); | |
1912 | const struct adv7604_format_info *info; | |
1913 | ||
1914 | if (format->pad != state->source_pad) | |
1915 | return -EINVAL; | |
1916 | ||
1917 | info = adv7604_format_info(state, format->format.code); | |
1918 | if (info == NULL) | |
1919 | info = adv7604_format_info(state, V4L2_MBUS_FMT_YUYV8_2X8); | |
1920 | ||
1921 | adv7604_fill_format(state, &format->format); | |
1922 | format->format.code = info->code; | |
1923 | ||
1924 | if (format->which == V4L2_SUBDEV_FORMAT_TRY) { | |
1925 | struct v4l2_mbus_framefmt *fmt; | |
1926 | ||
1927 | fmt = v4l2_subdev_get_try_format(fh, format->pad); | |
1928 | fmt->code = format->format.code; | |
1929 | } else { | |
1930 | state->format = info; | |
1931 | adv7604_setup_format(state); | |
1932 | } | |
1933 | ||
1934 | return 0; | |
1935 | } | |
1936 | ||
1937 | static int adv7604_isr(struct v4l2_subdev *sd, u32 status, bool *handled) | |
1938 | { | |
1939 | struct adv7604_state *state = to_state(sd); | |
1940 | const struct adv7604_chip_info *info = state->info; | |
1941 | const u8 irq_reg_0x43 = io_read(sd, 0x43); | |
1942 | const u8 irq_reg_0x6b = io_read(sd, 0x6b); | |
1943 | const u8 irq_reg_0x70 = io_read(sd, 0x70); | |
1944 | u8 fmt_change_digital; | |
1945 | u8 fmt_change; | |
1946 | u8 tx_5v; | |
1947 | ||
1948 | if (irq_reg_0x43) | |
1949 | io_write(sd, 0x44, irq_reg_0x43); | |
1950 | if (irq_reg_0x70) | |
1951 | io_write(sd, 0x71, irq_reg_0x70); | |
1952 | if (irq_reg_0x6b) | |
1953 | io_write(sd, 0x6c, irq_reg_0x6b); | |
1954 | ||
1955 | v4l2_dbg(2, debug, sd, "%s: ", __func__); | |
1956 | ||
1957 | /* format change */ | |
1958 | fmt_change = irq_reg_0x43 & 0x98; | |
1959 | fmt_change_digital = is_digital_input(sd) | |
1960 | ? irq_reg_0x6b & info->fmt_change_digital_mask | |
1961 | : 0; | |
1962 | ||
1963 | if (fmt_change || fmt_change_digital) { | |
1964 | v4l2_dbg(1, debug, sd, | |
1965 | "%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n", | |
1966 | __func__, fmt_change, fmt_change_digital); | |
1967 | ||
1968 | v4l2_subdev_notify(sd, ADV7604_FMT_CHANGE, NULL); | |
1969 | ||
1970 | if (handled) | |
1971 | *handled = true; | |
1972 | } | |
1973 | /* HDMI/DVI mode */ | |
1974 | if (irq_reg_0x6b & 0x01) { | |
1975 | v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__, | |
1976 | (io_read(sd, 0x6a) & 0x01) ? "HDMI" : "DVI"); | |
1977 | set_rgb_quantization_range(sd); | |
1978 | if (handled) | |
1979 | *handled = true; | |
1980 | } | |
1981 | ||
1982 | /* tx 5v detect */ | |
1983 | tx_5v = io_read(sd, 0x70) & info->cable_det_mask; | |
1984 | if (tx_5v) { | |
1985 | v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v); | |
1986 | io_write(sd, 0x71, tx_5v); | |
1987 | adv7604_s_detect_tx_5v_ctrl(sd); | |
1988 | if (handled) | |
1989 | *handled = true; | |
1990 | } | |
1991 | return 0; | |
1992 | } | |
1993 | ||
1994 | static int adv7604_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) | |
1995 | { | |
1996 | struct adv7604_state *state = to_state(sd); | |
1997 | u8 *data = NULL; | |
1998 | ||
1999 | if (edid->pad > ADV7604_PAD_HDMI_PORT_D) | |
2000 | return -EINVAL; | |
2001 | if (edid->blocks == 0) | |
2002 | return -EINVAL; | |
2003 | if (edid->blocks > 2) | |
2004 | return -EINVAL; | |
2005 | if (edid->start_block > 1) | |
2006 | return -EINVAL; | |
2007 | if (edid->start_block == 1) | |
2008 | edid->blocks = 1; | |
2009 | ||
2010 | if (edid->blocks > state->edid.blocks) | |
2011 | edid->blocks = state->edid.blocks; | |
2012 | ||
2013 | switch (edid->pad) { | |
2014 | case ADV7604_PAD_HDMI_PORT_A: | |
2015 | case ADV7604_PAD_HDMI_PORT_B: | |
2016 | case ADV7604_PAD_HDMI_PORT_C: | |
2017 | case ADV7604_PAD_HDMI_PORT_D: | |
2018 | if (state->edid.present & (1 << edid->pad)) | |
2019 | data = state->edid.edid; | |
2020 | break; | |
2021 | default: | |
2022 | return -EINVAL; | |
2023 | break; | |
2024 | } | |
2025 | if (!data) | |
2026 | return -ENODATA; | |
2027 | ||
2028 | memcpy(edid->edid, | |
2029 | data + edid->start_block * 128, | |
2030 | edid->blocks * 128); | |
2031 | return 0; | |
2032 | } | |
2033 | ||
2034 | static int get_edid_spa_location(const u8 *edid) | |
2035 | { | |
2036 | u8 d; | |
2037 | ||
2038 | if ((edid[0x7e] != 1) || | |
2039 | (edid[0x80] != 0x02) || | |
2040 | (edid[0x81] != 0x03)) { | |
2041 | return -1; | |
2042 | } | |
2043 | ||
2044 | /* search Vendor Specific Data Block (tag 3) */ | |
2045 | d = edid[0x82] & 0x7f; | |
2046 | if (d > 4) { | |
2047 | int i = 0x84; | |
2048 | int end = 0x80 + d; | |
2049 | ||
2050 | do { | |
2051 | u8 tag = edid[i] >> 5; | |
2052 | u8 len = edid[i] & 0x1f; | |
2053 | ||
2054 | if ((tag == 3) && (len >= 5)) | |
2055 | return i + 4; | |
2056 | i += len + 1; | |
2057 | } while (i < end); | |
2058 | } | |
2059 | return -1; | |
2060 | } | |
2061 | ||
2062 | static int adv7604_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) | |
2063 | { | |
2064 | struct adv7604_state *state = to_state(sd); | |
2065 | const struct adv7604_chip_info *info = state->info; | |
2066 | int spa_loc; | |
2067 | int err; | |
2068 | int i; | |
2069 | ||
2070 | if (edid->pad > ADV7604_PAD_HDMI_PORT_D) | |
2071 | return -EINVAL; | |
2072 | if (edid->start_block != 0) | |
2073 | return -EINVAL; | |
2074 | if (edid->blocks == 0) { | |
2075 | /* Disable hotplug and I2C access to EDID RAM from DDC port */ | |
2076 | state->edid.present &= ~(1 << edid->pad); | |
2077 | adv7604_set_hpd(state, state->edid.present); | |
2078 | rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present); | |
2079 | ||
2080 | /* Fall back to a 16:9 aspect ratio */ | |
2081 | state->aspect_ratio.numerator = 16; | |
2082 | state->aspect_ratio.denominator = 9; | |
2083 | ||
2084 | if (!state->edid.present) | |
2085 | state->edid.blocks = 0; | |
2086 | ||
2087 | v4l2_dbg(2, debug, sd, "%s: clear EDID pad %d, edid.present = 0x%x\n", | |
2088 | __func__, edid->pad, state->edid.present); | |
2089 | return 0; | |
2090 | } | |
2091 | if (edid->blocks > 2) { | |
2092 | edid->blocks = 2; | |
2093 | return -E2BIG; | |
2094 | } | |
2095 | ||
2096 | v4l2_dbg(2, debug, sd, "%s: write EDID pad %d, edid.present = 0x%x\n", | |
2097 | __func__, edid->pad, state->edid.present); | |
2098 | ||
2099 | /* Disable hotplug and I2C access to EDID RAM from DDC port */ | |
2100 | cancel_delayed_work_sync(&state->delayed_work_enable_hotplug); | |
2101 | adv7604_set_hpd(state, 0); | |
2102 | rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, 0x00); | |
2103 | ||
2104 | spa_loc = get_edid_spa_location(edid->edid); | |
2105 | if (spa_loc < 0) | |
2106 | spa_loc = 0xc0; /* Default value [REF_02, p. 116] */ | |
2107 | ||
2108 | switch (edid->pad) { | |
2109 | case ADV7604_PAD_HDMI_PORT_A: | |
2110 | state->spa_port_a[0] = edid->edid[spa_loc]; | |
2111 | state->spa_port_a[1] = edid->edid[spa_loc + 1]; | |
2112 | break; | |
2113 | case ADV7604_PAD_HDMI_PORT_B: | |
2114 | rep_write(sd, 0x70, edid->edid[spa_loc]); | |
2115 | rep_write(sd, 0x71, edid->edid[spa_loc + 1]); | |
2116 | break; | |
2117 | case ADV7604_PAD_HDMI_PORT_C: | |
2118 | rep_write(sd, 0x72, edid->edid[spa_loc]); | |
2119 | rep_write(sd, 0x73, edid->edid[spa_loc + 1]); | |
2120 | break; | |
2121 | case ADV7604_PAD_HDMI_PORT_D: | |
2122 | rep_write(sd, 0x74, edid->edid[spa_loc]); | |
2123 | rep_write(sd, 0x75, edid->edid[spa_loc + 1]); | |
2124 | break; | |
2125 | default: | |
2126 | return -EINVAL; | |
2127 | } | |
2128 | ||
2129 | if (info->type == ADV7604) { | |
2130 | rep_write(sd, 0x76, spa_loc & 0xff); | |
2131 | rep_write_clr_set(sd, 0x77, 0x40, (spa_loc & 0x100) >> 2); | |
2132 | } else { | |
2133 | /* FIXME: Where is the SPA location LSB register ? */ | |
2134 | rep_write_clr_set(sd, 0x71, 0x01, (spa_loc & 0x100) >> 8); | |
2135 | } | |
2136 | ||
2137 | edid->edid[spa_loc] = state->spa_port_a[0]; | |
2138 | edid->edid[spa_loc + 1] = state->spa_port_a[1]; | |
2139 | ||
2140 | memcpy(state->edid.edid, edid->edid, 128 * edid->blocks); | |
2141 | state->edid.blocks = edid->blocks; | |
2142 | state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15], | |
2143 | edid->edid[0x16]); | |
2144 | state->edid.present |= 1 << edid->pad; | |
2145 | ||
2146 | err = edid_write_block(sd, 128 * edid->blocks, state->edid.edid); | |
2147 | if (err < 0) { | |
2148 | v4l2_err(sd, "error %d writing edid pad %d\n", err, edid->pad); | |
2149 | return err; | |
2150 | } | |
2151 | ||
2152 | /* adv7604 calculates the checksums and enables I2C access to internal | |
2153 | EDID RAM from DDC port. */ | |
2154 | rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present); | |
2155 | ||
2156 | for (i = 0; i < 1000; i++) { | |
2157 | if (rep_read(sd, info->edid_status_reg) & state->edid.present) | |
2158 | break; | |
2159 | mdelay(1); | |
2160 | } | |
2161 | if (i == 1000) { | |
2162 | v4l2_err(sd, "error enabling edid (0x%x)\n", state->edid.present); | |
2163 | return -EIO; | |
2164 | } | |
2165 | ||
2166 | ||
2167 | /* enable hotplug after 100 ms */ | |
2168 | queue_delayed_work(state->work_queues, | |
2169 | &state->delayed_work_enable_hotplug, HZ / 10); | |
2170 | return 0; | |
2171 | } | |
2172 | ||
2173 | /*********** avi info frame CEA-861-E **************/ | |
2174 | ||
2175 | static void print_avi_infoframe(struct v4l2_subdev *sd) | |
2176 | { | |
2177 | int i; | |
2178 | u8 buf[14]; | |
2179 | u8 avi_len; | |
2180 | u8 avi_ver; | |
2181 | ||
2182 | if (!is_hdmi(sd)) { | |
2183 | v4l2_info(sd, "receive DVI-D signal (AVI infoframe not supported)\n"); | |
2184 | return; | |
2185 | } | |
2186 | if (!(io_read(sd, 0x60) & 0x01)) { | |
2187 | v4l2_info(sd, "AVI infoframe not received\n"); | |
2188 | return; | |
2189 | } | |
2190 | ||
2191 | if (io_read(sd, 0x83) & 0x01) { | |
2192 | v4l2_info(sd, "AVI infoframe checksum error has occurred earlier\n"); | |
2193 | io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */ | |
2194 | if (io_read(sd, 0x83) & 0x01) { | |
2195 | v4l2_info(sd, "AVI infoframe checksum error still present\n"); | |
2196 | io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */ | |
2197 | } | |
2198 | } | |
2199 | ||
2200 | avi_len = infoframe_read(sd, 0xe2); | |
2201 | avi_ver = infoframe_read(sd, 0xe1); | |
2202 | v4l2_info(sd, "AVI infoframe version %d (%d byte)\n", | |
2203 | avi_ver, avi_len); | |
2204 | ||
2205 | if (avi_ver != 0x02) | |
2206 | return; | |
2207 | ||
2208 | for (i = 0; i < 14; i++) | |
2209 | buf[i] = infoframe_read(sd, i); | |
2210 | ||
2211 | v4l2_info(sd, | |
2212 | "\t%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", | |
2213 | buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7], | |
2214 | buf[8], buf[9], buf[10], buf[11], buf[12], buf[13]); | |
2215 | } | |
2216 | ||
2217 | static int adv7604_log_status(struct v4l2_subdev *sd) | |
2218 | { | |
2219 | struct adv7604_state *state = to_state(sd); | |
2220 | const struct adv7604_chip_info *info = state->info; | |
2221 | struct v4l2_dv_timings timings; | |
2222 | struct stdi_readback stdi; | |
2223 | u8 reg_io_0x02 = io_read(sd, 0x02); | |
2224 | u8 edid_enabled; | |
2225 | u8 cable_det; | |
2226 | ||
2227 | static const char * const csc_coeff_sel_rb[16] = { | |
2228 | "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB", | |
2229 | "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709", | |
2230 | "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709", | |
2231 | "reserved", "reserved", "reserved", "reserved", "manual" | |
2232 | }; | |
2233 | static const char * const input_color_space_txt[16] = { | |
2234 | "RGB limited range (16-235)", "RGB full range (0-255)", | |
2235 | "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)", | |
2236 | "xvYCC Bt.601", "xvYCC Bt.709", | |
2237 | "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)", | |
2238 | "invalid", "invalid", "invalid", "invalid", "invalid", | |
2239 | "invalid", "invalid", "automatic" | |
2240 | }; | |
2241 | static const char * const rgb_quantization_range_txt[] = { | |
2242 | "Automatic", | |
2243 | "RGB limited range (16-235)", | |
2244 | "RGB full range (0-255)", | |
2245 | }; | |
2246 | static const char * const deep_color_mode_txt[4] = { | |
2247 | "8-bits per channel", | |
2248 | "10-bits per channel", | |
2249 | "12-bits per channel", | |
2250 | "16-bits per channel (not supported)" | |
2251 | }; | |
2252 | ||
2253 | v4l2_info(sd, "-----Chip status-----\n"); | |
2254 | v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on"); | |
2255 | edid_enabled = rep_read(sd, info->edid_status_reg); | |
2256 | v4l2_info(sd, "EDID enabled port A: %s, B: %s, C: %s, D: %s\n", | |
2257 | ((edid_enabled & 0x01) ? "Yes" : "No"), | |
2258 | ((edid_enabled & 0x02) ? "Yes" : "No"), | |
2259 | ((edid_enabled & 0x04) ? "Yes" : "No"), | |
2260 | ((edid_enabled & 0x08) ? "Yes" : "No")); | |
2261 | v4l2_info(sd, "CEC: %s\n", !!(cec_read(sd, 0x2a) & 0x01) ? | |
2262 | "enabled" : "disabled"); | |
2263 | ||
2264 | v4l2_info(sd, "-----Signal status-----\n"); | |
2265 | cable_det = info->read_cable_det(sd); | |
2266 | v4l2_info(sd, "Cable detected (+5V power) port A: %s, B: %s, C: %s, D: %s\n", | |
2267 | ((cable_det & 0x01) ? "Yes" : "No"), | |
2268 | ((cable_det & 0x02) ? "Yes" : "No"), | |
2269 | ((cable_det & 0x04) ? "Yes" : "No"), | |
2270 | ((cable_det & 0x08) ? "Yes" : "No")); | |
2271 | v4l2_info(sd, "TMDS signal detected: %s\n", | |
2272 | no_signal_tmds(sd) ? "false" : "true"); | |
2273 | v4l2_info(sd, "TMDS signal locked: %s\n", | |
2274 | no_lock_tmds(sd) ? "false" : "true"); | |
2275 | v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true"); | |
2276 | v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true"); | |
2277 | v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true"); | |
2278 | v4l2_info(sd, "CP free run: %s\n", | |
2279 | (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off")); | |
2280 | v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n", | |
2281 | io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f, | |
2282 | (io_read(sd, 0x01) & 0x70) >> 4); | |
2283 | ||
2284 | v4l2_info(sd, "-----Video Timings-----\n"); | |
2285 | if (read_stdi(sd, &stdi)) | |
2286 | v4l2_info(sd, "STDI: not locked\n"); | |
2287 | else | |
2288 | v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n", | |
2289 | stdi.lcf, stdi.bl, stdi.lcvs, | |
2290 | stdi.interlaced ? "interlaced" : "progressive", | |
2291 | stdi.hs_pol, stdi.vs_pol); | |
2292 | if (adv7604_query_dv_timings(sd, &timings)) | |
2293 | v4l2_info(sd, "No video detected\n"); | |
2294 | else | |
2295 | v4l2_print_dv_timings(sd->name, "Detected format: ", | |
2296 | &timings, true); | |
2297 | v4l2_print_dv_timings(sd->name, "Configured format: ", | |
2298 | &state->timings, true); | |
2299 | ||
2300 | if (no_signal(sd)) | |
2301 | return 0; | |
2302 | ||
2303 | v4l2_info(sd, "-----Color space-----\n"); | |
2304 | v4l2_info(sd, "RGB quantization range ctrl: %s\n", | |
2305 | rgb_quantization_range_txt[state->rgb_quantization_range]); | |
2306 | v4l2_info(sd, "Input color space: %s\n", | |
2307 | input_color_space_txt[reg_io_0x02 >> 4]); | |
2308 | v4l2_info(sd, "Output color space: %s %s, saturator %s\n", | |
2309 | (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr", | |
2310 | (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)", | |
2311 | ((reg_io_0x02 & 0x04) ^ (reg_io_0x02 & 0x01)) ? | |
2312 | "enabled" : "disabled"); | |
2313 | v4l2_info(sd, "Color space conversion: %s\n", | |
2314 | csc_coeff_sel_rb[cp_read(sd, 0xfc) >> 4]); | |
2315 | ||
2316 | if (!is_digital_input(sd)) | |
2317 | return 0; | |
2318 | ||
2319 | v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D"); | |
2320 | v4l2_info(sd, "Digital video port selected: %c\n", | |
2321 | (hdmi_read(sd, 0x00) & 0x03) + 'A'); | |
2322 | v4l2_info(sd, "HDCP encrypted content: %s\n", | |
2323 | (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false"); | |
2324 | v4l2_info(sd, "HDCP keys read: %s%s\n", | |
2325 | (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no", | |
2326 | (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : ""); | |
2327 | if (!is_hdmi(sd)) { | |
2328 | bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01; | |
2329 | bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01; | |
2330 | bool audio_mute = io_read(sd, 0x65) & 0x40; | |
2331 | ||
2332 | v4l2_info(sd, "Audio: pll %s, samples %s, %s\n", | |
2333 | audio_pll_locked ? "locked" : "not locked", | |
2334 | audio_sample_packet_detect ? "detected" : "not detected", | |
2335 | audio_mute ? "muted" : "enabled"); | |
2336 | if (audio_pll_locked && audio_sample_packet_detect) { | |
2337 | v4l2_info(sd, "Audio format: %s\n", | |
2338 | (hdmi_read(sd, 0x07) & 0x20) ? "multi-channel" : "stereo"); | |
2339 | } | |
2340 | v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) + | |
2341 | (hdmi_read(sd, 0x5c) << 8) + | |
2342 | (hdmi_read(sd, 0x5d) & 0xf0)); | |
2343 | v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) + | |
2344 | (hdmi_read(sd, 0x5e) << 8) + | |
2345 | hdmi_read(sd, 0x5f)); | |
2346 | v4l2_info(sd, "AV Mute: %s\n", (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off"); | |
2347 | ||
2348 | v4l2_info(sd, "Deep color mode: %s\n", deep_color_mode_txt[(hdmi_read(sd, 0x0b) & 0x60) >> 5]); | |
2349 | ||
2350 | print_avi_infoframe(sd); | |
2351 | } | |
2352 | ||
2353 | return 0; | |
2354 | } | |
2355 | ||
2356 | /* ----------------------------------------------------------------------- */ | |
2357 | ||
2358 | static const struct v4l2_ctrl_ops adv7604_ctrl_ops = { | |
2359 | .s_ctrl = adv7604_s_ctrl, | |
2360 | }; | |
2361 | ||
2362 | static const struct v4l2_subdev_core_ops adv7604_core_ops = { | |
2363 | .log_status = adv7604_log_status, | |
2364 | .interrupt_service_routine = adv7604_isr, | |
2365 | #ifdef CONFIG_VIDEO_ADV_DEBUG | |
2366 | .g_register = adv7604_g_register, | |
2367 | .s_register = adv7604_s_register, | |
2368 | #endif | |
2369 | }; | |
2370 | ||
2371 | static const struct v4l2_subdev_video_ops adv7604_video_ops = { | |
2372 | .s_routing = adv7604_s_routing, | |
2373 | .g_input_status = adv7604_g_input_status, | |
2374 | .s_dv_timings = adv7604_s_dv_timings, | |
2375 | .g_dv_timings = adv7604_g_dv_timings, | |
2376 | .query_dv_timings = adv7604_query_dv_timings, | |
2377 | }; | |
2378 | ||
2379 | static const struct v4l2_subdev_pad_ops adv7604_pad_ops = { | |
2380 | .enum_mbus_code = adv7604_enum_mbus_code, | |
2381 | .get_fmt = adv7604_get_format, | |
2382 | .set_fmt = adv7604_set_format, | |
2383 | .get_edid = adv7604_get_edid, | |
2384 | .set_edid = adv7604_set_edid, | |
2385 | .dv_timings_cap = adv7604_dv_timings_cap, | |
2386 | .enum_dv_timings = adv7604_enum_dv_timings, | |
2387 | }; | |
2388 | ||
2389 | static const struct v4l2_subdev_ops adv7604_ops = { | |
2390 | .core = &adv7604_core_ops, | |
2391 | .video = &adv7604_video_ops, | |
2392 | .pad = &adv7604_pad_ops, | |
2393 | }; | |
2394 | ||
2395 | /* -------------------------- custom ctrls ---------------------------------- */ | |
2396 | ||
2397 | static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = { | |
2398 | .ops = &adv7604_ctrl_ops, | |
2399 | .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE, | |
2400 | .name = "Analog Sampling Phase", | |
2401 | .type = V4L2_CTRL_TYPE_INTEGER, | |
2402 | .min = 0, | |
2403 | .max = 0x1f, | |
2404 | .step = 1, | |
2405 | .def = 0, | |
2406 | }; | |
2407 | ||
2408 | static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color_manual = { | |
2409 | .ops = &adv7604_ctrl_ops, | |
2410 | .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL, | |
2411 | .name = "Free Running Color, Manual", | |
2412 | .type = V4L2_CTRL_TYPE_BOOLEAN, | |
2413 | .min = false, | |
2414 | .max = true, | |
2415 | .step = 1, | |
2416 | .def = false, | |
2417 | }; | |
2418 | ||
2419 | static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color = { | |
2420 | .ops = &adv7604_ctrl_ops, | |
2421 | .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR, | |
2422 | .name = "Free Running Color", | |
2423 | .type = V4L2_CTRL_TYPE_INTEGER, | |
2424 | .min = 0x0, | |
2425 | .max = 0xffffff, | |
2426 | .step = 0x1, | |
2427 | .def = 0x0, | |
2428 | }; | |
2429 | ||
2430 | /* ----------------------------------------------------------------------- */ | |
2431 | ||
2432 | static int adv7604_core_init(struct v4l2_subdev *sd) | |
2433 | { | |
2434 | struct adv7604_state *state = to_state(sd); | |
2435 | const struct adv7604_chip_info *info = state->info; | |
2436 | struct adv7604_platform_data *pdata = &state->pdata; | |
2437 | ||
2438 | hdmi_write(sd, 0x48, | |
2439 | (pdata->disable_pwrdnb ? 0x80 : 0) | | |
2440 | (pdata->disable_cable_det_rst ? 0x40 : 0)); | |
2441 | ||
2442 | disable_input(sd); | |
2443 | ||
2444 | if (pdata->default_input >= 0 && | |
2445 | pdata->default_input < state->source_pad) { | |
2446 | state->selected_input = pdata->default_input; | |
2447 | select_input(sd); | |
2448 | enable_input(sd); | |
2449 | } | |
2450 | ||
2451 | /* power */ | |
2452 | io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */ | |
2453 | io_write(sd, 0x0b, 0x44); /* Power down ESDP block */ | |
2454 | cp_write(sd, 0xcf, 0x01); /* Power down macrovision */ | |
2455 | ||
2456 | /* video format */ | |
2457 | io_write_clr_set(sd, 0x02, 0x0f, | |
2458 | pdata->alt_gamma << 3 | | |
2459 | pdata->op_656_range << 2 | | |
2460 | pdata->alt_data_sat << 0); | |
2461 | io_write_clr_set(sd, 0x05, 0x0e, pdata->blank_data << 3 | | |
2462 | pdata->insert_av_codes << 2 | | |
2463 | pdata->replicate_av_codes << 1); | |
2464 | adv7604_setup_format(state); | |
2465 | ||
2466 | cp_write(sd, 0x69, 0x30); /* Enable CP CSC */ | |
2467 | ||
2468 | /* VS, HS polarities */ | |
2469 | io_write(sd, 0x06, 0xa0 | pdata->inv_vs_pol << 2 | pdata->inv_hs_pol << 1); | |
2470 | ||
2471 | /* Adjust drive strength */ | |
2472 | io_write(sd, 0x14, 0x40 | pdata->dr_str_data << 4 | | |
2473 | pdata->dr_str_clk << 2 | | |
2474 | pdata->dr_str_sync); | |
2475 | ||
2476 | cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */ | |
2477 | cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */ | |
2478 | cp_write(sd, 0xf9, 0x23); /* STDI ch. 1 - LCVS change threshold - | |
2479 | ADI recommended setting [REF_01, c. 2.3.3] */ | |
2480 | cp_write(sd, 0x45, 0x23); /* STDI ch. 2 - LCVS change threshold - | |
2481 | ADI recommended setting [REF_01, c. 2.3.3] */ | |
2482 | cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution | |
2483 | for digital formats */ | |
2484 | ||
2485 | /* HDMI audio */ | |
2486 | hdmi_write_clr_set(sd, 0x15, 0x03, 0x03); /* Mute on FIFO over-/underflow [REF_01, c. 1.2.18] */ | |
2487 | hdmi_write_clr_set(sd, 0x1a, 0x0e, 0x08); /* Wait 1 s before unmute */ | |
2488 | hdmi_write_clr_set(sd, 0x68, 0x06, 0x06); /* FIFO reset on over-/underflow [REF_01, c. 1.2.19] */ | |
2489 | ||
2490 | /* TODO from platform data */ | |
2491 | afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */ | |
2492 | ||
2493 | if (adv7604_has_afe(state)) { | |
2494 | afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */ | |
2495 | io_write_clr_set(sd, 0x30, 1 << 4, pdata->output_bus_lsb_to_msb << 4); | |
2496 | } | |
2497 | ||
2498 | /* interrupts */ | |
2499 | io_write(sd, 0x40, 0xc0 | pdata->int1_config); /* Configure INT1 */ | |
2500 | io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */ | |
2501 | io_write(sd, 0x6e, info->fmt_change_digital_mask); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */ | |
2502 | io_write(sd, 0x73, info->cable_det_mask); /* Enable cable detection (+5v) interrupts */ | |
2503 | info->setup_irqs(sd); | |
2504 | ||
2505 | return v4l2_ctrl_handler_setup(sd->ctrl_handler); | |
2506 | } | |
2507 | ||
2508 | static void adv7604_setup_irqs(struct v4l2_subdev *sd) | |
2509 | { | |
2510 | io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */ | |
2511 | } | |
2512 | ||
2513 | static void adv7611_setup_irqs(struct v4l2_subdev *sd) | |
2514 | { | |
2515 | io_write(sd, 0x41, 0xd0); /* STDI irq for any change, disable INT2 */ | |
2516 | } | |
2517 | ||
2518 | static void adv7604_unregister_clients(struct adv7604_state *state) | |
2519 | { | |
2520 | unsigned int i; | |
2521 | ||
2522 | for (i = 1; i < ARRAY_SIZE(state->i2c_clients); ++i) { | |
2523 | if (state->i2c_clients[i]) | |
2524 | i2c_unregister_device(state->i2c_clients[i]); | |
2525 | } | |
2526 | } | |
2527 | ||
2528 | static struct i2c_client *adv7604_dummy_client(struct v4l2_subdev *sd, | |
2529 | u8 addr, u8 io_reg) | |
2530 | { | |
2531 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
2532 | ||
2533 | if (addr) | |
2534 | io_write(sd, io_reg, addr << 1); | |
2535 | return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1); | |
2536 | } | |
2537 | ||
2538 | static const struct adv7604_reg_seq adv7604_recommended_settings_afe[] = { | |
2539 | /* reset ADI recommended settings for HDMI: */ | |
2540 | /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */ | |
2541 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */ | |
2542 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */ | |
2543 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x3d), 0x00 }, /* DDC bus active pull-up control */ | |
2544 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x3e), 0x74 }, /* TMDS PLL optimization */ | |
2545 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */ | |
2546 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x57), 0x74 }, /* TMDS PLL optimization */ | |
2547 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x58), 0x63 }, /* TMDS PLL optimization */ | |
2548 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */ | |
2549 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */ | |
2550 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x93), 0x88 }, /* equaliser */ | |
2551 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x94), 0x2e }, /* equaliser */ | |
2552 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x96), 0x00 }, /* enable automatic EQ changing */ | |
2553 | ||
2554 | /* set ADI recommended settings for digitizer */ | |
2555 | /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */ | |
2556 | { ADV7604_REG(ADV7604_PAGE_AFE, 0x12), 0x7b }, /* ADC noise shaping filter controls */ | |
2557 | { ADV7604_REG(ADV7604_PAGE_AFE, 0x0c), 0x1f }, /* CP core gain controls */ | |
2558 | { ADV7604_REG(ADV7604_PAGE_CP, 0x3e), 0x04 }, /* CP core pre-gain control */ | |
2559 | { ADV7604_REG(ADV7604_PAGE_CP, 0xc3), 0x39 }, /* CP coast control. Graphics mode */ | |
2560 | { ADV7604_REG(ADV7604_PAGE_CP, 0x40), 0x5c }, /* CP core pre-gain control. Graphics mode */ | |
2561 | ||
2562 | { ADV7604_REG_SEQ_TERM, 0 }, | |
2563 | }; | |
2564 | ||
2565 | static const struct adv7604_reg_seq adv7604_recommended_settings_hdmi[] = { | |
2566 | /* set ADI recommended settings for HDMI: */ | |
2567 | /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */ | |
2568 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x0d), 0x84 }, /* HDMI filter optimization */ | |
2569 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x3d), 0x10 }, /* DDC bus active pull-up control */ | |
2570 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x3e), 0x39 }, /* TMDS PLL optimization */ | |
2571 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */ | |
2572 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x57), 0xb6 }, /* TMDS PLL optimization */ | |
2573 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x58), 0x03 }, /* TMDS PLL optimization */ | |
2574 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */ | |
2575 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */ | |
2576 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x93), 0x8b }, /* equaliser */ | |
2577 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x94), 0x2d }, /* equaliser */ | |
2578 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x96), 0x01 }, /* enable automatic EQ changing */ | |
2579 | ||
2580 | /* reset ADI recommended settings for digitizer */ | |
2581 | /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */ | |
2582 | { ADV7604_REG(ADV7604_PAGE_AFE, 0x12), 0xfb }, /* ADC noise shaping filter controls */ | |
2583 | { ADV7604_REG(ADV7604_PAGE_AFE, 0x0c), 0x0d }, /* CP core gain controls */ | |
2584 | ||
2585 | { ADV7604_REG_SEQ_TERM, 0 }, | |
2586 | }; | |
2587 | ||
2588 | static const struct adv7604_reg_seq adv7611_recommended_settings_hdmi[] = { | |
2589 | { ADV7604_REG(ADV7604_PAGE_CP, 0x6c), 0x00 }, | |
2590 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x6f), 0x0c }, | |
2591 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x87), 0x70 }, | |
2592 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x57), 0xda }, | |
2593 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x58), 0x01 }, | |
2594 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x03), 0x98 }, | |
2595 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x4c), 0x44 }, | |
2596 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8d), 0x04 }, | |
2597 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8e), 0x1e }, | |
2598 | ||
2599 | { ADV7604_REG_SEQ_TERM, 0 }, | |
2600 | }; | |
2601 | ||
2602 | static const struct adv7604_chip_info adv7604_chip_info[] = { | |
2603 | [ADV7604] = { | |
2604 | .type = ADV7604, | |
2605 | .has_afe = true, | |
2606 | .max_port = ADV7604_PAD_VGA_COMP, | |
2607 | .num_dv_ports = 4, | |
2608 | .edid_enable_reg = 0x77, | |
2609 | .edid_status_reg = 0x7d, | |
2610 | .lcf_reg = 0xb3, | |
2611 | .tdms_lock_mask = 0xe0, | |
2612 | .cable_det_mask = 0x1e, | |
2613 | .fmt_change_digital_mask = 0xc1, | |
2614 | .formats = adv7604_formats, | |
2615 | .nformats = ARRAY_SIZE(adv7604_formats), | |
2616 | .set_termination = adv7604_set_termination, | |
2617 | .setup_irqs = adv7604_setup_irqs, | |
2618 | .read_hdmi_pixelclock = adv7604_read_hdmi_pixelclock, | |
2619 | .read_cable_det = adv7604_read_cable_det, | |
2620 | .recommended_settings = { | |
2621 | [0] = adv7604_recommended_settings_afe, | |
2622 | [1] = adv7604_recommended_settings_hdmi, | |
2623 | }, | |
2624 | .num_recommended_settings = { | |
2625 | [0] = ARRAY_SIZE(adv7604_recommended_settings_afe), | |
2626 | [1] = ARRAY_SIZE(adv7604_recommended_settings_hdmi), | |
2627 | }, | |
2628 | .page_mask = BIT(ADV7604_PAGE_IO) | BIT(ADV7604_PAGE_AVLINK) | | |
2629 | BIT(ADV7604_PAGE_CEC) | BIT(ADV7604_PAGE_INFOFRAME) | | |
2630 | BIT(ADV7604_PAGE_ESDP) | BIT(ADV7604_PAGE_DPP) | | |
2631 | BIT(ADV7604_PAGE_AFE) | BIT(ADV7604_PAGE_REP) | | |
2632 | BIT(ADV7604_PAGE_EDID) | BIT(ADV7604_PAGE_HDMI) | | |
2633 | BIT(ADV7604_PAGE_TEST) | BIT(ADV7604_PAGE_CP) | | |
2634 | BIT(ADV7604_PAGE_VDP), | |
2635 | }, | |
2636 | [ADV7611] = { | |
2637 | .type = ADV7611, | |
2638 | .has_afe = false, | |
2639 | .max_port = ADV7604_PAD_HDMI_PORT_A, | |
2640 | .num_dv_ports = 1, | |
2641 | .edid_enable_reg = 0x74, | |
2642 | .edid_status_reg = 0x76, | |
2643 | .lcf_reg = 0xa3, | |
2644 | .tdms_lock_mask = 0x43, | |
2645 | .cable_det_mask = 0x01, | |
2646 | .fmt_change_digital_mask = 0x03, | |
2647 | .formats = adv7611_formats, | |
2648 | .nformats = ARRAY_SIZE(adv7611_formats), | |
2649 | .set_termination = adv7611_set_termination, | |
2650 | .setup_irqs = adv7611_setup_irqs, | |
2651 | .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock, | |
2652 | .read_cable_det = adv7611_read_cable_det, | |
2653 | .recommended_settings = { | |
2654 | [1] = adv7611_recommended_settings_hdmi, | |
2655 | }, | |
2656 | .num_recommended_settings = { | |
2657 | [1] = ARRAY_SIZE(adv7611_recommended_settings_hdmi), | |
2658 | }, | |
2659 | .page_mask = BIT(ADV7604_PAGE_IO) | BIT(ADV7604_PAGE_CEC) | | |
2660 | BIT(ADV7604_PAGE_INFOFRAME) | BIT(ADV7604_PAGE_AFE) | | |
2661 | BIT(ADV7604_PAGE_REP) | BIT(ADV7604_PAGE_EDID) | | |
2662 | BIT(ADV7604_PAGE_HDMI) | BIT(ADV7604_PAGE_CP), | |
2663 | }, | |
2664 | }; | |
2665 | ||
2666 | static struct i2c_device_id adv7604_i2c_id[] = { | |
2667 | { "adv7604", (kernel_ulong_t)&adv7604_chip_info[ADV7604] }, | |
2668 | { "adv7611", (kernel_ulong_t)&adv7604_chip_info[ADV7611] }, | |
2669 | { } | |
2670 | }; | |
2671 | MODULE_DEVICE_TABLE(i2c, adv7604_i2c_id); | |
2672 | ||
2673 | static struct of_device_id adv7604_of_id[] __maybe_unused = { | |
2674 | { .compatible = "adi,adv7611", .data = &adv7604_chip_info[ADV7611] }, | |
2675 | { } | |
2676 | }; | |
2677 | MODULE_DEVICE_TABLE(of, adv7604_of_id); | |
2678 | ||
2679 | static int adv7604_parse_dt(struct adv7604_state *state) | |
2680 | { | |
2681 | /* Disable the interrupt for now as no DT-based board uses it. */ | |
2682 | state->pdata.int1_config = ADV7604_INT1_CONFIG_DISABLED; | |
2683 | ||
2684 | /* Use the default I2C addresses. */ | |
2685 | state->pdata.i2c_addresses[ADV7604_PAGE_AVLINK] = 0x42; | |
2686 | state->pdata.i2c_addresses[ADV7604_PAGE_CEC] = 0x40; | |
2687 | state->pdata.i2c_addresses[ADV7604_PAGE_INFOFRAME] = 0x3e; | |
2688 | state->pdata.i2c_addresses[ADV7604_PAGE_ESDP] = 0x38; | |
2689 | state->pdata.i2c_addresses[ADV7604_PAGE_DPP] = 0x3c; | |
2690 | state->pdata.i2c_addresses[ADV7604_PAGE_AFE] = 0x26; | |
2691 | state->pdata.i2c_addresses[ADV7604_PAGE_REP] = 0x32; | |
2692 | state->pdata.i2c_addresses[ADV7604_PAGE_EDID] = 0x36; | |
2693 | state->pdata.i2c_addresses[ADV7604_PAGE_HDMI] = 0x34; | |
2694 | state->pdata.i2c_addresses[ADV7604_PAGE_TEST] = 0x30; | |
2695 | state->pdata.i2c_addresses[ADV7604_PAGE_CP] = 0x22; | |
2696 | state->pdata.i2c_addresses[ADV7604_PAGE_VDP] = 0x24; | |
2697 | ||
2698 | /* Hardcode the remaining platform data fields. */ | |
2699 | state->pdata.disable_pwrdnb = 0; | |
2700 | state->pdata.disable_cable_det_rst = 0; | |
2701 | state->pdata.default_input = -1; | |
2702 | state->pdata.blank_data = 1; | |
2703 | state->pdata.op_656_range = 1; | |
2704 | state->pdata.alt_data_sat = 1; | |
2705 | state->pdata.insert_av_codes = 1; | |
2706 | state->pdata.op_format_mode_sel = ADV7604_OP_FORMAT_MODE0; | |
2707 | state->pdata.bus_order = ADV7604_BUS_ORDER_RGB; | |
2708 | ||
2709 | return 0; | |
2710 | } | |
2711 | ||
2712 | static int adv7604_probe(struct i2c_client *client, | |
2713 | const struct i2c_device_id *id) | |
2714 | { | |
2715 | static const struct v4l2_dv_timings cea640x480 = | |
2716 | V4L2_DV_BT_CEA_640X480P59_94; | |
2717 | struct adv7604_state *state; | |
2718 | struct v4l2_ctrl_handler *hdl; | |
2719 | struct v4l2_subdev *sd; | |
2720 | unsigned int i; | |
2721 | u16 val; | |
2722 | int err; | |
2723 | ||
2724 | /* Check if the adapter supports the needed features */ | |
2725 | if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) | |
2726 | return -EIO; | |
2727 | v4l_dbg(1, debug, client, "detecting adv7604 client on address 0x%x\n", | |
2728 | client->addr << 1); | |
2729 | ||
2730 | state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL); | |
2731 | if (!state) { | |
2732 | v4l_err(client, "Could not allocate adv7604_state memory!\n"); | |
2733 | return -ENOMEM; | |
2734 | } | |
2735 | ||
2736 | state->i2c_clients[ADV7604_PAGE_IO] = client; | |
2737 | ||
2738 | /* initialize variables */ | |
2739 | state->restart_stdi_once = true; | |
2740 | state->selected_input = ~0; | |
2741 | ||
2742 | if (IS_ENABLED(CONFIG_OF) && client->dev.of_node) { | |
2743 | const struct of_device_id *oid; | |
2744 | ||
2745 | oid = of_match_node(adv7604_of_id, client->dev.of_node); | |
2746 | state->info = oid->data; | |
2747 | ||
2748 | err = adv7604_parse_dt(state); | |
2749 | if (err < 0) { | |
2750 | v4l_err(client, "DT parsing error\n"); | |
2751 | return err; | |
2752 | } | |
2753 | } else if (client->dev.platform_data) { | |
2754 | struct adv7604_platform_data *pdata = client->dev.platform_data; | |
2755 | ||
2756 | state->info = (const struct adv7604_chip_info *)id->driver_data; | |
2757 | state->pdata = *pdata; | |
2758 | } else { | |
2759 | v4l_err(client, "No platform data!\n"); | |
2760 | return -ENODEV; | |
2761 | } | |
2762 | ||
2763 | /* Request GPIOs. */ | |
2764 | for (i = 0; i < state->info->num_dv_ports; ++i) { | |
2765 | state->hpd_gpio[i] = | |
2766 | devm_gpiod_get_index(&client->dev, "hpd", i); | |
2767 | if (IS_ERR(state->hpd_gpio[i])) | |
2768 | continue; | |
2769 | ||
2770 | gpiod_set_value_cansleep(state->hpd_gpio[i], 0); | |
2771 | ||
2772 | v4l_info(client, "Handling HPD %u GPIO\n", i); | |
2773 | } | |
2774 | ||
2775 | state->timings = cea640x480; | |
2776 | state->format = adv7604_format_info(state, V4L2_MBUS_FMT_YUYV8_2X8); | |
2777 | ||
2778 | sd = &state->sd; | |
2779 | v4l2_i2c_subdev_init(sd, client, &adv7604_ops); | |
2780 | snprintf(sd->name, sizeof(sd->name), "%s %d-%04x", | |
2781 | id->name, i2c_adapter_id(client->adapter), | |
2782 | client->addr); | |
2783 | sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; | |
2784 | ||
2785 | /* | |
2786 | * Verify that the chip is present. On ADV7604 the RD_INFO register only | |
2787 | * identifies the revision, while on ADV7611 it identifies the model as | |
2788 | * well. Use the HDMI slave address on ADV7604 and RD_INFO on ADV7611. | |
2789 | */ | |
2790 | if (state->info->type == ADV7604) { | |
2791 | val = adv_smbus_read_byte_data_check(client, 0xfb, false); | |
2792 | if (val != 0x68) { | |
2793 | v4l2_info(sd, "not an adv7604 on address 0x%x\n", | |
2794 | client->addr << 1); | |
2795 | return -ENODEV; | |
2796 | } | |
2797 | } else { | |
2798 | val = (adv_smbus_read_byte_data_check(client, 0xea, false) << 8) | |
2799 | | (adv_smbus_read_byte_data_check(client, 0xeb, false) << 0); | |
2800 | if (val != 0x2051) { | |
2801 | v4l2_info(sd, "not an adv7611 on address 0x%x\n", | |
2802 | client->addr << 1); | |
2803 | return -ENODEV; | |
2804 | } | |
2805 | } | |
2806 | ||
2807 | /* control handlers */ | |
2808 | hdl = &state->hdl; | |
2809 | v4l2_ctrl_handler_init(hdl, adv7604_has_afe(state) ? 9 : 8); | |
2810 | ||
2811 | v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops, | |
2812 | V4L2_CID_BRIGHTNESS, -128, 127, 1, 0); | |
2813 | v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops, | |
2814 | V4L2_CID_CONTRAST, 0, 255, 1, 128); | |
2815 | v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops, | |
2816 | V4L2_CID_SATURATION, 0, 255, 1, 128); | |
2817 | v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops, | |
2818 | V4L2_CID_HUE, 0, 128, 1, 0); | |
2819 | ||
2820 | /* private controls */ | |
2821 | state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL, | |
2822 | V4L2_CID_DV_RX_POWER_PRESENT, 0, | |
2823 | (1 << state->info->num_dv_ports) - 1, 0, 0); | |
2824 | state->rgb_quantization_range_ctrl = | |
2825 | v4l2_ctrl_new_std_menu(hdl, &adv7604_ctrl_ops, | |
2826 | V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL, | |
2827 | 0, V4L2_DV_RGB_RANGE_AUTO); | |
2828 | ||
2829 | /* custom controls */ | |
2830 | if (adv7604_has_afe(state)) | |
2831 | state->analog_sampling_phase_ctrl = | |
2832 | v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL); | |
2833 | state->free_run_color_manual_ctrl = | |
2834 | v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color_manual, NULL); | |
2835 | state->free_run_color_ctrl = | |
2836 | v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color, NULL); | |
2837 | ||
2838 | sd->ctrl_handler = hdl; | |
2839 | if (hdl->error) { | |
2840 | err = hdl->error; | |
2841 | goto err_hdl; | |
2842 | } | |
2843 | state->detect_tx_5v_ctrl->is_private = true; | |
2844 | state->rgb_quantization_range_ctrl->is_private = true; | |
2845 | if (adv7604_has_afe(state)) | |
2846 | state->analog_sampling_phase_ctrl->is_private = true; | |
2847 | state->free_run_color_manual_ctrl->is_private = true; | |
2848 | state->free_run_color_ctrl->is_private = true; | |
2849 | ||
2850 | if (adv7604_s_detect_tx_5v_ctrl(sd)) { | |
2851 | err = -ENODEV; | |
2852 | goto err_hdl; | |
2853 | } | |
2854 | ||
2855 | for (i = 1; i < ADV7604_PAGE_MAX; ++i) { | |
2856 | if (!(BIT(i) & state->info->page_mask)) | |
2857 | continue; | |
2858 | ||
2859 | state->i2c_clients[i] = | |
2860 | adv7604_dummy_client(sd, state->pdata.i2c_addresses[i], | |
2861 | 0xf2 + i); | |
2862 | if (state->i2c_clients[i] == NULL) { | |
2863 | err = -ENOMEM; | |
2864 | v4l2_err(sd, "failed to create i2c client %u\n", i); | |
2865 | goto err_i2c; | |
2866 | } | |
2867 | } | |
2868 | ||
2869 | /* work queues */ | |
2870 | state->work_queues = create_singlethread_workqueue(client->name); | |
2871 | if (!state->work_queues) { | |
2872 | v4l2_err(sd, "Could not create work queue\n"); | |
2873 | err = -ENOMEM; | |
2874 | goto err_i2c; | |
2875 | } | |
2876 | ||
2877 | INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug, | |
2878 | adv7604_delayed_work_enable_hotplug); | |
2879 | ||
2880 | state->source_pad = state->info->num_dv_ports | |
2881 | + (state->info->has_afe ? 2 : 0); | |
2882 | for (i = 0; i < state->source_pad; ++i) | |
2883 | state->pads[i].flags = MEDIA_PAD_FL_SINK; | |
2884 | state->pads[state->source_pad].flags = MEDIA_PAD_FL_SOURCE; | |
2885 | ||
2886 | err = media_entity_init(&sd->entity, state->source_pad + 1, | |
2887 | state->pads, 0); | |
2888 | if (err) | |
2889 | goto err_work_queues; | |
2890 | ||
2891 | err = adv7604_core_init(sd); | |
2892 | if (err) | |
2893 | goto err_entity; | |
2894 | v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name, | |
2895 | client->addr << 1, client->adapter->name); | |
2896 | ||
2897 | err = v4l2_async_register_subdev(sd); | |
2898 | if (err) | |
2899 | goto err_entity; | |
2900 | ||
2901 | return 0; | |
2902 | ||
2903 | err_entity: | |
2904 | media_entity_cleanup(&sd->entity); | |
2905 | err_work_queues: | |
2906 | cancel_delayed_work(&state->delayed_work_enable_hotplug); | |
2907 | destroy_workqueue(state->work_queues); | |
2908 | err_i2c: | |
2909 | adv7604_unregister_clients(state); | |
2910 | err_hdl: | |
2911 | v4l2_ctrl_handler_free(hdl); | |
2912 | return err; | |
2913 | } | |
2914 | ||
2915 | /* ----------------------------------------------------------------------- */ | |
2916 | ||
2917 | static int adv7604_remove(struct i2c_client *client) | |
2918 | { | |
2919 | struct v4l2_subdev *sd = i2c_get_clientdata(client); | |
2920 | struct adv7604_state *state = to_state(sd); | |
2921 | ||
2922 | cancel_delayed_work(&state->delayed_work_enable_hotplug); | |
2923 | destroy_workqueue(state->work_queues); | |
2924 | v4l2_async_unregister_subdev(sd); | |
2925 | v4l2_device_unregister_subdev(sd); | |
2926 | media_entity_cleanup(&sd->entity); | |
2927 | adv7604_unregister_clients(to_state(sd)); | |
2928 | v4l2_ctrl_handler_free(sd->ctrl_handler); | |
2929 | return 0; | |
2930 | } | |
2931 | ||
2932 | /* ----------------------------------------------------------------------- */ | |
2933 | ||
2934 | static struct i2c_driver adv7604_driver = { | |
2935 | .driver = { | |
2936 | .owner = THIS_MODULE, | |
2937 | .name = "adv7604", | |
2938 | .of_match_table = of_match_ptr(adv7604_of_id), | |
2939 | }, | |
2940 | .probe = adv7604_probe, | |
2941 | .remove = adv7604_remove, | |
2942 | .id_table = adv7604_i2c_id, | |
2943 | }; | |
2944 | ||
2945 | module_i2c_driver(adv7604_driver); |