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[mirror_ubuntu-hirsute-kernel.git] / drivers / mmc / host / omap_hsmmc.c
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1/*
2 * drivers/mmc/host/omap_hsmmc.c
3 *
4 * Driver for OMAP2430/3430 MMC controller.
5 *
6 * Copyright (C) 2007 Texas Instruments.
7 *
8 * Authors:
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
12 *
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
16 */
17
18#include <linux/module.h>
19#include <linux/init.h>
20#include <linux/kernel.h>
21#include <linux/debugfs.h>
22#include <linux/dmaengine.h>
23#include <linux/seq_file.h>
24#include <linux/sizes.h>
25#include <linux/interrupt.h>
26#include <linux/delay.h>
27#include <linux/dma-mapping.h>
28#include <linux/platform_device.h>
29#include <linux/timer.h>
30#include <linux/clk.h>
31#include <linux/of.h>
32#include <linux/of_irq.h>
33#include <linux/of_device.h>
34#include <linux/mmc/host.h>
35#include <linux/mmc/core.h>
36#include <linux/mmc/mmc.h>
37#include <linux/mmc/slot-gpio.h>
38#include <linux/io.h>
39#include <linux/irq.h>
40#include <linux/regulator/consumer.h>
41#include <linux/pinctrl/consumer.h>
42#include <linux/pm_runtime.h>
43#include <linux/pm_wakeirq.h>
44#include <linux/platform_data/hsmmc-omap.h>
45
46/* OMAP HSMMC Host Controller Registers */
47#define OMAP_HSMMC_SYSSTATUS 0x0014
48#define OMAP_HSMMC_CON 0x002C
49#define OMAP_HSMMC_SDMASA 0x0100
50#define OMAP_HSMMC_BLK 0x0104
51#define OMAP_HSMMC_ARG 0x0108
52#define OMAP_HSMMC_CMD 0x010C
53#define OMAP_HSMMC_RSP10 0x0110
54#define OMAP_HSMMC_RSP32 0x0114
55#define OMAP_HSMMC_RSP54 0x0118
56#define OMAP_HSMMC_RSP76 0x011C
57#define OMAP_HSMMC_DATA 0x0120
58#define OMAP_HSMMC_PSTATE 0x0124
59#define OMAP_HSMMC_HCTL 0x0128
60#define OMAP_HSMMC_SYSCTL 0x012C
61#define OMAP_HSMMC_STAT 0x0130
62#define OMAP_HSMMC_IE 0x0134
63#define OMAP_HSMMC_ISE 0x0138
64#define OMAP_HSMMC_AC12 0x013C
65#define OMAP_HSMMC_CAPA 0x0140
66
67#define VS18 (1 << 26)
68#define VS30 (1 << 25)
69#define HSS (1 << 21)
70#define SDVS18 (0x5 << 9)
71#define SDVS30 (0x6 << 9)
72#define SDVS33 (0x7 << 9)
73#define SDVS_MASK 0x00000E00
74#define SDVSCLR 0xFFFFF1FF
75#define SDVSDET 0x00000400
76#define AUTOIDLE 0x1
77#define SDBP (1 << 8)
78#define DTO 0xe
79#define ICE 0x1
80#define ICS 0x2
81#define CEN (1 << 2)
82#define CLKD_MAX 0x3FF /* max clock divisor: 1023 */
83#define CLKD_MASK 0x0000FFC0
84#define CLKD_SHIFT 6
85#define DTO_MASK 0x000F0000
86#define DTO_SHIFT 16
87#define INIT_STREAM (1 << 1)
88#define ACEN_ACMD23 (2 << 2)
89#define DP_SELECT (1 << 21)
90#define DDIR (1 << 4)
91#define DMAE 0x1
92#define MSBS (1 << 5)
93#define BCE (1 << 1)
94#define FOUR_BIT (1 << 1)
95#define HSPE (1 << 2)
96#define IWE (1 << 24)
97#define DDR (1 << 19)
98#define CLKEXTFREE (1 << 16)
99#define CTPL (1 << 11)
100#define DW8 (1 << 5)
101#define OD 0x1
102#define STAT_CLEAR 0xFFFFFFFF
103#define INIT_STREAM_CMD 0x00000000
104#define DUAL_VOLT_OCR_BIT 7
105#define SRC (1 << 25)
106#define SRD (1 << 26)
107#define SOFTRESET (1 << 1)
108
109/* PSTATE */
110#define DLEV_DAT(x) (1 << (20 + (x)))
111
112/* Interrupt masks for IE and ISE register */
113#define CC_EN (1 << 0)
114#define TC_EN (1 << 1)
115#define BWR_EN (1 << 4)
116#define BRR_EN (1 << 5)
117#define CIRQ_EN (1 << 8)
118#define ERR_EN (1 << 15)
119#define CTO_EN (1 << 16)
120#define CCRC_EN (1 << 17)
121#define CEB_EN (1 << 18)
122#define CIE_EN (1 << 19)
123#define DTO_EN (1 << 20)
124#define DCRC_EN (1 << 21)
125#define DEB_EN (1 << 22)
126#define ACE_EN (1 << 24)
127#define CERR_EN (1 << 28)
128#define BADA_EN (1 << 29)
129
130#define INT_EN_MASK (BADA_EN | CERR_EN | ACE_EN | DEB_EN | DCRC_EN |\
131 DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \
132 BRR_EN | BWR_EN | TC_EN | CC_EN)
133
134#define CNI (1 << 7)
135#define ACIE (1 << 4)
136#define ACEB (1 << 3)
137#define ACCE (1 << 2)
138#define ACTO (1 << 1)
139#define ACNE (1 << 0)
140
141#define MMC_AUTOSUSPEND_DELAY 100
142#define MMC_TIMEOUT_MS 20 /* 20 mSec */
143#define MMC_TIMEOUT_US 20000 /* 20000 micro Sec */
144#define OMAP_MMC_MIN_CLOCK 400000
145#define OMAP_MMC_MAX_CLOCK 52000000
146#define DRIVER_NAME "omap_hsmmc"
147
148/*
149 * One controller can have multiple slots, like on some omap boards using
150 * omap.c controller driver. Luckily this is not currently done on any known
151 * omap_hsmmc.c device.
152 */
153#define mmc_pdata(host) host->pdata
154
155/*
156 * MMC Host controller read/write API's
157 */
158#define OMAP_HSMMC_READ(base, reg) \
159 __raw_readl((base) + OMAP_HSMMC_##reg)
160
161#define OMAP_HSMMC_WRITE(base, reg, val) \
162 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
163
164struct omap_hsmmc_next {
165 unsigned int dma_len;
166 s32 cookie;
167};
168
169struct omap_hsmmc_host {
170 struct device *dev;
171 struct mmc_host *mmc;
172 struct mmc_request *mrq;
173 struct mmc_command *cmd;
174 struct mmc_data *data;
175 struct clk *fclk;
176 struct clk *dbclk;
177 struct regulator *pbias;
178 bool pbias_enabled;
179 void __iomem *base;
180 int vqmmc_enabled;
181 resource_size_t mapbase;
182 spinlock_t irq_lock; /* Prevent races with irq handler */
183 unsigned int dma_len;
184 unsigned int dma_sg_idx;
185 unsigned char bus_mode;
186 unsigned char power_mode;
187 int suspended;
188 u32 con;
189 u32 hctl;
190 u32 sysctl;
191 u32 capa;
192 int irq;
193 int wake_irq;
194 int use_dma, dma_ch;
195 struct dma_chan *tx_chan;
196 struct dma_chan *rx_chan;
197 int response_busy;
198 int context_loss;
199 int reqs_blocked;
200 int req_in_progress;
201 unsigned long clk_rate;
202 unsigned int flags;
203#define AUTO_CMD23 (1 << 0) /* Auto CMD23 support */
204#define HSMMC_SDIO_IRQ_ENABLED (1 << 1) /* SDIO irq enabled */
205 struct omap_hsmmc_next next_data;
206 struct omap_hsmmc_platform_data *pdata;
207};
208
209struct omap_mmc_of_data {
210 u32 reg_offset;
211 u8 controller_flags;
212};
213
214static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host);
215
216static int omap_hsmmc_enable_supply(struct mmc_host *mmc)
217{
218 int ret;
219 struct omap_hsmmc_host *host = mmc_priv(mmc);
220 struct mmc_ios *ios = &mmc->ios;
221
222 if (!IS_ERR(mmc->supply.vmmc)) {
223 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
224 if (ret)
225 return ret;
226 }
227
228 /* Enable interface voltage rail, if needed */
229 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
230 ret = regulator_enable(mmc->supply.vqmmc);
231 if (ret) {
232 dev_err(mmc_dev(mmc), "vmmc_aux reg enable failed\n");
233 goto err_vqmmc;
234 }
235 host->vqmmc_enabled = 1;
236 }
237
238 return 0;
239
240err_vqmmc:
241 if (!IS_ERR(mmc->supply.vmmc))
242 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
243
244 return ret;
245}
246
247static int omap_hsmmc_disable_supply(struct mmc_host *mmc)
248{
249 int ret;
250 int status;
251 struct omap_hsmmc_host *host = mmc_priv(mmc);
252
253 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
254 ret = regulator_disable(mmc->supply.vqmmc);
255 if (ret) {
256 dev_err(mmc_dev(mmc), "vmmc_aux reg disable failed\n");
257 return ret;
258 }
259 host->vqmmc_enabled = 0;
260 }
261
262 if (!IS_ERR(mmc->supply.vmmc)) {
263 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
264 if (ret)
265 goto err_set_ocr;
266 }
267
268 return 0;
269
270err_set_ocr:
271 if (!IS_ERR(mmc->supply.vqmmc)) {
272 status = regulator_enable(mmc->supply.vqmmc);
273 if (status)
274 dev_err(mmc_dev(mmc), "vmmc_aux re-enable failed\n");
275 }
276
277 return ret;
278}
279
280static int omap_hsmmc_set_pbias(struct omap_hsmmc_host *host, bool power_on)
281{
282 int ret;
283
284 if (IS_ERR(host->pbias))
285 return 0;
286
287 if (power_on) {
288 if (host->pbias_enabled == 0) {
289 ret = regulator_enable(host->pbias);
290 if (ret) {
291 dev_err(host->dev, "pbias reg enable fail\n");
292 return ret;
293 }
294 host->pbias_enabled = 1;
295 }
296 } else {
297 if (host->pbias_enabled == 1) {
298 ret = regulator_disable(host->pbias);
299 if (ret) {
300 dev_err(host->dev, "pbias reg disable fail\n");
301 return ret;
302 }
303 host->pbias_enabled = 0;
304 }
305 }
306
307 return 0;
308}
309
310static int omap_hsmmc_set_power(struct omap_hsmmc_host *host, int power_on)
311{
312 struct mmc_host *mmc = host->mmc;
313 int ret = 0;
314
315 /*
316 * If we don't see a Vcc regulator, assume it's a fixed
317 * voltage always-on regulator.
318 */
319 if (IS_ERR(mmc->supply.vmmc))
320 return 0;
321
322 ret = omap_hsmmc_set_pbias(host, false);
323 if (ret)
324 return ret;
325
326 /*
327 * Assume Vcc regulator is used only to power the card ... OMAP
328 * VDDS is used to power the pins, optionally with a transceiver to
329 * support cards using voltages other than VDDS (1.8V nominal). When a
330 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
331 *
332 * In some cases this regulator won't support enable/disable;
333 * e.g. it's a fixed rail for a WLAN chip.
334 *
335 * In other cases vcc_aux switches interface power. Example, for
336 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
337 * chips/cards need an interface voltage rail too.
338 */
339 if (power_on) {
340 ret = omap_hsmmc_enable_supply(mmc);
341 if (ret)
342 return ret;
343
344 ret = omap_hsmmc_set_pbias(host, true);
345 if (ret)
346 goto err_set_voltage;
347 } else {
348 ret = omap_hsmmc_disable_supply(mmc);
349 if (ret)
350 return ret;
351 }
352
353 return 0;
354
355err_set_voltage:
356 omap_hsmmc_disable_supply(mmc);
357
358 return ret;
359}
360
361static int omap_hsmmc_disable_boot_regulator(struct regulator *reg)
362{
363 int ret;
364
365 if (IS_ERR(reg))
366 return 0;
367
368 if (regulator_is_enabled(reg)) {
369 ret = regulator_enable(reg);
370 if (ret)
371 return ret;
372
373 ret = regulator_disable(reg);
374 if (ret)
375 return ret;
376 }
377
378 return 0;
379}
380
381static int omap_hsmmc_disable_boot_regulators(struct omap_hsmmc_host *host)
382{
383 struct mmc_host *mmc = host->mmc;
384 int ret;
385
386 /*
387 * disable regulators enabled during boot and get the usecount
388 * right so that regulators can be enabled/disabled by checking
389 * the return value of regulator_is_enabled
390 */
391 ret = omap_hsmmc_disable_boot_regulator(mmc->supply.vmmc);
392 if (ret) {
393 dev_err(host->dev, "fail to disable boot enabled vmmc reg\n");
394 return ret;
395 }
396
397 ret = omap_hsmmc_disable_boot_regulator(mmc->supply.vqmmc);
398 if (ret) {
399 dev_err(host->dev,
400 "fail to disable boot enabled vmmc_aux reg\n");
401 return ret;
402 }
403
404 ret = omap_hsmmc_disable_boot_regulator(host->pbias);
405 if (ret) {
406 dev_err(host->dev,
407 "failed to disable boot enabled pbias reg\n");
408 return ret;
409 }
410
411 return 0;
412}
413
414static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
415{
416 int ret;
417 struct mmc_host *mmc = host->mmc;
418
419
420 ret = mmc_regulator_get_supply(mmc);
421 if (ret)
422 return ret;
423
424 /* Allow an aux regulator */
425 if (IS_ERR(mmc->supply.vqmmc)) {
426 mmc->supply.vqmmc = devm_regulator_get_optional(host->dev,
427 "vmmc_aux");
428 if (IS_ERR(mmc->supply.vqmmc)) {
429 ret = PTR_ERR(mmc->supply.vqmmc);
430 if ((ret != -ENODEV) && host->dev->of_node)
431 return ret;
432 dev_dbg(host->dev, "unable to get vmmc_aux regulator %ld\n",
433 PTR_ERR(mmc->supply.vqmmc));
434 }
435 }
436
437 host->pbias = devm_regulator_get_optional(host->dev, "pbias");
438 if (IS_ERR(host->pbias)) {
439 ret = PTR_ERR(host->pbias);
440 if ((ret != -ENODEV) && host->dev->of_node) {
441 dev_err(host->dev,
442 "SD card detect fail? enable CONFIG_REGULATOR_PBIAS\n");
443 return ret;
444 }
445 dev_dbg(host->dev, "unable to get pbias regulator %ld\n",
446 PTR_ERR(host->pbias));
447 }
448
449 /* For eMMC do not power off when not in sleep state */
450 if (mmc_pdata(host)->no_regulator_off_init)
451 return 0;
452
453 ret = omap_hsmmc_disable_boot_regulators(host);
454 if (ret)
455 return ret;
456
457 return 0;
458}
459
460/*
461 * Start clock to the card
462 */
463static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
464{
465 OMAP_HSMMC_WRITE(host->base, SYSCTL,
466 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
467}
468
469/*
470 * Stop clock to the card
471 */
472static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
473{
474 OMAP_HSMMC_WRITE(host->base, SYSCTL,
475 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
476 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
477 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n");
478}
479
480static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
481 struct mmc_command *cmd)
482{
483 u32 irq_mask = INT_EN_MASK;
484 unsigned long flags;
485
486 if (host->use_dma)
487 irq_mask &= ~(BRR_EN | BWR_EN);
488
489 /* Disable timeout for erases */
490 if (cmd->opcode == MMC_ERASE)
491 irq_mask &= ~DTO_EN;
492
493 spin_lock_irqsave(&host->irq_lock, flags);
494 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
495 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
496
497 /* latch pending CIRQ, but don't signal MMC core */
498 if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
499 irq_mask |= CIRQ_EN;
500 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
501 spin_unlock_irqrestore(&host->irq_lock, flags);
502}
503
504static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
505{
506 u32 irq_mask = 0;
507 unsigned long flags;
508
509 spin_lock_irqsave(&host->irq_lock, flags);
510 /* no transfer running but need to keep cirq if enabled */
511 if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
512 irq_mask |= CIRQ_EN;
513 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
514 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
515 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
516 spin_unlock_irqrestore(&host->irq_lock, flags);
517}
518
519/* Calculate divisor for the given clock frequency */
520static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
521{
522 u16 dsor = 0;
523
524 if (ios->clock) {
525 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
526 if (dsor > CLKD_MAX)
527 dsor = CLKD_MAX;
528 }
529
530 return dsor;
531}
532
533static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
534{
535 struct mmc_ios *ios = &host->mmc->ios;
536 unsigned long regval;
537 unsigned long timeout;
538 unsigned long clkdiv;
539
540 dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
541
542 omap_hsmmc_stop_clock(host);
543
544 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
545 regval = regval & ~(CLKD_MASK | DTO_MASK);
546 clkdiv = calc_divisor(host, ios);
547 regval = regval | (clkdiv << 6) | (DTO << 16);
548 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
549 OMAP_HSMMC_WRITE(host->base, SYSCTL,
550 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
551
552 /* Wait till the ICS bit is set */
553 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
554 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
555 && time_before(jiffies, timeout))
556 cpu_relax();
557
558 /*
559 * Enable High-Speed Support
560 * Pre-Requisites
561 * - Controller should support High-Speed-Enable Bit
562 * - Controller should not be using DDR Mode
563 * - Controller should advertise that it supports High Speed
564 * in capabilities register
565 * - MMC/SD clock coming out of controller > 25MHz
566 */
567 if ((mmc_pdata(host)->features & HSMMC_HAS_HSPE_SUPPORT) &&
568 (ios->timing != MMC_TIMING_MMC_DDR52) &&
569 (ios->timing != MMC_TIMING_UHS_DDR50) &&
570 ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) {
571 regval = OMAP_HSMMC_READ(host->base, HCTL);
572 if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000)
573 regval |= HSPE;
574 else
575 regval &= ~HSPE;
576
577 OMAP_HSMMC_WRITE(host->base, HCTL, regval);
578 }
579
580 omap_hsmmc_start_clock(host);
581}
582
583static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
584{
585 struct mmc_ios *ios = &host->mmc->ios;
586 u32 con;
587
588 con = OMAP_HSMMC_READ(host->base, CON);
589 if (ios->timing == MMC_TIMING_MMC_DDR52 ||
590 ios->timing == MMC_TIMING_UHS_DDR50)
591 con |= DDR; /* configure in DDR mode */
592 else
593 con &= ~DDR;
594 switch (ios->bus_width) {
595 case MMC_BUS_WIDTH_8:
596 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
597 break;
598 case MMC_BUS_WIDTH_4:
599 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
600 OMAP_HSMMC_WRITE(host->base, HCTL,
601 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
602 break;
603 case MMC_BUS_WIDTH_1:
604 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
605 OMAP_HSMMC_WRITE(host->base, HCTL,
606 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
607 break;
608 }
609}
610
611static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
612{
613 struct mmc_ios *ios = &host->mmc->ios;
614 u32 con;
615
616 con = OMAP_HSMMC_READ(host->base, CON);
617 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
618 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
619 else
620 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
621}
622
623#ifdef CONFIG_PM
624
625/*
626 * Restore the MMC host context, if it was lost as result of a
627 * power state change.
628 */
629static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
630{
631 struct mmc_ios *ios = &host->mmc->ios;
632 u32 hctl, capa;
633 unsigned long timeout;
634
635 if (host->con == OMAP_HSMMC_READ(host->base, CON) &&
636 host->hctl == OMAP_HSMMC_READ(host->base, HCTL) &&
637 host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) &&
638 host->capa == OMAP_HSMMC_READ(host->base, CAPA))
639 return 0;
640
641 host->context_loss++;
642
643 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
644 if (host->power_mode != MMC_POWER_OFF &&
645 (1 << ios->vdd) <= MMC_VDD_23_24)
646 hctl = SDVS18;
647 else
648 hctl = SDVS30;
649 capa = VS30 | VS18;
650 } else {
651 hctl = SDVS18;
652 capa = VS18;
653 }
654
655 if (host->mmc->caps & MMC_CAP_SDIO_IRQ)
656 hctl |= IWE;
657
658 OMAP_HSMMC_WRITE(host->base, HCTL,
659 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
660
661 OMAP_HSMMC_WRITE(host->base, CAPA,
662 OMAP_HSMMC_READ(host->base, CAPA) | capa);
663
664 OMAP_HSMMC_WRITE(host->base, HCTL,
665 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
666
667 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
668 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
669 && time_before(jiffies, timeout))
670 ;
671
672 OMAP_HSMMC_WRITE(host->base, ISE, 0);
673 OMAP_HSMMC_WRITE(host->base, IE, 0);
674 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
675
676 /* Do not initialize card-specific things if the power is off */
677 if (host->power_mode == MMC_POWER_OFF)
678 goto out;
679
680 omap_hsmmc_set_bus_width(host);
681
682 omap_hsmmc_set_clock(host);
683
684 omap_hsmmc_set_bus_mode(host);
685
686out:
687 dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n",
688 host->context_loss);
689 return 0;
690}
691
692/*
693 * Save the MMC host context (store the number of power state changes so far).
694 */
695static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
696{
697 host->con = OMAP_HSMMC_READ(host->base, CON);
698 host->hctl = OMAP_HSMMC_READ(host->base, HCTL);
699 host->sysctl = OMAP_HSMMC_READ(host->base, SYSCTL);
700 host->capa = OMAP_HSMMC_READ(host->base, CAPA);
701}
702
703#else
704
705static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
706{
707 return 0;
708}
709
710static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
711{
712}
713
714#endif
715
716/*
717 * Send init stream sequence to card
718 * before sending IDLE command
719 */
720static void send_init_stream(struct omap_hsmmc_host *host)
721{
722 int reg = 0;
723 unsigned long timeout;
724
725 disable_irq(host->irq);
726
727 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
728 OMAP_HSMMC_WRITE(host->base, CON,
729 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
730 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
731
732 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
733 while ((reg != CC_EN) && time_before(jiffies, timeout))
734 reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN;
735
736 OMAP_HSMMC_WRITE(host->base, CON,
737 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
738
739 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
740 OMAP_HSMMC_READ(host->base, STAT);
741
742 enable_irq(host->irq);
743}
744
745static ssize_t
746omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
747 char *buf)
748{
749 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
750 struct omap_hsmmc_host *host = mmc_priv(mmc);
751
752 return sprintf(buf, "%s\n", mmc_pdata(host)->name);
753}
754
755static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
756
757/*
758 * Configure the response type and send the cmd.
759 */
760static void
761omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
762 struct mmc_data *data)
763{
764 int cmdreg = 0, resptype = 0, cmdtype = 0;
765
766 dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
767 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
768 host->cmd = cmd;
769
770 omap_hsmmc_enable_irq(host, cmd);
771
772 host->response_busy = 0;
773 if (cmd->flags & MMC_RSP_PRESENT) {
774 if (cmd->flags & MMC_RSP_136)
775 resptype = 1;
776 else if (cmd->flags & MMC_RSP_BUSY) {
777 resptype = 3;
778 host->response_busy = 1;
779 } else
780 resptype = 2;
781 }
782
783 /*
784 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
785 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
786 * a val of 0x3, rest 0x0.
787 */
788 if (cmd == host->mrq->stop)
789 cmdtype = 0x3;
790
791 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
792
793 if ((host->flags & AUTO_CMD23) && mmc_op_multi(cmd->opcode) &&
794 host->mrq->sbc) {
795 cmdreg |= ACEN_ACMD23;
796 OMAP_HSMMC_WRITE(host->base, SDMASA, host->mrq->sbc->arg);
797 }
798 if (data) {
799 cmdreg |= DP_SELECT | MSBS | BCE;
800 if (data->flags & MMC_DATA_READ)
801 cmdreg |= DDIR;
802 else
803 cmdreg &= ~(DDIR);
804 }
805
806 if (host->use_dma)
807 cmdreg |= DMAE;
808
809 host->req_in_progress = 1;
810
811 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
812 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
813}
814
815static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host,
816 struct mmc_data *data)
817{
818 return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
819}
820
821static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
822{
823 int dma_ch;
824 unsigned long flags;
825
826 spin_lock_irqsave(&host->irq_lock, flags);
827 host->req_in_progress = 0;
828 dma_ch = host->dma_ch;
829 spin_unlock_irqrestore(&host->irq_lock, flags);
830
831 omap_hsmmc_disable_irq(host);
832 /* Do not complete the request if DMA is still in progress */
833 if (mrq->data && host->use_dma && dma_ch != -1)
834 return;
835 host->mrq = NULL;
836 mmc_request_done(host->mmc, mrq);
837}
838
839/*
840 * Notify the transfer complete to MMC core
841 */
842static void
843omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
844{
845 if (!data) {
846 struct mmc_request *mrq = host->mrq;
847
848 /* TC before CC from CMD6 - don't know why, but it happens */
849 if (host->cmd && host->cmd->opcode == 6 &&
850 host->response_busy) {
851 host->response_busy = 0;
852 return;
853 }
854
855 omap_hsmmc_request_done(host, mrq);
856 return;
857 }
858
859 host->data = NULL;
860
861 if (!data->error)
862 data->bytes_xfered += data->blocks * (data->blksz);
863 else
864 data->bytes_xfered = 0;
865
866 if (data->stop && (data->error || !host->mrq->sbc))
867 omap_hsmmc_start_command(host, data->stop, NULL);
868 else
869 omap_hsmmc_request_done(host, data->mrq);
870}
871
872/*
873 * Notify the core about command completion
874 */
875static void
876omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
877{
878 if (host->mrq->sbc && (host->cmd == host->mrq->sbc) &&
879 !host->mrq->sbc->error && !(host->flags & AUTO_CMD23)) {
880 host->cmd = NULL;
881 omap_hsmmc_start_dma_transfer(host);
882 omap_hsmmc_start_command(host, host->mrq->cmd,
883 host->mrq->data);
884 return;
885 }
886
887 host->cmd = NULL;
888
889 if (cmd->flags & MMC_RSP_PRESENT) {
890 if (cmd->flags & MMC_RSP_136) {
891 /* response type 2 */
892 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
893 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
894 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
895 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
896 } else {
897 /* response types 1, 1b, 3, 4, 5, 6 */
898 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
899 }
900 }
901 if ((host->data == NULL && !host->response_busy) || cmd->error)
902 omap_hsmmc_request_done(host, host->mrq);
903}
904
905/*
906 * DMA clean up for command errors
907 */
908static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
909{
910 int dma_ch;
911 unsigned long flags;
912
913 host->data->error = errno;
914
915 spin_lock_irqsave(&host->irq_lock, flags);
916 dma_ch = host->dma_ch;
917 host->dma_ch = -1;
918 spin_unlock_irqrestore(&host->irq_lock, flags);
919
920 if (host->use_dma && dma_ch != -1) {
921 struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data);
922
923 dmaengine_terminate_all(chan);
924 dma_unmap_sg(chan->device->dev,
925 host->data->sg, host->data->sg_len,
926 mmc_get_dma_dir(host->data));
927
928 host->data->host_cookie = 0;
929 }
930 host->data = NULL;
931}
932
933/*
934 * Readable error output
935 */
936#ifdef CONFIG_MMC_DEBUG
937static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
938{
939 /* --- means reserved bit without definition at documentation */
940 static const char *omap_hsmmc_status_bits[] = {
941 "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
942 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
943 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
944 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
945 };
946 char res[256];
947 char *buf = res;
948 int len, i;
949
950 len = sprintf(buf, "MMC IRQ 0x%x :", status);
951 buf += len;
952
953 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
954 if (status & (1 << i)) {
955 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
956 buf += len;
957 }
958
959 dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
960}
961#else
962static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
963 u32 status)
964{
965}
966#endif /* CONFIG_MMC_DEBUG */
967
968/*
969 * MMC controller internal state machines reset
970 *
971 * Used to reset command or data internal state machines, using respectively
972 * SRC or SRD bit of SYSCTL register
973 * Can be called from interrupt context
974 */
975static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
976 unsigned long bit)
977{
978 unsigned long i = 0;
979 unsigned long limit = MMC_TIMEOUT_US;
980
981 OMAP_HSMMC_WRITE(host->base, SYSCTL,
982 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
983
984 /*
985 * OMAP4 ES2 and greater has an updated reset logic.
986 * Monitor a 0->1 transition first
987 */
988 if (mmc_pdata(host)->features & HSMMC_HAS_UPDATED_RESET) {
989 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
990 && (i++ < limit))
991 udelay(1);
992 }
993 i = 0;
994
995 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
996 (i++ < limit))
997 udelay(1);
998
999 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
1000 dev_err(mmc_dev(host->mmc),
1001 "Timeout waiting on controller reset in %s\n",
1002 __func__);
1003}
1004
1005static void hsmmc_command_incomplete(struct omap_hsmmc_host *host,
1006 int err, int end_cmd)
1007{
1008 if (end_cmd) {
1009 omap_hsmmc_reset_controller_fsm(host, SRC);
1010 if (host->cmd)
1011 host->cmd->error = err;
1012 }
1013
1014 if (host->data) {
1015 omap_hsmmc_reset_controller_fsm(host, SRD);
1016 omap_hsmmc_dma_cleanup(host, err);
1017 } else if (host->mrq && host->mrq->cmd)
1018 host->mrq->cmd->error = err;
1019}
1020
1021static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
1022{
1023 struct mmc_data *data;
1024 int end_cmd = 0, end_trans = 0;
1025 int error = 0;
1026
1027 data = host->data;
1028 dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1029
1030 if (status & ERR_EN) {
1031 omap_hsmmc_dbg_report_irq(host, status);
1032
1033 if (status & (CTO_EN | CCRC_EN | CEB_EN))
1034 end_cmd = 1;
1035 if (host->data || host->response_busy) {
1036 end_trans = !end_cmd;
1037 host->response_busy = 0;
1038 }
1039 if (status & (CTO_EN | DTO_EN))
1040 hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd);
1041 else if (status & (CCRC_EN | DCRC_EN | DEB_EN | CEB_EN |
1042 BADA_EN))
1043 hsmmc_command_incomplete(host, -EILSEQ, end_cmd);
1044
1045 if (status & ACE_EN) {
1046 u32 ac12;
1047 ac12 = OMAP_HSMMC_READ(host->base, AC12);
1048 if (!(ac12 & ACNE) && host->mrq->sbc) {
1049 end_cmd = 1;
1050 if (ac12 & ACTO)
1051 error = -ETIMEDOUT;
1052 else if (ac12 & (ACCE | ACEB | ACIE))
1053 error = -EILSEQ;
1054 host->mrq->sbc->error = error;
1055 hsmmc_command_incomplete(host, error, end_cmd);
1056 }
1057 dev_dbg(mmc_dev(host->mmc), "AC12 err: 0x%x\n", ac12);
1058 }
1059 }
1060
1061 OMAP_HSMMC_WRITE(host->base, STAT, status);
1062 if (end_cmd || ((status & CC_EN) && host->cmd))
1063 omap_hsmmc_cmd_done(host, host->cmd);
1064 if ((end_trans || (status & TC_EN)) && host->mrq)
1065 omap_hsmmc_xfer_done(host, data);
1066}
1067
1068/*
1069 * MMC controller IRQ handler
1070 */
1071static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1072{
1073 struct omap_hsmmc_host *host = dev_id;
1074 int status;
1075
1076 status = OMAP_HSMMC_READ(host->base, STAT);
1077 while (status & (INT_EN_MASK | CIRQ_EN)) {
1078 if (host->req_in_progress)
1079 omap_hsmmc_do_irq(host, status);
1080
1081 if (status & CIRQ_EN)
1082 mmc_signal_sdio_irq(host->mmc);
1083
1084 /* Flush posted write */
1085 status = OMAP_HSMMC_READ(host->base, STAT);
1086 }
1087
1088 return IRQ_HANDLED;
1089}
1090
1091static void set_sd_bus_power(struct omap_hsmmc_host *host)
1092{
1093 unsigned long i;
1094
1095 OMAP_HSMMC_WRITE(host->base, HCTL,
1096 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1097 for (i = 0; i < loops_per_jiffy; i++) {
1098 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1099 break;
1100 cpu_relax();
1101 }
1102}
1103
1104/*
1105 * Switch MMC interface voltage ... only relevant for MMC1.
1106 *
1107 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1108 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1109 * Some chips, like eMMC ones, use internal transceivers.
1110 */
1111static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1112{
1113 u32 reg_val = 0;
1114 int ret;
1115
1116 /* Disable the clocks */
1117 clk_disable_unprepare(host->dbclk);
1118
1119 /* Turn the power off */
1120 ret = omap_hsmmc_set_power(host, 0);
1121
1122 /* Turn the power ON with given VDD 1.8 or 3.0v */
1123 if (!ret)
1124 ret = omap_hsmmc_set_power(host, 1);
1125 clk_prepare_enable(host->dbclk);
1126
1127 if (ret != 0)
1128 goto err;
1129
1130 OMAP_HSMMC_WRITE(host->base, HCTL,
1131 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1132 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1133
1134 /*
1135 * If a MMC dual voltage card is detected, the set_ios fn calls
1136 * this fn with VDD bit set for 1.8V. Upon card removal from the
1137 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1138 *
1139 * Cope with a bit of slop in the range ... per data sheets:
1140 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1141 * but recommended values are 1.71V to 1.89V
1142 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1143 * but recommended values are 2.7V to 3.3V
1144 *
1145 * Board setup code shouldn't permit anything very out-of-range.
1146 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1147 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1148 */
1149 if ((1 << vdd) <= MMC_VDD_23_24)
1150 reg_val |= SDVS18;
1151 else
1152 reg_val |= SDVS30;
1153
1154 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1155 set_sd_bus_power(host);
1156
1157 return 0;
1158err:
1159 dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1160 return ret;
1161}
1162
1163static void omap_hsmmc_dma_callback(void *param)
1164{
1165 struct omap_hsmmc_host *host = param;
1166 struct dma_chan *chan;
1167 struct mmc_data *data;
1168 int req_in_progress;
1169
1170 spin_lock_irq(&host->irq_lock);
1171 if (host->dma_ch < 0) {
1172 spin_unlock_irq(&host->irq_lock);
1173 return;
1174 }
1175
1176 data = host->mrq->data;
1177 chan = omap_hsmmc_get_dma_chan(host, data);
1178 if (!data->host_cookie)
1179 dma_unmap_sg(chan->device->dev,
1180 data->sg, data->sg_len,
1181 mmc_get_dma_dir(data));
1182
1183 req_in_progress = host->req_in_progress;
1184 host->dma_ch = -1;
1185 spin_unlock_irq(&host->irq_lock);
1186
1187 /* If DMA has finished after TC, complete the request */
1188 if (!req_in_progress) {
1189 struct mmc_request *mrq = host->mrq;
1190
1191 host->mrq = NULL;
1192 mmc_request_done(host->mmc, mrq);
1193 }
1194}
1195
1196static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1197 struct mmc_data *data,
1198 struct omap_hsmmc_next *next,
1199 struct dma_chan *chan)
1200{
1201 int dma_len;
1202
1203 if (!next && data->host_cookie &&
1204 data->host_cookie != host->next_data.cookie) {
1205 dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d"
1206 " host->next_data.cookie %d\n",
1207 __func__, data->host_cookie, host->next_data.cookie);
1208 data->host_cookie = 0;
1209 }
1210
1211 /* Check if next job is already prepared */
1212 if (next || data->host_cookie != host->next_data.cookie) {
1213 dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len,
1214 mmc_get_dma_dir(data));
1215
1216 } else {
1217 dma_len = host->next_data.dma_len;
1218 host->next_data.dma_len = 0;
1219 }
1220
1221
1222 if (dma_len == 0)
1223 return -EINVAL;
1224
1225 if (next) {
1226 next->dma_len = dma_len;
1227 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1228 } else
1229 host->dma_len = dma_len;
1230
1231 return 0;
1232}
1233
1234/*
1235 * Routine to configure and start DMA for the MMC card
1236 */
1237static int omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host *host,
1238 struct mmc_request *req)
1239{
1240 struct dma_async_tx_descriptor *tx;
1241 int ret = 0, i;
1242 struct mmc_data *data = req->data;
1243 struct dma_chan *chan;
1244 struct dma_slave_config cfg = {
1245 .src_addr = host->mapbase + OMAP_HSMMC_DATA,
1246 .dst_addr = host->mapbase + OMAP_HSMMC_DATA,
1247 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
1248 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
1249 .src_maxburst = data->blksz / 4,
1250 .dst_maxburst = data->blksz / 4,
1251 };
1252
1253 /* Sanity check: all the SG entries must be aligned by block size. */
1254 for (i = 0; i < data->sg_len; i++) {
1255 struct scatterlist *sgl;
1256
1257 sgl = data->sg + i;
1258 if (sgl->length % data->blksz)
1259 return -EINVAL;
1260 }
1261 if ((data->blksz % 4) != 0)
1262 /* REVISIT: The MMC buffer increments only when MSB is written.
1263 * Return error for blksz which is non multiple of four.
1264 */
1265 return -EINVAL;
1266
1267 BUG_ON(host->dma_ch != -1);
1268
1269 chan = omap_hsmmc_get_dma_chan(host, data);
1270
1271 ret = dmaengine_slave_config(chan, &cfg);
1272 if (ret)
1273 return ret;
1274
1275 ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan);
1276 if (ret)
1277 return ret;
1278
1279 tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len,
1280 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1281 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1282 if (!tx) {
1283 dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n");
1284 /* FIXME: cleanup */
1285 return -1;
1286 }
1287
1288 tx->callback = omap_hsmmc_dma_callback;
1289 tx->callback_param = host;
1290
1291 /* Does not fail */
1292 dmaengine_submit(tx);
1293
1294 host->dma_ch = 1;
1295
1296 return 0;
1297}
1298
1299static void set_data_timeout(struct omap_hsmmc_host *host,
1300 unsigned long long timeout_ns,
1301 unsigned int timeout_clks)
1302{
1303 unsigned long long timeout = timeout_ns;
1304 unsigned int cycle_ns;
1305 uint32_t reg, clkd, dto = 0;
1306
1307 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1308 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1309 if (clkd == 0)
1310 clkd = 1;
1311
1312 cycle_ns = 1000000000 / (host->clk_rate / clkd);
1313 do_div(timeout, cycle_ns);
1314 timeout += timeout_clks;
1315 if (timeout) {
1316 while ((timeout & 0x80000000) == 0) {
1317 dto += 1;
1318 timeout <<= 1;
1319 }
1320 dto = 31 - dto;
1321 timeout <<= 1;
1322 if (timeout && dto)
1323 dto += 1;
1324 if (dto >= 13)
1325 dto -= 13;
1326 else
1327 dto = 0;
1328 if (dto > 14)
1329 dto = 14;
1330 }
1331
1332 reg &= ~DTO_MASK;
1333 reg |= dto << DTO_SHIFT;
1334 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1335}
1336
1337static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host)
1338{
1339 struct mmc_request *req = host->mrq;
1340 struct dma_chan *chan;
1341
1342 if (!req->data)
1343 return;
1344 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1345 | (req->data->blocks << 16));
1346 set_data_timeout(host, req->data->timeout_ns,
1347 req->data->timeout_clks);
1348 chan = omap_hsmmc_get_dma_chan(host, req->data);
1349 dma_async_issue_pending(chan);
1350}
1351
1352/*
1353 * Configure block length for MMC/SD cards and initiate the transfer.
1354 */
1355static int
1356omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1357{
1358 int ret;
1359 unsigned long long timeout;
1360
1361 host->data = req->data;
1362
1363 if (req->data == NULL) {
1364 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1365 if (req->cmd->flags & MMC_RSP_BUSY) {
1366 timeout = req->cmd->busy_timeout * NSEC_PER_MSEC;
1367
1368 /*
1369 * Set an arbitrary 100ms data timeout for commands with
1370 * busy signal and no indication of busy_timeout.
1371 */
1372 if (!timeout)
1373 timeout = 100000000U;
1374
1375 set_data_timeout(host, timeout, 0);
1376 }
1377 return 0;
1378 }
1379
1380 if (host->use_dma) {
1381 ret = omap_hsmmc_setup_dma_transfer(host, req);
1382 if (ret != 0) {
1383 dev_err(mmc_dev(host->mmc), "MMC start dma failure\n");
1384 return ret;
1385 }
1386 }
1387 return 0;
1388}
1389
1390static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1391 int err)
1392{
1393 struct omap_hsmmc_host *host = mmc_priv(mmc);
1394 struct mmc_data *data = mrq->data;
1395
1396 if (host->use_dma && data->host_cookie) {
1397 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data);
1398
1399 dma_unmap_sg(c->device->dev, data->sg, data->sg_len,
1400 mmc_get_dma_dir(data));
1401 data->host_cookie = 0;
1402 }
1403}
1404
1405static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
1406{
1407 struct omap_hsmmc_host *host = mmc_priv(mmc);
1408
1409 if (mrq->data->host_cookie) {
1410 mrq->data->host_cookie = 0;
1411 return ;
1412 }
1413
1414 if (host->use_dma) {
1415 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data);
1416
1417 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1418 &host->next_data, c))
1419 mrq->data->host_cookie = 0;
1420 }
1421}
1422
1423/*
1424 * Request function. for read/write operation
1425 */
1426static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1427{
1428 struct omap_hsmmc_host *host = mmc_priv(mmc);
1429 int err;
1430
1431 BUG_ON(host->req_in_progress);
1432 BUG_ON(host->dma_ch != -1);
1433 if (host->reqs_blocked)
1434 host->reqs_blocked = 0;
1435 WARN_ON(host->mrq != NULL);
1436 host->mrq = req;
1437 host->clk_rate = clk_get_rate(host->fclk);
1438 err = omap_hsmmc_prepare_data(host, req);
1439 if (err) {
1440 req->cmd->error = err;
1441 if (req->data)
1442 req->data->error = err;
1443 host->mrq = NULL;
1444 mmc_request_done(mmc, req);
1445 return;
1446 }
1447 if (req->sbc && !(host->flags & AUTO_CMD23)) {
1448 omap_hsmmc_start_command(host, req->sbc, NULL);
1449 return;
1450 }
1451
1452 omap_hsmmc_start_dma_transfer(host);
1453 omap_hsmmc_start_command(host, req->cmd, req->data);
1454}
1455
1456/* Routine to configure clock values. Exposed API to core */
1457static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1458{
1459 struct omap_hsmmc_host *host = mmc_priv(mmc);
1460 int do_send_init_stream = 0;
1461
1462 if (ios->power_mode != host->power_mode) {
1463 switch (ios->power_mode) {
1464 case MMC_POWER_OFF:
1465 omap_hsmmc_set_power(host, 0);
1466 break;
1467 case MMC_POWER_UP:
1468 omap_hsmmc_set_power(host, 1);
1469 break;
1470 case MMC_POWER_ON:
1471 do_send_init_stream = 1;
1472 break;
1473 }
1474 host->power_mode = ios->power_mode;
1475 }
1476
1477 /* FIXME: set registers based only on changes to ios */
1478
1479 omap_hsmmc_set_bus_width(host);
1480
1481 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1482 /* Only MMC1 can interface at 3V without some flavor
1483 * of external transceiver; but they all handle 1.8V.
1484 */
1485 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1486 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1487 /*
1488 * The mmc_select_voltage fn of the core does
1489 * not seem to set the power_mode to
1490 * MMC_POWER_UP upon recalculating the voltage.
1491 * vdd 1.8v.
1492 */
1493 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1494 dev_dbg(mmc_dev(host->mmc),
1495 "Switch operation failed\n");
1496 }
1497 }
1498
1499 omap_hsmmc_set_clock(host);
1500
1501 if (do_send_init_stream)
1502 send_init_stream(host);
1503
1504 omap_hsmmc_set_bus_mode(host);
1505}
1506
1507static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1508{
1509 struct omap_hsmmc_host *host = mmc_priv(mmc);
1510
1511 if (card->type == MMC_TYPE_SDIO || card->type == MMC_TYPE_SD_COMBO) {
1512 struct device_node *np = mmc_dev(mmc)->of_node;
1513
1514 /*
1515 * REVISIT: should be moved to sdio core and made more
1516 * general e.g. by expanding the DT bindings of child nodes
1517 * to provide a mechanism to provide this information:
1518 * Documentation/devicetree/bindings/mmc/mmc-card.txt
1519 */
1520
1521 np = of_get_compatible_child(np, "ti,wl1251");
1522 if (np) {
1523 /*
1524 * We have TI wl1251 attached to MMC3. Pass this
1525 * information to the SDIO core because it can't be
1526 * probed by normal methods.
1527 */
1528
1529 dev_info(host->dev, "found wl1251\n");
1530 card->quirks |= MMC_QUIRK_NONSTD_SDIO;
1531 card->cccr.wide_bus = 1;
1532 card->cis.vendor = 0x104c;
1533 card->cis.device = 0x9066;
1534 card->cis.blksize = 512;
1535 card->cis.max_dtr = 24000000;
1536 card->ocr = 0x80;
1537 of_node_put(np);
1538 }
1539 }
1540}
1541
1542static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
1543{
1544 struct omap_hsmmc_host *host = mmc_priv(mmc);
1545 u32 irq_mask, con;
1546 unsigned long flags;
1547
1548 spin_lock_irqsave(&host->irq_lock, flags);
1549
1550 con = OMAP_HSMMC_READ(host->base, CON);
1551 irq_mask = OMAP_HSMMC_READ(host->base, ISE);
1552 if (enable) {
1553 host->flags |= HSMMC_SDIO_IRQ_ENABLED;
1554 irq_mask |= CIRQ_EN;
1555 con |= CTPL | CLKEXTFREE;
1556 } else {
1557 host->flags &= ~HSMMC_SDIO_IRQ_ENABLED;
1558 irq_mask &= ~CIRQ_EN;
1559 con &= ~(CTPL | CLKEXTFREE);
1560 }
1561 OMAP_HSMMC_WRITE(host->base, CON, con);
1562 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
1563
1564 /*
1565 * if enable, piggy back detection on current request
1566 * but always disable immediately
1567 */
1568 if (!host->req_in_progress || !enable)
1569 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
1570
1571 /* flush posted write */
1572 OMAP_HSMMC_READ(host->base, IE);
1573
1574 spin_unlock_irqrestore(&host->irq_lock, flags);
1575}
1576
1577static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host *host)
1578{
1579 int ret;
1580
1581 /*
1582 * For omaps with wake-up path, wakeirq will be irq from pinctrl and
1583 * for other omaps, wakeirq will be from GPIO (dat line remuxed to
1584 * gpio). wakeirq is needed to detect sdio irq in runtime suspend state
1585 * with functional clock disabled.
1586 */
1587 if (!host->dev->of_node || !host->wake_irq)
1588 return -ENODEV;
1589
1590 ret = dev_pm_set_dedicated_wake_irq(host->dev, host->wake_irq);
1591 if (ret) {
1592 dev_err(mmc_dev(host->mmc), "Unable to request wake IRQ\n");
1593 goto err;
1594 }
1595
1596 /*
1597 * Some omaps don't have wake-up path from deeper idle states
1598 * and need to remux SDIO DAT1 to GPIO for wake-up from idle.
1599 */
1600 if (host->pdata->controller_flags & OMAP_HSMMC_SWAKEUP_MISSING) {
1601 struct pinctrl *p = devm_pinctrl_get(host->dev);
1602 if (IS_ERR(p)) {
1603 ret = PTR_ERR(p);
1604 goto err_free_irq;
1605 }
1606
1607 if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_IDLE))) {
1608 dev_info(host->dev, "missing idle pinctrl state\n");
1609 devm_pinctrl_put(p);
1610 ret = -EINVAL;
1611 goto err_free_irq;
1612 }
1613 devm_pinctrl_put(p);
1614 }
1615
1616 OMAP_HSMMC_WRITE(host->base, HCTL,
1617 OMAP_HSMMC_READ(host->base, HCTL) | IWE);
1618 return 0;
1619
1620err_free_irq:
1621 dev_pm_clear_wake_irq(host->dev);
1622err:
1623 dev_warn(host->dev, "no SDIO IRQ support, falling back to polling\n");
1624 host->wake_irq = 0;
1625 return ret;
1626}
1627
1628static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1629{
1630 u32 hctl, capa, value;
1631
1632 /* Only MMC1 supports 3.0V */
1633 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1634 hctl = SDVS30;
1635 capa = VS30 | VS18;
1636 } else {
1637 hctl = SDVS18;
1638 capa = VS18;
1639 }
1640
1641 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1642 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1643
1644 value = OMAP_HSMMC_READ(host->base, CAPA);
1645 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1646
1647 /* Set SD bus power bit */
1648 set_sd_bus_power(host);
1649}
1650
1651static int omap_hsmmc_multi_io_quirk(struct mmc_card *card,
1652 unsigned int direction, int blk_size)
1653{
1654 /* This controller can't do multiblock reads due to hw bugs */
1655 if (direction == MMC_DATA_READ)
1656 return 1;
1657
1658 return blk_size;
1659}
1660
1661static struct mmc_host_ops omap_hsmmc_ops = {
1662 .post_req = omap_hsmmc_post_req,
1663 .pre_req = omap_hsmmc_pre_req,
1664 .request = omap_hsmmc_request,
1665 .set_ios = omap_hsmmc_set_ios,
1666 .get_cd = mmc_gpio_get_cd,
1667 .get_ro = mmc_gpio_get_ro,
1668 .init_card = omap_hsmmc_init_card,
1669 .enable_sdio_irq = omap_hsmmc_enable_sdio_irq,
1670};
1671
1672#ifdef CONFIG_DEBUG_FS
1673
1674static int mmc_regs_show(struct seq_file *s, void *data)
1675{
1676 struct mmc_host *mmc = s->private;
1677 struct omap_hsmmc_host *host = mmc_priv(mmc);
1678
1679 seq_printf(s, "mmc%d:\n", mmc->index);
1680 seq_printf(s, "sdio irq mode\t%s\n",
1681 (mmc->caps & MMC_CAP_SDIO_IRQ) ? "interrupt" : "polling");
1682
1683 if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1684 seq_printf(s, "sdio irq \t%s\n",
1685 (host->flags & HSMMC_SDIO_IRQ_ENABLED) ? "enabled"
1686 : "disabled");
1687 }
1688 seq_printf(s, "ctx_loss:\t%d\n", host->context_loss);
1689
1690 pm_runtime_get_sync(host->dev);
1691 seq_puts(s, "\nregs:\n");
1692 seq_printf(s, "CON:\t\t0x%08x\n",
1693 OMAP_HSMMC_READ(host->base, CON));
1694 seq_printf(s, "PSTATE:\t\t0x%08x\n",
1695 OMAP_HSMMC_READ(host->base, PSTATE));
1696 seq_printf(s, "HCTL:\t\t0x%08x\n",
1697 OMAP_HSMMC_READ(host->base, HCTL));
1698 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1699 OMAP_HSMMC_READ(host->base, SYSCTL));
1700 seq_printf(s, "IE:\t\t0x%08x\n",
1701 OMAP_HSMMC_READ(host->base, IE));
1702 seq_printf(s, "ISE:\t\t0x%08x\n",
1703 OMAP_HSMMC_READ(host->base, ISE));
1704 seq_printf(s, "CAPA:\t\t0x%08x\n",
1705 OMAP_HSMMC_READ(host->base, CAPA));
1706
1707 pm_runtime_mark_last_busy(host->dev);
1708 pm_runtime_put_autosuspend(host->dev);
1709
1710 return 0;
1711}
1712
1713DEFINE_SHOW_ATTRIBUTE(mmc_regs);
1714
1715static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1716{
1717 if (mmc->debugfs_root)
1718 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1719 mmc, &mmc_regs_fops);
1720}
1721
1722#else
1723
1724static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1725{
1726}
1727
1728#endif
1729
1730#ifdef CONFIG_OF
1731static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = {
1732 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1733 .controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1734};
1735
1736static const struct omap_mmc_of_data omap4_mmc_of_data = {
1737 .reg_offset = 0x100,
1738};
1739static const struct omap_mmc_of_data am33xx_mmc_of_data = {
1740 .reg_offset = 0x100,
1741 .controller_flags = OMAP_HSMMC_SWAKEUP_MISSING,
1742};
1743
1744static const struct of_device_id omap_mmc_of_match[] = {
1745 {
1746 .compatible = "ti,omap2-hsmmc",
1747 },
1748 {
1749 .compatible = "ti,omap3-pre-es3-hsmmc",
1750 .data = &omap3_pre_es3_mmc_of_data,
1751 },
1752 {
1753 .compatible = "ti,omap3-hsmmc",
1754 },
1755 {
1756 .compatible = "ti,omap4-hsmmc",
1757 .data = &omap4_mmc_of_data,
1758 },
1759 {
1760 .compatible = "ti,am33xx-hsmmc",
1761 .data = &am33xx_mmc_of_data,
1762 },
1763 {},
1764};
1765MODULE_DEVICE_TABLE(of, omap_mmc_of_match);
1766
1767static struct omap_hsmmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
1768{
1769 struct omap_hsmmc_platform_data *pdata, *legacy;
1770 struct device_node *np = dev->of_node;
1771
1772 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1773 if (!pdata)
1774 return ERR_PTR(-ENOMEM); /* out of memory */
1775
1776 legacy = dev_get_platdata(dev);
1777 if (legacy && legacy->name)
1778 pdata->name = legacy->name;
1779
1780 if (of_find_property(np, "ti,dual-volt", NULL))
1781 pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1782
1783 if (of_find_property(np, "ti,non-removable", NULL)) {
1784 pdata->nonremovable = true;
1785 pdata->no_regulator_off_init = true;
1786 }
1787
1788 if (of_find_property(np, "ti,needs-special-reset", NULL))
1789 pdata->features |= HSMMC_HAS_UPDATED_RESET;
1790
1791 if (of_find_property(np, "ti,needs-special-hs-handling", NULL))
1792 pdata->features |= HSMMC_HAS_HSPE_SUPPORT;
1793
1794 return pdata;
1795}
1796#else
1797static inline struct omap_hsmmc_platform_data
1798 *of_get_hsmmc_pdata(struct device *dev)
1799{
1800 return ERR_PTR(-EINVAL);
1801}
1802#endif
1803
1804static int omap_hsmmc_probe(struct platform_device *pdev)
1805{
1806 struct omap_hsmmc_platform_data *pdata = pdev->dev.platform_data;
1807 struct mmc_host *mmc;
1808 struct omap_hsmmc_host *host = NULL;
1809 struct resource *res;
1810 int ret, irq;
1811 const struct of_device_id *match;
1812 const struct omap_mmc_of_data *data;
1813 void __iomem *base;
1814
1815 match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
1816 if (match) {
1817 pdata = of_get_hsmmc_pdata(&pdev->dev);
1818
1819 if (IS_ERR(pdata))
1820 return PTR_ERR(pdata);
1821
1822 if (match->data) {
1823 data = match->data;
1824 pdata->reg_offset = data->reg_offset;
1825 pdata->controller_flags |= data->controller_flags;
1826 }
1827 }
1828
1829 if (pdata == NULL) {
1830 dev_err(&pdev->dev, "Platform Data is missing\n");
1831 return -ENXIO;
1832 }
1833
1834 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1835 irq = platform_get_irq(pdev, 0);
1836 if (res == NULL || irq < 0)
1837 return -ENXIO;
1838
1839 base = devm_ioremap_resource(&pdev->dev, res);
1840 if (IS_ERR(base))
1841 return PTR_ERR(base);
1842
1843 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
1844 if (!mmc) {
1845 ret = -ENOMEM;
1846 goto err;
1847 }
1848
1849 ret = mmc_of_parse(mmc);
1850 if (ret)
1851 goto err1;
1852
1853 host = mmc_priv(mmc);
1854 host->mmc = mmc;
1855 host->pdata = pdata;
1856 host->dev = &pdev->dev;
1857 host->use_dma = 1;
1858 host->dma_ch = -1;
1859 host->irq = irq;
1860 host->mapbase = res->start + pdata->reg_offset;
1861 host->base = base + pdata->reg_offset;
1862 host->power_mode = MMC_POWER_OFF;
1863 host->next_data.cookie = 1;
1864 host->pbias_enabled = 0;
1865 host->vqmmc_enabled = 0;
1866
1867 platform_set_drvdata(pdev, host);
1868
1869 if (pdev->dev.of_node)
1870 host->wake_irq = irq_of_parse_and_map(pdev->dev.of_node, 1);
1871
1872 mmc->ops = &omap_hsmmc_ops;
1873
1874 mmc->f_min = OMAP_MMC_MIN_CLOCK;
1875
1876 if (pdata->max_freq > 0)
1877 mmc->f_max = pdata->max_freq;
1878 else if (mmc->f_max == 0)
1879 mmc->f_max = OMAP_MMC_MAX_CLOCK;
1880
1881 spin_lock_init(&host->irq_lock);
1882
1883 host->fclk = devm_clk_get(&pdev->dev, "fck");
1884 if (IS_ERR(host->fclk)) {
1885 ret = PTR_ERR(host->fclk);
1886 host->fclk = NULL;
1887 goto err1;
1888 }
1889
1890 if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
1891 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
1892 omap_hsmmc_ops.multi_io_quirk = omap_hsmmc_multi_io_quirk;
1893 }
1894
1895 device_init_wakeup(&pdev->dev, true);
1896 pm_runtime_enable(host->dev);
1897 pm_runtime_get_sync(host->dev);
1898 pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
1899 pm_runtime_use_autosuspend(host->dev);
1900
1901 omap_hsmmc_context_save(host);
1902
1903 host->dbclk = devm_clk_get(&pdev->dev, "mmchsdb_fck");
1904 /*
1905 * MMC can still work without debounce clock.
1906 */
1907 if (IS_ERR(host->dbclk)) {
1908 host->dbclk = NULL;
1909 } else if (clk_prepare_enable(host->dbclk) != 0) {
1910 dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n");
1911 host->dbclk = NULL;
1912 }
1913
1914 /* Set this to a value that allows allocating an entire descriptor
1915 * list within a page (zero order allocation). */
1916 mmc->max_segs = 64;
1917
1918 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
1919 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
1920 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1921
1922 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
1923 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_CMD23;
1924
1925 mmc->caps |= mmc_pdata(host)->caps;
1926 if (mmc->caps & MMC_CAP_8_BIT_DATA)
1927 mmc->caps |= MMC_CAP_4_BIT_DATA;
1928
1929 if (mmc_pdata(host)->nonremovable)
1930 mmc->caps |= MMC_CAP_NONREMOVABLE;
1931
1932 mmc->pm_caps |= mmc_pdata(host)->pm_caps;
1933
1934 omap_hsmmc_conf_bus_power(host);
1935
1936 host->rx_chan = dma_request_chan(&pdev->dev, "rx");
1937 if (IS_ERR(host->rx_chan)) {
1938 dev_err(mmc_dev(host->mmc), "RX DMA channel request failed\n");
1939 ret = PTR_ERR(host->rx_chan);
1940 goto err_irq;
1941 }
1942
1943 host->tx_chan = dma_request_chan(&pdev->dev, "tx");
1944 if (IS_ERR(host->tx_chan)) {
1945 dev_err(mmc_dev(host->mmc), "TX DMA channel request failed\n");
1946 ret = PTR_ERR(host->tx_chan);
1947 goto err_irq;
1948 }
1949
1950 /*
1951 * Limit the maximum segment size to the lower of the request size
1952 * and the DMA engine device segment size limits. In reality, with
1953 * 32-bit transfers, the DMA engine can do longer segments than this
1954 * but there is no way to represent that in the DMA model - if we
1955 * increase this figure here, we get warnings from the DMA API debug.
1956 */
1957 mmc->max_seg_size = min3(mmc->max_req_size,
1958 dma_get_max_seg_size(host->rx_chan->device->dev),
1959 dma_get_max_seg_size(host->tx_chan->device->dev));
1960
1961 /* Request IRQ for MMC operations */
1962 ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0,
1963 mmc_hostname(mmc), host);
1964 if (ret) {
1965 dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1966 goto err_irq;
1967 }
1968
1969 ret = omap_hsmmc_reg_get(host);
1970 if (ret)
1971 goto err_irq;
1972
1973 if (!mmc->ocr_avail)
1974 mmc->ocr_avail = mmc_pdata(host)->ocr_mask;
1975
1976 omap_hsmmc_disable_irq(host);
1977
1978 /*
1979 * For now, only support SDIO interrupt if we have a separate
1980 * wake-up interrupt configured from device tree. This is because
1981 * the wake-up interrupt is needed for idle state and some
1982 * platforms need special quirks. And we don't want to add new
1983 * legacy mux platform init code callbacks any longer as we
1984 * are moving to DT based booting anyways.
1985 */
1986 ret = omap_hsmmc_configure_wake_irq(host);
1987 if (!ret)
1988 mmc->caps |= MMC_CAP_SDIO_IRQ;
1989
1990 mmc_add_host(mmc);
1991
1992 if (mmc_pdata(host)->name != NULL) {
1993 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
1994 if (ret < 0)
1995 goto err_slot_name;
1996 }
1997
1998 omap_hsmmc_debugfs(mmc);
1999 pm_runtime_mark_last_busy(host->dev);
2000 pm_runtime_put_autosuspend(host->dev);
2001
2002 return 0;
2003
2004err_slot_name:
2005 mmc_remove_host(mmc);
2006err_irq:
2007 device_init_wakeup(&pdev->dev, false);
2008 if (!IS_ERR_OR_NULL(host->tx_chan))
2009 dma_release_channel(host->tx_chan);
2010 if (!IS_ERR_OR_NULL(host->rx_chan))
2011 dma_release_channel(host->rx_chan);
2012 pm_runtime_dont_use_autosuspend(host->dev);
2013 pm_runtime_put_sync(host->dev);
2014 pm_runtime_disable(host->dev);
2015 clk_disable_unprepare(host->dbclk);
2016err1:
2017 mmc_free_host(mmc);
2018err:
2019 return ret;
2020}
2021
2022static int omap_hsmmc_remove(struct platform_device *pdev)
2023{
2024 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2025
2026 pm_runtime_get_sync(host->dev);
2027 mmc_remove_host(host->mmc);
2028
2029 dma_release_channel(host->tx_chan);
2030 dma_release_channel(host->rx_chan);
2031
2032 dev_pm_clear_wake_irq(host->dev);
2033 pm_runtime_dont_use_autosuspend(host->dev);
2034 pm_runtime_put_sync(host->dev);
2035 pm_runtime_disable(host->dev);
2036 device_init_wakeup(&pdev->dev, false);
2037 clk_disable_unprepare(host->dbclk);
2038
2039 mmc_free_host(host->mmc);
2040
2041 return 0;
2042}
2043
2044#ifdef CONFIG_PM_SLEEP
2045static int omap_hsmmc_suspend(struct device *dev)
2046{
2047 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2048
2049 if (!host)
2050 return 0;
2051
2052 pm_runtime_get_sync(host->dev);
2053
2054 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
2055 OMAP_HSMMC_WRITE(host->base, ISE, 0);
2056 OMAP_HSMMC_WRITE(host->base, IE, 0);
2057 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2058 OMAP_HSMMC_WRITE(host->base, HCTL,
2059 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2060 }
2061
2062 clk_disable_unprepare(host->dbclk);
2063
2064 pm_runtime_put_sync(host->dev);
2065 return 0;
2066}
2067
2068/* Routine to resume the MMC device */
2069static int omap_hsmmc_resume(struct device *dev)
2070{
2071 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2072
2073 if (!host)
2074 return 0;
2075
2076 pm_runtime_get_sync(host->dev);
2077
2078 clk_prepare_enable(host->dbclk);
2079
2080 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
2081 omap_hsmmc_conf_bus_power(host);
2082
2083 pm_runtime_mark_last_busy(host->dev);
2084 pm_runtime_put_autosuspend(host->dev);
2085 return 0;
2086}
2087#endif
2088
2089static int omap_hsmmc_runtime_suspend(struct device *dev)
2090{
2091 struct omap_hsmmc_host *host;
2092 unsigned long flags;
2093 int ret = 0;
2094
2095 host = dev_get_drvdata(dev);
2096 omap_hsmmc_context_save(host);
2097 dev_dbg(dev, "disabled\n");
2098
2099 spin_lock_irqsave(&host->irq_lock, flags);
2100 if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2101 (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
2102 /* disable sdio irq handling to prevent race */
2103 OMAP_HSMMC_WRITE(host->base, ISE, 0);
2104 OMAP_HSMMC_WRITE(host->base, IE, 0);
2105
2106 if (!(OMAP_HSMMC_READ(host->base, PSTATE) & DLEV_DAT(1))) {
2107 /*
2108 * dat1 line low, pending sdio irq
2109 * race condition: possible irq handler running on
2110 * multi-core, abort
2111 */
2112 dev_dbg(dev, "pending sdio irq, abort suspend\n");
2113 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2114 OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
2115 OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
2116 pm_runtime_mark_last_busy(dev);
2117 ret = -EBUSY;
2118 goto abort;
2119 }
2120
2121 pinctrl_pm_select_idle_state(dev);
2122 } else {
2123 pinctrl_pm_select_idle_state(dev);
2124 }
2125
2126abort:
2127 spin_unlock_irqrestore(&host->irq_lock, flags);
2128 return ret;
2129}
2130
2131static int omap_hsmmc_runtime_resume(struct device *dev)
2132{
2133 struct omap_hsmmc_host *host;
2134 unsigned long flags;
2135
2136 host = dev_get_drvdata(dev);
2137 omap_hsmmc_context_restore(host);
2138 dev_dbg(dev, "enabled\n");
2139
2140 spin_lock_irqsave(&host->irq_lock, flags);
2141 if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2142 (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
2143
2144 pinctrl_select_default_state(host->dev);
2145
2146 /* irq lost, if pinmux incorrect */
2147 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2148 OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
2149 OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
2150 } else {
2151 pinctrl_select_default_state(host->dev);
2152 }
2153 spin_unlock_irqrestore(&host->irq_lock, flags);
2154 return 0;
2155}
2156
2157static const struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2158 SET_SYSTEM_SLEEP_PM_OPS(omap_hsmmc_suspend, omap_hsmmc_resume)
2159 .runtime_suspend = omap_hsmmc_runtime_suspend,
2160 .runtime_resume = omap_hsmmc_runtime_resume,
2161};
2162
2163static struct platform_driver omap_hsmmc_driver = {
2164 .probe = omap_hsmmc_probe,
2165 .remove = omap_hsmmc_remove,
2166 .driver = {
2167 .name = DRIVER_NAME,
2168 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
2169 .pm = &omap_hsmmc_dev_pm_ops,
2170 .of_match_table = of_match_ptr(omap_mmc_of_match),
2171 },
2172};
2173
2174module_platform_driver(omap_hsmmc_driver);
2175MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2176MODULE_LICENSE("GPL");
2177MODULE_ALIAS("platform:" DRIVER_NAME);
2178MODULE_AUTHOR("Texas Instruments Inc");
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