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1 | /* | |
2 | * CAN bus driver for Bosch C_CAN controller | |
3 | * | |
4 | * Copyright (C) 2010 ST Microelectronics | |
5 | * Bhupesh Sharma <bhupesh.sharma@st.com> | |
6 | * | |
7 | * Borrowed heavily from the C_CAN driver originally written by: | |
8 | * Copyright (C) 2007 | |
9 | * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de> | |
10 | * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch> | |
11 | * | |
12 | * TX and RX NAPI implementation has been borrowed from at91 CAN driver | |
13 | * written by: | |
14 | * Copyright | |
15 | * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de> | |
16 | * (C) 2008, 2009 by Marc Kleine-Budde <kernel@pengutronix.de> | |
17 | * | |
18 | * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B. | |
19 | * Bosch C_CAN user manual can be obtained from: | |
20 | * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/ | |
21 | * users_manual_c_can.pdf | |
22 | * | |
23 | * This file is licensed under the terms of the GNU General Public | |
24 | * License version 2. This program is licensed "as is" without any | |
25 | * warranty of any kind, whether express or implied. | |
26 | */ | |
27 | ||
28 | #include <linux/kernel.h> | |
29 | #include <linux/module.h> | |
30 | #include <linux/interrupt.h> | |
31 | #include <linux/delay.h> | |
32 | #include <linux/netdevice.h> | |
33 | #include <linux/if_arp.h> | |
34 | #include <linux/if_ether.h> | |
35 | #include <linux/list.h> | |
36 | #include <linux/io.h> | |
37 | #include <linux/pm_runtime.h> | |
38 | #include <linux/pinctrl/consumer.h> | |
39 | ||
40 | #include <linux/can.h> | |
41 | #include <linux/can/dev.h> | |
42 | #include <linux/can/error.h> | |
43 | #include <linux/can/led.h> | |
44 | ||
45 | #include "c_can.h" | |
46 | ||
47 | /* Number of interface registers */ | |
48 | #define IF_ENUM_REG_LEN 11 | |
49 | #define C_CAN_IFACE(reg, iface) (C_CAN_IF1_##reg + (iface) * IF_ENUM_REG_LEN) | |
50 | ||
51 | /* control extension register D_CAN specific */ | |
52 | #define CONTROL_EX_PDR BIT(8) | |
53 | ||
54 | /* control register */ | |
55 | #define CONTROL_TEST BIT(7) | |
56 | #define CONTROL_CCE BIT(6) | |
57 | #define CONTROL_DISABLE_AR BIT(5) | |
58 | #define CONTROL_ENABLE_AR (0 << 5) | |
59 | #define CONTROL_EIE BIT(3) | |
60 | #define CONTROL_SIE BIT(2) | |
61 | #define CONTROL_IE BIT(1) | |
62 | #define CONTROL_INIT BIT(0) | |
63 | ||
64 | #define CONTROL_IRQMSK (CONTROL_EIE | CONTROL_IE | CONTROL_SIE) | |
65 | ||
66 | /* test register */ | |
67 | #define TEST_RX BIT(7) | |
68 | #define TEST_TX1 BIT(6) | |
69 | #define TEST_TX2 BIT(5) | |
70 | #define TEST_LBACK BIT(4) | |
71 | #define TEST_SILENT BIT(3) | |
72 | #define TEST_BASIC BIT(2) | |
73 | ||
74 | /* status register */ | |
75 | #define STATUS_PDA BIT(10) | |
76 | #define STATUS_BOFF BIT(7) | |
77 | #define STATUS_EWARN BIT(6) | |
78 | #define STATUS_EPASS BIT(5) | |
79 | #define STATUS_RXOK BIT(4) | |
80 | #define STATUS_TXOK BIT(3) | |
81 | ||
82 | /* error counter register */ | |
83 | #define ERR_CNT_TEC_MASK 0xff | |
84 | #define ERR_CNT_TEC_SHIFT 0 | |
85 | #define ERR_CNT_REC_SHIFT 8 | |
86 | #define ERR_CNT_REC_MASK (0x7f << ERR_CNT_REC_SHIFT) | |
87 | #define ERR_CNT_RP_SHIFT 15 | |
88 | #define ERR_CNT_RP_MASK (0x1 << ERR_CNT_RP_SHIFT) | |
89 | ||
90 | /* bit-timing register */ | |
91 | #define BTR_BRP_MASK 0x3f | |
92 | #define BTR_BRP_SHIFT 0 | |
93 | #define BTR_SJW_SHIFT 6 | |
94 | #define BTR_SJW_MASK (0x3 << BTR_SJW_SHIFT) | |
95 | #define BTR_TSEG1_SHIFT 8 | |
96 | #define BTR_TSEG1_MASK (0xf << BTR_TSEG1_SHIFT) | |
97 | #define BTR_TSEG2_SHIFT 12 | |
98 | #define BTR_TSEG2_MASK (0x7 << BTR_TSEG2_SHIFT) | |
99 | ||
100 | /* brp extension register */ | |
101 | #define BRP_EXT_BRPE_MASK 0x0f | |
102 | #define BRP_EXT_BRPE_SHIFT 0 | |
103 | ||
104 | /* IFx command request */ | |
105 | #define IF_COMR_BUSY BIT(15) | |
106 | ||
107 | /* IFx command mask */ | |
108 | #define IF_COMM_WR BIT(7) | |
109 | #define IF_COMM_MASK BIT(6) | |
110 | #define IF_COMM_ARB BIT(5) | |
111 | #define IF_COMM_CONTROL BIT(4) | |
112 | #define IF_COMM_CLR_INT_PND BIT(3) | |
113 | #define IF_COMM_TXRQST BIT(2) | |
114 | #define IF_COMM_CLR_NEWDAT IF_COMM_TXRQST | |
115 | #define IF_COMM_DATAA BIT(1) | |
116 | #define IF_COMM_DATAB BIT(0) | |
117 | ||
118 | /* TX buffer setup */ | |
119 | #define IF_COMM_TX (IF_COMM_ARB | IF_COMM_CONTROL | \ | |
120 | IF_COMM_TXRQST | \ | |
121 | IF_COMM_DATAA | IF_COMM_DATAB) | |
122 | ||
123 | /* For the low buffers we clear the interrupt bit, but keep newdat */ | |
124 | #define IF_COMM_RCV_LOW (IF_COMM_MASK | IF_COMM_ARB | \ | |
125 | IF_COMM_CONTROL | IF_COMM_CLR_INT_PND | \ | |
126 | IF_COMM_DATAA | IF_COMM_DATAB) | |
127 | ||
128 | /* For the high buffers we clear the interrupt bit and newdat */ | |
129 | #define IF_COMM_RCV_HIGH (IF_COMM_RCV_LOW | IF_COMM_CLR_NEWDAT) | |
130 | ||
131 | ||
132 | /* Receive setup of message objects */ | |
133 | #define IF_COMM_RCV_SETUP (IF_COMM_MASK | IF_COMM_ARB | IF_COMM_CONTROL) | |
134 | ||
135 | /* Invalidation of message objects */ | |
136 | #define IF_COMM_INVAL (IF_COMM_ARB | IF_COMM_CONTROL) | |
137 | ||
138 | /* IFx arbitration */ | |
139 | #define IF_ARB_MSGVAL BIT(31) | |
140 | #define IF_ARB_MSGXTD BIT(30) | |
141 | #define IF_ARB_TRANSMIT BIT(29) | |
142 | ||
143 | /* IFx message control */ | |
144 | #define IF_MCONT_NEWDAT BIT(15) | |
145 | #define IF_MCONT_MSGLST BIT(14) | |
146 | #define IF_MCONT_INTPND BIT(13) | |
147 | #define IF_MCONT_UMASK BIT(12) | |
148 | #define IF_MCONT_TXIE BIT(11) | |
149 | #define IF_MCONT_RXIE BIT(10) | |
150 | #define IF_MCONT_RMTEN BIT(9) | |
151 | #define IF_MCONT_TXRQST BIT(8) | |
152 | #define IF_MCONT_EOB BIT(7) | |
153 | #define IF_MCONT_DLC_MASK 0xf | |
154 | ||
155 | #define IF_MCONT_RCV (IF_MCONT_RXIE | IF_MCONT_UMASK) | |
156 | #define IF_MCONT_RCV_EOB (IF_MCONT_RCV | IF_MCONT_EOB) | |
157 | ||
158 | #define IF_MCONT_TX (IF_MCONT_TXIE | IF_MCONT_EOB) | |
159 | ||
160 | /* | |
161 | * Use IF1 for RX and IF2 for TX | |
162 | */ | |
163 | #define IF_RX 0 | |
164 | #define IF_TX 1 | |
165 | ||
166 | /* minimum timeout for checking BUSY status */ | |
167 | #define MIN_TIMEOUT_VALUE 6 | |
168 | ||
169 | /* Wait for ~1 sec for INIT bit */ | |
170 | #define INIT_WAIT_MS 1000 | |
171 | ||
172 | /* napi related */ | |
173 | #define C_CAN_NAPI_WEIGHT C_CAN_MSG_OBJ_RX_NUM | |
174 | ||
175 | /* c_can lec values */ | |
176 | enum c_can_lec_type { | |
177 | LEC_NO_ERROR = 0, | |
178 | LEC_STUFF_ERROR, | |
179 | LEC_FORM_ERROR, | |
180 | LEC_ACK_ERROR, | |
181 | LEC_BIT1_ERROR, | |
182 | LEC_BIT0_ERROR, | |
183 | LEC_CRC_ERROR, | |
184 | LEC_UNUSED, | |
185 | LEC_MASK = LEC_UNUSED, | |
186 | }; | |
187 | ||
188 | /* | |
189 | * c_can error types: | |
190 | * Bus errors (BUS_OFF, ERROR_WARNING, ERROR_PASSIVE) are supported | |
191 | */ | |
192 | enum c_can_bus_error_types { | |
193 | C_CAN_NO_ERROR = 0, | |
194 | C_CAN_BUS_OFF, | |
195 | C_CAN_ERROR_WARNING, | |
196 | C_CAN_ERROR_PASSIVE, | |
197 | }; | |
198 | ||
199 | static const struct can_bittiming_const c_can_bittiming_const = { | |
200 | .name = KBUILD_MODNAME, | |
201 | .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */ | |
202 | .tseg1_max = 16, | |
203 | .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ | |
204 | .tseg2_max = 8, | |
205 | .sjw_max = 4, | |
206 | .brp_min = 1, | |
207 | .brp_max = 1024, /* 6-bit BRP field + 4-bit BRPE field*/ | |
208 | .brp_inc = 1, | |
209 | }; | |
210 | ||
211 | static inline void c_can_pm_runtime_enable(const struct c_can_priv *priv) | |
212 | { | |
213 | if (priv->device) | |
214 | pm_runtime_enable(priv->device); | |
215 | } | |
216 | ||
217 | static inline void c_can_pm_runtime_disable(const struct c_can_priv *priv) | |
218 | { | |
219 | if (priv->device) | |
220 | pm_runtime_disable(priv->device); | |
221 | } | |
222 | ||
223 | static inline void c_can_pm_runtime_get_sync(const struct c_can_priv *priv) | |
224 | { | |
225 | if (priv->device) | |
226 | pm_runtime_get_sync(priv->device); | |
227 | } | |
228 | ||
229 | static inline void c_can_pm_runtime_put_sync(const struct c_can_priv *priv) | |
230 | { | |
231 | if (priv->device) | |
232 | pm_runtime_put_sync(priv->device); | |
233 | } | |
234 | ||
235 | static inline void c_can_reset_ram(const struct c_can_priv *priv, bool enable) | |
236 | { | |
237 | if (priv->raminit) | |
238 | priv->raminit(priv, enable); | |
239 | } | |
240 | ||
241 | static void c_can_irq_control(struct c_can_priv *priv, bool enable) | |
242 | { | |
243 | u32 ctrl = priv->read_reg(priv, C_CAN_CTRL_REG) & ~CONTROL_IRQMSK; | |
244 | ||
245 | if (enable) | |
246 | ctrl |= CONTROL_IRQMSK; | |
247 | ||
248 | priv->write_reg(priv, C_CAN_CTRL_REG, ctrl); | |
249 | } | |
250 | ||
251 | static void c_can_obj_update(struct net_device *dev, int iface, u32 cmd, u32 obj) | |
252 | { | |
253 | struct c_can_priv *priv = netdev_priv(dev); | |
254 | int cnt, reg = C_CAN_IFACE(COMREQ_REG, iface); | |
255 | ||
256 | priv->write_reg32(priv, reg, (cmd << 16) | obj); | |
257 | ||
258 | for (cnt = MIN_TIMEOUT_VALUE; cnt; cnt--) { | |
259 | if (!(priv->read_reg(priv, reg) & IF_COMR_BUSY)) | |
260 | return; | |
261 | udelay(1); | |
262 | } | |
263 | netdev_err(dev, "Updating object timed out\n"); | |
264 | ||
265 | } | |
266 | ||
267 | static inline void c_can_object_get(struct net_device *dev, int iface, | |
268 | u32 obj, u32 cmd) | |
269 | { | |
270 | c_can_obj_update(dev, iface, cmd, obj); | |
271 | } | |
272 | ||
273 | static inline void c_can_object_put(struct net_device *dev, int iface, | |
274 | u32 obj, u32 cmd) | |
275 | { | |
276 | c_can_obj_update(dev, iface, cmd | IF_COMM_WR, obj); | |
277 | } | |
278 | ||
279 | /* | |
280 | * Note: According to documentation clearing TXIE while MSGVAL is set | |
281 | * is not allowed, but works nicely on C/DCAN. And that lowers the I/O | |
282 | * load significantly. | |
283 | */ | |
284 | static void c_can_inval_tx_object(struct net_device *dev, int iface, int obj) | |
285 | { | |
286 | struct c_can_priv *priv = netdev_priv(dev); | |
287 | ||
288 | priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 0); | |
289 | c_can_object_put(dev, iface, obj, IF_COMM_INVAL); | |
290 | } | |
291 | ||
292 | static void c_can_inval_msg_object(struct net_device *dev, int iface, int obj) | |
293 | { | |
294 | struct c_can_priv *priv = netdev_priv(dev); | |
295 | ||
296 | priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 0); | |
297 | priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), 0); | |
298 | c_can_inval_tx_object(dev, iface, obj); | |
299 | } | |
300 | ||
301 | static void c_can_setup_tx_object(struct net_device *dev, int iface, | |
302 | struct can_frame *frame, int idx) | |
303 | { | |
304 | struct c_can_priv *priv = netdev_priv(dev); | |
305 | u16 ctrl = IF_MCONT_TX | frame->can_dlc; | |
306 | bool rtr = frame->can_id & CAN_RTR_FLAG; | |
307 | u32 arb = IF_ARB_MSGVAL; | |
308 | int i; | |
309 | ||
310 | if (frame->can_id & CAN_EFF_FLAG) { | |
311 | arb |= frame->can_id & CAN_EFF_MASK; | |
312 | arb |= IF_ARB_MSGXTD; | |
313 | } else { | |
314 | arb |= (frame->can_id & CAN_SFF_MASK) << 18; | |
315 | } | |
316 | ||
317 | if (!rtr) | |
318 | arb |= IF_ARB_TRANSMIT; | |
319 | ||
320 | /* | |
321 | * If we change the DIR bit, we need to invalidate the buffer | |
322 | * first, i.e. clear the MSGVAL flag in the arbiter. | |
323 | */ | |
324 | if (rtr != (bool)test_bit(idx, &priv->tx_dir)) { | |
325 | u32 obj = idx + C_CAN_MSG_OBJ_TX_FIRST; | |
326 | ||
327 | c_can_inval_msg_object(dev, iface, obj); | |
328 | change_bit(idx, &priv->tx_dir); | |
329 | } | |
330 | ||
331 | priv->write_reg32(priv, C_CAN_IFACE(ARB1_REG, iface), arb); | |
332 | ||
333 | priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl); | |
334 | ||
335 | if (priv->type == BOSCH_D_CAN) { | |
336 | u32 data = 0, dreg = C_CAN_IFACE(DATA1_REG, iface); | |
337 | ||
338 | for (i = 0; i < frame->can_dlc; i += 4, dreg += 2) { | |
339 | data = (u32)frame->data[i]; | |
340 | data |= (u32)frame->data[i + 1] << 8; | |
341 | data |= (u32)frame->data[i + 2] << 16; | |
342 | data |= (u32)frame->data[i + 3] << 24; | |
343 | priv->write_reg32(priv, dreg, data); | |
344 | } | |
345 | } else { | |
346 | for (i = 0; i < frame->can_dlc; i += 2) { | |
347 | priv->write_reg(priv, | |
348 | C_CAN_IFACE(DATA1_REG, iface) + i / 2, | |
349 | frame->data[i] | | |
350 | (frame->data[i + 1] << 8)); | |
351 | } | |
352 | } | |
353 | } | |
354 | ||
355 | static inline void c_can_activate_all_lower_rx_msg_obj(struct net_device *dev, | |
356 | int iface) | |
357 | { | |
358 | int i; | |
359 | ||
360 | for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_MSG_RX_LOW_LAST; i++) | |
361 | c_can_object_get(dev, iface, i, IF_COMM_CLR_NEWDAT); | |
362 | } | |
363 | ||
364 | static int c_can_handle_lost_msg_obj(struct net_device *dev, | |
365 | int iface, int objno, u32 ctrl) | |
366 | { | |
367 | struct net_device_stats *stats = &dev->stats; | |
368 | struct c_can_priv *priv = netdev_priv(dev); | |
369 | struct can_frame *frame; | |
370 | struct sk_buff *skb; | |
371 | ||
372 | ctrl &= ~(IF_MCONT_MSGLST | IF_MCONT_INTPND | IF_MCONT_NEWDAT); | |
373 | priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl); | |
374 | c_can_object_put(dev, iface, objno, IF_COMM_CONTROL); | |
375 | ||
376 | stats->rx_errors++; | |
377 | stats->rx_over_errors++; | |
378 | ||
379 | /* create an error msg */ | |
380 | skb = alloc_can_err_skb(dev, &frame); | |
381 | if (unlikely(!skb)) | |
382 | return 0; | |
383 | ||
384 | frame->can_id |= CAN_ERR_CRTL; | |
385 | frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; | |
386 | ||
387 | netif_receive_skb(skb); | |
388 | return 1; | |
389 | } | |
390 | ||
391 | static int c_can_read_msg_object(struct net_device *dev, int iface, u32 ctrl) | |
392 | { | |
393 | struct net_device_stats *stats = &dev->stats; | |
394 | struct c_can_priv *priv = netdev_priv(dev); | |
395 | struct can_frame *frame; | |
396 | struct sk_buff *skb; | |
397 | u32 arb, data; | |
398 | ||
399 | skb = alloc_can_skb(dev, &frame); | |
400 | if (!skb) { | |
401 | stats->rx_dropped++; | |
402 | return -ENOMEM; | |
403 | } | |
404 | ||
405 | frame->can_dlc = get_can_dlc(ctrl & 0x0F); | |
406 | ||
407 | arb = priv->read_reg32(priv, C_CAN_IFACE(ARB1_REG, iface)); | |
408 | ||
409 | if (arb & IF_ARB_MSGXTD) | |
410 | frame->can_id = (arb & CAN_EFF_MASK) | CAN_EFF_FLAG; | |
411 | else | |
412 | frame->can_id = (arb >> 18) & CAN_SFF_MASK; | |
413 | ||
414 | if (arb & IF_ARB_TRANSMIT) { | |
415 | frame->can_id |= CAN_RTR_FLAG; | |
416 | } else { | |
417 | int i, dreg = C_CAN_IFACE(DATA1_REG, iface); | |
418 | ||
419 | if (priv->type == BOSCH_D_CAN) { | |
420 | for (i = 0; i < frame->can_dlc; i += 4, dreg += 2) { | |
421 | data = priv->read_reg32(priv, dreg); | |
422 | frame->data[i] = data; | |
423 | frame->data[i + 1] = data >> 8; | |
424 | frame->data[i + 2] = data >> 16; | |
425 | frame->data[i + 3] = data >> 24; | |
426 | } | |
427 | } else { | |
428 | for (i = 0; i < frame->can_dlc; i += 2, dreg++) { | |
429 | data = priv->read_reg(priv, dreg); | |
430 | frame->data[i] = data; | |
431 | frame->data[i + 1] = data >> 8; | |
432 | } | |
433 | } | |
434 | } | |
435 | ||
436 | stats->rx_packets++; | |
437 | stats->rx_bytes += frame->can_dlc; | |
438 | ||
439 | netif_receive_skb(skb); | |
440 | return 0; | |
441 | } | |
442 | ||
443 | static void c_can_setup_receive_object(struct net_device *dev, int iface, | |
444 | u32 obj, u32 mask, u32 id, u32 mcont) | |
445 | { | |
446 | struct c_can_priv *priv = netdev_priv(dev); | |
447 | ||
448 | mask |= BIT(29); | |
449 | priv->write_reg32(priv, C_CAN_IFACE(MASK1_REG, iface), mask); | |
450 | ||
451 | id |= IF_ARB_MSGVAL; | |
452 | priv->write_reg32(priv, C_CAN_IFACE(ARB1_REG, iface), id); | |
453 | ||
454 | priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), mcont); | |
455 | c_can_object_put(dev, iface, obj, IF_COMM_RCV_SETUP); | |
456 | } | |
457 | ||
458 | static netdev_tx_t c_can_start_xmit(struct sk_buff *skb, | |
459 | struct net_device *dev) | |
460 | { | |
461 | struct can_frame *frame = (struct can_frame *)skb->data; | |
462 | struct c_can_priv *priv = netdev_priv(dev); | |
463 | u32 idx, obj; | |
464 | ||
465 | if (can_dropped_invalid_skb(dev, skb)) | |
466 | return NETDEV_TX_OK; | |
467 | /* | |
468 | * This is not a FIFO. C/D_CAN sends out the buffers | |
469 | * prioritized. The lowest buffer number wins. | |
470 | */ | |
471 | idx = fls(atomic_read(&priv->tx_active)); | |
472 | obj = idx + C_CAN_MSG_OBJ_TX_FIRST; | |
473 | ||
474 | /* If this is the last buffer, stop the xmit queue */ | |
475 | if (idx == C_CAN_MSG_OBJ_TX_NUM - 1) | |
476 | netif_stop_queue(dev); | |
477 | /* | |
478 | * Store the message in the interface so we can call | |
479 | * can_put_echo_skb(). We must do this before we enable | |
480 | * transmit as we might race against do_tx(). | |
481 | */ | |
482 | c_can_setup_tx_object(dev, IF_TX, frame, idx); | |
483 | priv->dlc[idx] = frame->can_dlc; | |
484 | can_put_echo_skb(skb, dev, idx); | |
485 | ||
486 | /* Update the active bits */ | |
487 | atomic_add((1 << idx), &priv->tx_active); | |
488 | /* Start transmission */ | |
489 | c_can_object_put(dev, IF_TX, obj, IF_COMM_TX); | |
490 | ||
491 | return NETDEV_TX_OK; | |
492 | } | |
493 | ||
494 | static int c_can_wait_for_ctrl_init(struct net_device *dev, | |
495 | struct c_can_priv *priv, u32 init) | |
496 | { | |
497 | int retry = 0; | |
498 | ||
499 | while (init != (priv->read_reg(priv, C_CAN_CTRL_REG) & CONTROL_INIT)) { | |
500 | udelay(10); | |
501 | if (retry++ > 1000) { | |
502 | netdev_err(dev, "CCTRL: set CONTROL_INIT failed\n"); | |
503 | return -EIO; | |
504 | } | |
505 | } | |
506 | return 0; | |
507 | } | |
508 | ||
509 | static int c_can_set_bittiming(struct net_device *dev) | |
510 | { | |
511 | unsigned int reg_btr, reg_brpe, ctrl_save; | |
512 | u8 brp, brpe, sjw, tseg1, tseg2; | |
513 | u32 ten_bit_brp; | |
514 | struct c_can_priv *priv = netdev_priv(dev); | |
515 | const struct can_bittiming *bt = &priv->can.bittiming; | |
516 | int res; | |
517 | ||
518 | /* c_can provides a 6-bit brp and 4-bit brpe fields */ | |
519 | ten_bit_brp = bt->brp - 1; | |
520 | brp = ten_bit_brp & BTR_BRP_MASK; | |
521 | brpe = ten_bit_brp >> 6; | |
522 | ||
523 | sjw = bt->sjw - 1; | |
524 | tseg1 = bt->prop_seg + bt->phase_seg1 - 1; | |
525 | tseg2 = bt->phase_seg2 - 1; | |
526 | reg_btr = brp | (sjw << BTR_SJW_SHIFT) | (tseg1 << BTR_TSEG1_SHIFT) | | |
527 | (tseg2 << BTR_TSEG2_SHIFT); | |
528 | reg_brpe = brpe & BRP_EXT_BRPE_MASK; | |
529 | ||
530 | netdev_info(dev, | |
531 | "setting BTR=%04x BRPE=%04x\n", reg_btr, reg_brpe); | |
532 | ||
533 | ctrl_save = priv->read_reg(priv, C_CAN_CTRL_REG); | |
534 | ctrl_save &= ~CONTROL_INIT; | |
535 | priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_CCE | CONTROL_INIT); | |
536 | res = c_can_wait_for_ctrl_init(dev, priv, CONTROL_INIT); | |
537 | if (res) | |
538 | return res; | |
539 | ||
540 | priv->write_reg(priv, C_CAN_BTR_REG, reg_btr); | |
541 | priv->write_reg(priv, C_CAN_BRPEXT_REG, reg_brpe); | |
542 | priv->write_reg(priv, C_CAN_CTRL_REG, ctrl_save); | |
543 | ||
544 | return c_can_wait_for_ctrl_init(dev, priv, 0); | |
545 | } | |
546 | ||
547 | /* | |
548 | * Configure C_CAN message objects for Tx and Rx purposes: | |
549 | * C_CAN provides a total of 32 message objects that can be configured | |
550 | * either for Tx or Rx purposes. Here the first 16 message objects are used as | |
551 | * a reception FIFO. The end of reception FIFO is signified by the EoB bit | |
552 | * being SET. The remaining 16 message objects are kept aside for Tx purposes. | |
553 | * See user guide document for further details on configuring message | |
554 | * objects. | |
555 | */ | |
556 | static void c_can_configure_msg_objects(struct net_device *dev) | |
557 | { | |
558 | int i; | |
559 | ||
560 | /* first invalidate all message objects */ | |
561 | for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_NO_OF_OBJECTS; i++) | |
562 | c_can_inval_msg_object(dev, IF_RX, i); | |
563 | ||
564 | /* setup receive message objects */ | |
565 | for (i = C_CAN_MSG_OBJ_RX_FIRST; i < C_CAN_MSG_OBJ_RX_LAST; i++) | |
566 | c_can_setup_receive_object(dev, IF_RX, i, 0, 0, IF_MCONT_RCV); | |
567 | ||
568 | c_can_setup_receive_object(dev, IF_RX, C_CAN_MSG_OBJ_RX_LAST, 0, 0, | |
569 | IF_MCONT_RCV_EOB); | |
570 | } | |
571 | ||
572 | /* | |
573 | * Configure C_CAN chip: | |
574 | * - enable/disable auto-retransmission | |
575 | * - set operating mode | |
576 | * - configure message objects | |
577 | */ | |
578 | static int c_can_chip_config(struct net_device *dev) | |
579 | { | |
580 | struct c_can_priv *priv = netdev_priv(dev); | |
581 | ||
582 | /* enable automatic retransmission */ | |
583 | priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_ENABLE_AR); | |
584 | ||
585 | if ((priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) && | |
586 | (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)) { | |
587 | /* loopback + silent mode : useful for hot self-test */ | |
588 | priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST); | |
589 | priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK | TEST_SILENT); | |
590 | } else if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { | |
591 | /* loopback mode : useful for self-test function */ | |
592 | priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST); | |
593 | priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK); | |
594 | } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) { | |
595 | /* silent mode : bus-monitoring mode */ | |
596 | priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST); | |
597 | priv->write_reg(priv, C_CAN_TEST_REG, TEST_SILENT); | |
598 | } | |
599 | ||
600 | /* configure message objects */ | |
601 | c_can_configure_msg_objects(dev); | |
602 | ||
603 | /* set a `lec` value so that we can check for updates later */ | |
604 | priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED); | |
605 | ||
606 | /* Clear all internal status */ | |
607 | atomic_set(&priv->tx_active, 0); | |
608 | priv->rxmasked = 0; | |
609 | priv->tx_dir = 0; | |
610 | ||
611 | /* set bittiming params */ | |
612 | return c_can_set_bittiming(dev); | |
613 | } | |
614 | ||
615 | static int c_can_start(struct net_device *dev) | |
616 | { | |
617 | struct c_can_priv *priv = netdev_priv(dev); | |
618 | int err; | |
619 | struct pinctrl *p; | |
620 | ||
621 | /* basic c_can configuration */ | |
622 | err = c_can_chip_config(dev); | |
623 | if (err) | |
624 | return err; | |
625 | ||
626 | /* Setup the command for new messages */ | |
627 | priv->comm_rcv_high = priv->type != BOSCH_D_CAN ? | |
628 | IF_COMM_RCV_LOW : IF_COMM_RCV_HIGH; | |
629 | ||
630 | priv->can.state = CAN_STATE_ERROR_ACTIVE; | |
631 | ||
632 | /* Attempt to use "active" if available else use "default" */ | |
633 | p = pinctrl_get_select(priv->device, "active"); | |
634 | if (!IS_ERR(p)) | |
635 | pinctrl_put(p); | |
636 | else | |
637 | pinctrl_pm_select_default_state(priv->device); | |
638 | ||
639 | return 0; | |
640 | } | |
641 | ||
642 | static void c_can_stop(struct net_device *dev) | |
643 | { | |
644 | struct c_can_priv *priv = netdev_priv(dev); | |
645 | ||
646 | c_can_irq_control(priv, false); | |
647 | ||
648 | /* put ctrl to init on stop to end ongoing transmission */ | |
649 | priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_INIT); | |
650 | ||
651 | /* deactivate pins */ | |
652 | pinctrl_pm_select_sleep_state(dev->dev.parent); | |
653 | priv->can.state = CAN_STATE_STOPPED; | |
654 | } | |
655 | ||
656 | static int c_can_set_mode(struct net_device *dev, enum can_mode mode) | |
657 | { | |
658 | struct c_can_priv *priv = netdev_priv(dev); | |
659 | int err; | |
660 | ||
661 | switch (mode) { | |
662 | case CAN_MODE_START: | |
663 | err = c_can_start(dev); | |
664 | if (err) | |
665 | return err; | |
666 | netif_wake_queue(dev); | |
667 | c_can_irq_control(priv, true); | |
668 | break; | |
669 | default: | |
670 | return -EOPNOTSUPP; | |
671 | } | |
672 | ||
673 | return 0; | |
674 | } | |
675 | ||
676 | static int __c_can_get_berr_counter(const struct net_device *dev, | |
677 | struct can_berr_counter *bec) | |
678 | { | |
679 | unsigned int reg_err_counter; | |
680 | struct c_can_priv *priv = netdev_priv(dev); | |
681 | ||
682 | reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG); | |
683 | bec->rxerr = (reg_err_counter & ERR_CNT_REC_MASK) >> | |
684 | ERR_CNT_REC_SHIFT; | |
685 | bec->txerr = reg_err_counter & ERR_CNT_TEC_MASK; | |
686 | ||
687 | return 0; | |
688 | } | |
689 | ||
690 | static int c_can_get_berr_counter(const struct net_device *dev, | |
691 | struct can_berr_counter *bec) | |
692 | { | |
693 | struct c_can_priv *priv = netdev_priv(dev); | |
694 | int err; | |
695 | ||
696 | c_can_pm_runtime_get_sync(priv); | |
697 | err = __c_can_get_berr_counter(dev, bec); | |
698 | c_can_pm_runtime_put_sync(priv); | |
699 | ||
700 | return err; | |
701 | } | |
702 | ||
703 | static void c_can_do_tx(struct net_device *dev) | |
704 | { | |
705 | struct c_can_priv *priv = netdev_priv(dev); | |
706 | struct net_device_stats *stats = &dev->stats; | |
707 | u32 idx, obj, pkts = 0, bytes = 0, pend, clr; | |
708 | ||
709 | clr = pend = priv->read_reg(priv, C_CAN_INTPND2_REG); | |
710 | ||
711 | while ((idx = ffs(pend))) { | |
712 | idx--; | |
713 | pend &= ~(1 << idx); | |
714 | obj = idx + C_CAN_MSG_OBJ_TX_FIRST; | |
715 | c_can_inval_tx_object(dev, IF_RX, obj); | |
716 | can_get_echo_skb(dev, idx); | |
717 | bytes += priv->dlc[idx]; | |
718 | pkts++; | |
719 | } | |
720 | ||
721 | /* Clear the bits in the tx_active mask */ | |
722 | atomic_sub(clr, &priv->tx_active); | |
723 | ||
724 | if (clr & (1 << (C_CAN_MSG_OBJ_TX_NUM - 1))) | |
725 | netif_wake_queue(dev); | |
726 | ||
727 | if (pkts) { | |
728 | stats->tx_bytes += bytes; | |
729 | stats->tx_packets += pkts; | |
730 | can_led_event(dev, CAN_LED_EVENT_TX); | |
731 | } | |
732 | } | |
733 | ||
734 | /* | |
735 | * If we have a gap in the pending bits, that means we either | |
736 | * raced with the hardware or failed to readout all upper | |
737 | * objects in the last run due to quota limit. | |
738 | */ | |
739 | static u32 c_can_adjust_pending(u32 pend) | |
740 | { | |
741 | u32 weight, lasts; | |
742 | ||
743 | if (pend == RECEIVE_OBJECT_BITS) | |
744 | return pend; | |
745 | ||
746 | /* | |
747 | * If the last set bit is larger than the number of pending | |
748 | * bits we have a gap. | |
749 | */ | |
750 | weight = hweight32(pend); | |
751 | lasts = fls(pend); | |
752 | ||
753 | /* If the bits are linear, nothing to do */ | |
754 | if (lasts == weight) | |
755 | return pend; | |
756 | ||
757 | /* | |
758 | * Find the first set bit after the gap. We walk backwards | |
759 | * from the last set bit. | |
760 | */ | |
761 | for (lasts--; pend & (1 << (lasts - 1)); lasts--); | |
762 | ||
763 | return pend & ~((1 << lasts) - 1); | |
764 | } | |
765 | ||
766 | static inline void c_can_rx_object_get(struct net_device *dev, | |
767 | struct c_can_priv *priv, u32 obj) | |
768 | { | |
769 | c_can_object_get(dev, IF_RX, obj, priv->comm_rcv_high); | |
770 | } | |
771 | ||
772 | static inline void c_can_rx_finalize(struct net_device *dev, | |
773 | struct c_can_priv *priv, u32 obj) | |
774 | { | |
775 | if (priv->type != BOSCH_D_CAN) | |
776 | c_can_object_get(dev, IF_RX, obj, IF_COMM_CLR_NEWDAT); | |
777 | } | |
778 | ||
779 | static int c_can_read_objects(struct net_device *dev, struct c_can_priv *priv, | |
780 | u32 pend, int quota) | |
781 | { | |
782 | u32 pkts = 0, ctrl, obj; | |
783 | ||
784 | while ((obj = ffs(pend)) && quota > 0) { | |
785 | pend &= ~BIT(obj - 1); | |
786 | ||
787 | c_can_rx_object_get(dev, priv, obj); | |
788 | ctrl = priv->read_reg(priv, C_CAN_IFACE(MSGCTRL_REG, IF_RX)); | |
789 | ||
790 | if (ctrl & IF_MCONT_MSGLST) { | |
791 | int n = c_can_handle_lost_msg_obj(dev, IF_RX, obj, ctrl); | |
792 | ||
793 | pkts += n; | |
794 | quota -= n; | |
795 | continue; | |
796 | } | |
797 | ||
798 | /* | |
799 | * This really should not happen, but this covers some | |
800 | * odd HW behaviour. Do not remove that unless you | |
801 | * want to brick your machine. | |
802 | */ | |
803 | if (!(ctrl & IF_MCONT_NEWDAT)) | |
804 | continue; | |
805 | ||
806 | /* read the data from the message object */ | |
807 | c_can_read_msg_object(dev, IF_RX, ctrl); | |
808 | ||
809 | c_can_rx_finalize(dev, priv, obj); | |
810 | ||
811 | pkts++; | |
812 | quota--; | |
813 | } | |
814 | ||
815 | return pkts; | |
816 | } | |
817 | ||
818 | static inline u32 c_can_get_pending(struct c_can_priv *priv) | |
819 | { | |
820 | u32 pend = priv->read_reg(priv, C_CAN_NEWDAT1_REG); | |
821 | ||
822 | return pend; | |
823 | } | |
824 | ||
825 | /* | |
826 | * theory of operation: | |
827 | * | |
828 | * c_can core saves a received CAN message into the first free message | |
829 | * object it finds free (starting with the lowest). Bits NEWDAT and | |
830 | * INTPND are set for this message object indicating that a new message | |
831 | * has arrived. To work-around this issue, we keep two groups of message | |
832 | * objects whose partitioning is defined by C_CAN_MSG_OBJ_RX_SPLIT. | |
833 | * | |
834 | * We clear the newdat bit right away. | |
835 | * | |
836 | * This can result in packet reordering when the readout is slow. | |
837 | */ | |
838 | static int c_can_do_rx_poll(struct net_device *dev, int quota) | |
839 | { | |
840 | struct c_can_priv *priv = netdev_priv(dev); | |
841 | u32 pkts = 0, pend = 0, toread, n; | |
842 | ||
843 | /* | |
844 | * It is faster to read only one 16bit register. This is only possible | |
845 | * for a maximum number of 16 objects. | |
846 | */ | |
847 | BUILD_BUG_ON_MSG(C_CAN_MSG_OBJ_RX_LAST > 16, | |
848 | "Implementation does not support more message objects than 16"); | |
849 | ||
850 | while (quota > 0) { | |
851 | if (!pend) { | |
852 | pend = c_can_get_pending(priv); | |
853 | if (!pend) | |
854 | break; | |
855 | /* | |
856 | * If the pending field has a gap, handle the | |
857 | * bits above the gap first. | |
858 | */ | |
859 | toread = c_can_adjust_pending(pend); | |
860 | } else { | |
861 | toread = pend; | |
862 | } | |
863 | /* Remove the bits from pend */ | |
864 | pend &= ~toread; | |
865 | /* Read the objects */ | |
866 | n = c_can_read_objects(dev, priv, toread, quota); | |
867 | pkts += n; | |
868 | quota -= n; | |
869 | } | |
870 | ||
871 | if (pkts) | |
872 | can_led_event(dev, CAN_LED_EVENT_RX); | |
873 | ||
874 | return pkts; | |
875 | } | |
876 | ||
877 | static int c_can_handle_state_change(struct net_device *dev, | |
878 | enum c_can_bus_error_types error_type) | |
879 | { | |
880 | unsigned int reg_err_counter; | |
881 | unsigned int rx_err_passive; | |
882 | struct c_can_priv *priv = netdev_priv(dev); | |
883 | struct net_device_stats *stats = &dev->stats; | |
884 | struct can_frame *cf; | |
885 | struct sk_buff *skb; | |
886 | struct can_berr_counter bec; | |
887 | ||
888 | switch (error_type) { | |
889 | case C_CAN_ERROR_WARNING: | |
890 | /* error warning state */ | |
891 | priv->can.can_stats.error_warning++; | |
892 | priv->can.state = CAN_STATE_ERROR_WARNING; | |
893 | break; | |
894 | case C_CAN_ERROR_PASSIVE: | |
895 | /* error passive state */ | |
896 | priv->can.can_stats.error_passive++; | |
897 | priv->can.state = CAN_STATE_ERROR_PASSIVE; | |
898 | break; | |
899 | case C_CAN_BUS_OFF: | |
900 | /* bus-off state */ | |
901 | priv->can.state = CAN_STATE_BUS_OFF; | |
902 | priv->can.can_stats.bus_off++; | |
903 | break; | |
904 | default: | |
905 | break; | |
906 | } | |
907 | ||
908 | /* propagate the error condition to the CAN stack */ | |
909 | skb = alloc_can_err_skb(dev, &cf); | |
910 | if (unlikely(!skb)) | |
911 | return 0; | |
912 | ||
913 | __c_can_get_berr_counter(dev, &bec); | |
914 | reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG); | |
915 | rx_err_passive = (reg_err_counter & ERR_CNT_RP_MASK) >> | |
916 | ERR_CNT_RP_SHIFT; | |
917 | ||
918 | switch (error_type) { | |
919 | case C_CAN_ERROR_WARNING: | |
920 | /* error warning state */ | |
921 | cf->can_id |= CAN_ERR_CRTL; | |
922 | cf->data[1] = (bec.txerr > bec.rxerr) ? | |
923 | CAN_ERR_CRTL_TX_WARNING : | |
924 | CAN_ERR_CRTL_RX_WARNING; | |
925 | cf->data[6] = bec.txerr; | |
926 | cf->data[7] = bec.rxerr; | |
927 | ||
928 | break; | |
929 | case C_CAN_ERROR_PASSIVE: | |
930 | /* error passive state */ | |
931 | cf->can_id |= CAN_ERR_CRTL; | |
932 | if (rx_err_passive) | |
933 | cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; | |
934 | if (bec.txerr > 127) | |
935 | cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE; | |
936 | ||
937 | cf->data[6] = bec.txerr; | |
938 | cf->data[7] = bec.rxerr; | |
939 | break; | |
940 | case C_CAN_BUS_OFF: | |
941 | /* bus-off state */ | |
942 | cf->can_id |= CAN_ERR_BUSOFF; | |
943 | can_bus_off(dev); | |
944 | break; | |
945 | default: | |
946 | break; | |
947 | } | |
948 | ||
949 | stats->rx_packets++; | |
950 | stats->rx_bytes += cf->can_dlc; | |
951 | netif_receive_skb(skb); | |
952 | ||
953 | return 1; | |
954 | } | |
955 | ||
956 | static int c_can_handle_bus_err(struct net_device *dev, | |
957 | enum c_can_lec_type lec_type) | |
958 | { | |
959 | struct c_can_priv *priv = netdev_priv(dev); | |
960 | struct net_device_stats *stats = &dev->stats; | |
961 | struct can_frame *cf; | |
962 | struct sk_buff *skb; | |
963 | ||
964 | /* | |
965 | * early exit if no lec update or no error. | |
966 | * no lec update means that no CAN bus event has been detected | |
967 | * since CPU wrote 0x7 value to status reg. | |
968 | */ | |
969 | if (lec_type == LEC_UNUSED || lec_type == LEC_NO_ERROR) | |
970 | return 0; | |
971 | ||
972 | if (!(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) | |
973 | return 0; | |
974 | ||
975 | /* common for all type of bus errors */ | |
976 | priv->can.can_stats.bus_error++; | |
977 | stats->rx_errors++; | |
978 | ||
979 | /* propagate the error condition to the CAN stack */ | |
980 | skb = alloc_can_err_skb(dev, &cf); | |
981 | if (unlikely(!skb)) | |
982 | return 0; | |
983 | ||
984 | /* | |
985 | * check for 'last error code' which tells us the | |
986 | * type of the last error to occur on the CAN bus | |
987 | */ | |
988 | cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; | |
989 | ||
990 | switch (lec_type) { | |
991 | case LEC_STUFF_ERROR: | |
992 | netdev_dbg(dev, "stuff error\n"); | |
993 | cf->data[2] |= CAN_ERR_PROT_STUFF; | |
994 | break; | |
995 | case LEC_FORM_ERROR: | |
996 | netdev_dbg(dev, "form error\n"); | |
997 | cf->data[2] |= CAN_ERR_PROT_FORM; | |
998 | break; | |
999 | case LEC_ACK_ERROR: | |
1000 | netdev_dbg(dev, "ack error\n"); | |
1001 | cf->data[3] = CAN_ERR_PROT_LOC_ACK; | |
1002 | break; | |
1003 | case LEC_BIT1_ERROR: | |
1004 | netdev_dbg(dev, "bit1 error\n"); | |
1005 | cf->data[2] |= CAN_ERR_PROT_BIT1; | |
1006 | break; | |
1007 | case LEC_BIT0_ERROR: | |
1008 | netdev_dbg(dev, "bit0 error\n"); | |
1009 | cf->data[2] |= CAN_ERR_PROT_BIT0; | |
1010 | break; | |
1011 | case LEC_CRC_ERROR: | |
1012 | netdev_dbg(dev, "CRC error\n"); | |
1013 | cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ; | |
1014 | break; | |
1015 | default: | |
1016 | break; | |
1017 | } | |
1018 | ||
1019 | stats->rx_packets++; | |
1020 | stats->rx_bytes += cf->can_dlc; | |
1021 | netif_receive_skb(skb); | |
1022 | return 1; | |
1023 | } | |
1024 | ||
1025 | static int c_can_poll(struct napi_struct *napi, int quota) | |
1026 | { | |
1027 | struct net_device *dev = napi->dev; | |
1028 | struct c_can_priv *priv = netdev_priv(dev); | |
1029 | u16 curr, last = priv->last_status; | |
1030 | int work_done = 0; | |
1031 | ||
1032 | priv->last_status = curr = priv->read_reg(priv, C_CAN_STS_REG); | |
1033 | /* Ack status on C_CAN. D_CAN is self clearing */ | |
1034 | if (priv->type != BOSCH_D_CAN) | |
1035 | priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED); | |
1036 | ||
1037 | /* handle state changes */ | |
1038 | if ((curr & STATUS_EWARN) && (!(last & STATUS_EWARN))) { | |
1039 | netdev_dbg(dev, "entered error warning state\n"); | |
1040 | work_done += c_can_handle_state_change(dev, C_CAN_ERROR_WARNING); | |
1041 | } | |
1042 | ||
1043 | if ((curr & STATUS_EPASS) && (!(last & STATUS_EPASS))) { | |
1044 | netdev_dbg(dev, "entered error passive state\n"); | |
1045 | work_done += c_can_handle_state_change(dev, C_CAN_ERROR_PASSIVE); | |
1046 | } | |
1047 | ||
1048 | if ((curr & STATUS_BOFF) && (!(last & STATUS_BOFF))) { | |
1049 | netdev_dbg(dev, "entered bus off state\n"); | |
1050 | work_done += c_can_handle_state_change(dev, C_CAN_BUS_OFF); | |
1051 | goto end; | |
1052 | } | |
1053 | ||
1054 | /* handle bus recovery events */ | |
1055 | if ((!(curr & STATUS_BOFF)) && (last & STATUS_BOFF)) { | |
1056 | netdev_dbg(dev, "left bus off state\n"); | |
1057 | priv->can.state = CAN_STATE_ERROR_ACTIVE; | |
1058 | } | |
1059 | if ((!(curr & STATUS_EPASS)) && (last & STATUS_EPASS)) { | |
1060 | netdev_dbg(dev, "left error passive state\n"); | |
1061 | priv->can.state = CAN_STATE_ERROR_ACTIVE; | |
1062 | } | |
1063 | ||
1064 | /* handle lec errors on the bus */ | |
1065 | work_done += c_can_handle_bus_err(dev, curr & LEC_MASK); | |
1066 | ||
1067 | /* Handle Tx/Rx events. We do this unconditionally */ | |
1068 | work_done += c_can_do_rx_poll(dev, (quota - work_done)); | |
1069 | c_can_do_tx(dev); | |
1070 | ||
1071 | end: | |
1072 | if (work_done < quota) { | |
1073 | napi_complete_done(napi, work_done); | |
1074 | /* enable all IRQs if we are not in bus off state */ | |
1075 | if (priv->can.state != CAN_STATE_BUS_OFF) | |
1076 | c_can_irq_control(priv, true); | |
1077 | } | |
1078 | ||
1079 | return work_done; | |
1080 | } | |
1081 | ||
1082 | static irqreturn_t c_can_isr(int irq, void *dev_id) | |
1083 | { | |
1084 | struct net_device *dev = (struct net_device *)dev_id; | |
1085 | struct c_can_priv *priv = netdev_priv(dev); | |
1086 | ||
1087 | if (!priv->read_reg(priv, C_CAN_INT_REG)) | |
1088 | return IRQ_NONE; | |
1089 | ||
1090 | /* disable all interrupts and schedule the NAPI */ | |
1091 | c_can_irq_control(priv, false); | |
1092 | napi_schedule(&priv->napi); | |
1093 | ||
1094 | return IRQ_HANDLED; | |
1095 | } | |
1096 | ||
1097 | static int c_can_open(struct net_device *dev) | |
1098 | { | |
1099 | int err; | |
1100 | struct c_can_priv *priv = netdev_priv(dev); | |
1101 | ||
1102 | c_can_pm_runtime_get_sync(priv); | |
1103 | c_can_reset_ram(priv, true); | |
1104 | ||
1105 | /* open the can device */ | |
1106 | err = open_candev(dev); | |
1107 | if (err) { | |
1108 | netdev_err(dev, "failed to open can device\n"); | |
1109 | goto exit_open_fail; | |
1110 | } | |
1111 | ||
1112 | /* register interrupt handler */ | |
1113 | err = request_irq(dev->irq, &c_can_isr, IRQF_SHARED, dev->name, | |
1114 | dev); | |
1115 | if (err < 0) { | |
1116 | netdev_err(dev, "failed to request interrupt\n"); | |
1117 | goto exit_irq_fail; | |
1118 | } | |
1119 | ||
1120 | /* start the c_can controller */ | |
1121 | err = c_can_start(dev); | |
1122 | if (err) | |
1123 | goto exit_start_fail; | |
1124 | ||
1125 | can_led_event(dev, CAN_LED_EVENT_OPEN); | |
1126 | ||
1127 | napi_enable(&priv->napi); | |
1128 | /* enable status change, error and module interrupts */ | |
1129 | c_can_irq_control(priv, true); | |
1130 | netif_start_queue(dev); | |
1131 | ||
1132 | return 0; | |
1133 | ||
1134 | exit_start_fail: | |
1135 | free_irq(dev->irq, dev); | |
1136 | exit_irq_fail: | |
1137 | close_candev(dev); | |
1138 | exit_open_fail: | |
1139 | c_can_reset_ram(priv, false); | |
1140 | c_can_pm_runtime_put_sync(priv); | |
1141 | return err; | |
1142 | } | |
1143 | ||
1144 | static int c_can_close(struct net_device *dev) | |
1145 | { | |
1146 | struct c_can_priv *priv = netdev_priv(dev); | |
1147 | ||
1148 | netif_stop_queue(dev); | |
1149 | napi_disable(&priv->napi); | |
1150 | c_can_stop(dev); | |
1151 | free_irq(dev->irq, dev); | |
1152 | close_candev(dev); | |
1153 | ||
1154 | c_can_reset_ram(priv, false); | |
1155 | c_can_pm_runtime_put_sync(priv); | |
1156 | ||
1157 | can_led_event(dev, CAN_LED_EVENT_STOP); | |
1158 | ||
1159 | return 0; | |
1160 | } | |
1161 | ||
1162 | struct net_device *alloc_c_can_dev(void) | |
1163 | { | |
1164 | struct net_device *dev; | |
1165 | struct c_can_priv *priv; | |
1166 | ||
1167 | dev = alloc_candev(sizeof(struct c_can_priv), C_CAN_MSG_OBJ_TX_NUM); | |
1168 | if (!dev) | |
1169 | return NULL; | |
1170 | ||
1171 | priv = netdev_priv(dev); | |
1172 | netif_napi_add(dev, &priv->napi, c_can_poll, C_CAN_NAPI_WEIGHT); | |
1173 | ||
1174 | priv->dev = dev; | |
1175 | priv->can.bittiming_const = &c_can_bittiming_const; | |
1176 | priv->can.do_set_mode = c_can_set_mode; | |
1177 | priv->can.do_get_berr_counter = c_can_get_berr_counter; | |
1178 | priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | | |
1179 | CAN_CTRLMODE_LISTENONLY | | |
1180 | CAN_CTRLMODE_BERR_REPORTING; | |
1181 | ||
1182 | return dev; | |
1183 | } | |
1184 | EXPORT_SYMBOL_GPL(alloc_c_can_dev); | |
1185 | ||
1186 | #ifdef CONFIG_PM | |
1187 | int c_can_power_down(struct net_device *dev) | |
1188 | { | |
1189 | u32 val; | |
1190 | unsigned long time_out; | |
1191 | struct c_can_priv *priv = netdev_priv(dev); | |
1192 | ||
1193 | if (!(dev->flags & IFF_UP)) | |
1194 | return 0; | |
1195 | ||
1196 | WARN_ON(priv->type != BOSCH_D_CAN); | |
1197 | ||
1198 | /* set PDR value so the device goes to power down mode */ | |
1199 | val = priv->read_reg(priv, C_CAN_CTRL_EX_REG); | |
1200 | val |= CONTROL_EX_PDR; | |
1201 | priv->write_reg(priv, C_CAN_CTRL_EX_REG, val); | |
1202 | ||
1203 | /* Wait for the PDA bit to get set */ | |
1204 | time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS); | |
1205 | while (!(priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) && | |
1206 | time_after(time_out, jiffies)) | |
1207 | cpu_relax(); | |
1208 | ||
1209 | if (time_after(jiffies, time_out)) | |
1210 | return -ETIMEDOUT; | |
1211 | ||
1212 | c_can_stop(dev); | |
1213 | ||
1214 | c_can_reset_ram(priv, false); | |
1215 | c_can_pm_runtime_put_sync(priv); | |
1216 | ||
1217 | return 0; | |
1218 | } | |
1219 | EXPORT_SYMBOL_GPL(c_can_power_down); | |
1220 | ||
1221 | int c_can_power_up(struct net_device *dev) | |
1222 | { | |
1223 | u32 val; | |
1224 | unsigned long time_out; | |
1225 | struct c_can_priv *priv = netdev_priv(dev); | |
1226 | int ret; | |
1227 | ||
1228 | if (!(dev->flags & IFF_UP)) | |
1229 | return 0; | |
1230 | ||
1231 | WARN_ON(priv->type != BOSCH_D_CAN); | |
1232 | ||
1233 | c_can_pm_runtime_get_sync(priv); | |
1234 | c_can_reset_ram(priv, true); | |
1235 | ||
1236 | /* Clear PDR and INIT bits */ | |
1237 | val = priv->read_reg(priv, C_CAN_CTRL_EX_REG); | |
1238 | val &= ~CONTROL_EX_PDR; | |
1239 | priv->write_reg(priv, C_CAN_CTRL_EX_REG, val); | |
1240 | val = priv->read_reg(priv, C_CAN_CTRL_REG); | |
1241 | val &= ~CONTROL_INIT; | |
1242 | priv->write_reg(priv, C_CAN_CTRL_REG, val); | |
1243 | ||
1244 | /* Wait for the PDA bit to get clear */ | |
1245 | time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS); | |
1246 | while ((priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) && | |
1247 | time_after(time_out, jiffies)) | |
1248 | cpu_relax(); | |
1249 | ||
1250 | if (time_after(jiffies, time_out)) | |
1251 | return -ETIMEDOUT; | |
1252 | ||
1253 | ret = c_can_start(dev); | |
1254 | if (!ret) | |
1255 | c_can_irq_control(priv, true); | |
1256 | ||
1257 | return ret; | |
1258 | } | |
1259 | EXPORT_SYMBOL_GPL(c_can_power_up); | |
1260 | #endif | |
1261 | ||
1262 | void free_c_can_dev(struct net_device *dev) | |
1263 | { | |
1264 | struct c_can_priv *priv = netdev_priv(dev); | |
1265 | ||
1266 | netif_napi_del(&priv->napi); | |
1267 | free_candev(dev); | |
1268 | } | |
1269 | EXPORT_SYMBOL_GPL(free_c_can_dev); | |
1270 | ||
1271 | static const struct net_device_ops c_can_netdev_ops = { | |
1272 | .ndo_open = c_can_open, | |
1273 | .ndo_stop = c_can_close, | |
1274 | .ndo_start_xmit = c_can_start_xmit, | |
1275 | .ndo_change_mtu = can_change_mtu, | |
1276 | }; | |
1277 | ||
1278 | int register_c_can_dev(struct net_device *dev) | |
1279 | { | |
1280 | struct c_can_priv *priv = netdev_priv(dev); | |
1281 | int err; | |
1282 | ||
1283 | /* Deactivate pins to prevent DRA7 DCAN IP from being | |
1284 | * stuck in transition when module is disabled. | |
1285 | * Pins are activated in c_can_start() and deactivated | |
1286 | * in c_can_stop() | |
1287 | */ | |
1288 | pinctrl_pm_select_sleep_state(dev->dev.parent); | |
1289 | ||
1290 | c_can_pm_runtime_enable(priv); | |
1291 | ||
1292 | dev->flags |= IFF_ECHO; /* we support local echo */ | |
1293 | dev->netdev_ops = &c_can_netdev_ops; | |
1294 | ||
1295 | err = register_candev(dev); | |
1296 | if (err) | |
1297 | c_can_pm_runtime_disable(priv); | |
1298 | else | |
1299 | devm_can_led_init(dev); | |
1300 | ||
1301 | return err; | |
1302 | } | |
1303 | EXPORT_SYMBOL_GPL(register_c_can_dev); | |
1304 | ||
1305 | void unregister_c_can_dev(struct net_device *dev) | |
1306 | { | |
1307 | struct c_can_priv *priv = netdev_priv(dev); | |
1308 | ||
1309 | unregister_candev(dev); | |
1310 | ||
1311 | c_can_pm_runtime_disable(priv); | |
1312 | } | |
1313 | EXPORT_SYMBOL_GPL(unregister_c_can_dev); | |
1314 | ||
1315 | MODULE_AUTHOR("Bhupesh Sharma <bhupesh.sharma@st.com>"); | |
1316 | MODULE_LICENSE("GPL v2"); | |
1317 | MODULE_DESCRIPTION("CAN bus driver for Bosch C_CAN controller"); |