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1 | // SPDX-License-Identifier: GPL-2.0 | |
2 | /* Copyright 2019-2021 NXP Semiconductors | |
3 | * | |
4 | * This is an umbrella module for all network switches that are | |
5 | * register-compatible with Ocelot and that perform I/O to their host CPU | |
6 | * through an NPI (Node Processor Interface) Ethernet port. | |
7 | */ | |
8 | #include <uapi/linux/if_bridge.h> | |
9 | #include <soc/mscc/ocelot_vcap.h> | |
10 | #include <soc/mscc/ocelot_qsys.h> | |
11 | #include <soc/mscc/ocelot_sys.h> | |
12 | #include <soc/mscc/ocelot_dev.h> | |
13 | #include <soc/mscc/ocelot_ana.h> | |
14 | #include <soc/mscc/ocelot_ptp.h> | |
15 | #include <soc/mscc/ocelot.h> | |
16 | #include <linux/dsa/8021q.h> | |
17 | #include <linux/dsa/ocelot.h> | |
18 | #include <linux/platform_device.h> | |
19 | #include <linux/ptp_classify.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/of_net.h> | |
22 | #include <linux/pci.h> | |
23 | #include <linux/of.h> | |
24 | #include <linux/pcs-lynx.h> | |
25 | #include <net/pkt_sched.h> | |
26 | #include <net/dsa.h> | |
27 | #include "felix.h" | |
28 | ||
29 | static int felix_tag_8021q_rxvlan_add(struct felix *felix, int port, u16 vid, | |
30 | bool pvid, bool untagged) | |
31 | { | |
32 | struct ocelot_vcap_filter *outer_tagging_rule; | |
33 | struct ocelot *ocelot = &felix->ocelot; | |
34 | struct dsa_switch *ds = felix->ds; | |
35 | int key_length, upstream, err; | |
36 | ||
37 | /* We don't need to install the rxvlan into the other ports' filtering | |
38 | * tables, because we're just pushing the rxvlan when sending towards | |
39 | * the CPU | |
40 | */ | |
41 | if (!pvid) | |
42 | return 0; | |
43 | ||
44 | key_length = ocelot->vcap[VCAP_ES0].keys[VCAP_ES0_IGR_PORT].length; | |
45 | upstream = dsa_upstream_port(ds, port); | |
46 | ||
47 | outer_tagging_rule = kzalloc(sizeof(struct ocelot_vcap_filter), | |
48 | GFP_KERNEL); | |
49 | if (!outer_tagging_rule) | |
50 | return -ENOMEM; | |
51 | ||
52 | outer_tagging_rule->key_type = OCELOT_VCAP_KEY_ANY; | |
53 | outer_tagging_rule->prio = 1; | |
54 | outer_tagging_rule->id.cookie = port; | |
55 | outer_tagging_rule->id.tc_offload = false; | |
56 | outer_tagging_rule->block_id = VCAP_ES0; | |
57 | outer_tagging_rule->type = OCELOT_VCAP_FILTER_OFFLOAD; | |
58 | outer_tagging_rule->lookup = 0; | |
59 | outer_tagging_rule->ingress_port.value = port; | |
60 | outer_tagging_rule->ingress_port.mask = GENMASK(key_length - 1, 0); | |
61 | outer_tagging_rule->egress_port.value = upstream; | |
62 | outer_tagging_rule->egress_port.mask = GENMASK(key_length - 1, 0); | |
63 | outer_tagging_rule->action.push_outer_tag = OCELOT_ES0_TAG; | |
64 | outer_tagging_rule->action.tag_a_tpid_sel = OCELOT_TAG_TPID_SEL_8021AD; | |
65 | outer_tagging_rule->action.tag_a_vid_sel = 1; | |
66 | outer_tagging_rule->action.vid_a_val = vid; | |
67 | ||
68 | err = ocelot_vcap_filter_add(ocelot, outer_tagging_rule, NULL); | |
69 | if (err) | |
70 | kfree(outer_tagging_rule); | |
71 | ||
72 | return err; | |
73 | } | |
74 | ||
75 | static int felix_tag_8021q_txvlan_add(struct felix *felix, int port, u16 vid, | |
76 | bool pvid, bool untagged) | |
77 | { | |
78 | struct ocelot_vcap_filter *untagging_rule, *redirect_rule; | |
79 | struct ocelot *ocelot = &felix->ocelot; | |
80 | struct dsa_switch *ds = felix->ds; | |
81 | int upstream, err; | |
82 | ||
83 | /* tag_8021q.c assumes we are implementing this via port VLAN | |
84 | * membership, which we aren't. So we don't need to add any VCAP filter | |
85 | * for the CPU port. | |
86 | */ | |
87 | if (ocelot->ports[port]->is_dsa_8021q_cpu) | |
88 | return 0; | |
89 | ||
90 | untagging_rule = kzalloc(sizeof(struct ocelot_vcap_filter), GFP_KERNEL); | |
91 | if (!untagging_rule) | |
92 | return -ENOMEM; | |
93 | ||
94 | redirect_rule = kzalloc(sizeof(struct ocelot_vcap_filter), GFP_KERNEL); | |
95 | if (!redirect_rule) { | |
96 | kfree(untagging_rule); | |
97 | return -ENOMEM; | |
98 | } | |
99 | ||
100 | upstream = dsa_upstream_port(ds, port); | |
101 | ||
102 | untagging_rule->key_type = OCELOT_VCAP_KEY_ANY; | |
103 | untagging_rule->ingress_port_mask = BIT(upstream); | |
104 | untagging_rule->vlan.vid.value = vid; | |
105 | untagging_rule->vlan.vid.mask = VLAN_VID_MASK; | |
106 | untagging_rule->prio = 1; | |
107 | untagging_rule->id.cookie = port; | |
108 | untagging_rule->id.tc_offload = false; | |
109 | untagging_rule->block_id = VCAP_IS1; | |
110 | untagging_rule->type = OCELOT_VCAP_FILTER_OFFLOAD; | |
111 | untagging_rule->lookup = 0; | |
112 | untagging_rule->action.vlan_pop_cnt_ena = true; | |
113 | untagging_rule->action.vlan_pop_cnt = 1; | |
114 | untagging_rule->action.pag_override_mask = 0xff; | |
115 | untagging_rule->action.pag_val = port; | |
116 | ||
117 | err = ocelot_vcap_filter_add(ocelot, untagging_rule, NULL); | |
118 | if (err) { | |
119 | kfree(untagging_rule); | |
120 | kfree(redirect_rule); | |
121 | return err; | |
122 | } | |
123 | ||
124 | redirect_rule->key_type = OCELOT_VCAP_KEY_ANY; | |
125 | redirect_rule->ingress_port_mask = BIT(upstream); | |
126 | redirect_rule->pag = port; | |
127 | redirect_rule->prio = 1; | |
128 | redirect_rule->id.cookie = port; | |
129 | redirect_rule->id.tc_offload = false; | |
130 | redirect_rule->block_id = VCAP_IS2; | |
131 | redirect_rule->type = OCELOT_VCAP_FILTER_OFFLOAD; | |
132 | redirect_rule->lookup = 0; | |
133 | redirect_rule->action.mask_mode = OCELOT_MASK_MODE_REDIRECT; | |
134 | redirect_rule->action.port_mask = BIT(port); | |
135 | ||
136 | err = ocelot_vcap_filter_add(ocelot, redirect_rule, NULL); | |
137 | if (err) { | |
138 | ocelot_vcap_filter_del(ocelot, untagging_rule); | |
139 | kfree(redirect_rule); | |
140 | return err; | |
141 | } | |
142 | ||
143 | return 0; | |
144 | } | |
145 | ||
146 | static int felix_tag_8021q_vlan_add(struct dsa_switch *ds, int port, u16 vid, | |
147 | u16 flags) | |
148 | { | |
149 | bool untagged = flags & BRIDGE_VLAN_INFO_UNTAGGED; | |
150 | bool pvid = flags & BRIDGE_VLAN_INFO_PVID; | |
151 | struct ocelot *ocelot = ds->priv; | |
152 | ||
153 | if (vid_is_dsa_8021q_rxvlan(vid)) | |
154 | return felix_tag_8021q_rxvlan_add(ocelot_to_felix(ocelot), | |
155 | port, vid, pvid, untagged); | |
156 | ||
157 | if (vid_is_dsa_8021q_txvlan(vid)) | |
158 | return felix_tag_8021q_txvlan_add(ocelot_to_felix(ocelot), | |
159 | port, vid, pvid, untagged); | |
160 | ||
161 | return 0; | |
162 | } | |
163 | ||
164 | static int felix_tag_8021q_rxvlan_del(struct felix *felix, int port, u16 vid) | |
165 | { | |
166 | struct ocelot_vcap_filter *outer_tagging_rule; | |
167 | struct ocelot_vcap_block *block_vcap_es0; | |
168 | struct ocelot *ocelot = &felix->ocelot; | |
169 | ||
170 | block_vcap_es0 = &ocelot->block[VCAP_ES0]; | |
171 | ||
172 | outer_tagging_rule = ocelot_vcap_block_find_filter_by_id(block_vcap_es0, | |
173 | port, false); | |
174 | /* In rxvlan_add, we had the "if (!pvid) return 0" logic to avoid | |
175 | * installing outer tagging ES0 rules where they weren't needed. | |
176 | * But in rxvlan_del, the API doesn't give us the "flags" anymore, | |
177 | * so that forces us to be slightly sloppy here, and just assume that | |
178 | * if we didn't find an outer_tagging_rule it means that there was | |
179 | * none in the first place, i.e. rxvlan_del is called on a non-pvid | |
180 | * port. This is most probably true though. | |
181 | */ | |
182 | if (!outer_tagging_rule) | |
183 | return 0; | |
184 | ||
185 | return ocelot_vcap_filter_del(ocelot, outer_tagging_rule); | |
186 | } | |
187 | ||
188 | static int felix_tag_8021q_txvlan_del(struct felix *felix, int port, u16 vid) | |
189 | { | |
190 | struct ocelot_vcap_filter *untagging_rule, *redirect_rule; | |
191 | struct ocelot_vcap_block *block_vcap_is1; | |
192 | struct ocelot_vcap_block *block_vcap_is2; | |
193 | struct ocelot *ocelot = &felix->ocelot; | |
194 | int err; | |
195 | ||
196 | if (ocelot->ports[port]->is_dsa_8021q_cpu) | |
197 | return 0; | |
198 | ||
199 | block_vcap_is1 = &ocelot->block[VCAP_IS1]; | |
200 | block_vcap_is2 = &ocelot->block[VCAP_IS2]; | |
201 | ||
202 | untagging_rule = ocelot_vcap_block_find_filter_by_id(block_vcap_is1, | |
203 | port, false); | |
204 | if (!untagging_rule) | |
205 | return 0; | |
206 | ||
207 | err = ocelot_vcap_filter_del(ocelot, untagging_rule); | |
208 | if (err) | |
209 | return err; | |
210 | ||
211 | redirect_rule = ocelot_vcap_block_find_filter_by_id(block_vcap_is2, | |
212 | port, false); | |
213 | if (!redirect_rule) | |
214 | return 0; | |
215 | ||
216 | return ocelot_vcap_filter_del(ocelot, redirect_rule); | |
217 | } | |
218 | ||
219 | static int felix_tag_8021q_vlan_del(struct dsa_switch *ds, int port, u16 vid) | |
220 | { | |
221 | struct ocelot *ocelot = ds->priv; | |
222 | ||
223 | if (vid_is_dsa_8021q_rxvlan(vid)) | |
224 | return felix_tag_8021q_rxvlan_del(ocelot_to_felix(ocelot), | |
225 | port, vid); | |
226 | ||
227 | if (vid_is_dsa_8021q_txvlan(vid)) | |
228 | return felix_tag_8021q_txvlan_del(ocelot_to_felix(ocelot), | |
229 | port, vid); | |
230 | ||
231 | return 0; | |
232 | } | |
233 | ||
234 | static const struct dsa_8021q_ops felix_tag_8021q_ops = { | |
235 | .vlan_add = felix_tag_8021q_vlan_add, | |
236 | .vlan_del = felix_tag_8021q_vlan_del, | |
237 | }; | |
238 | ||
239 | /* Alternatively to using the NPI functionality, that same hardware MAC | |
240 | * connected internally to the enetc or fman DSA master can be configured to | |
241 | * use the software-defined tag_8021q frame format. As far as the hardware is | |
242 | * concerned, it thinks it is a "dumb switch" - the queues of the CPU port | |
243 | * module are now disconnected from it, but can still be accessed through | |
244 | * register-based MMIO. | |
245 | */ | |
246 | static void felix_8021q_cpu_port_init(struct ocelot *ocelot, int port) | |
247 | { | |
248 | ocelot->ports[port]->is_dsa_8021q_cpu = true; | |
249 | ocelot->npi = -1; | |
250 | ||
251 | /* Overwrite PGID_CPU with the non-tagging port */ | |
252 | ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, PGID_CPU); | |
253 | ||
254 | ocelot_apply_bridge_fwd_mask(ocelot); | |
255 | } | |
256 | ||
257 | static void felix_8021q_cpu_port_deinit(struct ocelot *ocelot, int port) | |
258 | { | |
259 | ocelot->ports[port]->is_dsa_8021q_cpu = false; | |
260 | ||
261 | /* Restore PGID_CPU */ | |
262 | ocelot_write_rix(ocelot, BIT(ocelot->num_phys_ports), ANA_PGID_PGID, | |
263 | PGID_CPU); | |
264 | ||
265 | ocelot_apply_bridge_fwd_mask(ocelot); | |
266 | } | |
267 | ||
268 | /* Set up a VCAP IS2 rule for delivering PTP frames to the CPU port module. | |
269 | * If the quirk_no_xtr_irq is in place, then also copy those PTP frames to the | |
270 | * tag_8021q CPU port. | |
271 | */ | |
272 | static int felix_setup_mmio_filtering(struct felix *felix) | |
273 | { | |
274 | unsigned long user_ports = 0, cpu_ports = 0; | |
275 | struct ocelot_vcap_filter *redirect_rule; | |
276 | struct ocelot_vcap_filter *tagging_rule; | |
277 | struct ocelot *ocelot = &felix->ocelot; | |
278 | struct dsa_switch *ds = felix->ds; | |
279 | int port, ret; | |
280 | ||
281 | tagging_rule = kzalloc(sizeof(struct ocelot_vcap_filter), GFP_KERNEL); | |
282 | if (!tagging_rule) | |
283 | return -ENOMEM; | |
284 | ||
285 | redirect_rule = kzalloc(sizeof(struct ocelot_vcap_filter), GFP_KERNEL); | |
286 | if (!redirect_rule) { | |
287 | kfree(tagging_rule); | |
288 | return -ENOMEM; | |
289 | } | |
290 | ||
291 | for (port = 0; port < ocelot->num_phys_ports; port++) { | |
292 | if (dsa_is_user_port(ds, port)) | |
293 | user_ports |= BIT(port); | |
294 | if (dsa_is_cpu_port(ds, port)) | |
295 | cpu_ports |= BIT(port); | |
296 | } | |
297 | ||
298 | tagging_rule->key_type = OCELOT_VCAP_KEY_ETYPE; | |
299 | *(__be16 *)tagging_rule->key.etype.etype.value = htons(ETH_P_1588); | |
300 | *(__be16 *)tagging_rule->key.etype.etype.mask = htons(0xffff); | |
301 | tagging_rule->ingress_port_mask = user_ports; | |
302 | tagging_rule->prio = 1; | |
303 | tagging_rule->id.cookie = ocelot->num_phys_ports; | |
304 | tagging_rule->id.tc_offload = false; | |
305 | tagging_rule->block_id = VCAP_IS1; | |
306 | tagging_rule->type = OCELOT_VCAP_FILTER_OFFLOAD; | |
307 | tagging_rule->lookup = 0; | |
308 | tagging_rule->action.pag_override_mask = 0xff; | |
309 | tagging_rule->action.pag_val = ocelot->num_phys_ports; | |
310 | ||
311 | ret = ocelot_vcap_filter_add(ocelot, tagging_rule, NULL); | |
312 | if (ret) { | |
313 | kfree(tagging_rule); | |
314 | kfree(redirect_rule); | |
315 | return ret; | |
316 | } | |
317 | ||
318 | redirect_rule->key_type = OCELOT_VCAP_KEY_ANY; | |
319 | redirect_rule->ingress_port_mask = user_ports; | |
320 | redirect_rule->pag = ocelot->num_phys_ports; | |
321 | redirect_rule->prio = 1; | |
322 | redirect_rule->id.cookie = ocelot->num_phys_ports; | |
323 | redirect_rule->id.tc_offload = false; | |
324 | redirect_rule->block_id = VCAP_IS2; | |
325 | redirect_rule->type = OCELOT_VCAP_FILTER_OFFLOAD; | |
326 | redirect_rule->lookup = 0; | |
327 | redirect_rule->action.cpu_copy_ena = true; | |
328 | if (felix->info->quirk_no_xtr_irq) { | |
329 | /* Redirect to the tag_8021q CPU but also copy PTP packets to | |
330 | * the CPU port module | |
331 | */ | |
332 | redirect_rule->action.mask_mode = OCELOT_MASK_MODE_REDIRECT; | |
333 | redirect_rule->action.port_mask = cpu_ports; | |
334 | } else { | |
335 | /* Trap PTP packets only to the CPU port module (which is | |
336 | * redirected to the NPI port) | |
337 | */ | |
338 | redirect_rule->action.mask_mode = OCELOT_MASK_MODE_PERMIT_DENY; | |
339 | redirect_rule->action.port_mask = 0; | |
340 | } | |
341 | ||
342 | ret = ocelot_vcap_filter_add(ocelot, redirect_rule, NULL); | |
343 | if (ret) { | |
344 | ocelot_vcap_filter_del(ocelot, tagging_rule); | |
345 | kfree(redirect_rule); | |
346 | return ret; | |
347 | } | |
348 | ||
349 | /* The ownership of the CPU port module's queues might have just been | |
350 | * transferred to the tag_8021q tagger from the NPI-based tagger. | |
351 | * So there might still be all sorts of crap in the queues. On the | |
352 | * other hand, the MMIO-based matching of PTP frames is very brittle, | |
353 | * so we need to be careful that there are no extra frames to be | |
354 | * dequeued over MMIO, since we would never know to discard them. | |
355 | */ | |
356 | ocelot_drain_cpu_queue(ocelot, 0); | |
357 | ||
358 | return 0; | |
359 | } | |
360 | ||
361 | static int felix_teardown_mmio_filtering(struct felix *felix) | |
362 | { | |
363 | struct ocelot_vcap_filter *tagging_rule, *redirect_rule; | |
364 | struct ocelot_vcap_block *block_vcap_is1; | |
365 | struct ocelot_vcap_block *block_vcap_is2; | |
366 | struct ocelot *ocelot = &felix->ocelot; | |
367 | int err; | |
368 | ||
369 | block_vcap_is1 = &ocelot->block[VCAP_IS1]; | |
370 | block_vcap_is2 = &ocelot->block[VCAP_IS2]; | |
371 | ||
372 | tagging_rule = ocelot_vcap_block_find_filter_by_id(block_vcap_is1, | |
373 | ocelot->num_phys_ports, | |
374 | false); | |
375 | if (!tagging_rule) | |
376 | return -ENOENT; | |
377 | ||
378 | err = ocelot_vcap_filter_del(ocelot, tagging_rule); | |
379 | if (err) | |
380 | return err; | |
381 | ||
382 | redirect_rule = ocelot_vcap_block_find_filter_by_id(block_vcap_is2, | |
383 | ocelot->num_phys_ports, | |
384 | false); | |
385 | if (!redirect_rule) | |
386 | return -ENOENT; | |
387 | ||
388 | return ocelot_vcap_filter_del(ocelot, redirect_rule); | |
389 | } | |
390 | ||
391 | static int felix_setup_tag_8021q(struct dsa_switch *ds, int cpu) | |
392 | { | |
393 | struct ocelot *ocelot = ds->priv; | |
394 | struct felix *felix = ocelot_to_felix(ocelot); | |
395 | unsigned long cpu_flood; | |
396 | int port, err; | |
397 | ||
398 | felix_8021q_cpu_port_init(ocelot, cpu); | |
399 | ||
400 | for (port = 0; port < ds->num_ports; port++) { | |
401 | if (dsa_is_unused_port(ds, port)) | |
402 | continue; | |
403 | ||
404 | /* This overwrites ocelot_init(): | |
405 | * Do not forward BPDU frames to the CPU port module, | |
406 | * for 2 reasons: | |
407 | * - When these packets are injected from the tag_8021q | |
408 | * CPU port, we want them to go out, not loop back | |
409 | * into the system. | |
410 | * - STP traffic ingressing on a user port should go to | |
411 | * the tag_8021q CPU port, not to the hardware CPU | |
412 | * port module. | |
413 | */ | |
414 | ocelot_write_gix(ocelot, | |
415 | ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0), | |
416 | ANA_PORT_CPU_FWD_BPDU_CFG, port); | |
417 | } | |
418 | ||
419 | /* In tag_8021q mode, the CPU port module is unused, except for PTP | |
420 | * frames. So we want to disable flooding of any kind to the CPU port | |
421 | * module, since packets going there will end in a black hole. | |
422 | */ | |
423 | cpu_flood = ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)); | |
424 | ocelot_rmw_rix(ocelot, 0, cpu_flood, ANA_PGID_PGID, PGID_UC); | |
425 | ocelot_rmw_rix(ocelot, 0, cpu_flood, ANA_PGID_PGID, PGID_MC); | |
426 | ocelot_rmw_rix(ocelot, 0, cpu_flood, ANA_PGID_PGID, PGID_BC); | |
427 | ||
428 | err = dsa_tag_8021q_register(ds, &felix_tag_8021q_ops, | |
429 | htons(ETH_P_8021AD)); | |
430 | if (err) | |
431 | return err; | |
432 | ||
433 | err = dsa_8021q_setup(ds, true); | |
434 | if (err) | |
435 | goto out_tag_8021q_unregister; | |
436 | ||
437 | err = felix_setup_mmio_filtering(felix); | |
438 | if (err) | |
439 | goto out_teardown_dsa_8021q; | |
440 | ||
441 | return 0; | |
442 | ||
443 | out_teardown_dsa_8021q: | |
444 | dsa_8021q_setup(ds, false); | |
445 | out_tag_8021q_unregister: | |
446 | dsa_tag_8021q_unregister(ds); | |
447 | return err; | |
448 | } | |
449 | ||
450 | static void felix_teardown_tag_8021q(struct dsa_switch *ds, int cpu) | |
451 | { | |
452 | struct ocelot *ocelot = ds->priv; | |
453 | struct felix *felix = ocelot_to_felix(ocelot); | |
454 | int err, port; | |
455 | ||
456 | err = felix_teardown_mmio_filtering(felix); | |
457 | if (err) | |
458 | dev_err(ds->dev, "felix_teardown_mmio_filtering returned %d", | |
459 | err); | |
460 | ||
461 | err = dsa_8021q_setup(ds, false); | |
462 | if (err) | |
463 | dev_err(ds->dev, "dsa_8021q_setup returned %d", err); | |
464 | ||
465 | dsa_tag_8021q_unregister(ds); | |
466 | ||
467 | for (port = 0; port < ds->num_ports; port++) { | |
468 | if (dsa_is_unused_port(ds, port)) | |
469 | continue; | |
470 | ||
471 | /* Restore the logic from ocelot_init: | |
472 | * do not forward BPDU frames to the front ports. | |
473 | */ | |
474 | ocelot_write_gix(ocelot, | |
475 | ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff), | |
476 | ANA_PORT_CPU_FWD_BPDU_CFG, | |
477 | port); | |
478 | } | |
479 | ||
480 | felix_8021q_cpu_port_deinit(ocelot, cpu); | |
481 | } | |
482 | ||
483 | /* The CPU port module is connected to the Node Processor Interface (NPI). This | |
484 | * is the mode through which frames can be injected from and extracted to an | |
485 | * external CPU, over Ethernet. In NXP SoCs, the "external CPU" is the ARM CPU | |
486 | * running Linux, and this forms a DSA setup together with the enetc or fman | |
487 | * DSA master. | |
488 | */ | |
489 | static void felix_npi_port_init(struct ocelot *ocelot, int port) | |
490 | { | |
491 | ocelot->npi = port; | |
492 | ||
493 | ocelot_write(ocelot, QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK_M | | |
494 | QSYS_EXT_CPU_CFG_EXT_CPU_PORT(port), | |
495 | QSYS_EXT_CPU_CFG); | |
496 | ||
497 | /* NPI port Injection/Extraction configuration */ | |
498 | ocelot_fields_write(ocelot, port, SYS_PORT_MODE_INCL_XTR_HDR, | |
499 | ocelot->npi_xtr_prefix); | |
500 | ocelot_fields_write(ocelot, port, SYS_PORT_MODE_INCL_INJ_HDR, | |
501 | ocelot->npi_inj_prefix); | |
502 | ||
503 | /* Disable transmission of pause frames */ | |
504 | ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 0); | |
505 | } | |
506 | ||
507 | static void felix_npi_port_deinit(struct ocelot *ocelot, int port) | |
508 | { | |
509 | /* Restore hardware defaults */ | |
510 | int unused_port = ocelot->num_phys_ports + 2; | |
511 | ||
512 | ocelot->npi = -1; | |
513 | ||
514 | ocelot_write(ocelot, QSYS_EXT_CPU_CFG_EXT_CPU_PORT(unused_port), | |
515 | QSYS_EXT_CPU_CFG); | |
516 | ||
517 | ocelot_fields_write(ocelot, port, SYS_PORT_MODE_INCL_XTR_HDR, | |
518 | OCELOT_TAG_PREFIX_DISABLED); | |
519 | ocelot_fields_write(ocelot, port, SYS_PORT_MODE_INCL_INJ_HDR, | |
520 | OCELOT_TAG_PREFIX_DISABLED); | |
521 | ||
522 | /* Enable transmission of pause frames */ | |
523 | ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 1); | |
524 | } | |
525 | ||
526 | static int felix_setup_tag_npi(struct dsa_switch *ds, int cpu) | |
527 | { | |
528 | struct ocelot *ocelot = ds->priv; | |
529 | unsigned long cpu_flood; | |
530 | ||
531 | felix_npi_port_init(ocelot, cpu); | |
532 | ||
533 | /* Include the CPU port module (and indirectly, the NPI port) | |
534 | * in the forwarding mask for unknown unicast - the hardware | |
535 | * default value for ANA_FLOODING_FLD_UNICAST excludes | |
536 | * BIT(ocelot->num_phys_ports), and so does ocelot_init, | |
537 | * since Ocelot relies on whitelisting MAC addresses towards | |
538 | * PGID_CPU. | |
539 | * We do this because DSA does not yet perform RX filtering, | |
540 | * and the NPI port does not perform source address learning, | |
541 | * so traffic sent to Linux is effectively unknown from the | |
542 | * switch's perspective. | |
543 | */ | |
544 | cpu_flood = ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)); | |
545 | ocelot_rmw_rix(ocelot, cpu_flood, cpu_flood, ANA_PGID_PGID, PGID_UC); | |
546 | ocelot_rmw_rix(ocelot, cpu_flood, cpu_flood, ANA_PGID_PGID, PGID_MC); | |
547 | ocelot_rmw_rix(ocelot, cpu_flood, cpu_flood, ANA_PGID_PGID, PGID_BC); | |
548 | ||
549 | return 0; | |
550 | } | |
551 | ||
552 | static void felix_teardown_tag_npi(struct dsa_switch *ds, int cpu) | |
553 | { | |
554 | struct ocelot *ocelot = ds->priv; | |
555 | ||
556 | felix_npi_port_deinit(ocelot, cpu); | |
557 | } | |
558 | ||
559 | static int felix_set_tag_protocol(struct dsa_switch *ds, int cpu, | |
560 | enum dsa_tag_protocol proto) | |
561 | { | |
562 | int err; | |
563 | ||
564 | switch (proto) { | |
565 | case DSA_TAG_PROTO_SEVILLE: | |
566 | case DSA_TAG_PROTO_OCELOT: | |
567 | err = felix_setup_tag_npi(ds, cpu); | |
568 | break; | |
569 | case DSA_TAG_PROTO_OCELOT_8021Q: | |
570 | err = felix_setup_tag_8021q(ds, cpu); | |
571 | break; | |
572 | default: | |
573 | err = -EPROTONOSUPPORT; | |
574 | } | |
575 | ||
576 | return err; | |
577 | } | |
578 | ||
579 | static void felix_del_tag_protocol(struct dsa_switch *ds, int cpu, | |
580 | enum dsa_tag_protocol proto) | |
581 | { | |
582 | switch (proto) { | |
583 | case DSA_TAG_PROTO_SEVILLE: | |
584 | case DSA_TAG_PROTO_OCELOT: | |
585 | felix_teardown_tag_npi(ds, cpu); | |
586 | break; | |
587 | case DSA_TAG_PROTO_OCELOT_8021Q: | |
588 | felix_teardown_tag_8021q(ds, cpu); | |
589 | break; | |
590 | default: | |
591 | break; | |
592 | } | |
593 | } | |
594 | ||
595 | /* This always leaves the switch in a consistent state, because although the | |
596 | * tag_8021q setup can fail, the NPI setup can't. So either the change is made, | |
597 | * or the restoration is guaranteed to work. | |
598 | */ | |
599 | static int felix_change_tag_protocol(struct dsa_switch *ds, int cpu, | |
600 | enum dsa_tag_protocol proto) | |
601 | { | |
602 | struct ocelot *ocelot = ds->priv; | |
603 | struct felix *felix = ocelot_to_felix(ocelot); | |
604 | enum dsa_tag_protocol old_proto = felix->tag_proto; | |
605 | int err; | |
606 | ||
607 | if (proto != DSA_TAG_PROTO_SEVILLE && | |
608 | proto != DSA_TAG_PROTO_OCELOT && | |
609 | proto != DSA_TAG_PROTO_OCELOT_8021Q) | |
610 | return -EPROTONOSUPPORT; | |
611 | ||
612 | felix_del_tag_protocol(ds, cpu, old_proto); | |
613 | ||
614 | err = felix_set_tag_protocol(ds, cpu, proto); | |
615 | if (err) { | |
616 | felix_set_tag_protocol(ds, cpu, old_proto); | |
617 | return err; | |
618 | } | |
619 | ||
620 | felix->tag_proto = proto; | |
621 | ||
622 | return 0; | |
623 | } | |
624 | ||
625 | static enum dsa_tag_protocol felix_get_tag_protocol(struct dsa_switch *ds, | |
626 | int port, | |
627 | enum dsa_tag_protocol mp) | |
628 | { | |
629 | struct ocelot *ocelot = ds->priv; | |
630 | struct felix *felix = ocelot_to_felix(ocelot); | |
631 | ||
632 | return felix->tag_proto; | |
633 | } | |
634 | ||
635 | static int felix_set_ageing_time(struct dsa_switch *ds, | |
636 | unsigned int ageing_time) | |
637 | { | |
638 | struct ocelot *ocelot = ds->priv; | |
639 | ||
640 | ocelot_set_ageing_time(ocelot, ageing_time); | |
641 | ||
642 | return 0; | |
643 | } | |
644 | ||
645 | static int felix_fdb_dump(struct dsa_switch *ds, int port, | |
646 | dsa_fdb_dump_cb_t *cb, void *data) | |
647 | { | |
648 | struct ocelot *ocelot = ds->priv; | |
649 | ||
650 | return ocelot_fdb_dump(ocelot, port, cb, data); | |
651 | } | |
652 | ||
653 | static int felix_fdb_add(struct dsa_switch *ds, int port, | |
654 | const unsigned char *addr, u16 vid) | |
655 | { | |
656 | struct ocelot *ocelot = ds->priv; | |
657 | ||
658 | return ocelot_fdb_add(ocelot, port, addr, vid); | |
659 | } | |
660 | ||
661 | static int felix_fdb_del(struct dsa_switch *ds, int port, | |
662 | const unsigned char *addr, u16 vid) | |
663 | { | |
664 | struct ocelot *ocelot = ds->priv; | |
665 | ||
666 | return ocelot_fdb_del(ocelot, port, addr, vid); | |
667 | } | |
668 | ||
669 | static int felix_mdb_add(struct dsa_switch *ds, int port, | |
670 | const struct switchdev_obj_port_mdb *mdb) | |
671 | { | |
672 | struct ocelot *ocelot = ds->priv; | |
673 | ||
674 | return ocelot_port_mdb_add(ocelot, port, mdb); | |
675 | } | |
676 | ||
677 | static int felix_mdb_del(struct dsa_switch *ds, int port, | |
678 | const struct switchdev_obj_port_mdb *mdb) | |
679 | { | |
680 | struct ocelot *ocelot = ds->priv; | |
681 | ||
682 | return ocelot_port_mdb_del(ocelot, port, mdb); | |
683 | } | |
684 | ||
685 | static void felix_bridge_stp_state_set(struct dsa_switch *ds, int port, | |
686 | u8 state) | |
687 | { | |
688 | struct ocelot *ocelot = ds->priv; | |
689 | ||
690 | return ocelot_bridge_stp_state_set(ocelot, port, state); | |
691 | } | |
692 | ||
693 | static int felix_pre_bridge_flags(struct dsa_switch *ds, int port, | |
694 | struct switchdev_brport_flags val, | |
695 | struct netlink_ext_ack *extack) | |
696 | { | |
697 | struct ocelot *ocelot = ds->priv; | |
698 | ||
699 | return ocelot_port_pre_bridge_flags(ocelot, port, val); | |
700 | } | |
701 | ||
702 | static int felix_bridge_flags(struct dsa_switch *ds, int port, | |
703 | struct switchdev_brport_flags val, | |
704 | struct netlink_ext_ack *extack) | |
705 | { | |
706 | struct ocelot *ocelot = ds->priv; | |
707 | ||
708 | ocelot_port_bridge_flags(ocelot, port, val); | |
709 | ||
710 | return 0; | |
711 | } | |
712 | ||
713 | static int felix_bridge_join(struct dsa_switch *ds, int port, | |
714 | struct net_device *br) | |
715 | { | |
716 | struct ocelot *ocelot = ds->priv; | |
717 | ||
718 | ocelot_port_bridge_join(ocelot, port, br); | |
719 | ||
720 | return 0; | |
721 | } | |
722 | ||
723 | static void felix_bridge_leave(struct dsa_switch *ds, int port, | |
724 | struct net_device *br) | |
725 | { | |
726 | struct ocelot *ocelot = ds->priv; | |
727 | ||
728 | ocelot_port_bridge_leave(ocelot, port, br); | |
729 | } | |
730 | ||
731 | static int felix_lag_join(struct dsa_switch *ds, int port, | |
732 | struct net_device *bond, | |
733 | struct netdev_lag_upper_info *info) | |
734 | { | |
735 | struct ocelot *ocelot = ds->priv; | |
736 | ||
737 | return ocelot_port_lag_join(ocelot, port, bond, info); | |
738 | } | |
739 | ||
740 | static int felix_lag_leave(struct dsa_switch *ds, int port, | |
741 | struct net_device *bond) | |
742 | { | |
743 | struct ocelot *ocelot = ds->priv; | |
744 | ||
745 | ocelot_port_lag_leave(ocelot, port, bond); | |
746 | ||
747 | return 0; | |
748 | } | |
749 | ||
750 | static int felix_lag_change(struct dsa_switch *ds, int port) | |
751 | { | |
752 | struct dsa_port *dp = dsa_to_port(ds, port); | |
753 | struct ocelot *ocelot = ds->priv; | |
754 | ||
755 | ocelot_port_lag_change(ocelot, port, dp->lag_tx_enabled); | |
756 | ||
757 | return 0; | |
758 | } | |
759 | ||
760 | static int felix_vlan_prepare(struct dsa_switch *ds, int port, | |
761 | const struct switchdev_obj_port_vlan *vlan) | |
762 | { | |
763 | struct ocelot *ocelot = ds->priv; | |
764 | u16 flags = vlan->flags; | |
765 | ||
766 | /* Ocelot switches copy frames as-is to the CPU, so the flags: | |
767 | * egress-untagged or not, pvid or not, make no difference. This | |
768 | * behavior is already better than what DSA just tries to approximate | |
769 | * when it installs the VLAN with the same flags on the CPU port. | |
770 | * Just accept any configuration, and don't let ocelot deny installing | |
771 | * multiple native VLANs on the NPI port, because the switch doesn't | |
772 | * look at the port tag settings towards the NPI interface anyway. | |
773 | */ | |
774 | if (port == ocelot->npi) | |
775 | return 0; | |
776 | ||
777 | return ocelot_vlan_prepare(ocelot, port, vlan->vid, | |
778 | flags & BRIDGE_VLAN_INFO_PVID, | |
779 | flags & BRIDGE_VLAN_INFO_UNTAGGED); | |
780 | } | |
781 | ||
782 | static int felix_vlan_filtering(struct dsa_switch *ds, int port, bool enabled, | |
783 | struct netlink_ext_ack *extack) | |
784 | { | |
785 | struct ocelot *ocelot = ds->priv; | |
786 | ||
787 | return ocelot_port_vlan_filtering(ocelot, port, enabled); | |
788 | } | |
789 | ||
790 | static int felix_vlan_add(struct dsa_switch *ds, int port, | |
791 | const struct switchdev_obj_port_vlan *vlan, | |
792 | struct netlink_ext_ack *extack) | |
793 | { | |
794 | struct ocelot *ocelot = ds->priv; | |
795 | u16 flags = vlan->flags; | |
796 | int err; | |
797 | ||
798 | err = felix_vlan_prepare(ds, port, vlan); | |
799 | if (err) | |
800 | return err; | |
801 | ||
802 | return ocelot_vlan_add(ocelot, port, vlan->vid, | |
803 | flags & BRIDGE_VLAN_INFO_PVID, | |
804 | flags & BRIDGE_VLAN_INFO_UNTAGGED); | |
805 | } | |
806 | ||
807 | static int felix_vlan_del(struct dsa_switch *ds, int port, | |
808 | const struct switchdev_obj_port_vlan *vlan) | |
809 | { | |
810 | struct ocelot *ocelot = ds->priv; | |
811 | ||
812 | return ocelot_vlan_del(ocelot, port, vlan->vid); | |
813 | } | |
814 | ||
815 | static int felix_port_enable(struct dsa_switch *ds, int port, | |
816 | struct phy_device *phy) | |
817 | { | |
818 | struct ocelot *ocelot = ds->priv; | |
819 | ||
820 | ocelot_port_enable(ocelot, port, phy); | |
821 | ||
822 | return 0; | |
823 | } | |
824 | ||
825 | static void felix_port_disable(struct dsa_switch *ds, int port) | |
826 | { | |
827 | struct ocelot *ocelot = ds->priv; | |
828 | ||
829 | return ocelot_port_disable(ocelot, port); | |
830 | } | |
831 | ||
832 | static void felix_phylink_validate(struct dsa_switch *ds, int port, | |
833 | unsigned long *supported, | |
834 | struct phylink_link_state *state) | |
835 | { | |
836 | struct ocelot *ocelot = ds->priv; | |
837 | struct felix *felix = ocelot_to_felix(ocelot); | |
838 | ||
839 | if (felix->info->phylink_validate) | |
840 | felix->info->phylink_validate(ocelot, port, supported, state); | |
841 | } | |
842 | ||
843 | static void felix_phylink_mac_config(struct dsa_switch *ds, int port, | |
844 | unsigned int link_an_mode, | |
845 | const struct phylink_link_state *state) | |
846 | { | |
847 | struct ocelot *ocelot = ds->priv; | |
848 | struct felix *felix = ocelot_to_felix(ocelot); | |
849 | struct dsa_port *dp = dsa_to_port(ds, port); | |
850 | ||
851 | if (felix->pcs[port]) | |
852 | phylink_set_pcs(dp->pl, &felix->pcs[port]->pcs); | |
853 | } | |
854 | ||
855 | static void felix_phylink_mac_link_down(struct dsa_switch *ds, int port, | |
856 | unsigned int link_an_mode, | |
857 | phy_interface_t interface) | |
858 | { | |
859 | struct ocelot *ocelot = ds->priv; | |
860 | struct ocelot_port *ocelot_port = ocelot->ports[port]; | |
861 | int err; | |
862 | ||
863 | ocelot_port_rmwl(ocelot_port, 0, DEV_MAC_ENA_CFG_RX_ENA, | |
864 | DEV_MAC_ENA_CFG); | |
865 | ||
866 | ocelot_fields_write(ocelot, port, QSYS_SWITCH_PORT_MODE_PORT_ENA, 0); | |
867 | ||
868 | err = ocelot_port_flush(ocelot, port); | |
869 | if (err) | |
870 | dev_err(ocelot->dev, "failed to flush port %d: %d\n", | |
871 | port, err); | |
872 | ||
873 | /* Put the port in reset. */ | |
874 | ocelot_port_writel(ocelot_port, | |
875 | DEV_CLOCK_CFG_MAC_TX_RST | | |
876 | DEV_CLOCK_CFG_MAC_RX_RST | | |
877 | DEV_CLOCK_CFG_LINK_SPEED(OCELOT_SPEED_1000), | |
878 | DEV_CLOCK_CFG); | |
879 | } | |
880 | ||
881 | static void felix_phylink_mac_link_up(struct dsa_switch *ds, int port, | |
882 | unsigned int link_an_mode, | |
883 | phy_interface_t interface, | |
884 | struct phy_device *phydev, | |
885 | int speed, int duplex, | |
886 | bool tx_pause, bool rx_pause) | |
887 | { | |
888 | struct ocelot *ocelot = ds->priv; | |
889 | struct ocelot_port *ocelot_port = ocelot->ports[port]; | |
890 | struct felix *felix = ocelot_to_felix(ocelot); | |
891 | u32 mac_fc_cfg; | |
892 | ||
893 | /* Take port out of reset by clearing the MAC_TX_RST, MAC_RX_RST and | |
894 | * PORT_RST bits in DEV_CLOCK_CFG. Note that the way this system is | |
895 | * integrated is that the MAC speed is fixed and it's the PCS who is | |
896 | * performing the rate adaptation, so we have to write "1000Mbps" into | |
897 | * the LINK_SPEED field of DEV_CLOCK_CFG (which is also its default | |
898 | * value). | |
899 | */ | |
900 | ocelot_port_writel(ocelot_port, | |
901 | DEV_CLOCK_CFG_LINK_SPEED(OCELOT_SPEED_1000), | |
902 | DEV_CLOCK_CFG); | |
903 | ||
904 | switch (speed) { | |
905 | case SPEED_10: | |
906 | mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(3); | |
907 | break; | |
908 | case SPEED_100: | |
909 | mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(2); | |
910 | break; | |
911 | case SPEED_1000: | |
912 | case SPEED_2500: | |
913 | mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(1); | |
914 | break; | |
915 | default: | |
916 | dev_err(ocelot->dev, "Unsupported speed on port %d: %d\n", | |
917 | port, speed); | |
918 | return; | |
919 | } | |
920 | ||
921 | /* handle Rx pause in all cases, with 2500base-X this is used for rate | |
922 | * adaptation. | |
923 | */ | |
924 | mac_fc_cfg |= SYS_MAC_FC_CFG_RX_FC_ENA; | |
925 | ||
926 | if (tx_pause) | |
927 | mac_fc_cfg |= SYS_MAC_FC_CFG_TX_FC_ENA | | |
928 | SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) | | |
929 | SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) | | |
930 | SYS_MAC_FC_CFG_ZERO_PAUSE_ENA; | |
931 | ||
932 | /* Flow control. Link speed is only used here to evaluate the time | |
933 | * specification in incoming pause frames. | |
934 | */ | |
935 | ocelot_write_rix(ocelot, mac_fc_cfg, SYS_MAC_FC_CFG, port); | |
936 | ||
937 | ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port); | |
938 | ||
939 | ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, tx_pause); | |
940 | ||
941 | /* Undo the effects of felix_phylink_mac_link_down: | |
942 | * enable MAC module | |
943 | */ | |
944 | ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA | | |
945 | DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG); | |
946 | ||
947 | /* Enable receiving frames on the port, and activate auto-learning of | |
948 | * MAC addresses. | |
949 | */ | |
950 | ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO | | |
951 | ANA_PORT_PORT_CFG_RECV_ENA | | |
952 | ANA_PORT_PORT_CFG_PORTID_VAL(port), | |
953 | ANA_PORT_PORT_CFG, port); | |
954 | ||
955 | /* Core: Enable port for frame transfer */ | |
956 | ocelot_fields_write(ocelot, port, | |
957 | QSYS_SWITCH_PORT_MODE_PORT_ENA, 1); | |
958 | ||
959 | if (felix->info->port_sched_speed_set) | |
960 | felix->info->port_sched_speed_set(ocelot, port, speed); | |
961 | } | |
962 | ||
963 | static void felix_port_qos_map_init(struct ocelot *ocelot, int port) | |
964 | { | |
965 | int i; | |
966 | ||
967 | ocelot_rmw_gix(ocelot, | |
968 | ANA_PORT_QOS_CFG_QOS_PCP_ENA, | |
969 | ANA_PORT_QOS_CFG_QOS_PCP_ENA, | |
970 | ANA_PORT_QOS_CFG, | |
971 | port); | |
972 | ||
973 | for (i = 0; i < OCELOT_NUM_TC * 2; i++) { | |
974 | ocelot_rmw_ix(ocelot, | |
975 | (ANA_PORT_PCP_DEI_MAP_DP_PCP_DEI_VAL & i) | | |
976 | ANA_PORT_PCP_DEI_MAP_QOS_PCP_DEI_VAL(i), | |
977 | ANA_PORT_PCP_DEI_MAP_DP_PCP_DEI_VAL | | |
978 | ANA_PORT_PCP_DEI_MAP_QOS_PCP_DEI_VAL_M, | |
979 | ANA_PORT_PCP_DEI_MAP, | |
980 | port, i); | |
981 | } | |
982 | } | |
983 | ||
984 | static void felix_get_strings(struct dsa_switch *ds, int port, | |
985 | u32 stringset, u8 *data) | |
986 | { | |
987 | struct ocelot *ocelot = ds->priv; | |
988 | ||
989 | return ocelot_get_strings(ocelot, port, stringset, data); | |
990 | } | |
991 | ||
992 | static void felix_get_ethtool_stats(struct dsa_switch *ds, int port, u64 *data) | |
993 | { | |
994 | struct ocelot *ocelot = ds->priv; | |
995 | ||
996 | ocelot_get_ethtool_stats(ocelot, port, data); | |
997 | } | |
998 | ||
999 | static int felix_get_sset_count(struct dsa_switch *ds, int port, int sset) | |
1000 | { | |
1001 | struct ocelot *ocelot = ds->priv; | |
1002 | ||
1003 | return ocelot_get_sset_count(ocelot, port, sset); | |
1004 | } | |
1005 | ||
1006 | static int felix_get_ts_info(struct dsa_switch *ds, int port, | |
1007 | struct ethtool_ts_info *info) | |
1008 | { | |
1009 | struct ocelot *ocelot = ds->priv; | |
1010 | ||
1011 | return ocelot_get_ts_info(ocelot, port, info); | |
1012 | } | |
1013 | ||
1014 | static int felix_parse_ports_node(struct felix *felix, | |
1015 | struct device_node *ports_node, | |
1016 | phy_interface_t *port_phy_modes) | |
1017 | { | |
1018 | struct ocelot *ocelot = &felix->ocelot; | |
1019 | struct device *dev = felix->ocelot.dev; | |
1020 | struct device_node *child; | |
1021 | ||
1022 | for_each_available_child_of_node(ports_node, child) { | |
1023 | phy_interface_t phy_mode; | |
1024 | u32 port; | |
1025 | int err; | |
1026 | ||
1027 | /* Get switch port number from DT */ | |
1028 | if (of_property_read_u32(child, "reg", &port) < 0) { | |
1029 | dev_err(dev, "Port number not defined in device tree " | |
1030 | "(property \"reg\")\n"); | |
1031 | of_node_put(child); | |
1032 | return -ENODEV; | |
1033 | } | |
1034 | ||
1035 | /* Get PHY mode from DT */ | |
1036 | err = of_get_phy_mode(child, &phy_mode); | |
1037 | if (err) { | |
1038 | dev_err(dev, "Failed to read phy-mode or " | |
1039 | "phy-interface-type property for port %d\n", | |
1040 | port); | |
1041 | of_node_put(child); | |
1042 | return -ENODEV; | |
1043 | } | |
1044 | ||
1045 | err = felix->info->prevalidate_phy_mode(ocelot, port, phy_mode); | |
1046 | if (err < 0) { | |
1047 | dev_err(dev, "Unsupported PHY mode %s on port %d\n", | |
1048 | phy_modes(phy_mode), port); | |
1049 | of_node_put(child); | |
1050 | return err; | |
1051 | } | |
1052 | ||
1053 | port_phy_modes[port] = phy_mode; | |
1054 | } | |
1055 | ||
1056 | return 0; | |
1057 | } | |
1058 | ||
1059 | static int felix_parse_dt(struct felix *felix, phy_interface_t *port_phy_modes) | |
1060 | { | |
1061 | struct device *dev = felix->ocelot.dev; | |
1062 | struct device_node *switch_node; | |
1063 | struct device_node *ports_node; | |
1064 | int err; | |
1065 | ||
1066 | switch_node = dev->of_node; | |
1067 | ||
1068 | ports_node = of_get_child_by_name(switch_node, "ports"); | |
1069 | if (!ports_node) { | |
1070 | dev_err(dev, "Incorrect bindings: absent \"ports\" node\n"); | |
1071 | return -ENODEV; | |
1072 | } | |
1073 | ||
1074 | err = felix_parse_ports_node(felix, ports_node, port_phy_modes); | |
1075 | of_node_put(ports_node); | |
1076 | ||
1077 | return err; | |
1078 | } | |
1079 | ||
1080 | static int felix_init_structs(struct felix *felix, int num_phys_ports) | |
1081 | { | |
1082 | struct ocelot *ocelot = &felix->ocelot; | |
1083 | phy_interface_t *port_phy_modes; | |
1084 | struct resource res; | |
1085 | int port, i, err; | |
1086 | ||
1087 | ocelot->num_phys_ports = num_phys_ports; | |
1088 | ocelot->ports = devm_kcalloc(ocelot->dev, num_phys_ports, | |
1089 | sizeof(struct ocelot_port *), GFP_KERNEL); | |
1090 | if (!ocelot->ports) | |
1091 | return -ENOMEM; | |
1092 | ||
1093 | ocelot->map = felix->info->map; | |
1094 | ocelot->stats_layout = felix->info->stats_layout; | |
1095 | ocelot->num_stats = felix->info->num_stats; | |
1096 | ocelot->num_mact_rows = felix->info->num_mact_rows; | |
1097 | ocelot->vcap = felix->info->vcap; | |
1098 | ocelot->ops = felix->info->ops; | |
1099 | ocelot->npi_inj_prefix = OCELOT_TAG_PREFIX_SHORT; | |
1100 | ocelot->npi_xtr_prefix = OCELOT_TAG_PREFIX_SHORT; | |
1101 | ocelot->devlink = felix->ds->devlink; | |
1102 | ||
1103 | port_phy_modes = kcalloc(num_phys_ports, sizeof(phy_interface_t), | |
1104 | GFP_KERNEL); | |
1105 | if (!port_phy_modes) | |
1106 | return -ENOMEM; | |
1107 | ||
1108 | err = felix_parse_dt(felix, port_phy_modes); | |
1109 | if (err) { | |
1110 | kfree(port_phy_modes); | |
1111 | return err; | |
1112 | } | |
1113 | ||
1114 | for (i = 0; i < TARGET_MAX; i++) { | |
1115 | struct regmap *target; | |
1116 | ||
1117 | if (!felix->info->target_io_res[i].name) | |
1118 | continue; | |
1119 | ||
1120 | memcpy(&res, &felix->info->target_io_res[i], sizeof(res)); | |
1121 | res.flags = IORESOURCE_MEM; | |
1122 | res.start += felix->switch_base; | |
1123 | res.end += felix->switch_base; | |
1124 | ||
1125 | target = ocelot_regmap_init(ocelot, &res); | |
1126 | if (IS_ERR(target)) { | |
1127 | dev_err(ocelot->dev, | |
1128 | "Failed to map device memory space\n"); | |
1129 | kfree(port_phy_modes); | |
1130 | return PTR_ERR(target); | |
1131 | } | |
1132 | ||
1133 | ocelot->targets[i] = target; | |
1134 | } | |
1135 | ||
1136 | err = ocelot_regfields_init(ocelot, felix->info->regfields); | |
1137 | if (err) { | |
1138 | dev_err(ocelot->dev, "failed to init reg fields map\n"); | |
1139 | kfree(port_phy_modes); | |
1140 | return err; | |
1141 | } | |
1142 | ||
1143 | for (port = 0; port < num_phys_ports; port++) { | |
1144 | struct ocelot_port *ocelot_port; | |
1145 | struct regmap *target; | |
1146 | ||
1147 | ocelot_port = devm_kzalloc(ocelot->dev, | |
1148 | sizeof(struct ocelot_port), | |
1149 | GFP_KERNEL); | |
1150 | if (!ocelot_port) { | |
1151 | dev_err(ocelot->dev, | |
1152 | "failed to allocate port memory\n"); | |
1153 | kfree(port_phy_modes); | |
1154 | return -ENOMEM; | |
1155 | } | |
1156 | ||
1157 | memcpy(&res, &felix->info->port_io_res[port], sizeof(res)); | |
1158 | res.flags = IORESOURCE_MEM; | |
1159 | res.start += felix->switch_base; | |
1160 | res.end += felix->switch_base; | |
1161 | ||
1162 | target = ocelot_regmap_init(ocelot, &res); | |
1163 | if (IS_ERR(target)) { | |
1164 | dev_err(ocelot->dev, | |
1165 | "Failed to map memory space for port %d\n", | |
1166 | port); | |
1167 | kfree(port_phy_modes); | |
1168 | return PTR_ERR(target); | |
1169 | } | |
1170 | ||
1171 | ocelot_port->phy_mode = port_phy_modes[port]; | |
1172 | ocelot_port->ocelot = ocelot; | |
1173 | ocelot_port->target = target; | |
1174 | ocelot->ports[port] = ocelot_port; | |
1175 | } | |
1176 | ||
1177 | kfree(port_phy_modes); | |
1178 | ||
1179 | if (felix->info->mdio_bus_alloc) { | |
1180 | err = felix->info->mdio_bus_alloc(ocelot); | |
1181 | if (err < 0) | |
1182 | return err; | |
1183 | } | |
1184 | ||
1185 | return 0; | |
1186 | } | |
1187 | ||
1188 | /* Hardware initialization done here so that we can allocate structures with | |
1189 | * devm without fear of dsa_register_switch returning -EPROBE_DEFER and causing | |
1190 | * us to allocate structures twice (leak memory) and map PCI memory twice | |
1191 | * (which will not work). | |
1192 | */ | |
1193 | static int felix_setup(struct dsa_switch *ds) | |
1194 | { | |
1195 | struct ocelot *ocelot = ds->priv; | |
1196 | struct felix *felix = ocelot_to_felix(ocelot); | |
1197 | int port, err; | |
1198 | ||
1199 | err = felix_init_structs(felix, ds->num_ports); | |
1200 | if (err) | |
1201 | return err; | |
1202 | ||
1203 | err = ocelot_init(ocelot); | |
1204 | if (err) | |
1205 | goto out_mdiobus_free; | |
1206 | ||
1207 | if (ocelot->ptp) { | |
1208 | err = ocelot_init_timestamp(ocelot, felix->info->ptp_caps); | |
1209 | if (err) { | |
1210 | dev_err(ocelot->dev, | |
1211 | "Timestamp initialization failed\n"); | |
1212 | ocelot->ptp = 0; | |
1213 | } | |
1214 | } | |
1215 | ||
1216 | for (port = 0; port < ds->num_ports; port++) { | |
1217 | if (dsa_is_unused_port(ds, port)) | |
1218 | continue; | |
1219 | ||
1220 | ocelot_init_port(ocelot, port); | |
1221 | ||
1222 | /* Set the default QoS Classification based on PCP and DEI | |
1223 | * bits of vlan tag. | |
1224 | */ | |
1225 | felix_port_qos_map_init(ocelot, port); | |
1226 | } | |
1227 | ||
1228 | err = ocelot_devlink_sb_register(ocelot); | |
1229 | if (err) | |
1230 | goto out_deinit_ports; | |
1231 | ||
1232 | for (port = 0; port < ds->num_ports; port++) { | |
1233 | if (!dsa_is_cpu_port(ds, port)) | |
1234 | continue; | |
1235 | ||
1236 | /* The initial tag protocol is NPI which always returns 0, so | |
1237 | * there's no real point in checking for errors. | |
1238 | */ | |
1239 | felix_set_tag_protocol(ds, port, felix->tag_proto); | |
1240 | } | |
1241 | ||
1242 | ds->mtu_enforcement_ingress = true; | |
1243 | ds->assisted_learning_on_cpu_port = true; | |
1244 | ||
1245 | return 0; | |
1246 | ||
1247 | out_deinit_ports: | |
1248 | for (port = 0; port < ocelot->num_phys_ports; port++) { | |
1249 | if (dsa_is_unused_port(ds, port)) | |
1250 | continue; | |
1251 | ||
1252 | ocelot_deinit_port(ocelot, port); | |
1253 | } | |
1254 | ||
1255 | ocelot_deinit_timestamp(ocelot); | |
1256 | ocelot_deinit(ocelot); | |
1257 | ||
1258 | out_mdiobus_free: | |
1259 | if (felix->info->mdio_bus_free) | |
1260 | felix->info->mdio_bus_free(ocelot); | |
1261 | ||
1262 | return err; | |
1263 | } | |
1264 | ||
1265 | static void felix_teardown(struct dsa_switch *ds) | |
1266 | { | |
1267 | struct ocelot *ocelot = ds->priv; | |
1268 | struct felix *felix = ocelot_to_felix(ocelot); | |
1269 | int port; | |
1270 | ||
1271 | for (port = 0; port < ds->num_ports; port++) { | |
1272 | if (!dsa_is_cpu_port(ds, port)) | |
1273 | continue; | |
1274 | ||
1275 | felix_del_tag_protocol(ds, port, felix->tag_proto); | |
1276 | } | |
1277 | ||
1278 | ocelot_devlink_sb_unregister(ocelot); | |
1279 | ocelot_deinit_timestamp(ocelot); | |
1280 | ocelot_deinit(ocelot); | |
1281 | ||
1282 | for (port = 0; port < ocelot->num_phys_ports; port++) { | |
1283 | if (dsa_is_unused_port(ds, port)) | |
1284 | continue; | |
1285 | ||
1286 | ocelot_deinit_port(ocelot, port); | |
1287 | } | |
1288 | ||
1289 | if (felix->info->mdio_bus_free) | |
1290 | felix->info->mdio_bus_free(ocelot); | |
1291 | } | |
1292 | ||
1293 | static int felix_hwtstamp_get(struct dsa_switch *ds, int port, | |
1294 | struct ifreq *ifr) | |
1295 | { | |
1296 | struct ocelot *ocelot = ds->priv; | |
1297 | ||
1298 | return ocelot_hwstamp_get(ocelot, port, ifr); | |
1299 | } | |
1300 | ||
1301 | static int felix_hwtstamp_set(struct dsa_switch *ds, int port, | |
1302 | struct ifreq *ifr) | |
1303 | { | |
1304 | struct ocelot *ocelot = ds->priv; | |
1305 | ||
1306 | return ocelot_hwstamp_set(ocelot, port, ifr); | |
1307 | } | |
1308 | ||
1309 | static bool felix_check_xtr_pkt(struct ocelot *ocelot, unsigned int ptp_type) | |
1310 | { | |
1311 | struct felix *felix = ocelot_to_felix(ocelot); | |
1312 | int err, grp = 0; | |
1313 | ||
1314 | if (felix->tag_proto != DSA_TAG_PROTO_OCELOT_8021Q) | |
1315 | return false; | |
1316 | ||
1317 | if (!felix->info->quirk_no_xtr_irq) | |
1318 | return false; | |
1319 | ||
1320 | if (ptp_type == PTP_CLASS_NONE) | |
1321 | return false; | |
1322 | ||
1323 | while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp)) { | |
1324 | struct sk_buff *skb; | |
1325 | unsigned int type; | |
1326 | ||
1327 | err = ocelot_xtr_poll_frame(ocelot, grp, &skb); | |
1328 | if (err) | |
1329 | goto out; | |
1330 | ||
1331 | /* We trap to the CPU port module all PTP frames, but | |
1332 | * felix_rxtstamp() only gets called for event frames. | |
1333 | * So we need to avoid sending duplicate general | |
1334 | * message frames by running a second BPF classifier | |
1335 | * here and dropping those. | |
1336 | */ | |
1337 | __skb_push(skb, ETH_HLEN); | |
1338 | ||
1339 | type = ptp_classify_raw(skb); | |
1340 | ||
1341 | __skb_pull(skb, ETH_HLEN); | |
1342 | ||
1343 | if (type == PTP_CLASS_NONE) { | |
1344 | kfree_skb(skb); | |
1345 | continue; | |
1346 | } | |
1347 | ||
1348 | netif_rx(skb); | |
1349 | } | |
1350 | ||
1351 | out: | |
1352 | if (err < 0) | |
1353 | ocelot_drain_cpu_queue(ocelot, 0); | |
1354 | ||
1355 | return true; | |
1356 | } | |
1357 | ||
1358 | static bool felix_rxtstamp(struct dsa_switch *ds, int port, | |
1359 | struct sk_buff *skb, unsigned int type) | |
1360 | { | |
1361 | u8 *extraction = skb->data - ETH_HLEN - OCELOT_TAG_LEN; | |
1362 | struct skb_shared_hwtstamps *shhwtstamps; | |
1363 | struct ocelot *ocelot = ds->priv; | |
1364 | u32 tstamp_lo, tstamp_hi; | |
1365 | struct timespec64 ts; | |
1366 | u64 tstamp, val; | |
1367 | ||
1368 | /* If the "no XTR IRQ" workaround is in use, tell DSA to defer this skb | |
1369 | * for RX timestamping. Then free it, and poll for its copy through | |
1370 | * MMIO in the CPU port module, and inject that into the stack from | |
1371 | * ocelot_xtr_poll(). | |
1372 | */ | |
1373 | if (felix_check_xtr_pkt(ocelot, type)) { | |
1374 | kfree_skb(skb); | |
1375 | return true; | |
1376 | } | |
1377 | ||
1378 | ocelot_ptp_gettime64(&ocelot->ptp_info, &ts); | |
1379 | tstamp = ktime_set(ts.tv_sec, ts.tv_nsec); | |
1380 | ||
1381 | ocelot_xfh_get_rew_val(extraction, &val); | |
1382 | tstamp_lo = (u32)val; | |
1383 | ||
1384 | tstamp_hi = tstamp >> 32; | |
1385 | if ((tstamp & 0xffffffff) < tstamp_lo) | |
1386 | tstamp_hi--; | |
1387 | ||
1388 | tstamp = ((u64)tstamp_hi << 32) | tstamp_lo; | |
1389 | ||
1390 | shhwtstamps = skb_hwtstamps(skb); | |
1391 | memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps)); | |
1392 | shhwtstamps->hwtstamp = tstamp; | |
1393 | return false; | |
1394 | } | |
1395 | ||
1396 | static void felix_txtstamp(struct dsa_switch *ds, int port, | |
1397 | struct sk_buff *skb) | |
1398 | { | |
1399 | struct ocelot *ocelot = ds->priv; | |
1400 | struct sk_buff *clone = NULL; | |
1401 | ||
1402 | if (!ocelot->ptp) | |
1403 | return; | |
1404 | ||
1405 | if (ocelot_port_txtstamp_request(ocelot, port, skb, &clone)) | |
1406 | return; | |
1407 | ||
1408 | if (clone) | |
1409 | OCELOT_SKB_CB(skb)->clone = clone; | |
1410 | } | |
1411 | ||
1412 | static int felix_change_mtu(struct dsa_switch *ds, int port, int new_mtu) | |
1413 | { | |
1414 | struct ocelot *ocelot = ds->priv; | |
1415 | ||
1416 | ocelot_port_set_maxlen(ocelot, port, new_mtu); | |
1417 | ||
1418 | return 0; | |
1419 | } | |
1420 | ||
1421 | static int felix_get_max_mtu(struct dsa_switch *ds, int port) | |
1422 | { | |
1423 | struct ocelot *ocelot = ds->priv; | |
1424 | ||
1425 | return ocelot_get_max_mtu(ocelot, port); | |
1426 | } | |
1427 | ||
1428 | static int felix_cls_flower_add(struct dsa_switch *ds, int port, | |
1429 | struct flow_cls_offload *cls, bool ingress) | |
1430 | { | |
1431 | struct ocelot *ocelot = ds->priv; | |
1432 | ||
1433 | return ocelot_cls_flower_replace(ocelot, port, cls, ingress); | |
1434 | } | |
1435 | ||
1436 | static int felix_cls_flower_del(struct dsa_switch *ds, int port, | |
1437 | struct flow_cls_offload *cls, bool ingress) | |
1438 | { | |
1439 | struct ocelot *ocelot = ds->priv; | |
1440 | ||
1441 | return ocelot_cls_flower_destroy(ocelot, port, cls, ingress); | |
1442 | } | |
1443 | ||
1444 | static int felix_cls_flower_stats(struct dsa_switch *ds, int port, | |
1445 | struct flow_cls_offload *cls, bool ingress) | |
1446 | { | |
1447 | struct ocelot *ocelot = ds->priv; | |
1448 | ||
1449 | return ocelot_cls_flower_stats(ocelot, port, cls, ingress); | |
1450 | } | |
1451 | ||
1452 | static int felix_port_policer_add(struct dsa_switch *ds, int port, | |
1453 | struct dsa_mall_policer_tc_entry *policer) | |
1454 | { | |
1455 | struct ocelot *ocelot = ds->priv; | |
1456 | struct ocelot_policer pol = { | |
1457 | .rate = div_u64(policer->rate_bytes_per_sec, 1000) * 8, | |
1458 | .burst = policer->burst, | |
1459 | }; | |
1460 | ||
1461 | return ocelot_port_policer_add(ocelot, port, &pol); | |
1462 | } | |
1463 | ||
1464 | static void felix_port_policer_del(struct dsa_switch *ds, int port) | |
1465 | { | |
1466 | struct ocelot *ocelot = ds->priv; | |
1467 | ||
1468 | ocelot_port_policer_del(ocelot, port); | |
1469 | } | |
1470 | ||
1471 | static int felix_port_setup_tc(struct dsa_switch *ds, int port, | |
1472 | enum tc_setup_type type, | |
1473 | void *type_data) | |
1474 | { | |
1475 | struct ocelot *ocelot = ds->priv; | |
1476 | struct felix *felix = ocelot_to_felix(ocelot); | |
1477 | ||
1478 | if (felix->info->port_setup_tc) | |
1479 | return felix->info->port_setup_tc(ds, port, type, type_data); | |
1480 | else | |
1481 | return -EOPNOTSUPP; | |
1482 | } | |
1483 | ||
1484 | static int felix_sb_pool_get(struct dsa_switch *ds, unsigned int sb_index, | |
1485 | u16 pool_index, | |
1486 | struct devlink_sb_pool_info *pool_info) | |
1487 | { | |
1488 | struct ocelot *ocelot = ds->priv; | |
1489 | ||
1490 | return ocelot_sb_pool_get(ocelot, sb_index, pool_index, pool_info); | |
1491 | } | |
1492 | ||
1493 | static int felix_sb_pool_set(struct dsa_switch *ds, unsigned int sb_index, | |
1494 | u16 pool_index, u32 size, | |
1495 | enum devlink_sb_threshold_type threshold_type, | |
1496 | struct netlink_ext_ack *extack) | |
1497 | { | |
1498 | struct ocelot *ocelot = ds->priv; | |
1499 | ||
1500 | return ocelot_sb_pool_set(ocelot, sb_index, pool_index, size, | |
1501 | threshold_type, extack); | |
1502 | } | |
1503 | ||
1504 | static int felix_sb_port_pool_get(struct dsa_switch *ds, int port, | |
1505 | unsigned int sb_index, u16 pool_index, | |
1506 | u32 *p_threshold) | |
1507 | { | |
1508 | struct ocelot *ocelot = ds->priv; | |
1509 | ||
1510 | return ocelot_sb_port_pool_get(ocelot, port, sb_index, pool_index, | |
1511 | p_threshold); | |
1512 | } | |
1513 | ||
1514 | static int felix_sb_port_pool_set(struct dsa_switch *ds, int port, | |
1515 | unsigned int sb_index, u16 pool_index, | |
1516 | u32 threshold, struct netlink_ext_ack *extack) | |
1517 | { | |
1518 | struct ocelot *ocelot = ds->priv; | |
1519 | ||
1520 | return ocelot_sb_port_pool_set(ocelot, port, sb_index, pool_index, | |
1521 | threshold, extack); | |
1522 | } | |
1523 | ||
1524 | static int felix_sb_tc_pool_bind_get(struct dsa_switch *ds, int port, | |
1525 | unsigned int sb_index, u16 tc_index, | |
1526 | enum devlink_sb_pool_type pool_type, | |
1527 | u16 *p_pool_index, u32 *p_threshold) | |
1528 | { | |
1529 | struct ocelot *ocelot = ds->priv; | |
1530 | ||
1531 | return ocelot_sb_tc_pool_bind_get(ocelot, port, sb_index, tc_index, | |
1532 | pool_type, p_pool_index, | |
1533 | p_threshold); | |
1534 | } | |
1535 | ||
1536 | static int felix_sb_tc_pool_bind_set(struct dsa_switch *ds, int port, | |
1537 | unsigned int sb_index, u16 tc_index, | |
1538 | enum devlink_sb_pool_type pool_type, | |
1539 | u16 pool_index, u32 threshold, | |
1540 | struct netlink_ext_ack *extack) | |
1541 | { | |
1542 | struct ocelot *ocelot = ds->priv; | |
1543 | ||
1544 | return ocelot_sb_tc_pool_bind_set(ocelot, port, sb_index, tc_index, | |
1545 | pool_type, pool_index, threshold, | |
1546 | extack); | |
1547 | } | |
1548 | ||
1549 | static int felix_sb_occ_snapshot(struct dsa_switch *ds, | |
1550 | unsigned int sb_index) | |
1551 | { | |
1552 | struct ocelot *ocelot = ds->priv; | |
1553 | ||
1554 | return ocelot_sb_occ_snapshot(ocelot, sb_index); | |
1555 | } | |
1556 | ||
1557 | static int felix_sb_occ_max_clear(struct dsa_switch *ds, | |
1558 | unsigned int sb_index) | |
1559 | { | |
1560 | struct ocelot *ocelot = ds->priv; | |
1561 | ||
1562 | return ocelot_sb_occ_max_clear(ocelot, sb_index); | |
1563 | } | |
1564 | ||
1565 | static int felix_sb_occ_port_pool_get(struct dsa_switch *ds, int port, | |
1566 | unsigned int sb_index, u16 pool_index, | |
1567 | u32 *p_cur, u32 *p_max) | |
1568 | { | |
1569 | struct ocelot *ocelot = ds->priv; | |
1570 | ||
1571 | return ocelot_sb_occ_port_pool_get(ocelot, port, sb_index, pool_index, | |
1572 | p_cur, p_max); | |
1573 | } | |
1574 | ||
1575 | static int felix_sb_occ_tc_port_bind_get(struct dsa_switch *ds, int port, | |
1576 | unsigned int sb_index, u16 tc_index, | |
1577 | enum devlink_sb_pool_type pool_type, | |
1578 | u32 *p_cur, u32 *p_max) | |
1579 | { | |
1580 | struct ocelot *ocelot = ds->priv; | |
1581 | ||
1582 | return ocelot_sb_occ_tc_port_bind_get(ocelot, port, sb_index, tc_index, | |
1583 | pool_type, p_cur, p_max); | |
1584 | } | |
1585 | ||
1586 | static int felix_mrp_add(struct dsa_switch *ds, int port, | |
1587 | const struct switchdev_obj_mrp *mrp) | |
1588 | { | |
1589 | struct ocelot *ocelot = ds->priv; | |
1590 | ||
1591 | return ocelot_mrp_add(ocelot, port, mrp); | |
1592 | } | |
1593 | ||
1594 | static int felix_mrp_del(struct dsa_switch *ds, int port, | |
1595 | const struct switchdev_obj_mrp *mrp) | |
1596 | { | |
1597 | struct ocelot *ocelot = ds->priv; | |
1598 | ||
1599 | return ocelot_mrp_add(ocelot, port, mrp); | |
1600 | } | |
1601 | ||
1602 | static int | |
1603 | felix_mrp_add_ring_role(struct dsa_switch *ds, int port, | |
1604 | const struct switchdev_obj_ring_role_mrp *mrp) | |
1605 | { | |
1606 | struct ocelot *ocelot = ds->priv; | |
1607 | ||
1608 | return ocelot_mrp_add_ring_role(ocelot, port, mrp); | |
1609 | } | |
1610 | ||
1611 | static int | |
1612 | felix_mrp_del_ring_role(struct dsa_switch *ds, int port, | |
1613 | const struct switchdev_obj_ring_role_mrp *mrp) | |
1614 | { | |
1615 | struct ocelot *ocelot = ds->priv; | |
1616 | ||
1617 | return ocelot_mrp_del_ring_role(ocelot, port, mrp); | |
1618 | } | |
1619 | ||
1620 | const struct dsa_switch_ops felix_switch_ops = { | |
1621 | .get_tag_protocol = felix_get_tag_protocol, | |
1622 | .change_tag_protocol = felix_change_tag_protocol, | |
1623 | .setup = felix_setup, | |
1624 | .teardown = felix_teardown, | |
1625 | .set_ageing_time = felix_set_ageing_time, | |
1626 | .get_strings = felix_get_strings, | |
1627 | .get_ethtool_stats = felix_get_ethtool_stats, | |
1628 | .get_sset_count = felix_get_sset_count, | |
1629 | .get_ts_info = felix_get_ts_info, | |
1630 | .phylink_validate = felix_phylink_validate, | |
1631 | .phylink_mac_config = felix_phylink_mac_config, | |
1632 | .phylink_mac_link_down = felix_phylink_mac_link_down, | |
1633 | .phylink_mac_link_up = felix_phylink_mac_link_up, | |
1634 | .port_enable = felix_port_enable, | |
1635 | .port_disable = felix_port_disable, | |
1636 | .port_fdb_dump = felix_fdb_dump, | |
1637 | .port_fdb_add = felix_fdb_add, | |
1638 | .port_fdb_del = felix_fdb_del, | |
1639 | .port_mdb_add = felix_mdb_add, | |
1640 | .port_mdb_del = felix_mdb_del, | |
1641 | .port_pre_bridge_flags = felix_pre_bridge_flags, | |
1642 | .port_bridge_flags = felix_bridge_flags, | |
1643 | .port_bridge_join = felix_bridge_join, | |
1644 | .port_bridge_leave = felix_bridge_leave, | |
1645 | .port_lag_join = felix_lag_join, | |
1646 | .port_lag_leave = felix_lag_leave, | |
1647 | .port_lag_change = felix_lag_change, | |
1648 | .port_stp_state_set = felix_bridge_stp_state_set, | |
1649 | .port_vlan_filtering = felix_vlan_filtering, | |
1650 | .port_vlan_add = felix_vlan_add, | |
1651 | .port_vlan_del = felix_vlan_del, | |
1652 | .port_hwtstamp_get = felix_hwtstamp_get, | |
1653 | .port_hwtstamp_set = felix_hwtstamp_set, | |
1654 | .port_rxtstamp = felix_rxtstamp, | |
1655 | .port_txtstamp = felix_txtstamp, | |
1656 | .port_change_mtu = felix_change_mtu, | |
1657 | .port_max_mtu = felix_get_max_mtu, | |
1658 | .port_policer_add = felix_port_policer_add, | |
1659 | .port_policer_del = felix_port_policer_del, | |
1660 | .cls_flower_add = felix_cls_flower_add, | |
1661 | .cls_flower_del = felix_cls_flower_del, | |
1662 | .cls_flower_stats = felix_cls_flower_stats, | |
1663 | .port_setup_tc = felix_port_setup_tc, | |
1664 | .devlink_sb_pool_get = felix_sb_pool_get, | |
1665 | .devlink_sb_pool_set = felix_sb_pool_set, | |
1666 | .devlink_sb_port_pool_get = felix_sb_port_pool_get, | |
1667 | .devlink_sb_port_pool_set = felix_sb_port_pool_set, | |
1668 | .devlink_sb_tc_pool_bind_get = felix_sb_tc_pool_bind_get, | |
1669 | .devlink_sb_tc_pool_bind_set = felix_sb_tc_pool_bind_set, | |
1670 | .devlink_sb_occ_snapshot = felix_sb_occ_snapshot, | |
1671 | .devlink_sb_occ_max_clear = felix_sb_occ_max_clear, | |
1672 | .devlink_sb_occ_port_pool_get = felix_sb_occ_port_pool_get, | |
1673 | .devlink_sb_occ_tc_port_bind_get= felix_sb_occ_tc_port_bind_get, | |
1674 | .port_mrp_add = felix_mrp_add, | |
1675 | .port_mrp_del = felix_mrp_del, | |
1676 | .port_mrp_add_ring_role = felix_mrp_add_ring_role, | |
1677 | .port_mrp_del_ring_role = felix_mrp_del_ring_role, | |
1678 | }; | |
1679 | ||
1680 | struct net_device *felix_port_to_netdev(struct ocelot *ocelot, int port) | |
1681 | { | |
1682 | struct felix *felix = ocelot_to_felix(ocelot); | |
1683 | struct dsa_switch *ds = felix->ds; | |
1684 | ||
1685 | if (!dsa_is_user_port(ds, port)) | |
1686 | return NULL; | |
1687 | ||
1688 | return dsa_to_port(ds, port)->slave; | |
1689 | } | |
1690 | ||
1691 | int felix_netdev_to_port(struct net_device *dev) | |
1692 | { | |
1693 | struct dsa_port *dp; | |
1694 | ||
1695 | dp = dsa_port_from_netdev(dev); | |
1696 | if (IS_ERR(dp)) | |
1697 | return -EINVAL; | |
1698 | ||
1699 | return dp->index; | |
1700 | } |