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1 | /* | |
2 | * Driver for BCM963xx builtin Ethernet mac | |
3 | * | |
4 | * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
19 | */ | |
20 | #include <linux/init.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/clk.h> | |
24 | #include <linux/etherdevice.h> | |
25 | #include <linux/slab.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/ethtool.h> | |
28 | #include <linux/crc32.h> | |
29 | #include <linux/err.h> | |
30 | #include <linux/dma-mapping.h> | |
31 | #include <linux/platform_device.h> | |
32 | #include <linux/if_vlan.h> | |
33 | ||
34 | #include <bcm63xx_dev_enet.h> | |
35 | #include "bcm63xx_enet.h" | |
36 | ||
37 | static char bcm_enet_driver_name[] = "bcm63xx_enet"; | |
38 | static char bcm_enet_driver_version[] = "1.0"; | |
39 | ||
40 | static int copybreak __read_mostly = 128; | |
41 | module_param(copybreak, int, 0); | |
42 | MODULE_PARM_DESC(copybreak, "Receive copy threshold"); | |
43 | ||
44 | /* io registers memory shared between all devices */ | |
45 | static void __iomem *bcm_enet_shared_base[3]; | |
46 | ||
47 | /* | |
48 | * io helpers to access mac registers | |
49 | */ | |
50 | static inline u32 enet_readl(struct bcm_enet_priv *priv, u32 off) | |
51 | { | |
52 | return bcm_readl(priv->base + off); | |
53 | } | |
54 | ||
55 | static inline void enet_writel(struct bcm_enet_priv *priv, | |
56 | u32 val, u32 off) | |
57 | { | |
58 | bcm_writel(val, priv->base + off); | |
59 | } | |
60 | ||
61 | /* | |
62 | * io helpers to access switch registers | |
63 | */ | |
64 | static inline u32 enetsw_readl(struct bcm_enet_priv *priv, u32 off) | |
65 | { | |
66 | return bcm_readl(priv->base + off); | |
67 | } | |
68 | ||
69 | static inline void enetsw_writel(struct bcm_enet_priv *priv, | |
70 | u32 val, u32 off) | |
71 | { | |
72 | bcm_writel(val, priv->base + off); | |
73 | } | |
74 | ||
75 | static inline u16 enetsw_readw(struct bcm_enet_priv *priv, u32 off) | |
76 | { | |
77 | return bcm_readw(priv->base + off); | |
78 | } | |
79 | ||
80 | static inline void enetsw_writew(struct bcm_enet_priv *priv, | |
81 | u16 val, u32 off) | |
82 | { | |
83 | bcm_writew(val, priv->base + off); | |
84 | } | |
85 | ||
86 | static inline u8 enetsw_readb(struct bcm_enet_priv *priv, u32 off) | |
87 | { | |
88 | return bcm_readb(priv->base + off); | |
89 | } | |
90 | ||
91 | static inline void enetsw_writeb(struct bcm_enet_priv *priv, | |
92 | u8 val, u32 off) | |
93 | { | |
94 | bcm_writeb(val, priv->base + off); | |
95 | } | |
96 | ||
97 | ||
98 | /* io helpers to access shared registers */ | |
99 | static inline u32 enet_dma_readl(struct bcm_enet_priv *priv, u32 off) | |
100 | { | |
101 | return bcm_readl(bcm_enet_shared_base[0] + off); | |
102 | } | |
103 | ||
104 | static inline void enet_dma_writel(struct bcm_enet_priv *priv, | |
105 | u32 val, u32 off) | |
106 | { | |
107 | bcm_writel(val, bcm_enet_shared_base[0] + off); | |
108 | } | |
109 | ||
110 | static inline u32 enet_dmac_readl(struct bcm_enet_priv *priv, u32 off, int chan) | |
111 | { | |
112 | return bcm_readl(bcm_enet_shared_base[1] + | |
113 | bcm63xx_enetdmacreg(off) + chan * priv->dma_chan_width); | |
114 | } | |
115 | ||
116 | static inline void enet_dmac_writel(struct bcm_enet_priv *priv, | |
117 | u32 val, u32 off, int chan) | |
118 | { | |
119 | bcm_writel(val, bcm_enet_shared_base[1] + | |
120 | bcm63xx_enetdmacreg(off) + chan * priv->dma_chan_width); | |
121 | } | |
122 | ||
123 | static inline u32 enet_dmas_readl(struct bcm_enet_priv *priv, u32 off, int chan) | |
124 | { | |
125 | return bcm_readl(bcm_enet_shared_base[2] + off + chan * priv->dma_chan_width); | |
126 | } | |
127 | ||
128 | static inline void enet_dmas_writel(struct bcm_enet_priv *priv, | |
129 | u32 val, u32 off, int chan) | |
130 | { | |
131 | bcm_writel(val, bcm_enet_shared_base[2] + off + chan * priv->dma_chan_width); | |
132 | } | |
133 | ||
134 | /* | |
135 | * write given data into mii register and wait for transfer to end | |
136 | * with timeout (average measured transfer time is 25us) | |
137 | */ | |
138 | static int do_mdio_op(struct bcm_enet_priv *priv, unsigned int data) | |
139 | { | |
140 | int limit; | |
141 | ||
142 | /* make sure mii interrupt status is cleared */ | |
143 | enet_writel(priv, ENET_IR_MII, ENET_IR_REG); | |
144 | ||
145 | enet_writel(priv, data, ENET_MIIDATA_REG); | |
146 | wmb(); | |
147 | ||
148 | /* busy wait on mii interrupt bit, with timeout */ | |
149 | limit = 1000; | |
150 | do { | |
151 | if (enet_readl(priv, ENET_IR_REG) & ENET_IR_MII) | |
152 | break; | |
153 | udelay(1); | |
154 | } while (limit-- > 0); | |
155 | ||
156 | return (limit < 0) ? 1 : 0; | |
157 | } | |
158 | ||
159 | /* | |
160 | * MII internal read callback | |
161 | */ | |
162 | static int bcm_enet_mdio_read(struct bcm_enet_priv *priv, int mii_id, | |
163 | int regnum) | |
164 | { | |
165 | u32 tmp, val; | |
166 | ||
167 | tmp = regnum << ENET_MIIDATA_REG_SHIFT; | |
168 | tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT; | |
169 | tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT; | |
170 | tmp |= ENET_MIIDATA_OP_READ_MASK; | |
171 | ||
172 | if (do_mdio_op(priv, tmp)) | |
173 | return -1; | |
174 | ||
175 | val = enet_readl(priv, ENET_MIIDATA_REG); | |
176 | val &= 0xffff; | |
177 | return val; | |
178 | } | |
179 | ||
180 | /* | |
181 | * MII internal write callback | |
182 | */ | |
183 | static int bcm_enet_mdio_write(struct bcm_enet_priv *priv, int mii_id, | |
184 | int regnum, u16 value) | |
185 | { | |
186 | u32 tmp; | |
187 | ||
188 | tmp = (value & 0xffff) << ENET_MIIDATA_DATA_SHIFT; | |
189 | tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT; | |
190 | tmp |= regnum << ENET_MIIDATA_REG_SHIFT; | |
191 | tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT; | |
192 | tmp |= ENET_MIIDATA_OP_WRITE_MASK; | |
193 | ||
194 | (void)do_mdio_op(priv, tmp); | |
195 | return 0; | |
196 | } | |
197 | ||
198 | /* | |
199 | * MII read callback from phylib | |
200 | */ | |
201 | static int bcm_enet_mdio_read_phylib(struct mii_bus *bus, int mii_id, | |
202 | int regnum) | |
203 | { | |
204 | return bcm_enet_mdio_read(bus->priv, mii_id, regnum); | |
205 | } | |
206 | ||
207 | /* | |
208 | * MII write callback from phylib | |
209 | */ | |
210 | static int bcm_enet_mdio_write_phylib(struct mii_bus *bus, int mii_id, | |
211 | int regnum, u16 value) | |
212 | { | |
213 | return bcm_enet_mdio_write(bus->priv, mii_id, regnum, value); | |
214 | } | |
215 | ||
216 | /* | |
217 | * MII read callback from mii core | |
218 | */ | |
219 | static int bcm_enet_mdio_read_mii(struct net_device *dev, int mii_id, | |
220 | int regnum) | |
221 | { | |
222 | return bcm_enet_mdio_read(netdev_priv(dev), mii_id, regnum); | |
223 | } | |
224 | ||
225 | /* | |
226 | * MII write callback from mii core | |
227 | */ | |
228 | static void bcm_enet_mdio_write_mii(struct net_device *dev, int mii_id, | |
229 | int regnum, int value) | |
230 | { | |
231 | bcm_enet_mdio_write(netdev_priv(dev), mii_id, regnum, value); | |
232 | } | |
233 | ||
234 | /* | |
235 | * refill rx queue | |
236 | */ | |
237 | static int bcm_enet_refill_rx(struct net_device *dev) | |
238 | { | |
239 | struct bcm_enet_priv *priv; | |
240 | ||
241 | priv = netdev_priv(dev); | |
242 | ||
243 | while (priv->rx_desc_count < priv->rx_ring_size) { | |
244 | struct bcm_enet_desc *desc; | |
245 | struct sk_buff *skb; | |
246 | dma_addr_t p; | |
247 | int desc_idx; | |
248 | u32 len_stat; | |
249 | ||
250 | desc_idx = priv->rx_dirty_desc; | |
251 | desc = &priv->rx_desc_cpu[desc_idx]; | |
252 | ||
253 | if (!priv->rx_skb[desc_idx]) { | |
254 | skb = netdev_alloc_skb(dev, priv->rx_skb_size); | |
255 | if (!skb) | |
256 | break; | |
257 | priv->rx_skb[desc_idx] = skb; | |
258 | p = dma_map_single(&priv->pdev->dev, skb->data, | |
259 | priv->rx_skb_size, | |
260 | DMA_FROM_DEVICE); | |
261 | desc->address = p; | |
262 | } | |
263 | ||
264 | len_stat = priv->rx_skb_size << DMADESC_LENGTH_SHIFT; | |
265 | len_stat |= DMADESC_OWNER_MASK; | |
266 | if (priv->rx_dirty_desc == priv->rx_ring_size - 1) { | |
267 | len_stat |= (DMADESC_WRAP_MASK >> priv->dma_desc_shift); | |
268 | priv->rx_dirty_desc = 0; | |
269 | } else { | |
270 | priv->rx_dirty_desc++; | |
271 | } | |
272 | wmb(); | |
273 | desc->len_stat = len_stat; | |
274 | ||
275 | priv->rx_desc_count++; | |
276 | ||
277 | /* tell dma engine we allocated one buffer */ | |
278 | if (priv->dma_has_sram) | |
279 | enet_dma_writel(priv, 1, ENETDMA_BUFALLOC_REG(priv->rx_chan)); | |
280 | else | |
281 | enet_dmac_writel(priv, 1, ENETDMAC_BUFALLOC, priv->rx_chan); | |
282 | } | |
283 | ||
284 | /* If rx ring is still empty, set a timer to try allocating | |
285 | * again at a later time. */ | |
286 | if (priv->rx_desc_count == 0 && netif_running(dev)) { | |
287 | dev_warn(&priv->pdev->dev, "unable to refill rx ring\n"); | |
288 | priv->rx_timeout.expires = jiffies + HZ; | |
289 | add_timer(&priv->rx_timeout); | |
290 | } | |
291 | ||
292 | return 0; | |
293 | } | |
294 | ||
295 | /* | |
296 | * timer callback to defer refill rx queue in case we're OOM | |
297 | */ | |
298 | static void bcm_enet_refill_rx_timer(unsigned long data) | |
299 | { | |
300 | struct net_device *dev; | |
301 | struct bcm_enet_priv *priv; | |
302 | ||
303 | dev = (struct net_device *)data; | |
304 | priv = netdev_priv(dev); | |
305 | ||
306 | spin_lock(&priv->rx_lock); | |
307 | bcm_enet_refill_rx((struct net_device *)data); | |
308 | spin_unlock(&priv->rx_lock); | |
309 | } | |
310 | ||
311 | /* | |
312 | * extract packet from rx queue | |
313 | */ | |
314 | static int bcm_enet_receive_queue(struct net_device *dev, int budget) | |
315 | { | |
316 | struct bcm_enet_priv *priv; | |
317 | struct device *kdev; | |
318 | int processed; | |
319 | ||
320 | priv = netdev_priv(dev); | |
321 | kdev = &priv->pdev->dev; | |
322 | processed = 0; | |
323 | ||
324 | /* don't scan ring further than number of refilled | |
325 | * descriptor */ | |
326 | if (budget > priv->rx_desc_count) | |
327 | budget = priv->rx_desc_count; | |
328 | ||
329 | do { | |
330 | struct bcm_enet_desc *desc; | |
331 | struct sk_buff *skb; | |
332 | int desc_idx; | |
333 | u32 len_stat; | |
334 | unsigned int len; | |
335 | ||
336 | desc_idx = priv->rx_curr_desc; | |
337 | desc = &priv->rx_desc_cpu[desc_idx]; | |
338 | ||
339 | /* make sure we actually read the descriptor status at | |
340 | * each loop */ | |
341 | rmb(); | |
342 | ||
343 | len_stat = desc->len_stat; | |
344 | ||
345 | /* break if dma ownership belongs to hw */ | |
346 | if (len_stat & DMADESC_OWNER_MASK) | |
347 | break; | |
348 | ||
349 | processed++; | |
350 | priv->rx_curr_desc++; | |
351 | if (priv->rx_curr_desc == priv->rx_ring_size) | |
352 | priv->rx_curr_desc = 0; | |
353 | priv->rx_desc_count--; | |
354 | ||
355 | /* if the packet does not have start of packet _and_ | |
356 | * end of packet flag set, then just recycle it */ | |
357 | if ((len_stat & (DMADESC_ESOP_MASK >> priv->dma_desc_shift)) != | |
358 | (DMADESC_ESOP_MASK >> priv->dma_desc_shift)) { | |
359 | dev->stats.rx_dropped++; | |
360 | continue; | |
361 | } | |
362 | ||
363 | /* recycle packet if it's marked as bad */ | |
364 | if (!priv->enet_is_sw && | |
365 | unlikely(len_stat & DMADESC_ERR_MASK)) { | |
366 | dev->stats.rx_errors++; | |
367 | ||
368 | if (len_stat & DMADESC_OVSIZE_MASK) | |
369 | dev->stats.rx_length_errors++; | |
370 | if (len_stat & DMADESC_CRC_MASK) | |
371 | dev->stats.rx_crc_errors++; | |
372 | if (len_stat & DMADESC_UNDER_MASK) | |
373 | dev->stats.rx_frame_errors++; | |
374 | if (len_stat & DMADESC_OV_MASK) | |
375 | dev->stats.rx_fifo_errors++; | |
376 | continue; | |
377 | } | |
378 | ||
379 | /* valid packet */ | |
380 | skb = priv->rx_skb[desc_idx]; | |
381 | len = (len_stat & DMADESC_LENGTH_MASK) >> DMADESC_LENGTH_SHIFT; | |
382 | /* don't include FCS */ | |
383 | len -= 4; | |
384 | ||
385 | if (len < copybreak) { | |
386 | struct sk_buff *nskb; | |
387 | ||
388 | nskb = napi_alloc_skb(&priv->napi, len); | |
389 | if (!nskb) { | |
390 | /* forget packet, just rearm desc */ | |
391 | dev->stats.rx_dropped++; | |
392 | continue; | |
393 | } | |
394 | ||
395 | dma_sync_single_for_cpu(kdev, desc->address, | |
396 | len, DMA_FROM_DEVICE); | |
397 | memcpy(nskb->data, skb->data, len); | |
398 | dma_sync_single_for_device(kdev, desc->address, | |
399 | len, DMA_FROM_DEVICE); | |
400 | skb = nskb; | |
401 | } else { | |
402 | dma_unmap_single(&priv->pdev->dev, desc->address, | |
403 | priv->rx_skb_size, DMA_FROM_DEVICE); | |
404 | priv->rx_skb[desc_idx] = NULL; | |
405 | } | |
406 | ||
407 | skb_put(skb, len); | |
408 | skb->protocol = eth_type_trans(skb, dev); | |
409 | dev->stats.rx_packets++; | |
410 | dev->stats.rx_bytes += len; | |
411 | netif_receive_skb(skb); | |
412 | ||
413 | } while (--budget > 0); | |
414 | ||
415 | if (processed || !priv->rx_desc_count) { | |
416 | bcm_enet_refill_rx(dev); | |
417 | ||
418 | /* kick rx dma */ | |
419 | enet_dmac_writel(priv, priv->dma_chan_en_mask, | |
420 | ENETDMAC_CHANCFG, priv->rx_chan); | |
421 | } | |
422 | ||
423 | return processed; | |
424 | } | |
425 | ||
426 | ||
427 | /* | |
428 | * try to or force reclaim of transmitted buffers | |
429 | */ | |
430 | static int bcm_enet_tx_reclaim(struct net_device *dev, int force) | |
431 | { | |
432 | struct bcm_enet_priv *priv; | |
433 | int released; | |
434 | ||
435 | priv = netdev_priv(dev); | |
436 | released = 0; | |
437 | ||
438 | while (priv->tx_desc_count < priv->tx_ring_size) { | |
439 | struct bcm_enet_desc *desc; | |
440 | struct sk_buff *skb; | |
441 | ||
442 | /* We run in a bh and fight against start_xmit, which | |
443 | * is called with bh disabled */ | |
444 | spin_lock(&priv->tx_lock); | |
445 | ||
446 | desc = &priv->tx_desc_cpu[priv->tx_dirty_desc]; | |
447 | ||
448 | if (!force && (desc->len_stat & DMADESC_OWNER_MASK)) { | |
449 | spin_unlock(&priv->tx_lock); | |
450 | break; | |
451 | } | |
452 | ||
453 | /* ensure other field of the descriptor were not read | |
454 | * before we checked ownership */ | |
455 | rmb(); | |
456 | ||
457 | skb = priv->tx_skb[priv->tx_dirty_desc]; | |
458 | priv->tx_skb[priv->tx_dirty_desc] = NULL; | |
459 | dma_unmap_single(&priv->pdev->dev, desc->address, skb->len, | |
460 | DMA_TO_DEVICE); | |
461 | ||
462 | priv->tx_dirty_desc++; | |
463 | if (priv->tx_dirty_desc == priv->tx_ring_size) | |
464 | priv->tx_dirty_desc = 0; | |
465 | priv->tx_desc_count++; | |
466 | ||
467 | spin_unlock(&priv->tx_lock); | |
468 | ||
469 | if (desc->len_stat & DMADESC_UNDER_MASK) | |
470 | dev->stats.tx_errors++; | |
471 | ||
472 | dev_kfree_skb(skb); | |
473 | released++; | |
474 | } | |
475 | ||
476 | if (netif_queue_stopped(dev) && released) | |
477 | netif_wake_queue(dev); | |
478 | ||
479 | return released; | |
480 | } | |
481 | ||
482 | /* | |
483 | * poll func, called by network core | |
484 | */ | |
485 | static int bcm_enet_poll(struct napi_struct *napi, int budget) | |
486 | { | |
487 | struct bcm_enet_priv *priv; | |
488 | struct net_device *dev; | |
489 | int rx_work_done; | |
490 | ||
491 | priv = container_of(napi, struct bcm_enet_priv, napi); | |
492 | dev = priv->net_dev; | |
493 | ||
494 | /* ack interrupts */ | |
495 | enet_dmac_writel(priv, priv->dma_chan_int_mask, | |
496 | ENETDMAC_IR, priv->rx_chan); | |
497 | enet_dmac_writel(priv, priv->dma_chan_int_mask, | |
498 | ENETDMAC_IR, priv->tx_chan); | |
499 | ||
500 | /* reclaim sent skb */ | |
501 | bcm_enet_tx_reclaim(dev, 0); | |
502 | ||
503 | spin_lock(&priv->rx_lock); | |
504 | rx_work_done = bcm_enet_receive_queue(dev, budget); | |
505 | spin_unlock(&priv->rx_lock); | |
506 | ||
507 | if (rx_work_done >= budget) { | |
508 | /* rx queue is not yet empty/clean */ | |
509 | return rx_work_done; | |
510 | } | |
511 | ||
512 | /* no more packet in rx/tx queue, remove device from poll | |
513 | * queue */ | |
514 | napi_complete(napi); | |
515 | ||
516 | /* restore rx/tx interrupt */ | |
517 | enet_dmac_writel(priv, priv->dma_chan_int_mask, | |
518 | ENETDMAC_IRMASK, priv->rx_chan); | |
519 | enet_dmac_writel(priv, priv->dma_chan_int_mask, | |
520 | ENETDMAC_IRMASK, priv->tx_chan); | |
521 | ||
522 | return rx_work_done; | |
523 | } | |
524 | ||
525 | /* | |
526 | * mac interrupt handler | |
527 | */ | |
528 | static irqreturn_t bcm_enet_isr_mac(int irq, void *dev_id) | |
529 | { | |
530 | struct net_device *dev; | |
531 | struct bcm_enet_priv *priv; | |
532 | u32 stat; | |
533 | ||
534 | dev = dev_id; | |
535 | priv = netdev_priv(dev); | |
536 | ||
537 | stat = enet_readl(priv, ENET_IR_REG); | |
538 | if (!(stat & ENET_IR_MIB)) | |
539 | return IRQ_NONE; | |
540 | ||
541 | /* clear & mask interrupt */ | |
542 | enet_writel(priv, ENET_IR_MIB, ENET_IR_REG); | |
543 | enet_writel(priv, 0, ENET_IRMASK_REG); | |
544 | ||
545 | /* read mib registers in workqueue */ | |
546 | schedule_work(&priv->mib_update_task); | |
547 | ||
548 | return IRQ_HANDLED; | |
549 | } | |
550 | ||
551 | /* | |
552 | * rx/tx dma interrupt handler | |
553 | */ | |
554 | static irqreturn_t bcm_enet_isr_dma(int irq, void *dev_id) | |
555 | { | |
556 | struct net_device *dev; | |
557 | struct bcm_enet_priv *priv; | |
558 | ||
559 | dev = dev_id; | |
560 | priv = netdev_priv(dev); | |
561 | ||
562 | /* mask rx/tx interrupts */ | |
563 | enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan); | |
564 | enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan); | |
565 | ||
566 | napi_schedule(&priv->napi); | |
567 | ||
568 | return IRQ_HANDLED; | |
569 | } | |
570 | ||
571 | /* | |
572 | * tx request callback | |
573 | */ | |
574 | static int bcm_enet_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
575 | { | |
576 | struct bcm_enet_priv *priv; | |
577 | struct bcm_enet_desc *desc; | |
578 | u32 len_stat; | |
579 | int ret; | |
580 | ||
581 | priv = netdev_priv(dev); | |
582 | ||
583 | /* lock against tx reclaim */ | |
584 | spin_lock(&priv->tx_lock); | |
585 | ||
586 | /* make sure the tx hw queue is not full, should not happen | |
587 | * since we stop queue before it's the case */ | |
588 | if (unlikely(!priv->tx_desc_count)) { | |
589 | netif_stop_queue(dev); | |
590 | dev_err(&priv->pdev->dev, "xmit called with no tx desc " | |
591 | "available?\n"); | |
592 | ret = NETDEV_TX_BUSY; | |
593 | goto out_unlock; | |
594 | } | |
595 | ||
596 | /* pad small packets sent on a switch device */ | |
597 | if (priv->enet_is_sw && skb->len < 64) { | |
598 | int needed = 64 - skb->len; | |
599 | char *data; | |
600 | ||
601 | if (unlikely(skb_tailroom(skb) < needed)) { | |
602 | struct sk_buff *nskb; | |
603 | ||
604 | nskb = skb_copy_expand(skb, 0, needed, GFP_ATOMIC); | |
605 | if (!nskb) { | |
606 | ret = NETDEV_TX_BUSY; | |
607 | goto out_unlock; | |
608 | } | |
609 | dev_kfree_skb(skb); | |
610 | skb = nskb; | |
611 | } | |
612 | data = skb_put(skb, needed); | |
613 | memset(data, 0, needed); | |
614 | } | |
615 | ||
616 | /* point to the next available desc */ | |
617 | desc = &priv->tx_desc_cpu[priv->tx_curr_desc]; | |
618 | priv->tx_skb[priv->tx_curr_desc] = skb; | |
619 | ||
620 | /* fill descriptor */ | |
621 | desc->address = dma_map_single(&priv->pdev->dev, skb->data, skb->len, | |
622 | DMA_TO_DEVICE); | |
623 | ||
624 | len_stat = (skb->len << DMADESC_LENGTH_SHIFT) & DMADESC_LENGTH_MASK; | |
625 | len_stat |= (DMADESC_ESOP_MASK >> priv->dma_desc_shift) | | |
626 | DMADESC_APPEND_CRC | | |
627 | DMADESC_OWNER_MASK; | |
628 | ||
629 | priv->tx_curr_desc++; | |
630 | if (priv->tx_curr_desc == priv->tx_ring_size) { | |
631 | priv->tx_curr_desc = 0; | |
632 | len_stat |= (DMADESC_WRAP_MASK >> priv->dma_desc_shift); | |
633 | } | |
634 | priv->tx_desc_count--; | |
635 | ||
636 | /* dma might be already polling, make sure we update desc | |
637 | * fields in correct order */ | |
638 | wmb(); | |
639 | desc->len_stat = len_stat; | |
640 | wmb(); | |
641 | ||
642 | /* kick tx dma */ | |
643 | enet_dmac_writel(priv, priv->dma_chan_en_mask, | |
644 | ENETDMAC_CHANCFG, priv->tx_chan); | |
645 | ||
646 | /* stop queue if no more desc available */ | |
647 | if (!priv->tx_desc_count) | |
648 | netif_stop_queue(dev); | |
649 | ||
650 | dev->stats.tx_bytes += skb->len; | |
651 | dev->stats.tx_packets++; | |
652 | ret = NETDEV_TX_OK; | |
653 | ||
654 | out_unlock: | |
655 | spin_unlock(&priv->tx_lock); | |
656 | return ret; | |
657 | } | |
658 | ||
659 | /* | |
660 | * Change the interface's mac address. | |
661 | */ | |
662 | static int bcm_enet_set_mac_address(struct net_device *dev, void *p) | |
663 | { | |
664 | struct bcm_enet_priv *priv; | |
665 | struct sockaddr *addr = p; | |
666 | u32 val; | |
667 | ||
668 | priv = netdev_priv(dev); | |
669 | memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); | |
670 | ||
671 | /* use perfect match register 0 to store my mac address */ | |
672 | val = (dev->dev_addr[2] << 24) | (dev->dev_addr[3] << 16) | | |
673 | (dev->dev_addr[4] << 8) | dev->dev_addr[5]; | |
674 | enet_writel(priv, val, ENET_PML_REG(0)); | |
675 | ||
676 | val = (dev->dev_addr[0] << 8 | dev->dev_addr[1]); | |
677 | val |= ENET_PMH_DATAVALID_MASK; | |
678 | enet_writel(priv, val, ENET_PMH_REG(0)); | |
679 | ||
680 | return 0; | |
681 | } | |
682 | ||
683 | /* | |
684 | * Change rx mode (promiscuous/allmulti) and update multicast list | |
685 | */ | |
686 | static void bcm_enet_set_multicast_list(struct net_device *dev) | |
687 | { | |
688 | struct bcm_enet_priv *priv; | |
689 | struct netdev_hw_addr *ha; | |
690 | u32 val; | |
691 | int i; | |
692 | ||
693 | priv = netdev_priv(dev); | |
694 | ||
695 | val = enet_readl(priv, ENET_RXCFG_REG); | |
696 | ||
697 | if (dev->flags & IFF_PROMISC) | |
698 | val |= ENET_RXCFG_PROMISC_MASK; | |
699 | else | |
700 | val &= ~ENET_RXCFG_PROMISC_MASK; | |
701 | ||
702 | /* only 3 perfect match registers left, first one is used for | |
703 | * own mac address */ | |
704 | if ((dev->flags & IFF_ALLMULTI) || netdev_mc_count(dev) > 3) | |
705 | val |= ENET_RXCFG_ALLMCAST_MASK; | |
706 | else | |
707 | val &= ~ENET_RXCFG_ALLMCAST_MASK; | |
708 | ||
709 | /* no need to set perfect match registers if we catch all | |
710 | * multicast */ | |
711 | if (val & ENET_RXCFG_ALLMCAST_MASK) { | |
712 | enet_writel(priv, val, ENET_RXCFG_REG); | |
713 | return; | |
714 | } | |
715 | ||
716 | i = 0; | |
717 | netdev_for_each_mc_addr(ha, dev) { | |
718 | u8 *dmi_addr; | |
719 | u32 tmp; | |
720 | ||
721 | if (i == 3) | |
722 | break; | |
723 | /* update perfect match registers */ | |
724 | dmi_addr = ha->addr; | |
725 | tmp = (dmi_addr[2] << 24) | (dmi_addr[3] << 16) | | |
726 | (dmi_addr[4] << 8) | dmi_addr[5]; | |
727 | enet_writel(priv, tmp, ENET_PML_REG(i + 1)); | |
728 | ||
729 | tmp = (dmi_addr[0] << 8 | dmi_addr[1]); | |
730 | tmp |= ENET_PMH_DATAVALID_MASK; | |
731 | enet_writel(priv, tmp, ENET_PMH_REG(i++ + 1)); | |
732 | } | |
733 | ||
734 | for (; i < 3; i++) { | |
735 | enet_writel(priv, 0, ENET_PML_REG(i + 1)); | |
736 | enet_writel(priv, 0, ENET_PMH_REG(i + 1)); | |
737 | } | |
738 | ||
739 | enet_writel(priv, val, ENET_RXCFG_REG); | |
740 | } | |
741 | ||
742 | /* | |
743 | * set mac duplex parameters | |
744 | */ | |
745 | static void bcm_enet_set_duplex(struct bcm_enet_priv *priv, int fullduplex) | |
746 | { | |
747 | u32 val; | |
748 | ||
749 | val = enet_readl(priv, ENET_TXCTL_REG); | |
750 | if (fullduplex) | |
751 | val |= ENET_TXCTL_FD_MASK; | |
752 | else | |
753 | val &= ~ENET_TXCTL_FD_MASK; | |
754 | enet_writel(priv, val, ENET_TXCTL_REG); | |
755 | } | |
756 | ||
757 | /* | |
758 | * set mac flow control parameters | |
759 | */ | |
760 | static void bcm_enet_set_flow(struct bcm_enet_priv *priv, int rx_en, int tx_en) | |
761 | { | |
762 | u32 val; | |
763 | ||
764 | /* rx flow control (pause frame handling) */ | |
765 | val = enet_readl(priv, ENET_RXCFG_REG); | |
766 | if (rx_en) | |
767 | val |= ENET_RXCFG_ENFLOW_MASK; | |
768 | else | |
769 | val &= ~ENET_RXCFG_ENFLOW_MASK; | |
770 | enet_writel(priv, val, ENET_RXCFG_REG); | |
771 | ||
772 | if (!priv->dma_has_sram) | |
773 | return; | |
774 | ||
775 | /* tx flow control (pause frame generation) */ | |
776 | val = enet_dma_readl(priv, ENETDMA_CFG_REG); | |
777 | if (tx_en) | |
778 | val |= ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan); | |
779 | else | |
780 | val &= ~ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan); | |
781 | enet_dma_writel(priv, val, ENETDMA_CFG_REG); | |
782 | } | |
783 | ||
784 | /* | |
785 | * link changed callback (from phylib) | |
786 | */ | |
787 | static void bcm_enet_adjust_phy_link(struct net_device *dev) | |
788 | { | |
789 | struct bcm_enet_priv *priv; | |
790 | struct phy_device *phydev; | |
791 | int status_changed; | |
792 | ||
793 | priv = netdev_priv(dev); | |
794 | phydev = dev->phydev; | |
795 | status_changed = 0; | |
796 | ||
797 | if (priv->old_link != phydev->link) { | |
798 | status_changed = 1; | |
799 | priv->old_link = phydev->link; | |
800 | } | |
801 | ||
802 | /* reflect duplex change in mac configuration */ | |
803 | if (phydev->link && phydev->duplex != priv->old_duplex) { | |
804 | bcm_enet_set_duplex(priv, | |
805 | (phydev->duplex == DUPLEX_FULL) ? 1 : 0); | |
806 | status_changed = 1; | |
807 | priv->old_duplex = phydev->duplex; | |
808 | } | |
809 | ||
810 | /* enable flow control if remote advertise it (trust phylib to | |
811 | * check that duplex is full */ | |
812 | if (phydev->link && phydev->pause != priv->old_pause) { | |
813 | int rx_pause_en, tx_pause_en; | |
814 | ||
815 | if (phydev->pause) { | |
816 | /* pause was advertised by lpa and us */ | |
817 | rx_pause_en = 1; | |
818 | tx_pause_en = 1; | |
819 | } else if (!priv->pause_auto) { | |
820 | /* pause setting overrided by user */ | |
821 | rx_pause_en = priv->pause_rx; | |
822 | tx_pause_en = priv->pause_tx; | |
823 | } else { | |
824 | rx_pause_en = 0; | |
825 | tx_pause_en = 0; | |
826 | } | |
827 | ||
828 | bcm_enet_set_flow(priv, rx_pause_en, tx_pause_en); | |
829 | status_changed = 1; | |
830 | priv->old_pause = phydev->pause; | |
831 | } | |
832 | ||
833 | if (status_changed) { | |
834 | pr_info("%s: link %s", dev->name, phydev->link ? | |
835 | "UP" : "DOWN"); | |
836 | if (phydev->link) | |
837 | pr_cont(" - %d/%s - flow control %s", phydev->speed, | |
838 | DUPLEX_FULL == phydev->duplex ? "full" : "half", | |
839 | phydev->pause == 1 ? "rx&tx" : "off"); | |
840 | ||
841 | pr_cont("\n"); | |
842 | } | |
843 | } | |
844 | ||
845 | /* | |
846 | * link changed callback (if phylib is not used) | |
847 | */ | |
848 | static void bcm_enet_adjust_link(struct net_device *dev) | |
849 | { | |
850 | struct bcm_enet_priv *priv; | |
851 | ||
852 | priv = netdev_priv(dev); | |
853 | bcm_enet_set_duplex(priv, priv->force_duplex_full); | |
854 | bcm_enet_set_flow(priv, priv->pause_rx, priv->pause_tx); | |
855 | netif_carrier_on(dev); | |
856 | ||
857 | pr_info("%s: link forced UP - %d/%s - flow control %s/%s\n", | |
858 | dev->name, | |
859 | priv->force_speed_100 ? 100 : 10, | |
860 | priv->force_duplex_full ? "full" : "half", | |
861 | priv->pause_rx ? "rx" : "off", | |
862 | priv->pause_tx ? "tx" : "off"); | |
863 | } | |
864 | ||
865 | /* | |
866 | * open callback, allocate dma rings & buffers and start rx operation | |
867 | */ | |
868 | static int bcm_enet_open(struct net_device *dev) | |
869 | { | |
870 | struct bcm_enet_priv *priv; | |
871 | struct sockaddr addr; | |
872 | struct device *kdev; | |
873 | struct phy_device *phydev; | |
874 | int i, ret; | |
875 | unsigned int size; | |
876 | char phy_id[MII_BUS_ID_SIZE + 3]; | |
877 | void *p; | |
878 | u32 val; | |
879 | ||
880 | priv = netdev_priv(dev); | |
881 | kdev = &priv->pdev->dev; | |
882 | ||
883 | if (priv->has_phy) { | |
884 | /* connect to PHY */ | |
885 | snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, | |
886 | priv->mii_bus->id, priv->phy_id); | |
887 | ||
888 | phydev = phy_connect(dev, phy_id, bcm_enet_adjust_phy_link, | |
889 | PHY_INTERFACE_MODE_MII); | |
890 | ||
891 | if (IS_ERR(phydev)) { | |
892 | dev_err(kdev, "could not attach to PHY\n"); | |
893 | return PTR_ERR(phydev); | |
894 | } | |
895 | ||
896 | /* mask with MAC supported features */ | |
897 | phydev->supported &= (SUPPORTED_10baseT_Half | | |
898 | SUPPORTED_10baseT_Full | | |
899 | SUPPORTED_100baseT_Half | | |
900 | SUPPORTED_100baseT_Full | | |
901 | SUPPORTED_Autoneg | | |
902 | SUPPORTED_Pause | | |
903 | SUPPORTED_MII); | |
904 | phydev->advertising = phydev->supported; | |
905 | ||
906 | if (priv->pause_auto && priv->pause_rx && priv->pause_tx) | |
907 | phydev->advertising |= SUPPORTED_Pause; | |
908 | else | |
909 | phydev->advertising &= ~SUPPORTED_Pause; | |
910 | ||
911 | phy_attached_info(phydev); | |
912 | ||
913 | priv->old_link = 0; | |
914 | priv->old_duplex = -1; | |
915 | priv->old_pause = -1; | |
916 | } else { | |
917 | phydev = NULL; | |
918 | } | |
919 | ||
920 | /* mask all interrupts and request them */ | |
921 | enet_writel(priv, 0, ENET_IRMASK_REG); | |
922 | enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan); | |
923 | enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan); | |
924 | ||
925 | ret = request_irq(dev->irq, bcm_enet_isr_mac, 0, dev->name, dev); | |
926 | if (ret) | |
927 | goto out_phy_disconnect; | |
928 | ||
929 | ret = request_irq(priv->irq_rx, bcm_enet_isr_dma, 0, | |
930 | dev->name, dev); | |
931 | if (ret) | |
932 | goto out_freeirq; | |
933 | ||
934 | ret = request_irq(priv->irq_tx, bcm_enet_isr_dma, | |
935 | 0, dev->name, dev); | |
936 | if (ret) | |
937 | goto out_freeirq_rx; | |
938 | ||
939 | /* initialize perfect match registers */ | |
940 | for (i = 0; i < 4; i++) { | |
941 | enet_writel(priv, 0, ENET_PML_REG(i)); | |
942 | enet_writel(priv, 0, ENET_PMH_REG(i)); | |
943 | } | |
944 | ||
945 | /* write device mac address */ | |
946 | memcpy(addr.sa_data, dev->dev_addr, ETH_ALEN); | |
947 | bcm_enet_set_mac_address(dev, &addr); | |
948 | ||
949 | /* allocate rx dma ring */ | |
950 | size = priv->rx_ring_size * sizeof(struct bcm_enet_desc); | |
951 | p = dma_zalloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL); | |
952 | if (!p) { | |
953 | ret = -ENOMEM; | |
954 | goto out_freeirq_tx; | |
955 | } | |
956 | ||
957 | priv->rx_desc_alloc_size = size; | |
958 | priv->rx_desc_cpu = p; | |
959 | ||
960 | /* allocate tx dma ring */ | |
961 | size = priv->tx_ring_size * sizeof(struct bcm_enet_desc); | |
962 | p = dma_zalloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL); | |
963 | if (!p) { | |
964 | ret = -ENOMEM; | |
965 | goto out_free_rx_ring; | |
966 | } | |
967 | ||
968 | priv->tx_desc_alloc_size = size; | |
969 | priv->tx_desc_cpu = p; | |
970 | ||
971 | priv->tx_skb = kcalloc(priv->tx_ring_size, sizeof(struct sk_buff *), | |
972 | GFP_KERNEL); | |
973 | if (!priv->tx_skb) { | |
974 | ret = -ENOMEM; | |
975 | goto out_free_tx_ring; | |
976 | } | |
977 | ||
978 | priv->tx_desc_count = priv->tx_ring_size; | |
979 | priv->tx_dirty_desc = 0; | |
980 | priv->tx_curr_desc = 0; | |
981 | spin_lock_init(&priv->tx_lock); | |
982 | ||
983 | /* init & fill rx ring with skbs */ | |
984 | priv->rx_skb = kcalloc(priv->rx_ring_size, sizeof(struct sk_buff *), | |
985 | GFP_KERNEL); | |
986 | if (!priv->rx_skb) { | |
987 | ret = -ENOMEM; | |
988 | goto out_free_tx_skb; | |
989 | } | |
990 | ||
991 | priv->rx_desc_count = 0; | |
992 | priv->rx_dirty_desc = 0; | |
993 | priv->rx_curr_desc = 0; | |
994 | ||
995 | /* initialize flow control buffer allocation */ | |
996 | if (priv->dma_has_sram) | |
997 | enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0, | |
998 | ENETDMA_BUFALLOC_REG(priv->rx_chan)); | |
999 | else | |
1000 | enet_dmac_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0, | |
1001 | ENETDMAC_BUFALLOC, priv->rx_chan); | |
1002 | ||
1003 | if (bcm_enet_refill_rx(dev)) { | |
1004 | dev_err(kdev, "cannot allocate rx skb queue\n"); | |
1005 | ret = -ENOMEM; | |
1006 | goto out; | |
1007 | } | |
1008 | ||
1009 | /* write rx & tx ring addresses */ | |
1010 | if (priv->dma_has_sram) { | |
1011 | enet_dmas_writel(priv, priv->rx_desc_dma, | |
1012 | ENETDMAS_RSTART_REG, priv->rx_chan); | |
1013 | enet_dmas_writel(priv, priv->tx_desc_dma, | |
1014 | ENETDMAS_RSTART_REG, priv->tx_chan); | |
1015 | } else { | |
1016 | enet_dmac_writel(priv, priv->rx_desc_dma, | |
1017 | ENETDMAC_RSTART, priv->rx_chan); | |
1018 | enet_dmac_writel(priv, priv->tx_desc_dma, | |
1019 | ENETDMAC_RSTART, priv->tx_chan); | |
1020 | } | |
1021 | ||
1022 | /* clear remaining state ram for rx & tx channel */ | |
1023 | if (priv->dma_has_sram) { | |
1024 | enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->rx_chan); | |
1025 | enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->tx_chan); | |
1026 | enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->rx_chan); | |
1027 | enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->tx_chan); | |
1028 | enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->rx_chan); | |
1029 | enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->tx_chan); | |
1030 | } else { | |
1031 | enet_dmac_writel(priv, 0, ENETDMAC_FC, priv->rx_chan); | |
1032 | enet_dmac_writel(priv, 0, ENETDMAC_FC, priv->tx_chan); | |
1033 | } | |
1034 | ||
1035 | /* set max rx/tx length */ | |
1036 | enet_writel(priv, priv->hw_mtu, ENET_RXMAXLEN_REG); | |
1037 | enet_writel(priv, priv->hw_mtu, ENET_TXMAXLEN_REG); | |
1038 | ||
1039 | /* set dma maximum burst len */ | |
1040 | enet_dmac_writel(priv, priv->dma_maxburst, | |
1041 | ENETDMAC_MAXBURST, priv->rx_chan); | |
1042 | enet_dmac_writel(priv, priv->dma_maxburst, | |
1043 | ENETDMAC_MAXBURST, priv->tx_chan); | |
1044 | ||
1045 | /* set correct transmit fifo watermark */ | |
1046 | enet_writel(priv, BCMENET_TX_FIFO_TRESH, ENET_TXWMARK_REG); | |
1047 | ||
1048 | /* set flow control low/high threshold to 1/3 / 2/3 */ | |
1049 | if (priv->dma_has_sram) { | |
1050 | val = priv->rx_ring_size / 3; | |
1051 | enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan)); | |
1052 | val = (priv->rx_ring_size * 2) / 3; | |
1053 | enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan)); | |
1054 | } else { | |
1055 | enet_dmac_writel(priv, 5, ENETDMAC_FC, priv->rx_chan); | |
1056 | enet_dmac_writel(priv, priv->rx_ring_size, ENETDMAC_LEN, priv->rx_chan); | |
1057 | enet_dmac_writel(priv, priv->tx_ring_size, ENETDMAC_LEN, priv->tx_chan); | |
1058 | } | |
1059 | ||
1060 | /* all set, enable mac and interrupts, start dma engine and | |
1061 | * kick rx dma channel */ | |
1062 | wmb(); | |
1063 | val = enet_readl(priv, ENET_CTL_REG); | |
1064 | val |= ENET_CTL_ENABLE_MASK; | |
1065 | enet_writel(priv, val, ENET_CTL_REG); | |
1066 | enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG); | |
1067 | enet_dmac_writel(priv, priv->dma_chan_en_mask, | |
1068 | ENETDMAC_CHANCFG, priv->rx_chan); | |
1069 | ||
1070 | /* watch "mib counters about to overflow" interrupt */ | |
1071 | enet_writel(priv, ENET_IR_MIB, ENET_IR_REG); | |
1072 | enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG); | |
1073 | ||
1074 | /* watch "packet transferred" interrupt in rx and tx */ | |
1075 | enet_dmac_writel(priv, priv->dma_chan_int_mask, | |
1076 | ENETDMAC_IR, priv->rx_chan); | |
1077 | enet_dmac_writel(priv, priv->dma_chan_int_mask, | |
1078 | ENETDMAC_IR, priv->tx_chan); | |
1079 | ||
1080 | /* make sure we enable napi before rx interrupt */ | |
1081 | napi_enable(&priv->napi); | |
1082 | ||
1083 | enet_dmac_writel(priv, priv->dma_chan_int_mask, | |
1084 | ENETDMAC_IRMASK, priv->rx_chan); | |
1085 | enet_dmac_writel(priv, priv->dma_chan_int_mask, | |
1086 | ENETDMAC_IRMASK, priv->tx_chan); | |
1087 | ||
1088 | if (phydev) | |
1089 | phy_start(phydev); | |
1090 | else | |
1091 | bcm_enet_adjust_link(dev); | |
1092 | ||
1093 | netif_start_queue(dev); | |
1094 | return 0; | |
1095 | ||
1096 | out: | |
1097 | for (i = 0; i < priv->rx_ring_size; i++) { | |
1098 | struct bcm_enet_desc *desc; | |
1099 | ||
1100 | if (!priv->rx_skb[i]) | |
1101 | continue; | |
1102 | ||
1103 | desc = &priv->rx_desc_cpu[i]; | |
1104 | dma_unmap_single(kdev, desc->address, priv->rx_skb_size, | |
1105 | DMA_FROM_DEVICE); | |
1106 | kfree_skb(priv->rx_skb[i]); | |
1107 | } | |
1108 | kfree(priv->rx_skb); | |
1109 | ||
1110 | out_free_tx_skb: | |
1111 | kfree(priv->tx_skb); | |
1112 | ||
1113 | out_free_tx_ring: | |
1114 | dma_free_coherent(kdev, priv->tx_desc_alloc_size, | |
1115 | priv->tx_desc_cpu, priv->tx_desc_dma); | |
1116 | ||
1117 | out_free_rx_ring: | |
1118 | dma_free_coherent(kdev, priv->rx_desc_alloc_size, | |
1119 | priv->rx_desc_cpu, priv->rx_desc_dma); | |
1120 | ||
1121 | out_freeirq_tx: | |
1122 | free_irq(priv->irq_tx, dev); | |
1123 | ||
1124 | out_freeirq_rx: | |
1125 | free_irq(priv->irq_rx, dev); | |
1126 | ||
1127 | out_freeirq: | |
1128 | free_irq(dev->irq, dev); | |
1129 | ||
1130 | out_phy_disconnect: | |
1131 | if (phydev) | |
1132 | phy_disconnect(phydev); | |
1133 | ||
1134 | return ret; | |
1135 | } | |
1136 | ||
1137 | /* | |
1138 | * disable mac | |
1139 | */ | |
1140 | static void bcm_enet_disable_mac(struct bcm_enet_priv *priv) | |
1141 | { | |
1142 | int limit; | |
1143 | u32 val; | |
1144 | ||
1145 | val = enet_readl(priv, ENET_CTL_REG); | |
1146 | val |= ENET_CTL_DISABLE_MASK; | |
1147 | enet_writel(priv, val, ENET_CTL_REG); | |
1148 | ||
1149 | limit = 1000; | |
1150 | do { | |
1151 | u32 val; | |
1152 | ||
1153 | val = enet_readl(priv, ENET_CTL_REG); | |
1154 | if (!(val & ENET_CTL_DISABLE_MASK)) | |
1155 | break; | |
1156 | udelay(1); | |
1157 | } while (limit--); | |
1158 | } | |
1159 | ||
1160 | /* | |
1161 | * disable dma in given channel | |
1162 | */ | |
1163 | static void bcm_enet_disable_dma(struct bcm_enet_priv *priv, int chan) | |
1164 | { | |
1165 | int limit; | |
1166 | ||
1167 | enet_dmac_writel(priv, 0, ENETDMAC_CHANCFG, chan); | |
1168 | ||
1169 | limit = 1000; | |
1170 | do { | |
1171 | u32 val; | |
1172 | ||
1173 | val = enet_dmac_readl(priv, ENETDMAC_CHANCFG, chan); | |
1174 | if (!(val & ENETDMAC_CHANCFG_EN_MASK)) | |
1175 | break; | |
1176 | udelay(1); | |
1177 | } while (limit--); | |
1178 | } | |
1179 | ||
1180 | /* | |
1181 | * stop callback | |
1182 | */ | |
1183 | static int bcm_enet_stop(struct net_device *dev) | |
1184 | { | |
1185 | struct bcm_enet_priv *priv; | |
1186 | struct device *kdev; | |
1187 | int i; | |
1188 | ||
1189 | priv = netdev_priv(dev); | |
1190 | kdev = &priv->pdev->dev; | |
1191 | ||
1192 | netif_stop_queue(dev); | |
1193 | napi_disable(&priv->napi); | |
1194 | if (priv->has_phy) | |
1195 | phy_stop(dev->phydev); | |
1196 | del_timer_sync(&priv->rx_timeout); | |
1197 | ||
1198 | /* mask all interrupts */ | |
1199 | enet_writel(priv, 0, ENET_IRMASK_REG); | |
1200 | enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan); | |
1201 | enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan); | |
1202 | ||
1203 | /* make sure no mib update is scheduled */ | |
1204 | cancel_work_sync(&priv->mib_update_task); | |
1205 | ||
1206 | /* disable dma & mac */ | |
1207 | bcm_enet_disable_dma(priv, priv->tx_chan); | |
1208 | bcm_enet_disable_dma(priv, priv->rx_chan); | |
1209 | bcm_enet_disable_mac(priv); | |
1210 | ||
1211 | /* force reclaim of all tx buffers */ | |
1212 | bcm_enet_tx_reclaim(dev, 1); | |
1213 | ||
1214 | /* free the rx skb ring */ | |
1215 | for (i = 0; i < priv->rx_ring_size; i++) { | |
1216 | struct bcm_enet_desc *desc; | |
1217 | ||
1218 | if (!priv->rx_skb[i]) | |
1219 | continue; | |
1220 | ||
1221 | desc = &priv->rx_desc_cpu[i]; | |
1222 | dma_unmap_single(kdev, desc->address, priv->rx_skb_size, | |
1223 | DMA_FROM_DEVICE); | |
1224 | kfree_skb(priv->rx_skb[i]); | |
1225 | } | |
1226 | ||
1227 | /* free remaining allocated memory */ | |
1228 | kfree(priv->rx_skb); | |
1229 | kfree(priv->tx_skb); | |
1230 | dma_free_coherent(kdev, priv->rx_desc_alloc_size, | |
1231 | priv->rx_desc_cpu, priv->rx_desc_dma); | |
1232 | dma_free_coherent(kdev, priv->tx_desc_alloc_size, | |
1233 | priv->tx_desc_cpu, priv->tx_desc_dma); | |
1234 | free_irq(priv->irq_tx, dev); | |
1235 | free_irq(priv->irq_rx, dev); | |
1236 | free_irq(dev->irq, dev); | |
1237 | ||
1238 | /* release phy */ | |
1239 | if (priv->has_phy) | |
1240 | phy_disconnect(dev->phydev); | |
1241 | ||
1242 | return 0; | |
1243 | } | |
1244 | ||
1245 | /* | |
1246 | * ethtool callbacks | |
1247 | */ | |
1248 | struct bcm_enet_stats { | |
1249 | char stat_string[ETH_GSTRING_LEN]; | |
1250 | int sizeof_stat; | |
1251 | int stat_offset; | |
1252 | int mib_reg; | |
1253 | }; | |
1254 | ||
1255 | #define GEN_STAT(m) sizeof(((struct bcm_enet_priv *)0)->m), \ | |
1256 | offsetof(struct bcm_enet_priv, m) | |
1257 | #define DEV_STAT(m) sizeof(((struct net_device_stats *)0)->m), \ | |
1258 | offsetof(struct net_device_stats, m) | |
1259 | ||
1260 | static const struct bcm_enet_stats bcm_enet_gstrings_stats[] = { | |
1261 | { "rx_packets", DEV_STAT(rx_packets), -1 }, | |
1262 | { "tx_packets", DEV_STAT(tx_packets), -1 }, | |
1263 | { "rx_bytes", DEV_STAT(rx_bytes), -1 }, | |
1264 | { "tx_bytes", DEV_STAT(tx_bytes), -1 }, | |
1265 | { "rx_errors", DEV_STAT(rx_errors), -1 }, | |
1266 | { "tx_errors", DEV_STAT(tx_errors), -1 }, | |
1267 | { "rx_dropped", DEV_STAT(rx_dropped), -1 }, | |
1268 | { "tx_dropped", DEV_STAT(tx_dropped), -1 }, | |
1269 | ||
1270 | { "rx_good_octets", GEN_STAT(mib.rx_gd_octets), ETH_MIB_RX_GD_OCTETS}, | |
1271 | { "rx_good_pkts", GEN_STAT(mib.rx_gd_pkts), ETH_MIB_RX_GD_PKTS }, | |
1272 | { "rx_broadcast", GEN_STAT(mib.rx_brdcast), ETH_MIB_RX_BRDCAST }, | |
1273 | { "rx_multicast", GEN_STAT(mib.rx_mult), ETH_MIB_RX_MULT }, | |
1274 | { "rx_64_octets", GEN_STAT(mib.rx_64), ETH_MIB_RX_64 }, | |
1275 | { "rx_65_127_oct", GEN_STAT(mib.rx_65_127), ETH_MIB_RX_65_127 }, | |
1276 | { "rx_128_255_oct", GEN_STAT(mib.rx_128_255), ETH_MIB_RX_128_255 }, | |
1277 | { "rx_256_511_oct", GEN_STAT(mib.rx_256_511), ETH_MIB_RX_256_511 }, | |
1278 | { "rx_512_1023_oct", GEN_STAT(mib.rx_512_1023), ETH_MIB_RX_512_1023 }, | |
1279 | { "rx_1024_max_oct", GEN_STAT(mib.rx_1024_max), ETH_MIB_RX_1024_MAX }, | |
1280 | { "rx_jabber", GEN_STAT(mib.rx_jab), ETH_MIB_RX_JAB }, | |
1281 | { "rx_oversize", GEN_STAT(mib.rx_ovr), ETH_MIB_RX_OVR }, | |
1282 | { "rx_fragment", GEN_STAT(mib.rx_frag), ETH_MIB_RX_FRAG }, | |
1283 | { "rx_dropped", GEN_STAT(mib.rx_drop), ETH_MIB_RX_DROP }, | |
1284 | { "rx_crc_align", GEN_STAT(mib.rx_crc_align), ETH_MIB_RX_CRC_ALIGN }, | |
1285 | { "rx_undersize", GEN_STAT(mib.rx_und), ETH_MIB_RX_UND }, | |
1286 | { "rx_crc", GEN_STAT(mib.rx_crc), ETH_MIB_RX_CRC }, | |
1287 | { "rx_align", GEN_STAT(mib.rx_align), ETH_MIB_RX_ALIGN }, | |
1288 | { "rx_symbol_error", GEN_STAT(mib.rx_sym), ETH_MIB_RX_SYM }, | |
1289 | { "rx_pause", GEN_STAT(mib.rx_pause), ETH_MIB_RX_PAUSE }, | |
1290 | { "rx_control", GEN_STAT(mib.rx_cntrl), ETH_MIB_RX_CNTRL }, | |
1291 | ||
1292 | { "tx_good_octets", GEN_STAT(mib.tx_gd_octets), ETH_MIB_TX_GD_OCTETS }, | |
1293 | { "tx_good_pkts", GEN_STAT(mib.tx_gd_pkts), ETH_MIB_TX_GD_PKTS }, | |
1294 | { "tx_broadcast", GEN_STAT(mib.tx_brdcast), ETH_MIB_TX_BRDCAST }, | |
1295 | { "tx_multicast", GEN_STAT(mib.tx_mult), ETH_MIB_TX_MULT }, | |
1296 | { "tx_64_oct", GEN_STAT(mib.tx_64), ETH_MIB_TX_64 }, | |
1297 | { "tx_65_127_oct", GEN_STAT(mib.tx_65_127), ETH_MIB_TX_65_127 }, | |
1298 | { "tx_128_255_oct", GEN_STAT(mib.tx_128_255), ETH_MIB_TX_128_255 }, | |
1299 | { "tx_256_511_oct", GEN_STAT(mib.tx_256_511), ETH_MIB_TX_256_511 }, | |
1300 | { "tx_512_1023_oct", GEN_STAT(mib.tx_512_1023), ETH_MIB_TX_512_1023}, | |
1301 | { "tx_1024_max_oct", GEN_STAT(mib.tx_1024_max), ETH_MIB_TX_1024_MAX }, | |
1302 | { "tx_jabber", GEN_STAT(mib.tx_jab), ETH_MIB_TX_JAB }, | |
1303 | { "tx_oversize", GEN_STAT(mib.tx_ovr), ETH_MIB_TX_OVR }, | |
1304 | { "tx_fragment", GEN_STAT(mib.tx_frag), ETH_MIB_TX_FRAG }, | |
1305 | { "tx_underrun", GEN_STAT(mib.tx_underrun), ETH_MIB_TX_UNDERRUN }, | |
1306 | { "tx_collisions", GEN_STAT(mib.tx_col), ETH_MIB_TX_COL }, | |
1307 | { "tx_single_collision", GEN_STAT(mib.tx_1_col), ETH_MIB_TX_1_COL }, | |
1308 | { "tx_multiple_collision", GEN_STAT(mib.tx_m_col), ETH_MIB_TX_M_COL }, | |
1309 | { "tx_excess_collision", GEN_STAT(mib.tx_ex_col), ETH_MIB_TX_EX_COL }, | |
1310 | { "tx_late_collision", GEN_STAT(mib.tx_late), ETH_MIB_TX_LATE }, | |
1311 | { "tx_deferred", GEN_STAT(mib.tx_def), ETH_MIB_TX_DEF }, | |
1312 | { "tx_carrier_sense", GEN_STAT(mib.tx_crs), ETH_MIB_TX_CRS }, | |
1313 | { "tx_pause", GEN_STAT(mib.tx_pause), ETH_MIB_TX_PAUSE }, | |
1314 | ||
1315 | }; | |
1316 | ||
1317 | #define BCM_ENET_STATS_LEN ARRAY_SIZE(bcm_enet_gstrings_stats) | |
1318 | ||
1319 | static const u32 unused_mib_regs[] = { | |
1320 | ETH_MIB_TX_ALL_OCTETS, | |
1321 | ETH_MIB_TX_ALL_PKTS, | |
1322 | ETH_MIB_RX_ALL_OCTETS, | |
1323 | ETH_MIB_RX_ALL_PKTS, | |
1324 | }; | |
1325 | ||
1326 | ||
1327 | static void bcm_enet_get_drvinfo(struct net_device *netdev, | |
1328 | struct ethtool_drvinfo *drvinfo) | |
1329 | { | |
1330 | strlcpy(drvinfo->driver, bcm_enet_driver_name, sizeof(drvinfo->driver)); | |
1331 | strlcpy(drvinfo->version, bcm_enet_driver_version, | |
1332 | sizeof(drvinfo->version)); | |
1333 | strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version)); | |
1334 | strlcpy(drvinfo->bus_info, "bcm63xx", sizeof(drvinfo->bus_info)); | |
1335 | } | |
1336 | ||
1337 | static int bcm_enet_get_sset_count(struct net_device *netdev, | |
1338 | int string_set) | |
1339 | { | |
1340 | switch (string_set) { | |
1341 | case ETH_SS_STATS: | |
1342 | return BCM_ENET_STATS_LEN; | |
1343 | default: | |
1344 | return -EINVAL; | |
1345 | } | |
1346 | } | |
1347 | ||
1348 | static void bcm_enet_get_strings(struct net_device *netdev, | |
1349 | u32 stringset, u8 *data) | |
1350 | { | |
1351 | int i; | |
1352 | ||
1353 | switch (stringset) { | |
1354 | case ETH_SS_STATS: | |
1355 | for (i = 0; i < BCM_ENET_STATS_LEN; i++) { | |
1356 | memcpy(data + i * ETH_GSTRING_LEN, | |
1357 | bcm_enet_gstrings_stats[i].stat_string, | |
1358 | ETH_GSTRING_LEN); | |
1359 | } | |
1360 | break; | |
1361 | } | |
1362 | } | |
1363 | ||
1364 | static void update_mib_counters(struct bcm_enet_priv *priv) | |
1365 | { | |
1366 | int i; | |
1367 | ||
1368 | for (i = 0; i < BCM_ENET_STATS_LEN; i++) { | |
1369 | const struct bcm_enet_stats *s; | |
1370 | u32 val; | |
1371 | char *p; | |
1372 | ||
1373 | s = &bcm_enet_gstrings_stats[i]; | |
1374 | if (s->mib_reg == -1) | |
1375 | continue; | |
1376 | ||
1377 | val = enet_readl(priv, ENET_MIB_REG(s->mib_reg)); | |
1378 | p = (char *)priv + s->stat_offset; | |
1379 | ||
1380 | if (s->sizeof_stat == sizeof(u64)) | |
1381 | *(u64 *)p += val; | |
1382 | else | |
1383 | *(u32 *)p += val; | |
1384 | } | |
1385 | ||
1386 | /* also empty unused mib counters to make sure mib counter | |
1387 | * overflow interrupt is cleared */ | |
1388 | for (i = 0; i < ARRAY_SIZE(unused_mib_regs); i++) | |
1389 | (void)enet_readl(priv, ENET_MIB_REG(unused_mib_regs[i])); | |
1390 | } | |
1391 | ||
1392 | static void bcm_enet_update_mib_counters_defer(struct work_struct *t) | |
1393 | { | |
1394 | struct bcm_enet_priv *priv; | |
1395 | ||
1396 | priv = container_of(t, struct bcm_enet_priv, mib_update_task); | |
1397 | mutex_lock(&priv->mib_update_lock); | |
1398 | update_mib_counters(priv); | |
1399 | mutex_unlock(&priv->mib_update_lock); | |
1400 | ||
1401 | /* reenable mib interrupt */ | |
1402 | if (netif_running(priv->net_dev)) | |
1403 | enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG); | |
1404 | } | |
1405 | ||
1406 | static void bcm_enet_get_ethtool_stats(struct net_device *netdev, | |
1407 | struct ethtool_stats *stats, | |
1408 | u64 *data) | |
1409 | { | |
1410 | struct bcm_enet_priv *priv; | |
1411 | int i; | |
1412 | ||
1413 | priv = netdev_priv(netdev); | |
1414 | ||
1415 | mutex_lock(&priv->mib_update_lock); | |
1416 | update_mib_counters(priv); | |
1417 | ||
1418 | for (i = 0; i < BCM_ENET_STATS_LEN; i++) { | |
1419 | const struct bcm_enet_stats *s; | |
1420 | char *p; | |
1421 | ||
1422 | s = &bcm_enet_gstrings_stats[i]; | |
1423 | if (s->mib_reg == -1) | |
1424 | p = (char *)&netdev->stats; | |
1425 | else | |
1426 | p = (char *)priv; | |
1427 | p += s->stat_offset; | |
1428 | data[i] = (s->sizeof_stat == sizeof(u64)) ? | |
1429 | *(u64 *)p : *(u32 *)p; | |
1430 | } | |
1431 | mutex_unlock(&priv->mib_update_lock); | |
1432 | } | |
1433 | ||
1434 | static int bcm_enet_nway_reset(struct net_device *dev) | |
1435 | { | |
1436 | struct bcm_enet_priv *priv; | |
1437 | ||
1438 | priv = netdev_priv(dev); | |
1439 | if (priv->has_phy) | |
1440 | return phy_ethtool_nway_reset(dev); | |
1441 | ||
1442 | return -EOPNOTSUPP; | |
1443 | } | |
1444 | ||
1445 | static int bcm_enet_get_link_ksettings(struct net_device *dev, | |
1446 | struct ethtool_link_ksettings *cmd) | |
1447 | { | |
1448 | struct bcm_enet_priv *priv; | |
1449 | u32 supported, advertising; | |
1450 | ||
1451 | priv = netdev_priv(dev); | |
1452 | ||
1453 | if (priv->has_phy) { | |
1454 | if (!dev->phydev) | |
1455 | return -ENODEV; | |
1456 | return phy_ethtool_ksettings_get(dev->phydev, cmd); | |
1457 | } else { | |
1458 | cmd->base.autoneg = 0; | |
1459 | cmd->base.speed = (priv->force_speed_100) ? | |
1460 | SPEED_100 : SPEED_10; | |
1461 | cmd->base.duplex = (priv->force_duplex_full) ? | |
1462 | DUPLEX_FULL : DUPLEX_HALF; | |
1463 | supported = ADVERTISED_10baseT_Half | | |
1464 | ADVERTISED_10baseT_Full | | |
1465 | ADVERTISED_100baseT_Half | | |
1466 | ADVERTISED_100baseT_Full; | |
1467 | advertising = 0; | |
1468 | ethtool_convert_legacy_u32_to_link_mode( | |
1469 | cmd->link_modes.supported, supported); | |
1470 | ethtool_convert_legacy_u32_to_link_mode( | |
1471 | cmd->link_modes.advertising, advertising); | |
1472 | cmd->base.port = PORT_MII; | |
1473 | } | |
1474 | return 0; | |
1475 | } | |
1476 | ||
1477 | static int bcm_enet_set_link_ksettings(struct net_device *dev, | |
1478 | const struct ethtool_link_ksettings *cmd) | |
1479 | { | |
1480 | struct bcm_enet_priv *priv; | |
1481 | ||
1482 | priv = netdev_priv(dev); | |
1483 | if (priv->has_phy) { | |
1484 | if (!dev->phydev) | |
1485 | return -ENODEV; | |
1486 | return phy_ethtool_ksettings_set(dev->phydev, cmd); | |
1487 | } else { | |
1488 | ||
1489 | if (cmd->base.autoneg || | |
1490 | (cmd->base.speed != SPEED_100 && | |
1491 | cmd->base.speed != SPEED_10) || | |
1492 | cmd->base.port != PORT_MII) | |
1493 | return -EINVAL; | |
1494 | ||
1495 | priv->force_speed_100 = | |
1496 | (cmd->base.speed == SPEED_100) ? 1 : 0; | |
1497 | priv->force_duplex_full = | |
1498 | (cmd->base.duplex == DUPLEX_FULL) ? 1 : 0; | |
1499 | ||
1500 | if (netif_running(dev)) | |
1501 | bcm_enet_adjust_link(dev); | |
1502 | return 0; | |
1503 | } | |
1504 | } | |
1505 | ||
1506 | static void bcm_enet_get_ringparam(struct net_device *dev, | |
1507 | struct ethtool_ringparam *ering) | |
1508 | { | |
1509 | struct bcm_enet_priv *priv; | |
1510 | ||
1511 | priv = netdev_priv(dev); | |
1512 | ||
1513 | /* rx/tx ring is actually only limited by memory */ | |
1514 | ering->rx_max_pending = 8192; | |
1515 | ering->tx_max_pending = 8192; | |
1516 | ering->rx_pending = priv->rx_ring_size; | |
1517 | ering->tx_pending = priv->tx_ring_size; | |
1518 | } | |
1519 | ||
1520 | static int bcm_enet_set_ringparam(struct net_device *dev, | |
1521 | struct ethtool_ringparam *ering) | |
1522 | { | |
1523 | struct bcm_enet_priv *priv; | |
1524 | int was_running; | |
1525 | ||
1526 | priv = netdev_priv(dev); | |
1527 | ||
1528 | was_running = 0; | |
1529 | if (netif_running(dev)) { | |
1530 | bcm_enet_stop(dev); | |
1531 | was_running = 1; | |
1532 | } | |
1533 | ||
1534 | priv->rx_ring_size = ering->rx_pending; | |
1535 | priv->tx_ring_size = ering->tx_pending; | |
1536 | ||
1537 | if (was_running) { | |
1538 | int err; | |
1539 | ||
1540 | err = bcm_enet_open(dev); | |
1541 | if (err) | |
1542 | dev_close(dev); | |
1543 | else | |
1544 | bcm_enet_set_multicast_list(dev); | |
1545 | } | |
1546 | return 0; | |
1547 | } | |
1548 | ||
1549 | static void bcm_enet_get_pauseparam(struct net_device *dev, | |
1550 | struct ethtool_pauseparam *ecmd) | |
1551 | { | |
1552 | struct bcm_enet_priv *priv; | |
1553 | ||
1554 | priv = netdev_priv(dev); | |
1555 | ecmd->autoneg = priv->pause_auto; | |
1556 | ecmd->rx_pause = priv->pause_rx; | |
1557 | ecmd->tx_pause = priv->pause_tx; | |
1558 | } | |
1559 | ||
1560 | static int bcm_enet_set_pauseparam(struct net_device *dev, | |
1561 | struct ethtool_pauseparam *ecmd) | |
1562 | { | |
1563 | struct bcm_enet_priv *priv; | |
1564 | ||
1565 | priv = netdev_priv(dev); | |
1566 | ||
1567 | if (priv->has_phy) { | |
1568 | if (ecmd->autoneg && (ecmd->rx_pause != ecmd->tx_pause)) { | |
1569 | /* asymetric pause mode not supported, | |
1570 | * actually possible but integrated PHY has RO | |
1571 | * asym_pause bit */ | |
1572 | return -EINVAL; | |
1573 | } | |
1574 | } else { | |
1575 | /* no pause autoneg on direct mii connection */ | |
1576 | if (ecmd->autoneg) | |
1577 | return -EINVAL; | |
1578 | } | |
1579 | ||
1580 | priv->pause_auto = ecmd->autoneg; | |
1581 | priv->pause_rx = ecmd->rx_pause; | |
1582 | priv->pause_tx = ecmd->tx_pause; | |
1583 | ||
1584 | return 0; | |
1585 | } | |
1586 | ||
1587 | static const struct ethtool_ops bcm_enet_ethtool_ops = { | |
1588 | .get_strings = bcm_enet_get_strings, | |
1589 | .get_sset_count = bcm_enet_get_sset_count, | |
1590 | .get_ethtool_stats = bcm_enet_get_ethtool_stats, | |
1591 | .nway_reset = bcm_enet_nway_reset, | |
1592 | .get_drvinfo = bcm_enet_get_drvinfo, | |
1593 | .get_link = ethtool_op_get_link, | |
1594 | .get_ringparam = bcm_enet_get_ringparam, | |
1595 | .set_ringparam = bcm_enet_set_ringparam, | |
1596 | .get_pauseparam = bcm_enet_get_pauseparam, | |
1597 | .set_pauseparam = bcm_enet_set_pauseparam, | |
1598 | .get_link_ksettings = bcm_enet_get_link_ksettings, | |
1599 | .set_link_ksettings = bcm_enet_set_link_ksettings, | |
1600 | }; | |
1601 | ||
1602 | static int bcm_enet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
1603 | { | |
1604 | struct bcm_enet_priv *priv; | |
1605 | ||
1606 | priv = netdev_priv(dev); | |
1607 | if (priv->has_phy) { | |
1608 | if (!dev->phydev) | |
1609 | return -ENODEV; | |
1610 | return phy_mii_ioctl(dev->phydev, rq, cmd); | |
1611 | } else { | |
1612 | struct mii_if_info mii; | |
1613 | ||
1614 | mii.dev = dev; | |
1615 | mii.mdio_read = bcm_enet_mdio_read_mii; | |
1616 | mii.mdio_write = bcm_enet_mdio_write_mii; | |
1617 | mii.phy_id = 0; | |
1618 | mii.phy_id_mask = 0x3f; | |
1619 | mii.reg_num_mask = 0x1f; | |
1620 | return generic_mii_ioctl(&mii, if_mii(rq), cmd, NULL); | |
1621 | } | |
1622 | } | |
1623 | ||
1624 | /* | |
1625 | * adjust mtu, can't be called while device is running | |
1626 | */ | |
1627 | static int bcm_enet_change_mtu(struct net_device *dev, int new_mtu) | |
1628 | { | |
1629 | struct bcm_enet_priv *priv = netdev_priv(dev); | |
1630 | int actual_mtu = new_mtu; | |
1631 | ||
1632 | if (netif_running(dev)) | |
1633 | return -EBUSY; | |
1634 | ||
1635 | /* add ethernet header + vlan tag size */ | |
1636 | actual_mtu += VLAN_ETH_HLEN; | |
1637 | ||
1638 | /* | |
1639 | * setup maximum size before we get overflow mark in | |
1640 | * descriptor, note that this will not prevent reception of | |
1641 | * big frames, they will be split into multiple buffers | |
1642 | * anyway | |
1643 | */ | |
1644 | priv->hw_mtu = actual_mtu; | |
1645 | ||
1646 | /* | |
1647 | * align rx buffer size to dma burst len, account FCS since | |
1648 | * it's appended | |
1649 | */ | |
1650 | priv->rx_skb_size = ALIGN(actual_mtu + ETH_FCS_LEN, | |
1651 | priv->dma_maxburst * 4); | |
1652 | ||
1653 | dev->mtu = new_mtu; | |
1654 | return 0; | |
1655 | } | |
1656 | ||
1657 | /* | |
1658 | * preinit hardware to allow mii operation while device is down | |
1659 | */ | |
1660 | static void bcm_enet_hw_preinit(struct bcm_enet_priv *priv) | |
1661 | { | |
1662 | u32 val; | |
1663 | int limit; | |
1664 | ||
1665 | /* make sure mac is disabled */ | |
1666 | bcm_enet_disable_mac(priv); | |
1667 | ||
1668 | /* soft reset mac */ | |
1669 | val = ENET_CTL_SRESET_MASK; | |
1670 | enet_writel(priv, val, ENET_CTL_REG); | |
1671 | wmb(); | |
1672 | ||
1673 | limit = 1000; | |
1674 | do { | |
1675 | val = enet_readl(priv, ENET_CTL_REG); | |
1676 | if (!(val & ENET_CTL_SRESET_MASK)) | |
1677 | break; | |
1678 | udelay(1); | |
1679 | } while (limit--); | |
1680 | ||
1681 | /* select correct mii interface */ | |
1682 | val = enet_readl(priv, ENET_CTL_REG); | |
1683 | if (priv->use_external_mii) | |
1684 | val |= ENET_CTL_EPHYSEL_MASK; | |
1685 | else | |
1686 | val &= ~ENET_CTL_EPHYSEL_MASK; | |
1687 | enet_writel(priv, val, ENET_CTL_REG); | |
1688 | ||
1689 | /* turn on mdc clock */ | |
1690 | enet_writel(priv, (0x1f << ENET_MIISC_MDCFREQDIV_SHIFT) | | |
1691 | ENET_MIISC_PREAMBLEEN_MASK, ENET_MIISC_REG); | |
1692 | ||
1693 | /* set mib counters to self-clear when read */ | |
1694 | val = enet_readl(priv, ENET_MIBCTL_REG); | |
1695 | val |= ENET_MIBCTL_RDCLEAR_MASK; | |
1696 | enet_writel(priv, val, ENET_MIBCTL_REG); | |
1697 | } | |
1698 | ||
1699 | static const struct net_device_ops bcm_enet_ops = { | |
1700 | .ndo_open = bcm_enet_open, | |
1701 | .ndo_stop = bcm_enet_stop, | |
1702 | .ndo_start_xmit = bcm_enet_start_xmit, | |
1703 | .ndo_set_mac_address = bcm_enet_set_mac_address, | |
1704 | .ndo_set_rx_mode = bcm_enet_set_multicast_list, | |
1705 | .ndo_do_ioctl = bcm_enet_ioctl, | |
1706 | .ndo_change_mtu = bcm_enet_change_mtu, | |
1707 | }; | |
1708 | ||
1709 | /* | |
1710 | * allocate netdevice, request register memory and register device. | |
1711 | */ | |
1712 | static int bcm_enet_probe(struct platform_device *pdev) | |
1713 | { | |
1714 | struct bcm_enet_priv *priv; | |
1715 | struct net_device *dev; | |
1716 | struct bcm63xx_enet_platform_data *pd; | |
1717 | struct resource *res_mem, *res_irq, *res_irq_rx, *res_irq_tx; | |
1718 | struct mii_bus *bus; | |
1719 | const char *clk_name; | |
1720 | int i, ret; | |
1721 | ||
1722 | /* stop if shared driver failed, assume driver->probe will be | |
1723 | * called in the same order we register devices (correct ?) */ | |
1724 | if (!bcm_enet_shared_base[0]) | |
1725 | return -ENODEV; | |
1726 | ||
1727 | res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
1728 | res_irq_rx = platform_get_resource(pdev, IORESOURCE_IRQ, 1); | |
1729 | res_irq_tx = platform_get_resource(pdev, IORESOURCE_IRQ, 2); | |
1730 | if (!res_irq || !res_irq_rx || !res_irq_tx) | |
1731 | return -ENODEV; | |
1732 | ||
1733 | ret = 0; | |
1734 | dev = alloc_etherdev(sizeof(*priv)); | |
1735 | if (!dev) | |
1736 | return -ENOMEM; | |
1737 | priv = netdev_priv(dev); | |
1738 | ||
1739 | priv->enet_is_sw = false; | |
1740 | priv->dma_maxburst = BCMENET_DMA_MAXBURST; | |
1741 | ||
1742 | ret = bcm_enet_change_mtu(dev, dev->mtu); | |
1743 | if (ret) | |
1744 | goto out; | |
1745 | ||
1746 | res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1747 | priv->base = devm_ioremap_resource(&pdev->dev, res_mem); | |
1748 | if (IS_ERR(priv->base)) { | |
1749 | ret = PTR_ERR(priv->base); | |
1750 | goto out; | |
1751 | } | |
1752 | ||
1753 | dev->irq = priv->irq = res_irq->start; | |
1754 | priv->irq_rx = res_irq_rx->start; | |
1755 | priv->irq_tx = res_irq_tx->start; | |
1756 | priv->mac_id = pdev->id; | |
1757 | ||
1758 | /* get rx & tx dma channel id for this mac */ | |
1759 | if (priv->mac_id == 0) { | |
1760 | priv->rx_chan = 0; | |
1761 | priv->tx_chan = 1; | |
1762 | clk_name = "enet0"; | |
1763 | } else { | |
1764 | priv->rx_chan = 2; | |
1765 | priv->tx_chan = 3; | |
1766 | clk_name = "enet1"; | |
1767 | } | |
1768 | ||
1769 | priv->mac_clk = clk_get(&pdev->dev, clk_name); | |
1770 | if (IS_ERR(priv->mac_clk)) { | |
1771 | ret = PTR_ERR(priv->mac_clk); | |
1772 | goto out; | |
1773 | } | |
1774 | clk_prepare_enable(priv->mac_clk); | |
1775 | ||
1776 | /* initialize default and fetch platform data */ | |
1777 | priv->rx_ring_size = BCMENET_DEF_RX_DESC; | |
1778 | priv->tx_ring_size = BCMENET_DEF_TX_DESC; | |
1779 | ||
1780 | pd = dev_get_platdata(&pdev->dev); | |
1781 | if (pd) { | |
1782 | memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN); | |
1783 | priv->has_phy = pd->has_phy; | |
1784 | priv->phy_id = pd->phy_id; | |
1785 | priv->has_phy_interrupt = pd->has_phy_interrupt; | |
1786 | priv->phy_interrupt = pd->phy_interrupt; | |
1787 | priv->use_external_mii = !pd->use_internal_phy; | |
1788 | priv->pause_auto = pd->pause_auto; | |
1789 | priv->pause_rx = pd->pause_rx; | |
1790 | priv->pause_tx = pd->pause_tx; | |
1791 | priv->force_duplex_full = pd->force_duplex_full; | |
1792 | priv->force_speed_100 = pd->force_speed_100; | |
1793 | priv->dma_chan_en_mask = pd->dma_chan_en_mask; | |
1794 | priv->dma_chan_int_mask = pd->dma_chan_int_mask; | |
1795 | priv->dma_chan_width = pd->dma_chan_width; | |
1796 | priv->dma_has_sram = pd->dma_has_sram; | |
1797 | priv->dma_desc_shift = pd->dma_desc_shift; | |
1798 | } | |
1799 | ||
1800 | if (priv->mac_id == 0 && priv->has_phy && !priv->use_external_mii) { | |
1801 | /* using internal PHY, enable clock */ | |
1802 | priv->phy_clk = clk_get(&pdev->dev, "ephy"); | |
1803 | if (IS_ERR(priv->phy_clk)) { | |
1804 | ret = PTR_ERR(priv->phy_clk); | |
1805 | priv->phy_clk = NULL; | |
1806 | goto out_put_clk_mac; | |
1807 | } | |
1808 | clk_prepare_enable(priv->phy_clk); | |
1809 | } | |
1810 | ||
1811 | /* do minimal hardware init to be able to probe mii bus */ | |
1812 | bcm_enet_hw_preinit(priv); | |
1813 | ||
1814 | /* MII bus registration */ | |
1815 | if (priv->has_phy) { | |
1816 | ||
1817 | priv->mii_bus = mdiobus_alloc(); | |
1818 | if (!priv->mii_bus) { | |
1819 | ret = -ENOMEM; | |
1820 | goto out_uninit_hw; | |
1821 | } | |
1822 | ||
1823 | bus = priv->mii_bus; | |
1824 | bus->name = "bcm63xx_enet MII bus"; | |
1825 | bus->parent = &pdev->dev; | |
1826 | bus->priv = priv; | |
1827 | bus->read = bcm_enet_mdio_read_phylib; | |
1828 | bus->write = bcm_enet_mdio_write_phylib; | |
1829 | sprintf(bus->id, "%s-%d", pdev->name, priv->mac_id); | |
1830 | ||
1831 | /* only probe bus where we think the PHY is, because | |
1832 | * the mdio read operation return 0 instead of 0xffff | |
1833 | * if a slave is not present on hw */ | |
1834 | bus->phy_mask = ~(1 << priv->phy_id); | |
1835 | ||
1836 | if (priv->has_phy_interrupt) | |
1837 | bus->irq[priv->phy_id] = priv->phy_interrupt; | |
1838 | ||
1839 | ret = mdiobus_register(bus); | |
1840 | if (ret) { | |
1841 | dev_err(&pdev->dev, "unable to register mdio bus\n"); | |
1842 | goto out_free_mdio; | |
1843 | } | |
1844 | } else { | |
1845 | ||
1846 | /* run platform code to initialize PHY device */ | |
1847 | if (pd && pd->mii_config && | |
1848 | pd->mii_config(dev, 1, bcm_enet_mdio_read_mii, | |
1849 | bcm_enet_mdio_write_mii)) { | |
1850 | dev_err(&pdev->dev, "unable to configure mdio bus\n"); | |
1851 | goto out_uninit_hw; | |
1852 | } | |
1853 | } | |
1854 | ||
1855 | spin_lock_init(&priv->rx_lock); | |
1856 | ||
1857 | /* init rx timeout (used for oom) */ | |
1858 | init_timer(&priv->rx_timeout); | |
1859 | priv->rx_timeout.function = bcm_enet_refill_rx_timer; | |
1860 | priv->rx_timeout.data = (unsigned long)dev; | |
1861 | ||
1862 | /* init the mib update lock&work */ | |
1863 | mutex_init(&priv->mib_update_lock); | |
1864 | INIT_WORK(&priv->mib_update_task, bcm_enet_update_mib_counters_defer); | |
1865 | ||
1866 | /* zero mib counters */ | |
1867 | for (i = 0; i < ENET_MIB_REG_COUNT; i++) | |
1868 | enet_writel(priv, 0, ENET_MIB_REG(i)); | |
1869 | ||
1870 | /* register netdevice */ | |
1871 | dev->netdev_ops = &bcm_enet_ops; | |
1872 | netif_napi_add(dev, &priv->napi, bcm_enet_poll, 16); | |
1873 | ||
1874 | dev->ethtool_ops = &bcm_enet_ethtool_ops; | |
1875 | /* MTU range: 46 - 2028 */ | |
1876 | dev->min_mtu = ETH_ZLEN - ETH_HLEN; | |
1877 | dev->max_mtu = BCMENET_MAX_MTU - VLAN_ETH_HLEN; | |
1878 | SET_NETDEV_DEV(dev, &pdev->dev); | |
1879 | ||
1880 | ret = register_netdev(dev); | |
1881 | if (ret) | |
1882 | goto out_unregister_mdio; | |
1883 | ||
1884 | netif_carrier_off(dev); | |
1885 | platform_set_drvdata(pdev, dev); | |
1886 | priv->pdev = pdev; | |
1887 | priv->net_dev = dev; | |
1888 | ||
1889 | return 0; | |
1890 | ||
1891 | out_unregister_mdio: | |
1892 | if (priv->mii_bus) | |
1893 | mdiobus_unregister(priv->mii_bus); | |
1894 | ||
1895 | out_free_mdio: | |
1896 | if (priv->mii_bus) | |
1897 | mdiobus_free(priv->mii_bus); | |
1898 | ||
1899 | out_uninit_hw: | |
1900 | /* turn off mdc clock */ | |
1901 | enet_writel(priv, 0, ENET_MIISC_REG); | |
1902 | if (priv->phy_clk) { | |
1903 | clk_disable_unprepare(priv->phy_clk); | |
1904 | clk_put(priv->phy_clk); | |
1905 | } | |
1906 | ||
1907 | out_put_clk_mac: | |
1908 | clk_disable_unprepare(priv->mac_clk); | |
1909 | clk_put(priv->mac_clk); | |
1910 | out: | |
1911 | free_netdev(dev); | |
1912 | return ret; | |
1913 | } | |
1914 | ||
1915 | ||
1916 | /* | |
1917 | * exit func, stops hardware and unregisters netdevice | |
1918 | */ | |
1919 | static int bcm_enet_remove(struct platform_device *pdev) | |
1920 | { | |
1921 | struct bcm_enet_priv *priv; | |
1922 | struct net_device *dev; | |
1923 | ||
1924 | /* stop netdevice */ | |
1925 | dev = platform_get_drvdata(pdev); | |
1926 | priv = netdev_priv(dev); | |
1927 | unregister_netdev(dev); | |
1928 | ||
1929 | /* turn off mdc clock */ | |
1930 | enet_writel(priv, 0, ENET_MIISC_REG); | |
1931 | ||
1932 | if (priv->has_phy) { | |
1933 | mdiobus_unregister(priv->mii_bus); | |
1934 | mdiobus_free(priv->mii_bus); | |
1935 | } else { | |
1936 | struct bcm63xx_enet_platform_data *pd; | |
1937 | ||
1938 | pd = dev_get_platdata(&pdev->dev); | |
1939 | if (pd && pd->mii_config) | |
1940 | pd->mii_config(dev, 0, bcm_enet_mdio_read_mii, | |
1941 | bcm_enet_mdio_write_mii); | |
1942 | } | |
1943 | ||
1944 | /* disable hw block clocks */ | |
1945 | if (priv->phy_clk) { | |
1946 | clk_disable_unprepare(priv->phy_clk); | |
1947 | clk_put(priv->phy_clk); | |
1948 | } | |
1949 | clk_disable_unprepare(priv->mac_clk); | |
1950 | clk_put(priv->mac_clk); | |
1951 | ||
1952 | free_netdev(dev); | |
1953 | return 0; | |
1954 | } | |
1955 | ||
1956 | struct platform_driver bcm63xx_enet_driver = { | |
1957 | .probe = bcm_enet_probe, | |
1958 | .remove = bcm_enet_remove, | |
1959 | .driver = { | |
1960 | .name = "bcm63xx_enet", | |
1961 | .owner = THIS_MODULE, | |
1962 | }, | |
1963 | }; | |
1964 | ||
1965 | /* | |
1966 | * switch mii access callbacks | |
1967 | */ | |
1968 | static int bcmenet_sw_mdio_read(struct bcm_enet_priv *priv, | |
1969 | int ext, int phy_id, int location) | |
1970 | { | |
1971 | u32 reg; | |
1972 | int ret; | |
1973 | ||
1974 | spin_lock_bh(&priv->enetsw_mdio_lock); | |
1975 | enetsw_writel(priv, 0, ENETSW_MDIOC_REG); | |
1976 | ||
1977 | reg = ENETSW_MDIOC_RD_MASK | | |
1978 | (phy_id << ENETSW_MDIOC_PHYID_SHIFT) | | |
1979 | (location << ENETSW_MDIOC_REG_SHIFT); | |
1980 | ||
1981 | if (ext) | |
1982 | reg |= ENETSW_MDIOC_EXT_MASK; | |
1983 | ||
1984 | enetsw_writel(priv, reg, ENETSW_MDIOC_REG); | |
1985 | udelay(50); | |
1986 | ret = enetsw_readw(priv, ENETSW_MDIOD_REG); | |
1987 | spin_unlock_bh(&priv->enetsw_mdio_lock); | |
1988 | return ret; | |
1989 | } | |
1990 | ||
1991 | static void bcmenet_sw_mdio_write(struct bcm_enet_priv *priv, | |
1992 | int ext, int phy_id, int location, | |
1993 | uint16_t data) | |
1994 | { | |
1995 | u32 reg; | |
1996 | ||
1997 | spin_lock_bh(&priv->enetsw_mdio_lock); | |
1998 | enetsw_writel(priv, 0, ENETSW_MDIOC_REG); | |
1999 | ||
2000 | reg = ENETSW_MDIOC_WR_MASK | | |
2001 | (phy_id << ENETSW_MDIOC_PHYID_SHIFT) | | |
2002 | (location << ENETSW_MDIOC_REG_SHIFT); | |
2003 | ||
2004 | if (ext) | |
2005 | reg |= ENETSW_MDIOC_EXT_MASK; | |
2006 | ||
2007 | reg |= data; | |
2008 | ||
2009 | enetsw_writel(priv, reg, ENETSW_MDIOC_REG); | |
2010 | udelay(50); | |
2011 | spin_unlock_bh(&priv->enetsw_mdio_lock); | |
2012 | } | |
2013 | ||
2014 | static inline int bcm_enet_port_is_rgmii(int portid) | |
2015 | { | |
2016 | return portid >= ENETSW_RGMII_PORT0; | |
2017 | } | |
2018 | ||
2019 | /* | |
2020 | * enet sw PHY polling | |
2021 | */ | |
2022 | static void swphy_poll_timer(unsigned long data) | |
2023 | { | |
2024 | struct bcm_enet_priv *priv = (struct bcm_enet_priv *)data; | |
2025 | unsigned int i; | |
2026 | ||
2027 | for (i = 0; i < priv->num_ports; i++) { | |
2028 | struct bcm63xx_enetsw_port *port; | |
2029 | int val, j, up, advertise, lpa, speed, duplex, media; | |
2030 | int external_phy = bcm_enet_port_is_rgmii(i); | |
2031 | u8 override; | |
2032 | ||
2033 | port = &priv->used_ports[i]; | |
2034 | if (!port->used) | |
2035 | continue; | |
2036 | ||
2037 | if (port->bypass_link) | |
2038 | continue; | |
2039 | ||
2040 | /* dummy read to clear */ | |
2041 | for (j = 0; j < 2; j++) | |
2042 | val = bcmenet_sw_mdio_read(priv, external_phy, | |
2043 | port->phy_id, MII_BMSR); | |
2044 | ||
2045 | if (val == 0xffff) | |
2046 | continue; | |
2047 | ||
2048 | up = (val & BMSR_LSTATUS) ? 1 : 0; | |
2049 | if (!(up ^ priv->sw_port_link[i])) | |
2050 | continue; | |
2051 | ||
2052 | priv->sw_port_link[i] = up; | |
2053 | ||
2054 | /* link changed */ | |
2055 | if (!up) { | |
2056 | dev_info(&priv->pdev->dev, "link DOWN on %s\n", | |
2057 | port->name); | |
2058 | enetsw_writeb(priv, ENETSW_PORTOV_ENABLE_MASK, | |
2059 | ENETSW_PORTOV_REG(i)); | |
2060 | enetsw_writeb(priv, ENETSW_PTCTRL_RXDIS_MASK | | |
2061 | ENETSW_PTCTRL_TXDIS_MASK, | |
2062 | ENETSW_PTCTRL_REG(i)); | |
2063 | continue; | |
2064 | } | |
2065 | ||
2066 | advertise = bcmenet_sw_mdio_read(priv, external_phy, | |
2067 | port->phy_id, MII_ADVERTISE); | |
2068 | ||
2069 | lpa = bcmenet_sw_mdio_read(priv, external_phy, port->phy_id, | |
2070 | MII_LPA); | |
2071 | ||
2072 | /* figure out media and duplex from advertise and LPA values */ | |
2073 | media = mii_nway_result(lpa & advertise); | |
2074 | duplex = (media & ADVERTISE_FULL) ? 1 : 0; | |
2075 | ||
2076 | if (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)) | |
2077 | speed = 100; | |
2078 | else | |
2079 | speed = 10; | |
2080 | ||
2081 | if (val & BMSR_ESTATEN) { | |
2082 | advertise = bcmenet_sw_mdio_read(priv, external_phy, | |
2083 | port->phy_id, MII_CTRL1000); | |
2084 | ||
2085 | lpa = bcmenet_sw_mdio_read(priv, external_phy, | |
2086 | port->phy_id, MII_STAT1000); | |
2087 | ||
2088 | if (advertise & (ADVERTISE_1000FULL | ADVERTISE_1000HALF) | |
2089 | && lpa & (LPA_1000FULL | LPA_1000HALF)) { | |
2090 | speed = 1000; | |
2091 | duplex = (lpa & LPA_1000FULL); | |
2092 | } | |
2093 | } | |
2094 | ||
2095 | dev_info(&priv->pdev->dev, | |
2096 | "link UP on %s, %dMbps, %s-duplex\n", | |
2097 | port->name, speed, duplex ? "full" : "half"); | |
2098 | ||
2099 | override = ENETSW_PORTOV_ENABLE_MASK | | |
2100 | ENETSW_PORTOV_LINKUP_MASK; | |
2101 | ||
2102 | if (speed == 1000) | |
2103 | override |= ENETSW_IMPOV_1000_MASK; | |
2104 | else if (speed == 100) | |
2105 | override |= ENETSW_IMPOV_100_MASK; | |
2106 | if (duplex) | |
2107 | override |= ENETSW_IMPOV_FDX_MASK; | |
2108 | ||
2109 | enetsw_writeb(priv, override, ENETSW_PORTOV_REG(i)); | |
2110 | enetsw_writeb(priv, 0, ENETSW_PTCTRL_REG(i)); | |
2111 | } | |
2112 | ||
2113 | priv->swphy_poll.expires = jiffies + HZ; | |
2114 | add_timer(&priv->swphy_poll); | |
2115 | } | |
2116 | ||
2117 | /* | |
2118 | * open callback, allocate dma rings & buffers and start rx operation | |
2119 | */ | |
2120 | static int bcm_enetsw_open(struct net_device *dev) | |
2121 | { | |
2122 | struct bcm_enet_priv *priv; | |
2123 | struct device *kdev; | |
2124 | int i, ret; | |
2125 | unsigned int size; | |
2126 | void *p; | |
2127 | u32 val; | |
2128 | ||
2129 | priv = netdev_priv(dev); | |
2130 | kdev = &priv->pdev->dev; | |
2131 | ||
2132 | /* mask all interrupts and request them */ | |
2133 | enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan); | |
2134 | enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan); | |
2135 | ||
2136 | ret = request_irq(priv->irq_rx, bcm_enet_isr_dma, | |
2137 | 0, dev->name, dev); | |
2138 | if (ret) | |
2139 | goto out_freeirq; | |
2140 | ||
2141 | if (priv->irq_tx != -1) { | |
2142 | ret = request_irq(priv->irq_tx, bcm_enet_isr_dma, | |
2143 | 0, dev->name, dev); | |
2144 | if (ret) | |
2145 | goto out_freeirq_rx; | |
2146 | } | |
2147 | ||
2148 | /* allocate rx dma ring */ | |
2149 | size = priv->rx_ring_size * sizeof(struct bcm_enet_desc); | |
2150 | p = dma_alloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL); | |
2151 | if (!p) { | |
2152 | dev_err(kdev, "cannot allocate rx ring %u\n", size); | |
2153 | ret = -ENOMEM; | |
2154 | goto out_freeirq_tx; | |
2155 | } | |
2156 | ||
2157 | memset(p, 0, size); | |
2158 | priv->rx_desc_alloc_size = size; | |
2159 | priv->rx_desc_cpu = p; | |
2160 | ||
2161 | /* allocate tx dma ring */ | |
2162 | size = priv->tx_ring_size * sizeof(struct bcm_enet_desc); | |
2163 | p = dma_alloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL); | |
2164 | if (!p) { | |
2165 | dev_err(kdev, "cannot allocate tx ring\n"); | |
2166 | ret = -ENOMEM; | |
2167 | goto out_free_rx_ring; | |
2168 | } | |
2169 | ||
2170 | memset(p, 0, size); | |
2171 | priv->tx_desc_alloc_size = size; | |
2172 | priv->tx_desc_cpu = p; | |
2173 | ||
2174 | priv->tx_skb = kzalloc(sizeof(struct sk_buff *) * priv->tx_ring_size, | |
2175 | GFP_KERNEL); | |
2176 | if (!priv->tx_skb) { | |
2177 | dev_err(kdev, "cannot allocate rx skb queue\n"); | |
2178 | ret = -ENOMEM; | |
2179 | goto out_free_tx_ring; | |
2180 | } | |
2181 | ||
2182 | priv->tx_desc_count = priv->tx_ring_size; | |
2183 | priv->tx_dirty_desc = 0; | |
2184 | priv->tx_curr_desc = 0; | |
2185 | spin_lock_init(&priv->tx_lock); | |
2186 | ||
2187 | /* init & fill rx ring with skbs */ | |
2188 | priv->rx_skb = kzalloc(sizeof(struct sk_buff *) * priv->rx_ring_size, | |
2189 | GFP_KERNEL); | |
2190 | if (!priv->rx_skb) { | |
2191 | dev_err(kdev, "cannot allocate rx skb queue\n"); | |
2192 | ret = -ENOMEM; | |
2193 | goto out_free_tx_skb; | |
2194 | } | |
2195 | ||
2196 | priv->rx_desc_count = 0; | |
2197 | priv->rx_dirty_desc = 0; | |
2198 | priv->rx_curr_desc = 0; | |
2199 | ||
2200 | /* disable all ports */ | |
2201 | for (i = 0; i < priv->num_ports; i++) { | |
2202 | enetsw_writeb(priv, ENETSW_PORTOV_ENABLE_MASK, | |
2203 | ENETSW_PORTOV_REG(i)); | |
2204 | enetsw_writeb(priv, ENETSW_PTCTRL_RXDIS_MASK | | |
2205 | ENETSW_PTCTRL_TXDIS_MASK, | |
2206 | ENETSW_PTCTRL_REG(i)); | |
2207 | ||
2208 | priv->sw_port_link[i] = 0; | |
2209 | } | |
2210 | ||
2211 | /* reset mib */ | |
2212 | val = enetsw_readb(priv, ENETSW_GMCR_REG); | |
2213 | val |= ENETSW_GMCR_RST_MIB_MASK; | |
2214 | enetsw_writeb(priv, val, ENETSW_GMCR_REG); | |
2215 | mdelay(1); | |
2216 | val &= ~ENETSW_GMCR_RST_MIB_MASK; | |
2217 | enetsw_writeb(priv, val, ENETSW_GMCR_REG); | |
2218 | mdelay(1); | |
2219 | ||
2220 | /* force CPU port state */ | |
2221 | val = enetsw_readb(priv, ENETSW_IMPOV_REG); | |
2222 | val |= ENETSW_IMPOV_FORCE_MASK | ENETSW_IMPOV_LINKUP_MASK; | |
2223 | enetsw_writeb(priv, val, ENETSW_IMPOV_REG); | |
2224 | ||
2225 | /* enable switch forward engine */ | |
2226 | val = enetsw_readb(priv, ENETSW_SWMODE_REG); | |
2227 | val |= ENETSW_SWMODE_FWD_EN_MASK; | |
2228 | enetsw_writeb(priv, val, ENETSW_SWMODE_REG); | |
2229 | ||
2230 | /* enable jumbo on all ports */ | |
2231 | enetsw_writel(priv, 0x1ff, ENETSW_JMBCTL_PORT_REG); | |
2232 | enetsw_writew(priv, 9728, ENETSW_JMBCTL_MAXSIZE_REG); | |
2233 | ||
2234 | /* initialize flow control buffer allocation */ | |
2235 | enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0, | |
2236 | ENETDMA_BUFALLOC_REG(priv->rx_chan)); | |
2237 | ||
2238 | if (bcm_enet_refill_rx(dev)) { | |
2239 | dev_err(kdev, "cannot allocate rx skb queue\n"); | |
2240 | ret = -ENOMEM; | |
2241 | goto out; | |
2242 | } | |
2243 | ||
2244 | /* write rx & tx ring addresses */ | |
2245 | enet_dmas_writel(priv, priv->rx_desc_dma, | |
2246 | ENETDMAS_RSTART_REG, priv->rx_chan); | |
2247 | enet_dmas_writel(priv, priv->tx_desc_dma, | |
2248 | ENETDMAS_RSTART_REG, priv->tx_chan); | |
2249 | ||
2250 | /* clear remaining state ram for rx & tx channel */ | |
2251 | enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->rx_chan); | |
2252 | enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->tx_chan); | |
2253 | enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->rx_chan); | |
2254 | enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->tx_chan); | |
2255 | enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->rx_chan); | |
2256 | enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->tx_chan); | |
2257 | ||
2258 | /* set dma maximum burst len */ | |
2259 | enet_dmac_writel(priv, priv->dma_maxburst, | |
2260 | ENETDMAC_MAXBURST, priv->rx_chan); | |
2261 | enet_dmac_writel(priv, priv->dma_maxburst, | |
2262 | ENETDMAC_MAXBURST, priv->tx_chan); | |
2263 | ||
2264 | /* set flow control low/high threshold to 1/3 / 2/3 */ | |
2265 | val = priv->rx_ring_size / 3; | |
2266 | enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan)); | |
2267 | val = (priv->rx_ring_size * 2) / 3; | |
2268 | enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan)); | |
2269 | ||
2270 | /* all set, enable mac and interrupts, start dma engine and | |
2271 | * kick rx dma channel | |
2272 | */ | |
2273 | wmb(); | |
2274 | enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG); | |
2275 | enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK, | |
2276 | ENETDMAC_CHANCFG, priv->rx_chan); | |
2277 | ||
2278 | /* watch "packet transferred" interrupt in rx and tx */ | |
2279 | enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK, | |
2280 | ENETDMAC_IR, priv->rx_chan); | |
2281 | enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK, | |
2282 | ENETDMAC_IR, priv->tx_chan); | |
2283 | ||
2284 | /* make sure we enable napi before rx interrupt */ | |
2285 | napi_enable(&priv->napi); | |
2286 | ||
2287 | enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK, | |
2288 | ENETDMAC_IRMASK, priv->rx_chan); | |
2289 | enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK, | |
2290 | ENETDMAC_IRMASK, priv->tx_chan); | |
2291 | ||
2292 | netif_carrier_on(dev); | |
2293 | netif_start_queue(dev); | |
2294 | ||
2295 | /* apply override config for bypass_link ports here. */ | |
2296 | for (i = 0; i < priv->num_ports; i++) { | |
2297 | struct bcm63xx_enetsw_port *port; | |
2298 | u8 override; | |
2299 | port = &priv->used_ports[i]; | |
2300 | if (!port->used) | |
2301 | continue; | |
2302 | ||
2303 | if (!port->bypass_link) | |
2304 | continue; | |
2305 | ||
2306 | override = ENETSW_PORTOV_ENABLE_MASK | | |
2307 | ENETSW_PORTOV_LINKUP_MASK; | |
2308 | ||
2309 | switch (port->force_speed) { | |
2310 | case 1000: | |
2311 | override |= ENETSW_IMPOV_1000_MASK; | |
2312 | break; | |
2313 | case 100: | |
2314 | override |= ENETSW_IMPOV_100_MASK; | |
2315 | break; | |
2316 | case 10: | |
2317 | break; | |
2318 | default: | |
2319 | pr_warn("invalid forced speed on port %s: assume 10\n", | |
2320 | port->name); | |
2321 | break; | |
2322 | } | |
2323 | ||
2324 | if (port->force_duplex_full) | |
2325 | override |= ENETSW_IMPOV_FDX_MASK; | |
2326 | ||
2327 | ||
2328 | enetsw_writeb(priv, override, ENETSW_PORTOV_REG(i)); | |
2329 | enetsw_writeb(priv, 0, ENETSW_PTCTRL_REG(i)); | |
2330 | } | |
2331 | ||
2332 | /* start phy polling timer */ | |
2333 | init_timer(&priv->swphy_poll); | |
2334 | priv->swphy_poll.function = swphy_poll_timer; | |
2335 | priv->swphy_poll.data = (unsigned long)priv; | |
2336 | priv->swphy_poll.expires = jiffies; | |
2337 | add_timer(&priv->swphy_poll); | |
2338 | return 0; | |
2339 | ||
2340 | out: | |
2341 | for (i = 0; i < priv->rx_ring_size; i++) { | |
2342 | struct bcm_enet_desc *desc; | |
2343 | ||
2344 | if (!priv->rx_skb[i]) | |
2345 | continue; | |
2346 | ||
2347 | desc = &priv->rx_desc_cpu[i]; | |
2348 | dma_unmap_single(kdev, desc->address, priv->rx_skb_size, | |
2349 | DMA_FROM_DEVICE); | |
2350 | kfree_skb(priv->rx_skb[i]); | |
2351 | } | |
2352 | kfree(priv->rx_skb); | |
2353 | ||
2354 | out_free_tx_skb: | |
2355 | kfree(priv->tx_skb); | |
2356 | ||
2357 | out_free_tx_ring: | |
2358 | dma_free_coherent(kdev, priv->tx_desc_alloc_size, | |
2359 | priv->tx_desc_cpu, priv->tx_desc_dma); | |
2360 | ||
2361 | out_free_rx_ring: | |
2362 | dma_free_coherent(kdev, priv->rx_desc_alloc_size, | |
2363 | priv->rx_desc_cpu, priv->rx_desc_dma); | |
2364 | ||
2365 | out_freeirq_tx: | |
2366 | if (priv->irq_tx != -1) | |
2367 | free_irq(priv->irq_tx, dev); | |
2368 | ||
2369 | out_freeirq_rx: | |
2370 | free_irq(priv->irq_rx, dev); | |
2371 | ||
2372 | out_freeirq: | |
2373 | return ret; | |
2374 | } | |
2375 | ||
2376 | /* stop callback */ | |
2377 | static int bcm_enetsw_stop(struct net_device *dev) | |
2378 | { | |
2379 | struct bcm_enet_priv *priv; | |
2380 | struct device *kdev; | |
2381 | int i; | |
2382 | ||
2383 | priv = netdev_priv(dev); | |
2384 | kdev = &priv->pdev->dev; | |
2385 | ||
2386 | del_timer_sync(&priv->swphy_poll); | |
2387 | netif_stop_queue(dev); | |
2388 | napi_disable(&priv->napi); | |
2389 | del_timer_sync(&priv->rx_timeout); | |
2390 | ||
2391 | /* mask all interrupts */ | |
2392 | enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan); | |
2393 | enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan); | |
2394 | ||
2395 | /* disable dma & mac */ | |
2396 | bcm_enet_disable_dma(priv, priv->tx_chan); | |
2397 | bcm_enet_disable_dma(priv, priv->rx_chan); | |
2398 | ||
2399 | /* force reclaim of all tx buffers */ | |
2400 | bcm_enet_tx_reclaim(dev, 1); | |
2401 | ||
2402 | /* free the rx skb ring */ | |
2403 | for (i = 0; i < priv->rx_ring_size; i++) { | |
2404 | struct bcm_enet_desc *desc; | |
2405 | ||
2406 | if (!priv->rx_skb[i]) | |
2407 | continue; | |
2408 | ||
2409 | desc = &priv->rx_desc_cpu[i]; | |
2410 | dma_unmap_single(kdev, desc->address, priv->rx_skb_size, | |
2411 | DMA_FROM_DEVICE); | |
2412 | kfree_skb(priv->rx_skb[i]); | |
2413 | } | |
2414 | ||
2415 | /* free remaining allocated memory */ | |
2416 | kfree(priv->rx_skb); | |
2417 | kfree(priv->tx_skb); | |
2418 | dma_free_coherent(kdev, priv->rx_desc_alloc_size, | |
2419 | priv->rx_desc_cpu, priv->rx_desc_dma); | |
2420 | dma_free_coherent(kdev, priv->tx_desc_alloc_size, | |
2421 | priv->tx_desc_cpu, priv->tx_desc_dma); | |
2422 | if (priv->irq_tx != -1) | |
2423 | free_irq(priv->irq_tx, dev); | |
2424 | free_irq(priv->irq_rx, dev); | |
2425 | ||
2426 | return 0; | |
2427 | } | |
2428 | ||
2429 | /* try to sort out phy external status by walking the used_port field | |
2430 | * in the bcm_enet_priv structure. in case the phy address is not | |
2431 | * assigned to any physical port on the switch, assume it is external | |
2432 | * (and yell at the user). | |
2433 | */ | |
2434 | static int bcm_enetsw_phy_is_external(struct bcm_enet_priv *priv, int phy_id) | |
2435 | { | |
2436 | int i; | |
2437 | ||
2438 | for (i = 0; i < priv->num_ports; ++i) { | |
2439 | if (!priv->used_ports[i].used) | |
2440 | continue; | |
2441 | if (priv->used_ports[i].phy_id == phy_id) | |
2442 | return bcm_enet_port_is_rgmii(i); | |
2443 | } | |
2444 | ||
2445 | printk_once(KERN_WARNING "bcm63xx_enet: could not find a used port with phy_id %i, assuming phy is external\n", | |
2446 | phy_id); | |
2447 | return 1; | |
2448 | } | |
2449 | ||
2450 | /* can't use bcmenet_sw_mdio_read directly as we need to sort out | |
2451 | * external/internal status of the given phy_id first. | |
2452 | */ | |
2453 | static int bcm_enetsw_mii_mdio_read(struct net_device *dev, int phy_id, | |
2454 | int location) | |
2455 | { | |
2456 | struct bcm_enet_priv *priv; | |
2457 | ||
2458 | priv = netdev_priv(dev); | |
2459 | return bcmenet_sw_mdio_read(priv, | |
2460 | bcm_enetsw_phy_is_external(priv, phy_id), | |
2461 | phy_id, location); | |
2462 | } | |
2463 | ||
2464 | /* can't use bcmenet_sw_mdio_write directly as we need to sort out | |
2465 | * external/internal status of the given phy_id first. | |
2466 | */ | |
2467 | static void bcm_enetsw_mii_mdio_write(struct net_device *dev, int phy_id, | |
2468 | int location, | |
2469 | int val) | |
2470 | { | |
2471 | struct bcm_enet_priv *priv; | |
2472 | ||
2473 | priv = netdev_priv(dev); | |
2474 | bcmenet_sw_mdio_write(priv, bcm_enetsw_phy_is_external(priv, phy_id), | |
2475 | phy_id, location, val); | |
2476 | } | |
2477 | ||
2478 | static int bcm_enetsw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
2479 | { | |
2480 | struct mii_if_info mii; | |
2481 | ||
2482 | mii.dev = dev; | |
2483 | mii.mdio_read = bcm_enetsw_mii_mdio_read; | |
2484 | mii.mdio_write = bcm_enetsw_mii_mdio_write; | |
2485 | mii.phy_id = 0; | |
2486 | mii.phy_id_mask = 0x3f; | |
2487 | mii.reg_num_mask = 0x1f; | |
2488 | return generic_mii_ioctl(&mii, if_mii(rq), cmd, NULL); | |
2489 | ||
2490 | } | |
2491 | ||
2492 | static const struct net_device_ops bcm_enetsw_ops = { | |
2493 | .ndo_open = bcm_enetsw_open, | |
2494 | .ndo_stop = bcm_enetsw_stop, | |
2495 | .ndo_start_xmit = bcm_enet_start_xmit, | |
2496 | .ndo_change_mtu = bcm_enet_change_mtu, | |
2497 | .ndo_do_ioctl = bcm_enetsw_ioctl, | |
2498 | }; | |
2499 | ||
2500 | ||
2501 | static const struct bcm_enet_stats bcm_enetsw_gstrings_stats[] = { | |
2502 | { "rx_packets", DEV_STAT(rx_packets), -1 }, | |
2503 | { "tx_packets", DEV_STAT(tx_packets), -1 }, | |
2504 | { "rx_bytes", DEV_STAT(rx_bytes), -1 }, | |
2505 | { "tx_bytes", DEV_STAT(tx_bytes), -1 }, | |
2506 | { "rx_errors", DEV_STAT(rx_errors), -1 }, | |
2507 | { "tx_errors", DEV_STAT(tx_errors), -1 }, | |
2508 | { "rx_dropped", DEV_STAT(rx_dropped), -1 }, | |
2509 | { "tx_dropped", DEV_STAT(tx_dropped), -1 }, | |
2510 | ||
2511 | { "tx_good_octets", GEN_STAT(mib.tx_gd_octets), ETHSW_MIB_RX_GD_OCT }, | |
2512 | { "tx_unicast", GEN_STAT(mib.tx_unicast), ETHSW_MIB_RX_BRDCAST }, | |
2513 | { "tx_broadcast", GEN_STAT(mib.tx_brdcast), ETHSW_MIB_RX_BRDCAST }, | |
2514 | { "tx_multicast", GEN_STAT(mib.tx_mult), ETHSW_MIB_RX_MULT }, | |
2515 | { "tx_64_octets", GEN_STAT(mib.tx_64), ETHSW_MIB_RX_64 }, | |
2516 | { "tx_65_127_oct", GEN_STAT(mib.tx_65_127), ETHSW_MIB_RX_65_127 }, | |
2517 | { "tx_128_255_oct", GEN_STAT(mib.tx_128_255), ETHSW_MIB_RX_128_255 }, | |
2518 | { "tx_256_511_oct", GEN_STAT(mib.tx_256_511), ETHSW_MIB_RX_256_511 }, | |
2519 | { "tx_512_1023_oct", GEN_STAT(mib.tx_512_1023), ETHSW_MIB_RX_512_1023}, | |
2520 | { "tx_1024_1522_oct", GEN_STAT(mib.tx_1024_max), | |
2521 | ETHSW_MIB_RX_1024_1522 }, | |
2522 | { "tx_1523_2047_oct", GEN_STAT(mib.tx_1523_2047), | |
2523 | ETHSW_MIB_RX_1523_2047 }, | |
2524 | { "tx_2048_4095_oct", GEN_STAT(mib.tx_2048_4095), | |
2525 | ETHSW_MIB_RX_2048_4095 }, | |
2526 | { "tx_4096_8191_oct", GEN_STAT(mib.tx_4096_8191), | |
2527 | ETHSW_MIB_RX_4096_8191 }, | |
2528 | { "tx_8192_9728_oct", GEN_STAT(mib.tx_8192_9728), | |
2529 | ETHSW_MIB_RX_8192_9728 }, | |
2530 | { "tx_oversize", GEN_STAT(mib.tx_ovr), ETHSW_MIB_RX_OVR }, | |
2531 | { "tx_oversize_drop", GEN_STAT(mib.tx_ovr), ETHSW_MIB_RX_OVR_DISC }, | |
2532 | { "tx_dropped", GEN_STAT(mib.tx_drop), ETHSW_MIB_RX_DROP }, | |
2533 | { "tx_undersize", GEN_STAT(mib.tx_underrun), ETHSW_MIB_RX_UND }, | |
2534 | { "tx_pause", GEN_STAT(mib.tx_pause), ETHSW_MIB_RX_PAUSE }, | |
2535 | ||
2536 | { "rx_good_octets", GEN_STAT(mib.rx_gd_octets), ETHSW_MIB_TX_ALL_OCT }, | |
2537 | { "rx_broadcast", GEN_STAT(mib.rx_brdcast), ETHSW_MIB_TX_BRDCAST }, | |
2538 | { "rx_multicast", GEN_STAT(mib.rx_mult), ETHSW_MIB_TX_MULT }, | |
2539 | { "rx_unicast", GEN_STAT(mib.rx_unicast), ETHSW_MIB_TX_MULT }, | |
2540 | { "rx_pause", GEN_STAT(mib.rx_pause), ETHSW_MIB_TX_PAUSE }, | |
2541 | { "rx_dropped", GEN_STAT(mib.rx_drop), ETHSW_MIB_TX_DROP_PKTS }, | |
2542 | ||
2543 | }; | |
2544 | ||
2545 | #define BCM_ENETSW_STATS_LEN \ | |
2546 | (sizeof(bcm_enetsw_gstrings_stats) / sizeof(struct bcm_enet_stats)) | |
2547 | ||
2548 | static void bcm_enetsw_get_strings(struct net_device *netdev, | |
2549 | u32 stringset, u8 *data) | |
2550 | { | |
2551 | int i; | |
2552 | ||
2553 | switch (stringset) { | |
2554 | case ETH_SS_STATS: | |
2555 | for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) { | |
2556 | memcpy(data + i * ETH_GSTRING_LEN, | |
2557 | bcm_enetsw_gstrings_stats[i].stat_string, | |
2558 | ETH_GSTRING_LEN); | |
2559 | } | |
2560 | break; | |
2561 | } | |
2562 | } | |
2563 | ||
2564 | static int bcm_enetsw_get_sset_count(struct net_device *netdev, | |
2565 | int string_set) | |
2566 | { | |
2567 | switch (string_set) { | |
2568 | case ETH_SS_STATS: | |
2569 | return BCM_ENETSW_STATS_LEN; | |
2570 | default: | |
2571 | return -EINVAL; | |
2572 | } | |
2573 | } | |
2574 | ||
2575 | static void bcm_enetsw_get_drvinfo(struct net_device *netdev, | |
2576 | struct ethtool_drvinfo *drvinfo) | |
2577 | { | |
2578 | strncpy(drvinfo->driver, bcm_enet_driver_name, 32); | |
2579 | strncpy(drvinfo->version, bcm_enet_driver_version, 32); | |
2580 | strncpy(drvinfo->fw_version, "N/A", 32); | |
2581 | strncpy(drvinfo->bus_info, "bcm63xx", 32); | |
2582 | } | |
2583 | ||
2584 | static void bcm_enetsw_get_ethtool_stats(struct net_device *netdev, | |
2585 | struct ethtool_stats *stats, | |
2586 | u64 *data) | |
2587 | { | |
2588 | struct bcm_enet_priv *priv; | |
2589 | int i; | |
2590 | ||
2591 | priv = netdev_priv(netdev); | |
2592 | ||
2593 | for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) { | |
2594 | const struct bcm_enet_stats *s; | |
2595 | u32 lo, hi; | |
2596 | char *p; | |
2597 | int reg; | |
2598 | ||
2599 | s = &bcm_enetsw_gstrings_stats[i]; | |
2600 | ||
2601 | reg = s->mib_reg; | |
2602 | if (reg == -1) | |
2603 | continue; | |
2604 | ||
2605 | lo = enetsw_readl(priv, ENETSW_MIB_REG(reg)); | |
2606 | p = (char *)priv + s->stat_offset; | |
2607 | ||
2608 | if (s->sizeof_stat == sizeof(u64)) { | |
2609 | hi = enetsw_readl(priv, ENETSW_MIB_REG(reg + 1)); | |
2610 | *(u64 *)p = ((u64)hi << 32 | lo); | |
2611 | } else { | |
2612 | *(u32 *)p = lo; | |
2613 | } | |
2614 | } | |
2615 | ||
2616 | for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) { | |
2617 | const struct bcm_enet_stats *s; | |
2618 | char *p; | |
2619 | ||
2620 | s = &bcm_enetsw_gstrings_stats[i]; | |
2621 | ||
2622 | if (s->mib_reg == -1) | |
2623 | p = (char *)&netdev->stats + s->stat_offset; | |
2624 | else | |
2625 | p = (char *)priv + s->stat_offset; | |
2626 | ||
2627 | data[i] = (s->sizeof_stat == sizeof(u64)) ? | |
2628 | *(u64 *)p : *(u32 *)p; | |
2629 | } | |
2630 | } | |
2631 | ||
2632 | static void bcm_enetsw_get_ringparam(struct net_device *dev, | |
2633 | struct ethtool_ringparam *ering) | |
2634 | { | |
2635 | struct bcm_enet_priv *priv; | |
2636 | ||
2637 | priv = netdev_priv(dev); | |
2638 | ||
2639 | /* rx/tx ring is actually only limited by memory */ | |
2640 | ering->rx_max_pending = 8192; | |
2641 | ering->tx_max_pending = 8192; | |
2642 | ering->rx_mini_max_pending = 0; | |
2643 | ering->rx_jumbo_max_pending = 0; | |
2644 | ering->rx_pending = priv->rx_ring_size; | |
2645 | ering->tx_pending = priv->tx_ring_size; | |
2646 | } | |
2647 | ||
2648 | static int bcm_enetsw_set_ringparam(struct net_device *dev, | |
2649 | struct ethtool_ringparam *ering) | |
2650 | { | |
2651 | struct bcm_enet_priv *priv; | |
2652 | int was_running; | |
2653 | ||
2654 | priv = netdev_priv(dev); | |
2655 | ||
2656 | was_running = 0; | |
2657 | if (netif_running(dev)) { | |
2658 | bcm_enetsw_stop(dev); | |
2659 | was_running = 1; | |
2660 | } | |
2661 | ||
2662 | priv->rx_ring_size = ering->rx_pending; | |
2663 | priv->tx_ring_size = ering->tx_pending; | |
2664 | ||
2665 | if (was_running) { | |
2666 | int err; | |
2667 | ||
2668 | err = bcm_enetsw_open(dev); | |
2669 | if (err) | |
2670 | dev_close(dev); | |
2671 | } | |
2672 | return 0; | |
2673 | } | |
2674 | ||
2675 | static struct ethtool_ops bcm_enetsw_ethtool_ops = { | |
2676 | .get_strings = bcm_enetsw_get_strings, | |
2677 | .get_sset_count = bcm_enetsw_get_sset_count, | |
2678 | .get_ethtool_stats = bcm_enetsw_get_ethtool_stats, | |
2679 | .get_drvinfo = bcm_enetsw_get_drvinfo, | |
2680 | .get_ringparam = bcm_enetsw_get_ringparam, | |
2681 | .set_ringparam = bcm_enetsw_set_ringparam, | |
2682 | }; | |
2683 | ||
2684 | /* allocate netdevice, request register memory and register device. */ | |
2685 | static int bcm_enetsw_probe(struct platform_device *pdev) | |
2686 | { | |
2687 | struct bcm_enet_priv *priv; | |
2688 | struct net_device *dev; | |
2689 | struct bcm63xx_enetsw_platform_data *pd; | |
2690 | struct resource *res_mem; | |
2691 | int ret, irq_rx, irq_tx; | |
2692 | ||
2693 | /* stop if shared driver failed, assume driver->probe will be | |
2694 | * called in the same order we register devices (correct ?) | |
2695 | */ | |
2696 | if (!bcm_enet_shared_base[0]) | |
2697 | return -ENODEV; | |
2698 | ||
2699 | res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
2700 | irq_rx = platform_get_irq(pdev, 0); | |
2701 | irq_tx = platform_get_irq(pdev, 1); | |
2702 | if (!res_mem || irq_rx < 0) | |
2703 | return -ENODEV; | |
2704 | ||
2705 | ret = 0; | |
2706 | dev = alloc_etherdev(sizeof(*priv)); | |
2707 | if (!dev) | |
2708 | return -ENOMEM; | |
2709 | priv = netdev_priv(dev); | |
2710 | memset(priv, 0, sizeof(*priv)); | |
2711 | ||
2712 | /* initialize default and fetch platform data */ | |
2713 | priv->enet_is_sw = true; | |
2714 | priv->irq_rx = irq_rx; | |
2715 | priv->irq_tx = irq_tx; | |
2716 | priv->rx_ring_size = BCMENET_DEF_RX_DESC; | |
2717 | priv->tx_ring_size = BCMENET_DEF_TX_DESC; | |
2718 | priv->dma_maxburst = BCMENETSW_DMA_MAXBURST; | |
2719 | ||
2720 | pd = dev_get_platdata(&pdev->dev); | |
2721 | if (pd) { | |
2722 | memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN); | |
2723 | memcpy(priv->used_ports, pd->used_ports, | |
2724 | sizeof(pd->used_ports)); | |
2725 | priv->num_ports = pd->num_ports; | |
2726 | priv->dma_has_sram = pd->dma_has_sram; | |
2727 | priv->dma_chan_en_mask = pd->dma_chan_en_mask; | |
2728 | priv->dma_chan_int_mask = pd->dma_chan_int_mask; | |
2729 | priv->dma_chan_width = pd->dma_chan_width; | |
2730 | } | |
2731 | ||
2732 | ret = bcm_enet_change_mtu(dev, dev->mtu); | |
2733 | if (ret) | |
2734 | goto out; | |
2735 | ||
2736 | if (!request_mem_region(res_mem->start, resource_size(res_mem), | |
2737 | "bcm63xx_enetsw")) { | |
2738 | ret = -EBUSY; | |
2739 | goto out; | |
2740 | } | |
2741 | ||
2742 | priv->base = ioremap(res_mem->start, resource_size(res_mem)); | |
2743 | if (priv->base == NULL) { | |
2744 | ret = -ENOMEM; | |
2745 | goto out_release_mem; | |
2746 | } | |
2747 | ||
2748 | priv->mac_clk = clk_get(&pdev->dev, "enetsw"); | |
2749 | if (IS_ERR(priv->mac_clk)) { | |
2750 | ret = PTR_ERR(priv->mac_clk); | |
2751 | goto out_unmap; | |
2752 | } | |
2753 | clk_enable(priv->mac_clk); | |
2754 | ||
2755 | priv->rx_chan = 0; | |
2756 | priv->tx_chan = 1; | |
2757 | spin_lock_init(&priv->rx_lock); | |
2758 | ||
2759 | /* init rx timeout (used for oom) */ | |
2760 | init_timer(&priv->rx_timeout); | |
2761 | priv->rx_timeout.function = bcm_enet_refill_rx_timer; | |
2762 | priv->rx_timeout.data = (unsigned long)dev; | |
2763 | ||
2764 | /* register netdevice */ | |
2765 | dev->netdev_ops = &bcm_enetsw_ops; | |
2766 | netif_napi_add(dev, &priv->napi, bcm_enet_poll, 16); | |
2767 | dev->ethtool_ops = &bcm_enetsw_ethtool_ops; | |
2768 | SET_NETDEV_DEV(dev, &pdev->dev); | |
2769 | ||
2770 | spin_lock_init(&priv->enetsw_mdio_lock); | |
2771 | ||
2772 | ret = register_netdev(dev); | |
2773 | if (ret) | |
2774 | goto out_put_clk; | |
2775 | ||
2776 | netif_carrier_off(dev); | |
2777 | platform_set_drvdata(pdev, dev); | |
2778 | priv->pdev = pdev; | |
2779 | priv->net_dev = dev; | |
2780 | ||
2781 | return 0; | |
2782 | ||
2783 | out_put_clk: | |
2784 | clk_put(priv->mac_clk); | |
2785 | ||
2786 | out_unmap: | |
2787 | iounmap(priv->base); | |
2788 | ||
2789 | out_release_mem: | |
2790 | release_mem_region(res_mem->start, resource_size(res_mem)); | |
2791 | out: | |
2792 | free_netdev(dev); | |
2793 | return ret; | |
2794 | } | |
2795 | ||
2796 | ||
2797 | /* exit func, stops hardware and unregisters netdevice */ | |
2798 | static int bcm_enetsw_remove(struct platform_device *pdev) | |
2799 | { | |
2800 | struct bcm_enet_priv *priv; | |
2801 | struct net_device *dev; | |
2802 | struct resource *res; | |
2803 | ||
2804 | /* stop netdevice */ | |
2805 | dev = platform_get_drvdata(pdev); | |
2806 | priv = netdev_priv(dev); | |
2807 | unregister_netdev(dev); | |
2808 | ||
2809 | /* release device resources */ | |
2810 | iounmap(priv->base); | |
2811 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
2812 | release_mem_region(res->start, resource_size(res)); | |
2813 | ||
2814 | free_netdev(dev); | |
2815 | return 0; | |
2816 | } | |
2817 | ||
2818 | struct platform_driver bcm63xx_enetsw_driver = { | |
2819 | .probe = bcm_enetsw_probe, | |
2820 | .remove = bcm_enetsw_remove, | |
2821 | .driver = { | |
2822 | .name = "bcm63xx_enetsw", | |
2823 | .owner = THIS_MODULE, | |
2824 | }, | |
2825 | }; | |
2826 | ||
2827 | /* reserve & remap memory space shared between all macs */ | |
2828 | static int bcm_enet_shared_probe(struct platform_device *pdev) | |
2829 | { | |
2830 | struct resource *res; | |
2831 | void __iomem *p[3]; | |
2832 | unsigned int i; | |
2833 | ||
2834 | memset(bcm_enet_shared_base, 0, sizeof(bcm_enet_shared_base)); | |
2835 | ||
2836 | for (i = 0; i < 3; i++) { | |
2837 | res = platform_get_resource(pdev, IORESOURCE_MEM, i); | |
2838 | p[i] = devm_ioremap_resource(&pdev->dev, res); | |
2839 | if (IS_ERR(p[i])) | |
2840 | return PTR_ERR(p[i]); | |
2841 | } | |
2842 | ||
2843 | memcpy(bcm_enet_shared_base, p, sizeof(bcm_enet_shared_base)); | |
2844 | ||
2845 | return 0; | |
2846 | } | |
2847 | ||
2848 | static int bcm_enet_shared_remove(struct platform_device *pdev) | |
2849 | { | |
2850 | return 0; | |
2851 | } | |
2852 | ||
2853 | /* this "shared" driver is needed because both macs share a single | |
2854 | * address space | |
2855 | */ | |
2856 | struct platform_driver bcm63xx_enet_shared_driver = { | |
2857 | .probe = bcm_enet_shared_probe, | |
2858 | .remove = bcm_enet_shared_remove, | |
2859 | .driver = { | |
2860 | .name = "bcm63xx_enet_shared", | |
2861 | .owner = THIS_MODULE, | |
2862 | }, | |
2863 | }; | |
2864 | ||
2865 | static struct platform_driver * const drivers[] = { | |
2866 | &bcm63xx_enet_shared_driver, | |
2867 | &bcm63xx_enet_driver, | |
2868 | &bcm63xx_enetsw_driver, | |
2869 | }; | |
2870 | ||
2871 | /* entry point */ | |
2872 | static int __init bcm_enet_init(void) | |
2873 | { | |
2874 | return platform_register_drivers(drivers, ARRAY_SIZE(drivers)); | |
2875 | } | |
2876 | ||
2877 | static void __exit bcm_enet_exit(void) | |
2878 | { | |
2879 | platform_unregister_drivers(drivers, ARRAY_SIZE(drivers)); | |
2880 | } | |
2881 | ||
2882 | ||
2883 | module_init(bcm_enet_init); | |
2884 | module_exit(bcm_enet_exit); | |
2885 | ||
2886 | MODULE_DESCRIPTION("BCM63xx internal ethernet mac driver"); | |
2887 | MODULE_AUTHOR("Maxime Bizon <mbizon@freebox.fr>"); | |
2888 | MODULE_LICENSE("GPL"); |