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1 | /* | |
2 | * Broadcom GENET MDIO routines | |
3 | * | |
4 | * Copyright (c) 2014-2017 Broadcom | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | ||
12 | #include <linux/types.h> | |
13 | #include <linux/delay.h> | |
14 | #include <linux/wait.h> | |
15 | #include <linux/mii.h> | |
16 | #include <linux/ethtool.h> | |
17 | #include <linux/bitops.h> | |
18 | #include <linux/netdevice.h> | |
19 | #include <linux/platform_device.h> | |
20 | #include <linux/phy.h> | |
21 | #include <linux/phy_fixed.h> | |
22 | #include <linux/brcmphy.h> | |
23 | #include <linux/of.h> | |
24 | #include <linux/of_net.h> | |
25 | #include <linux/of_mdio.h> | |
26 | #include <linux/platform_data/bcmgenet.h> | |
27 | ||
28 | #include "bcmgenet.h" | |
29 | ||
30 | /* read a value from the MII */ | |
31 | static int bcmgenet_mii_read(struct mii_bus *bus, int phy_id, int location) | |
32 | { | |
33 | int ret; | |
34 | struct net_device *dev = bus->priv; | |
35 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
36 | u32 reg; | |
37 | ||
38 | bcmgenet_umac_writel(priv, (MDIO_RD | (phy_id << MDIO_PMD_SHIFT) | | |
39 | (location << MDIO_REG_SHIFT)), UMAC_MDIO_CMD); | |
40 | /* Start MDIO transaction*/ | |
41 | reg = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD); | |
42 | reg |= MDIO_START_BUSY; | |
43 | bcmgenet_umac_writel(priv, reg, UMAC_MDIO_CMD); | |
44 | wait_event_timeout(priv->wq, | |
45 | !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD) | |
46 | & MDIO_START_BUSY), | |
47 | HZ / 100); | |
48 | ret = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD); | |
49 | ||
50 | /* Some broken devices are known not to release the line during | |
51 | * turn-around, e.g: Broadcom BCM53125 external switches, so check for | |
52 | * that condition here and ignore the MDIO controller read failure | |
53 | * indication. | |
54 | */ | |
55 | if (!(bus->phy_ignore_ta_mask & 1 << phy_id) && (ret & MDIO_READ_FAIL)) | |
56 | return -EIO; | |
57 | ||
58 | return ret & 0xffff; | |
59 | } | |
60 | ||
61 | /* write a value to the MII */ | |
62 | static int bcmgenet_mii_write(struct mii_bus *bus, int phy_id, | |
63 | int location, u16 val) | |
64 | { | |
65 | struct net_device *dev = bus->priv; | |
66 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
67 | u32 reg; | |
68 | ||
69 | bcmgenet_umac_writel(priv, (MDIO_WR | (phy_id << MDIO_PMD_SHIFT) | | |
70 | (location << MDIO_REG_SHIFT) | (0xffff & val)), | |
71 | UMAC_MDIO_CMD); | |
72 | reg = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD); | |
73 | reg |= MDIO_START_BUSY; | |
74 | bcmgenet_umac_writel(priv, reg, UMAC_MDIO_CMD); | |
75 | wait_event_timeout(priv->wq, | |
76 | !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD) & | |
77 | MDIO_START_BUSY), | |
78 | HZ / 100); | |
79 | ||
80 | return 0; | |
81 | } | |
82 | ||
83 | /* setup netdev link state when PHY link status change and | |
84 | * update UMAC and RGMII block when link up | |
85 | */ | |
86 | void bcmgenet_mii_setup(struct net_device *dev) | |
87 | { | |
88 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
89 | struct phy_device *phydev = priv->phydev; | |
90 | u32 reg, cmd_bits = 0; | |
91 | bool status_changed = false; | |
92 | ||
93 | if (priv->old_link != phydev->link) { | |
94 | status_changed = true; | |
95 | priv->old_link = phydev->link; | |
96 | } | |
97 | ||
98 | if (phydev->link) { | |
99 | /* check speed/duplex/pause changes */ | |
100 | if (priv->old_speed != phydev->speed) { | |
101 | status_changed = true; | |
102 | priv->old_speed = phydev->speed; | |
103 | } | |
104 | ||
105 | if (priv->old_duplex != phydev->duplex) { | |
106 | status_changed = true; | |
107 | priv->old_duplex = phydev->duplex; | |
108 | } | |
109 | ||
110 | if (priv->old_pause != phydev->pause) { | |
111 | status_changed = true; | |
112 | priv->old_pause = phydev->pause; | |
113 | } | |
114 | ||
115 | /* done if nothing has changed */ | |
116 | if (!status_changed) | |
117 | return; | |
118 | ||
119 | /* speed */ | |
120 | if (phydev->speed == SPEED_1000) | |
121 | cmd_bits = UMAC_SPEED_1000; | |
122 | else if (phydev->speed == SPEED_100) | |
123 | cmd_bits = UMAC_SPEED_100; | |
124 | else | |
125 | cmd_bits = UMAC_SPEED_10; | |
126 | cmd_bits <<= CMD_SPEED_SHIFT; | |
127 | ||
128 | /* duplex */ | |
129 | if (phydev->duplex != DUPLEX_FULL) | |
130 | cmd_bits |= CMD_HD_EN; | |
131 | ||
132 | /* pause capability */ | |
133 | if (!phydev->pause) | |
134 | cmd_bits |= CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE; | |
135 | ||
136 | /* | |
137 | * Program UMAC and RGMII block based on established | |
138 | * link speed, duplex, and pause. The speed set in | |
139 | * umac->cmd tell RGMII block which clock to use for | |
140 | * transmit -- 25MHz(100Mbps) or 125MHz(1Gbps). | |
141 | * Receive clock is provided by the PHY. | |
142 | */ | |
143 | reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL); | |
144 | reg &= ~OOB_DISABLE; | |
145 | reg |= RGMII_LINK; | |
146 | bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL); | |
147 | ||
148 | reg = bcmgenet_umac_readl(priv, UMAC_CMD); | |
149 | reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) | | |
150 | CMD_HD_EN | | |
151 | CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE); | |
152 | reg |= cmd_bits; | |
153 | bcmgenet_umac_writel(priv, reg, UMAC_CMD); | |
154 | } else { | |
155 | /* done if nothing has changed */ | |
156 | if (!status_changed) | |
157 | return; | |
158 | ||
159 | /* needed for MoCA fixed PHY to reflect correct link status */ | |
160 | netif_carrier_off(dev); | |
161 | } | |
162 | ||
163 | phy_print_status(phydev); | |
164 | } | |
165 | ||
166 | ||
167 | static int bcmgenet_fixed_phy_link_update(struct net_device *dev, | |
168 | struct fixed_phy_status *status) | |
169 | { | |
170 | if (dev && dev->phydev && status) | |
171 | status->link = dev->phydev->link; | |
172 | ||
173 | return 0; | |
174 | } | |
175 | ||
176 | /* Perform a voluntary PHY software reset, since the EPHY is very finicky about | |
177 | * not doing it and will start corrupting packets | |
178 | */ | |
179 | void bcmgenet_mii_reset(struct net_device *dev) | |
180 | { | |
181 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
182 | ||
183 | if (GENET_IS_V4(priv)) | |
184 | return; | |
185 | ||
186 | if (priv->phydev) { | |
187 | phy_init_hw(priv->phydev); | |
188 | phy_start_aneg(priv->phydev); | |
189 | } | |
190 | } | |
191 | ||
192 | void bcmgenet_phy_power_set(struct net_device *dev, bool enable) | |
193 | { | |
194 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
195 | u32 reg = 0; | |
196 | ||
197 | /* EXT_GPHY_CTRL is only valid for GENETv4 and onward */ | |
198 | if (GENET_IS_V4(priv)) { | |
199 | reg = bcmgenet_ext_readl(priv, EXT_GPHY_CTRL); | |
200 | if (enable) { | |
201 | reg &= ~EXT_CK25_DIS; | |
202 | bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); | |
203 | mdelay(1); | |
204 | ||
205 | reg &= ~(EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN); | |
206 | reg |= EXT_GPHY_RESET; | |
207 | bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); | |
208 | mdelay(1); | |
209 | ||
210 | reg &= ~EXT_GPHY_RESET; | |
211 | } else { | |
212 | reg |= EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN | | |
213 | EXT_GPHY_RESET; | |
214 | bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); | |
215 | mdelay(1); | |
216 | reg |= EXT_CK25_DIS; | |
217 | } | |
218 | bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); | |
219 | udelay(60); | |
220 | } else { | |
221 | mdelay(1); | |
222 | } | |
223 | } | |
224 | ||
225 | static void bcmgenet_moca_phy_setup(struct bcmgenet_priv *priv) | |
226 | { | |
227 | u32 reg; | |
228 | ||
229 | if (!GENET_IS_V5(priv)) { | |
230 | /* Speed settings are set in bcmgenet_mii_setup() */ | |
231 | reg = bcmgenet_sys_readl(priv, SYS_PORT_CTRL); | |
232 | reg |= LED_ACT_SOURCE_MAC; | |
233 | bcmgenet_sys_writel(priv, reg, SYS_PORT_CTRL); | |
234 | } | |
235 | ||
236 | if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET) | |
237 | fixed_phy_set_link_update(priv->phydev, | |
238 | bcmgenet_fixed_phy_link_update); | |
239 | } | |
240 | ||
241 | int bcmgenet_mii_config(struct net_device *dev, bool init) | |
242 | { | |
243 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
244 | struct phy_device *phydev = priv->phydev; | |
245 | struct device *kdev = &priv->pdev->dev; | |
246 | const char *phy_name = NULL; | |
247 | u32 id_mode_dis = 0; | |
248 | u32 port_ctrl; | |
249 | u32 reg; | |
250 | ||
251 | priv->ext_phy = !priv->internal_phy && | |
252 | (priv->phy_interface != PHY_INTERFACE_MODE_MOCA); | |
253 | ||
254 | switch (priv->phy_interface) { | |
255 | case PHY_INTERFACE_MODE_INTERNAL: | |
256 | case PHY_INTERFACE_MODE_MOCA: | |
257 | /* Irrespective of the actually configured PHY speed (100 or | |
258 | * 1000) GENETv4 only has an internal GPHY so we will just end | |
259 | * up masking the Gigabit features from what we support, not | |
260 | * switching to the EPHY | |
261 | */ | |
262 | if (GENET_IS_V4(priv)) | |
263 | port_ctrl = PORT_MODE_INT_GPHY; | |
264 | else | |
265 | port_ctrl = PORT_MODE_INT_EPHY; | |
266 | ||
267 | bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL); | |
268 | ||
269 | if (priv->internal_phy) { | |
270 | phy_name = "internal PHY"; | |
271 | } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) { | |
272 | phy_name = "MoCA"; | |
273 | bcmgenet_moca_phy_setup(priv); | |
274 | } | |
275 | break; | |
276 | ||
277 | case PHY_INTERFACE_MODE_MII: | |
278 | phy_name = "external MII"; | |
279 | phydev->supported &= PHY_BASIC_FEATURES; | |
280 | bcmgenet_sys_writel(priv, | |
281 | PORT_MODE_EXT_EPHY, SYS_PORT_CTRL); | |
282 | break; | |
283 | ||
284 | case PHY_INTERFACE_MODE_REVMII: | |
285 | phy_name = "external RvMII"; | |
286 | /* of_mdiobus_register took care of reading the 'max-speed' | |
287 | * PHY property for us, effectively limiting the PHY supported | |
288 | * capabilities, use that knowledge to also configure the | |
289 | * Reverse MII interface correctly. | |
290 | */ | |
291 | if ((priv->phydev->supported & PHY_BASIC_FEATURES) == | |
292 | PHY_BASIC_FEATURES) | |
293 | port_ctrl = PORT_MODE_EXT_RVMII_25; | |
294 | else | |
295 | port_ctrl = PORT_MODE_EXT_RVMII_50; | |
296 | bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL); | |
297 | break; | |
298 | ||
299 | case PHY_INTERFACE_MODE_RGMII: | |
300 | /* RGMII_NO_ID: TXC transitions at the same time as TXD | |
301 | * (requires PCB or receiver-side delay) | |
302 | * RGMII: Add 2ns delay on TXC (90 degree shift) | |
303 | * | |
304 | * ID is implicitly disabled for 100Mbps (RG)MII operation. | |
305 | */ | |
306 | id_mode_dis = BIT(16); | |
307 | /* fall through */ | |
308 | case PHY_INTERFACE_MODE_RGMII_TXID: | |
309 | if (id_mode_dis) | |
310 | phy_name = "external RGMII (no delay)"; | |
311 | else | |
312 | phy_name = "external RGMII (TX delay)"; | |
313 | bcmgenet_sys_writel(priv, | |
314 | PORT_MODE_EXT_GPHY, SYS_PORT_CTRL); | |
315 | break; | |
316 | default: | |
317 | dev_err(kdev, "unknown phy mode: %d\n", priv->phy_interface); | |
318 | return -EINVAL; | |
319 | } | |
320 | ||
321 | /* This is an external PHY (xMII), so we need to enable the RGMII | |
322 | * block for the interface to work | |
323 | */ | |
324 | if (priv->ext_phy) { | |
325 | reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL); | |
326 | reg |= RGMII_MODE_EN | id_mode_dis; | |
327 | bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL); | |
328 | } | |
329 | ||
330 | if (init) | |
331 | dev_info(kdev, "configuring instance for %s\n", phy_name); | |
332 | ||
333 | return 0; | |
334 | } | |
335 | ||
336 | int bcmgenet_mii_probe(struct net_device *dev) | |
337 | { | |
338 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
339 | struct device_node *dn = priv->pdev->dev.of_node; | |
340 | struct phy_device *phydev; | |
341 | u32 phy_flags; | |
342 | int ret; | |
343 | ||
344 | /* Communicate the integrated PHY revision */ | |
345 | phy_flags = priv->gphy_rev; | |
346 | ||
347 | /* Initialize link state variables that bcmgenet_mii_setup() uses */ | |
348 | priv->old_link = -1; | |
349 | priv->old_speed = -1; | |
350 | priv->old_duplex = -1; | |
351 | priv->old_pause = -1; | |
352 | ||
353 | if (dn) { | |
354 | phydev = of_phy_connect(dev, priv->phy_dn, bcmgenet_mii_setup, | |
355 | phy_flags, priv->phy_interface); | |
356 | if (!phydev) { | |
357 | pr_err("could not attach to PHY\n"); | |
358 | return -ENODEV; | |
359 | } | |
360 | } else { | |
361 | phydev = priv->phydev; | |
362 | phydev->dev_flags = phy_flags; | |
363 | ||
364 | ret = phy_connect_direct(dev, phydev, bcmgenet_mii_setup, | |
365 | priv->phy_interface); | |
366 | if (ret) { | |
367 | pr_err("could not attach to PHY\n"); | |
368 | return -ENODEV; | |
369 | } | |
370 | } | |
371 | ||
372 | priv->phydev = phydev; | |
373 | ||
374 | /* Configure port multiplexer based on what the probed PHY device since | |
375 | * reading the 'max-speed' property determines the maximum supported | |
376 | * PHY speed which is needed for bcmgenet_mii_config() to configure | |
377 | * things appropriately. | |
378 | */ | |
379 | ret = bcmgenet_mii_config(dev, true); | |
380 | if (ret) { | |
381 | phy_disconnect(priv->phydev); | |
382 | return ret; | |
383 | } | |
384 | ||
385 | phydev->advertising = phydev->supported; | |
386 | ||
387 | /* The internal PHY has its link interrupts routed to the | |
388 | * Ethernet MAC ISRs | |
389 | */ | |
390 | if (priv->internal_phy) | |
391 | priv->phydev->irq = PHY_IGNORE_INTERRUPT; | |
392 | ||
393 | return 0; | |
394 | } | |
395 | ||
396 | /* Workaround for integrated BCM7xxx Gigabit PHYs which have a problem with | |
397 | * their internal MDIO management controller making them fail to successfully | |
398 | * be read from or written to for the first transaction. We insert a dummy | |
399 | * BMSR read here to make sure that phy_get_device() and get_phy_id() can | |
400 | * correctly read the PHY MII_PHYSID1/2 registers and successfully register a | |
401 | * PHY device for this peripheral. | |
402 | * | |
403 | * Once the PHY driver is registered, we can workaround subsequent reads from | |
404 | * there (e.g: during system-wide power management). | |
405 | * | |
406 | * bus->reset is invoked before mdiobus_scan during mdiobus_register and is | |
407 | * therefore the right location to stick that workaround. Since we do not want | |
408 | * to read from non-existing PHYs, we either use bus->phy_mask or do a manual | |
409 | * Device Tree scan to limit the search area. | |
410 | */ | |
411 | static int bcmgenet_mii_bus_reset(struct mii_bus *bus) | |
412 | { | |
413 | struct net_device *dev = bus->priv; | |
414 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
415 | struct device_node *np = priv->mdio_dn; | |
416 | struct device_node *child = NULL; | |
417 | u32 read_mask = 0; | |
418 | int addr = 0; | |
419 | ||
420 | if (!np) { | |
421 | read_mask = 1 << priv->phy_addr; | |
422 | } else { | |
423 | for_each_available_child_of_node(np, child) { | |
424 | addr = of_mdio_parse_addr(&dev->dev, child); | |
425 | if (addr < 0) | |
426 | continue; | |
427 | ||
428 | read_mask |= 1 << addr; | |
429 | } | |
430 | } | |
431 | ||
432 | for (addr = 0; addr < PHY_MAX_ADDR; addr++) { | |
433 | if (read_mask & 1 << addr) { | |
434 | dev_dbg(&dev->dev, "Workaround for PHY @ %d\n", addr); | |
435 | mdiobus_read(bus, addr, MII_BMSR); | |
436 | } | |
437 | } | |
438 | ||
439 | return 0; | |
440 | } | |
441 | ||
442 | static int bcmgenet_mii_alloc(struct bcmgenet_priv *priv) | |
443 | { | |
444 | struct mii_bus *bus; | |
445 | ||
446 | if (priv->mii_bus) | |
447 | return 0; | |
448 | ||
449 | priv->mii_bus = mdiobus_alloc(); | |
450 | if (!priv->mii_bus) { | |
451 | pr_err("failed to allocate\n"); | |
452 | return -ENOMEM; | |
453 | } | |
454 | ||
455 | bus = priv->mii_bus; | |
456 | bus->priv = priv->dev; | |
457 | bus->name = "bcmgenet MII bus"; | |
458 | bus->parent = &priv->pdev->dev; | |
459 | bus->read = bcmgenet_mii_read; | |
460 | bus->write = bcmgenet_mii_write; | |
461 | bus->reset = bcmgenet_mii_bus_reset; | |
462 | snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d", | |
463 | priv->pdev->name, priv->pdev->id); | |
464 | ||
465 | return 0; | |
466 | } | |
467 | ||
468 | static int bcmgenet_mii_of_init(struct bcmgenet_priv *priv) | |
469 | { | |
470 | struct device_node *dn = priv->pdev->dev.of_node; | |
471 | struct device *kdev = &priv->pdev->dev; | |
472 | struct phy_device *phydev = NULL; | |
473 | char *compat; | |
474 | int phy_mode; | |
475 | int ret; | |
476 | ||
477 | compat = kasprintf(GFP_KERNEL, "brcm,genet-mdio-v%d", priv->version); | |
478 | if (!compat) | |
479 | return -ENOMEM; | |
480 | ||
481 | priv->mdio_dn = of_find_compatible_node(dn, NULL, compat); | |
482 | kfree(compat); | |
483 | if (!priv->mdio_dn) { | |
484 | dev_err(kdev, "unable to find MDIO bus node\n"); | |
485 | return -ENODEV; | |
486 | } | |
487 | ||
488 | ret = of_mdiobus_register(priv->mii_bus, priv->mdio_dn); | |
489 | if (ret) { | |
490 | dev_err(kdev, "failed to register MDIO bus\n"); | |
491 | return ret; | |
492 | } | |
493 | ||
494 | /* Fetch the PHY phandle */ | |
495 | priv->phy_dn = of_parse_phandle(dn, "phy-handle", 0); | |
496 | ||
497 | /* In the case of a fixed PHY, the DT node associated | |
498 | * to the PHY is the Ethernet MAC DT node. | |
499 | */ | |
500 | if (!priv->phy_dn && of_phy_is_fixed_link(dn)) { | |
501 | ret = of_phy_register_fixed_link(dn); | |
502 | if (ret) | |
503 | return ret; | |
504 | ||
505 | priv->phy_dn = of_node_get(dn); | |
506 | } | |
507 | ||
508 | /* Get the link mode */ | |
509 | phy_mode = of_get_phy_mode(dn); | |
510 | if (phy_mode < 0) { | |
511 | dev_err(kdev, "invalid PHY mode property\n"); | |
512 | return phy_mode; | |
513 | } | |
514 | ||
515 | priv->phy_interface = phy_mode; | |
516 | ||
517 | /* We need to specifically look up whether this PHY interface is internal | |
518 | * or not *before* we even try to probe the PHY driver over MDIO as we | |
519 | * may have shut down the internal PHY for power saving purposes. | |
520 | */ | |
521 | if (priv->phy_interface == PHY_INTERFACE_MODE_INTERNAL) | |
522 | priv->internal_phy = true; | |
523 | ||
524 | /* Make sure we initialize MoCA PHYs with a link down */ | |
525 | if (phy_mode == PHY_INTERFACE_MODE_MOCA) { | |
526 | phydev = of_phy_find_device(dn); | |
527 | if (phydev) { | |
528 | phydev->link = 0; | |
529 | put_device(&phydev->mdio.dev); | |
530 | } | |
531 | } | |
532 | ||
533 | return 0; | |
534 | } | |
535 | ||
536 | static int bcmgenet_mii_pd_init(struct bcmgenet_priv *priv) | |
537 | { | |
538 | struct device *kdev = &priv->pdev->dev; | |
539 | struct bcmgenet_platform_data *pd = kdev->platform_data; | |
540 | struct mii_bus *mdio = priv->mii_bus; | |
541 | struct phy_device *phydev; | |
542 | int ret; | |
543 | ||
544 | if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) { | |
545 | /* | |
546 | * Internal or external PHY with MDIO access | |
547 | */ | |
548 | if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR) | |
549 | mdio->phy_mask = ~(1 << pd->phy_address); | |
550 | else | |
551 | mdio->phy_mask = 0; | |
552 | ||
553 | ret = mdiobus_register(mdio); | |
554 | if (ret) { | |
555 | dev_err(kdev, "failed to register MDIO bus\n"); | |
556 | return ret; | |
557 | } | |
558 | ||
559 | if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR) | |
560 | phydev = mdiobus_get_phy(mdio, pd->phy_address); | |
561 | else | |
562 | phydev = phy_find_first(mdio); | |
563 | ||
564 | if (!phydev) { | |
565 | dev_err(kdev, "failed to register PHY device\n"); | |
566 | mdiobus_unregister(mdio); | |
567 | return -ENODEV; | |
568 | } | |
569 | } else { | |
570 | /* | |
571 | * MoCA port or no MDIO access. | |
572 | * Use fixed PHY to represent the link layer. | |
573 | */ | |
574 | struct fixed_phy_status fphy_status = { | |
575 | .link = 1, | |
576 | .speed = pd->phy_speed, | |
577 | .duplex = pd->phy_duplex, | |
578 | .pause = 0, | |
579 | .asym_pause = 0, | |
580 | }; | |
581 | ||
582 | phydev = fixed_phy_register(PHY_POLL, &fphy_status, -1, NULL); | |
583 | if (!phydev || IS_ERR(phydev)) { | |
584 | dev_err(kdev, "failed to register fixed PHY device\n"); | |
585 | return -ENODEV; | |
586 | } | |
587 | ||
588 | /* Make sure we initialize MoCA PHYs with a link down */ | |
589 | phydev->link = 0; | |
590 | ||
591 | } | |
592 | ||
593 | priv->phydev = phydev; | |
594 | priv->phy_interface = pd->phy_interface; | |
595 | ||
596 | return 0; | |
597 | } | |
598 | ||
599 | static int bcmgenet_mii_bus_init(struct bcmgenet_priv *priv) | |
600 | { | |
601 | struct device_node *dn = priv->pdev->dev.of_node; | |
602 | ||
603 | if (dn) | |
604 | return bcmgenet_mii_of_init(priv); | |
605 | else | |
606 | return bcmgenet_mii_pd_init(priv); | |
607 | } | |
608 | ||
609 | int bcmgenet_mii_init(struct net_device *dev) | |
610 | { | |
611 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
612 | struct device_node *dn = priv->pdev->dev.of_node; | |
613 | int ret; | |
614 | ||
615 | ret = bcmgenet_mii_alloc(priv); | |
616 | if (ret) | |
617 | return ret; | |
618 | ||
619 | ret = bcmgenet_mii_bus_init(priv); | |
620 | if (ret) | |
621 | goto out; | |
622 | ||
623 | return 0; | |
624 | ||
625 | out: | |
626 | if (of_phy_is_fixed_link(dn)) | |
627 | of_phy_deregister_fixed_link(dn); | |
628 | of_node_put(priv->phy_dn); | |
629 | mdiobus_unregister(priv->mii_bus); | |
630 | mdiobus_free(priv->mii_bus); | |
631 | return ret; | |
632 | } | |
633 | ||
634 | void bcmgenet_mii_exit(struct net_device *dev) | |
635 | { | |
636 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
637 | struct device_node *dn = priv->pdev->dev.of_node; | |
638 | ||
639 | if (of_phy_is_fixed_link(dn)) | |
640 | of_phy_deregister_fixed_link(dn); | |
641 | of_node_put(priv->phy_dn); | |
642 | mdiobus_unregister(priv->mii_bus); | |
643 | mdiobus_free(priv->mii_bus); | |
644 | } |