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1 | /* | |
2 | * This file is part of the Chelsio T4 Ethernet driver for Linux. | |
3 | * | |
4 | * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved. | |
5 | * | |
6 | * This software is available to you under a choice of one of two | |
7 | * licenses. You may choose to be licensed under the terms of the GNU | |
8 | * General Public License (GPL) Version 2, available from the file | |
9 | * COPYING in the main directory of this source tree, or the | |
10 | * OpenIB.org BSD license below: | |
11 | * | |
12 | * Redistribution and use in source and binary forms, with or | |
13 | * without modification, are permitted provided that the following | |
14 | * conditions are met: | |
15 | * | |
16 | * - Redistributions of source code must retain the above | |
17 | * copyright notice, this list of conditions and the following | |
18 | * disclaimer. | |
19 | * | |
20 | * - Redistributions in binary form must reproduce the above | |
21 | * copyright notice, this list of conditions and the following | |
22 | * disclaimer in the documentation and/or other materials | |
23 | * provided with the distribution. | |
24 | * | |
25 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
26 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
27 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
28 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
29 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
30 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
31 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
32 | * SOFTWARE. | |
33 | */ | |
34 | ||
35 | #ifndef __CXGB4_H__ | |
36 | #define __CXGB4_H__ | |
37 | ||
38 | #include "t4_hw.h" | |
39 | ||
40 | #include <linux/bitops.h> | |
41 | #include <linux/cache.h> | |
42 | #include <linux/interrupt.h> | |
43 | #include <linux/list.h> | |
44 | #include <linux/netdevice.h> | |
45 | #include <linux/pci.h> | |
46 | #include <linux/spinlock.h> | |
47 | #include <linux/timer.h> | |
48 | #include <linux/vmalloc.h> | |
49 | #include <linux/etherdevice.h> | |
50 | #include <linux/net_tstamp.h> | |
51 | #include <linux/ptp_clock_kernel.h> | |
52 | #include <linux/ptp_classify.h> | |
53 | #include <asm/io.h> | |
54 | #include "t4_chip_type.h" | |
55 | #include "cxgb4_uld.h" | |
56 | ||
57 | #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__) | |
58 | extern struct list_head adapter_list; | |
59 | extern struct mutex uld_mutex; | |
60 | ||
61 | enum { | |
62 | MAX_NPORTS = 4, /* max # of ports */ | |
63 | SERNUM_LEN = 24, /* Serial # length */ | |
64 | EC_LEN = 16, /* E/C length */ | |
65 | ID_LEN = 16, /* ID length */ | |
66 | PN_LEN = 16, /* Part Number length */ | |
67 | MACADDR_LEN = 12, /* MAC Address length */ | |
68 | }; | |
69 | ||
70 | enum { | |
71 | T4_REGMAP_SIZE = (160 * 1024), | |
72 | T5_REGMAP_SIZE = (332 * 1024), | |
73 | }; | |
74 | ||
75 | enum { | |
76 | MEM_EDC0, | |
77 | MEM_EDC1, | |
78 | MEM_MC, | |
79 | MEM_MC0 = MEM_MC, | |
80 | MEM_MC1 | |
81 | }; | |
82 | ||
83 | enum { | |
84 | MEMWIN0_APERTURE = 2048, | |
85 | MEMWIN0_BASE = 0x1b800, | |
86 | MEMWIN1_APERTURE = 32768, | |
87 | MEMWIN1_BASE = 0x28000, | |
88 | MEMWIN1_BASE_T5 = 0x52000, | |
89 | MEMWIN2_APERTURE = 65536, | |
90 | MEMWIN2_BASE = 0x30000, | |
91 | MEMWIN2_APERTURE_T5 = 131072, | |
92 | MEMWIN2_BASE_T5 = 0x60000, | |
93 | }; | |
94 | ||
95 | enum dev_master { | |
96 | MASTER_CANT, | |
97 | MASTER_MAY, | |
98 | MASTER_MUST | |
99 | }; | |
100 | ||
101 | enum dev_state { | |
102 | DEV_STATE_UNINIT, | |
103 | DEV_STATE_INIT, | |
104 | DEV_STATE_ERR | |
105 | }; | |
106 | ||
107 | enum cc_pause { | |
108 | PAUSE_RX = 1 << 0, | |
109 | PAUSE_TX = 1 << 1, | |
110 | PAUSE_AUTONEG = 1 << 2 | |
111 | }; | |
112 | ||
113 | enum cc_fec { | |
114 | FEC_AUTO = 1 << 0, /* IEEE 802.3 "automatic" */ | |
115 | FEC_RS = 1 << 1, /* Reed-Solomon */ | |
116 | FEC_BASER_RS = 1 << 2 /* BaseR/Reed-Solomon */ | |
117 | }; | |
118 | ||
119 | struct port_stats { | |
120 | u64 tx_octets; /* total # of octets in good frames */ | |
121 | u64 tx_frames; /* all good frames */ | |
122 | u64 tx_bcast_frames; /* all broadcast frames */ | |
123 | u64 tx_mcast_frames; /* all multicast frames */ | |
124 | u64 tx_ucast_frames; /* all unicast frames */ | |
125 | u64 tx_error_frames; /* all error frames */ | |
126 | ||
127 | u64 tx_frames_64; /* # of Tx frames in a particular range */ | |
128 | u64 tx_frames_65_127; | |
129 | u64 tx_frames_128_255; | |
130 | u64 tx_frames_256_511; | |
131 | u64 tx_frames_512_1023; | |
132 | u64 tx_frames_1024_1518; | |
133 | u64 tx_frames_1519_max; | |
134 | ||
135 | u64 tx_drop; /* # of dropped Tx frames */ | |
136 | u64 tx_pause; /* # of transmitted pause frames */ | |
137 | u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ | |
138 | u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ | |
139 | u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ | |
140 | u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ | |
141 | u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ | |
142 | u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ | |
143 | u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ | |
144 | u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ | |
145 | ||
146 | u64 rx_octets; /* total # of octets in good frames */ | |
147 | u64 rx_frames; /* all good frames */ | |
148 | u64 rx_bcast_frames; /* all broadcast frames */ | |
149 | u64 rx_mcast_frames; /* all multicast frames */ | |
150 | u64 rx_ucast_frames; /* all unicast frames */ | |
151 | u64 rx_too_long; /* # of frames exceeding MTU */ | |
152 | u64 rx_jabber; /* # of jabber frames */ | |
153 | u64 rx_fcs_err; /* # of received frames with bad FCS */ | |
154 | u64 rx_len_err; /* # of received frames with length error */ | |
155 | u64 rx_symbol_err; /* symbol errors */ | |
156 | u64 rx_runt; /* # of short frames */ | |
157 | ||
158 | u64 rx_frames_64; /* # of Rx frames in a particular range */ | |
159 | u64 rx_frames_65_127; | |
160 | u64 rx_frames_128_255; | |
161 | u64 rx_frames_256_511; | |
162 | u64 rx_frames_512_1023; | |
163 | u64 rx_frames_1024_1518; | |
164 | u64 rx_frames_1519_max; | |
165 | ||
166 | u64 rx_pause; /* # of received pause frames */ | |
167 | u64 rx_ppp0; /* # of received PPP prio 0 frames */ | |
168 | u64 rx_ppp1; /* # of received PPP prio 1 frames */ | |
169 | u64 rx_ppp2; /* # of received PPP prio 2 frames */ | |
170 | u64 rx_ppp3; /* # of received PPP prio 3 frames */ | |
171 | u64 rx_ppp4; /* # of received PPP prio 4 frames */ | |
172 | u64 rx_ppp5; /* # of received PPP prio 5 frames */ | |
173 | u64 rx_ppp6; /* # of received PPP prio 6 frames */ | |
174 | u64 rx_ppp7; /* # of received PPP prio 7 frames */ | |
175 | ||
176 | u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ | |
177 | u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ | |
178 | u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ | |
179 | u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ | |
180 | u64 rx_trunc0; /* buffer-group 0 truncated packets */ | |
181 | u64 rx_trunc1; /* buffer-group 1 truncated packets */ | |
182 | u64 rx_trunc2; /* buffer-group 2 truncated packets */ | |
183 | u64 rx_trunc3; /* buffer-group 3 truncated packets */ | |
184 | }; | |
185 | ||
186 | struct lb_port_stats { | |
187 | u64 octets; | |
188 | u64 frames; | |
189 | u64 bcast_frames; | |
190 | u64 mcast_frames; | |
191 | u64 ucast_frames; | |
192 | u64 error_frames; | |
193 | ||
194 | u64 frames_64; | |
195 | u64 frames_65_127; | |
196 | u64 frames_128_255; | |
197 | u64 frames_256_511; | |
198 | u64 frames_512_1023; | |
199 | u64 frames_1024_1518; | |
200 | u64 frames_1519_max; | |
201 | ||
202 | u64 drop; | |
203 | ||
204 | u64 ovflow0; | |
205 | u64 ovflow1; | |
206 | u64 ovflow2; | |
207 | u64 ovflow3; | |
208 | u64 trunc0; | |
209 | u64 trunc1; | |
210 | u64 trunc2; | |
211 | u64 trunc3; | |
212 | }; | |
213 | ||
214 | struct tp_tcp_stats { | |
215 | u32 tcp_out_rsts; | |
216 | u64 tcp_in_segs; | |
217 | u64 tcp_out_segs; | |
218 | u64 tcp_retrans_segs; | |
219 | }; | |
220 | ||
221 | struct tp_usm_stats { | |
222 | u32 frames; | |
223 | u32 drops; | |
224 | u64 octets; | |
225 | }; | |
226 | ||
227 | struct tp_fcoe_stats { | |
228 | u32 frames_ddp; | |
229 | u32 frames_drop; | |
230 | u64 octets_ddp; | |
231 | }; | |
232 | ||
233 | struct tp_err_stats { | |
234 | u32 mac_in_errs[4]; | |
235 | u32 hdr_in_errs[4]; | |
236 | u32 tcp_in_errs[4]; | |
237 | u32 tnl_cong_drops[4]; | |
238 | u32 ofld_chan_drops[4]; | |
239 | u32 tnl_tx_drops[4]; | |
240 | u32 ofld_vlan_drops[4]; | |
241 | u32 tcp6_in_errs[4]; | |
242 | u32 ofld_no_neigh; | |
243 | u32 ofld_cong_defer; | |
244 | }; | |
245 | ||
246 | struct tp_cpl_stats { | |
247 | u32 req[4]; | |
248 | u32 rsp[4]; | |
249 | }; | |
250 | ||
251 | struct tp_rdma_stats { | |
252 | u32 rqe_dfr_pkt; | |
253 | u32 rqe_dfr_mod; | |
254 | }; | |
255 | ||
256 | struct sge_params { | |
257 | u32 hps; /* host page size for our PF/VF */ | |
258 | u32 eq_qpp; /* egress queues/page for our PF/VF */ | |
259 | u32 iq_qpp; /* egress queues/page for our PF/VF */ | |
260 | }; | |
261 | ||
262 | struct tp_params { | |
263 | unsigned int tre; /* log2 of core clocks per TP tick */ | |
264 | unsigned int la_mask; /* what events are recorded by TP LA */ | |
265 | unsigned short tx_modq_map; /* TX modulation scheduler queue to */ | |
266 | /* channel map */ | |
267 | ||
268 | uint32_t dack_re; /* DACK timer resolution */ | |
269 | unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ | |
270 | ||
271 | u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */ | |
272 | u32 ingress_config; /* cached TP_INGRESS_CONFIG */ | |
273 | ||
274 | /* cached TP_OUT_CONFIG compressed error vector | |
275 | * and passing outer header info for encapsulated packets. | |
276 | */ | |
277 | int rx_pkt_encap; | |
278 | ||
279 | /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a | |
280 | * subset of the set of fields which may be present in the Compressed | |
281 | * Filter Tuple portion of filters and TCP TCB connections. The | |
282 | * fields which are present are controlled by the TP_VLAN_PRI_MAP. | |
283 | * Since a variable number of fields may or may not be present, their | |
284 | * shifted field positions within the Compressed Filter Tuple may | |
285 | * vary, or not even be present if the field isn't selected in | |
286 | * TP_VLAN_PRI_MAP. Since some of these fields are needed in various | |
287 | * places we store their offsets here, or a -1 if the field isn't | |
288 | * present. | |
289 | */ | |
290 | int fcoe_shift; | |
291 | int port_shift; | |
292 | int vnic_shift; | |
293 | int vlan_shift; | |
294 | int tos_shift; | |
295 | int protocol_shift; | |
296 | int ethertype_shift; | |
297 | int macmatch_shift; | |
298 | int matchtype_shift; | |
299 | int frag_shift; | |
300 | ||
301 | u64 hash_filter_mask; | |
302 | }; | |
303 | ||
304 | struct vpd_params { | |
305 | unsigned int cclk; | |
306 | u8 ec[EC_LEN + 1]; | |
307 | u8 sn[SERNUM_LEN + 1]; | |
308 | u8 id[ID_LEN + 1]; | |
309 | u8 pn[PN_LEN + 1]; | |
310 | u8 na[MACADDR_LEN + 1]; | |
311 | }; | |
312 | ||
313 | struct pci_params { | |
314 | unsigned char speed; | |
315 | unsigned char width; | |
316 | }; | |
317 | ||
318 | struct devlog_params { | |
319 | u32 memtype; /* which memory (EDC0, EDC1, MC) */ | |
320 | u32 start; /* start of log in firmware memory */ | |
321 | u32 size; /* size of log */ | |
322 | }; | |
323 | ||
324 | /* Stores chip specific parameters */ | |
325 | struct arch_specific_params { | |
326 | u8 nchan; | |
327 | u8 pm_stats_cnt; | |
328 | u8 cng_ch_bits_log; /* congestion channel map bits width */ | |
329 | u16 mps_rplc_size; | |
330 | u16 vfcount; | |
331 | u32 sge_fl_db; | |
332 | u16 mps_tcam_size; | |
333 | }; | |
334 | ||
335 | struct adapter_params { | |
336 | struct sge_params sge; | |
337 | struct tp_params tp; | |
338 | struct vpd_params vpd; | |
339 | struct pci_params pci; | |
340 | struct devlog_params devlog; | |
341 | enum pcie_memwin drv_memwin; | |
342 | ||
343 | unsigned int cim_la_size; | |
344 | ||
345 | unsigned int sf_size; /* serial flash size in bytes */ | |
346 | unsigned int sf_nsec; /* # of flash sectors */ | |
347 | ||
348 | unsigned int fw_vers; /* firmware version */ | |
349 | unsigned int bs_vers; /* bootstrap version */ | |
350 | unsigned int tp_vers; /* TP microcode version */ | |
351 | unsigned int er_vers; /* expansion ROM version */ | |
352 | unsigned int scfg_vers; /* Serial Configuration version */ | |
353 | unsigned int vpd_vers; /* VPD Version */ | |
354 | u8 api_vers[7]; | |
355 | ||
356 | unsigned short mtus[NMTUS]; | |
357 | unsigned short a_wnd[NCCTRL_WIN]; | |
358 | unsigned short b_wnd[NCCTRL_WIN]; | |
359 | ||
360 | unsigned char nports; /* # of ethernet ports */ | |
361 | unsigned char portvec; | |
362 | enum chip_type chip; /* chip code */ | |
363 | struct arch_specific_params arch; /* chip specific params */ | |
364 | unsigned char offload; | |
365 | unsigned char crypto; /* HW capability for crypto */ | |
366 | ||
367 | unsigned char bypass; | |
368 | unsigned char hash_filter; | |
369 | ||
370 | unsigned int ofldq_wr_cred; | |
371 | bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ | |
372 | ||
373 | unsigned int nsched_cls; /* number of traffic classes */ | |
374 | unsigned int max_ordird_qp; /* Max read depth per RDMA QP */ | |
375 | unsigned int max_ird_adapter; /* Max read depth per adapter */ | |
376 | bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */ | |
377 | u8 fw_caps_support; /* 32-bit Port Capabilities */ | |
378 | bool filter2_wr_support; /* FW support for FILTER2_WR */ | |
379 | ||
380 | /* MPS Buffer Group Map[per Port]. Bit i is set if buffer group i is | |
381 | * used by the Port | |
382 | */ | |
383 | u8 mps_bg_map[MAX_NPORTS]; /* MPS Buffer Group Map */ | |
384 | }; | |
385 | ||
386 | /* State needed to monitor the forward progress of SGE Ingress DMA activities | |
387 | * and possible hangs. | |
388 | */ | |
389 | struct sge_idma_monitor_state { | |
390 | unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */ | |
391 | unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */ | |
392 | unsigned int idma_state[2]; /* IDMA Hang detect state */ | |
393 | unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */ | |
394 | unsigned int idma_warn[2]; /* time to warning in HZ */ | |
395 | }; | |
396 | ||
397 | /* Firmware Mailbox Command/Reply log. All values are in Host-Endian format. | |
398 | * The access and execute times are signed in order to accommodate negative | |
399 | * error returns. | |
400 | */ | |
401 | struct mbox_cmd { | |
402 | u64 cmd[MBOX_LEN / 8]; /* a Firmware Mailbox Command/Reply */ | |
403 | u64 timestamp; /* OS-dependent timestamp */ | |
404 | u32 seqno; /* sequence number */ | |
405 | s16 access; /* time (ms) to access mailbox */ | |
406 | s16 execute; /* time (ms) to execute */ | |
407 | }; | |
408 | ||
409 | struct mbox_cmd_log { | |
410 | unsigned int size; /* number of entries in the log */ | |
411 | unsigned int cursor; /* next position in the log to write */ | |
412 | u32 seqno; /* next sequence number */ | |
413 | /* variable length mailbox command log starts here */ | |
414 | }; | |
415 | ||
416 | /* Given a pointer to a Firmware Mailbox Command Log and a log entry index, | |
417 | * return a pointer to the specified entry. | |
418 | */ | |
419 | static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log, | |
420 | unsigned int entry_idx) | |
421 | { | |
422 | return &((struct mbox_cmd *)&(log)[1])[entry_idx]; | |
423 | } | |
424 | ||
425 | #include "t4fw_api.h" | |
426 | ||
427 | #define FW_VERSION(chip) ( \ | |
428 | FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \ | |
429 | FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \ | |
430 | FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \ | |
431 | FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD)) | |
432 | #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf) | |
433 | ||
434 | struct fw_info { | |
435 | u8 chip; | |
436 | char *fs_name; | |
437 | char *fw_mod_name; | |
438 | struct fw_hdr fw_hdr; | |
439 | }; | |
440 | ||
441 | struct trace_params { | |
442 | u32 data[TRACE_LEN / 4]; | |
443 | u32 mask[TRACE_LEN / 4]; | |
444 | unsigned short snap_len; | |
445 | unsigned short min_len; | |
446 | unsigned char skip_ofst; | |
447 | unsigned char skip_len; | |
448 | unsigned char invert; | |
449 | unsigned char port; | |
450 | }; | |
451 | ||
452 | /* Firmware Port Capabilities types. */ | |
453 | ||
454 | typedef u16 fw_port_cap16_t; /* 16-bit Port Capabilities integral value */ | |
455 | typedef u32 fw_port_cap32_t; /* 32-bit Port Capabilities integral value */ | |
456 | ||
457 | enum fw_caps { | |
458 | FW_CAPS_UNKNOWN = 0, /* 0'ed out initial state */ | |
459 | FW_CAPS16 = 1, /* old Firmware: 16-bit Port Capabilities */ | |
460 | FW_CAPS32 = 2, /* new Firmware: 32-bit Port Capabilities */ | |
461 | }; | |
462 | ||
463 | struct link_config { | |
464 | fw_port_cap32_t pcaps; /* link capabilities */ | |
465 | fw_port_cap32_t def_acaps; /* default advertised capabilities */ | |
466 | fw_port_cap32_t acaps; /* advertised capabilities */ | |
467 | fw_port_cap32_t lpacaps; /* peer advertised capabilities */ | |
468 | ||
469 | fw_port_cap32_t speed_caps; /* speed(s) user has requested */ | |
470 | unsigned int speed; /* actual link speed (Mb/s) */ | |
471 | ||
472 | enum cc_pause requested_fc; /* flow control user has requested */ | |
473 | enum cc_pause fc; /* actual link flow control */ | |
474 | ||
475 | enum cc_fec requested_fec; /* Forward Error Correction: */ | |
476 | enum cc_fec fec; /* requested and actual in use */ | |
477 | ||
478 | unsigned char autoneg; /* autonegotiating? */ | |
479 | ||
480 | unsigned char link_ok; /* link up? */ | |
481 | unsigned char link_down_rc; /* link down reason */ | |
482 | }; | |
483 | ||
484 | #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) | |
485 | ||
486 | enum { | |
487 | MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */ | |
488 | MAX_OFLD_QSETS = 16, /* # of offload Tx, iscsi Rx queue sets */ | |
489 | MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */ | |
490 | }; | |
491 | ||
492 | enum { | |
493 | MAX_TXQ_ENTRIES = 16384, | |
494 | MAX_CTRL_TXQ_ENTRIES = 1024, | |
495 | MAX_RSPQ_ENTRIES = 16384, | |
496 | MAX_RX_BUFFERS = 16384, | |
497 | MIN_TXQ_ENTRIES = 32, | |
498 | MIN_CTRL_TXQ_ENTRIES = 32, | |
499 | MIN_RSPQ_ENTRIES = 128, | |
500 | MIN_FL_ENTRIES = 16 | |
501 | }; | |
502 | ||
503 | enum { | |
504 | INGQ_EXTRAS = 2, /* firmware event queue and */ | |
505 | /* forwarded interrupts */ | |
506 | MAX_INGQ = MAX_ETH_QSETS + INGQ_EXTRAS, | |
507 | }; | |
508 | ||
509 | struct adapter; | |
510 | struct sge_rspq; | |
511 | ||
512 | #include "cxgb4_dcb.h" | |
513 | ||
514 | #ifdef CONFIG_CHELSIO_T4_FCOE | |
515 | #include "cxgb4_fcoe.h" | |
516 | #endif /* CONFIG_CHELSIO_T4_FCOE */ | |
517 | ||
518 | struct port_info { | |
519 | struct adapter *adapter; | |
520 | u16 viid; | |
521 | s16 xact_addr_filt; /* index of exact MAC address filter */ | |
522 | u16 rss_size; /* size of VI's RSS table slice */ | |
523 | s8 mdio_addr; | |
524 | enum fw_port_type port_type; | |
525 | u8 mod_type; | |
526 | u8 port_id; | |
527 | u8 tx_chan; | |
528 | u8 lport; /* associated offload logical port */ | |
529 | u8 nqsets; /* # of qsets */ | |
530 | u8 first_qset; /* index of first qset */ | |
531 | u8 rss_mode; | |
532 | struct link_config link_cfg; | |
533 | u16 *rss; | |
534 | struct port_stats stats_base; | |
535 | #ifdef CONFIG_CHELSIO_T4_DCB | |
536 | struct port_dcb_info dcb; /* Data Center Bridging support */ | |
537 | #endif | |
538 | #ifdef CONFIG_CHELSIO_T4_FCOE | |
539 | struct cxgb_fcoe fcoe; | |
540 | #endif /* CONFIG_CHELSIO_T4_FCOE */ | |
541 | bool rxtstamp; /* Enable TS */ | |
542 | struct hwtstamp_config tstamp_config; | |
543 | bool ptp_enable; | |
544 | struct sched_table *sched_tbl; | |
545 | }; | |
546 | ||
547 | struct dentry; | |
548 | struct work_struct; | |
549 | ||
550 | enum { /* adapter flags */ | |
551 | FULL_INIT_DONE = (1 << 0), | |
552 | DEV_ENABLED = (1 << 1), | |
553 | USING_MSI = (1 << 2), | |
554 | USING_MSIX = (1 << 3), | |
555 | FW_OK = (1 << 4), | |
556 | RSS_TNLALLLOOKUP = (1 << 5), | |
557 | USING_SOFT_PARAMS = (1 << 6), | |
558 | MASTER_PF = (1 << 7), | |
559 | FW_OFLD_CONN = (1 << 9), | |
560 | ROOT_NO_RELAXED_ORDERING = (1 << 10), | |
561 | SHUTTING_DOWN = (1 << 11), | |
562 | }; | |
563 | ||
564 | enum { | |
565 | ULP_CRYPTO_LOOKASIDE = 1 << 0, | |
566 | }; | |
567 | ||
568 | struct rx_sw_desc; | |
569 | ||
570 | struct sge_fl { /* SGE free-buffer queue state */ | |
571 | unsigned int avail; /* # of available Rx buffers */ | |
572 | unsigned int pend_cred; /* new buffers since last FL DB ring */ | |
573 | unsigned int cidx; /* consumer index */ | |
574 | unsigned int pidx; /* producer index */ | |
575 | unsigned long alloc_failed; /* # of times buffer allocation failed */ | |
576 | unsigned long large_alloc_failed; | |
577 | unsigned long mapping_err; /* # of RX Buffer DMA Mapping failures */ | |
578 | unsigned long low; /* # of times momentarily starving */ | |
579 | unsigned long starving; | |
580 | /* RO fields */ | |
581 | unsigned int cntxt_id; /* SGE context id for the free list */ | |
582 | unsigned int size; /* capacity of free list */ | |
583 | struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */ | |
584 | __be64 *desc; /* address of HW Rx descriptor ring */ | |
585 | dma_addr_t addr; /* bus address of HW ring start */ | |
586 | void __iomem *bar2_addr; /* address of BAR2 Queue registers */ | |
587 | unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ | |
588 | }; | |
589 | ||
590 | /* A packet gather list */ | |
591 | struct pkt_gl { | |
592 | u64 sgetstamp; /* SGE Time Stamp for Ingress Packet */ | |
593 | struct page_frag frags[MAX_SKB_FRAGS]; | |
594 | void *va; /* virtual address of first byte */ | |
595 | unsigned int nfrags; /* # of fragments */ | |
596 | unsigned int tot_len; /* total length of fragments */ | |
597 | }; | |
598 | ||
599 | typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp, | |
600 | const struct pkt_gl *gl); | |
601 | typedef void (*rspq_flush_handler_t)(struct sge_rspq *q); | |
602 | /* LRO related declarations for ULD */ | |
603 | struct t4_lro_mgr { | |
604 | #define MAX_LRO_SESSIONS 64 | |
605 | u8 lro_session_cnt; /* # of sessions to aggregate */ | |
606 | unsigned long lro_pkts; /* # of LRO super packets */ | |
607 | unsigned long lro_merged; /* # of wire packets merged by LRO */ | |
608 | struct sk_buff_head lroq; /* list of aggregated sessions */ | |
609 | }; | |
610 | ||
611 | struct sge_rspq { /* state for an SGE response queue */ | |
612 | struct napi_struct napi; | |
613 | const __be64 *cur_desc; /* current descriptor in queue */ | |
614 | unsigned int cidx; /* consumer index */ | |
615 | u8 gen; /* current generation bit */ | |
616 | u8 intr_params; /* interrupt holdoff parameters */ | |
617 | u8 next_intr_params; /* holdoff params for next interrupt */ | |
618 | u8 adaptive_rx; | |
619 | u8 pktcnt_idx; /* interrupt packet threshold */ | |
620 | u8 uld; /* ULD handling this queue */ | |
621 | u8 idx; /* queue index within its group */ | |
622 | int offset; /* offset into current Rx buffer */ | |
623 | u16 cntxt_id; /* SGE context id for the response q */ | |
624 | u16 abs_id; /* absolute SGE id for the response q */ | |
625 | __be64 *desc; /* address of HW response ring */ | |
626 | dma_addr_t phys_addr; /* physical address of the ring */ | |
627 | void __iomem *bar2_addr; /* address of BAR2 Queue registers */ | |
628 | unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ | |
629 | unsigned int iqe_len; /* entry size */ | |
630 | unsigned int size; /* capacity of response queue */ | |
631 | struct adapter *adap; | |
632 | struct net_device *netdev; /* associated net device */ | |
633 | rspq_handler_t handler; | |
634 | rspq_flush_handler_t flush_handler; | |
635 | struct t4_lro_mgr lro_mgr; | |
636 | }; | |
637 | ||
638 | struct sge_eth_stats { /* Ethernet queue statistics */ | |
639 | unsigned long pkts; /* # of ethernet packets */ | |
640 | unsigned long lro_pkts; /* # of LRO super packets */ | |
641 | unsigned long lro_merged; /* # of wire packets merged by LRO */ | |
642 | unsigned long rx_cso; /* # of Rx checksum offloads */ | |
643 | unsigned long vlan_ex; /* # of Rx VLAN extractions */ | |
644 | unsigned long rx_drops; /* # of packets dropped due to no mem */ | |
645 | }; | |
646 | ||
647 | struct sge_eth_rxq { /* SW Ethernet Rx queue */ | |
648 | struct sge_rspq rspq; | |
649 | struct sge_fl fl; | |
650 | struct sge_eth_stats stats; | |
651 | } ____cacheline_aligned_in_smp; | |
652 | ||
653 | struct sge_ofld_stats { /* offload queue statistics */ | |
654 | unsigned long pkts; /* # of packets */ | |
655 | unsigned long imm; /* # of immediate-data packets */ | |
656 | unsigned long an; /* # of asynchronous notifications */ | |
657 | unsigned long nomem; /* # of responses deferred due to no mem */ | |
658 | }; | |
659 | ||
660 | struct sge_ofld_rxq { /* SW offload Rx queue */ | |
661 | struct sge_rspq rspq; | |
662 | struct sge_fl fl; | |
663 | struct sge_ofld_stats stats; | |
664 | } ____cacheline_aligned_in_smp; | |
665 | ||
666 | struct tx_desc { | |
667 | __be64 flit[8]; | |
668 | }; | |
669 | ||
670 | struct tx_sw_desc; | |
671 | ||
672 | struct sge_txq { | |
673 | unsigned int in_use; /* # of in-use Tx descriptors */ | |
674 | unsigned int q_type; /* Q type Eth/Ctrl/Ofld */ | |
675 | unsigned int size; /* # of descriptors */ | |
676 | unsigned int cidx; /* SW consumer index */ | |
677 | unsigned int pidx; /* producer index */ | |
678 | unsigned long stops; /* # of times q has been stopped */ | |
679 | unsigned long restarts; /* # of queue restarts */ | |
680 | unsigned int cntxt_id; /* SGE context id for the Tx q */ | |
681 | struct tx_desc *desc; /* address of HW Tx descriptor ring */ | |
682 | struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */ | |
683 | struct sge_qstat *stat; /* queue status entry */ | |
684 | dma_addr_t phys_addr; /* physical address of the ring */ | |
685 | spinlock_t db_lock; | |
686 | int db_disabled; | |
687 | unsigned short db_pidx; | |
688 | unsigned short db_pidx_inc; | |
689 | void __iomem *bar2_addr; /* address of BAR2 Queue registers */ | |
690 | unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ | |
691 | }; | |
692 | ||
693 | struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */ | |
694 | struct sge_txq q; | |
695 | struct netdev_queue *txq; /* associated netdev TX queue */ | |
696 | #ifdef CONFIG_CHELSIO_T4_DCB | |
697 | u8 dcb_prio; /* DCB Priority bound to queue */ | |
698 | #endif | |
699 | unsigned long tso; /* # of TSO requests */ | |
700 | unsigned long tx_cso; /* # of Tx checksum offloads */ | |
701 | unsigned long vlan_ins; /* # of Tx VLAN insertions */ | |
702 | unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ | |
703 | } ____cacheline_aligned_in_smp; | |
704 | ||
705 | struct sge_uld_txq { /* state for an SGE offload Tx queue */ | |
706 | struct sge_txq q; | |
707 | struct adapter *adap; | |
708 | struct sk_buff_head sendq; /* list of backpressured packets */ | |
709 | struct tasklet_struct qresume_tsk; /* restarts the queue */ | |
710 | bool service_ofldq_running; /* service_ofldq() is processing sendq */ | |
711 | u8 full; /* the Tx ring is full */ | |
712 | unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ | |
713 | } ____cacheline_aligned_in_smp; | |
714 | ||
715 | struct sge_ctrl_txq { /* state for an SGE control Tx queue */ | |
716 | struct sge_txq q; | |
717 | struct adapter *adap; | |
718 | struct sk_buff_head sendq; /* list of backpressured packets */ | |
719 | struct tasklet_struct qresume_tsk; /* restarts the queue */ | |
720 | u8 full; /* the Tx ring is full */ | |
721 | } ____cacheline_aligned_in_smp; | |
722 | ||
723 | struct sge_uld_rxq_info { | |
724 | char name[IFNAMSIZ]; /* name of ULD driver */ | |
725 | struct sge_ofld_rxq *uldrxq; /* Rxq's for ULD */ | |
726 | u16 *msix_tbl; /* msix_tbl for uld */ | |
727 | u16 *rspq_id; /* response queue id's of rxq */ | |
728 | u16 nrxq; /* # of ingress uld queues */ | |
729 | u16 nciq; /* # of completion queues */ | |
730 | u8 uld; /* uld type */ | |
731 | }; | |
732 | ||
733 | struct sge_uld_txq_info { | |
734 | struct sge_uld_txq *uldtxq; /* Txq's for ULD */ | |
735 | atomic_t users; /* num users */ | |
736 | u16 ntxq; /* # of egress uld queues */ | |
737 | }; | |
738 | ||
739 | struct sge { | |
740 | struct sge_eth_txq ethtxq[MAX_ETH_QSETS]; | |
741 | struct sge_eth_txq ptptxq; | |
742 | struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES]; | |
743 | ||
744 | struct sge_eth_rxq ethrxq[MAX_ETH_QSETS]; | |
745 | struct sge_rspq fw_evtq ____cacheline_aligned_in_smp; | |
746 | struct sge_uld_rxq_info **uld_rxq_info; | |
747 | struct sge_uld_txq_info **uld_txq_info; | |
748 | ||
749 | struct sge_rspq intrq ____cacheline_aligned_in_smp; | |
750 | spinlock_t intrq_lock; | |
751 | ||
752 | u16 max_ethqsets; /* # of available Ethernet queue sets */ | |
753 | u16 ethqsets; /* # of active Ethernet queue sets */ | |
754 | u16 ethtxq_rover; /* Tx queue to clean up next */ | |
755 | u16 ofldqsets; /* # of active ofld queue sets */ | |
756 | u16 nqs_per_uld; /* # of Rx queues per ULD */ | |
757 | u16 timer_val[SGE_NTIMERS]; | |
758 | u8 counter_val[SGE_NCOUNTERS]; | |
759 | u32 fl_pg_order; /* large page allocation size */ | |
760 | u32 stat_len; /* length of status page at ring end */ | |
761 | u32 pktshift; /* padding between CPL & packet data */ | |
762 | u32 fl_align; /* response queue message alignment */ | |
763 | u32 fl_starve_thres; /* Free List starvation threshold */ | |
764 | ||
765 | struct sge_idma_monitor_state idma_monitor; | |
766 | unsigned int egr_start; | |
767 | unsigned int egr_sz; | |
768 | unsigned int ingr_start; | |
769 | unsigned int ingr_sz; | |
770 | void **egr_map; /* qid->queue egress queue map */ | |
771 | struct sge_rspq **ingr_map; /* qid->queue ingress queue map */ | |
772 | unsigned long *starving_fl; | |
773 | unsigned long *txq_maperr; | |
774 | unsigned long *blocked_fl; | |
775 | struct timer_list rx_timer; /* refills starving FLs */ | |
776 | struct timer_list tx_timer; /* checks Tx queues */ | |
777 | }; | |
778 | ||
779 | #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++) | |
780 | #define for_each_ofldtxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++) | |
781 | ||
782 | struct l2t_data; | |
783 | ||
784 | #ifdef CONFIG_PCI_IOV | |
785 | ||
786 | /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial | |
787 | * Configuration initialization for T5 only has SR-IOV functionality enabled | |
788 | * on PF0-3 in order to simplify everything. | |
789 | */ | |
790 | #define NUM_OF_PF_WITH_SRIOV 4 | |
791 | ||
792 | #endif | |
793 | ||
794 | struct doorbell_stats { | |
795 | u32 db_drop; | |
796 | u32 db_empty; | |
797 | u32 db_full; | |
798 | }; | |
799 | ||
800 | struct hash_mac_addr { | |
801 | struct list_head list; | |
802 | u8 addr[ETH_ALEN]; | |
803 | }; | |
804 | ||
805 | struct uld_msix_bmap { | |
806 | unsigned long *msix_bmap; | |
807 | unsigned int mapsize; | |
808 | spinlock_t lock; /* lock for acquiring bitmap */ | |
809 | }; | |
810 | ||
811 | struct uld_msix_info { | |
812 | unsigned short vec; | |
813 | char desc[IFNAMSIZ + 10]; | |
814 | unsigned int idx; | |
815 | }; | |
816 | ||
817 | struct vf_info { | |
818 | unsigned char vf_mac_addr[ETH_ALEN]; | |
819 | unsigned int tx_rate; | |
820 | bool pf_set_mac; | |
821 | }; | |
822 | ||
823 | struct mbox_list { | |
824 | struct list_head list; | |
825 | }; | |
826 | ||
827 | struct adapter { | |
828 | void __iomem *regs; | |
829 | void __iomem *bar2; | |
830 | u32 t4_bar0; | |
831 | struct pci_dev *pdev; | |
832 | struct device *pdev_dev; | |
833 | const char *name; | |
834 | unsigned int mbox; | |
835 | unsigned int pf; | |
836 | unsigned int flags; | |
837 | unsigned int adap_idx; | |
838 | enum chip_type chip; | |
839 | ||
840 | int msg_enable; | |
841 | ||
842 | struct adapter_params params; | |
843 | struct cxgb4_virt_res vres; | |
844 | unsigned int swintr; | |
845 | ||
846 | struct { | |
847 | unsigned short vec; | |
848 | char desc[IFNAMSIZ + 10]; | |
849 | } msix_info[MAX_INGQ + 1]; | |
850 | struct uld_msix_info *msix_info_ulds; /* msix info for uld's */ | |
851 | struct uld_msix_bmap msix_bmap_ulds; /* msix bitmap for all uld */ | |
852 | int msi_idx; | |
853 | ||
854 | struct doorbell_stats db_stats; | |
855 | struct sge sge; | |
856 | ||
857 | struct net_device *port[MAX_NPORTS]; | |
858 | u8 chan_map[NCHAN]; /* channel -> port map */ | |
859 | ||
860 | struct vf_info *vfinfo; | |
861 | u8 num_vfs; | |
862 | ||
863 | u32 filter_mode; | |
864 | unsigned int l2t_start; | |
865 | unsigned int l2t_end; | |
866 | struct l2t_data *l2t; | |
867 | unsigned int clipt_start; | |
868 | unsigned int clipt_end; | |
869 | struct clip_tbl *clipt; | |
870 | struct smt_data *smt; | |
871 | struct cxgb4_uld_info *uld; | |
872 | void *uld_handle[CXGB4_ULD_MAX]; | |
873 | unsigned int num_uld; | |
874 | unsigned int num_ofld_uld; | |
875 | struct list_head list_node; | |
876 | struct list_head rcu_node; | |
877 | struct list_head mac_hlist; /* list of MAC addresses in MPS Hash */ | |
878 | ||
879 | void *iscsi_ppm; | |
880 | ||
881 | struct tid_info tids; | |
882 | void **tid_release_head; | |
883 | spinlock_t tid_release_lock; | |
884 | struct workqueue_struct *workq; | |
885 | struct work_struct tid_release_task; | |
886 | struct work_struct db_full_task; | |
887 | struct work_struct db_drop_task; | |
888 | bool tid_release_task_busy; | |
889 | ||
890 | /* lock for mailbox cmd list */ | |
891 | spinlock_t mbox_lock; | |
892 | struct mbox_list mlist; | |
893 | ||
894 | /* support for mailbox command/reply logging */ | |
895 | #define T4_OS_LOG_MBOX_CMDS 256 | |
896 | struct mbox_cmd_log *mbox_log; | |
897 | ||
898 | struct mutex uld_mutex; | |
899 | ||
900 | struct dentry *debugfs_root; | |
901 | bool use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */ | |
902 | bool trace_rss; /* 1 implies that different RSS flit per filter is | |
903 | * used per filter else if 0 default RSS flit is | |
904 | * used for all 4 filters. | |
905 | */ | |
906 | ||
907 | struct ptp_clock *ptp_clock; | |
908 | struct ptp_clock_info ptp_clock_info; | |
909 | struct sk_buff *ptp_tx_skb; | |
910 | /* ptp lock */ | |
911 | spinlock_t ptp_lock; | |
912 | spinlock_t stats_lock; | |
913 | spinlock_t win0_lock ____cacheline_aligned_in_smp; | |
914 | ||
915 | /* TC u32 offload */ | |
916 | struct cxgb4_tc_u32_table *tc_u32; | |
917 | struct chcr_stats_debug chcr_stats; | |
918 | ||
919 | /* TC flower offload */ | |
920 | struct rhashtable flower_tbl; | |
921 | struct rhashtable_params flower_ht_params; | |
922 | struct timer_list flower_stats_timer; | |
923 | struct work_struct flower_stats_work; | |
924 | ||
925 | /* Ethtool Dump */ | |
926 | struct ethtool_dump eth_dump; | |
927 | }; | |
928 | ||
929 | /* Support for "sched-class" command to allow a TX Scheduling Class to be | |
930 | * programmed with various parameters. | |
931 | */ | |
932 | struct ch_sched_params { | |
933 | s8 type; /* packet or flow */ | |
934 | union { | |
935 | struct { | |
936 | s8 level; /* scheduler hierarchy level */ | |
937 | s8 mode; /* per-class or per-flow */ | |
938 | s8 rateunit; /* bit or packet rate */ | |
939 | s8 ratemode; /* %port relative or kbps absolute */ | |
940 | s8 channel; /* scheduler channel [0..N] */ | |
941 | s8 class; /* scheduler class [0..N] */ | |
942 | s32 minrate; /* minimum rate */ | |
943 | s32 maxrate; /* maximum rate */ | |
944 | s16 weight; /* percent weight */ | |
945 | s16 pktsize; /* average packet size */ | |
946 | } params; | |
947 | } u; | |
948 | }; | |
949 | ||
950 | enum { | |
951 | SCHED_CLASS_TYPE_PACKET = 0, /* class type */ | |
952 | }; | |
953 | ||
954 | enum { | |
955 | SCHED_CLASS_LEVEL_CL_RL = 0, /* class rate limiter */ | |
956 | }; | |
957 | ||
958 | enum { | |
959 | SCHED_CLASS_MODE_CLASS = 0, /* per-class scheduling */ | |
960 | }; | |
961 | ||
962 | enum { | |
963 | SCHED_CLASS_RATEUNIT_BITS = 0, /* bit rate scheduling */ | |
964 | }; | |
965 | ||
966 | enum { | |
967 | SCHED_CLASS_RATEMODE_ABS = 1, /* Kb/s */ | |
968 | }; | |
969 | ||
970 | /* Support for "sched_queue" command to allow one or more NIC TX Queues | |
971 | * to be bound to a TX Scheduling Class. | |
972 | */ | |
973 | struct ch_sched_queue { | |
974 | s8 queue; /* queue index */ | |
975 | s8 class; /* class index */ | |
976 | }; | |
977 | ||
978 | /* Defined bit width of user definable filter tuples | |
979 | */ | |
980 | #define ETHTYPE_BITWIDTH 16 | |
981 | #define FRAG_BITWIDTH 1 | |
982 | #define MACIDX_BITWIDTH 9 | |
983 | #define FCOE_BITWIDTH 1 | |
984 | #define IPORT_BITWIDTH 3 | |
985 | #define MATCHTYPE_BITWIDTH 3 | |
986 | #define PROTO_BITWIDTH 8 | |
987 | #define TOS_BITWIDTH 8 | |
988 | #define PF_BITWIDTH 8 | |
989 | #define VF_BITWIDTH 8 | |
990 | #define IVLAN_BITWIDTH 16 | |
991 | #define OVLAN_BITWIDTH 16 | |
992 | ||
993 | /* Filter matching rules. These consist of a set of ingress packet field | |
994 | * (value, mask) tuples. The associated ingress packet field matches the | |
995 | * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field | |
996 | * rule can be constructed by specifying a tuple of (0, 0).) A filter rule | |
997 | * matches an ingress packet when all of the individual individual field | |
998 | * matching rules are true. | |
999 | * | |
1000 | * Partial field masks are always valid, however, while it may be easy to | |
1001 | * understand their meanings for some fields (e.g. IP address to match a | |
1002 | * subnet), for others making sensible partial masks is less intuitive (e.g. | |
1003 | * MPS match type) ... | |
1004 | * | |
1005 | * Most of the following data structures are modeled on T4 capabilities. | |
1006 | * Drivers for earlier chips use the subsets which make sense for those chips. | |
1007 | * We really need to come up with a hardware-independent mechanism to | |
1008 | * represent hardware filter capabilities ... | |
1009 | */ | |
1010 | struct ch_filter_tuple { | |
1011 | /* Compressed header matching field rules. The TP_VLAN_PRI_MAP | |
1012 | * register selects which of these fields will participate in the | |
1013 | * filter match rules -- up to a maximum of 36 bits. Because | |
1014 | * TP_VLAN_PRI_MAP is a global register, all filters must use the same | |
1015 | * set of fields. | |
1016 | */ | |
1017 | uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */ | |
1018 | uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */ | |
1019 | uint32_t ivlan_vld:1; /* inner VLAN valid */ | |
1020 | uint32_t ovlan_vld:1; /* outer VLAN valid */ | |
1021 | uint32_t pfvf_vld:1; /* PF/VF valid */ | |
1022 | uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */ | |
1023 | uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */ | |
1024 | uint32_t iport:IPORT_BITWIDTH; /* ingress port */ | |
1025 | uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */ | |
1026 | uint32_t proto:PROTO_BITWIDTH; /* protocol type */ | |
1027 | uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */ | |
1028 | uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */ | |
1029 | uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */ | |
1030 | uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */ | |
1031 | uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */ | |
1032 | ||
1033 | /* Uncompressed header matching field rules. These are always | |
1034 | * available for field rules. | |
1035 | */ | |
1036 | uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */ | |
1037 | uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */ | |
1038 | uint16_t lport; /* local port */ | |
1039 | uint16_t fport; /* foreign port */ | |
1040 | }; | |
1041 | ||
1042 | /* A filter ioctl command. | |
1043 | */ | |
1044 | struct ch_filter_specification { | |
1045 | /* Administrative fields for filter. | |
1046 | */ | |
1047 | uint32_t hitcnts:1; /* count filter hits in TCB */ | |
1048 | uint32_t prio:1; /* filter has priority over active/server */ | |
1049 | ||
1050 | /* Fundamental filter typing. This is the one element of filter | |
1051 | * matching that doesn't exist as a (value, mask) tuple. | |
1052 | */ | |
1053 | uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ | |
1054 | u32 hash:1; /* 0 => wild-card, 1 => exact-match */ | |
1055 | ||
1056 | /* Packet dispatch information. Ingress packets which match the | |
1057 | * filter rules will be dropped, passed to the host or switched back | |
1058 | * out as egress packets. | |
1059 | */ | |
1060 | uint32_t action:2; /* drop, pass, switch */ | |
1061 | ||
1062 | uint32_t rpttid:1; /* report TID in RSS hash field */ | |
1063 | ||
1064 | uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ | |
1065 | uint32_t iq:10; /* ingress queue */ | |
1066 | ||
1067 | uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ | |
1068 | uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ | |
1069 | /* 1 => TCB contains IQ ID */ | |
1070 | ||
1071 | /* Switch proxy/rewrite fields. An ingress packet which matches a | |
1072 | * filter with "switch" set will be looped back out as an egress | |
1073 | * packet -- potentially with some Ethernet header rewriting. | |
1074 | */ | |
1075 | uint32_t eport:2; /* egress port to switch packet out */ | |
1076 | uint32_t newdmac:1; /* rewrite destination MAC address */ | |
1077 | uint32_t newsmac:1; /* rewrite source MAC address */ | |
1078 | uint32_t newvlan:2; /* rewrite VLAN Tag */ | |
1079 | uint32_t nat_mode:3; /* specify NAT operation mode */ | |
1080 | uint8_t dmac[ETH_ALEN]; /* new destination MAC address */ | |
1081 | uint8_t smac[ETH_ALEN]; /* new source MAC address */ | |
1082 | uint16_t vlan; /* VLAN Tag to insert */ | |
1083 | ||
1084 | u8 nat_lip[16]; /* local IP to use after NAT'ing */ | |
1085 | u8 nat_fip[16]; /* foreign IP to use after NAT'ing */ | |
1086 | u16 nat_lport; /* local port to use after NAT'ing */ | |
1087 | u16 nat_fport; /* foreign port to use after NAT'ing */ | |
1088 | ||
1089 | /* reservation for future additions */ | |
1090 | u8 rsvd[24]; | |
1091 | ||
1092 | /* Filter rule value/mask pairs. | |
1093 | */ | |
1094 | struct ch_filter_tuple val; | |
1095 | struct ch_filter_tuple mask; | |
1096 | }; | |
1097 | ||
1098 | enum { | |
1099 | FILTER_PASS = 0, /* default */ | |
1100 | FILTER_DROP, | |
1101 | FILTER_SWITCH | |
1102 | }; | |
1103 | ||
1104 | enum { | |
1105 | VLAN_NOCHANGE = 0, /* default */ | |
1106 | VLAN_REMOVE, | |
1107 | VLAN_INSERT, | |
1108 | VLAN_REWRITE | |
1109 | }; | |
1110 | ||
1111 | enum { | |
1112 | NAT_MODE_NONE = 0, /* No NAT performed */ | |
1113 | NAT_MODE_DIP, /* NAT on Dst IP */ | |
1114 | NAT_MODE_DIP_DP, /* NAT on Dst IP, Dst Port */ | |
1115 | NAT_MODE_DIP_DP_SIP, /* NAT on Dst IP, Dst Port and Src IP */ | |
1116 | NAT_MODE_DIP_DP_SP, /* NAT on Dst IP, Dst Port and Src Port */ | |
1117 | NAT_MODE_SIP_SP, /* NAT on Src IP and Src Port */ | |
1118 | NAT_MODE_DIP_SIP_SP, /* NAT on Dst IP, Src IP and Src Port */ | |
1119 | NAT_MODE_ALL /* NAT on entire 4-tuple */ | |
1120 | }; | |
1121 | ||
1122 | /* Host shadow copy of ingress filter entry. This is in host native format | |
1123 | * and doesn't match the ordering or bit order, etc. of the hardware of the | |
1124 | * firmware command. The use of bit-field structure elements is purely to | |
1125 | * remind ourselves of the field size limitations and save memory in the case | |
1126 | * where the filter table is large. | |
1127 | */ | |
1128 | struct filter_entry { | |
1129 | /* Administrative fields for filter. */ | |
1130 | u32 valid:1; /* filter allocated and valid */ | |
1131 | u32 locked:1; /* filter is administratively locked */ | |
1132 | ||
1133 | u32 pending:1; /* filter action is pending firmware reply */ | |
1134 | struct filter_ctx *ctx; /* Caller's completion hook */ | |
1135 | struct l2t_entry *l2t; /* Layer Two Table entry for dmac */ | |
1136 | struct smt_entry *smt; /* Source Mac Table entry for smac */ | |
1137 | struct net_device *dev; /* Associated net device */ | |
1138 | u32 tid; /* This will store the actual tid */ | |
1139 | ||
1140 | /* The filter itself. Most of this is a straight copy of information | |
1141 | * provided by the extended ioctl(). Some fields are translated to | |
1142 | * internal forms -- for instance the Ingress Queue ID passed in from | |
1143 | * the ioctl() is translated into the Absolute Ingress Queue ID. | |
1144 | */ | |
1145 | struct ch_filter_specification fs; | |
1146 | }; | |
1147 | ||
1148 | static inline int is_offload(const struct adapter *adap) | |
1149 | { | |
1150 | return adap->params.offload; | |
1151 | } | |
1152 | ||
1153 | static inline int is_hashfilter(const struct adapter *adap) | |
1154 | { | |
1155 | return adap->params.hash_filter; | |
1156 | } | |
1157 | ||
1158 | static inline int is_pci_uld(const struct adapter *adap) | |
1159 | { | |
1160 | return adap->params.crypto; | |
1161 | } | |
1162 | ||
1163 | static inline int is_uld(const struct adapter *adap) | |
1164 | { | |
1165 | return (adap->params.offload || adap->params.crypto); | |
1166 | } | |
1167 | ||
1168 | static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr) | |
1169 | { | |
1170 | return readl(adap->regs + reg_addr); | |
1171 | } | |
1172 | ||
1173 | static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val) | |
1174 | { | |
1175 | writel(val, adap->regs + reg_addr); | |
1176 | } | |
1177 | ||
1178 | #ifndef readq | |
1179 | static inline u64 readq(const volatile void __iomem *addr) | |
1180 | { | |
1181 | return readl(addr) + ((u64)readl(addr + 4) << 32); | |
1182 | } | |
1183 | ||
1184 | static inline void writeq(u64 val, volatile void __iomem *addr) | |
1185 | { | |
1186 | writel(val, addr); | |
1187 | writel(val >> 32, addr + 4); | |
1188 | } | |
1189 | #endif | |
1190 | ||
1191 | static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr) | |
1192 | { | |
1193 | return readq(adap->regs + reg_addr); | |
1194 | } | |
1195 | ||
1196 | static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val) | |
1197 | { | |
1198 | writeq(val, adap->regs + reg_addr); | |
1199 | } | |
1200 | ||
1201 | /** | |
1202 | * t4_set_hw_addr - store a port's MAC address in SW | |
1203 | * @adapter: the adapter | |
1204 | * @port_idx: the port index | |
1205 | * @hw_addr: the Ethernet address | |
1206 | * | |
1207 | * Store the Ethernet address of the given port in SW. Called by the common | |
1208 | * code when it retrieves a port's Ethernet address from EEPROM. | |
1209 | */ | |
1210 | static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx, | |
1211 | u8 hw_addr[]) | |
1212 | { | |
1213 | ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr); | |
1214 | ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr); | |
1215 | } | |
1216 | ||
1217 | /** | |
1218 | * netdev2pinfo - return the port_info structure associated with a net_device | |
1219 | * @dev: the netdev | |
1220 | * | |
1221 | * Return the struct port_info associated with a net_device | |
1222 | */ | |
1223 | static inline struct port_info *netdev2pinfo(const struct net_device *dev) | |
1224 | { | |
1225 | return netdev_priv(dev); | |
1226 | } | |
1227 | ||
1228 | /** | |
1229 | * adap2pinfo - return the port_info of a port | |
1230 | * @adap: the adapter | |
1231 | * @idx: the port index | |
1232 | * | |
1233 | * Return the port_info structure for the port of the given index. | |
1234 | */ | |
1235 | static inline struct port_info *adap2pinfo(struct adapter *adap, int idx) | |
1236 | { | |
1237 | return netdev_priv(adap->port[idx]); | |
1238 | } | |
1239 | ||
1240 | /** | |
1241 | * netdev2adap - return the adapter structure associated with a net_device | |
1242 | * @dev: the netdev | |
1243 | * | |
1244 | * Return the struct adapter associated with a net_device | |
1245 | */ | |
1246 | static inline struct adapter *netdev2adap(const struct net_device *dev) | |
1247 | { | |
1248 | return netdev2pinfo(dev)->adapter; | |
1249 | } | |
1250 | ||
1251 | /* Return a version number to identify the type of adapter. The scheme is: | |
1252 | * - bits 0..9: chip version | |
1253 | * - bits 10..15: chip revision | |
1254 | * - bits 16..23: register dump version | |
1255 | */ | |
1256 | static inline unsigned int mk_adap_vers(struct adapter *ap) | |
1257 | { | |
1258 | return CHELSIO_CHIP_VERSION(ap->params.chip) | | |
1259 | (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16); | |
1260 | } | |
1261 | ||
1262 | /* Return a queue's interrupt hold-off time in us. 0 means no timer. */ | |
1263 | static inline unsigned int qtimer_val(const struct adapter *adap, | |
1264 | const struct sge_rspq *q) | |
1265 | { | |
1266 | unsigned int idx = q->intr_params >> 1; | |
1267 | ||
1268 | return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0; | |
1269 | } | |
1270 | ||
1271 | /* driver version & name used for ethtool_drvinfo */ | |
1272 | extern char cxgb4_driver_name[]; | |
1273 | extern const char cxgb4_driver_version[]; | |
1274 | ||
1275 | void t4_os_portmod_changed(const struct adapter *adap, int port_id); | |
1276 | void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat); | |
1277 | ||
1278 | void t4_free_sge_resources(struct adapter *adap); | |
1279 | void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q); | |
1280 | irq_handler_t t4_intr_handler(struct adapter *adap); | |
1281 | netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev); | |
1282 | int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, | |
1283 | const struct pkt_gl *gl); | |
1284 | int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb); | |
1285 | int t4_ofld_send(struct adapter *adap, struct sk_buff *skb); | |
1286 | int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, | |
1287 | struct net_device *dev, int intr_idx, | |
1288 | struct sge_fl *fl, rspq_handler_t hnd, | |
1289 | rspq_flush_handler_t flush_handler, int cong); | |
1290 | int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, | |
1291 | struct net_device *dev, struct netdev_queue *netdevq, | |
1292 | unsigned int iqid); | |
1293 | int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, | |
1294 | struct net_device *dev, unsigned int iqid, | |
1295 | unsigned int cmplqid); | |
1296 | int t4_sge_mod_ctrl_txq(struct adapter *adap, unsigned int eqid, | |
1297 | unsigned int cmplqid); | |
1298 | int t4_sge_alloc_uld_txq(struct adapter *adap, struct sge_uld_txq *txq, | |
1299 | struct net_device *dev, unsigned int iqid, | |
1300 | unsigned int uld_type); | |
1301 | irqreturn_t t4_sge_intr_msix(int irq, void *cookie); | |
1302 | int t4_sge_init(struct adapter *adap); | |
1303 | void t4_sge_start(struct adapter *adap); | |
1304 | void t4_sge_stop(struct adapter *adap); | |
1305 | void cxgb4_set_ethtool_ops(struct net_device *netdev); | |
1306 | int cxgb4_write_rss(const struct port_info *pi, const u16 *queues); | |
1307 | extern int dbfifo_int_thresh; | |
1308 | ||
1309 | #define for_each_port(adapter, iter) \ | |
1310 | for (iter = 0; iter < (adapter)->params.nports; ++iter) | |
1311 | ||
1312 | static inline int is_bypass(struct adapter *adap) | |
1313 | { | |
1314 | return adap->params.bypass; | |
1315 | } | |
1316 | ||
1317 | static inline int is_bypass_device(int device) | |
1318 | { | |
1319 | /* this should be set based upon device capabilities */ | |
1320 | switch (device) { | |
1321 | case 0x440b: | |
1322 | case 0x440c: | |
1323 | return 1; | |
1324 | default: | |
1325 | return 0; | |
1326 | } | |
1327 | } | |
1328 | ||
1329 | static inline int is_10gbt_device(int device) | |
1330 | { | |
1331 | /* this should be set based upon device capabilities */ | |
1332 | switch (device) { | |
1333 | case 0x4409: | |
1334 | case 0x4486: | |
1335 | return 1; | |
1336 | ||
1337 | default: | |
1338 | return 0; | |
1339 | } | |
1340 | } | |
1341 | ||
1342 | static inline unsigned int core_ticks_per_usec(const struct adapter *adap) | |
1343 | { | |
1344 | return adap->params.vpd.cclk / 1000; | |
1345 | } | |
1346 | ||
1347 | static inline unsigned int us_to_core_ticks(const struct adapter *adap, | |
1348 | unsigned int us) | |
1349 | { | |
1350 | return (us * adap->params.vpd.cclk) / 1000; | |
1351 | } | |
1352 | ||
1353 | static inline unsigned int core_ticks_to_us(const struct adapter *adapter, | |
1354 | unsigned int ticks) | |
1355 | { | |
1356 | /* add Core Clock / 2 to round ticks to nearest uS */ | |
1357 | return ((ticks * 1000 + adapter->params.vpd.cclk/2) / | |
1358 | adapter->params.vpd.cclk); | |
1359 | } | |
1360 | ||
1361 | static inline unsigned int dack_ticks_to_usec(const struct adapter *adap, | |
1362 | unsigned int ticks) | |
1363 | { | |
1364 | return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap); | |
1365 | } | |
1366 | ||
1367 | void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, | |
1368 | u32 val); | |
1369 | ||
1370 | int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, | |
1371 | int size, void *rpl, bool sleep_ok, int timeout); | |
1372 | int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, | |
1373 | void *rpl, bool sleep_ok); | |
1374 | ||
1375 | static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox, | |
1376 | const void *cmd, int size, void *rpl, | |
1377 | int timeout) | |
1378 | { | |
1379 | return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true, | |
1380 | timeout); | |
1381 | } | |
1382 | ||
1383 | static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, | |
1384 | int size, void *rpl) | |
1385 | { | |
1386 | return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); | |
1387 | } | |
1388 | ||
1389 | static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, | |
1390 | int size, void *rpl) | |
1391 | { | |
1392 | return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); | |
1393 | } | |
1394 | ||
1395 | /** | |
1396 | * hash_mac_addr - return the hash value of a MAC address | |
1397 | * @addr: the 48-bit Ethernet MAC address | |
1398 | * | |
1399 | * Hashes a MAC address according to the hash function used by HW inexact | |
1400 | * (hash) address matching. | |
1401 | */ | |
1402 | static inline int hash_mac_addr(const u8 *addr) | |
1403 | { | |
1404 | u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; | |
1405 | u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; | |
1406 | ||
1407 | a ^= b; | |
1408 | a ^= (a >> 12); | |
1409 | a ^= (a >> 6); | |
1410 | return a & 0x3f; | |
1411 | } | |
1412 | ||
1413 | int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us, | |
1414 | unsigned int cnt); | |
1415 | static inline void init_rspq(struct adapter *adap, struct sge_rspq *q, | |
1416 | unsigned int us, unsigned int cnt, | |
1417 | unsigned int size, unsigned int iqe_size) | |
1418 | { | |
1419 | q->adap = adap; | |
1420 | cxgb4_set_rspq_intr_params(q, us, cnt); | |
1421 | q->iqe_len = iqe_size; | |
1422 | q->size = size; | |
1423 | } | |
1424 | ||
1425 | void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, | |
1426 | unsigned int data_reg, const u32 *vals, | |
1427 | unsigned int nregs, unsigned int start_idx); | |
1428 | void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, | |
1429 | unsigned int data_reg, u32 *vals, unsigned int nregs, | |
1430 | unsigned int start_idx); | |
1431 | void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val); | |
1432 | ||
1433 | struct fw_filter_wr; | |
1434 | ||
1435 | void t4_intr_enable(struct adapter *adapter); | |
1436 | void t4_intr_disable(struct adapter *adapter); | |
1437 | int t4_slow_intr_handler(struct adapter *adapter); | |
1438 | ||
1439 | int t4_wait_dev_ready(void __iomem *regs); | |
1440 | int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port, | |
1441 | struct link_config *lc); | |
1442 | int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); | |
1443 | ||
1444 | u32 t4_read_pcie_cfg4(struct adapter *adap, int reg); | |
1445 | u32 t4_get_util_window(struct adapter *adap); | |
1446 | void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window); | |
1447 | ||
1448 | #define T4_MEMORY_WRITE 0 | |
1449 | #define T4_MEMORY_READ 1 | |
1450 | int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len, | |
1451 | void *buf, int dir); | |
1452 | static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr, | |
1453 | u32 len, __be32 *buf) | |
1454 | { | |
1455 | return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0); | |
1456 | } | |
1457 | ||
1458 | unsigned int t4_get_regs_len(struct adapter *adapter); | |
1459 | void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size); | |
1460 | ||
1461 | int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz); | |
1462 | int t4_seeprom_wp(struct adapter *adapter, bool enable); | |
1463 | int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p); | |
1464 | int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p); | |
1465 | int t4_read_flash(struct adapter *adapter, unsigned int addr, | |
1466 | unsigned int nwords, u32 *data, int byte_oriented); | |
1467 | int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); | |
1468 | int t4_load_phy_fw(struct adapter *adap, | |
1469 | int win, spinlock_t *lock, | |
1470 | int (*phy_fw_version)(const u8 *, size_t), | |
1471 | const u8 *phy_fw_data, size_t phy_fw_size); | |
1472 | int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver); | |
1473 | int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op); | |
1474 | int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, | |
1475 | const u8 *fw_data, unsigned int size, int force); | |
1476 | int t4_fl_pkt_align(struct adapter *adap); | |
1477 | unsigned int t4_flash_cfg_addr(struct adapter *adapter); | |
1478 | int t4_check_fw_version(struct adapter *adap); | |
1479 | int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); | |
1480 | int t4_get_fw_version(struct adapter *adapter, u32 *vers); | |
1481 | int t4_get_bs_version(struct adapter *adapter, u32 *vers); | |
1482 | int t4_get_tp_version(struct adapter *adapter, u32 *vers); | |
1483 | int t4_get_exprom_version(struct adapter *adapter, u32 *vers); | |
1484 | int t4_get_scfg_version(struct adapter *adapter, u32 *vers); | |
1485 | int t4_get_vpd_version(struct adapter *adapter, u32 *vers); | |
1486 | int t4_get_version_info(struct adapter *adapter); | |
1487 | void t4_dump_version_info(struct adapter *adapter); | |
1488 | int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, | |
1489 | const u8 *fw_data, unsigned int fw_size, | |
1490 | struct fw_hdr *card_fw, enum dev_state state, int *reset); | |
1491 | int t4_prep_adapter(struct adapter *adapter); | |
1492 | int t4_shutdown_adapter(struct adapter *adapter); | |
1493 | ||
1494 | enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; | |
1495 | int t4_bar2_sge_qregs(struct adapter *adapter, | |
1496 | unsigned int qid, | |
1497 | enum t4_bar2_qtype qtype, | |
1498 | int user, | |
1499 | u64 *pbar2_qoffset, | |
1500 | unsigned int *pbar2_qid); | |
1501 | ||
1502 | unsigned int qtimer_val(const struct adapter *adap, | |
1503 | const struct sge_rspq *q); | |
1504 | ||
1505 | int t4_init_devlog_params(struct adapter *adapter); | |
1506 | int t4_init_sge_params(struct adapter *adapter); | |
1507 | int t4_init_tp_params(struct adapter *adap, bool sleep_ok); | |
1508 | int t4_filter_field_shift(const struct adapter *adap, int filter_sel); | |
1509 | int t4_init_rss_mode(struct adapter *adap, int mbox); | |
1510 | int t4_init_portinfo(struct port_info *pi, int mbox, | |
1511 | int port, int pf, int vf, u8 mac[]); | |
1512 | int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); | |
1513 | void t4_fatal_err(struct adapter *adapter); | |
1514 | int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, | |
1515 | int start, int n, const u16 *rspq, unsigned int nrspq); | |
1516 | int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, | |
1517 | unsigned int flags); | |
1518 | int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, | |
1519 | unsigned int flags, unsigned int defq); | |
1520 | int t4_read_rss(struct adapter *adapter, u16 *entries); | |
1521 | void t4_read_rss_key(struct adapter *adapter, u32 *key, bool sleep_ok); | |
1522 | void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx, | |
1523 | bool sleep_ok); | |
1524 | void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, | |
1525 | u32 *valp, bool sleep_ok); | |
1526 | void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, | |
1527 | u32 *vfl, u32 *vfh, bool sleep_ok); | |
1528 | u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok); | |
1529 | u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok); | |
1530 | ||
1531 | unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx); | |
1532 | unsigned int t4_get_tp_ch_map(struct adapter *adapter, int pidx); | |
1533 | void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); | |
1534 | void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); | |
1535 | int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, | |
1536 | size_t n); | |
1537 | int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, | |
1538 | size_t n); | |
1539 | int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, | |
1540 | unsigned int *valp); | |
1541 | int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, | |
1542 | const unsigned int *valp); | |
1543 | int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); | |
1544 | void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, | |
1545 | unsigned int *pif_req_wrptr, | |
1546 | unsigned int *pif_rsp_wrptr); | |
1547 | void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); | |
1548 | void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); | |
1549 | const char *t4_get_port_type_description(enum fw_port_type port_type); | |
1550 | void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); | |
1551 | void t4_get_port_stats_offset(struct adapter *adap, int idx, | |
1552 | struct port_stats *stats, | |
1553 | struct port_stats *offset); | |
1554 | void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); | |
1555 | void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); | |
1556 | void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); | |
1557 | void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, | |
1558 | unsigned int mask, unsigned int val); | |
1559 | void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); | |
1560 | void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st, | |
1561 | bool sleep_ok); | |
1562 | void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st, | |
1563 | bool sleep_ok); | |
1564 | void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st, | |
1565 | bool sleep_ok); | |
1566 | void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st, | |
1567 | bool sleep_ok); | |
1568 | void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, | |
1569 | struct tp_tcp_stats *v6, bool sleep_ok); | |
1570 | void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, | |
1571 | struct tp_fcoe_stats *st, bool sleep_ok); | |
1572 | void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, | |
1573 | const unsigned short *alpha, const unsigned short *beta); | |
1574 | ||
1575 | void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); | |
1576 | ||
1577 | void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate); | |
1578 | void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); | |
1579 | ||
1580 | void t4_wol_magic_enable(struct adapter *adap, unsigned int port, | |
1581 | const u8 *addr); | |
1582 | int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, | |
1583 | u64 mask0, u64 mask1, unsigned int crc, bool enable); | |
1584 | ||
1585 | int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, | |
1586 | enum dev_master master, enum dev_state *state); | |
1587 | int t4_fw_bye(struct adapter *adap, unsigned int mbox); | |
1588 | int t4_early_init(struct adapter *adap, unsigned int mbox); | |
1589 | int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); | |
1590 | int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, | |
1591 | unsigned int cache_line_size); | |
1592 | int t4_fw_initialize(struct adapter *adap, unsigned int mbox); | |
1593 | int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, | |
1594 | unsigned int vf, unsigned int nparams, const u32 *params, | |
1595 | u32 *val); | |
1596 | int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf, | |
1597 | unsigned int vf, unsigned int nparams, const u32 *params, | |
1598 | u32 *val); | |
1599 | int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, | |
1600 | unsigned int vf, unsigned int nparams, const u32 *params, | |
1601 | u32 *val, int rw, bool sleep_ok); | |
1602 | int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, | |
1603 | unsigned int pf, unsigned int vf, | |
1604 | unsigned int nparams, const u32 *params, | |
1605 | const u32 *val, int timeout); | |
1606 | int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, | |
1607 | unsigned int vf, unsigned int nparams, const u32 *params, | |
1608 | const u32 *val); | |
1609 | int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, | |
1610 | unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, | |
1611 | unsigned int rxqi, unsigned int rxq, unsigned int tc, | |
1612 | unsigned int vi, unsigned int cmask, unsigned int pmask, | |
1613 | unsigned int nexact, unsigned int rcaps, unsigned int wxcaps); | |
1614 | int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, | |
1615 | unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, | |
1616 | unsigned int *rss_size); | |
1617 | int t4_free_vi(struct adapter *adap, unsigned int mbox, | |
1618 | unsigned int pf, unsigned int vf, | |
1619 | unsigned int viid); | |
1620 | int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, | |
1621 | int mtu, int promisc, int all_multi, int bcast, int vlanex, | |
1622 | bool sleep_ok); | |
1623 | int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, | |
1624 | unsigned int viid, bool free, unsigned int naddr, | |
1625 | const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok); | |
1626 | int t4_free_mac_filt(struct adapter *adap, unsigned int mbox, | |
1627 | unsigned int viid, unsigned int naddr, | |
1628 | const u8 **addr, bool sleep_ok); | |
1629 | int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, | |
1630 | int idx, const u8 *addr, bool persist, bool add_smt); | |
1631 | int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, | |
1632 | bool ucast, u64 vec, bool sleep_ok); | |
1633 | int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, | |
1634 | unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); | |
1635 | int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, | |
1636 | bool rx_en, bool tx_en); | |
1637 | int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, | |
1638 | unsigned int nblinks); | |
1639 | int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, | |
1640 | unsigned int mmd, unsigned int reg, u16 *valp); | |
1641 | int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, | |
1642 | unsigned int mmd, unsigned int reg, u16 val); | |
1643 | int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, | |
1644 | unsigned int vf, unsigned int iqtype, unsigned int iqid, | |
1645 | unsigned int fl0id, unsigned int fl1id); | |
1646 | int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, | |
1647 | unsigned int vf, unsigned int iqtype, unsigned int iqid, | |
1648 | unsigned int fl0id, unsigned int fl1id); | |
1649 | int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, | |
1650 | unsigned int vf, unsigned int eqid); | |
1651 | int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, | |
1652 | unsigned int vf, unsigned int eqid); | |
1653 | int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, | |
1654 | unsigned int vf, unsigned int eqid); | |
1655 | int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox); | |
1656 | void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl); | |
1657 | int t4_update_port_info(struct port_info *pi); | |
1658 | int t4_get_link_params(struct port_info *pi, unsigned int *link_okp, | |
1659 | unsigned int *speedp, unsigned int *mtup); | |
1660 | int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); | |
1661 | void t4_db_full(struct adapter *adapter); | |
1662 | void t4_db_dropped(struct adapter *adapter); | |
1663 | int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp, | |
1664 | int filter_index, int enable); | |
1665 | void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp, | |
1666 | int filter_index, int *enabled); | |
1667 | int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, | |
1668 | u32 addr, u32 val); | |
1669 | void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]); | |
1670 | void t4_get_tx_sched(struct adapter *adap, unsigned int sched, | |
1671 | unsigned int *kbps, unsigned int *ipg, bool sleep_ok); | |
1672 | int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid, | |
1673 | enum ctxt_type ctype, u32 *data); | |
1674 | int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, | |
1675 | enum ctxt_type ctype, u32 *data); | |
1676 | int t4_sched_params(struct adapter *adapter, int type, int level, int mode, | |
1677 | int rateunit, int ratemode, int channel, int class, | |
1678 | int minrate, int maxrate, int weight, int pktsize); | |
1679 | void t4_sge_decode_idma_state(struct adapter *adapter, int state); | |
1680 | void t4_idma_monitor_init(struct adapter *adapter, | |
1681 | struct sge_idma_monitor_state *idma); | |
1682 | void t4_idma_monitor(struct adapter *adapter, | |
1683 | struct sge_idma_monitor_state *idma, | |
1684 | int hz, int ticks); | |
1685 | int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf, | |
1686 | unsigned int naddr, u8 *addr); | |
1687 | void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs, | |
1688 | u32 start_index, bool sleep_ok); | |
1689 | void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs, | |
1690 | u32 start_index, bool sleep_ok); | |
1691 | void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, | |
1692 | u32 start_index, bool sleep_ok); | |
1693 | ||
1694 | void t4_uld_mem_free(struct adapter *adap); | |
1695 | int t4_uld_mem_alloc(struct adapter *adap); | |
1696 | void t4_uld_clean_up(struct adapter *adap); | |
1697 | void t4_register_netevent_notifier(void); | |
1698 | void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, struct sge_fl *fl); | |
1699 | void free_tx_desc(struct adapter *adap, struct sge_txq *q, | |
1700 | unsigned int n, bool unmap); | |
1701 | void free_txq(struct adapter *adap, struct sge_txq *q); | |
1702 | #endif /* __CXGB4_H__ */ |