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1 | // SPDX-License-Identifier: GPL-2.0+ | |
2 | // Copyright (c) 2016-2017 Hisilicon Limited. | |
3 | ||
4 | #ifndef __HCLGE_CMD_H | |
5 | #define __HCLGE_CMD_H | |
6 | #include <linux/types.h> | |
7 | #include <linux/io.h> | |
8 | ||
9 | #define HCLGE_CMDQ_TX_TIMEOUT 30000 | |
10 | ||
11 | struct hclge_dev; | |
12 | struct hclge_desc { | |
13 | __le16 opcode; | |
14 | ||
15 | #define HCLGE_CMDQ_RX_INVLD_B 0 | |
16 | #define HCLGE_CMDQ_RX_OUTVLD_B 1 | |
17 | ||
18 | __le16 flag; | |
19 | __le16 retval; | |
20 | __le16 rsv; | |
21 | __le32 data[6]; | |
22 | }; | |
23 | ||
24 | struct hclge_cmq_ring { | |
25 | dma_addr_t desc_dma_addr; | |
26 | struct hclge_desc *desc; | |
27 | struct hclge_dev *dev; | |
28 | u32 head; | |
29 | u32 tail; | |
30 | ||
31 | u16 buf_size; | |
32 | u16 desc_num; | |
33 | int next_to_use; | |
34 | int next_to_clean; | |
35 | u8 ring_type; /* cmq ring type */ | |
36 | spinlock_t lock; /* Command queue lock */ | |
37 | }; | |
38 | ||
39 | enum hclge_cmd_return_status { | |
40 | HCLGE_CMD_EXEC_SUCCESS = 0, | |
41 | HCLGE_CMD_NO_AUTH = 1, | |
42 | HCLGE_CMD_NOT_SUPPORTED = 2, | |
43 | HCLGE_CMD_QUEUE_FULL = 3, | |
44 | }; | |
45 | ||
46 | enum hclge_cmd_status { | |
47 | HCLGE_STATUS_SUCCESS = 0, | |
48 | HCLGE_ERR_CSQ_FULL = -1, | |
49 | HCLGE_ERR_CSQ_TIMEOUT = -2, | |
50 | HCLGE_ERR_CSQ_ERROR = -3, | |
51 | }; | |
52 | ||
53 | struct hclge_misc_vector { | |
54 | u8 __iomem *addr; | |
55 | int vector_irq; | |
56 | }; | |
57 | ||
58 | struct hclge_cmq { | |
59 | struct hclge_cmq_ring csq; | |
60 | struct hclge_cmq_ring crq; | |
61 | u16 tx_timeout; | |
62 | enum hclge_cmd_status last_status; | |
63 | }; | |
64 | ||
65 | #define HCLGE_CMD_FLAG_IN BIT(0) | |
66 | #define HCLGE_CMD_FLAG_OUT BIT(1) | |
67 | #define HCLGE_CMD_FLAG_NEXT BIT(2) | |
68 | #define HCLGE_CMD_FLAG_WR BIT(3) | |
69 | #define HCLGE_CMD_FLAG_NO_INTR BIT(4) | |
70 | #define HCLGE_CMD_FLAG_ERR_INTR BIT(5) | |
71 | ||
72 | enum hclge_opcode_type { | |
73 | /* Generic commands */ | |
74 | HCLGE_OPC_QUERY_FW_VER = 0x0001, | |
75 | HCLGE_OPC_CFG_RST_TRIGGER = 0x0020, | |
76 | HCLGE_OPC_GBL_RST_STATUS = 0x0021, | |
77 | HCLGE_OPC_QUERY_FUNC_STATUS = 0x0022, | |
78 | HCLGE_OPC_QUERY_PF_RSRC = 0x0023, | |
79 | HCLGE_OPC_QUERY_VF_RSRC = 0x0024, | |
80 | HCLGE_OPC_GET_CFG_PARAM = 0x0025, | |
81 | ||
82 | HCLGE_OPC_STATS_64_BIT = 0x0030, | |
83 | HCLGE_OPC_STATS_32_BIT = 0x0031, | |
84 | HCLGE_OPC_STATS_MAC = 0x0032, | |
85 | ||
86 | HCLGE_OPC_QUERY_REG_NUM = 0x0040, | |
87 | HCLGE_OPC_QUERY_32_BIT_REG = 0x0041, | |
88 | HCLGE_OPC_QUERY_64_BIT_REG = 0x0042, | |
89 | HCLGE_OPC_DFX_BD_NUM = 0x0043, | |
90 | HCLGE_OPC_DFX_BIOS_COMMON_REG = 0x0044, | |
91 | HCLGE_OPC_DFX_SSU_REG_0 = 0x0045, | |
92 | HCLGE_OPC_DFX_SSU_REG_1 = 0x0046, | |
93 | HCLGE_OPC_DFX_IGU_EGU_REG = 0x0047, | |
94 | HCLGE_OPC_DFX_RPU_REG_0 = 0x0048, | |
95 | HCLGE_OPC_DFX_RPU_REG_1 = 0x0049, | |
96 | HCLGE_OPC_DFX_NCSI_REG = 0x004A, | |
97 | HCLGE_OPC_DFX_RTC_REG = 0x004B, | |
98 | HCLGE_OPC_DFX_PPP_REG = 0x004C, | |
99 | HCLGE_OPC_DFX_RCB_REG = 0x004D, | |
100 | HCLGE_OPC_DFX_TQP_REG = 0x004E, | |
101 | HCLGE_OPC_DFX_SSU_REG_2 = 0x004F, | |
102 | HCLGE_OPC_DFX_QUERY_CHIP_CAP = 0x0050, | |
103 | ||
104 | /* MAC command */ | |
105 | HCLGE_OPC_CONFIG_MAC_MODE = 0x0301, | |
106 | HCLGE_OPC_CONFIG_AN_MODE = 0x0304, | |
107 | HCLGE_OPC_QUERY_LINK_STATUS = 0x0307, | |
108 | HCLGE_OPC_CONFIG_MAX_FRM_SIZE = 0x0308, | |
109 | HCLGE_OPC_CONFIG_SPEED_DUP = 0x0309, | |
110 | HCLGE_OPC_SERDES_LOOPBACK = 0x0315, | |
111 | ||
112 | /* PFC/Pause commands */ | |
113 | HCLGE_OPC_CFG_MAC_PAUSE_EN = 0x0701, | |
114 | HCLGE_OPC_CFG_PFC_PAUSE_EN = 0x0702, | |
115 | HCLGE_OPC_CFG_MAC_PARA = 0x0703, | |
116 | HCLGE_OPC_CFG_PFC_PARA = 0x0704, | |
117 | HCLGE_OPC_QUERY_MAC_TX_PKT_CNT = 0x0705, | |
118 | HCLGE_OPC_QUERY_MAC_RX_PKT_CNT = 0x0706, | |
119 | HCLGE_OPC_QUERY_PFC_TX_PKT_CNT = 0x0707, | |
120 | HCLGE_OPC_QUERY_PFC_RX_PKT_CNT = 0x0708, | |
121 | HCLGE_OPC_PRI_TO_TC_MAPPING = 0x0709, | |
122 | HCLGE_OPC_QOS_MAP = 0x070A, | |
123 | ||
124 | /* ETS/scheduler commands */ | |
125 | HCLGE_OPC_TM_PG_TO_PRI_LINK = 0x0804, | |
126 | HCLGE_OPC_TM_QS_TO_PRI_LINK = 0x0805, | |
127 | HCLGE_OPC_TM_NQ_TO_QS_LINK = 0x0806, | |
128 | HCLGE_OPC_TM_RQ_TO_QS_LINK = 0x0807, | |
129 | HCLGE_OPC_TM_PORT_WEIGHT = 0x0808, | |
130 | HCLGE_OPC_TM_PG_WEIGHT = 0x0809, | |
131 | HCLGE_OPC_TM_QS_WEIGHT = 0x080A, | |
132 | HCLGE_OPC_TM_PRI_WEIGHT = 0x080B, | |
133 | HCLGE_OPC_TM_PRI_C_SHAPPING = 0x080C, | |
134 | HCLGE_OPC_TM_PRI_P_SHAPPING = 0x080D, | |
135 | HCLGE_OPC_TM_PG_C_SHAPPING = 0x080E, | |
136 | HCLGE_OPC_TM_PG_P_SHAPPING = 0x080F, | |
137 | HCLGE_OPC_TM_PORT_SHAPPING = 0x0810, | |
138 | HCLGE_OPC_TM_PG_SCH_MODE_CFG = 0x0812, | |
139 | HCLGE_OPC_TM_PRI_SCH_MODE_CFG = 0x0813, | |
140 | HCLGE_OPC_TM_QS_SCH_MODE_CFG = 0x0814, | |
141 | HCLGE_OPC_TM_BP_TO_QSET_MAPPING = 0x0815, | |
142 | HCLGE_OPC_ETS_TC_WEIGHT = 0x0843, | |
143 | HCLGE_OPC_QSET_DFX_STS = 0x0844, | |
144 | HCLGE_OPC_PRI_DFX_STS = 0x0845, | |
145 | HCLGE_OPC_PG_DFX_STS = 0x0846, | |
146 | HCLGE_OPC_PORT_DFX_STS = 0x0847, | |
147 | HCLGE_OPC_SCH_NQ_CNT = 0x0848, | |
148 | HCLGE_OPC_SCH_RQ_CNT = 0x0849, | |
149 | HCLGE_OPC_TM_INTERNAL_STS = 0x0850, | |
150 | HCLGE_OPC_TM_INTERNAL_CNT = 0x0851, | |
151 | HCLGE_OPC_TM_INTERNAL_STS_1 = 0x0852, | |
152 | ||
153 | /* Packet buffer allocate commands */ | |
154 | HCLGE_OPC_TX_BUFF_ALLOC = 0x0901, | |
155 | HCLGE_OPC_RX_PRIV_BUFF_ALLOC = 0x0902, | |
156 | HCLGE_OPC_RX_PRIV_WL_ALLOC = 0x0903, | |
157 | HCLGE_OPC_RX_COM_THRD_ALLOC = 0x0904, | |
158 | HCLGE_OPC_RX_COM_WL_ALLOC = 0x0905, | |
159 | HCLGE_OPC_RX_GBL_PKT_CNT = 0x0906, | |
160 | ||
161 | /* TQP management command */ | |
162 | HCLGE_OPC_SET_TQP_MAP = 0x0A01, | |
163 | ||
164 | /* TQP commands */ | |
165 | HCLGE_OPC_CFG_TX_QUEUE = 0x0B01, | |
166 | HCLGE_OPC_QUERY_TX_POINTER = 0x0B02, | |
167 | HCLGE_OPC_QUERY_TX_STATUS = 0x0B03, | |
168 | HCLGE_OPC_TQP_TX_QUEUE_TC = 0x0B04, | |
169 | HCLGE_OPC_CFG_RX_QUEUE = 0x0B11, | |
170 | HCLGE_OPC_QUERY_RX_POINTER = 0x0B12, | |
171 | HCLGE_OPC_QUERY_RX_STATUS = 0x0B13, | |
172 | HCLGE_OPC_STASH_RX_QUEUE_LRO = 0x0B16, | |
173 | HCLGE_OPC_CFG_RX_QUEUE_LRO = 0x0B17, | |
174 | HCLGE_OPC_CFG_COM_TQP_QUEUE = 0x0B20, | |
175 | HCLGE_OPC_RESET_TQP_QUEUE = 0x0B22, | |
176 | ||
177 | /* TSO command */ | |
178 | HCLGE_OPC_TSO_GENERIC_CONFIG = 0x0C01, | |
179 | HCLGE_OPC_GRO_GENERIC_CONFIG = 0x0C10, | |
180 | ||
181 | /* RSS commands */ | |
182 | HCLGE_OPC_RSS_GENERIC_CONFIG = 0x0D01, | |
183 | HCLGE_OPC_RSS_INDIR_TABLE = 0x0D07, | |
184 | HCLGE_OPC_RSS_TC_MODE = 0x0D08, | |
185 | HCLGE_OPC_RSS_INPUT_TUPLE = 0x0D02, | |
186 | ||
187 | /* Promisuous mode command */ | |
188 | HCLGE_OPC_CFG_PROMISC_MODE = 0x0E01, | |
189 | ||
190 | /* Vlan offload commands */ | |
191 | HCLGE_OPC_VLAN_PORT_TX_CFG = 0x0F01, | |
192 | HCLGE_OPC_VLAN_PORT_RX_CFG = 0x0F02, | |
193 | ||
194 | /* Interrupts commands */ | |
195 | HCLGE_OPC_ADD_RING_TO_VECTOR = 0x1503, | |
196 | HCLGE_OPC_DEL_RING_TO_VECTOR = 0x1504, | |
197 | ||
198 | /* MAC commands */ | |
199 | HCLGE_OPC_MAC_VLAN_ADD = 0x1000, | |
200 | HCLGE_OPC_MAC_VLAN_REMOVE = 0x1001, | |
201 | HCLGE_OPC_MAC_VLAN_TYPE_ID = 0x1002, | |
202 | HCLGE_OPC_MAC_VLAN_INSERT = 0x1003, | |
203 | HCLGE_OPC_MAC_VLAN_ALLOCATE = 0x1004, | |
204 | HCLGE_OPC_MAC_ETHTYPE_ADD = 0x1010, | |
205 | HCLGE_OPC_MAC_ETHTYPE_REMOVE = 0x1011, | |
206 | ||
207 | /* VLAN commands */ | |
208 | HCLGE_OPC_VLAN_FILTER_CTRL = 0x1100, | |
209 | HCLGE_OPC_VLAN_FILTER_PF_CFG = 0x1101, | |
210 | HCLGE_OPC_VLAN_FILTER_VF_CFG = 0x1102, | |
211 | ||
212 | /* Flow Director commands */ | |
213 | HCLGE_OPC_FD_MODE_CTRL = 0x1200, | |
214 | HCLGE_OPC_FD_GET_ALLOCATION = 0x1201, | |
215 | HCLGE_OPC_FD_KEY_CONFIG = 0x1202, | |
216 | HCLGE_OPC_FD_TCAM_OP = 0x1203, | |
217 | HCLGE_OPC_FD_AD_OP = 0x1204, | |
218 | ||
219 | /* MDIO command */ | |
220 | HCLGE_OPC_MDIO_CONFIG = 0x1900, | |
221 | ||
222 | /* QCN commands */ | |
223 | HCLGE_OPC_QCN_MOD_CFG = 0x1A01, | |
224 | HCLGE_OPC_QCN_GRP_TMPLT_CFG = 0x1A02, | |
225 | HCLGE_OPC_QCN_SHAPPING_IR_CFG = 0x1A03, | |
226 | HCLGE_OPC_QCN_SHAPPING_BS_CFG = 0x1A04, | |
227 | HCLGE_OPC_QCN_QSET_LINK_CFG = 0x1A05, | |
228 | HCLGE_OPC_QCN_RP_STATUS_GET = 0x1A06, | |
229 | HCLGE_OPC_QCN_AJUST_INIT = 0x1A07, | |
230 | HCLGE_OPC_QCN_DFX_CNT_STATUS = 0x1A08, | |
231 | ||
232 | /* Mailbox command */ | |
233 | HCLGEVF_OPC_MBX_PF_TO_VF = 0x2000, | |
234 | ||
235 | /* Led command */ | |
236 | HCLGE_OPC_LED_STATUS_CFG = 0xB000, | |
237 | ||
238 | /* SFP command */ | |
239 | HCLGE_OPC_SFP_GET_SPEED = 0x7104, | |
240 | ||
241 | /* Error INT commands */ | |
242 | HCLGE_MAC_COMMON_INT_EN = 0x030E, | |
243 | HCLGE_TM_SCH_ECC_INT_EN = 0x0829, | |
244 | HCLGE_SSU_ECC_INT_CMD = 0x0989, | |
245 | HCLGE_SSU_COMMON_INT_CMD = 0x098C, | |
246 | HCLGE_PPU_MPF_ECC_INT_CMD = 0x0B40, | |
247 | HCLGE_PPU_MPF_OTHER_INT_CMD = 0x0B41, | |
248 | HCLGE_PPU_PF_OTHER_INT_CMD = 0x0B42, | |
249 | HCLGE_COMMON_ECC_INT_CFG = 0x1505, | |
250 | HCLGE_QUERY_RAS_INT_STS_BD_NUM = 0x1510, | |
251 | HCLGE_QUERY_CLEAR_MPF_RAS_INT = 0x1511, | |
252 | HCLGE_QUERY_CLEAR_PF_RAS_INT = 0x1512, | |
253 | HCLGE_QUERY_MSIX_INT_STS_BD_NUM = 0x1513, | |
254 | HCLGE_QUERY_CLEAR_ALL_MPF_MSIX_INT = 0x1514, | |
255 | HCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT = 0x1515, | |
256 | HCLGE_CONFIG_ROCEE_RAS_INT_EN = 0x1580, | |
257 | HCLGE_QUERY_CLEAR_ROCEE_RAS_INT = 0x1581, | |
258 | HCLGE_ROCEE_PF_RAS_INT_CMD = 0x1584, | |
259 | HCLGE_IGU_EGU_TNL_INT_EN = 0x1803, | |
260 | HCLGE_IGU_COMMON_INT_EN = 0x1806, | |
261 | HCLGE_TM_QCN_MEM_INT_CFG = 0x1A14, | |
262 | HCLGE_PPP_CMD0_INT_CMD = 0x2100, | |
263 | HCLGE_PPP_CMD1_INT_CMD = 0x2101, | |
264 | HCLGE_MAC_ETHERTYPE_IDX_RD = 0x2105, | |
265 | HCLGE_NCSI_INT_EN = 0x2401, | |
266 | }; | |
267 | ||
268 | #define HCLGE_TQP_REG_OFFSET 0x80000 | |
269 | #define HCLGE_TQP_REG_SIZE 0x200 | |
270 | ||
271 | #define HCLGE_RCB_INIT_QUERY_TIMEOUT 10 | |
272 | #define HCLGE_RCB_INIT_FLAG_EN_B 0 | |
273 | #define HCLGE_RCB_INIT_FLAG_FINI_B 8 | |
274 | struct hclge_config_rcb_init_cmd { | |
275 | __le16 rcb_init_flag; | |
276 | u8 rsv[22]; | |
277 | }; | |
278 | ||
279 | struct hclge_tqp_map_cmd { | |
280 | __le16 tqp_id; /* Absolute tqp id for in this pf */ | |
281 | u8 tqp_vf; /* VF id */ | |
282 | #define HCLGE_TQP_MAP_TYPE_PF 0 | |
283 | #define HCLGE_TQP_MAP_TYPE_VF 1 | |
284 | #define HCLGE_TQP_MAP_TYPE_B 0 | |
285 | #define HCLGE_TQP_MAP_EN_B 1 | |
286 | u8 tqp_flag; /* Indicate it's pf or vf tqp */ | |
287 | __le16 tqp_vid; /* Virtual id in this pf/vf */ | |
288 | u8 rsv[18]; | |
289 | }; | |
290 | ||
291 | #define HCLGE_VECTOR_ELEMENTS_PER_CMD 10 | |
292 | ||
293 | enum hclge_int_type { | |
294 | HCLGE_INT_TX, | |
295 | HCLGE_INT_RX, | |
296 | HCLGE_INT_EVENT, | |
297 | }; | |
298 | ||
299 | struct hclge_ctrl_vector_chain_cmd { | |
300 | u8 int_vector_id; | |
301 | u8 int_cause_num; | |
302 | #define HCLGE_INT_TYPE_S 0 | |
303 | #define HCLGE_INT_TYPE_M GENMASK(1, 0) | |
304 | #define HCLGE_TQP_ID_S 2 | |
305 | #define HCLGE_TQP_ID_M GENMASK(12, 2) | |
306 | #define HCLGE_INT_GL_IDX_S 13 | |
307 | #define HCLGE_INT_GL_IDX_M GENMASK(14, 13) | |
308 | __le16 tqp_type_and_id[HCLGE_VECTOR_ELEMENTS_PER_CMD]; | |
309 | u8 vfid; | |
310 | u8 rsv; | |
311 | }; | |
312 | ||
313 | #define HCLGE_TC_NUM 8 | |
314 | #define HCLGE_TC0_PRI_BUF_EN_B 15 /* Bit 15 indicate enable or not */ | |
315 | #define HCLGE_BUF_UNIT_S 7 /* Buf size is united by 128 bytes */ | |
316 | struct hclge_tx_buff_alloc_cmd { | |
317 | __le16 tx_pkt_buff[HCLGE_TC_NUM]; | |
318 | u8 tx_buff_rsv[8]; | |
319 | }; | |
320 | ||
321 | struct hclge_rx_priv_buff_cmd { | |
322 | __le16 buf_num[HCLGE_TC_NUM]; | |
323 | __le16 shared_buf; | |
324 | u8 rsv[6]; | |
325 | }; | |
326 | ||
327 | struct hclge_query_version_cmd { | |
328 | __le32 firmware; | |
329 | __le32 firmware_rsv[5]; | |
330 | }; | |
331 | ||
332 | #define HCLGE_RX_PRIV_EN_B 15 | |
333 | #define HCLGE_TC_NUM_ONE_DESC 4 | |
334 | struct hclge_priv_wl { | |
335 | __le16 high; | |
336 | __le16 low; | |
337 | }; | |
338 | ||
339 | struct hclge_rx_priv_wl_buf { | |
340 | struct hclge_priv_wl tc_wl[HCLGE_TC_NUM_ONE_DESC]; | |
341 | }; | |
342 | ||
343 | struct hclge_rx_com_thrd { | |
344 | struct hclge_priv_wl com_thrd[HCLGE_TC_NUM_ONE_DESC]; | |
345 | }; | |
346 | ||
347 | struct hclge_rx_com_wl { | |
348 | struct hclge_priv_wl com_wl; | |
349 | }; | |
350 | ||
351 | struct hclge_waterline { | |
352 | u32 low; | |
353 | u32 high; | |
354 | }; | |
355 | ||
356 | struct hclge_tc_thrd { | |
357 | u32 low; | |
358 | u32 high; | |
359 | }; | |
360 | ||
361 | struct hclge_priv_buf { | |
362 | struct hclge_waterline wl; /* Waterline for low and high*/ | |
363 | u32 buf_size; /* TC private buffer size */ | |
364 | u32 tx_buf_size; | |
365 | u32 enable; /* Enable TC private buffer or not */ | |
366 | }; | |
367 | ||
368 | #define HCLGE_MAX_TC_NUM 8 | |
369 | struct hclge_shared_buf { | |
370 | struct hclge_waterline self; | |
371 | struct hclge_tc_thrd tc_thrd[HCLGE_MAX_TC_NUM]; | |
372 | u32 buf_size; | |
373 | }; | |
374 | ||
375 | struct hclge_pkt_buf_alloc { | |
376 | struct hclge_priv_buf priv_buf[HCLGE_MAX_TC_NUM]; | |
377 | struct hclge_shared_buf s_buf; | |
378 | }; | |
379 | ||
380 | #define HCLGE_RX_COM_WL_EN_B 15 | |
381 | struct hclge_rx_com_wl_buf_cmd { | |
382 | __le16 high_wl; | |
383 | __le16 low_wl; | |
384 | u8 rsv[20]; | |
385 | }; | |
386 | ||
387 | #define HCLGE_RX_PKT_EN_B 15 | |
388 | struct hclge_rx_pkt_buf_cmd { | |
389 | __le16 high_pkt; | |
390 | __le16 low_pkt; | |
391 | u8 rsv[20]; | |
392 | }; | |
393 | ||
394 | #define HCLGE_PF_STATE_DONE_B 0 | |
395 | #define HCLGE_PF_STATE_MAIN_B 1 | |
396 | #define HCLGE_PF_STATE_BOND_B 2 | |
397 | #define HCLGE_PF_STATE_MAC_N_B 6 | |
398 | #define HCLGE_PF_MAC_NUM_MASK 0x3 | |
399 | #define HCLGE_PF_STATE_MAIN BIT(HCLGE_PF_STATE_MAIN_B) | |
400 | #define HCLGE_PF_STATE_DONE BIT(HCLGE_PF_STATE_DONE_B) | |
401 | struct hclge_func_status_cmd { | |
402 | __le32 vf_rst_state[4]; | |
403 | u8 pf_state; | |
404 | u8 mac_id; | |
405 | u8 rsv1; | |
406 | u8 pf_cnt_in_mac; | |
407 | u8 pf_num; | |
408 | u8 vf_num; | |
409 | u8 rsv[2]; | |
410 | }; | |
411 | ||
412 | struct hclge_pf_res_cmd { | |
413 | __le16 tqp_num; | |
414 | __le16 buf_size; | |
415 | __le16 msixcap_localid_ba_nic; | |
416 | __le16 msixcap_localid_ba_rocee; | |
417 | #define HCLGE_MSIX_OFT_ROCEE_S 0 | |
418 | #define HCLGE_MSIX_OFT_ROCEE_M GENMASK(15, 0) | |
419 | #define HCLGE_PF_VEC_NUM_S 0 | |
420 | #define HCLGE_PF_VEC_NUM_M GENMASK(7, 0) | |
421 | __le16 pf_intr_vector_number; | |
422 | __le16 pf_own_fun_number; | |
423 | __le16 tx_buf_size; | |
424 | __le16 dv_buf_size; | |
425 | __le32 rsv[2]; | |
426 | }; | |
427 | ||
428 | #define HCLGE_CFG_OFFSET_S 0 | |
429 | #define HCLGE_CFG_OFFSET_M GENMASK(19, 0) | |
430 | #define HCLGE_CFG_RD_LEN_S 24 | |
431 | #define HCLGE_CFG_RD_LEN_M GENMASK(27, 24) | |
432 | #define HCLGE_CFG_RD_LEN_BYTES 16 | |
433 | #define HCLGE_CFG_RD_LEN_UNIT 4 | |
434 | ||
435 | #define HCLGE_CFG_VMDQ_S 0 | |
436 | #define HCLGE_CFG_VMDQ_M GENMASK(7, 0) | |
437 | #define HCLGE_CFG_TC_NUM_S 8 | |
438 | #define HCLGE_CFG_TC_NUM_M GENMASK(15, 8) | |
439 | #define HCLGE_CFG_TQP_DESC_N_S 16 | |
440 | #define HCLGE_CFG_TQP_DESC_N_M GENMASK(31, 16) | |
441 | #define HCLGE_CFG_PHY_ADDR_S 0 | |
442 | #define HCLGE_CFG_PHY_ADDR_M GENMASK(7, 0) | |
443 | #define HCLGE_CFG_MEDIA_TP_S 8 | |
444 | #define HCLGE_CFG_MEDIA_TP_M GENMASK(15, 8) | |
445 | #define HCLGE_CFG_RX_BUF_LEN_S 16 | |
446 | #define HCLGE_CFG_RX_BUF_LEN_M GENMASK(31, 16) | |
447 | #define HCLGE_CFG_MAC_ADDR_H_S 0 | |
448 | #define HCLGE_CFG_MAC_ADDR_H_M GENMASK(15, 0) | |
449 | #define HCLGE_CFG_DEFAULT_SPEED_S 16 | |
450 | #define HCLGE_CFG_DEFAULT_SPEED_M GENMASK(23, 16) | |
451 | #define HCLGE_CFG_RSS_SIZE_S 24 | |
452 | #define HCLGE_CFG_RSS_SIZE_M GENMASK(31, 24) | |
453 | #define HCLGE_CFG_SPEED_ABILITY_S 0 | |
454 | #define HCLGE_CFG_SPEED_ABILITY_M GENMASK(7, 0) | |
455 | #define HCLGE_CFG_UMV_TBL_SPACE_S 16 | |
456 | #define HCLGE_CFG_UMV_TBL_SPACE_M GENMASK(31, 16) | |
457 | ||
458 | struct hclge_cfg_param_cmd { | |
459 | __le32 offset; | |
460 | __le32 rsv; | |
461 | __le32 param[4]; | |
462 | }; | |
463 | ||
464 | #define HCLGE_MAC_MODE 0x0 | |
465 | #define HCLGE_DESC_NUM 0x40 | |
466 | ||
467 | #define HCLGE_ALLOC_VALID_B 0 | |
468 | struct hclge_vf_num_cmd { | |
469 | u8 alloc_valid; | |
470 | u8 rsv[23]; | |
471 | }; | |
472 | ||
473 | #define HCLGE_RSS_DEFAULT_OUTPORT_B 4 | |
474 | #define HCLGE_RSS_HASH_KEY_OFFSET_B 4 | |
475 | #define HCLGE_RSS_HASH_KEY_NUM 16 | |
476 | struct hclge_rss_config_cmd { | |
477 | u8 hash_config; | |
478 | u8 rsv[7]; | |
479 | u8 hash_key[HCLGE_RSS_HASH_KEY_NUM]; | |
480 | }; | |
481 | ||
482 | struct hclge_rss_input_tuple_cmd { | |
483 | u8 ipv4_tcp_en; | |
484 | u8 ipv4_udp_en; | |
485 | u8 ipv4_sctp_en; | |
486 | u8 ipv4_fragment_en; | |
487 | u8 ipv6_tcp_en; | |
488 | u8 ipv6_udp_en; | |
489 | u8 ipv6_sctp_en; | |
490 | u8 ipv6_fragment_en; | |
491 | u8 rsv[16]; | |
492 | }; | |
493 | ||
494 | #define HCLGE_RSS_CFG_TBL_SIZE 16 | |
495 | ||
496 | struct hclge_rss_indirection_table_cmd { | |
497 | __le16 start_table_index; | |
498 | __le16 rss_set_bitmap; | |
499 | u8 rsv[4]; | |
500 | u8 rss_result[HCLGE_RSS_CFG_TBL_SIZE]; | |
501 | }; | |
502 | ||
503 | #define HCLGE_RSS_TC_OFFSET_S 0 | |
504 | #define HCLGE_RSS_TC_OFFSET_M GENMASK(9, 0) | |
505 | #define HCLGE_RSS_TC_SIZE_S 12 | |
506 | #define HCLGE_RSS_TC_SIZE_M GENMASK(14, 12) | |
507 | #define HCLGE_RSS_TC_VALID_B 15 | |
508 | struct hclge_rss_tc_mode_cmd { | |
509 | __le16 rss_tc_mode[HCLGE_MAX_TC_NUM]; | |
510 | u8 rsv[8]; | |
511 | }; | |
512 | ||
513 | #define HCLGE_LINK_STATUS_UP_B 0 | |
514 | #define HCLGE_LINK_STATUS_UP_M BIT(HCLGE_LINK_STATUS_UP_B) | |
515 | struct hclge_link_status_cmd { | |
516 | u8 status; | |
517 | u8 rsv[23]; | |
518 | }; | |
519 | ||
520 | struct hclge_promisc_param { | |
521 | u8 vf_id; | |
522 | u8 enable; | |
523 | }; | |
524 | ||
525 | #define HCLGE_PROMISC_TX_EN_B BIT(4) | |
526 | #define HCLGE_PROMISC_RX_EN_B BIT(5) | |
527 | #define HCLGE_PROMISC_EN_B 1 | |
528 | #define HCLGE_PROMISC_EN_ALL 0x7 | |
529 | #define HCLGE_PROMISC_EN_UC 0x1 | |
530 | #define HCLGE_PROMISC_EN_MC 0x2 | |
531 | #define HCLGE_PROMISC_EN_BC 0x4 | |
532 | struct hclge_promisc_cfg_cmd { | |
533 | u8 flag; | |
534 | u8 vf_id; | |
535 | __le16 rsv0; | |
536 | u8 rsv1[20]; | |
537 | }; | |
538 | ||
539 | enum hclge_promisc_type { | |
540 | HCLGE_UNICAST = 1, | |
541 | HCLGE_MULTICAST = 2, | |
542 | HCLGE_BROADCAST = 3, | |
543 | }; | |
544 | ||
545 | #define HCLGE_MAC_TX_EN_B 6 | |
546 | #define HCLGE_MAC_RX_EN_B 7 | |
547 | #define HCLGE_MAC_PAD_TX_B 11 | |
548 | #define HCLGE_MAC_PAD_RX_B 12 | |
549 | #define HCLGE_MAC_1588_TX_B 13 | |
550 | #define HCLGE_MAC_1588_RX_B 14 | |
551 | #define HCLGE_MAC_APP_LP_B 15 | |
552 | #define HCLGE_MAC_LINE_LP_B 16 | |
553 | #define HCLGE_MAC_FCS_TX_B 17 | |
554 | #define HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B 18 | |
555 | #define HCLGE_MAC_RX_FCS_STRIP_B 19 | |
556 | #define HCLGE_MAC_RX_FCS_B 20 | |
557 | #define HCLGE_MAC_TX_UNDER_MIN_ERR_B 21 | |
558 | #define HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B 22 | |
559 | ||
560 | struct hclge_config_mac_mode_cmd { | |
561 | __le32 txrx_pad_fcs_loop_en; | |
562 | u8 rsv[20]; | |
563 | }; | |
564 | ||
565 | #define HCLGE_CFG_SPEED_S 0 | |
566 | #define HCLGE_CFG_SPEED_M GENMASK(5, 0) | |
567 | ||
568 | #define HCLGE_CFG_DUPLEX_B 7 | |
569 | #define HCLGE_CFG_DUPLEX_M BIT(HCLGE_CFG_DUPLEX_B) | |
570 | ||
571 | struct hclge_config_mac_speed_dup_cmd { | |
572 | u8 speed_dup; | |
573 | ||
574 | #define HCLGE_CFG_MAC_SPEED_CHANGE_EN_B 0 | |
575 | u8 mac_change_fec_en; | |
576 | u8 rsv[22]; | |
577 | }; | |
578 | ||
579 | #define HCLGE_RING_ID_MASK GENMASK(9, 0) | |
580 | #define HCLGE_TQP_ENABLE_B 0 | |
581 | ||
582 | #define HCLGE_MAC_CFG_AN_EN_B 0 | |
583 | #define HCLGE_MAC_CFG_AN_INT_EN_B 1 | |
584 | #define HCLGE_MAC_CFG_AN_INT_MSK_B 2 | |
585 | #define HCLGE_MAC_CFG_AN_INT_CLR_B 3 | |
586 | #define HCLGE_MAC_CFG_AN_RST_B 4 | |
587 | ||
588 | #define HCLGE_MAC_CFG_AN_EN BIT(HCLGE_MAC_CFG_AN_EN_B) | |
589 | ||
590 | struct hclge_config_auto_neg_cmd { | |
591 | __le32 cfg_an_cmd_flag; | |
592 | u8 rsv[20]; | |
593 | }; | |
594 | ||
595 | struct hclge_sfp_speed_cmd { | |
596 | __le32 sfp_speed; | |
597 | u32 rsv[5]; | |
598 | }; | |
599 | ||
600 | #define HCLGE_MAC_UPLINK_PORT 0x100 | |
601 | ||
602 | struct hclge_config_max_frm_size_cmd { | |
603 | __le16 max_frm_size; | |
604 | u8 min_frm_size; | |
605 | u8 rsv[21]; | |
606 | }; | |
607 | ||
608 | enum hclge_mac_vlan_tbl_opcode { | |
609 | HCLGE_MAC_VLAN_ADD, /* Add new or modify mac_vlan */ | |
610 | HCLGE_MAC_VLAN_UPDATE, /* Modify other fields of this table */ | |
611 | HCLGE_MAC_VLAN_REMOVE, /* Remove a entry through mac_vlan key */ | |
612 | HCLGE_MAC_VLAN_LKUP, /* Lookup a entry through mac_vlan key */ | |
613 | }; | |
614 | ||
615 | #define HCLGE_MAC_VLAN_BIT0_EN_B 0 | |
616 | #define HCLGE_MAC_VLAN_BIT1_EN_B 1 | |
617 | #define HCLGE_MAC_EPORT_SW_EN_B 12 | |
618 | #define HCLGE_MAC_EPORT_TYPE_B 11 | |
619 | #define HCLGE_MAC_EPORT_VFID_S 3 | |
620 | #define HCLGE_MAC_EPORT_VFID_M GENMASK(10, 3) | |
621 | #define HCLGE_MAC_EPORT_PFID_S 0 | |
622 | #define HCLGE_MAC_EPORT_PFID_M GENMASK(2, 0) | |
623 | struct hclge_mac_vlan_tbl_entry_cmd { | |
624 | u8 flags; | |
625 | u8 resp_code; | |
626 | __le16 vlan_tag; | |
627 | __le32 mac_addr_hi32; | |
628 | __le16 mac_addr_lo16; | |
629 | __le16 rsv1; | |
630 | u8 entry_type; | |
631 | u8 mc_mac_en; | |
632 | __le16 egress_port; | |
633 | __le16 egress_queue; | |
634 | u8 rsv2[6]; | |
635 | }; | |
636 | ||
637 | #define HCLGE_UMV_SPC_ALC_B 0 | |
638 | struct hclge_umv_spc_alc_cmd { | |
639 | u8 allocate; | |
640 | u8 rsv1[3]; | |
641 | __le32 space_size; | |
642 | u8 rsv2[16]; | |
643 | }; | |
644 | ||
645 | #define HCLGE_MAC_MGR_MASK_VLAN_B BIT(0) | |
646 | #define HCLGE_MAC_MGR_MASK_MAC_B BIT(1) | |
647 | #define HCLGE_MAC_MGR_MASK_ETHERTYPE_B BIT(2) | |
648 | #define HCLGE_MAC_ETHERTYPE_LLDP 0x88cc | |
649 | ||
650 | struct hclge_mac_mgr_tbl_entry_cmd { | |
651 | u8 flags; | |
652 | u8 resp_code; | |
653 | __le16 vlan_tag; | |
654 | __le32 mac_addr_hi32; | |
655 | __le16 mac_addr_lo16; | |
656 | __le16 rsv1; | |
657 | __le16 ethter_type; | |
658 | __le16 egress_port; | |
659 | __le16 egress_queue; | |
660 | u8 sw_port_id_aware; | |
661 | u8 rsv2; | |
662 | u8 i_port_bitmap; | |
663 | u8 i_port_direction; | |
664 | u8 rsv3[2]; | |
665 | }; | |
666 | ||
667 | struct hclge_mac_vlan_add_cmd { | |
668 | __le16 flags; | |
669 | __le16 mac_addr_hi16; | |
670 | __le32 mac_addr_lo32; | |
671 | __le32 mac_addr_msk_hi32; | |
672 | __le16 mac_addr_msk_lo16; | |
673 | __le16 vlan_tag; | |
674 | __le16 ingress_port; | |
675 | __le16 egress_port; | |
676 | u8 rsv[4]; | |
677 | }; | |
678 | ||
679 | #define HNS3_MAC_VLAN_CFG_FLAG_BIT 0 | |
680 | struct hclge_mac_vlan_remove_cmd { | |
681 | __le16 flags; | |
682 | __le16 mac_addr_hi16; | |
683 | __le32 mac_addr_lo32; | |
684 | __le32 mac_addr_msk_hi32; | |
685 | __le16 mac_addr_msk_lo16; | |
686 | __le16 vlan_tag; | |
687 | __le16 ingress_port; | |
688 | __le16 egress_port; | |
689 | u8 rsv[4]; | |
690 | }; | |
691 | ||
692 | struct hclge_vlan_filter_ctrl_cmd { | |
693 | u8 vlan_type; | |
694 | u8 vlan_fe; | |
695 | u8 rsv[22]; | |
696 | }; | |
697 | ||
698 | struct hclge_vlan_filter_pf_cfg_cmd { | |
699 | u8 vlan_offset; | |
700 | u8 vlan_cfg; | |
701 | u8 rsv[2]; | |
702 | u8 vlan_offset_bitmap[20]; | |
703 | }; | |
704 | ||
705 | struct hclge_vlan_filter_vf_cfg_cmd { | |
706 | __le16 vlan_id; | |
707 | u8 resp_code; | |
708 | u8 rsv; | |
709 | u8 vlan_cfg; | |
710 | u8 rsv1[3]; | |
711 | u8 vf_bitmap[16]; | |
712 | }; | |
713 | ||
714 | #define HCLGE_ACCEPT_TAG1_B 0 | |
715 | #define HCLGE_ACCEPT_UNTAG1_B 1 | |
716 | #define HCLGE_PORT_INS_TAG1_EN_B 2 | |
717 | #define HCLGE_PORT_INS_TAG2_EN_B 3 | |
718 | #define HCLGE_CFG_NIC_ROCE_SEL_B 4 | |
719 | #define HCLGE_ACCEPT_TAG2_B 5 | |
720 | #define HCLGE_ACCEPT_UNTAG2_B 6 | |
721 | ||
722 | struct hclge_vport_vtag_tx_cfg_cmd { | |
723 | u8 vport_vlan_cfg; | |
724 | u8 vf_offset; | |
725 | u8 rsv1[2]; | |
726 | __le16 def_vlan_tag1; | |
727 | __le16 def_vlan_tag2; | |
728 | u8 vf_bitmap[8]; | |
729 | u8 rsv2[8]; | |
730 | }; | |
731 | ||
732 | #define HCLGE_REM_TAG1_EN_B 0 | |
733 | #define HCLGE_REM_TAG2_EN_B 1 | |
734 | #define HCLGE_SHOW_TAG1_EN_B 2 | |
735 | #define HCLGE_SHOW_TAG2_EN_B 3 | |
736 | struct hclge_vport_vtag_rx_cfg_cmd { | |
737 | u8 vport_vlan_cfg; | |
738 | u8 vf_offset; | |
739 | u8 rsv1[6]; | |
740 | u8 vf_bitmap[8]; | |
741 | u8 rsv2[8]; | |
742 | }; | |
743 | ||
744 | struct hclge_tx_vlan_type_cfg_cmd { | |
745 | __le16 ot_vlan_type; | |
746 | __le16 in_vlan_type; | |
747 | u8 rsv[20]; | |
748 | }; | |
749 | ||
750 | struct hclge_rx_vlan_type_cfg_cmd { | |
751 | __le16 ot_fst_vlan_type; | |
752 | __le16 ot_sec_vlan_type; | |
753 | __le16 in_fst_vlan_type; | |
754 | __le16 in_sec_vlan_type; | |
755 | u8 rsv[16]; | |
756 | }; | |
757 | ||
758 | struct hclge_cfg_com_tqp_queue_cmd { | |
759 | __le16 tqp_id; | |
760 | __le16 stream_id; | |
761 | u8 enable; | |
762 | u8 rsv[19]; | |
763 | }; | |
764 | ||
765 | struct hclge_cfg_tx_queue_pointer_cmd { | |
766 | __le16 tqp_id; | |
767 | __le16 tx_tail; | |
768 | __le16 tx_head; | |
769 | __le16 fbd_num; | |
770 | __le16 ring_offset; | |
771 | u8 rsv[14]; | |
772 | }; | |
773 | ||
774 | #pragma pack(1) | |
775 | struct hclge_mac_ethertype_idx_rd_cmd { | |
776 | u8 flags; | |
777 | u8 resp_code; | |
778 | __le16 vlan_tag; | |
779 | u8 mac_add[6]; | |
780 | __le16 index; | |
781 | __le16 ethter_type; | |
782 | __le16 egress_port; | |
783 | __le16 egress_queue; | |
784 | __le16 rev0; | |
785 | u8 i_port_bitmap; | |
786 | u8 i_port_direction; | |
787 | u8 rev1[2]; | |
788 | }; | |
789 | ||
790 | #pragma pack() | |
791 | ||
792 | #define HCLGE_TSO_MSS_MIN_S 0 | |
793 | #define HCLGE_TSO_MSS_MIN_M GENMASK(13, 0) | |
794 | ||
795 | #define HCLGE_TSO_MSS_MAX_S 16 | |
796 | #define HCLGE_TSO_MSS_MAX_M GENMASK(29, 16) | |
797 | ||
798 | struct hclge_cfg_tso_status_cmd { | |
799 | __le16 tso_mss_min; | |
800 | __le16 tso_mss_max; | |
801 | u8 rsv[20]; | |
802 | }; | |
803 | ||
804 | #define HCLGE_GRO_EN_B 0 | |
805 | struct hclge_cfg_gro_status_cmd { | |
806 | __le16 gro_en; | |
807 | u8 rsv[22]; | |
808 | }; | |
809 | ||
810 | #define HCLGE_TSO_MSS_MIN 256 | |
811 | #define HCLGE_TSO_MSS_MAX 9668 | |
812 | ||
813 | #define HCLGE_TQP_RESET_B 0 | |
814 | struct hclge_reset_tqp_queue_cmd { | |
815 | __le16 tqp_id; | |
816 | u8 reset_req; | |
817 | u8 ready_to_reset; | |
818 | u8 rsv[20]; | |
819 | }; | |
820 | ||
821 | #define HCLGE_CFG_RESET_MAC_B 3 | |
822 | #define HCLGE_CFG_RESET_FUNC_B 7 | |
823 | struct hclge_reset_cmd { | |
824 | u8 mac_func_reset; | |
825 | u8 fun_reset_vfid; | |
826 | u8 rsv[22]; | |
827 | }; | |
828 | ||
829 | #define HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B BIT(0) | |
830 | #define HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B BIT(2) | |
831 | #define HCLGE_CMD_SERDES_DONE_B BIT(0) | |
832 | #define HCLGE_CMD_SERDES_SUCCESS_B BIT(1) | |
833 | struct hclge_serdes_lb_cmd { | |
834 | u8 mask; | |
835 | u8 enable; | |
836 | u8 result; | |
837 | u8 rsv[21]; | |
838 | }; | |
839 | ||
840 | #define HCLGE_DEFAULT_TX_BUF 0x4000 /* 16k bytes */ | |
841 | #define HCLGE_TOTAL_PKT_BUF 0x108000 /* 1.03125M bytes */ | |
842 | #define HCLGE_DEFAULT_DV 0xA000 /* 40k byte */ | |
843 | #define HCLGE_DEFAULT_NON_DCB_DV 0x7800 /* 30K byte */ | |
844 | #define HCLGE_NON_DCB_ADDITIONAL_BUF 0x200 /* 512 byte */ | |
845 | ||
846 | #define HCLGE_TYPE_CRQ 0 | |
847 | #define HCLGE_TYPE_CSQ 1 | |
848 | #define HCLGE_NIC_CSQ_BASEADDR_L_REG 0x27000 | |
849 | #define HCLGE_NIC_CSQ_BASEADDR_H_REG 0x27004 | |
850 | #define HCLGE_NIC_CSQ_DEPTH_REG 0x27008 | |
851 | #define HCLGE_NIC_CSQ_TAIL_REG 0x27010 | |
852 | #define HCLGE_NIC_CSQ_HEAD_REG 0x27014 | |
853 | #define HCLGE_NIC_CRQ_BASEADDR_L_REG 0x27018 | |
854 | #define HCLGE_NIC_CRQ_BASEADDR_H_REG 0x2701c | |
855 | #define HCLGE_NIC_CRQ_DEPTH_REG 0x27020 | |
856 | #define HCLGE_NIC_CRQ_TAIL_REG 0x27024 | |
857 | #define HCLGE_NIC_CRQ_HEAD_REG 0x27028 | |
858 | #define HCLGE_NIC_CMQ_EN_B 16 | |
859 | #define HCLGE_NIC_CMQ_ENABLE BIT(HCLGE_NIC_CMQ_EN_B) | |
860 | #define HCLGE_NIC_CMQ_DESC_NUM 1024 | |
861 | #define HCLGE_NIC_CMQ_DESC_NUM_S 3 | |
862 | ||
863 | #define HCLGE_LED_LOCATE_STATE_S 0 | |
864 | #define HCLGE_LED_LOCATE_STATE_M GENMASK(1, 0) | |
865 | ||
866 | struct hclge_set_led_state_cmd { | |
867 | u8 rsv1[3]; | |
868 | u8 locate_led_config; | |
869 | u8 rsv2[20]; | |
870 | }; | |
871 | ||
872 | struct hclge_get_fd_mode_cmd { | |
873 | u8 mode; | |
874 | u8 enable; | |
875 | u8 rsv[22]; | |
876 | }; | |
877 | ||
878 | struct hclge_get_fd_allocation_cmd { | |
879 | __le32 stage1_entry_num; | |
880 | __le32 stage2_entry_num; | |
881 | __le16 stage1_counter_num; | |
882 | __le16 stage2_counter_num; | |
883 | u8 rsv[12]; | |
884 | }; | |
885 | ||
886 | struct hclge_set_fd_key_config_cmd { | |
887 | u8 stage; | |
888 | u8 key_select; | |
889 | u8 inner_sipv6_word_en; | |
890 | u8 inner_dipv6_word_en; | |
891 | u8 outer_sipv6_word_en; | |
892 | u8 outer_dipv6_word_en; | |
893 | u8 rsv1[2]; | |
894 | __le32 tuple_mask; | |
895 | __le32 meta_data_mask; | |
896 | u8 rsv2[8]; | |
897 | }; | |
898 | ||
899 | #define HCLGE_FD_EPORT_SW_EN_B 0 | |
900 | struct hclge_fd_tcam_config_1_cmd { | |
901 | u8 stage; | |
902 | u8 xy_sel; | |
903 | u8 port_info; | |
904 | u8 rsv1[1]; | |
905 | __le32 index; | |
906 | u8 entry_vld; | |
907 | u8 rsv2[7]; | |
908 | u8 tcam_data[8]; | |
909 | }; | |
910 | ||
911 | struct hclge_fd_tcam_config_2_cmd { | |
912 | u8 tcam_data[24]; | |
913 | }; | |
914 | ||
915 | struct hclge_fd_tcam_config_3_cmd { | |
916 | u8 tcam_data[20]; | |
917 | u8 rsv[4]; | |
918 | }; | |
919 | ||
920 | #define HCLGE_FD_AD_DROP_B 0 | |
921 | #define HCLGE_FD_AD_DIRECT_QID_B 1 | |
922 | #define HCLGE_FD_AD_QID_S 2 | |
923 | #define HCLGE_FD_AD_QID_M GENMASK(12, 2) | |
924 | #define HCLGE_FD_AD_USE_COUNTER_B 12 | |
925 | #define HCLGE_FD_AD_COUNTER_NUM_S 13 | |
926 | #define HCLGE_FD_AD_COUNTER_NUM_M GENMASK(20, 13) | |
927 | #define HCLGE_FD_AD_NXT_STEP_B 20 | |
928 | #define HCLGE_FD_AD_NXT_KEY_S 21 | |
929 | #define HCLGE_FD_AD_NXT_KEY_M GENMASK(26, 21) | |
930 | #define HCLGE_FD_AD_WR_RULE_ID_B 0 | |
931 | #define HCLGE_FD_AD_RULE_ID_S 1 | |
932 | #define HCLGE_FD_AD_RULE_ID_M GENMASK(13, 1) | |
933 | ||
934 | struct hclge_fd_ad_config_cmd { | |
935 | u8 stage; | |
936 | u8 rsv1[3]; | |
937 | __le32 index; | |
938 | __le64 ad_data; | |
939 | u8 rsv2[8]; | |
940 | }; | |
941 | ||
942 | int hclge_cmd_init(struct hclge_dev *hdev); | |
943 | static inline void hclge_write_reg(void __iomem *base, u32 reg, u32 value) | |
944 | { | |
945 | writel(value, base + reg); | |
946 | } | |
947 | ||
948 | #define hclge_write_dev(a, reg, value) \ | |
949 | hclge_write_reg((a)->io_base, (reg), (value)) | |
950 | #define hclge_read_dev(a, reg) \ | |
951 | hclge_read_reg((a)->io_base, (reg)) | |
952 | ||
953 | static inline u32 hclge_read_reg(u8 __iomem *base, u32 reg) | |
954 | { | |
955 | u8 __iomem *reg_addr = READ_ONCE(base); | |
956 | ||
957 | return readl(reg_addr + reg); | |
958 | } | |
959 | ||
960 | #define HCLGE_SEND_SYNC(flag) \ | |
961 | ((flag) & HCLGE_CMD_FLAG_NO_INTR) | |
962 | ||
963 | struct hclge_hw; | |
964 | int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num); | |
965 | void hclge_cmd_setup_basic_desc(struct hclge_desc *desc, | |
966 | enum hclge_opcode_type opcode, bool is_read); | |
967 | void hclge_cmd_reuse_desc(struct hclge_desc *desc, bool is_read); | |
968 | ||
969 | int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev, | |
970 | struct hclge_promisc_param *param); | |
971 | ||
972 | enum hclge_cmd_status hclge_cmd_mdio_write(struct hclge_hw *hw, | |
973 | struct hclge_desc *desc); | |
974 | enum hclge_cmd_status hclge_cmd_mdio_read(struct hclge_hw *hw, | |
975 | struct hclge_desc *desc); | |
976 | ||
977 | void hclge_destroy_cmd_queue(struct hclge_hw *hw); | |
978 | int hclge_cmd_queue_init(struct hclge_dev *hdev); | |
979 | #endif |