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1 | /* Intel PRO/1000 Linux driver | |
2 | * Copyright(c) 1999 - 2014 Intel Corporation. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | * | |
13 | * The full GNU General Public License is included in this distribution in | |
14 | * the file called "COPYING". | |
15 | * | |
16 | * Contact Information: | |
17 | * Linux NICS <linux.nics@intel.com> | |
18 | * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
19 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
20 | */ | |
21 | ||
22 | /* 82562G 10/100 Network Connection | |
23 | * 82562G-2 10/100 Network Connection | |
24 | * 82562GT 10/100 Network Connection | |
25 | * 82562GT-2 10/100 Network Connection | |
26 | * 82562V 10/100 Network Connection | |
27 | * 82562V-2 10/100 Network Connection | |
28 | * 82566DC-2 Gigabit Network Connection | |
29 | * 82566DC Gigabit Network Connection | |
30 | * 82566DM-2 Gigabit Network Connection | |
31 | * 82566DM Gigabit Network Connection | |
32 | * 82566MC Gigabit Network Connection | |
33 | * 82566MM Gigabit Network Connection | |
34 | * 82567LM Gigabit Network Connection | |
35 | * 82567LF Gigabit Network Connection | |
36 | * 82567V Gigabit Network Connection | |
37 | * 82567LM-2 Gigabit Network Connection | |
38 | * 82567LF-2 Gigabit Network Connection | |
39 | * 82567V-2 Gigabit Network Connection | |
40 | * 82567LF-3 Gigabit Network Connection | |
41 | * 82567LM-3 Gigabit Network Connection | |
42 | * 82567LM-4 Gigabit Network Connection | |
43 | * 82577LM Gigabit Network Connection | |
44 | * 82577LC Gigabit Network Connection | |
45 | * 82578DM Gigabit Network Connection | |
46 | * 82578DC Gigabit Network Connection | |
47 | * 82579LM Gigabit Network Connection | |
48 | * 82579V Gigabit Network Connection | |
49 | * Ethernet Connection I217-LM | |
50 | * Ethernet Connection I217-V | |
51 | * Ethernet Connection I218-V | |
52 | * Ethernet Connection I218-LM | |
53 | * Ethernet Connection (2) I218-LM | |
54 | * Ethernet Connection (2) I218-V | |
55 | * Ethernet Connection (3) I218-LM | |
56 | * Ethernet Connection (3) I218-V | |
57 | */ | |
58 | ||
59 | #include "e1000.h" | |
60 | ||
61 | /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ | |
62 | /* Offset 04h HSFSTS */ | |
63 | union ich8_hws_flash_status { | |
64 | struct ich8_hsfsts { | |
65 | u16 flcdone:1; /* bit 0 Flash Cycle Done */ | |
66 | u16 flcerr:1; /* bit 1 Flash Cycle Error */ | |
67 | u16 dael:1; /* bit 2 Direct Access error Log */ | |
68 | u16 berasesz:2; /* bit 4:3 Sector Erase Size */ | |
69 | u16 flcinprog:1; /* bit 5 flash cycle in Progress */ | |
70 | u16 reserved1:2; /* bit 13:6 Reserved */ | |
71 | u16 reserved2:6; /* bit 13:6 Reserved */ | |
72 | u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */ | |
73 | u16 flockdn:1; /* bit 15 Flash Config Lock-Down */ | |
74 | } hsf_status; | |
75 | u16 regval; | |
76 | }; | |
77 | ||
78 | /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */ | |
79 | /* Offset 06h FLCTL */ | |
80 | union ich8_hws_flash_ctrl { | |
81 | struct ich8_hsflctl { | |
82 | u16 flcgo:1; /* 0 Flash Cycle Go */ | |
83 | u16 flcycle:2; /* 2:1 Flash Cycle */ | |
84 | u16 reserved:5; /* 7:3 Reserved */ | |
85 | u16 fldbcount:2; /* 9:8 Flash Data Byte Count */ | |
86 | u16 flockdn:6; /* 15:10 Reserved */ | |
87 | } hsf_ctrl; | |
88 | u16 regval; | |
89 | }; | |
90 | ||
91 | /* ICH Flash Region Access Permissions */ | |
92 | union ich8_hws_flash_regacc { | |
93 | struct ich8_flracc { | |
94 | u32 grra:8; /* 0:7 GbE region Read Access */ | |
95 | u32 grwa:8; /* 8:15 GbE region Write Access */ | |
96 | u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */ | |
97 | u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */ | |
98 | } hsf_flregacc; | |
99 | u16 regval; | |
100 | }; | |
101 | ||
102 | /* ICH Flash Protected Region */ | |
103 | union ich8_flash_protected_range { | |
104 | struct ich8_pr { | |
105 | u32 base:13; /* 0:12 Protected Range Base */ | |
106 | u32 reserved1:2; /* 13:14 Reserved */ | |
107 | u32 rpe:1; /* 15 Read Protection Enable */ | |
108 | u32 limit:13; /* 16:28 Protected Range Limit */ | |
109 | u32 reserved2:2; /* 29:30 Reserved */ | |
110 | u32 wpe:1; /* 31 Write Protection Enable */ | |
111 | } range; | |
112 | u32 regval; | |
113 | }; | |
114 | ||
115 | static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw); | |
116 | static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw); | |
117 | static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank); | |
118 | static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, | |
119 | u32 offset, u8 byte); | |
120 | static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, | |
121 | u8 *data); | |
122 | static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, | |
123 | u16 *data); | |
124 | static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, | |
125 | u8 size, u16 *data); | |
126 | static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw); | |
127 | static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw); | |
128 | static s32 e1000_led_on_ich8lan(struct e1000_hw *hw); | |
129 | static s32 e1000_led_off_ich8lan(struct e1000_hw *hw); | |
130 | static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw); | |
131 | static s32 e1000_setup_led_pchlan(struct e1000_hw *hw); | |
132 | static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw); | |
133 | static s32 e1000_led_on_pchlan(struct e1000_hw *hw); | |
134 | static s32 e1000_led_off_pchlan(struct e1000_hw *hw); | |
135 | static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active); | |
136 | static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw); | |
137 | static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw); | |
138 | static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link); | |
139 | static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw); | |
140 | static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw); | |
141 | static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw); | |
142 | static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index); | |
143 | static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index); | |
144 | static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw); | |
145 | static s32 e1000_k1_workaround_lv(struct e1000_hw *hw); | |
146 | static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate); | |
147 | static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force); | |
148 | static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw); | |
149 | static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state); | |
150 | ||
151 | static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg) | |
152 | { | |
153 | return readw(hw->flash_address + reg); | |
154 | } | |
155 | ||
156 | static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg) | |
157 | { | |
158 | return readl(hw->flash_address + reg); | |
159 | } | |
160 | ||
161 | static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val) | |
162 | { | |
163 | writew(val, hw->flash_address + reg); | |
164 | } | |
165 | ||
166 | static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val) | |
167 | { | |
168 | writel(val, hw->flash_address + reg); | |
169 | } | |
170 | ||
171 | #define er16flash(reg) __er16flash(hw, (reg)) | |
172 | #define er32flash(reg) __er32flash(hw, (reg)) | |
173 | #define ew16flash(reg, val) __ew16flash(hw, (reg), (val)) | |
174 | #define ew32flash(reg, val) __ew32flash(hw, (reg), (val)) | |
175 | ||
176 | /** | |
177 | * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers | |
178 | * @hw: pointer to the HW structure | |
179 | * | |
180 | * Test access to the PHY registers by reading the PHY ID registers. If | |
181 | * the PHY ID is already known (e.g. resume path) compare it with known ID, | |
182 | * otherwise assume the read PHY ID is correct if it is valid. | |
183 | * | |
184 | * Assumes the sw/fw/hw semaphore is already acquired. | |
185 | **/ | |
186 | static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw) | |
187 | { | |
188 | u16 phy_reg = 0; | |
189 | u32 phy_id = 0; | |
190 | s32 ret_val = 0; | |
191 | u16 retry_count; | |
192 | u32 mac_reg = 0; | |
193 | ||
194 | for (retry_count = 0; retry_count < 2; retry_count++) { | |
195 | ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg); | |
196 | if (ret_val || (phy_reg == 0xFFFF)) | |
197 | continue; | |
198 | phy_id = (u32)(phy_reg << 16); | |
199 | ||
200 | ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg); | |
201 | if (ret_val || (phy_reg == 0xFFFF)) { | |
202 | phy_id = 0; | |
203 | continue; | |
204 | } | |
205 | phy_id |= (u32)(phy_reg & PHY_REVISION_MASK); | |
206 | break; | |
207 | } | |
208 | ||
209 | if (hw->phy.id) { | |
210 | if (hw->phy.id == phy_id) | |
211 | goto out; | |
212 | } else if (phy_id) { | |
213 | hw->phy.id = phy_id; | |
214 | hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK); | |
215 | goto out; | |
216 | } | |
217 | ||
218 | /* In case the PHY needs to be in mdio slow mode, | |
219 | * set slow mode and try to get the PHY id again. | |
220 | */ | |
221 | if (hw->mac.type < e1000_pch_lpt) { | |
222 | hw->phy.ops.release(hw); | |
223 | ret_val = e1000_set_mdio_slow_mode_hv(hw); | |
224 | if (!ret_val) | |
225 | ret_val = e1000e_get_phy_id(hw); | |
226 | hw->phy.ops.acquire(hw); | |
227 | } | |
228 | ||
229 | if (ret_val) | |
230 | return false; | |
231 | out: | |
232 | if (hw->mac.type == e1000_pch_lpt) { | |
233 | /* Unforce SMBus mode in PHY */ | |
234 | e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg); | |
235 | phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS; | |
236 | e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg); | |
237 | ||
238 | /* Unforce SMBus mode in MAC */ | |
239 | mac_reg = er32(CTRL_EXT); | |
240 | mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; | |
241 | ew32(CTRL_EXT, mac_reg); | |
242 | } | |
243 | ||
244 | return true; | |
245 | } | |
246 | ||
247 | /** | |
248 | * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value | |
249 | * @hw: pointer to the HW structure | |
250 | * | |
251 | * Toggling the LANPHYPC pin value fully power-cycles the PHY and is | |
252 | * used to reset the PHY to a quiescent state when necessary. | |
253 | **/ | |
254 | static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw) | |
255 | { | |
256 | u32 mac_reg; | |
257 | ||
258 | /* Set Phy Config Counter to 50msec */ | |
259 | mac_reg = er32(FEXTNVM3); | |
260 | mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK; | |
261 | mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; | |
262 | ew32(FEXTNVM3, mac_reg); | |
263 | ||
264 | /* Toggle LANPHYPC Value bit */ | |
265 | mac_reg = er32(CTRL); | |
266 | mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE; | |
267 | mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE; | |
268 | ew32(CTRL, mac_reg); | |
269 | e1e_flush(); | |
270 | usleep_range(10, 20); | |
271 | mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE; | |
272 | ew32(CTRL, mac_reg); | |
273 | e1e_flush(); | |
274 | ||
275 | if (hw->mac.type < e1000_pch_lpt) { | |
276 | msleep(50); | |
277 | } else { | |
278 | u16 count = 20; | |
279 | ||
280 | do { | |
281 | usleep_range(5000, 10000); | |
282 | } while (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LPCD) && count--); | |
283 | ||
284 | msleep(30); | |
285 | } | |
286 | } | |
287 | ||
288 | /** | |
289 | * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds | |
290 | * @hw: pointer to the HW structure | |
291 | * | |
292 | * Workarounds/flow necessary for PHY initialization during driver load | |
293 | * and resume paths. | |
294 | **/ | |
295 | static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw) | |
296 | { | |
297 | struct e1000_adapter *adapter = hw->adapter; | |
298 | u32 mac_reg, fwsm = er32(FWSM); | |
299 | s32 ret_val; | |
300 | ||
301 | /* Gate automatic PHY configuration by hardware on managed and | |
302 | * non-managed 82579 and newer adapters. | |
303 | */ | |
304 | e1000_gate_hw_phy_config_ich8lan(hw, true); | |
305 | ||
306 | /* It is not possible to be certain of the current state of ULP | |
307 | * so forcibly disable it. | |
308 | */ | |
309 | hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown; | |
310 | e1000_disable_ulp_lpt_lp(hw, true); | |
311 | ||
312 | ret_val = hw->phy.ops.acquire(hw); | |
313 | if (ret_val) { | |
314 | e_dbg("Failed to initialize PHY flow\n"); | |
315 | goto out; | |
316 | } | |
317 | ||
318 | /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is | |
319 | * inaccessible and resetting the PHY is not blocked, toggle the | |
320 | * LANPHYPC Value bit to force the interconnect to PCIe mode. | |
321 | */ | |
322 | switch (hw->mac.type) { | |
323 | case e1000_pch_lpt: | |
324 | if (e1000_phy_is_accessible_pchlan(hw)) | |
325 | break; | |
326 | ||
327 | /* Before toggling LANPHYPC, see if PHY is accessible by | |
328 | * forcing MAC to SMBus mode first. | |
329 | */ | |
330 | mac_reg = er32(CTRL_EXT); | |
331 | mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; | |
332 | ew32(CTRL_EXT, mac_reg); | |
333 | ||
334 | /* Wait 50 milliseconds for MAC to finish any retries | |
335 | * that it might be trying to perform from previous | |
336 | * attempts to acknowledge any phy read requests. | |
337 | */ | |
338 | msleep(50); | |
339 | ||
340 | /* fall-through */ | |
341 | case e1000_pch2lan: | |
342 | if (e1000_phy_is_accessible_pchlan(hw)) | |
343 | break; | |
344 | ||
345 | /* fall-through */ | |
346 | case e1000_pchlan: | |
347 | if ((hw->mac.type == e1000_pchlan) && | |
348 | (fwsm & E1000_ICH_FWSM_FW_VALID)) | |
349 | break; | |
350 | ||
351 | if (hw->phy.ops.check_reset_block(hw)) { | |
352 | e_dbg("Required LANPHYPC toggle blocked by ME\n"); | |
353 | ret_val = -E1000_ERR_PHY; | |
354 | break; | |
355 | } | |
356 | ||
357 | /* Toggle LANPHYPC Value bit */ | |
358 | e1000_toggle_lanphypc_pch_lpt(hw); | |
359 | if (hw->mac.type >= e1000_pch_lpt) { | |
360 | if (e1000_phy_is_accessible_pchlan(hw)) | |
361 | break; | |
362 | ||
363 | /* Toggling LANPHYPC brings the PHY out of SMBus mode | |
364 | * so ensure that the MAC is also out of SMBus mode | |
365 | */ | |
366 | mac_reg = er32(CTRL_EXT); | |
367 | mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; | |
368 | ew32(CTRL_EXT, mac_reg); | |
369 | ||
370 | if (e1000_phy_is_accessible_pchlan(hw)) | |
371 | break; | |
372 | ||
373 | ret_val = -E1000_ERR_PHY; | |
374 | } | |
375 | break; | |
376 | default: | |
377 | break; | |
378 | } | |
379 | ||
380 | hw->phy.ops.release(hw); | |
381 | if (!ret_val) { | |
382 | ||
383 | /* Check to see if able to reset PHY. Print error if not */ | |
384 | if (hw->phy.ops.check_reset_block(hw)) { | |
385 | e_err("Reset blocked by ME\n"); | |
386 | goto out; | |
387 | } | |
388 | ||
389 | /* Reset the PHY before any access to it. Doing so, ensures | |
390 | * that the PHY is in a known good state before we read/write | |
391 | * PHY registers. The generic reset is sufficient here, | |
392 | * because we haven't determined the PHY type yet. | |
393 | */ | |
394 | ret_val = e1000e_phy_hw_reset_generic(hw); | |
395 | if (ret_val) | |
396 | goto out; | |
397 | ||
398 | /* On a successful reset, possibly need to wait for the PHY | |
399 | * to quiesce to an accessible state before returning control | |
400 | * to the calling function. If the PHY does not quiesce, then | |
401 | * return E1000E_BLK_PHY_RESET, as this is the condition that | |
402 | * the PHY is in. | |
403 | */ | |
404 | ret_val = hw->phy.ops.check_reset_block(hw); | |
405 | if (ret_val) | |
406 | e_err("ME blocked access to PHY after reset\n"); | |
407 | } | |
408 | ||
409 | out: | |
410 | /* Ungate automatic PHY configuration on non-managed 82579 */ | |
411 | if ((hw->mac.type == e1000_pch2lan) && | |
412 | !(fwsm & E1000_ICH_FWSM_FW_VALID)) { | |
413 | usleep_range(10000, 20000); | |
414 | e1000_gate_hw_phy_config_ich8lan(hw, false); | |
415 | } | |
416 | ||
417 | return ret_val; | |
418 | } | |
419 | ||
420 | /** | |
421 | * e1000_init_phy_params_pchlan - Initialize PHY function pointers | |
422 | * @hw: pointer to the HW structure | |
423 | * | |
424 | * Initialize family-specific PHY parameters and function pointers. | |
425 | **/ | |
426 | static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw) | |
427 | { | |
428 | struct e1000_phy_info *phy = &hw->phy; | |
429 | s32 ret_val; | |
430 | ||
431 | phy->addr = 1; | |
432 | phy->reset_delay_us = 100; | |
433 | ||
434 | phy->ops.set_page = e1000_set_page_igp; | |
435 | phy->ops.read_reg = e1000_read_phy_reg_hv; | |
436 | phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked; | |
437 | phy->ops.read_reg_page = e1000_read_phy_reg_page_hv; | |
438 | phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan; | |
439 | phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan; | |
440 | phy->ops.write_reg = e1000_write_phy_reg_hv; | |
441 | phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked; | |
442 | phy->ops.write_reg_page = e1000_write_phy_reg_page_hv; | |
443 | phy->ops.power_up = e1000_power_up_phy_copper; | |
444 | phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; | |
445 | phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; | |
446 | ||
447 | phy->id = e1000_phy_unknown; | |
448 | ||
449 | ret_val = e1000_init_phy_workarounds_pchlan(hw); | |
450 | if (ret_val) | |
451 | return ret_val; | |
452 | ||
453 | if (phy->id == e1000_phy_unknown) | |
454 | switch (hw->mac.type) { | |
455 | default: | |
456 | ret_val = e1000e_get_phy_id(hw); | |
457 | if (ret_val) | |
458 | return ret_val; | |
459 | if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK)) | |
460 | break; | |
461 | /* fall-through */ | |
462 | case e1000_pch2lan: | |
463 | case e1000_pch_lpt: | |
464 | /* In case the PHY needs to be in mdio slow mode, | |
465 | * set slow mode and try to get the PHY id again. | |
466 | */ | |
467 | ret_val = e1000_set_mdio_slow_mode_hv(hw); | |
468 | if (ret_val) | |
469 | return ret_val; | |
470 | ret_val = e1000e_get_phy_id(hw); | |
471 | if (ret_val) | |
472 | return ret_val; | |
473 | break; | |
474 | } | |
475 | phy->type = e1000e_get_phy_type_from_id(phy->id); | |
476 | ||
477 | switch (phy->type) { | |
478 | case e1000_phy_82577: | |
479 | case e1000_phy_82579: | |
480 | case e1000_phy_i217: | |
481 | phy->ops.check_polarity = e1000_check_polarity_82577; | |
482 | phy->ops.force_speed_duplex = | |
483 | e1000_phy_force_speed_duplex_82577; | |
484 | phy->ops.get_cable_length = e1000_get_cable_length_82577; | |
485 | phy->ops.get_info = e1000_get_phy_info_82577; | |
486 | phy->ops.commit = e1000e_phy_sw_reset; | |
487 | break; | |
488 | case e1000_phy_82578: | |
489 | phy->ops.check_polarity = e1000_check_polarity_m88; | |
490 | phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88; | |
491 | phy->ops.get_cable_length = e1000e_get_cable_length_m88; | |
492 | phy->ops.get_info = e1000e_get_phy_info_m88; | |
493 | break; | |
494 | default: | |
495 | ret_val = -E1000_ERR_PHY; | |
496 | break; | |
497 | } | |
498 | ||
499 | return ret_val; | |
500 | } | |
501 | ||
502 | /** | |
503 | * e1000_init_phy_params_ich8lan - Initialize PHY function pointers | |
504 | * @hw: pointer to the HW structure | |
505 | * | |
506 | * Initialize family-specific PHY parameters and function pointers. | |
507 | **/ | |
508 | static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) | |
509 | { | |
510 | struct e1000_phy_info *phy = &hw->phy; | |
511 | s32 ret_val; | |
512 | u16 i = 0; | |
513 | ||
514 | phy->addr = 1; | |
515 | phy->reset_delay_us = 100; | |
516 | ||
517 | phy->ops.power_up = e1000_power_up_phy_copper; | |
518 | phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; | |
519 | ||
520 | /* We may need to do this twice - once for IGP and if that fails, | |
521 | * we'll set BM func pointers and try again | |
522 | */ | |
523 | ret_val = e1000e_determine_phy_address(hw); | |
524 | if (ret_val) { | |
525 | phy->ops.write_reg = e1000e_write_phy_reg_bm; | |
526 | phy->ops.read_reg = e1000e_read_phy_reg_bm; | |
527 | ret_val = e1000e_determine_phy_address(hw); | |
528 | if (ret_val) { | |
529 | e_dbg("Cannot determine PHY addr. Erroring out\n"); | |
530 | return ret_val; | |
531 | } | |
532 | } | |
533 | ||
534 | phy->id = 0; | |
535 | while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) && | |
536 | (i++ < 100)) { | |
537 | usleep_range(1000, 2000); | |
538 | ret_val = e1000e_get_phy_id(hw); | |
539 | if (ret_val) | |
540 | return ret_val; | |
541 | } | |
542 | ||
543 | /* Verify phy id */ | |
544 | switch (phy->id) { | |
545 | case IGP03E1000_E_PHY_ID: | |
546 | phy->type = e1000_phy_igp_3; | |
547 | phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; | |
548 | phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked; | |
549 | phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked; | |
550 | phy->ops.get_info = e1000e_get_phy_info_igp; | |
551 | phy->ops.check_polarity = e1000_check_polarity_igp; | |
552 | phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp; | |
553 | break; | |
554 | case IFE_E_PHY_ID: | |
555 | case IFE_PLUS_E_PHY_ID: | |
556 | case IFE_C_E_PHY_ID: | |
557 | phy->type = e1000_phy_ife; | |
558 | phy->autoneg_mask = E1000_ALL_NOT_GIG; | |
559 | phy->ops.get_info = e1000_get_phy_info_ife; | |
560 | phy->ops.check_polarity = e1000_check_polarity_ife; | |
561 | phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife; | |
562 | break; | |
563 | case BME1000_E_PHY_ID: | |
564 | phy->type = e1000_phy_bm; | |
565 | phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; | |
566 | phy->ops.read_reg = e1000e_read_phy_reg_bm; | |
567 | phy->ops.write_reg = e1000e_write_phy_reg_bm; | |
568 | phy->ops.commit = e1000e_phy_sw_reset; | |
569 | phy->ops.get_info = e1000e_get_phy_info_m88; | |
570 | phy->ops.check_polarity = e1000_check_polarity_m88; | |
571 | phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88; | |
572 | break; | |
573 | default: | |
574 | return -E1000_ERR_PHY; | |
575 | } | |
576 | ||
577 | return 0; | |
578 | } | |
579 | ||
580 | /** | |
581 | * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers | |
582 | * @hw: pointer to the HW structure | |
583 | * | |
584 | * Initialize family-specific NVM parameters and function | |
585 | * pointers. | |
586 | **/ | |
587 | static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) | |
588 | { | |
589 | struct e1000_nvm_info *nvm = &hw->nvm; | |
590 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; | |
591 | u32 gfpreg, sector_base_addr, sector_end_addr; | |
592 | u16 i; | |
593 | ||
594 | /* Can't read flash registers if the register set isn't mapped. */ | |
595 | if (!hw->flash_address) { | |
596 | e_dbg("ERROR: Flash registers not mapped\n"); | |
597 | return -E1000_ERR_CONFIG; | |
598 | } | |
599 | ||
600 | nvm->type = e1000_nvm_flash_sw; | |
601 | ||
602 | gfpreg = er32flash(ICH_FLASH_GFPREG); | |
603 | ||
604 | /* sector_X_addr is a "sector"-aligned address (4096 bytes) | |
605 | * Add 1 to sector_end_addr since this sector is included in | |
606 | * the overall size. | |
607 | */ | |
608 | sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK; | |
609 | sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1; | |
610 | ||
611 | /* flash_base_addr is byte-aligned */ | |
612 | nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT; | |
613 | ||
614 | /* find total size of the NVM, then cut in half since the total | |
615 | * size represents two separate NVM banks. | |
616 | */ | |
617 | nvm->flash_bank_size = ((sector_end_addr - sector_base_addr) | |
618 | << FLASH_SECTOR_ADDR_SHIFT); | |
619 | nvm->flash_bank_size /= 2; | |
620 | /* Adjust to word count */ | |
621 | nvm->flash_bank_size /= sizeof(u16); | |
622 | ||
623 | nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS; | |
624 | ||
625 | /* Clear shadow ram */ | |
626 | for (i = 0; i < nvm->word_size; i++) { | |
627 | dev_spec->shadow_ram[i].modified = false; | |
628 | dev_spec->shadow_ram[i].value = 0xFFFF; | |
629 | } | |
630 | ||
631 | return 0; | |
632 | } | |
633 | ||
634 | /** | |
635 | * e1000_init_mac_params_ich8lan - Initialize MAC function pointers | |
636 | * @hw: pointer to the HW structure | |
637 | * | |
638 | * Initialize family-specific MAC parameters and function | |
639 | * pointers. | |
640 | **/ | |
641 | static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw) | |
642 | { | |
643 | struct e1000_mac_info *mac = &hw->mac; | |
644 | ||
645 | /* Set media type function pointer */ | |
646 | hw->phy.media_type = e1000_media_type_copper; | |
647 | ||
648 | /* Set mta register count */ | |
649 | mac->mta_reg_count = 32; | |
650 | /* Set rar entry count */ | |
651 | mac->rar_entry_count = E1000_ICH_RAR_ENTRIES; | |
652 | if (mac->type == e1000_ich8lan) | |
653 | mac->rar_entry_count--; | |
654 | /* FWSM register */ | |
655 | mac->has_fwsm = true; | |
656 | /* ARC subsystem not supported */ | |
657 | mac->arc_subsystem_valid = false; | |
658 | /* Adaptive IFS supported */ | |
659 | mac->adaptive_ifs = true; | |
660 | ||
661 | /* LED and other operations */ | |
662 | switch (mac->type) { | |
663 | case e1000_ich8lan: | |
664 | case e1000_ich9lan: | |
665 | case e1000_ich10lan: | |
666 | /* check management mode */ | |
667 | mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan; | |
668 | /* ID LED init */ | |
669 | mac->ops.id_led_init = e1000e_id_led_init_generic; | |
670 | /* blink LED */ | |
671 | mac->ops.blink_led = e1000e_blink_led_generic; | |
672 | /* setup LED */ | |
673 | mac->ops.setup_led = e1000e_setup_led_generic; | |
674 | /* cleanup LED */ | |
675 | mac->ops.cleanup_led = e1000_cleanup_led_ich8lan; | |
676 | /* turn on/off LED */ | |
677 | mac->ops.led_on = e1000_led_on_ich8lan; | |
678 | mac->ops.led_off = e1000_led_off_ich8lan; | |
679 | break; | |
680 | case e1000_pch2lan: | |
681 | mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES; | |
682 | mac->ops.rar_set = e1000_rar_set_pch2lan; | |
683 | /* fall-through */ | |
684 | case e1000_pch_lpt: | |
685 | case e1000_pchlan: | |
686 | /* check management mode */ | |
687 | mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan; | |
688 | /* ID LED init */ | |
689 | mac->ops.id_led_init = e1000_id_led_init_pchlan; | |
690 | /* setup LED */ | |
691 | mac->ops.setup_led = e1000_setup_led_pchlan; | |
692 | /* cleanup LED */ | |
693 | mac->ops.cleanup_led = e1000_cleanup_led_pchlan; | |
694 | /* turn on/off LED */ | |
695 | mac->ops.led_on = e1000_led_on_pchlan; | |
696 | mac->ops.led_off = e1000_led_off_pchlan; | |
697 | break; | |
698 | default: | |
699 | break; | |
700 | } | |
701 | ||
702 | if (mac->type == e1000_pch_lpt) { | |
703 | mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES; | |
704 | mac->ops.rar_set = e1000_rar_set_pch_lpt; | |
705 | mac->ops.setup_physical_interface = | |
706 | e1000_setup_copper_link_pch_lpt; | |
707 | mac->ops.rar_get_count = e1000_rar_get_count_pch_lpt; | |
708 | } | |
709 | ||
710 | /* Enable PCS Lock-loss workaround for ICH8 */ | |
711 | if (mac->type == e1000_ich8lan) | |
712 | e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true); | |
713 | ||
714 | return 0; | |
715 | } | |
716 | ||
717 | /** | |
718 | * __e1000_access_emi_reg_locked - Read/write EMI register | |
719 | * @hw: pointer to the HW structure | |
720 | * @addr: EMI address to program | |
721 | * @data: pointer to value to read/write from/to the EMI address | |
722 | * @read: boolean flag to indicate read or write | |
723 | * | |
724 | * This helper function assumes the SW/FW/HW Semaphore is already acquired. | |
725 | **/ | |
726 | static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address, | |
727 | u16 *data, bool read) | |
728 | { | |
729 | s32 ret_val; | |
730 | ||
731 | ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address); | |
732 | if (ret_val) | |
733 | return ret_val; | |
734 | ||
735 | if (read) | |
736 | ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data); | |
737 | else | |
738 | ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data); | |
739 | ||
740 | return ret_val; | |
741 | } | |
742 | ||
743 | /** | |
744 | * e1000_read_emi_reg_locked - Read Extended Management Interface register | |
745 | * @hw: pointer to the HW structure | |
746 | * @addr: EMI address to program | |
747 | * @data: value to be read from the EMI address | |
748 | * | |
749 | * Assumes the SW/FW/HW Semaphore is already acquired. | |
750 | **/ | |
751 | s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data) | |
752 | { | |
753 | return __e1000_access_emi_reg_locked(hw, addr, data, true); | |
754 | } | |
755 | ||
756 | /** | |
757 | * e1000_write_emi_reg_locked - Write Extended Management Interface register | |
758 | * @hw: pointer to the HW structure | |
759 | * @addr: EMI address to program | |
760 | * @data: value to be written to the EMI address | |
761 | * | |
762 | * Assumes the SW/FW/HW Semaphore is already acquired. | |
763 | **/ | |
764 | s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data) | |
765 | { | |
766 | return __e1000_access_emi_reg_locked(hw, addr, &data, false); | |
767 | } | |
768 | ||
769 | /** | |
770 | * e1000_set_eee_pchlan - Enable/disable EEE support | |
771 | * @hw: pointer to the HW structure | |
772 | * | |
773 | * Enable/disable EEE based on setting in dev_spec structure, the duplex of | |
774 | * the link and the EEE capabilities of the link partner. The LPI Control | |
775 | * register bits will remain set only if/when link is up. | |
776 | * | |
777 | * EEE LPI must not be asserted earlier than one second after link is up. | |
778 | * On 82579, EEE LPI should not be enabled until such time otherwise there | |
779 | * can be link issues with some switches. Other devices can have EEE LPI | |
780 | * enabled immediately upon link up since they have a timer in hardware which | |
781 | * prevents LPI from being asserted too early. | |
782 | **/ | |
783 | s32 e1000_set_eee_pchlan(struct e1000_hw *hw) | |
784 | { | |
785 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; | |
786 | s32 ret_val; | |
787 | u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data; | |
788 | ||
789 | switch (hw->phy.type) { | |
790 | case e1000_phy_82579: | |
791 | lpa = I82579_EEE_LP_ABILITY; | |
792 | pcs_status = I82579_EEE_PCS_STATUS; | |
793 | adv_addr = I82579_EEE_ADVERTISEMENT; | |
794 | break; | |
795 | case e1000_phy_i217: | |
796 | lpa = I217_EEE_LP_ABILITY; | |
797 | pcs_status = I217_EEE_PCS_STATUS; | |
798 | adv_addr = I217_EEE_ADVERTISEMENT; | |
799 | break; | |
800 | default: | |
801 | return 0; | |
802 | } | |
803 | ||
804 | ret_val = hw->phy.ops.acquire(hw); | |
805 | if (ret_val) | |
806 | return ret_val; | |
807 | ||
808 | ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl); | |
809 | if (ret_val) | |
810 | goto release; | |
811 | ||
812 | /* Clear bits that enable EEE in various speeds */ | |
813 | lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK; | |
814 | ||
815 | /* Enable EEE if not disabled by user */ | |
816 | if (!dev_spec->eee_disable) { | |
817 | /* Save off link partner's EEE ability */ | |
818 | ret_val = e1000_read_emi_reg_locked(hw, lpa, | |
819 | &dev_spec->eee_lp_ability); | |
820 | if (ret_val) | |
821 | goto release; | |
822 | ||
823 | /* Read EEE advertisement */ | |
824 | ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv); | |
825 | if (ret_val) | |
826 | goto release; | |
827 | ||
828 | /* Enable EEE only for speeds in which the link partner is | |
829 | * EEE capable and for which we advertise EEE. | |
830 | */ | |
831 | if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED) | |
832 | lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE; | |
833 | ||
834 | if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) { | |
835 | e1e_rphy_locked(hw, MII_LPA, &data); | |
836 | if (data & LPA_100FULL) | |
837 | lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE; | |
838 | else | |
839 | /* EEE is not supported in 100Half, so ignore | |
840 | * partner's EEE in 100 ability if full-duplex | |
841 | * is not advertised. | |
842 | */ | |
843 | dev_spec->eee_lp_ability &= | |
844 | ~I82579_EEE_100_SUPPORTED; | |
845 | } | |
846 | } | |
847 | ||
848 | if (hw->phy.type == e1000_phy_82579) { | |
849 | ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT, | |
850 | &data); | |
851 | if (ret_val) | |
852 | goto release; | |
853 | ||
854 | data &= ~I82579_LPI_100_PLL_SHUT; | |
855 | ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT, | |
856 | data); | |
857 | } | |
858 | ||
859 | /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */ | |
860 | ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data); | |
861 | if (ret_val) | |
862 | goto release; | |
863 | ||
864 | ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl); | |
865 | release: | |
866 | hw->phy.ops.release(hw); | |
867 | ||
868 | return ret_val; | |
869 | } | |
870 | ||
871 | /** | |
872 | * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP | |
873 | * @hw: pointer to the HW structure | |
874 | * @link: link up bool flag | |
875 | * | |
876 | * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications | |
877 | * preventing further DMA write requests. Workaround the issue by disabling | |
878 | * the de-assertion of the clock request when in 1Gpbs mode. | |
879 | * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link | |
880 | * speeds in order to avoid Tx hangs. | |
881 | **/ | |
882 | static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link) | |
883 | { | |
884 | u32 fextnvm6 = er32(FEXTNVM6); | |
885 | u32 status = er32(STATUS); | |
886 | s32 ret_val = 0; | |
887 | u16 reg; | |
888 | ||
889 | if (link && (status & E1000_STATUS_SPEED_1000)) { | |
890 | ret_val = hw->phy.ops.acquire(hw); | |
891 | if (ret_val) | |
892 | return ret_val; | |
893 | ||
894 | ret_val = | |
895 | e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, | |
896 | ®); | |
897 | if (ret_val) | |
898 | goto release; | |
899 | ||
900 | ret_val = | |
901 | e1000e_write_kmrn_reg_locked(hw, | |
902 | E1000_KMRNCTRLSTA_K1_CONFIG, | |
903 | reg & | |
904 | ~E1000_KMRNCTRLSTA_K1_ENABLE); | |
905 | if (ret_val) | |
906 | goto release; | |
907 | ||
908 | usleep_range(10, 20); | |
909 | ||
910 | ew32(FEXTNVM6, fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK); | |
911 | ||
912 | ret_val = | |
913 | e1000e_write_kmrn_reg_locked(hw, | |
914 | E1000_KMRNCTRLSTA_K1_CONFIG, | |
915 | reg); | |
916 | release: | |
917 | hw->phy.ops.release(hw); | |
918 | } else { | |
919 | /* clear FEXTNVM6 bit 8 on link down or 10/100 */ | |
920 | fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK; | |
921 | ||
922 | if (!link || ((status & E1000_STATUS_SPEED_100) && | |
923 | (status & E1000_STATUS_FD))) | |
924 | goto update_fextnvm6; | |
925 | ||
926 | ret_val = e1e_rphy(hw, I217_INBAND_CTRL, ®); | |
927 | if (ret_val) | |
928 | return ret_val; | |
929 | ||
930 | /* Clear link status transmit timeout */ | |
931 | reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK; | |
932 | ||
933 | if (status & E1000_STATUS_SPEED_100) { | |
934 | /* Set inband Tx timeout to 5x10us for 100Half */ | |
935 | reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT; | |
936 | ||
937 | /* Do not extend the K1 entry latency for 100Half */ | |
938 | fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION; | |
939 | } else { | |
940 | /* Set inband Tx timeout to 50x10us for 10Full/Half */ | |
941 | reg |= 50 << | |
942 | I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT; | |
943 | ||
944 | /* Extend the K1 entry latency for 10 Mbps */ | |
945 | fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION; | |
946 | } | |
947 | ||
948 | ret_val = e1e_wphy(hw, I217_INBAND_CTRL, reg); | |
949 | if (ret_val) | |
950 | return ret_val; | |
951 | ||
952 | update_fextnvm6: | |
953 | ew32(FEXTNVM6, fextnvm6); | |
954 | } | |
955 | ||
956 | return ret_val; | |
957 | } | |
958 | ||
959 | /** | |
960 | * e1000_platform_pm_pch_lpt - Set platform power management values | |
961 | * @hw: pointer to the HW structure | |
962 | * @link: bool indicating link status | |
963 | * | |
964 | * Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like" | |
965 | * GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed | |
966 | * when link is up (which must not exceed the maximum latency supported | |
967 | * by the platform), otherwise specify there is no LTR requirement. | |
968 | * Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop | |
969 | * latencies in the LTR Extended Capability Structure in the PCIe Extended | |
970 | * Capability register set, on this device LTR is set by writing the | |
971 | * equivalent snoop/no-snoop latencies in the LTRV register in the MAC and | |
972 | * set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB) | |
973 | * message to the PMC. | |
974 | **/ | |
975 | static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link) | |
976 | { | |
977 | u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) | | |
978 | link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND; | |
979 | u16 lat_enc = 0; /* latency encoded */ | |
980 | ||
981 | if (link) { | |
982 | u16 speed, duplex, scale = 0; | |
983 | u16 max_snoop, max_nosnoop; | |
984 | u16 max_ltr_enc; /* max LTR latency encoded */ | |
985 | s64 lat_ns; /* latency (ns) */ | |
986 | s64 value; | |
987 | u32 rxa; | |
988 | ||
989 | if (!hw->adapter->max_frame_size) { | |
990 | e_dbg("max_frame_size not set.\n"); | |
991 | return -E1000_ERR_CONFIG; | |
992 | } | |
993 | ||
994 | hw->mac.ops.get_link_up_info(hw, &speed, &duplex); | |
995 | if (!speed) { | |
996 | e_dbg("Speed not set.\n"); | |
997 | return -E1000_ERR_CONFIG; | |
998 | } | |
999 | ||
1000 | /* Rx Packet Buffer Allocation size (KB) */ | |
1001 | rxa = er32(PBA) & E1000_PBA_RXA_MASK; | |
1002 | ||
1003 | /* Determine the maximum latency tolerated by the device. | |
1004 | * | |
1005 | * Per the PCIe spec, the tolerated latencies are encoded as | |
1006 | * a 3-bit encoded scale (only 0-5 are valid) multiplied by | |
1007 | * a 10-bit value (0-1023) to provide a range from 1 ns to | |
1008 | * 2^25*(2^10-1) ns. The scale is encoded as 0=2^0ns, | |
1009 | * 1=2^5ns, 2=2^10ns,...5=2^25ns. | |
1010 | */ | |
1011 | lat_ns = ((s64)rxa * 1024 - | |
1012 | (2 * (s64)hw->adapter->max_frame_size)) * 8 * 1000; | |
1013 | if (lat_ns < 0) | |
1014 | lat_ns = 0; | |
1015 | else | |
1016 | do_div(lat_ns, speed); | |
1017 | ||
1018 | value = lat_ns; | |
1019 | while (value > PCI_LTR_VALUE_MASK) { | |
1020 | scale++; | |
1021 | value = DIV_ROUND_UP(value, (1 << 5)); | |
1022 | } | |
1023 | if (scale > E1000_LTRV_SCALE_MAX) { | |
1024 | e_dbg("Invalid LTR latency scale %d\n", scale); | |
1025 | return -E1000_ERR_CONFIG; | |
1026 | } | |
1027 | lat_enc = (u16)((scale << PCI_LTR_SCALE_SHIFT) | value); | |
1028 | ||
1029 | /* Determine the maximum latency tolerated by the platform */ | |
1030 | pci_read_config_word(hw->adapter->pdev, E1000_PCI_LTR_CAP_LPT, | |
1031 | &max_snoop); | |
1032 | pci_read_config_word(hw->adapter->pdev, | |
1033 | E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop); | |
1034 | max_ltr_enc = max_t(u16, max_snoop, max_nosnoop); | |
1035 | ||
1036 | if (lat_enc > max_ltr_enc) | |
1037 | lat_enc = max_ltr_enc; | |
1038 | } | |
1039 | ||
1040 | /* Set Snoop and No-Snoop latencies the same */ | |
1041 | reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT); | |
1042 | ew32(LTRV, reg); | |
1043 | ||
1044 | return 0; | |
1045 | } | |
1046 | ||
1047 | /** | |
1048 | * e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP | |
1049 | * @hw: pointer to the HW structure | |
1050 | * @to_sx: boolean indicating a system power state transition to Sx | |
1051 | * | |
1052 | * When link is down, configure ULP mode to significantly reduce the power | |
1053 | * to the PHY. If on a Manageability Engine (ME) enabled system, tell the | |
1054 | * ME firmware to start the ULP configuration. If not on an ME enabled | |
1055 | * system, configure the ULP mode by software. | |
1056 | */ | |
1057 | s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx) | |
1058 | { | |
1059 | u32 mac_reg; | |
1060 | s32 ret_val = 0; | |
1061 | u16 phy_reg; | |
1062 | ||
1063 | if ((hw->mac.type < e1000_pch_lpt) || | |
1064 | (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) || | |
1065 | (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) || | |
1066 | (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) || | |
1067 | (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) || | |
1068 | (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on)) | |
1069 | return 0; | |
1070 | ||
1071 | if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) { | |
1072 | /* Request ME configure ULP mode in the PHY */ | |
1073 | mac_reg = er32(H2ME); | |
1074 | mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS; | |
1075 | ew32(H2ME, mac_reg); | |
1076 | ||
1077 | goto out; | |
1078 | } | |
1079 | ||
1080 | if (!to_sx) { | |
1081 | int i = 0; | |
1082 | ||
1083 | /* Poll up to 5 seconds for Cable Disconnected indication */ | |
1084 | while (!(er32(FEXT) & E1000_FEXT_PHY_CABLE_DISCONNECTED)) { | |
1085 | /* Bail if link is re-acquired */ | |
1086 | if (er32(STATUS) & E1000_STATUS_LU) | |
1087 | return -E1000_ERR_PHY; | |
1088 | ||
1089 | if (i++ == 100) | |
1090 | break; | |
1091 | ||
1092 | msleep(50); | |
1093 | } | |
1094 | e_dbg("CABLE_DISCONNECTED %s set after %dmsec\n", | |
1095 | (er32(FEXT) & | |
1096 | E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not", i * 50); | |
1097 | } | |
1098 | ||
1099 | ret_val = hw->phy.ops.acquire(hw); | |
1100 | if (ret_val) | |
1101 | goto out; | |
1102 | ||
1103 | /* Force SMBus mode in PHY */ | |
1104 | ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg); | |
1105 | if (ret_val) | |
1106 | goto release; | |
1107 | phy_reg |= CV_SMB_CTRL_FORCE_SMBUS; | |
1108 | e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg); | |
1109 | ||
1110 | /* Force SMBus mode in MAC */ | |
1111 | mac_reg = er32(CTRL_EXT); | |
1112 | mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; | |
1113 | ew32(CTRL_EXT, mac_reg); | |
1114 | ||
1115 | /* Set Inband ULP Exit, Reset to SMBus mode and | |
1116 | * Disable SMBus Release on PERST# in PHY | |
1117 | */ | |
1118 | ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg); | |
1119 | if (ret_val) | |
1120 | goto release; | |
1121 | phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS | | |
1122 | I218_ULP_CONFIG1_DISABLE_SMB_PERST); | |
1123 | if (to_sx) { | |
1124 | if (er32(WUFC) & E1000_WUFC_LNKC) | |
1125 | phy_reg |= I218_ULP_CONFIG1_WOL_HOST; | |
1126 | ||
1127 | phy_reg |= I218_ULP_CONFIG1_STICKY_ULP; | |
1128 | } else { | |
1129 | phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT; | |
1130 | } | |
1131 | e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); | |
1132 | ||
1133 | /* Set Disable SMBus Release on PERST# in MAC */ | |
1134 | mac_reg = er32(FEXTNVM7); | |
1135 | mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST; | |
1136 | ew32(FEXTNVM7, mac_reg); | |
1137 | ||
1138 | /* Commit ULP changes in PHY by starting auto ULP configuration */ | |
1139 | phy_reg |= I218_ULP_CONFIG1_START; | |
1140 | e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); | |
1141 | release: | |
1142 | hw->phy.ops.release(hw); | |
1143 | out: | |
1144 | if (ret_val) | |
1145 | e_dbg("Error in ULP enable flow: %d\n", ret_val); | |
1146 | else | |
1147 | hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on; | |
1148 | ||
1149 | return ret_val; | |
1150 | } | |
1151 | ||
1152 | /** | |
1153 | * e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP | |
1154 | * @hw: pointer to the HW structure | |
1155 | * @force: boolean indicating whether or not to force disabling ULP | |
1156 | * | |
1157 | * Un-configure ULP mode when link is up, the system is transitioned from | |
1158 | * Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled | |
1159 | * system, poll for an indication from ME that ULP has been un-configured. | |
1160 | * If not on an ME enabled system, un-configure the ULP mode by software. | |
1161 | * | |
1162 | * During nominal operation, this function is called when link is acquired | |
1163 | * to disable ULP mode (force=false); otherwise, for example when unloading | |
1164 | * the driver or during Sx->S0 transitions, this is called with force=true | |
1165 | * to forcibly disable ULP. | |
1166 | */ | |
1167 | static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force) | |
1168 | { | |
1169 | s32 ret_val = 0; | |
1170 | u32 mac_reg; | |
1171 | u16 phy_reg; | |
1172 | int i = 0; | |
1173 | ||
1174 | if ((hw->mac.type < e1000_pch_lpt) || | |
1175 | (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) || | |
1176 | (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) || | |
1177 | (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) || | |
1178 | (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) || | |
1179 | (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off)) | |
1180 | return 0; | |
1181 | ||
1182 | if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) { | |
1183 | if (force) { | |
1184 | /* Request ME un-configure ULP mode in the PHY */ | |
1185 | mac_reg = er32(H2ME); | |
1186 | mac_reg &= ~E1000_H2ME_ULP; | |
1187 | mac_reg |= E1000_H2ME_ENFORCE_SETTINGS; | |
1188 | ew32(H2ME, mac_reg); | |
1189 | } | |
1190 | ||
1191 | /* Poll up to 100msec for ME to clear ULP_CFG_DONE */ | |
1192 | while (er32(FWSM) & E1000_FWSM_ULP_CFG_DONE) { | |
1193 | if (i++ == 10) { | |
1194 | ret_val = -E1000_ERR_PHY; | |
1195 | goto out; | |
1196 | } | |
1197 | ||
1198 | usleep_range(10000, 20000); | |
1199 | } | |
1200 | e_dbg("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10); | |
1201 | ||
1202 | if (force) { | |
1203 | mac_reg = er32(H2ME); | |
1204 | mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS; | |
1205 | ew32(H2ME, mac_reg); | |
1206 | } else { | |
1207 | /* Clear H2ME.ULP after ME ULP configuration */ | |
1208 | mac_reg = er32(H2ME); | |
1209 | mac_reg &= ~E1000_H2ME_ULP; | |
1210 | ew32(H2ME, mac_reg); | |
1211 | } | |
1212 | ||
1213 | goto out; | |
1214 | } | |
1215 | ||
1216 | ret_val = hw->phy.ops.acquire(hw); | |
1217 | if (ret_val) | |
1218 | goto out; | |
1219 | ||
1220 | if (force) | |
1221 | /* Toggle LANPHYPC Value bit */ | |
1222 | e1000_toggle_lanphypc_pch_lpt(hw); | |
1223 | ||
1224 | /* Unforce SMBus mode in PHY */ | |
1225 | ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg); | |
1226 | if (ret_val) { | |
1227 | /* The MAC might be in PCIe mode, so temporarily force to | |
1228 | * SMBus mode in order to access the PHY. | |
1229 | */ | |
1230 | mac_reg = er32(CTRL_EXT); | |
1231 | mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; | |
1232 | ew32(CTRL_EXT, mac_reg); | |
1233 | ||
1234 | msleep(50); | |
1235 | ||
1236 | ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, | |
1237 | &phy_reg); | |
1238 | if (ret_val) | |
1239 | goto release; | |
1240 | } | |
1241 | phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS; | |
1242 | e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg); | |
1243 | ||
1244 | /* Unforce SMBus mode in MAC */ | |
1245 | mac_reg = er32(CTRL_EXT); | |
1246 | mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; | |
1247 | ew32(CTRL_EXT, mac_reg); | |
1248 | ||
1249 | /* When ULP mode was previously entered, K1 was disabled by the | |
1250 | * hardware. Re-Enable K1 in the PHY when exiting ULP. | |
1251 | */ | |
1252 | ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg); | |
1253 | if (ret_val) | |
1254 | goto release; | |
1255 | phy_reg |= HV_PM_CTRL_K1_ENABLE; | |
1256 | e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg); | |
1257 | ||
1258 | /* Clear ULP enabled configuration */ | |
1259 | ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg); | |
1260 | if (ret_val) | |
1261 | goto release; | |
1262 | phy_reg &= ~(I218_ULP_CONFIG1_IND | | |
1263 | I218_ULP_CONFIG1_STICKY_ULP | | |
1264 | I218_ULP_CONFIG1_RESET_TO_SMBUS | | |
1265 | I218_ULP_CONFIG1_WOL_HOST | | |
1266 | I218_ULP_CONFIG1_INBAND_EXIT | | |
1267 | I218_ULP_CONFIG1_DISABLE_SMB_PERST); | |
1268 | e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); | |
1269 | ||
1270 | /* Commit ULP changes by starting auto ULP configuration */ | |
1271 | phy_reg |= I218_ULP_CONFIG1_START; | |
1272 | e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); | |
1273 | ||
1274 | /* Clear Disable SMBus Release on PERST# in MAC */ | |
1275 | mac_reg = er32(FEXTNVM7); | |
1276 | mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST; | |
1277 | ew32(FEXTNVM7, mac_reg); | |
1278 | ||
1279 | release: | |
1280 | hw->phy.ops.release(hw); | |
1281 | if (force) { | |
1282 | e1000_phy_hw_reset(hw); | |
1283 | msleep(50); | |
1284 | } | |
1285 | out: | |
1286 | if (ret_val) | |
1287 | e_dbg("Error in ULP disable flow: %d\n", ret_val); | |
1288 | else | |
1289 | hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off; | |
1290 | ||
1291 | return ret_val; | |
1292 | } | |
1293 | ||
1294 | /** | |
1295 | * e1000_check_for_copper_link_ich8lan - Check for link (Copper) | |
1296 | * @hw: pointer to the HW structure | |
1297 | * | |
1298 | * Checks to see of the link status of the hardware has changed. If a | |
1299 | * change in link status has been detected, then we read the PHY registers | |
1300 | * to get the current speed/duplex if link exists. | |
1301 | **/ | |
1302 | static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) | |
1303 | { | |
1304 | struct e1000_mac_info *mac = &hw->mac; | |
1305 | s32 ret_val; | |
1306 | bool link; | |
1307 | u16 phy_reg; | |
1308 | ||
1309 | /* We only want to go out to the PHY registers to see if Auto-Neg | |
1310 | * has completed and/or if our link status has changed. The | |
1311 | * get_link_status flag is set upon receiving a Link Status | |
1312 | * Change or Rx Sequence Error interrupt. | |
1313 | */ | |
1314 | if (!mac->get_link_status) | |
1315 | return 0; | |
1316 | ||
1317 | /* First we want to see if the MII Status Register reports | |
1318 | * link. If so, then we want to get the current speed/duplex | |
1319 | * of the PHY. | |
1320 | */ | |
1321 | ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); | |
1322 | if (ret_val) | |
1323 | return ret_val; | |
1324 | ||
1325 | if (hw->mac.type == e1000_pchlan) { | |
1326 | ret_val = e1000_k1_gig_workaround_hv(hw, link); | |
1327 | if (ret_val) | |
1328 | return ret_val; | |
1329 | } | |
1330 | ||
1331 | /* When connected at 10Mbps half-duplex, some parts are excessively | |
1332 | * aggressive resulting in many collisions. To avoid this, increase | |
1333 | * the IPG and reduce Rx latency in the PHY. | |
1334 | */ | |
1335 | if (((hw->mac.type == e1000_pch2lan) || | |
1336 | (hw->mac.type == e1000_pch_lpt)) && link) { | |
1337 | u32 reg; | |
1338 | ||
1339 | reg = er32(STATUS); | |
1340 | if (!(reg & (E1000_STATUS_FD | E1000_STATUS_SPEED_MASK))) { | |
1341 | u16 emi_addr; | |
1342 | ||
1343 | reg = er32(TIPG); | |
1344 | reg &= ~E1000_TIPG_IPGT_MASK; | |
1345 | reg |= 0xFF; | |
1346 | ew32(TIPG, reg); | |
1347 | ||
1348 | /* Reduce Rx latency in analog PHY */ | |
1349 | ret_val = hw->phy.ops.acquire(hw); | |
1350 | if (ret_val) | |
1351 | return ret_val; | |
1352 | ||
1353 | if (hw->mac.type == e1000_pch2lan) | |
1354 | emi_addr = I82579_RX_CONFIG; | |
1355 | else | |
1356 | emi_addr = I217_RX_CONFIG; | |
1357 | ||
1358 | ret_val = e1000_write_emi_reg_locked(hw, emi_addr, 0); | |
1359 | ||
1360 | hw->phy.ops.release(hw); | |
1361 | ||
1362 | if (ret_val) | |
1363 | return ret_val; | |
1364 | } | |
1365 | } | |
1366 | ||
1367 | /* Work-around I218 hang issue */ | |
1368 | if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) || | |
1369 | (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V) || | |
1370 | (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM3) || | |
1371 | (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V3)) { | |
1372 | ret_val = e1000_k1_workaround_lpt_lp(hw, link); | |
1373 | if (ret_val) | |
1374 | return ret_val; | |
1375 | } | |
1376 | ||
1377 | if (hw->mac.type == e1000_pch_lpt) { | |
1378 | /* Set platform power management values for | |
1379 | * Latency Tolerance Reporting (LTR) | |
1380 | */ | |
1381 | ret_val = e1000_platform_pm_pch_lpt(hw, link); | |
1382 | if (ret_val) | |
1383 | return ret_val; | |
1384 | } | |
1385 | ||
1386 | /* Clear link partner's EEE ability */ | |
1387 | hw->dev_spec.ich8lan.eee_lp_ability = 0; | |
1388 | ||
1389 | if (!link) | |
1390 | return 0; /* No link detected */ | |
1391 | ||
1392 | mac->get_link_status = false; | |
1393 | ||
1394 | switch (hw->mac.type) { | |
1395 | case e1000_pch2lan: | |
1396 | ret_val = e1000_k1_workaround_lv(hw); | |
1397 | if (ret_val) | |
1398 | return ret_val; | |
1399 | /* fall-thru */ | |
1400 | case e1000_pchlan: | |
1401 | if (hw->phy.type == e1000_phy_82578) { | |
1402 | ret_val = e1000_link_stall_workaround_hv(hw); | |
1403 | if (ret_val) | |
1404 | return ret_val; | |
1405 | } | |
1406 | ||
1407 | /* Workaround for PCHx parts in half-duplex: | |
1408 | * Set the number of preambles removed from the packet | |
1409 | * when it is passed from the PHY to the MAC to prevent | |
1410 | * the MAC from misinterpreting the packet type. | |
1411 | */ | |
1412 | e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg); | |
1413 | phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK; | |
1414 | ||
1415 | if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD) | |
1416 | phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT); | |
1417 | ||
1418 | e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg); | |
1419 | break; | |
1420 | default: | |
1421 | break; | |
1422 | } | |
1423 | ||
1424 | /* Check if there was DownShift, must be checked | |
1425 | * immediately after link-up | |
1426 | */ | |
1427 | e1000e_check_downshift(hw); | |
1428 | ||
1429 | /* Enable/Disable EEE after link up */ | |
1430 | if (hw->phy.type > e1000_phy_82579) { | |
1431 | ret_val = e1000_set_eee_pchlan(hw); | |
1432 | if (ret_val) | |
1433 | return ret_val; | |
1434 | } | |
1435 | ||
1436 | /* If we are forcing speed/duplex, then we simply return since | |
1437 | * we have already determined whether we have link or not. | |
1438 | */ | |
1439 | if (!mac->autoneg) | |
1440 | return -E1000_ERR_CONFIG; | |
1441 | ||
1442 | /* Auto-Neg is enabled. Auto Speed Detection takes care | |
1443 | * of MAC speed/duplex configuration. So we only need to | |
1444 | * configure Collision Distance in the MAC. | |
1445 | */ | |
1446 | mac->ops.config_collision_dist(hw); | |
1447 | ||
1448 | /* Configure Flow Control now that Auto-Neg has completed. | |
1449 | * First, we need to restore the desired flow control | |
1450 | * settings because we may have had to re-autoneg with a | |
1451 | * different link partner. | |
1452 | */ | |
1453 | ret_val = e1000e_config_fc_after_link_up(hw); | |
1454 | if (ret_val) | |
1455 | e_dbg("Error configuring flow control\n"); | |
1456 | ||
1457 | return ret_val; | |
1458 | } | |
1459 | ||
1460 | static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter) | |
1461 | { | |
1462 | struct e1000_hw *hw = &adapter->hw; | |
1463 | s32 rc; | |
1464 | ||
1465 | rc = e1000_init_mac_params_ich8lan(hw); | |
1466 | if (rc) | |
1467 | return rc; | |
1468 | ||
1469 | rc = e1000_init_nvm_params_ich8lan(hw); | |
1470 | if (rc) | |
1471 | return rc; | |
1472 | ||
1473 | switch (hw->mac.type) { | |
1474 | case e1000_ich8lan: | |
1475 | case e1000_ich9lan: | |
1476 | case e1000_ich10lan: | |
1477 | rc = e1000_init_phy_params_ich8lan(hw); | |
1478 | break; | |
1479 | case e1000_pchlan: | |
1480 | case e1000_pch2lan: | |
1481 | case e1000_pch_lpt: | |
1482 | rc = e1000_init_phy_params_pchlan(hw); | |
1483 | break; | |
1484 | default: | |
1485 | break; | |
1486 | } | |
1487 | if (rc) | |
1488 | return rc; | |
1489 | ||
1490 | /* Disable Jumbo Frame support on parts with Intel 10/100 PHY or | |
1491 | * on parts with MACsec enabled in NVM (reflected in CTRL_EXT). | |
1492 | */ | |
1493 | if ((adapter->hw.phy.type == e1000_phy_ife) || | |
1494 | ((adapter->hw.mac.type >= e1000_pch2lan) && | |
1495 | (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) { | |
1496 | adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES; | |
1497 | adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN; | |
1498 | ||
1499 | hw->mac.ops.blink_led = NULL; | |
1500 | } | |
1501 | ||
1502 | if ((adapter->hw.mac.type == e1000_ich8lan) && | |
1503 | (adapter->hw.phy.type != e1000_phy_ife)) | |
1504 | adapter->flags |= FLAG_LSC_GIG_SPEED_DROP; | |
1505 | ||
1506 | /* Enable workaround for 82579 w/ ME enabled */ | |
1507 | if ((adapter->hw.mac.type == e1000_pch2lan) && | |
1508 | (er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) | |
1509 | adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA; | |
1510 | ||
1511 | return 0; | |
1512 | } | |
1513 | ||
1514 | static DEFINE_MUTEX(nvm_mutex); | |
1515 | ||
1516 | /** | |
1517 | * e1000_acquire_nvm_ich8lan - Acquire NVM mutex | |
1518 | * @hw: pointer to the HW structure | |
1519 | * | |
1520 | * Acquires the mutex for performing NVM operations. | |
1521 | **/ | |
1522 | static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused *hw) | |
1523 | { | |
1524 | mutex_lock(&nvm_mutex); | |
1525 | ||
1526 | return 0; | |
1527 | } | |
1528 | ||
1529 | /** | |
1530 | * e1000_release_nvm_ich8lan - Release NVM mutex | |
1531 | * @hw: pointer to the HW structure | |
1532 | * | |
1533 | * Releases the mutex used while performing NVM operations. | |
1534 | **/ | |
1535 | static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused *hw) | |
1536 | { | |
1537 | mutex_unlock(&nvm_mutex); | |
1538 | } | |
1539 | ||
1540 | /** | |
1541 | * e1000_acquire_swflag_ich8lan - Acquire software control flag | |
1542 | * @hw: pointer to the HW structure | |
1543 | * | |
1544 | * Acquires the software control flag for performing PHY and select | |
1545 | * MAC CSR accesses. | |
1546 | **/ | |
1547 | static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) | |
1548 | { | |
1549 | u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT; | |
1550 | s32 ret_val = 0; | |
1551 | ||
1552 | if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE, | |
1553 | &hw->adapter->state)) { | |
1554 | e_dbg("contention for Phy access\n"); | |
1555 | return -E1000_ERR_PHY; | |
1556 | } | |
1557 | ||
1558 | while (timeout) { | |
1559 | extcnf_ctrl = er32(EXTCNF_CTRL); | |
1560 | if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)) | |
1561 | break; | |
1562 | ||
1563 | mdelay(1); | |
1564 | timeout--; | |
1565 | } | |
1566 | ||
1567 | if (!timeout) { | |
1568 | e_dbg("SW has already locked the resource.\n"); | |
1569 | ret_val = -E1000_ERR_CONFIG; | |
1570 | goto out; | |
1571 | } | |
1572 | ||
1573 | timeout = SW_FLAG_TIMEOUT; | |
1574 | ||
1575 | extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; | |
1576 | ew32(EXTCNF_CTRL, extcnf_ctrl); | |
1577 | ||
1578 | while (timeout) { | |
1579 | extcnf_ctrl = er32(EXTCNF_CTRL); | |
1580 | if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) | |
1581 | break; | |
1582 | ||
1583 | mdelay(1); | |
1584 | timeout--; | |
1585 | } | |
1586 | ||
1587 | if (!timeout) { | |
1588 | e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n", | |
1589 | er32(FWSM), extcnf_ctrl); | |
1590 | extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; | |
1591 | ew32(EXTCNF_CTRL, extcnf_ctrl); | |
1592 | ret_val = -E1000_ERR_CONFIG; | |
1593 | goto out; | |
1594 | } | |
1595 | ||
1596 | out: | |
1597 | if (ret_val) | |
1598 | clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); | |
1599 | ||
1600 | return ret_val; | |
1601 | } | |
1602 | ||
1603 | /** | |
1604 | * e1000_release_swflag_ich8lan - Release software control flag | |
1605 | * @hw: pointer to the HW structure | |
1606 | * | |
1607 | * Releases the software control flag for performing PHY and select | |
1608 | * MAC CSR accesses. | |
1609 | **/ | |
1610 | static void e1000_release_swflag_ich8lan(struct e1000_hw *hw) | |
1611 | { | |
1612 | u32 extcnf_ctrl; | |
1613 | ||
1614 | extcnf_ctrl = er32(EXTCNF_CTRL); | |
1615 | ||
1616 | if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) { | |
1617 | extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; | |
1618 | ew32(EXTCNF_CTRL, extcnf_ctrl); | |
1619 | } else { | |
1620 | e_dbg("Semaphore unexpectedly released by sw/fw/hw\n"); | |
1621 | } | |
1622 | ||
1623 | clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); | |
1624 | } | |
1625 | ||
1626 | /** | |
1627 | * e1000_check_mng_mode_ich8lan - Checks management mode | |
1628 | * @hw: pointer to the HW structure | |
1629 | * | |
1630 | * This checks if the adapter has any manageability enabled. | |
1631 | * This is a function pointer entry point only called by read/write | |
1632 | * routines for the PHY and NVM parts. | |
1633 | **/ | |
1634 | static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw) | |
1635 | { | |
1636 | u32 fwsm; | |
1637 | ||
1638 | fwsm = er32(FWSM); | |
1639 | return (fwsm & E1000_ICH_FWSM_FW_VALID) && | |
1640 | ((fwsm & E1000_FWSM_MODE_MASK) == | |
1641 | (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)); | |
1642 | } | |
1643 | ||
1644 | /** | |
1645 | * e1000_check_mng_mode_pchlan - Checks management mode | |
1646 | * @hw: pointer to the HW structure | |
1647 | * | |
1648 | * This checks if the adapter has iAMT enabled. | |
1649 | * This is a function pointer entry point only called by read/write | |
1650 | * routines for the PHY and NVM parts. | |
1651 | **/ | |
1652 | static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw) | |
1653 | { | |
1654 | u32 fwsm; | |
1655 | ||
1656 | fwsm = er32(FWSM); | |
1657 | return (fwsm & E1000_ICH_FWSM_FW_VALID) && | |
1658 | (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)); | |
1659 | } | |
1660 | ||
1661 | /** | |
1662 | * e1000_rar_set_pch2lan - Set receive address register | |
1663 | * @hw: pointer to the HW structure | |
1664 | * @addr: pointer to the receive address | |
1665 | * @index: receive address array register | |
1666 | * | |
1667 | * Sets the receive address array register at index to the address passed | |
1668 | * in by addr. For 82579, RAR[0] is the base address register that is to | |
1669 | * contain the MAC address but RAR[1-6] are reserved for manageability (ME). | |
1670 | * Use SHRA[0-3] in place of those reserved for ME. | |
1671 | **/ | |
1672 | static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index) | |
1673 | { | |
1674 | u32 rar_low, rar_high; | |
1675 | ||
1676 | /* HW expects these in little endian so we reverse the byte order | |
1677 | * from network order (big endian) to little endian | |
1678 | */ | |
1679 | rar_low = ((u32)addr[0] | | |
1680 | ((u32)addr[1] << 8) | | |
1681 | ((u32)addr[2] << 16) | ((u32)addr[3] << 24)); | |
1682 | ||
1683 | rar_high = ((u32)addr[4] | ((u32)addr[5] << 8)); | |
1684 | ||
1685 | /* If MAC address zero, no need to set the AV bit */ | |
1686 | if (rar_low || rar_high) | |
1687 | rar_high |= E1000_RAH_AV; | |
1688 | ||
1689 | if (index == 0) { | |
1690 | ew32(RAL(index), rar_low); | |
1691 | e1e_flush(); | |
1692 | ew32(RAH(index), rar_high); | |
1693 | e1e_flush(); | |
1694 | return 0; | |
1695 | } | |
1696 | ||
1697 | /* RAR[1-6] are owned by manageability. Skip those and program the | |
1698 | * next address into the SHRA register array. | |
1699 | */ | |
1700 | if (index < (u32)(hw->mac.rar_entry_count)) { | |
1701 | s32 ret_val; | |
1702 | ||
1703 | ret_val = e1000_acquire_swflag_ich8lan(hw); | |
1704 | if (ret_val) | |
1705 | goto out; | |
1706 | ||
1707 | ew32(SHRAL(index - 1), rar_low); | |
1708 | e1e_flush(); | |
1709 | ew32(SHRAH(index - 1), rar_high); | |
1710 | e1e_flush(); | |
1711 | ||
1712 | e1000_release_swflag_ich8lan(hw); | |
1713 | ||
1714 | /* verify the register updates */ | |
1715 | if ((er32(SHRAL(index - 1)) == rar_low) && | |
1716 | (er32(SHRAH(index - 1)) == rar_high)) | |
1717 | return 0; | |
1718 | ||
1719 | e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n", | |
1720 | (index - 1), er32(FWSM)); | |
1721 | } | |
1722 | ||
1723 | out: | |
1724 | e_dbg("Failed to write receive address at index %d\n", index); | |
1725 | return -E1000_ERR_CONFIG; | |
1726 | } | |
1727 | ||
1728 | /** | |
1729 | * e1000_rar_get_count_pch_lpt - Get the number of available SHRA | |
1730 | * @hw: pointer to the HW structure | |
1731 | * | |
1732 | * Get the number of available receive registers that the Host can | |
1733 | * program. SHRA[0-10] are the shared receive address registers | |
1734 | * that are shared between the Host and manageability engine (ME). | |
1735 | * ME can reserve any number of addresses and the host needs to be | |
1736 | * able to tell how many available registers it has access to. | |
1737 | **/ | |
1738 | static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw) | |
1739 | { | |
1740 | u32 wlock_mac; | |
1741 | u32 num_entries; | |
1742 | ||
1743 | wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK; | |
1744 | wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT; | |
1745 | ||
1746 | switch (wlock_mac) { | |
1747 | case 0: | |
1748 | /* All SHRA[0..10] and RAR[0] available */ | |
1749 | num_entries = hw->mac.rar_entry_count; | |
1750 | break; | |
1751 | case 1: | |
1752 | /* Only RAR[0] available */ | |
1753 | num_entries = 1; | |
1754 | break; | |
1755 | default: | |
1756 | /* SHRA[0..(wlock_mac - 1)] available + RAR[0] */ | |
1757 | num_entries = wlock_mac + 1; | |
1758 | break; | |
1759 | } | |
1760 | ||
1761 | return num_entries; | |
1762 | } | |
1763 | ||
1764 | /** | |
1765 | * e1000_rar_set_pch_lpt - Set receive address registers | |
1766 | * @hw: pointer to the HW structure | |
1767 | * @addr: pointer to the receive address | |
1768 | * @index: receive address array register | |
1769 | * | |
1770 | * Sets the receive address register array at index to the address passed | |
1771 | * in by addr. For LPT, RAR[0] is the base address register that is to | |
1772 | * contain the MAC address. SHRA[0-10] are the shared receive address | |
1773 | * registers that are shared between the Host and manageability engine (ME). | |
1774 | **/ | |
1775 | static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index) | |
1776 | { | |
1777 | u32 rar_low, rar_high; | |
1778 | u32 wlock_mac; | |
1779 | ||
1780 | /* HW expects these in little endian so we reverse the byte order | |
1781 | * from network order (big endian) to little endian | |
1782 | */ | |
1783 | rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) | | |
1784 | ((u32)addr[2] << 16) | ((u32)addr[3] << 24)); | |
1785 | ||
1786 | rar_high = ((u32)addr[4] | ((u32)addr[5] << 8)); | |
1787 | ||
1788 | /* If MAC address zero, no need to set the AV bit */ | |
1789 | if (rar_low || rar_high) | |
1790 | rar_high |= E1000_RAH_AV; | |
1791 | ||
1792 | if (index == 0) { | |
1793 | ew32(RAL(index), rar_low); | |
1794 | e1e_flush(); | |
1795 | ew32(RAH(index), rar_high); | |
1796 | e1e_flush(); | |
1797 | return 0; | |
1798 | } | |
1799 | ||
1800 | /* The manageability engine (ME) can lock certain SHRAR registers that | |
1801 | * it is using - those registers are unavailable for use. | |
1802 | */ | |
1803 | if (index < hw->mac.rar_entry_count) { | |
1804 | wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK; | |
1805 | wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT; | |
1806 | ||
1807 | /* Check if all SHRAR registers are locked */ | |
1808 | if (wlock_mac == 1) | |
1809 | goto out; | |
1810 | ||
1811 | if ((wlock_mac == 0) || (index <= wlock_mac)) { | |
1812 | s32 ret_val; | |
1813 | ||
1814 | ret_val = e1000_acquire_swflag_ich8lan(hw); | |
1815 | ||
1816 | if (ret_val) | |
1817 | goto out; | |
1818 | ||
1819 | ew32(SHRAL_PCH_LPT(index - 1), rar_low); | |
1820 | e1e_flush(); | |
1821 | ew32(SHRAH_PCH_LPT(index - 1), rar_high); | |
1822 | e1e_flush(); | |
1823 | ||
1824 | e1000_release_swflag_ich8lan(hw); | |
1825 | ||
1826 | /* verify the register updates */ | |
1827 | if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) && | |
1828 | (er32(SHRAH_PCH_LPT(index - 1)) == rar_high)) | |
1829 | return 0; | |
1830 | } | |
1831 | } | |
1832 | ||
1833 | out: | |
1834 | e_dbg("Failed to write receive address at index %d\n", index); | |
1835 | return -E1000_ERR_CONFIG; | |
1836 | } | |
1837 | ||
1838 | /** | |
1839 | * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked | |
1840 | * @hw: pointer to the HW structure | |
1841 | * | |
1842 | * Checks if firmware is blocking the reset of the PHY. | |
1843 | * This is a function pointer entry point only called by | |
1844 | * reset routines. | |
1845 | **/ | |
1846 | static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw) | |
1847 | { | |
1848 | bool blocked = false; | |
1849 | int i = 0; | |
1850 | ||
1851 | while ((blocked = !(er32(FWSM) & E1000_ICH_FWSM_RSPCIPHY)) && | |
1852 | (i++ < 10)) | |
1853 | usleep_range(10000, 20000); | |
1854 | return blocked ? E1000_BLK_PHY_RESET : 0; | |
1855 | } | |
1856 | ||
1857 | /** | |
1858 | * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states | |
1859 | * @hw: pointer to the HW structure | |
1860 | * | |
1861 | * Assumes semaphore already acquired. | |
1862 | * | |
1863 | **/ | |
1864 | static s32 e1000_write_smbus_addr(struct e1000_hw *hw) | |
1865 | { | |
1866 | u16 phy_data; | |
1867 | u32 strap = er32(STRAP); | |
1868 | u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >> | |
1869 | E1000_STRAP_SMT_FREQ_SHIFT; | |
1870 | s32 ret_val; | |
1871 | ||
1872 | strap &= E1000_STRAP_SMBUS_ADDRESS_MASK; | |
1873 | ||
1874 | ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data); | |
1875 | if (ret_val) | |
1876 | return ret_val; | |
1877 | ||
1878 | phy_data &= ~HV_SMB_ADDR_MASK; | |
1879 | phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT); | |
1880 | phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID; | |
1881 | ||
1882 | if (hw->phy.type == e1000_phy_i217) { | |
1883 | /* Restore SMBus frequency */ | |
1884 | if (freq--) { | |
1885 | phy_data &= ~HV_SMB_ADDR_FREQ_MASK; | |
1886 | phy_data |= (freq & (1 << 0)) << | |
1887 | HV_SMB_ADDR_FREQ_LOW_SHIFT; | |
1888 | phy_data |= (freq & (1 << 1)) << | |
1889 | (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1); | |
1890 | } else { | |
1891 | e_dbg("Unsupported SMB frequency in PHY\n"); | |
1892 | } | |
1893 | } | |
1894 | ||
1895 | return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data); | |
1896 | } | |
1897 | ||
1898 | /** | |
1899 | * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration | |
1900 | * @hw: pointer to the HW structure | |
1901 | * | |
1902 | * SW should configure the LCD from the NVM extended configuration region | |
1903 | * as a workaround for certain parts. | |
1904 | **/ | |
1905 | static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw) | |
1906 | { | |
1907 | struct e1000_phy_info *phy = &hw->phy; | |
1908 | u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask; | |
1909 | s32 ret_val = 0; | |
1910 | u16 word_addr, reg_data, reg_addr, phy_page = 0; | |
1911 | ||
1912 | /* Initialize the PHY from the NVM on ICH platforms. This | |
1913 | * is needed due to an issue where the NVM configuration is | |
1914 | * not properly autoloaded after power transitions. | |
1915 | * Therefore, after each PHY reset, we will load the | |
1916 | * configuration data out of the NVM manually. | |
1917 | */ | |
1918 | switch (hw->mac.type) { | |
1919 | case e1000_ich8lan: | |
1920 | if (phy->type != e1000_phy_igp_3) | |
1921 | return ret_val; | |
1922 | ||
1923 | if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) || | |
1924 | (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) { | |
1925 | sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG; | |
1926 | break; | |
1927 | } | |
1928 | /* Fall-thru */ | |
1929 | case e1000_pchlan: | |
1930 | case e1000_pch2lan: | |
1931 | case e1000_pch_lpt: | |
1932 | sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M; | |
1933 | break; | |
1934 | default: | |
1935 | return ret_val; | |
1936 | } | |
1937 | ||
1938 | ret_val = hw->phy.ops.acquire(hw); | |
1939 | if (ret_val) | |
1940 | return ret_val; | |
1941 | ||
1942 | data = er32(FEXTNVM); | |
1943 | if (!(data & sw_cfg_mask)) | |
1944 | goto release; | |
1945 | ||
1946 | /* Make sure HW does not configure LCD from PHY | |
1947 | * extended configuration before SW configuration | |
1948 | */ | |
1949 | data = er32(EXTCNF_CTRL); | |
1950 | if ((hw->mac.type < e1000_pch2lan) && | |
1951 | (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)) | |
1952 | goto release; | |
1953 | ||
1954 | cnf_size = er32(EXTCNF_SIZE); | |
1955 | cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK; | |
1956 | cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT; | |
1957 | if (!cnf_size) | |
1958 | goto release; | |
1959 | ||
1960 | cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK; | |
1961 | cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT; | |
1962 | ||
1963 | if (((hw->mac.type == e1000_pchlan) && | |
1964 | !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) || | |
1965 | (hw->mac.type > e1000_pchlan)) { | |
1966 | /* HW configures the SMBus address and LEDs when the | |
1967 | * OEM and LCD Write Enable bits are set in the NVM. | |
1968 | * When both NVM bits are cleared, SW will configure | |
1969 | * them instead. | |
1970 | */ | |
1971 | ret_val = e1000_write_smbus_addr(hw); | |
1972 | if (ret_val) | |
1973 | goto release; | |
1974 | ||
1975 | data = er32(LEDCTL); | |
1976 | ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG, | |
1977 | (u16)data); | |
1978 | if (ret_val) | |
1979 | goto release; | |
1980 | } | |
1981 | ||
1982 | /* Configure LCD from extended configuration region. */ | |
1983 | ||
1984 | /* cnf_base_addr is in DWORD */ | |
1985 | word_addr = (u16)(cnf_base_addr << 1); | |
1986 | ||
1987 | for (i = 0; i < cnf_size; i++) { | |
1988 | ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, ®_data); | |
1989 | if (ret_val) | |
1990 | goto release; | |
1991 | ||
1992 | ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1), | |
1993 | 1, ®_addr); | |
1994 | if (ret_val) | |
1995 | goto release; | |
1996 | ||
1997 | /* Save off the PHY page for future writes. */ | |
1998 | if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) { | |
1999 | phy_page = reg_data; | |
2000 | continue; | |
2001 | } | |
2002 | ||
2003 | reg_addr &= PHY_REG_MASK; | |
2004 | reg_addr |= phy_page; | |
2005 | ||
2006 | ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data); | |
2007 | if (ret_val) | |
2008 | goto release; | |
2009 | } | |
2010 | ||
2011 | release: | |
2012 | hw->phy.ops.release(hw); | |
2013 | return ret_val; | |
2014 | } | |
2015 | ||
2016 | /** | |
2017 | * e1000_k1_gig_workaround_hv - K1 Si workaround | |
2018 | * @hw: pointer to the HW structure | |
2019 | * @link: link up bool flag | |
2020 | * | |
2021 | * If K1 is enabled for 1Gbps, the MAC might stall when transitioning | |
2022 | * from a lower speed. This workaround disables K1 whenever link is at 1Gig | |
2023 | * If link is down, the function will restore the default K1 setting located | |
2024 | * in the NVM. | |
2025 | **/ | |
2026 | static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link) | |
2027 | { | |
2028 | s32 ret_val = 0; | |
2029 | u16 status_reg = 0; | |
2030 | bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled; | |
2031 | ||
2032 | if (hw->mac.type != e1000_pchlan) | |
2033 | return 0; | |
2034 | ||
2035 | /* Wrap the whole flow with the sw flag */ | |
2036 | ret_val = hw->phy.ops.acquire(hw); | |
2037 | if (ret_val) | |
2038 | return ret_val; | |
2039 | ||
2040 | /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */ | |
2041 | if (link) { | |
2042 | if (hw->phy.type == e1000_phy_82578) { | |
2043 | ret_val = e1e_rphy_locked(hw, BM_CS_STATUS, | |
2044 | &status_reg); | |
2045 | if (ret_val) | |
2046 | goto release; | |
2047 | ||
2048 | status_reg &= (BM_CS_STATUS_LINK_UP | | |
2049 | BM_CS_STATUS_RESOLVED | | |
2050 | BM_CS_STATUS_SPEED_MASK); | |
2051 | ||
2052 | if (status_reg == (BM_CS_STATUS_LINK_UP | | |
2053 | BM_CS_STATUS_RESOLVED | | |
2054 | BM_CS_STATUS_SPEED_1000)) | |
2055 | k1_enable = false; | |
2056 | } | |
2057 | ||
2058 | if (hw->phy.type == e1000_phy_82577) { | |
2059 | ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg); | |
2060 | if (ret_val) | |
2061 | goto release; | |
2062 | ||
2063 | status_reg &= (HV_M_STATUS_LINK_UP | | |
2064 | HV_M_STATUS_AUTONEG_COMPLETE | | |
2065 | HV_M_STATUS_SPEED_MASK); | |
2066 | ||
2067 | if (status_reg == (HV_M_STATUS_LINK_UP | | |
2068 | HV_M_STATUS_AUTONEG_COMPLETE | | |
2069 | HV_M_STATUS_SPEED_1000)) | |
2070 | k1_enable = false; | |
2071 | } | |
2072 | ||
2073 | /* Link stall fix for link up */ | |
2074 | ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100); | |
2075 | if (ret_val) | |
2076 | goto release; | |
2077 | ||
2078 | } else { | |
2079 | /* Link stall fix for link down */ | |
2080 | ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100); | |
2081 | if (ret_val) | |
2082 | goto release; | |
2083 | } | |
2084 | ||
2085 | ret_val = e1000_configure_k1_ich8lan(hw, k1_enable); | |
2086 | ||
2087 | release: | |
2088 | hw->phy.ops.release(hw); | |
2089 | ||
2090 | return ret_val; | |
2091 | } | |
2092 | ||
2093 | /** | |
2094 | * e1000_configure_k1_ich8lan - Configure K1 power state | |
2095 | * @hw: pointer to the HW structure | |
2096 | * @enable: K1 state to configure | |
2097 | * | |
2098 | * Configure the K1 power state based on the provided parameter. | |
2099 | * Assumes semaphore already acquired. | |
2100 | * | |
2101 | * Success returns 0, Failure returns -E1000_ERR_PHY (-2) | |
2102 | **/ | |
2103 | s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable) | |
2104 | { | |
2105 | s32 ret_val; | |
2106 | u32 ctrl_reg = 0; | |
2107 | u32 ctrl_ext = 0; | |
2108 | u32 reg = 0; | |
2109 | u16 kmrn_reg = 0; | |
2110 | ||
2111 | ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, | |
2112 | &kmrn_reg); | |
2113 | if (ret_val) | |
2114 | return ret_val; | |
2115 | ||
2116 | if (k1_enable) | |
2117 | kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE; | |
2118 | else | |
2119 | kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE; | |
2120 | ||
2121 | ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, | |
2122 | kmrn_reg); | |
2123 | if (ret_val) | |
2124 | return ret_val; | |
2125 | ||
2126 | usleep_range(20, 40); | |
2127 | ctrl_ext = er32(CTRL_EXT); | |
2128 | ctrl_reg = er32(CTRL); | |
2129 | ||
2130 | reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); | |
2131 | reg |= E1000_CTRL_FRCSPD; | |
2132 | ew32(CTRL, reg); | |
2133 | ||
2134 | ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS); | |
2135 | e1e_flush(); | |
2136 | usleep_range(20, 40); | |
2137 | ew32(CTRL, ctrl_reg); | |
2138 | ew32(CTRL_EXT, ctrl_ext); | |
2139 | e1e_flush(); | |
2140 | usleep_range(20, 40); | |
2141 | ||
2142 | return 0; | |
2143 | } | |
2144 | ||
2145 | /** | |
2146 | * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration | |
2147 | * @hw: pointer to the HW structure | |
2148 | * @d0_state: boolean if entering d0 or d3 device state | |
2149 | * | |
2150 | * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are | |
2151 | * collectively called OEM bits. The OEM Write Enable bit and SW Config bit | |
2152 | * in NVM determines whether HW should configure LPLU and Gbe Disable. | |
2153 | **/ | |
2154 | static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state) | |
2155 | { | |
2156 | s32 ret_val = 0; | |
2157 | u32 mac_reg; | |
2158 | u16 oem_reg; | |
2159 | ||
2160 | if (hw->mac.type < e1000_pchlan) | |
2161 | return ret_val; | |
2162 | ||
2163 | ret_val = hw->phy.ops.acquire(hw); | |
2164 | if (ret_val) | |
2165 | return ret_val; | |
2166 | ||
2167 | if (hw->mac.type == e1000_pchlan) { | |
2168 | mac_reg = er32(EXTCNF_CTRL); | |
2169 | if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) | |
2170 | goto release; | |
2171 | } | |
2172 | ||
2173 | mac_reg = er32(FEXTNVM); | |
2174 | if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M)) | |
2175 | goto release; | |
2176 | ||
2177 | mac_reg = er32(PHY_CTRL); | |
2178 | ||
2179 | ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg); | |
2180 | if (ret_val) | |
2181 | goto release; | |
2182 | ||
2183 | oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU); | |
2184 | ||
2185 | if (d0_state) { | |
2186 | if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE) | |
2187 | oem_reg |= HV_OEM_BITS_GBE_DIS; | |
2188 | ||
2189 | if (mac_reg & E1000_PHY_CTRL_D0A_LPLU) | |
2190 | oem_reg |= HV_OEM_BITS_LPLU; | |
2191 | } else { | |
2192 | if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE | | |
2193 | E1000_PHY_CTRL_NOND0A_GBE_DISABLE)) | |
2194 | oem_reg |= HV_OEM_BITS_GBE_DIS; | |
2195 | ||
2196 | if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU | | |
2197 | E1000_PHY_CTRL_NOND0A_LPLU)) | |
2198 | oem_reg |= HV_OEM_BITS_LPLU; | |
2199 | } | |
2200 | ||
2201 | /* Set Restart auto-neg to activate the bits */ | |
2202 | if ((d0_state || (hw->mac.type != e1000_pchlan)) && | |
2203 | !hw->phy.ops.check_reset_block(hw)) | |
2204 | oem_reg |= HV_OEM_BITS_RESTART_AN; | |
2205 | ||
2206 | ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg); | |
2207 | ||
2208 | release: | |
2209 | hw->phy.ops.release(hw); | |
2210 | ||
2211 | return ret_val; | |
2212 | } | |
2213 | ||
2214 | /** | |
2215 | * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode | |
2216 | * @hw: pointer to the HW structure | |
2217 | **/ | |
2218 | static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw) | |
2219 | { | |
2220 | s32 ret_val; | |
2221 | u16 data; | |
2222 | ||
2223 | ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data); | |
2224 | if (ret_val) | |
2225 | return ret_val; | |
2226 | ||
2227 | data |= HV_KMRN_MDIO_SLOW; | |
2228 | ||
2229 | ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data); | |
2230 | ||
2231 | return ret_val; | |
2232 | } | |
2233 | ||
2234 | /** | |
2235 | * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be | |
2236 | * done after every PHY reset. | |
2237 | **/ | |
2238 | static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw) | |
2239 | { | |
2240 | s32 ret_val = 0; | |
2241 | u16 phy_data; | |
2242 | ||
2243 | if (hw->mac.type != e1000_pchlan) | |
2244 | return 0; | |
2245 | ||
2246 | /* Set MDIO slow mode before any other MDIO access */ | |
2247 | if (hw->phy.type == e1000_phy_82577) { | |
2248 | ret_val = e1000_set_mdio_slow_mode_hv(hw); | |
2249 | if (ret_val) | |
2250 | return ret_val; | |
2251 | } | |
2252 | ||
2253 | if (((hw->phy.type == e1000_phy_82577) && | |
2254 | ((hw->phy.revision == 1) || (hw->phy.revision == 2))) || | |
2255 | ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) { | |
2256 | /* Disable generation of early preamble */ | |
2257 | ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431); | |
2258 | if (ret_val) | |
2259 | return ret_val; | |
2260 | ||
2261 | /* Preamble tuning for SSC */ | |
2262 | ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204); | |
2263 | if (ret_val) | |
2264 | return ret_val; | |
2265 | } | |
2266 | ||
2267 | if (hw->phy.type == e1000_phy_82578) { | |
2268 | /* Return registers to default by doing a soft reset then | |
2269 | * writing 0x3140 to the control register. | |
2270 | */ | |
2271 | if (hw->phy.revision < 2) { | |
2272 | e1000e_phy_sw_reset(hw); | |
2273 | ret_val = e1e_wphy(hw, MII_BMCR, 0x3140); | |
2274 | } | |
2275 | } | |
2276 | ||
2277 | /* Select page 0 */ | |
2278 | ret_val = hw->phy.ops.acquire(hw); | |
2279 | if (ret_val) | |
2280 | return ret_val; | |
2281 | ||
2282 | hw->phy.addr = 1; | |
2283 | ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0); | |
2284 | hw->phy.ops.release(hw); | |
2285 | if (ret_val) | |
2286 | return ret_val; | |
2287 | ||
2288 | /* Configure the K1 Si workaround during phy reset assuming there is | |
2289 | * link so that it disables K1 if link is in 1Gbps. | |
2290 | */ | |
2291 | ret_val = e1000_k1_gig_workaround_hv(hw, true); | |
2292 | if (ret_val) | |
2293 | return ret_val; | |
2294 | ||
2295 | /* Workaround for link disconnects on a busy hub in half duplex */ | |
2296 | ret_val = hw->phy.ops.acquire(hw); | |
2297 | if (ret_val) | |
2298 | return ret_val; | |
2299 | ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data); | |
2300 | if (ret_val) | |
2301 | goto release; | |
2302 | ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF); | |
2303 | if (ret_val) | |
2304 | goto release; | |
2305 | ||
2306 | /* set MSE higher to enable link to stay up when noise is high */ | |
2307 | ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034); | |
2308 | release: | |
2309 | hw->phy.ops.release(hw); | |
2310 | ||
2311 | return ret_val; | |
2312 | } | |
2313 | ||
2314 | /** | |
2315 | * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY | |
2316 | * @hw: pointer to the HW structure | |
2317 | **/ | |
2318 | void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw) | |
2319 | { | |
2320 | u32 mac_reg; | |
2321 | u16 i, phy_reg = 0; | |
2322 | s32 ret_val; | |
2323 | ||
2324 | ret_val = hw->phy.ops.acquire(hw); | |
2325 | if (ret_val) | |
2326 | return; | |
2327 | ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg); | |
2328 | if (ret_val) | |
2329 | goto release; | |
2330 | ||
2331 | /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */ | |
2332 | for (i = 0; i < (hw->mac.rar_entry_count); i++) { | |
2333 | mac_reg = er32(RAL(i)); | |
2334 | hw->phy.ops.write_reg_page(hw, BM_RAR_L(i), | |
2335 | (u16)(mac_reg & 0xFFFF)); | |
2336 | hw->phy.ops.write_reg_page(hw, BM_RAR_M(i), | |
2337 | (u16)((mac_reg >> 16) & 0xFFFF)); | |
2338 | ||
2339 | mac_reg = er32(RAH(i)); | |
2340 | hw->phy.ops.write_reg_page(hw, BM_RAR_H(i), | |
2341 | (u16)(mac_reg & 0xFFFF)); | |
2342 | hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i), | |
2343 | (u16)((mac_reg & E1000_RAH_AV) | |
2344 | >> 16)); | |
2345 | } | |
2346 | ||
2347 | e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg); | |
2348 | ||
2349 | release: | |
2350 | hw->phy.ops.release(hw); | |
2351 | } | |
2352 | ||
2353 | /** | |
2354 | * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation | |
2355 | * with 82579 PHY | |
2356 | * @hw: pointer to the HW structure | |
2357 | * @enable: flag to enable/disable workaround when enabling/disabling jumbos | |
2358 | **/ | |
2359 | s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable) | |
2360 | { | |
2361 | s32 ret_val = 0; | |
2362 | u16 phy_reg, data; | |
2363 | u32 mac_reg; | |
2364 | u16 i; | |
2365 | ||
2366 | if (hw->mac.type < e1000_pch2lan) | |
2367 | return 0; | |
2368 | ||
2369 | /* disable Rx path while enabling/disabling workaround */ | |
2370 | e1e_rphy(hw, PHY_REG(769, 20), &phy_reg); | |
2371 | ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14)); | |
2372 | if (ret_val) | |
2373 | return ret_val; | |
2374 | ||
2375 | if (enable) { | |
2376 | /* Write Rx addresses (rar_entry_count for RAL/H, and | |
2377 | * SHRAL/H) and initial CRC values to the MAC | |
2378 | */ | |
2379 | for (i = 0; i < hw->mac.rar_entry_count; i++) { | |
2380 | u8 mac_addr[ETH_ALEN] = { 0 }; | |
2381 | u32 addr_high, addr_low; | |
2382 | ||
2383 | addr_high = er32(RAH(i)); | |
2384 | if (!(addr_high & E1000_RAH_AV)) | |
2385 | continue; | |
2386 | addr_low = er32(RAL(i)); | |
2387 | mac_addr[0] = (addr_low & 0xFF); | |
2388 | mac_addr[1] = ((addr_low >> 8) & 0xFF); | |
2389 | mac_addr[2] = ((addr_low >> 16) & 0xFF); | |
2390 | mac_addr[3] = ((addr_low >> 24) & 0xFF); | |
2391 | mac_addr[4] = (addr_high & 0xFF); | |
2392 | mac_addr[5] = ((addr_high >> 8) & 0xFF); | |
2393 | ||
2394 | ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr)); | |
2395 | } | |
2396 | ||
2397 | /* Write Rx addresses to the PHY */ | |
2398 | e1000_copy_rx_addrs_to_phy_ich8lan(hw); | |
2399 | ||
2400 | /* Enable jumbo frame workaround in the MAC */ | |
2401 | mac_reg = er32(FFLT_DBG); | |
2402 | mac_reg &= ~(1 << 14); | |
2403 | mac_reg |= (7 << 15); | |
2404 | ew32(FFLT_DBG, mac_reg); | |
2405 | ||
2406 | mac_reg = er32(RCTL); | |
2407 | mac_reg |= E1000_RCTL_SECRC; | |
2408 | ew32(RCTL, mac_reg); | |
2409 | ||
2410 | ret_val = e1000e_read_kmrn_reg(hw, | |
2411 | E1000_KMRNCTRLSTA_CTRL_OFFSET, | |
2412 | &data); | |
2413 | if (ret_val) | |
2414 | return ret_val; | |
2415 | ret_val = e1000e_write_kmrn_reg(hw, | |
2416 | E1000_KMRNCTRLSTA_CTRL_OFFSET, | |
2417 | data | (1 << 0)); | |
2418 | if (ret_val) | |
2419 | return ret_val; | |
2420 | ret_val = e1000e_read_kmrn_reg(hw, | |
2421 | E1000_KMRNCTRLSTA_HD_CTRL, | |
2422 | &data); | |
2423 | if (ret_val) | |
2424 | return ret_val; | |
2425 | data &= ~(0xF << 8); | |
2426 | data |= (0xB << 8); | |
2427 | ret_val = e1000e_write_kmrn_reg(hw, | |
2428 | E1000_KMRNCTRLSTA_HD_CTRL, | |
2429 | data); | |
2430 | if (ret_val) | |
2431 | return ret_val; | |
2432 | ||
2433 | /* Enable jumbo frame workaround in the PHY */ | |
2434 | e1e_rphy(hw, PHY_REG(769, 23), &data); | |
2435 | data &= ~(0x7F << 5); | |
2436 | data |= (0x37 << 5); | |
2437 | ret_val = e1e_wphy(hw, PHY_REG(769, 23), data); | |
2438 | if (ret_val) | |
2439 | return ret_val; | |
2440 | e1e_rphy(hw, PHY_REG(769, 16), &data); | |
2441 | data &= ~(1 << 13); | |
2442 | ret_val = e1e_wphy(hw, PHY_REG(769, 16), data); | |
2443 | if (ret_val) | |
2444 | return ret_val; | |
2445 | e1e_rphy(hw, PHY_REG(776, 20), &data); | |
2446 | data &= ~(0x3FF << 2); | |
2447 | data |= (E1000_TX_PTR_GAP << 2); | |
2448 | ret_val = e1e_wphy(hw, PHY_REG(776, 20), data); | |
2449 | if (ret_val) | |
2450 | return ret_val; | |
2451 | ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100); | |
2452 | if (ret_val) | |
2453 | return ret_val; | |
2454 | e1e_rphy(hw, HV_PM_CTRL, &data); | |
2455 | ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10)); | |
2456 | if (ret_val) | |
2457 | return ret_val; | |
2458 | } else { | |
2459 | /* Write MAC register values back to h/w defaults */ | |
2460 | mac_reg = er32(FFLT_DBG); | |
2461 | mac_reg &= ~(0xF << 14); | |
2462 | ew32(FFLT_DBG, mac_reg); | |
2463 | ||
2464 | mac_reg = er32(RCTL); | |
2465 | mac_reg &= ~E1000_RCTL_SECRC; | |
2466 | ew32(RCTL, mac_reg); | |
2467 | ||
2468 | ret_val = e1000e_read_kmrn_reg(hw, | |
2469 | E1000_KMRNCTRLSTA_CTRL_OFFSET, | |
2470 | &data); | |
2471 | if (ret_val) | |
2472 | return ret_val; | |
2473 | ret_val = e1000e_write_kmrn_reg(hw, | |
2474 | E1000_KMRNCTRLSTA_CTRL_OFFSET, | |
2475 | data & ~(1 << 0)); | |
2476 | if (ret_val) | |
2477 | return ret_val; | |
2478 | ret_val = e1000e_read_kmrn_reg(hw, | |
2479 | E1000_KMRNCTRLSTA_HD_CTRL, | |
2480 | &data); | |
2481 | if (ret_val) | |
2482 | return ret_val; | |
2483 | data &= ~(0xF << 8); | |
2484 | data |= (0xB << 8); | |
2485 | ret_val = e1000e_write_kmrn_reg(hw, | |
2486 | E1000_KMRNCTRLSTA_HD_CTRL, | |
2487 | data); | |
2488 | if (ret_val) | |
2489 | return ret_val; | |
2490 | ||
2491 | /* Write PHY register values back to h/w defaults */ | |
2492 | e1e_rphy(hw, PHY_REG(769, 23), &data); | |
2493 | data &= ~(0x7F << 5); | |
2494 | ret_val = e1e_wphy(hw, PHY_REG(769, 23), data); | |
2495 | if (ret_val) | |
2496 | return ret_val; | |
2497 | e1e_rphy(hw, PHY_REG(769, 16), &data); | |
2498 | data |= (1 << 13); | |
2499 | ret_val = e1e_wphy(hw, PHY_REG(769, 16), data); | |
2500 | if (ret_val) | |
2501 | return ret_val; | |
2502 | e1e_rphy(hw, PHY_REG(776, 20), &data); | |
2503 | data &= ~(0x3FF << 2); | |
2504 | data |= (0x8 << 2); | |
2505 | ret_val = e1e_wphy(hw, PHY_REG(776, 20), data); | |
2506 | if (ret_val) | |
2507 | return ret_val; | |
2508 | ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00); | |
2509 | if (ret_val) | |
2510 | return ret_val; | |
2511 | e1e_rphy(hw, HV_PM_CTRL, &data); | |
2512 | ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10)); | |
2513 | if (ret_val) | |
2514 | return ret_val; | |
2515 | } | |
2516 | ||
2517 | /* re-enable Rx path after enabling/disabling workaround */ | |
2518 | return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14)); | |
2519 | } | |
2520 | ||
2521 | /** | |
2522 | * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be | |
2523 | * done after every PHY reset. | |
2524 | **/ | |
2525 | static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw) | |
2526 | { | |
2527 | s32 ret_val = 0; | |
2528 | ||
2529 | if (hw->mac.type != e1000_pch2lan) | |
2530 | return 0; | |
2531 | ||
2532 | /* Set MDIO slow mode before any other MDIO access */ | |
2533 | ret_val = e1000_set_mdio_slow_mode_hv(hw); | |
2534 | if (ret_val) | |
2535 | return ret_val; | |
2536 | ||
2537 | ret_val = hw->phy.ops.acquire(hw); | |
2538 | if (ret_val) | |
2539 | return ret_val; | |
2540 | /* set MSE higher to enable link to stay up when noise is high */ | |
2541 | ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034); | |
2542 | if (ret_val) | |
2543 | goto release; | |
2544 | /* drop link after 5 times MSE threshold was reached */ | |
2545 | ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005); | |
2546 | release: | |
2547 | hw->phy.ops.release(hw); | |
2548 | ||
2549 | return ret_val; | |
2550 | } | |
2551 | ||
2552 | /** | |
2553 | * e1000_k1_gig_workaround_lv - K1 Si workaround | |
2554 | * @hw: pointer to the HW structure | |
2555 | * | |
2556 | * Workaround to set the K1 beacon duration for 82579 parts in 10Mbps | |
2557 | * Disable K1 in 1000Mbps and 100Mbps | |
2558 | **/ | |
2559 | static s32 e1000_k1_workaround_lv(struct e1000_hw *hw) | |
2560 | { | |
2561 | s32 ret_val = 0; | |
2562 | u16 status_reg = 0; | |
2563 | ||
2564 | if (hw->mac.type != e1000_pch2lan) | |
2565 | return 0; | |
2566 | ||
2567 | /* Set K1 beacon duration based on 10Mbs speed */ | |
2568 | ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg); | |
2569 | if (ret_val) | |
2570 | return ret_val; | |
2571 | ||
2572 | if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) | |
2573 | == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) { | |
2574 | if (status_reg & | |
2575 | (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) { | |
2576 | u16 pm_phy_reg; | |
2577 | ||
2578 | /* LV 1G/100 Packet drop issue wa */ | |
2579 | ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg); | |
2580 | if (ret_val) | |
2581 | return ret_val; | |
2582 | pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE; | |
2583 | ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg); | |
2584 | if (ret_val) | |
2585 | return ret_val; | |
2586 | } else { | |
2587 | u32 mac_reg; | |
2588 | ||
2589 | mac_reg = er32(FEXTNVM4); | |
2590 | mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK; | |
2591 | mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC; | |
2592 | ew32(FEXTNVM4, mac_reg); | |
2593 | } | |
2594 | } | |
2595 | ||
2596 | return ret_val; | |
2597 | } | |
2598 | ||
2599 | /** | |
2600 | * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware | |
2601 | * @hw: pointer to the HW structure | |
2602 | * @gate: boolean set to true to gate, false to ungate | |
2603 | * | |
2604 | * Gate/ungate the automatic PHY configuration via hardware; perform | |
2605 | * the configuration via software instead. | |
2606 | **/ | |
2607 | static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate) | |
2608 | { | |
2609 | u32 extcnf_ctrl; | |
2610 | ||
2611 | if (hw->mac.type < e1000_pch2lan) | |
2612 | return; | |
2613 | ||
2614 | extcnf_ctrl = er32(EXTCNF_CTRL); | |
2615 | ||
2616 | if (gate) | |
2617 | extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG; | |
2618 | else | |
2619 | extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG; | |
2620 | ||
2621 | ew32(EXTCNF_CTRL, extcnf_ctrl); | |
2622 | } | |
2623 | ||
2624 | /** | |
2625 | * e1000_lan_init_done_ich8lan - Check for PHY config completion | |
2626 | * @hw: pointer to the HW structure | |
2627 | * | |
2628 | * Check the appropriate indication the MAC has finished configuring the | |
2629 | * PHY after a software reset. | |
2630 | **/ | |
2631 | static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw) | |
2632 | { | |
2633 | u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT; | |
2634 | ||
2635 | /* Wait for basic configuration completes before proceeding */ | |
2636 | do { | |
2637 | data = er32(STATUS); | |
2638 | data &= E1000_STATUS_LAN_INIT_DONE; | |
2639 | usleep_range(100, 200); | |
2640 | } while ((!data) && --loop); | |
2641 | ||
2642 | /* If basic configuration is incomplete before the above loop | |
2643 | * count reaches 0, loading the configuration from NVM will | |
2644 | * leave the PHY in a bad state possibly resulting in no link. | |
2645 | */ | |
2646 | if (loop == 0) | |
2647 | e_dbg("LAN_INIT_DONE not set, increase timeout\n"); | |
2648 | ||
2649 | /* Clear the Init Done bit for the next init event */ | |
2650 | data = er32(STATUS); | |
2651 | data &= ~E1000_STATUS_LAN_INIT_DONE; | |
2652 | ew32(STATUS, data); | |
2653 | } | |
2654 | ||
2655 | /** | |
2656 | * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset | |
2657 | * @hw: pointer to the HW structure | |
2658 | **/ | |
2659 | static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw) | |
2660 | { | |
2661 | s32 ret_val = 0; | |
2662 | u16 reg; | |
2663 | ||
2664 | if (hw->phy.ops.check_reset_block(hw)) | |
2665 | return 0; | |
2666 | ||
2667 | /* Allow time for h/w to get to quiescent state after reset */ | |
2668 | usleep_range(10000, 20000); | |
2669 | ||
2670 | /* Perform any necessary post-reset workarounds */ | |
2671 | switch (hw->mac.type) { | |
2672 | case e1000_pchlan: | |
2673 | ret_val = e1000_hv_phy_workarounds_ich8lan(hw); | |
2674 | if (ret_val) | |
2675 | return ret_val; | |
2676 | break; | |
2677 | case e1000_pch2lan: | |
2678 | ret_val = e1000_lv_phy_workarounds_ich8lan(hw); | |
2679 | if (ret_val) | |
2680 | return ret_val; | |
2681 | break; | |
2682 | default: | |
2683 | break; | |
2684 | } | |
2685 | ||
2686 | /* Clear the host wakeup bit after lcd reset */ | |
2687 | if (hw->mac.type >= e1000_pchlan) { | |
2688 | e1e_rphy(hw, BM_PORT_GEN_CFG, ®); | |
2689 | reg &= ~BM_WUC_HOST_WU_BIT; | |
2690 | e1e_wphy(hw, BM_PORT_GEN_CFG, reg); | |
2691 | } | |
2692 | ||
2693 | /* Configure the LCD with the extended configuration region in NVM */ | |
2694 | ret_val = e1000_sw_lcd_config_ich8lan(hw); | |
2695 | if (ret_val) | |
2696 | return ret_val; | |
2697 | ||
2698 | /* Configure the LCD with the OEM bits in NVM */ | |
2699 | ret_val = e1000_oem_bits_config_ich8lan(hw, true); | |
2700 | ||
2701 | if (hw->mac.type == e1000_pch2lan) { | |
2702 | /* Ungate automatic PHY configuration on non-managed 82579 */ | |
2703 | if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { | |
2704 | usleep_range(10000, 20000); | |
2705 | e1000_gate_hw_phy_config_ich8lan(hw, false); | |
2706 | } | |
2707 | ||
2708 | /* Set EEE LPI Update Timer to 200usec */ | |
2709 | ret_val = hw->phy.ops.acquire(hw); | |
2710 | if (ret_val) | |
2711 | return ret_val; | |
2712 | ret_val = e1000_write_emi_reg_locked(hw, | |
2713 | I82579_LPI_UPDATE_TIMER, | |
2714 | 0x1387); | |
2715 | hw->phy.ops.release(hw); | |
2716 | } | |
2717 | ||
2718 | return ret_val; | |
2719 | } | |
2720 | ||
2721 | /** | |
2722 | * e1000_phy_hw_reset_ich8lan - Performs a PHY reset | |
2723 | * @hw: pointer to the HW structure | |
2724 | * | |
2725 | * Resets the PHY | |
2726 | * This is a function pointer entry point called by drivers | |
2727 | * or other shared routines. | |
2728 | **/ | |
2729 | static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) | |
2730 | { | |
2731 | s32 ret_val = 0; | |
2732 | ||
2733 | /* Gate automatic PHY configuration by hardware on non-managed 82579 */ | |
2734 | if ((hw->mac.type == e1000_pch2lan) && | |
2735 | !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) | |
2736 | e1000_gate_hw_phy_config_ich8lan(hw, true); | |
2737 | ||
2738 | ret_val = e1000e_phy_hw_reset_generic(hw); | |
2739 | if (ret_val) | |
2740 | return ret_val; | |
2741 | ||
2742 | return e1000_post_phy_reset_ich8lan(hw); | |
2743 | } | |
2744 | ||
2745 | /** | |
2746 | * e1000_set_lplu_state_pchlan - Set Low Power Link Up state | |
2747 | * @hw: pointer to the HW structure | |
2748 | * @active: true to enable LPLU, false to disable | |
2749 | * | |
2750 | * Sets the LPLU state according to the active flag. For PCH, if OEM write | |
2751 | * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set | |
2752 | * the phy speed. This function will manually set the LPLU bit and restart | |
2753 | * auto-neg as hw would do. D3 and D0 LPLU will call the same function | |
2754 | * since it configures the same bit. | |
2755 | **/ | |
2756 | static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active) | |
2757 | { | |
2758 | s32 ret_val; | |
2759 | u16 oem_reg; | |
2760 | ||
2761 | ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg); | |
2762 | if (ret_val) | |
2763 | return ret_val; | |
2764 | ||
2765 | if (active) | |
2766 | oem_reg |= HV_OEM_BITS_LPLU; | |
2767 | else | |
2768 | oem_reg &= ~HV_OEM_BITS_LPLU; | |
2769 | ||
2770 | if (!hw->phy.ops.check_reset_block(hw)) | |
2771 | oem_reg |= HV_OEM_BITS_RESTART_AN; | |
2772 | ||
2773 | return e1e_wphy(hw, HV_OEM_BITS, oem_reg); | |
2774 | } | |
2775 | ||
2776 | /** | |
2777 | * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state | |
2778 | * @hw: pointer to the HW structure | |
2779 | * @active: true to enable LPLU, false to disable | |
2780 | * | |
2781 | * Sets the LPLU D0 state according to the active flag. When | |
2782 | * activating LPLU this function also disables smart speed | |
2783 | * and vice versa. LPLU will not be activated unless the | |
2784 | * device autonegotiation advertisement meets standards of | |
2785 | * either 10 or 10/100 or 10/100/1000 at all duplexes. | |
2786 | * This is a function pointer entry point only called by | |
2787 | * PHY setup routines. | |
2788 | **/ | |
2789 | static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active) | |
2790 | { | |
2791 | struct e1000_phy_info *phy = &hw->phy; | |
2792 | u32 phy_ctrl; | |
2793 | s32 ret_val = 0; | |
2794 | u16 data; | |
2795 | ||
2796 | if (phy->type == e1000_phy_ife) | |
2797 | return 0; | |
2798 | ||
2799 | phy_ctrl = er32(PHY_CTRL); | |
2800 | ||
2801 | if (active) { | |
2802 | phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; | |
2803 | ew32(PHY_CTRL, phy_ctrl); | |
2804 | ||
2805 | if (phy->type != e1000_phy_igp_3) | |
2806 | return 0; | |
2807 | ||
2808 | /* Call gig speed drop workaround on LPLU before accessing | |
2809 | * any PHY registers | |
2810 | */ | |
2811 | if (hw->mac.type == e1000_ich8lan) | |
2812 | e1000e_gig_downshift_workaround_ich8lan(hw); | |
2813 | ||
2814 | /* When LPLU is enabled, we should disable SmartSpeed */ | |
2815 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); | |
2816 | if (ret_val) | |
2817 | return ret_val; | |
2818 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
2819 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); | |
2820 | if (ret_val) | |
2821 | return ret_val; | |
2822 | } else { | |
2823 | phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; | |
2824 | ew32(PHY_CTRL, phy_ctrl); | |
2825 | ||
2826 | if (phy->type != e1000_phy_igp_3) | |
2827 | return 0; | |
2828 | ||
2829 | /* LPLU and SmartSpeed are mutually exclusive. LPLU is used | |
2830 | * during Dx states where the power conservation is most | |
2831 | * important. During driver activity we should enable | |
2832 | * SmartSpeed, so performance is maintained. | |
2833 | */ | |
2834 | if (phy->smart_speed == e1000_smart_speed_on) { | |
2835 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
2836 | &data); | |
2837 | if (ret_val) | |
2838 | return ret_val; | |
2839 | ||
2840 | data |= IGP01E1000_PSCFR_SMART_SPEED; | |
2841 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
2842 | data); | |
2843 | if (ret_val) | |
2844 | return ret_val; | |
2845 | } else if (phy->smart_speed == e1000_smart_speed_off) { | |
2846 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
2847 | &data); | |
2848 | if (ret_val) | |
2849 | return ret_val; | |
2850 | ||
2851 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
2852 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
2853 | data); | |
2854 | if (ret_val) | |
2855 | return ret_val; | |
2856 | } | |
2857 | } | |
2858 | ||
2859 | return 0; | |
2860 | } | |
2861 | ||
2862 | /** | |
2863 | * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state | |
2864 | * @hw: pointer to the HW structure | |
2865 | * @active: true to enable LPLU, false to disable | |
2866 | * | |
2867 | * Sets the LPLU D3 state according to the active flag. When | |
2868 | * activating LPLU this function also disables smart speed | |
2869 | * and vice versa. LPLU will not be activated unless the | |
2870 | * device autonegotiation advertisement meets standards of | |
2871 | * either 10 or 10/100 or 10/100/1000 at all duplexes. | |
2872 | * This is a function pointer entry point only called by | |
2873 | * PHY setup routines. | |
2874 | **/ | |
2875 | static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) | |
2876 | { | |
2877 | struct e1000_phy_info *phy = &hw->phy; | |
2878 | u32 phy_ctrl; | |
2879 | s32 ret_val = 0; | |
2880 | u16 data; | |
2881 | ||
2882 | phy_ctrl = er32(PHY_CTRL); | |
2883 | ||
2884 | if (!active) { | |
2885 | phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; | |
2886 | ew32(PHY_CTRL, phy_ctrl); | |
2887 | ||
2888 | if (phy->type != e1000_phy_igp_3) | |
2889 | return 0; | |
2890 | ||
2891 | /* LPLU and SmartSpeed are mutually exclusive. LPLU is used | |
2892 | * during Dx states where the power conservation is most | |
2893 | * important. During driver activity we should enable | |
2894 | * SmartSpeed, so performance is maintained. | |
2895 | */ | |
2896 | if (phy->smart_speed == e1000_smart_speed_on) { | |
2897 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
2898 | &data); | |
2899 | if (ret_val) | |
2900 | return ret_val; | |
2901 | ||
2902 | data |= IGP01E1000_PSCFR_SMART_SPEED; | |
2903 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
2904 | data); | |
2905 | if (ret_val) | |
2906 | return ret_val; | |
2907 | } else if (phy->smart_speed == e1000_smart_speed_off) { | |
2908 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
2909 | &data); | |
2910 | if (ret_val) | |
2911 | return ret_val; | |
2912 | ||
2913 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
2914 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
2915 | data); | |
2916 | if (ret_val) | |
2917 | return ret_val; | |
2918 | } | |
2919 | } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || | |
2920 | (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || | |
2921 | (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { | |
2922 | phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; | |
2923 | ew32(PHY_CTRL, phy_ctrl); | |
2924 | ||
2925 | if (phy->type != e1000_phy_igp_3) | |
2926 | return 0; | |
2927 | ||
2928 | /* Call gig speed drop workaround on LPLU before accessing | |
2929 | * any PHY registers | |
2930 | */ | |
2931 | if (hw->mac.type == e1000_ich8lan) | |
2932 | e1000e_gig_downshift_workaround_ich8lan(hw); | |
2933 | ||
2934 | /* When LPLU is enabled, we should disable SmartSpeed */ | |
2935 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); | |
2936 | if (ret_val) | |
2937 | return ret_val; | |
2938 | ||
2939 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
2940 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); | |
2941 | } | |
2942 | ||
2943 | return ret_val; | |
2944 | } | |
2945 | ||
2946 | /** | |
2947 | * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1 | |
2948 | * @hw: pointer to the HW structure | |
2949 | * @bank: pointer to the variable that returns the active bank | |
2950 | * | |
2951 | * Reads signature byte from the NVM using the flash access registers. | |
2952 | * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank. | |
2953 | **/ | |
2954 | static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank) | |
2955 | { | |
2956 | u32 eecd; | |
2957 | struct e1000_nvm_info *nvm = &hw->nvm; | |
2958 | u32 bank1_offset = nvm->flash_bank_size * sizeof(u16); | |
2959 | u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1; | |
2960 | u8 sig_byte = 0; | |
2961 | s32 ret_val; | |
2962 | ||
2963 | switch (hw->mac.type) { | |
2964 | case e1000_ich8lan: | |
2965 | case e1000_ich9lan: | |
2966 | eecd = er32(EECD); | |
2967 | if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) == | |
2968 | E1000_EECD_SEC1VAL_VALID_MASK) { | |
2969 | if (eecd & E1000_EECD_SEC1VAL) | |
2970 | *bank = 1; | |
2971 | else | |
2972 | *bank = 0; | |
2973 | ||
2974 | return 0; | |
2975 | } | |
2976 | e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n"); | |
2977 | /* fall-thru */ | |
2978 | default: | |
2979 | /* set bank to 0 in case flash read fails */ | |
2980 | *bank = 0; | |
2981 | ||
2982 | /* Check bank 0 */ | |
2983 | ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset, | |
2984 | &sig_byte); | |
2985 | if (ret_val) | |
2986 | return ret_val; | |
2987 | if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == | |
2988 | E1000_ICH_NVM_SIG_VALUE) { | |
2989 | *bank = 0; | |
2990 | return 0; | |
2991 | } | |
2992 | ||
2993 | /* Check bank 1 */ | |
2994 | ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset + | |
2995 | bank1_offset, | |
2996 | &sig_byte); | |
2997 | if (ret_val) | |
2998 | return ret_val; | |
2999 | if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == | |
3000 | E1000_ICH_NVM_SIG_VALUE) { | |
3001 | *bank = 1; | |
3002 | return 0; | |
3003 | } | |
3004 | ||
3005 | e_dbg("ERROR: No valid NVM bank present\n"); | |
3006 | return -E1000_ERR_NVM; | |
3007 | } | |
3008 | } | |
3009 | ||
3010 | /** | |
3011 | * e1000_read_nvm_ich8lan - Read word(s) from the NVM | |
3012 | * @hw: pointer to the HW structure | |
3013 | * @offset: The offset (in bytes) of the word(s) to read. | |
3014 | * @words: Size of data to read in words | |
3015 | * @data: Pointer to the word(s) to read at offset. | |
3016 | * | |
3017 | * Reads a word(s) from the NVM using the flash access registers. | |
3018 | **/ | |
3019 | static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, | |
3020 | u16 *data) | |
3021 | { | |
3022 | struct e1000_nvm_info *nvm = &hw->nvm; | |
3023 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; | |
3024 | u32 act_offset; | |
3025 | s32 ret_val = 0; | |
3026 | u32 bank = 0; | |
3027 | u16 i, word; | |
3028 | ||
3029 | if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || | |
3030 | (words == 0)) { | |
3031 | e_dbg("nvm parameter(s) out of bounds\n"); | |
3032 | ret_val = -E1000_ERR_NVM; | |
3033 | goto out; | |
3034 | } | |
3035 | ||
3036 | nvm->ops.acquire(hw); | |
3037 | ||
3038 | ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); | |
3039 | if (ret_val) { | |
3040 | e_dbg("Could not detect valid bank, assuming bank 0\n"); | |
3041 | bank = 0; | |
3042 | } | |
3043 | ||
3044 | act_offset = (bank) ? nvm->flash_bank_size : 0; | |
3045 | act_offset += offset; | |
3046 | ||
3047 | ret_val = 0; | |
3048 | for (i = 0; i < words; i++) { | |
3049 | if (dev_spec->shadow_ram[offset + i].modified) { | |
3050 | data[i] = dev_spec->shadow_ram[offset + i].value; | |
3051 | } else { | |
3052 | ret_val = e1000_read_flash_word_ich8lan(hw, | |
3053 | act_offset + i, | |
3054 | &word); | |
3055 | if (ret_val) | |
3056 | break; | |
3057 | data[i] = word; | |
3058 | } | |
3059 | } | |
3060 | ||
3061 | nvm->ops.release(hw); | |
3062 | ||
3063 | out: | |
3064 | if (ret_val) | |
3065 | e_dbg("NVM read error: %d\n", ret_val); | |
3066 | ||
3067 | return ret_val; | |
3068 | } | |
3069 | ||
3070 | /** | |
3071 | * e1000_flash_cycle_init_ich8lan - Initialize flash | |
3072 | * @hw: pointer to the HW structure | |
3073 | * | |
3074 | * This function does initial flash setup so that a new read/write/erase cycle | |
3075 | * can be started. | |
3076 | **/ | |
3077 | static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) | |
3078 | { | |
3079 | union ich8_hws_flash_status hsfsts; | |
3080 | s32 ret_val = -E1000_ERR_NVM; | |
3081 | ||
3082 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); | |
3083 | ||
3084 | /* Check if the flash descriptor is valid */ | |
3085 | if (!hsfsts.hsf_status.fldesvalid) { | |
3086 | e_dbg("Flash descriptor invalid. SW Sequencing must be used.\n"); | |
3087 | return -E1000_ERR_NVM; | |
3088 | } | |
3089 | ||
3090 | /* Clear FCERR and DAEL in hw status by writing 1 */ | |
3091 | hsfsts.hsf_status.flcerr = 1; | |
3092 | hsfsts.hsf_status.dael = 1; | |
3093 | ||
3094 | ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); | |
3095 | ||
3096 | /* Either we should have a hardware SPI cycle in progress | |
3097 | * bit to check against, in order to start a new cycle or | |
3098 | * FDONE bit should be changed in the hardware so that it | |
3099 | * is 1 after hardware reset, which can then be used as an | |
3100 | * indication whether a cycle is in progress or has been | |
3101 | * completed. | |
3102 | */ | |
3103 | ||
3104 | if (!hsfsts.hsf_status.flcinprog) { | |
3105 | /* There is no cycle running at present, | |
3106 | * so we can start a cycle. | |
3107 | * Begin by setting Flash Cycle Done. | |
3108 | */ | |
3109 | hsfsts.hsf_status.flcdone = 1; | |
3110 | ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); | |
3111 | ret_val = 0; | |
3112 | } else { | |
3113 | s32 i; | |
3114 | ||
3115 | /* Otherwise poll for sometime so the current | |
3116 | * cycle has a chance to end before giving up. | |
3117 | */ | |
3118 | for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) { | |
3119 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); | |
3120 | if (!hsfsts.hsf_status.flcinprog) { | |
3121 | ret_val = 0; | |
3122 | break; | |
3123 | } | |
3124 | udelay(1); | |
3125 | } | |
3126 | if (!ret_val) { | |
3127 | /* Successful in waiting for previous cycle to timeout, | |
3128 | * now set the Flash Cycle Done. | |
3129 | */ | |
3130 | hsfsts.hsf_status.flcdone = 1; | |
3131 | ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); | |
3132 | } else { | |
3133 | e_dbg("Flash controller busy, cannot get access\n"); | |
3134 | } | |
3135 | } | |
3136 | ||
3137 | return ret_val; | |
3138 | } | |
3139 | ||
3140 | /** | |
3141 | * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase) | |
3142 | * @hw: pointer to the HW structure | |
3143 | * @timeout: maximum time to wait for completion | |
3144 | * | |
3145 | * This function starts a flash cycle and waits for its completion. | |
3146 | **/ | |
3147 | static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout) | |
3148 | { | |
3149 | union ich8_hws_flash_ctrl hsflctl; | |
3150 | union ich8_hws_flash_status hsfsts; | |
3151 | u32 i = 0; | |
3152 | ||
3153 | /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ | |
3154 | hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); | |
3155 | hsflctl.hsf_ctrl.flcgo = 1; | |
3156 | ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); | |
3157 | ||
3158 | /* wait till FDONE bit is set to 1 */ | |
3159 | do { | |
3160 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); | |
3161 | if (hsfsts.hsf_status.flcdone) | |
3162 | break; | |
3163 | udelay(1); | |
3164 | } while (i++ < timeout); | |
3165 | ||
3166 | if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr) | |
3167 | return 0; | |
3168 | ||
3169 | return -E1000_ERR_NVM; | |
3170 | } | |
3171 | ||
3172 | /** | |
3173 | * e1000_read_flash_word_ich8lan - Read word from flash | |
3174 | * @hw: pointer to the HW structure | |
3175 | * @offset: offset to data location | |
3176 | * @data: pointer to the location for storing the data | |
3177 | * | |
3178 | * Reads the flash word at offset into data. Offset is converted | |
3179 | * to bytes before read. | |
3180 | **/ | |
3181 | static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, | |
3182 | u16 *data) | |
3183 | { | |
3184 | /* Must convert offset into bytes. */ | |
3185 | offset <<= 1; | |
3186 | ||
3187 | return e1000_read_flash_data_ich8lan(hw, offset, 2, data); | |
3188 | } | |
3189 | ||
3190 | /** | |
3191 | * e1000_read_flash_byte_ich8lan - Read byte from flash | |
3192 | * @hw: pointer to the HW structure | |
3193 | * @offset: The offset of the byte to read. | |
3194 | * @data: Pointer to a byte to store the value read. | |
3195 | * | |
3196 | * Reads a single byte from the NVM using the flash access registers. | |
3197 | **/ | |
3198 | static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, | |
3199 | u8 *data) | |
3200 | { | |
3201 | s32 ret_val; | |
3202 | u16 word = 0; | |
3203 | ||
3204 | ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word); | |
3205 | if (ret_val) | |
3206 | return ret_val; | |
3207 | ||
3208 | *data = (u8)word; | |
3209 | ||
3210 | return 0; | |
3211 | } | |
3212 | ||
3213 | /** | |
3214 | * e1000_read_flash_data_ich8lan - Read byte or word from NVM | |
3215 | * @hw: pointer to the HW structure | |
3216 | * @offset: The offset (in bytes) of the byte or word to read. | |
3217 | * @size: Size of data to read, 1=byte 2=word | |
3218 | * @data: Pointer to the word to store the value read. | |
3219 | * | |
3220 | * Reads a byte or word from the NVM using the flash access registers. | |
3221 | **/ | |
3222 | static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, | |
3223 | u8 size, u16 *data) | |
3224 | { | |
3225 | union ich8_hws_flash_status hsfsts; | |
3226 | union ich8_hws_flash_ctrl hsflctl; | |
3227 | u32 flash_linear_addr; | |
3228 | u32 flash_data = 0; | |
3229 | s32 ret_val = -E1000_ERR_NVM; | |
3230 | u8 count = 0; | |
3231 | ||
3232 | if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) | |
3233 | return -E1000_ERR_NVM; | |
3234 | ||
3235 | flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + | |
3236 | hw->nvm.flash_base_addr); | |
3237 | ||
3238 | do { | |
3239 | udelay(1); | |
3240 | /* Steps */ | |
3241 | ret_val = e1000_flash_cycle_init_ich8lan(hw); | |
3242 | if (ret_val) | |
3243 | break; | |
3244 | ||
3245 | hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); | |
3246 | /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ | |
3247 | hsflctl.hsf_ctrl.fldbcount = size - 1; | |
3248 | hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; | |
3249 | ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); | |
3250 | ||
3251 | ew32flash(ICH_FLASH_FADDR, flash_linear_addr); | |
3252 | ||
3253 | ret_val = | |
3254 | e1000_flash_cycle_ich8lan(hw, | |
3255 | ICH_FLASH_READ_COMMAND_TIMEOUT); | |
3256 | ||
3257 | /* Check if FCERR is set to 1, if set to 1, clear it | |
3258 | * and try the whole sequence a few more times, else | |
3259 | * read in (shift in) the Flash Data0, the order is | |
3260 | * least significant byte first msb to lsb | |
3261 | */ | |
3262 | if (!ret_val) { | |
3263 | flash_data = er32flash(ICH_FLASH_FDATA0); | |
3264 | if (size == 1) | |
3265 | *data = (u8)(flash_data & 0x000000FF); | |
3266 | else if (size == 2) | |
3267 | *data = (u16)(flash_data & 0x0000FFFF); | |
3268 | break; | |
3269 | } else { | |
3270 | /* If we've gotten here, then things are probably | |
3271 | * completely hosed, but if the error condition is | |
3272 | * detected, it won't hurt to give it another try... | |
3273 | * ICH_FLASH_CYCLE_REPEAT_COUNT times. | |
3274 | */ | |
3275 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); | |
3276 | if (hsfsts.hsf_status.flcerr) { | |
3277 | /* Repeat for some time before giving up. */ | |
3278 | continue; | |
3279 | } else if (!hsfsts.hsf_status.flcdone) { | |
3280 | e_dbg("Timeout error - flash cycle did not complete.\n"); | |
3281 | break; | |
3282 | } | |
3283 | } | |
3284 | } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); | |
3285 | ||
3286 | return ret_val; | |
3287 | } | |
3288 | ||
3289 | /** | |
3290 | * e1000_write_nvm_ich8lan - Write word(s) to the NVM | |
3291 | * @hw: pointer to the HW structure | |
3292 | * @offset: The offset (in bytes) of the word(s) to write. | |
3293 | * @words: Size of data to write in words | |
3294 | * @data: Pointer to the word(s) to write at offset. | |
3295 | * | |
3296 | * Writes a byte or word to the NVM using the flash access registers. | |
3297 | **/ | |
3298 | static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, | |
3299 | u16 *data) | |
3300 | { | |
3301 | struct e1000_nvm_info *nvm = &hw->nvm; | |
3302 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; | |
3303 | u16 i; | |
3304 | ||
3305 | if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || | |
3306 | (words == 0)) { | |
3307 | e_dbg("nvm parameter(s) out of bounds\n"); | |
3308 | return -E1000_ERR_NVM; | |
3309 | } | |
3310 | ||
3311 | nvm->ops.acquire(hw); | |
3312 | ||
3313 | for (i = 0; i < words; i++) { | |
3314 | dev_spec->shadow_ram[offset + i].modified = true; | |
3315 | dev_spec->shadow_ram[offset + i].value = data[i]; | |
3316 | } | |
3317 | ||
3318 | nvm->ops.release(hw); | |
3319 | ||
3320 | return 0; | |
3321 | } | |
3322 | ||
3323 | /** | |
3324 | * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM | |
3325 | * @hw: pointer to the HW structure | |
3326 | * | |
3327 | * The NVM checksum is updated by calling the generic update_nvm_checksum, | |
3328 | * which writes the checksum to the shadow ram. The changes in the shadow | |
3329 | * ram are then committed to the EEPROM by processing each bank at a time | |
3330 | * checking for the modified bit and writing only the pending changes. | |
3331 | * After a successful commit, the shadow ram is cleared and is ready for | |
3332 | * future writes. | |
3333 | **/ | |
3334 | static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) | |
3335 | { | |
3336 | struct e1000_nvm_info *nvm = &hw->nvm; | |
3337 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; | |
3338 | u32 i, act_offset, new_bank_offset, old_bank_offset, bank; | |
3339 | s32 ret_val; | |
3340 | u16 data; | |
3341 | ||
3342 | ret_val = e1000e_update_nvm_checksum_generic(hw); | |
3343 | if (ret_val) | |
3344 | goto out; | |
3345 | ||
3346 | if (nvm->type != e1000_nvm_flash_sw) | |
3347 | goto out; | |
3348 | ||
3349 | nvm->ops.acquire(hw); | |
3350 | ||
3351 | /* We're writing to the opposite bank so if we're on bank 1, | |
3352 | * write to bank 0 etc. We also need to erase the segment that | |
3353 | * is going to be written | |
3354 | */ | |
3355 | ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); | |
3356 | if (ret_val) { | |
3357 | e_dbg("Could not detect valid bank, assuming bank 0\n"); | |
3358 | bank = 0; | |
3359 | } | |
3360 | ||
3361 | if (bank == 0) { | |
3362 | new_bank_offset = nvm->flash_bank_size; | |
3363 | old_bank_offset = 0; | |
3364 | ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); | |
3365 | if (ret_val) | |
3366 | goto release; | |
3367 | } else { | |
3368 | old_bank_offset = nvm->flash_bank_size; | |
3369 | new_bank_offset = 0; | |
3370 | ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); | |
3371 | if (ret_val) | |
3372 | goto release; | |
3373 | } | |
3374 | ||
3375 | for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { | |
3376 | /* Determine whether to write the value stored | |
3377 | * in the other NVM bank or a modified value stored | |
3378 | * in the shadow RAM | |
3379 | */ | |
3380 | if (dev_spec->shadow_ram[i].modified) { | |
3381 | data = dev_spec->shadow_ram[i].value; | |
3382 | } else { | |
3383 | ret_val = e1000_read_flash_word_ich8lan(hw, i + | |
3384 | old_bank_offset, | |
3385 | &data); | |
3386 | if (ret_val) | |
3387 | break; | |
3388 | } | |
3389 | ||
3390 | /* If the word is 0x13, then make sure the signature bits | |
3391 | * (15:14) are 11b until the commit has completed. | |
3392 | * This will allow us to write 10b which indicates the | |
3393 | * signature is valid. We want to do this after the write | |
3394 | * has completed so that we don't mark the segment valid | |
3395 | * while the write is still in progress | |
3396 | */ | |
3397 | if (i == E1000_ICH_NVM_SIG_WORD) | |
3398 | data |= E1000_ICH_NVM_SIG_MASK; | |
3399 | ||
3400 | /* Convert offset to bytes. */ | |
3401 | act_offset = (i + new_bank_offset) << 1; | |
3402 | ||
3403 | usleep_range(100, 200); | |
3404 | /* Write the bytes to the new bank. */ | |
3405 | ret_val = e1000_retry_write_flash_byte_ich8lan(hw, | |
3406 | act_offset, | |
3407 | (u8)data); | |
3408 | if (ret_val) | |
3409 | break; | |
3410 | ||
3411 | usleep_range(100, 200); | |
3412 | ret_val = e1000_retry_write_flash_byte_ich8lan(hw, | |
3413 | act_offset + 1, | |
3414 | (u8)(data >> 8)); | |
3415 | if (ret_val) | |
3416 | break; | |
3417 | } | |
3418 | ||
3419 | /* Don't bother writing the segment valid bits if sector | |
3420 | * programming failed. | |
3421 | */ | |
3422 | if (ret_val) { | |
3423 | /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */ | |
3424 | e_dbg("Flash commit failed.\n"); | |
3425 | goto release; | |
3426 | } | |
3427 | ||
3428 | /* Finally validate the new segment by setting bit 15:14 | |
3429 | * to 10b in word 0x13 , this can be done without an | |
3430 | * erase as well since these bits are 11 to start with | |
3431 | * and we need to change bit 14 to 0b | |
3432 | */ | |
3433 | act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; | |
3434 | ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data); | |
3435 | if (ret_val) | |
3436 | goto release; | |
3437 | ||
3438 | data &= 0xBFFF; | |
3439 | ret_val = e1000_retry_write_flash_byte_ich8lan(hw, | |
3440 | act_offset * 2 + 1, | |
3441 | (u8)(data >> 8)); | |
3442 | if (ret_val) | |
3443 | goto release; | |
3444 | ||
3445 | /* And invalidate the previously valid segment by setting | |
3446 | * its signature word (0x13) high_byte to 0b. This can be | |
3447 | * done without an erase because flash erase sets all bits | |
3448 | * to 1's. We can write 1's to 0's without an erase | |
3449 | */ | |
3450 | act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1; | |
3451 | ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0); | |
3452 | if (ret_val) | |
3453 | goto release; | |
3454 | ||
3455 | /* Great! Everything worked, we can now clear the cached entries. */ | |
3456 | for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { | |
3457 | dev_spec->shadow_ram[i].modified = false; | |
3458 | dev_spec->shadow_ram[i].value = 0xFFFF; | |
3459 | } | |
3460 | ||
3461 | release: | |
3462 | nvm->ops.release(hw); | |
3463 | ||
3464 | /* Reload the EEPROM, or else modifications will not appear | |
3465 | * until after the next adapter reset. | |
3466 | */ | |
3467 | if (!ret_val) { | |
3468 | nvm->ops.reload(hw); | |
3469 | usleep_range(10000, 20000); | |
3470 | } | |
3471 | ||
3472 | out: | |
3473 | if (ret_val) | |
3474 | e_dbg("NVM update error: %d\n", ret_val); | |
3475 | ||
3476 | return ret_val; | |
3477 | } | |
3478 | ||
3479 | /** | |
3480 | * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum | |
3481 | * @hw: pointer to the HW structure | |
3482 | * | |
3483 | * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19. | |
3484 | * If the bit is 0, that the EEPROM had been modified, but the checksum was not | |
3485 | * calculated, in which case we need to calculate the checksum and set bit 6. | |
3486 | **/ | |
3487 | static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw) | |
3488 | { | |
3489 | s32 ret_val; | |
3490 | u16 data; | |
3491 | u16 word; | |
3492 | u16 valid_csum_mask; | |
3493 | ||
3494 | /* Read NVM and check Invalid Image CSUM bit. If this bit is 0, | |
3495 | * the checksum needs to be fixed. This bit is an indication that | |
3496 | * the NVM was prepared by OEM software and did not calculate | |
3497 | * the checksum...a likely scenario. | |
3498 | */ | |
3499 | switch (hw->mac.type) { | |
3500 | case e1000_pch_lpt: | |
3501 | word = NVM_COMPAT; | |
3502 | valid_csum_mask = NVM_COMPAT_VALID_CSUM; | |
3503 | break; | |
3504 | default: | |
3505 | word = NVM_FUTURE_INIT_WORD1; | |
3506 | valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM; | |
3507 | break; | |
3508 | } | |
3509 | ||
3510 | ret_val = e1000_read_nvm(hw, word, 1, &data); | |
3511 | if (ret_val) | |
3512 | return ret_val; | |
3513 | ||
3514 | if (!(data & valid_csum_mask)) { | |
3515 | data |= valid_csum_mask; | |
3516 | ret_val = e1000_write_nvm(hw, word, 1, &data); | |
3517 | if (ret_val) | |
3518 | return ret_val; | |
3519 | ret_val = e1000e_update_nvm_checksum(hw); | |
3520 | if (ret_val) | |
3521 | return ret_val; | |
3522 | } | |
3523 | ||
3524 | return e1000e_validate_nvm_checksum_generic(hw); | |
3525 | } | |
3526 | ||
3527 | /** | |
3528 | * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only | |
3529 | * @hw: pointer to the HW structure | |
3530 | * | |
3531 | * To prevent malicious write/erase of the NVM, set it to be read-only | |
3532 | * so that the hardware ignores all write/erase cycles of the NVM via | |
3533 | * the flash control registers. The shadow-ram copy of the NVM will | |
3534 | * still be updated, however any updates to this copy will not stick | |
3535 | * across driver reloads. | |
3536 | **/ | |
3537 | void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw) | |
3538 | { | |
3539 | struct e1000_nvm_info *nvm = &hw->nvm; | |
3540 | union ich8_flash_protected_range pr0; | |
3541 | union ich8_hws_flash_status hsfsts; | |
3542 | u32 gfpreg; | |
3543 | ||
3544 | nvm->ops.acquire(hw); | |
3545 | ||
3546 | gfpreg = er32flash(ICH_FLASH_GFPREG); | |
3547 | ||
3548 | /* Write-protect GbE Sector of NVM */ | |
3549 | pr0.regval = er32flash(ICH_FLASH_PR0); | |
3550 | pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK; | |
3551 | pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK); | |
3552 | pr0.range.wpe = true; | |
3553 | ew32flash(ICH_FLASH_PR0, pr0.regval); | |
3554 | ||
3555 | /* Lock down a subset of GbE Flash Control Registers, e.g. | |
3556 | * PR0 to prevent the write-protection from being lifted. | |
3557 | * Once FLOCKDN is set, the registers protected by it cannot | |
3558 | * be written until FLOCKDN is cleared by a hardware reset. | |
3559 | */ | |
3560 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); | |
3561 | hsfsts.hsf_status.flockdn = true; | |
3562 | ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval); | |
3563 | ||
3564 | nvm->ops.release(hw); | |
3565 | } | |
3566 | ||
3567 | /** | |
3568 | * e1000_write_flash_data_ich8lan - Writes bytes to the NVM | |
3569 | * @hw: pointer to the HW structure | |
3570 | * @offset: The offset (in bytes) of the byte/word to read. | |
3571 | * @size: Size of data to read, 1=byte 2=word | |
3572 | * @data: The byte(s) to write to the NVM. | |
3573 | * | |
3574 | * Writes one/two bytes to the NVM using the flash access registers. | |
3575 | **/ | |
3576 | static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, | |
3577 | u8 size, u16 data) | |
3578 | { | |
3579 | union ich8_hws_flash_status hsfsts; | |
3580 | union ich8_hws_flash_ctrl hsflctl; | |
3581 | u32 flash_linear_addr; | |
3582 | u32 flash_data = 0; | |
3583 | s32 ret_val; | |
3584 | u8 count = 0; | |
3585 | ||
3586 | if (size < 1 || size > 2 || data > size * 0xff || | |
3587 | offset > ICH_FLASH_LINEAR_ADDR_MASK) | |
3588 | return -E1000_ERR_NVM; | |
3589 | ||
3590 | flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + | |
3591 | hw->nvm.flash_base_addr); | |
3592 | ||
3593 | do { | |
3594 | udelay(1); | |
3595 | /* Steps */ | |
3596 | ret_val = e1000_flash_cycle_init_ich8lan(hw); | |
3597 | if (ret_val) | |
3598 | break; | |
3599 | ||
3600 | hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); | |
3601 | /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ | |
3602 | hsflctl.hsf_ctrl.fldbcount = size - 1; | |
3603 | hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; | |
3604 | ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); | |
3605 | ||
3606 | ew32flash(ICH_FLASH_FADDR, flash_linear_addr); | |
3607 | ||
3608 | if (size == 1) | |
3609 | flash_data = (u32)data & 0x00FF; | |
3610 | else | |
3611 | flash_data = (u32)data; | |
3612 | ||
3613 | ew32flash(ICH_FLASH_FDATA0, flash_data); | |
3614 | ||
3615 | /* check if FCERR is set to 1 , if set to 1, clear it | |
3616 | * and try the whole sequence a few more times else done | |
3617 | */ | |
3618 | ret_val = | |
3619 | e1000_flash_cycle_ich8lan(hw, | |
3620 | ICH_FLASH_WRITE_COMMAND_TIMEOUT); | |
3621 | if (!ret_val) | |
3622 | break; | |
3623 | ||
3624 | /* If we're here, then things are most likely | |
3625 | * completely hosed, but if the error condition | |
3626 | * is detected, it won't hurt to give it another | |
3627 | * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. | |
3628 | */ | |
3629 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); | |
3630 | if (hsfsts.hsf_status.flcerr) | |
3631 | /* Repeat for some time before giving up. */ | |
3632 | continue; | |
3633 | if (!hsfsts.hsf_status.flcdone) { | |
3634 | e_dbg("Timeout error - flash cycle did not complete.\n"); | |
3635 | break; | |
3636 | } | |
3637 | } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); | |
3638 | ||
3639 | return ret_val; | |
3640 | } | |
3641 | ||
3642 | /** | |
3643 | * e1000_write_flash_byte_ich8lan - Write a single byte to NVM | |
3644 | * @hw: pointer to the HW structure | |
3645 | * @offset: The index of the byte to read. | |
3646 | * @data: The byte to write to the NVM. | |
3647 | * | |
3648 | * Writes a single byte to the NVM using the flash access registers. | |
3649 | **/ | |
3650 | static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, | |
3651 | u8 data) | |
3652 | { | |
3653 | u16 word = (u16)data; | |
3654 | ||
3655 | return e1000_write_flash_data_ich8lan(hw, offset, 1, word); | |
3656 | } | |
3657 | ||
3658 | /** | |
3659 | * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM | |
3660 | * @hw: pointer to the HW structure | |
3661 | * @offset: The offset of the byte to write. | |
3662 | * @byte: The byte to write to the NVM. | |
3663 | * | |
3664 | * Writes a single byte to the NVM using the flash access registers. | |
3665 | * Goes through a retry algorithm before giving up. | |
3666 | **/ | |
3667 | static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, | |
3668 | u32 offset, u8 byte) | |
3669 | { | |
3670 | s32 ret_val; | |
3671 | u16 program_retries; | |
3672 | ||
3673 | ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); | |
3674 | if (!ret_val) | |
3675 | return ret_val; | |
3676 | ||
3677 | for (program_retries = 0; program_retries < 100; program_retries++) { | |
3678 | e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset); | |
3679 | usleep_range(100, 200); | |
3680 | ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); | |
3681 | if (!ret_val) | |
3682 | break; | |
3683 | } | |
3684 | if (program_retries == 100) | |
3685 | return -E1000_ERR_NVM; | |
3686 | ||
3687 | return 0; | |
3688 | } | |
3689 | ||
3690 | /** | |
3691 | * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM | |
3692 | * @hw: pointer to the HW structure | |
3693 | * @bank: 0 for first bank, 1 for second bank, etc. | |
3694 | * | |
3695 | * Erases the bank specified. Each bank is a 4k block. Banks are 0 based. | |
3696 | * bank N is 4096 * N + flash_reg_addr. | |
3697 | **/ | |
3698 | static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) | |
3699 | { | |
3700 | struct e1000_nvm_info *nvm = &hw->nvm; | |
3701 | union ich8_hws_flash_status hsfsts; | |
3702 | union ich8_hws_flash_ctrl hsflctl; | |
3703 | u32 flash_linear_addr; | |
3704 | /* bank size is in 16bit words - adjust to bytes */ | |
3705 | u32 flash_bank_size = nvm->flash_bank_size * 2; | |
3706 | s32 ret_val; | |
3707 | s32 count = 0; | |
3708 | s32 j, iteration, sector_size; | |
3709 | ||
3710 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); | |
3711 | ||
3712 | /* Determine HW Sector size: Read BERASE bits of hw flash status | |
3713 | * register | |
3714 | * 00: The Hw sector is 256 bytes, hence we need to erase 16 | |
3715 | * consecutive sectors. The start index for the nth Hw sector | |
3716 | * can be calculated as = bank * 4096 + n * 256 | |
3717 | * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. | |
3718 | * The start index for the nth Hw sector can be calculated | |
3719 | * as = bank * 4096 | |
3720 | * 10: The Hw sector is 8K bytes, nth sector = bank * 8192 | |
3721 | * (ich9 only, otherwise error condition) | |
3722 | * 11: The Hw sector is 64K bytes, nth sector = bank * 65536 | |
3723 | */ | |
3724 | switch (hsfsts.hsf_status.berasesz) { | |
3725 | case 0: | |
3726 | /* Hw sector size 256 */ | |
3727 | sector_size = ICH_FLASH_SEG_SIZE_256; | |
3728 | iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256; | |
3729 | break; | |
3730 | case 1: | |
3731 | sector_size = ICH_FLASH_SEG_SIZE_4K; | |
3732 | iteration = 1; | |
3733 | break; | |
3734 | case 2: | |
3735 | sector_size = ICH_FLASH_SEG_SIZE_8K; | |
3736 | iteration = 1; | |
3737 | break; | |
3738 | case 3: | |
3739 | sector_size = ICH_FLASH_SEG_SIZE_64K; | |
3740 | iteration = 1; | |
3741 | break; | |
3742 | default: | |
3743 | return -E1000_ERR_NVM; | |
3744 | } | |
3745 | ||
3746 | /* Start with the base address, then add the sector offset. */ | |
3747 | flash_linear_addr = hw->nvm.flash_base_addr; | |
3748 | flash_linear_addr += (bank) ? flash_bank_size : 0; | |
3749 | ||
3750 | for (j = 0; j < iteration; j++) { | |
3751 | do { | |
3752 | u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT; | |
3753 | ||
3754 | /* Steps */ | |
3755 | ret_val = e1000_flash_cycle_init_ich8lan(hw); | |
3756 | if (ret_val) | |
3757 | return ret_val; | |
3758 | ||
3759 | /* Write a value 11 (block Erase) in Flash | |
3760 | * Cycle field in hw flash control | |
3761 | */ | |
3762 | hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); | |
3763 | hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; | |
3764 | ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); | |
3765 | ||
3766 | /* Write the last 24 bits of an index within the | |
3767 | * block into Flash Linear address field in Flash | |
3768 | * Address. | |
3769 | */ | |
3770 | flash_linear_addr += (j * sector_size); | |
3771 | ew32flash(ICH_FLASH_FADDR, flash_linear_addr); | |
3772 | ||
3773 | ret_val = e1000_flash_cycle_ich8lan(hw, timeout); | |
3774 | if (!ret_val) | |
3775 | break; | |
3776 | ||
3777 | /* Check if FCERR is set to 1. If 1, | |
3778 | * clear it and try the whole sequence | |
3779 | * a few more times else Done | |
3780 | */ | |
3781 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); | |
3782 | if (hsfsts.hsf_status.flcerr) | |
3783 | /* repeat for some time before giving up */ | |
3784 | continue; | |
3785 | else if (!hsfsts.hsf_status.flcdone) | |
3786 | return ret_val; | |
3787 | } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT); | |
3788 | } | |
3789 | ||
3790 | return 0; | |
3791 | } | |
3792 | ||
3793 | /** | |
3794 | * e1000_valid_led_default_ich8lan - Set the default LED settings | |
3795 | * @hw: pointer to the HW structure | |
3796 | * @data: Pointer to the LED settings | |
3797 | * | |
3798 | * Reads the LED default settings from the NVM to data. If the NVM LED | |
3799 | * settings is all 0's or F's, set the LED default to a valid LED default | |
3800 | * setting. | |
3801 | **/ | |
3802 | static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data) | |
3803 | { | |
3804 | s32 ret_val; | |
3805 | ||
3806 | ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); | |
3807 | if (ret_val) { | |
3808 | e_dbg("NVM Read Error\n"); | |
3809 | return ret_val; | |
3810 | } | |
3811 | ||
3812 | if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) | |
3813 | *data = ID_LED_DEFAULT_ICH8LAN; | |
3814 | ||
3815 | return 0; | |
3816 | } | |
3817 | ||
3818 | /** | |
3819 | * e1000_id_led_init_pchlan - store LED configurations | |
3820 | * @hw: pointer to the HW structure | |
3821 | * | |
3822 | * PCH does not control LEDs via the LEDCTL register, rather it uses | |
3823 | * the PHY LED configuration register. | |
3824 | * | |
3825 | * PCH also does not have an "always on" or "always off" mode which | |
3826 | * complicates the ID feature. Instead of using the "on" mode to indicate | |
3827 | * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()), | |
3828 | * use "link_up" mode. The LEDs will still ID on request if there is no | |
3829 | * link based on logic in e1000_led_[on|off]_pchlan(). | |
3830 | **/ | |
3831 | static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw) | |
3832 | { | |
3833 | struct e1000_mac_info *mac = &hw->mac; | |
3834 | s32 ret_val; | |
3835 | const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP; | |
3836 | const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT; | |
3837 | u16 data, i, temp, shift; | |
3838 | ||
3839 | /* Get default ID LED modes */ | |
3840 | ret_val = hw->nvm.ops.valid_led_default(hw, &data); | |
3841 | if (ret_val) | |
3842 | return ret_val; | |
3843 | ||
3844 | mac->ledctl_default = er32(LEDCTL); | |
3845 | mac->ledctl_mode1 = mac->ledctl_default; | |
3846 | mac->ledctl_mode2 = mac->ledctl_default; | |
3847 | ||
3848 | for (i = 0; i < 4; i++) { | |
3849 | temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK; | |
3850 | shift = (i * 5); | |
3851 | switch (temp) { | |
3852 | case ID_LED_ON1_DEF2: | |
3853 | case ID_LED_ON1_ON2: | |
3854 | case ID_LED_ON1_OFF2: | |
3855 | mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); | |
3856 | mac->ledctl_mode1 |= (ledctl_on << shift); | |
3857 | break; | |
3858 | case ID_LED_OFF1_DEF2: | |
3859 | case ID_LED_OFF1_ON2: | |
3860 | case ID_LED_OFF1_OFF2: | |
3861 | mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); | |
3862 | mac->ledctl_mode1 |= (ledctl_off << shift); | |
3863 | break; | |
3864 | default: | |
3865 | /* Do nothing */ | |
3866 | break; | |
3867 | } | |
3868 | switch (temp) { | |
3869 | case ID_LED_DEF1_ON2: | |
3870 | case ID_LED_ON1_ON2: | |
3871 | case ID_LED_OFF1_ON2: | |
3872 | mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); | |
3873 | mac->ledctl_mode2 |= (ledctl_on << shift); | |
3874 | break; | |
3875 | case ID_LED_DEF1_OFF2: | |
3876 | case ID_LED_ON1_OFF2: | |
3877 | case ID_LED_OFF1_OFF2: | |
3878 | mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); | |
3879 | mac->ledctl_mode2 |= (ledctl_off << shift); | |
3880 | break; | |
3881 | default: | |
3882 | /* Do nothing */ | |
3883 | break; | |
3884 | } | |
3885 | } | |
3886 | ||
3887 | return 0; | |
3888 | } | |
3889 | ||
3890 | /** | |
3891 | * e1000_get_bus_info_ich8lan - Get/Set the bus type and width | |
3892 | * @hw: pointer to the HW structure | |
3893 | * | |
3894 | * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability | |
3895 | * register, so the the bus width is hard coded. | |
3896 | **/ | |
3897 | static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw) | |
3898 | { | |
3899 | struct e1000_bus_info *bus = &hw->bus; | |
3900 | s32 ret_val; | |
3901 | ||
3902 | ret_val = e1000e_get_bus_info_pcie(hw); | |
3903 | ||
3904 | /* ICH devices are "PCI Express"-ish. They have | |
3905 | * a configuration space, but do not contain | |
3906 | * PCI Express Capability registers, so bus width | |
3907 | * must be hardcoded. | |
3908 | */ | |
3909 | if (bus->width == e1000_bus_width_unknown) | |
3910 | bus->width = e1000_bus_width_pcie_x1; | |
3911 | ||
3912 | return ret_val; | |
3913 | } | |
3914 | ||
3915 | /** | |
3916 | * e1000_reset_hw_ich8lan - Reset the hardware | |
3917 | * @hw: pointer to the HW structure | |
3918 | * | |
3919 | * Does a full reset of the hardware which includes a reset of the PHY and | |
3920 | * MAC. | |
3921 | **/ | |
3922 | static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) | |
3923 | { | |
3924 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; | |
3925 | u16 kum_cfg; | |
3926 | u32 ctrl, reg; | |
3927 | s32 ret_val; | |
3928 | ||
3929 | /* Prevent the PCI-E bus from sticking if there is no TLP connection | |
3930 | * on the last TLP read/write transaction when MAC is reset. | |
3931 | */ | |
3932 | ret_val = e1000e_disable_pcie_master(hw); | |
3933 | if (ret_val) | |
3934 | e_dbg("PCI-E Master disable polling has failed.\n"); | |
3935 | ||
3936 | e_dbg("Masking off all interrupts\n"); | |
3937 | ew32(IMC, 0xffffffff); | |
3938 | ||
3939 | /* Disable the Transmit and Receive units. Then delay to allow | |
3940 | * any pending transactions to complete before we hit the MAC | |
3941 | * with the global reset. | |
3942 | */ | |
3943 | ew32(RCTL, 0); | |
3944 | ew32(TCTL, E1000_TCTL_PSP); | |
3945 | e1e_flush(); | |
3946 | ||
3947 | usleep_range(10000, 20000); | |
3948 | ||
3949 | /* Workaround for ICH8 bit corruption issue in FIFO memory */ | |
3950 | if (hw->mac.type == e1000_ich8lan) { | |
3951 | /* Set Tx and Rx buffer allocation to 8k apiece. */ | |
3952 | ew32(PBA, E1000_PBA_8K); | |
3953 | /* Set Packet Buffer Size to 16k. */ | |
3954 | ew32(PBS, E1000_PBS_16K); | |
3955 | } | |
3956 | ||
3957 | if (hw->mac.type == e1000_pchlan) { | |
3958 | /* Save the NVM K1 bit setting */ | |
3959 | ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg); | |
3960 | if (ret_val) | |
3961 | return ret_val; | |
3962 | ||
3963 | if (kum_cfg & E1000_NVM_K1_ENABLE) | |
3964 | dev_spec->nvm_k1_enabled = true; | |
3965 | else | |
3966 | dev_spec->nvm_k1_enabled = false; | |
3967 | } | |
3968 | ||
3969 | ctrl = er32(CTRL); | |
3970 | ||
3971 | if (!hw->phy.ops.check_reset_block(hw)) { | |
3972 | /* Full-chip reset requires MAC and PHY reset at the same | |
3973 | * time to make sure the interface between MAC and the | |
3974 | * external PHY is reset. | |
3975 | */ | |
3976 | ctrl |= E1000_CTRL_PHY_RST; | |
3977 | ||
3978 | /* Gate automatic PHY configuration by hardware on | |
3979 | * non-managed 82579 | |
3980 | */ | |
3981 | if ((hw->mac.type == e1000_pch2lan) && | |
3982 | !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) | |
3983 | e1000_gate_hw_phy_config_ich8lan(hw, true); | |
3984 | } | |
3985 | ret_val = e1000_acquire_swflag_ich8lan(hw); | |
3986 | e_dbg("Issuing a global reset to ich8lan\n"); | |
3987 | ew32(CTRL, (ctrl | E1000_CTRL_RST)); | |
3988 | /* cannot issue a flush here because it hangs the hardware */ | |
3989 | msleep(20); | |
3990 | ||
3991 | /* Set Phy Config Counter to 50msec */ | |
3992 | if (hw->mac.type == e1000_pch2lan) { | |
3993 | reg = er32(FEXTNVM3); | |
3994 | reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK; | |
3995 | reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; | |
3996 | ew32(FEXTNVM3, reg); | |
3997 | } | |
3998 | ||
3999 | if (!ret_val) | |
4000 | clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); | |
4001 | ||
4002 | if (ctrl & E1000_CTRL_PHY_RST) { | |
4003 | ret_val = hw->phy.ops.get_cfg_done(hw); | |
4004 | if (ret_val) | |
4005 | return ret_val; | |
4006 | ||
4007 | ret_val = e1000_post_phy_reset_ich8lan(hw); | |
4008 | if (ret_val) | |
4009 | return ret_val; | |
4010 | } | |
4011 | ||
4012 | /* For PCH, this write will make sure that any noise | |
4013 | * will be detected as a CRC error and be dropped rather than show up | |
4014 | * as a bad packet to the DMA engine. | |
4015 | */ | |
4016 | if (hw->mac.type == e1000_pchlan) | |
4017 | ew32(CRC_OFFSET, 0x65656565); | |
4018 | ||
4019 | ew32(IMC, 0xffffffff); | |
4020 | er32(ICR); | |
4021 | ||
4022 | reg = er32(KABGTXD); | |
4023 | reg |= E1000_KABGTXD_BGSQLBIAS; | |
4024 | ew32(KABGTXD, reg); | |
4025 | ||
4026 | return 0; | |
4027 | } | |
4028 | ||
4029 | /** | |
4030 | * e1000_init_hw_ich8lan - Initialize the hardware | |
4031 | * @hw: pointer to the HW structure | |
4032 | * | |
4033 | * Prepares the hardware for transmit and receive by doing the following: | |
4034 | * - initialize hardware bits | |
4035 | * - initialize LED identification | |
4036 | * - setup receive address registers | |
4037 | * - setup flow control | |
4038 | * - setup transmit descriptors | |
4039 | * - clear statistics | |
4040 | **/ | |
4041 | static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) | |
4042 | { | |
4043 | struct e1000_mac_info *mac = &hw->mac; | |
4044 | u32 ctrl_ext, txdctl, snoop; | |
4045 | s32 ret_val; | |
4046 | u16 i; | |
4047 | ||
4048 | e1000_initialize_hw_bits_ich8lan(hw); | |
4049 | ||
4050 | /* Initialize identification LED */ | |
4051 | ret_val = mac->ops.id_led_init(hw); | |
4052 | /* An error is not fatal and we should not stop init due to this */ | |
4053 | if (ret_val) | |
4054 | e_dbg("Error initializing identification LED\n"); | |
4055 | ||
4056 | /* Setup the receive address. */ | |
4057 | e1000e_init_rx_addrs(hw, mac->rar_entry_count); | |
4058 | ||
4059 | /* Zero out the Multicast HASH table */ | |
4060 | e_dbg("Zeroing the MTA\n"); | |
4061 | for (i = 0; i < mac->mta_reg_count; i++) | |
4062 | E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); | |
4063 | ||
4064 | /* The 82578 Rx buffer will stall if wakeup is enabled in host and | |
4065 | * the ME. Disable wakeup by clearing the host wakeup bit. | |
4066 | * Reset the phy after disabling host wakeup to reset the Rx buffer. | |
4067 | */ | |
4068 | if (hw->phy.type == e1000_phy_82578) { | |
4069 | e1e_rphy(hw, BM_PORT_GEN_CFG, &i); | |
4070 | i &= ~BM_WUC_HOST_WU_BIT; | |
4071 | e1e_wphy(hw, BM_PORT_GEN_CFG, i); | |
4072 | ret_val = e1000_phy_hw_reset_ich8lan(hw); | |
4073 | if (ret_val) | |
4074 | return ret_val; | |
4075 | } | |
4076 | ||
4077 | /* Setup link and flow control */ | |
4078 | ret_val = mac->ops.setup_link(hw); | |
4079 | ||
4080 | /* Set the transmit descriptor write-back policy for both queues */ | |
4081 | txdctl = er32(TXDCTL(0)); | |
4082 | txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) | | |
4083 | E1000_TXDCTL_FULL_TX_DESC_WB); | |
4084 | txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) | | |
4085 | E1000_TXDCTL_MAX_TX_DESC_PREFETCH); | |
4086 | ew32(TXDCTL(0), txdctl); | |
4087 | txdctl = er32(TXDCTL(1)); | |
4088 | txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) | | |
4089 | E1000_TXDCTL_FULL_TX_DESC_WB); | |
4090 | txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) | | |
4091 | E1000_TXDCTL_MAX_TX_DESC_PREFETCH); | |
4092 | ew32(TXDCTL(1), txdctl); | |
4093 | ||
4094 | /* ICH8 has opposite polarity of no_snoop bits. | |
4095 | * By default, we should use snoop behavior. | |
4096 | */ | |
4097 | if (mac->type == e1000_ich8lan) | |
4098 | snoop = PCIE_ICH8_SNOOP_ALL; | |
4099 | else | |
4100 | snoop = (u32)~(PCIE_NO_SNOOP_ALL); | |
4101 | e1000e_set_pcie_no_snoop(hw, snoop); | |
4102 | ||
4103 | ctrl_ext = er32(CTRL_EXT); | |
4104 | ctrl_ext |= E1000_CTRL_EXT_RO_DIS; | |
4105 | ew32(CTRL_EXT, ctrl_ext); | |
4106 | ||
4107 | /* Clear all of the statistics registers (clear on read). It is | |
4108 | * important that we do this after we have tried to establish link | |
4109 | * because the symbol error count will increment wildly if there | |
4110 | * is no link. | |
4111 | */ | |
4112 | e1000_clear_hw_cntrs_ich8lan(hw); | |
4113 | ||
4114 | return ret_val; | |
4115 | } | |
4116 | ||
4117 | /** | |
4118 | * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits | |
4119 | * @hw: pointer to the HW structure | |
4120 | * | |
4121 | * Sets/Clears required hardware bits necessary for correctly setting up the | |
4122 | * hardware for transmit and receive. | |
4123 | **/ | |
4124 | static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) | |
4125 | { | |
4126 | u32 reg; | |
4127 | ||
4128 | /* Extended Device Control */ | |
4129 | reg = er32(CTRL_EXT); | |
4130 | reg |= (1 << 22); | |
4131 | /* Enable PHY low-power state when MAC is at D3 w/o WoL */ | |
4132 | if (hw->mac.type >= e1000_pchlan) | |
4133 | reg |= E1000_CTRL_EXT_PHYPDEN; | |
4134 | ew32(CTRL_EXT, reg); | |
4135 | ||
4136 | /* Transmit Descriptor Control 0 */ | |
4137 | reg = er32(TXDCTL(0)); | |
4138 | reg |= (1 << 22); | |
4139 | ew32(TXDCTL(0), reg); | |
4140 | ||
4141 | /* Transmit Descriptor Control 1 */ | |
4142 | reg = er32(TXDCTL(1)); | |
4143 | reg |= (1 << 22); | |
4144 | ew32(TXDCTL(1), reg); | |
4145 | ||
4146 | /* Transmit Arbitration Control 0 */ | |
4147 | reg = er32(TARC(0)); | |
4148 | if (hw->mac.type == e1000_ich8lan) | |
4149 | reg |= (1 << 28) | (1 << 29); | |
4150 | reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27); | |
4151 | ew32(TARC(0), reg); | |
4152 | ||
4153 | /* Transmit Arbitration Control 1 */ | |
4154 | reg = er32(TARC(1)); | |
4155 | if (er32(TCTL) & E1000_TCTL_MULR) | |
4156 | reg &= ~(1 << 28); | |
4157 | else | |
4158 | reg |= (1 << 28); | |
4159 | reg |= (1 << 24) | (1 << 26) | (1 << 30); | |
4160 | ew32(TARC(1), reg); | |
4161 | ||
4162 | /* Device Status */ | |
4163 | if (hw->mac.type == e1000_ich8lan) { | |
4164 | reg = er32(STATUS); | |
4165 | reg &= ~(1 << 31); | |
4166 | ew32(STATUS, reg); | |
4167 | } | |
4168 | ||
4169 | /* work-around descriptor data corruption issue during nfs v2 udp | |
4170 | * traffic, just disable the nfs filtering capability | |
4171 | */ | |
4172 | reg = er32(RFCTL); | |
4173 | reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS); | |
4174 | ||
4175 | /* Disable IPv6 extension header parsing because some malformed | |
4176 | * IPv6 headers can hang the Rx. | |
4177 | */ | |
4178 | if (hw->mac.type == e1000_ich8lan) | |
4179 | reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS); | |
4180 | ew32(RFCTL, reg); | |
4181 | ||
4182 | /* Enable ECC on Lynxpoint */ | |
4183 | if (hw->mac.type == e1000_pch_lpt) { | |
4184 | reg = er32(PBECCSTS); | |
4185 | reg |= E1000_PBECCSTS_ECC_ENABLE; | |
4186 | ew32(PBECCSTS, reg); | |
4187 | ||
4188 | reg = er32(CTRL); | |
4189 | reg |= E1000_CTRL_MEHE; | |
4190 | ew32(CTRL, reg); | |
4191 | } | |
4192 | } | |
4193 | ||
4194 | /** | |
4195 | * e1000_setup_link_ich8lan - Setup flow control and link settings | |
4196 | * @hw: pointer to the HW structure | |
4197 | * | |
4198 | * Determines which flow control settings to use, then configures flow | |
4199 | * control. Calls the appropriate media-specific link configuration | |
4200 | * function. Assuming the adapter has a valid link partner, a valid link | |
4201 | * should be established. Assumes the hardware has previously been reset | |
4202 | * and the transmitter and receiver are not enabled. | |
4203 | **/ | |
4204 | static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw) | |
4205 | { | |
4206 | s32 ret_val; | |
4207 | ||
4208 | if (hw->phy.ops.check_reset_block(hw)) | |
4209 | return 0; | |
4210 | ||
4211 | /* ICH parts do not have a word in the NVM to determine | |
4212 | * the default flow control setting, so we explicitly | |
4213 | * set it to full. | |
4214 | */ | |
4215 | if (hw->fc.requested_mode == e1000_fc_default) { | |
4216 | /* Workaround h/w hang when Tx flow control enabled */ | |
4217 | if (hw->mac.type == e1000_pchlan) | |
4218 | hw->fc.requested_mode = e1000_fc_rx_pause; | |
4219 | else | |
4220 | hw->fc.requested_mode = e1000_fc_full; | |
4221 | } | |
4222 | ||
4223 | /* Save off the requested flow control mode for use later. Depending | |
4224 | * on the link partner's capabilities, we may or may not use this mode. | |
4225 | */ | |
4226 | hw->fc.current_mode = hw->fc.requested_mode; | |
4227 | ||
4228 | e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode); | |
4229 | ||
4230 | /* Continue to configure the copper link. */ | |
4231 | ret_val = hw->mac.ops.setup_physical_interface(hw); | |
4232 | if (ret_val) | |
4233 | return ret_val; | |
4234 | ||
4235 | ew32(FCTTV, hw->fc.pause_time); | |
4236 | if ((hw->phy.type == e1000_phy_82578) || | |
4237 | (hw->phy.type == e1000_phy_82579) || | |
4238 | (hw->phy.type == e1000_phy_i217) || | |
4239 | (hw->phy.type == e1000_phy_82577)) { | |
4240 | ew32(FCRTV_PCH, hw->fc.refresh_time); | |
4241 | ||
4242 | ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27), | |
4243 | hw->fc.pause_time); | |
4244 | if (ret_val) | |
4245 | return ret_val; | |
4246 | } | |
4247 | ||
4248 | return e1000e_set_fc_watermarks(hw); | |
4249 | } | |
4250 | ||
4251 | /** | |
4252 | * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface | |
4253 | * @hw: pointer to the HW structure | |
4254 | * | |
4255 | * Configures the kumeran interface to the PHY to wait the appropriate time | |
4256 | * when polling the PHY, then call the generic setup_copper_link to finish | |
4257 | * configuring the copper link. | |
4258 | **/ | |
4259 | static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw) | |
4260 | { | |
4261 | u32 ctrl; | |
4262 | s32 ret_val; | |
4263 | u16 reg_data; | |
4264 | ||
4265 | ctrl = er32(CTRL); | |
4266 | ctrl |= E1000_CTRL_SLU; | |
4267 | ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); | |
4268 | ew32(CTRL, ctrl); | |
4269 | ||
4270 | /* Set the mac to wait the maximum time between each iteration | |
4271 | * and increase the max iterations when polling the phy; | |
4272 | * this fixes erroneous timeouts at 10Mbps. | |
4273 | */ | |
4274 | ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF); | |
4275 | if (ret_val) | |
4276 | return ret_val; | |
4277 | ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, | |
4278 | ®_data); | |
4279 | if (ret_val) | |
4280 | return ret_val; | |
4281 | reg_data |= 0x3F; | |
4282 | ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, | |
4283 | reg_data); | |
4284 | if (ret_val) | |
4285 | return ret_val; | |
4286 | ||
4287 | switch (hw->phy.type) { | |
4288 | case e1000_phy_igp_3: | |
4289 | ret_val = e1000e_copper_link_setup_igp(hw); | |
4290 | if (ret_val) | |
4291 | return ret_val; | |
4292 | break; | |
4293 | case e1000_phy_bm: | |
4294 | case e1000_phy_82578: | |
4295 | ret_val = e1000e_copper_link_setup_m88(hw); | |
4296 | if (ret_val) | |
4297 | return ret_val; | |
4298 | break; | |
4299 | case e1000_phy_82577: | |
4300 | case e1000_phy_82579: | |
4301 | ret_val = e1000_copper_link_setup_82577(hw); | |
4302 | if (ret_val) | |
4303 | return ret_val; | |
4304 | break; | |
4305 | case e1000_phy_ife: | |
4306 | ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, ®_data); | |
4307 | if (ret_val) | |
4308 | return ret_val; | |
4309 | ||
4310 | reg_data &= ~IFE_PMC_AUTO_MDIX; | |
4311 | ||
4312 | switch (hw->phy.mdix) { | |
4313 | case 1: | |
4314 | reg_data &= ~IFE_PMC_FORCE_MDIX; | |
4315 | break; | |
4316 | case 2: | |
4317 | reg_data |= IFE_PMC_FORCE_MDIX; | |
4318 | break; | |
4319 | case 0: | |
4320 | default: | |
4321 | reg_data |= IFE_PMC_AUTO_MDIX; | |
4322 | break; | |
4323 | } | |
4324 | ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data); | |
4325 | if (ret_val) | |
4326 | return ret_val; | |
4327 | break; | |
4328 | default: | |
4329 | break; | |
4330 | } | |
4331 | ||
4332 | return e1000e_setup_copper_link(hw); | |
4333 | } | |
4334 | ||
4335 | /** | |
4336 | * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface | |
4337 | * @hw: pointer to the HW structure | |
4338 | * | |
4339 | * Calls the PHY specific link setup function and then calls the | |
4340 | * generic setup_copper_link to finish configuring the link for | |
4341 | * Lynxpoint PCH devices | |
4342 | **/ | |
4343 | static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw) | |
4344 | { | |
4345 | u32 ctrl; | |
4346 | s32 ret_val; | |
4347 | ||
4348 | ctrl = er32(CTRL); | |
4349 | ctrl |= E1000_CTRL_SLU; | |
4350 | ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); | |
4351 | ew32(CTRL, ctrl); | |
4352 | ||
4353 | ret_val = e1000_copper_link_setup_82577(hw); | |
4354 | if (ret_val) | |
4355 | return ret_val; | |
4356 | ||
4357 | return e1000e_setup_copper_link(hw); | |
4358 | } | |
4359 | ||
4360 | /** | |
4361 | * e1000_get_link_up_info_ich8lan - Get current link speed and duplex | |
4362 | * @hw: pointer to the HW structure | |
4363 | * @speed: pointer to store current link speed | |
4364 | * @duplex: pointer to store the current link duplex | |
4365 | * | |
4366 | * Calls the generic get_speed_and_duplex to retrieve the current link | |
4367 | * information and then calls the Kumeran lock loss workaround for links at | |
4368 | * gigabit speeds. | |
4369 | **/ | |
4370 | static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, | |
4371 | u16 *duplex) | |
4372 | { | |
4373 | s32 ret_val; | |
4374 | ||
4375 | ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex); | |
4376 | if (ret_val) | |
4377 | return ret_val; | |
4378 | ||
4379 | if ((hw->mac.type == e1000_ich8lan) && | |
4380 | (hw->phy.type == e1000_phy_igp_3) && (*speed == SPEED_1000)) { | |
4381 | ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw); | |
4382 | } | |
4383 | ||
4384 | return ret_val; | |
4385 | } | |
4386 | ||
4387 | /** | |
4388 | * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround | |
4389 | * @hw: pointer to the HW structure | |
4390 | * | |
4391 | * Work-around for 82566 Kumeran PCS lock loss: | |
4392 | * On link status change (i.e. PCI reset, speed change) and link is up and | |
4393 | * speed is gigabit- | |
4394 | * 0) if workaround is optionally disabled do nothing | |
4395 | * 1) wait 1ms for Kumeran link to come up | |
4396 | * 2) check Kumeran Diagnostic register PCS lock loss bit | |
4397 | * 3) if not set the link is locked (all is good), otherwise... | |
4398 | * 4) reset the PHY | |
4399 | * 5) repeat up to 10 times | |
4400 | * Note: this is only called for IGP3 copper when speed is 1gb. | |
4401 | **/ | |
4402 | static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw) | |
4403 | { | |
4404 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; | |
4405 | u32 phy_ctrl; | |
4406 | s32 ret_val; | |
4407 | u16 i, data; | |
4408 | bool link; | |
4409 | ||
4410 | if (!dev_spec->kmrn_lock_loss_workaround_enabled) | |
4411 | return 0; | |
4412 | ||
4413 | /* Make sure link is up before proceeding. If not just return. | |
4414 | * Attempting this while link is negotiating fouled up link | |
4415 | * stability | |
4416 | */ | |
4417 | ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); | |
4418 | if (!link) | |
4419 | return 0; | |
4420 | ||
4421 | for (i = 0; i < 10; i++) { | |
4422 | /* read once to clear */ | |
4423 | ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); | |
4424 | if (ret_val) | |
4425 | return ret_val; | |
4426 | /* and again to get new status */ | |
4427 | ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); | |
4428 | if (ret_val) | |
4429 | return ret_val; | |
4430 | ||
4431 | /* check for PCS lock */ | |
4432 | if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) | |
4433 | return 0; | |
4434 | ||
4435 | /* Issue PHY reset */ | |
4436 | e1000_phy_hw_reset(hw); | |
4437 | mdelay(5); | |
4438 | } | |
4439 | /* Disable GigE link negotiation */ | |
4440 | phy_ctrl = er32(PHY_CTRL); | |
4441 | phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE | | |
4442 | E1000_PHY_CTRL_NOND0A_GBE_DISABLE); | |
4443 | ew32(PHY_CTRL, phy_ctrl); | |
4444 | ||
4445 | /* Call gig speed drop workaround on Gig disable before accessing | |
4446 | * any PHY registers | |
4447 | */ | |
4448 | e1000e_gig_downshift_workaround_ich8lan(hw); | |
4449 | ||
4450 | /* unable to acquire PCS lock */ | |
4451 | return -E1000_ERR_PHY; | |
4452 | } | |
4453 | ||
4454 | /** | |
4455 | * e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state | |
4456 | * @hw: pointer to the HW structure | |
4457 | * @state: boolean value used to set the current Kumeran workaround state | |
4458 | * | |
4459 | * If ICH8, set the current Kumeran workaround state (enabled - true | |
4460 | * /disabled - false). | |
4461 | **/ | |
4462 | void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, | |
4463 | bool state) | |
4464 | { | |
4465 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; | |
4466 | ||
4467 | if (hw->mac.type != e1000_ich8lan) { | |
4468 | e_dbg("Workaround applies to ICH8 only.\n"); | |
4469 | return; | |
4470 | } | |
4471 | ||
4472 | dev_spec->kmrn_lock_loss_workaround_enabled = state; | |
4473 | } | |
4474 | ||
4475 | /** | |
4476 | * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3 | |
4477 | * @hw: pointer to the HW structure | |
4478 | * | |
4479 | * Workaround for 82566 power-down on D3 entry: | |
4480 | * 1) disable gigabit link | |
4481 | * 2) write VR power-down enable | |
4482 | * 3) read it back | |
4483 | * Continue if successful, else issue LCD reset and repeat | |
4484 | **/ | |
4485 | void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) | |
4486 | { | |
4487 | u32 reg; | |
4488 | u16 data; | |
4489 | u8 retry = 0; | |
4490 | ||
4491 | if (hw->phy.type != e1000_phy_igp_3) | |
4492 | return; | |
4493 | ||
4494 | /* Try the workaround twice (if needed) */ | |
4495 | do { | |
4496 | /* Disable link */ | |
4497 | reg = er32(PHY_CTRL); | |
4498 | reg |= (E1000_PHY_CTRL_GBE_DISABLE | | |
4499 | E1000_PHY_CTRL_NOND0A_GBE_DISABLE); | |
4500 | ew32(PHY_CTRL, reg); | |
4501 | ||
4502 | /* Call gig speed drop workaround on Gig disable before | |
4503 | * accessing any PHY registers | |
4504 | */ | |
4505 | if (hw->mac.type == e1000_ich8lan) | |
4506 | e1000e_gig_downshift_workaround_ich8lan(hw); | |
4507 | ||
4508 | /* Write VR power-down enable */ | |
4509 | e1e_rphy(hw, IGP3_VR_CTRL, &data); | |
4510 | data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; | |
4511 | e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN); | |
4512 | ||
4513 | /* Read it back and test */ | |
4514 | e1e_rphy(hw, IGP3_VR_CTRL, &data); | |
4515 | data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; | |
4516 | if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry) | |
4517 | break; | |
4518 | ||
4519 | /* Issue PHY reset and repeat at most one more time */ | |
4520 | reg = er32(CTRL); | |
4521 | ew32(CTRL, reg | E1000_CTRL_PHY_RST); | |
4522 | retry++; | |
4523 | } while (retry); | |
4524 | } | |
4525 | ||
4526 | /** | |
4527 | * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working | |
4528 | * @hw: pointer to the HW structure | |
4529 | * | |
4530 | * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC), | |
4531 | * LPLU, Gig disable, MDIC PHY reset): | |
4532 | * 1) Set Kumeran Near-end loopback | |
4533 | * 2) Clear Kumeran Near-end loopback | |
4534 | * Should only be called for ICH8[m] devices with any 1G Phy. | |
4535 | **/ | |
4536 | void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw) | |
4537 | { | |
4538 | s32 ret_val; | |
4539 | u16 reg_data; | |
4540 | ||
4541 | if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife)) | |
4542 | return; | |
4543 | ||
4544 | ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, | |
4545 | ®_data); | |
4546 | if (ret_val) | |
4547 | return; | |
4548 | reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK; | |
4549 | ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, | |
4550 | reg_data); | |
4551 | if (ret_val) | |
4552 | return; | |
4553 | reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK; | |
4554 | e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, reg_data); | |
4555 | } | |
4556 | ||
4557 | /** | |
4558 | * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx | |
4559 | * @hw: pointer to the HW structure | |
4560 | * | |
4561 | * During S0 to Sx transition, it is possible the link remains at gig | |
4562 | * instead of negotiating to a lower speed. Before going to Sx, set | |
4563 | * 'Gig Disable' to force link speed negotiation to a lower speed based on | |
4564 | * the LPLU setting in the NVM or custom setting. For PCH and newer parts, | |
4565 | * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also | |
4566 | * needs to be written. | |
4567 | * Parts that support (and are linked to a partner which support) EEE in | |
4568 | * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power | |
4569 | * than 10Mbps w/o EEE. | |
4570 | **/ | |
4571 | void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw) | |
4572 | { | |
4573 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; | |
4574 | u32 phy_ctrl; | |
4575 | s32 ret_val; | |
4576 | ||
4577 | phy_ctrl = er32(PHY_CTRL); | |
4578 | phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE; | |
4579 | ||
4580 | if (hw->phy.type == e1000_phy_i217) { | |
4581 | u16 phy_reg, device_id = hw->adapter->pdev->device; | |
4582 | ||
4583 | if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) || | |
4584 | (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) || | |
4585 | (device_id == E1000_DEV_ID_PCH_I218_LM3) || | |
4586 | (device_id == E1000_DEV_ID_PCH_I218_V3)) { | |
4587 | u32 fextnvm6 = er32(FEXTNVM6); | |
4588 | ||
4589 | ew32(FEXTNVM6, fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK); | |
4590 | } | |
4591 | ||
4592 | ret_val = hw->phy.ops.acquire(hw); | |
4593 | if (ret_val) | |
4594 | goto out; | |
4595 | ||
4596 | if (!dev_spec->eee_disable) { | |
4597 | u16 eee_advert; | |
4598 | ||
4599 | ret_val = | |
4600 | e1000_read_emi_reg_locked(hw, | |
4601 | I217_EEE_ADVERTISEMENT, | |
4602 | &eee_advert); | |
4603 | if (ret_val) | |
4604 | goto release; | |
4605 | ||
4606 | /* Disable LPLU if both link partners support 100BaseT | |
4607 | * EEE and 100Full is advertised on both ends of the | |
4608 | * link. | |
4609 | */ | |
4610 | if ((eee_advert & I82579_EEE_100_SUPPORTED) && | |
4611 | (dev_spec->eee_lp_ability & | |
4612 | I82579_EEE_100_SUPPORTED) && | |
4613 | (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) | |
4614 | phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU | | |
4615 | E1000_PHY_CTRL_NOND0A_LPLU); | |
4616 | } | |
4617 | ||
4618 | /* For i217 Intel Rapid Start Technology support, | |
4619 | * when the system is going into Sx and no manageability engine | |
4620 | * is present, the driver must configure proxy to reset only on | |
4621 | * power good. LPI (Low Power Idle) state must also reset only | |
4622 | * on power good, as well as the MTA (Multicast table array). | |
4623 | * The SMBus release must also be disabled on LCD reset. | |
4624 | */ | |
4625 | if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { | |
4626 | /* Enable proxy to reset only on power good. */ | |
4627 | e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg); | |
4628 | phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE; | |
4629 | e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg); | |
4630 | ||
4631 | /* Set bit enable LPI (EEE) to reset only on | |
4632 | * power good. | |
4633 | */ | |
4634 | e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg); | |
4635 | phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET; | |
4636 | e1e_wphy_locked(hw, I217_SxCTRL, phy_reg); | |
4637 | ||
4638 | /* Disable the SMB release on LCD reset. */ | |
4639 | e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg); | |
4640 | phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE; | |
4641 | e1e_wphy_locked(hw, I217_MEMPWR, phy_reg); | |
4642 | } | |
4643 | ||
4644 | /* Enable MTA to reset for Intel Rapid Start Technology | |
4645 | * Support | |
4646 | */ | |
4647 | e1e_rphy_locked(hw, I217_CGFREG, &phy_reg); | |
4648 | phy_reg |= I217_CGFREG_ENABLE_MTA_RESET; | |
4649 | e1e_wphy_locked(hw, I217_CGFREG, phy_reg); | |
4650 | ||
4651 | release: | |
4652 | hw->phy.ops.release(hw); | |
4653 | } | |
4654 | out: | |
4655 | ew32(PHY_CTRL, phy_ctrl); | |
4656 | ||
4657 | if (hw->mac.type == e1000_ich8lan) | |
4658 | e1000e_gig_downshift_workaround_ich8lan(hw); | |
4659 | ||
4660 | if (hw->mac.type >= e1000_pchlan) { | |
4661 | e1000_oem_bits_config_ich8lan(hw, false); | |
4662 | ||
4663 | /* Reset PHY to activate OEM bits on 82577/8 */ | |
4664 | if (hw->mac.type == e1000_pchlan) | |
4665 | e1000e_phy_hw_reset_generic(hw); | |
4666 | ||
4667 | ret_val = hw->phy.ops.acquire(hw); | |
4668 | if (ret_val) | |
4669 | return; | |
4670 | e1000_write_smbus_addr(hw); | |
4671 | hw->phy.ops.release(hw); | |
4672 | } | |
4673 | } | |
4674 | ||
4675 | /** | |
4676 | * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0 | |
4677 | * @hw: pointer to the HW structure | |
4678 | * | |
4679 | * During Sx to S0 transitions on non-managed devices or managed devices | |
4680 | * on which PHY resets are not blocked, if the PHY registers cannot be | |
4681 | * accessed properly by the s/w toggle the LANPHYPC value to power cycle | |
4682 | * the PHY. | |
4683 | * On i217, setup Intel Rapid Start Technology. | |
4684 | **/ | |
4685 | void e1000_resume_workarounds_pchlan(struct e1000_hw *hw) | |
4686 | { | |
4687 | s32 ret_val; | |
4688 | ||
4689 | if (hw->mac.type < e1000_pch2lan) | |
4690 | return; | |
4691 | ||
4692 | ret_val = e1000_init_phy_workarounds_pchlan(hw); | |
4693 | if (ret_val) { | |
4694 | e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val); | |
4695 | return; | |
4696 | } | |
4697 | ||
4698 | /* For i217 Intel Rapid Start Technology support when the system | |
4699 | * is transitioning from Sx and no manageability engine is present | |
4700 | * configure SMBus to restore on reset, disable proxy, and enable | |
4701 | * the reset on MTA (Multicast table array). | |
4702 | */ | |
4703 | if (hw->phy.type == e1000_phy_i217) { | |
4704 | u16 phy_reg; | |
4705 | ||
4706 | ret_val = hw->phy.ops.acquire(hw); | |
4707 | if (ret_val) { | |
4708 | e_dbg("Failed to setup iRST\n"); | |
4709 | return; | |
4710 | } | |
4711 | ||
4712 | if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { | |
4713 | /* Restore clear on SMB if no manageability engine | |
4714 | * is present | |
4715 | */ | |
4716 | ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg); | |
4717 | if (ret_val) | |
4718 | goto release; | |
4719 | phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE; | |
4720 | e1e_wphy_locked(hw, I217_MEMPWR, phy_reg); | |
4721 | ||
4722 | /* Disable Proxy */ | |
4723 | e1e_wphy_locked(hw, I217_PROXY_CTRL, 0); | |
4724 | } | |
4725 | /* Enable reset on MTA */ | |
4726 | ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg); | |
4727 | if (ret_val) | |
4728 | goto release; | |
4729 | phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET; | |
4730 | e1e_wphy_locked(hw, I217_CGFREG, phy_reg); | |
4731 | release: | |
4732 | if (ret_val) | |
4733 | e_dbg("Error %d in resume workarounds\n", ret_val); | |
4734 | hw->phy.ops.release(hw); | |
4735 | } | |
4736 | } | |
4737 | ||
4738 | /** | |
4739 | * e1000_cleanup_led_ich8lan - Restore the default LED operation | |
4740 | * @hw: pointer to the HW structure | |
4741 | * | |
4742 | * Return the LED back to the default configuration. | |
4743 | **/ | |
4744 | static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw) | |
4745 | { | |
4746 | if (hw->phy.type == e1000_phy_ife) | |
4747 | return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0); | |
4748 | ||
4749 | ew32(LEDCTL, hw->mac.ledctl_default); | |
4750 | return 0; | |
4751 | } | |
4752 | ||
4753 | /** | |
4754 | * e1000_led_on_ich8lan - Turn LEDs on | |
4755 | * @hw: pointer to the HW structure | |
4756 | * | |
4757 | * Turn on the LEDs. | |
4758 | **/ | |
4759 | static s32 e1000_led_on_ich8lan(struct e1000_hw *hw) | |
4760 | { | |
4761 | if (hw->phy.type == e1000_phy_ife) | |
4762 | return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, | |
4763 | (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON)); | |
4764 | ||
4765 | ew32(LEDCTL, hw->mac.ledctl_mode2); | |
4766 | return 0; | |
4767 | } | |
4768 | ||
4769 | /** | |
4770 | * e1000_led_off_ich8lan - Turn LEDs off | |
4771 | * @hw: pointer to the HW structure | |
4772 | * | |
4773 | * Turn off the LEDs. | |
4774 | **/ | |
4775 | static s32 e1000_led_off_ich8lan(struct e1000_hw *hw) | |
4776 | { | |
4777 | if (hw->phy.type == e1000_phy_ife) | |
4778 | return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, | |
4779 | (IFE_PSCL_PROBE_MODE | | |
4780 | IFE_PSCL_PROBE_LEDS_OFF)); | |
4781 | ||
4782 | ew32(LEDCTL, hw->mac.ledctl_mode1); | |
4783 | return 0; | |
4784 | } | |
4785 | ||
4786 | /** | |
4787 | * e1000_setup_led_pchlan - Configures SW controllable LED | |
4788 | * @hw: pointer to the HW structure | |
4789 | * | |
4790 | * This prepares the SW controllable LED for use. | |
4791 | **/ | |
4792 | static s32 e1000_setup_led_pchlan(struct e1000_hw *hw) | |
4793 | { | |
4794 | return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1); | |
4795 | } | |
4796 | ||
4797 | /** | |
4798 | * e1000_cleanup_led_pchlan - Restore the default LED operation | |
4799 | * @hw: pointer to the HW structure | |
4800 | * | |
4801 | * Return the LED back to the default configuration. | |
4802 | **/ | |
4803 | static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw) | |
4804 | { | |
4805 | return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default); | |
4806 | } | |
4807 | ||
4808 | /** | |
4809 | * e1000_led_on_pchlan - Turn LEDs on | |
4810 | * @hw: pointer to the HW structure | |
4811 | * | |
4812 | * Turn on the LEDs. | |
4813 | **/ | |
4814 | static s32 e1000_led_on_pchlan(struct e1000_hw *hw) | |
4815 | { | |
4816 | u16 data = (u16)hw->mac.ledctl_mode2; | |
4817 | u32 i, led; | |
4818 | ||
4819 | /* If no link, then turn LED on by setting the invert bit | |
4820 | * for each LED that's mode is "link_up" in ledctl_mode2. | |
4821 | */ | |
4822 | if (!(er32(STATUS) & E1000_STATUS_LU)) { | |
4823 | for (i = 0; i < 3; i++) { | |
4824 | led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; | |
4825 | if ((led & E1000_PHY_LED0_MODE_MASK) != | |
4826 | E1000_LEDCTL_MODE_LINK_UP) | |
4827 | continue; | |
4828 | if (led & E1000_PHY_LED0_IVRT) | |
4829 | data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); | |
4830 | else | |
4831 | data |= (E1000_PHY_LED0_IVRT << (i * 5)); | |
4832 | } | |
4833 | } | |
4834 | ||
4835 | return e1e_wphy(hw, HV_LED_CONFIG, data); | |
4836 | } | |
4837 | ||
4838 | /** | |
4839 | * e1000_led_off_pchlan - Turn LEDs off | |
4840 | * @hw: pointer to the HW structure | |
4841 | * | |
4842 | * Turn off the LEDs. | |
4843 | **/ | |
4844 | static s32 e1000_led_off_pchlan(struct e1000_hw *hw) | |
4845 | { | |
4846 | u16 data = (u16)hw->mac.ledctl_mode1; | |
4847 | u32 i, led; | |
4848 | ||
4849 | /* If no link, then turn LED off by clearing the invert bit | |
4850 | * for each LED that's mode is "link_up" in ledctl_mode1. | |
4851 | */ | |
4852 | if (!(er32(STATUS) & E1000_STATUS_LU)) { | |
4853 | for (i = 0; i < 3; i++) { | |
4854 | led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; | |
4855 | if ((led & E1000_PHY_LED0_MODE_MASK) != | |
4856 | E1000_LEDCTL_MODE_LINK_UP) | |
4857 | continue; | |
4858 | if (led & E1000_PHY_LED0_IVRT) | |
4859 | data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); | |
4860 | else | |
4861 | data |= (E1000_PHY_LED0_IVRT << (i * 5)); | |
4862 | } | |
4863 | } | |
4864 | ||
4865 | return e1e_wphy(hw, HV_LED_CONFIG, data); | |
4866 | } | |
4867 | ||
4868 | /** | |
4869 | * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset | |
4870 | * @hw: pointer to the HW structure | |
4871 | * | |
4872 | * Read appropriate register for the config done bit for completion status | |
4873 | * and configure the PHY through s/w for EEPROM-less parts. | |
4874 | * | |
4875 | * NOTE: some silicon which is EEPROM-less will fail trying to read the | |
4876 | * config done bit, so only an error is logged and continues. If we were | |
4877 | * to return with error, EEPROM-less silicon would not be able to be reset | |
4878 | * or change link. | |
4879 | **/ | |
4880 | static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw) | |
4881 | { | |
4882 | s32 ret_val = 0; | |
4883 | u32 bank = 0; | |
4884 | u32 status; | |
4885 | ||
4886 | e1000e_get_cfg_done_generic(hw); | |
4887 | ||
4888 | /* Wait for indication from h/w that it has completed basic config */ | |
4889 | if (hw->mac.type >= e1000_ich10lan) { | |
4890 | e1000_lan_init_done_ich8lan(hw); | |
4891 | } else { | |
4892 | ret_val = e1000e_get_auto_rd_done(hw); | |
4893 | if (ret_val) { | |
4894 | /* When auto config read does not complete, do not | |
4895 | * return with an error. This can happen in situations | |
4896 | * where there is no eeprom and prevents getting link. | |
4897 | */ | |
4898 | e_dbg("Auto Read Done did not complete\n"); | |
4899 | ret_val = 0; | |
4900 | } | |
4901 | } | |
4902 | ||
4903 | /* Clear PHY Reset Asserted bit */ | |
4904 | status = er32(STATUS); | |
4905 | if (status & E1000_STATUS_PHYRA) | |
4906 | ew32(STATUS, status & ~E1000_STATUS_PHYRA); | |
4907 | else | |
4908 | e_dbg("PHY Reset Asserted not set - needs delay\n"); | |
4909 | ||
4910 | /* If EEPROM is not marked present, init the IGP 3 PHY manually */ | |
4911 | if (hw->mac.type <= e1000_ich9lan) { | |
4912 | if (!(er32(EECD) & E1000_EECD_PRES) && | |
4913 | (hw->phy.type == e1000_phy_igp_3)) { | |
4914 | e1000e_phy_init_script_igp3(hw); | |
4915 | } | |
4916 | } else { | |
4917 | if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) { | |
4918 | /* Maybe we should do a basic PHY config */ | |
4919 | e_dbg("EEPROM not present\n"); | |
4920 | ret_val = -E1000_ERR_CONFIG; | |
4921 | } | |
4922 | } | |
4923 | ||
4924 | return ret_val; | |
4925 | } | |
4926 | ||
4927 | /** | |
4928 | * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down | |
4929 | * @hw: pointer to the HW structure | |
4930 | * | |
4931 | * In the case of a PHY power down to save power, or to turn off link during a | |
4932 | * driver unload, or wake on lan is not enabled, remove the link. | |
4933 | **/ | |
4934 | static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw) | |
4935 | { | |
4936 | /* If the management interface is not enabled, then power down */ | |
4937 | if (!(hw->mac.ops.check_mng_mode(hw) || | |
4938 | hw->phy.ops.check_reset_block(hw))) | |
4939 | e1000_power_down_phy_copper(hw); | |
4940 | } | |
4941 | ||
4942 | /** | |
4943 | * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters | |
4944 | * @hw: pointer to the HW structure | |
4945 | * | |
4946 | * Clears hardware counters specific to the silicon family and calls | |
4947 | * clear_hw_cntrs_generic to clear all general purpose counters. | |
4948 | **/ | |
4949 | static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw) | |
4950 | { | |
4951 | u16 phy_data; | |
4952 | s32 ret_val; | |
4953 | ||
4954 | e1000e_clear_hw_cntrs_base(hw); | |
4955 | ||
4956 | er32(ALGNERRC); | |
4957 | er32(RXERRC); | |
4958 | er32(TNCRS); | |
4959 | er32(CEXTERR); | |
4960 | er32(TSCTC); | |
4961 | er32(TSCTFC); | |
4962 | ||
4963 | er32(MGTPRC); | |
4964 | er32(MGTPDC); | |
4965 | er32(MGTPTC); | |
4966 | ||
4967 | er32(IAC); | |
4968 | er32(ICRXOC); | |
4969 | ||
4970 | /* Clear PHY statistics registers */ | |
4971 | if ((hw->phy.type == e1000_phy_82578) || | |
4972 | (hw->phy.type == e1000_phy_82579) || | |
4973 | (hw->phy.type == e1000_phy_i217) || | |
4974 | (hw->phy.type == e1000_phy_82577)) { | |
4975 | ret_val = hw->phy.ops.acquire(hw); | |
4976 | if (ret_val) | |
4977 | return; | |
4978 | ret_val = hw->phy.ops.set_page(hw, | |
4979 | HV_STATS_PAGE << IGP_PAGE_SHIFT); | |
4980 | if (ret_val) | |
4981 | goto release; | |
4982 | hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data); | |
4983 | hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data); | |
4984 | hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data); | |
4985 | hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data); | |
4986 | hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data); | |
4987 | hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data); | |
4988 | hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data); | |
4989 | hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data); | |
4990 | hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data); | |
4991 | hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data); | |
4992 | hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data); | |
4993 | hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data); | |
4994 | hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data); | |
4995 | hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data); | |
4996 | release: | |
4997 | hw->phy.ops.release(hw); | |
4998 | } | |
4999 | } | |
5000 | ||
5001 | static const struct e1000_mac_operations ich8_mac_ops = { | |
5002 | /* check_mng_mode dependent on mac type */ | |
5003 | .check_for_link = e1000_check_for_copper_link_ich8lan, | |
5004 | /* cleanup_led dependent on mac type */ | |
5005 | .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan, | |
5006 | .get_bus_info = e1000_get_bus_info_ich8lan, | |
5007 | .set_lan_id = e1000_set_lan_id_single_port, | |
5008 | .get_link_up_info = e1000_get_link_up_info_ich8lan, | |
5009 | /* led_on dependent on mac type */ | |
5010 | /* led_off dependent on mac type */ | |
5011 | .update_mc_addr_list = e1000e_update_mc_addr_list_generic, | |
5012 | .reset_hw = e1000_reset_hw_ich8lan, | |
5013 | .init_hw = e1000_init_hw_ich8lan, | |
5014 | .setup_link = e1000_setup_link_ich8lan, | |
5015 | .setup_physical_interface = e1000_setup_copper_link_ich8lan, | |
5016 | /* id_led_init dependent on mac type */ | |
5017 | .config_collision_dist = e1000e_config_collision_dist_generic, | |
5018 | .rar_set = e1000e_rar_set_generic, | |
5019 | .rar_get_count = e1000e_rar_get_count_generic, | |
5020 | }; | |
5021 | ||
5022 | static const struct e1000_phy_operations ich8_phy_ops = { | |
5023 | .acquire = e1000_acquire_swflag_ich8lan, | |
5024 | .check_reset_block = e1000_check_reset_block_ich8lan, | |
5025 | .commit = NULL, | |
5026 | .get_cfg_done = e1000_get_cfg_done_ich8lan, | |
5027 | .get_cable_length = e1000e_get_cable_length_igp_2, | |
5028 | .read_reg = e1000e_read_phy_reg_igp, | |
5029 | .release = e1000_release_swflag_ich8lan, | |
5030 | .reset = e1000_phy_hw_reset_ich8lan, | |
5031 | .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan, | |
5032 | .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan, | |
5033 | .write_reg = e1000e_write_phy_reg_igp, | |
5034 | }; | |
5035 | ||
5036 | static const struct e1000_nvm_operations ich8_nvm_ops = { | |
5037 | .acquire = e1000_acquire_nvm_ich8lan, | |
5038 | .read = e1000_read_nvm_ich8lan, | |
5039 | .release = e1000_release_nvm_ich8lan, | |
5040 | .reload = e1000e_reload_nvm_generic, | |
5041 | .update = e1000_update_nvm_checksum_ich8lan, | |
5042 | .valid_led_default = e1000_valid_led_default_ich8lan, | |
5043 | .validate = e1000_validate_nvm_checksum_ich8lan, | |
5044 | .write = e1000_write_nvm_ich8lan, | |
5045 | }; | |
5046 | ||
5047 | const struct e1000_info e1000_ich8_info = { | |
5048 | .mac = e1000_ich8lan, | |
5049 | .flags = FLAG_HAS_WOL | |
5050 | | FLAG_IS_ICH | |
5051 | | FLAG_HAS_CTRLEXT_ON_LOAD | |
5052 | | FLAG_HAS_AMT | |
5053 | | FLAG_HAS_FLASH | |
5054 | | FLAG_APME_IN_WUC, | |
5055 | .pba = 8, | |
5056 | .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN, | |
5057 | .get_variants = e1000_get_variants_ich8lan, | |
5058 | .mac_ops = &ich8_mac_ops, | |
5059 | .phy_ops = &ich8_phy_ops, | |
5060 | .nvm_ops = &ich8_nvm_ops, | |
5061 | }; | |
5062 | ||
5063 | const struct e1000_info e1000_ich9_info = { | |
5064 | .mac = e1000_ich9lan, | |
5065 | .flags = FLAG_HAS_JUMBO_FRAMES | |
5066 | | FLAG_IS_ICH | |
5067 | | FLAG_HAS_WOL | |
5068 | | FLAG_HAS_CTRLEXT_ON_LOAD | |
5069 | | FLAG_HAS_AMT | |
5070 | | FLAG_HAS_FLASH | |
5071 | | FLAG_APME_IN_WUC, | |
5072 | .pba = 18, | |
5073 | .max_hw_frame_size = DEFAULT_JUMBO, | |
5074 | .get_variants = e1000_get_variants_ich8lan, | |
5075 | .mac_ops = &ich8_mac_ops, | |
5076 | .phy_ops = &ich8_phy_ops, | |
5077 | .nvm_ops = &ich8_nvm_ops, | |
5078 | }; | |
5079 | ||
5080 | const struct e1000_info e1000_ich10_info = { | |
5081 | .mac = e1000_ich10lan, | |
5082 | .flags = FLAG_HAS_JUMBO_FRAMES | |
5083 | | FLAG_IS_ICH | |
5084 | | FLAG_HAS_WOL | |
5085 | | FLAG_HAS_CTRLEXT_ON_LOAD | |
5086 | | FLAG_HAS_AMT | |
5087 | | FLAG_HAS_FLASH | |
5088 | | FLAG_APME_IN_WUC, | |
5089 | .pba = 18, | |
5090 | .max_hw_frame_size = DEFAULT_JUMBO, | |
5091 | .get_variants = e1000_get_variants_ich8lan, | |
5092 | .mac_ops = &ich8_mac_ops, | |
5093 | .phy_ops = &ich8_phy_ops, | |
5094 | .nvm_ops = &ich8_nvm_ops, | |
5095 | }; | |
5096 | ||
5097 | const struct e1000_info e1000_pch_info = { | |
5098 | .mac = e1000_pchlan, | |
5099 | .flags = FLAG_IS_ICH | |
5100 | | FLAG_HAS_WOL | |
5101 | | FLAG_HAS_CTRLEXT_ON_LOAD | |
5102 | | FLAG_HAS_AMT | |
5103 | | FLAG_HAS_FLASH | |
5104 | | FLAG_HAS_JUMBO_FRAMES | |
5105 | | FLAG_DISABLE_FC_PAUSE_TIME /* errata */ | |
5106 | | FLAG_APME_IN_WUC, | |
5107 | .flags2 = FLAG2_HAS_PHY_STATS, | |
5108 | .pba = 26, | |
5109 | .max_hw_frame_size = 4096, | |
5110 | .get_variants = e1000_get_variants_ich8lan, | |
5111 | .mac_ops = &ich8_mac_ops, | |
5112 | .phy_ops = &ich8_phy_ops, | |
5113 | .nvm_ops = &ich8_nvm_ops, | |
5114 | }; | |
5115 | ||
5116 | const struct e1000_info e1000_pch2_info = { | |
5117 | .mac = e1000_pch2lan, | |
5118 | .flags = FLAG_IS_ICH | |
5119 | | FLAG_HAS_WOL | |
5120 | | FLAG_HAS_HW_TIMESTAMP | |
5121 | | FLAG_HAS_CTRLEXT_ON_LOAD | |
5122 | | FLAG_HAS_AMT | |
5123 | | FLAG_HAS_FLASH | |
5124 | | FLAG_HAS_JUMBO_FRAMES | |
5125 | | FLAG_APME_IN_WUC, | |
5126 | .flags2 = FLAG2_HAS_PHY_STATS | |
5127 | | FLAG2_HAS_EEE, | |
5128 | .pba = 26, | |
5129 | .max_hw_frame_size = 9018, | |
5130 | .get_variants = e1000_get_variants_ich8lan, | |
5131 | .mac_ops = &ich8_mac_ops, | |
5132 | .phy_ops = &ich8_phy_ops, | |
5133 | .nvm_ops = &ich8_nvm_ops, | |
5134 | }; | |
5135 | ||
5136 | const struct e1000_info e1000_pch_lpt_info = { | |
5137 | .mac = e1000_pch_lpt, | |
5138 | .flags = FLAG_IS_ICH | |
5139 | | FLAG_HAS_WOL | |
5140 | | FLAG_HAS_HW_TIMESTAMP | |
5141 | | FLAG_HAS_CTRLEXT_ON_LOAD | |
5142 | | FLAG_HAS_AMT | |
5143 | | FLAG_HAS_FLASH | |
5144 | | FLAG_HAS_JUMBO_FRAMES | |
5145 | | FLAG_APME_IN_WUC, | |
5146 | .flags2 = FLAG2_HAS_PHY_STATS | |
5147 | | FLAG2_HAS_EEE, | |
5148 | .pba = 26, | |
5149 | .max_hw_frame_size = 9018, | |
5150 | .get_variants = e1000_get_variants_ich8lan, | |
5151 | .mac_ops = &ich8_mac_ops, | |
5152 | .phy_ops = &ich8_phy_ops, | |
5153 | .nvm_ops = &ich8_nvm_ops, | |
5154 | }; |