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1 | /* This program is free software; you can redistribute it and/or modify | |
2 | * it under the terms of the GNU General Public License as published by | |
3 | * the Free Software Foundation; version 2 of the License | |
4 | * | |
5 | * This program is distributed in the hope that it will be useful, | |
6 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
7 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
8 | * GNU General Public License for more details. | |
9 | * | |
10 | * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> | |
11 | * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> | |
12 | * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> | |
13 | */ | |
14 | ||
15 | #include <linux/of_device.h> | |
16 | #include <linux/of_mdio.h> | |
17 | #include <linux/of_net.h> | |
18 | #include <linux/mfd/syscon.h> | |
19 | #include <linux/regmap.h> | |
20 | #include <linux/clk.h> | |
21 | #include <linux/pm_runtime.h> | |
22 | #include <linux/if_vlan.h> | |
23 | #include <linux/reset.h> | |
24 | #include <linux/tcp.h> | |
25 | #include <linux/interrupt.h> | |
26 | ||
27 | #include "mtk_eth_soc.h" | |
28 | ||
29 | static int mtk_msg_level = -1; | |
30 | module_param_named(msg_level, mtk_msg_level, int, 0); | |
31 | MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)"); | |
32 | ||
33 | #define MTK_ETHTOOL_STAT(x) { #x, \ | |
34 | offsetof(struct mtk_hw_stats, x) / sizeof(u64) } | |
35 | ||
36 | /* strings used by ethtool */ | |
37 | static const struct mtk_ethtool_stats { | |
38 | char str[ETH_GSTRING_LEN]; | |
39 | u32 offset; | |
40 | } mtk_ethtool_stats[] = { | |
41 | MTK_ETHTOOL_STAT(tx_bytes), | |
42 | MTK_ETHTOOL_STAT(tx_packets), | |
43 | MTK_ETHTOOL_STAT(tx_skip), | |
44 | MTK_ETHTOOL_STAT(tx_collisions), | |
45 | MTK_ETHTOOL_STAT(rx_bytes), | |
46 | MTK_ETHTOOL_STAT(rx_packets), | |
47 | MTK_ETHTOOL_STAT(rx_overflow), | |
48 | MTK_ETHTOOL_STAT(rx_fcs_errors), | |
49 | MTK_ETHTOOL_STAT(rx_short_errors), | |
50 | MTK_ETHTOOL_STAT(rx_long_errors), | |
51 | MTK_ETHTOOL_STAT(rx_checksum_errors), | |
52 | MTK_ETHTOOL_STAT(rx_flow_control_packets), | |
53 | }; | |
54 | ||
55 | static const char * const mtk_clks_source_name[] = { | |
56 | "ethif", "esw", "gp1", "gp2", "trgpll" | |
57 | }; | |
58 | ||
59 | void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg) | |
60 | { | |
61 | __raw_writel(val, eth->base + reg); | |
62 | } | |
63 | ||
64 | u32 mtk_r32(struct mtk_eth *eth, unsigned reg) | |
65 | { | |
66 | return __raw_readl(eth->base + reg); | |
67 | } | |
68 | ||
69 | static int mtk_mdio_busy_wait(struct mtk_eth *eth) | |
70 | { | |
71 | unsigned long t_start = jiffies; | |
72 | ||
73 | while (1) { | |
74 | if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS)) | |
75 | return 0; | |
76 | if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT)) | |
77 | break; | |
78 | usleep_range(10, 20); | |
79 | } | |
80 | ||
81 | dev_err(eth->dev, "mdio: MDIO timeout\n"); | |
82 | return -1; | |
83 | } | |
84 | ||
85 | static u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr, | |
86 | u32 phy_register, u32 write_data) | |
87 | { | |
88 | if (mtk_mdio_busy_wait(eth)) | |
89 | return -1; | |
90 | ||
91 | write_data &= 0xffff; | |
92 | ||
93 | mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE | | |
94 | (phy_register << PHY_IAC_REG_SHIFT) | | |
95 | (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data, | |
96 | MTK_PHY_IAC); | |
97 | ||
98 | if (mtk_mdio_busy_wait(eth)) | |
99 | return -1; | |
100 | ||
101 | return 0; | |
102 | } | |
103 | ||
104 | static u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg) | |
105 | { | |
106 | u32 d; | |
107 | ||
108 | if (mtk_mdio_busy_wait(eth)) | |
109 | return 0xffff; | |
110 | ||
111 | mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ | | |
112 | (phy_reg << PHY_IAC_REG_SHIFT) | | |
113 | (phy_addr << PHY_IAC_ADDR_SHIFT), | |
114 | MTK_PHY_IAC); | |
115 | ||
116 | if (mtk_mdio_busy_wait(eth)) | |
117 | return 0xffff; | |
118 | ||
119 | d = mtk_r32(eth, MTK_PHY_IAC) & 0xffff; | |
120 | ||
121 | return d; | |
122 | } | |
123 | ||
124 | static int mtk_mdio_write(struct mii_bus *bus, int phy_addr, | |
125 | int phy_reg, u16 val) | |
126 | { | |
127 | struct mtk_eth *eth = bus->priv; | |
128 | ||
129 | return _mtk_mdio_write(eth, phy_addr, phy_reg, val); | |
130 | } | |
131 | ||
132 | static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg) | |
133 | { | |
134 | struct mtk_eth *eth = bus->priv; | |
135 | ||
136 | return _mtk_mdio_read(eth, phy_addr, phy_reg); | |
137 | } | |
138 | ||
139 | static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, int speed) | |
140 | { | |
141 | u32 val; | |
142 | int ret; | |
143 | ||
144 | val = (speed == SPEED_1000) ? | |
145 | INTF_MODE_RGMII_1000 : INTF_MODE_RGMII_10_100; | |
146 | mtk_w32(eth, val, INTF_MODE); | |
147 | ||
148 | regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, | |
149 | ETHSYS_TRGMII_CLK_SEL362_5, | |
150 | ETHSYS_TRGMII_CLK_SEL362_5); | |
151 | ||
152 | val = (speed == SPEED_1000) ? 250000000 : 500000000; | |
153 | ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val); | |
154 | if (ret) | |
155 | dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret); | |
156 | ||
157 | val = (speed == SPEED_1000) ? | |
158 | RCK_CTRL_RGMII_1000 : RCK_CTRL_RGMII_10_100; | |
159 | mtk_w32(eth, val, TRGMII_RCK_CTRL); | |
160 | ||
161 | val = (speed == SPEED_1000) ? | |
162 | TCK_CTRL_RGMII_1000 : TCK_CTRL_RGMII_10_100; | |
163 | mtk_w32(eth, val, TRGMII_TCK_CTRL); | |
164 | } | |
165 | ||
166 | static void mtk_phy_link_adjust(struct net_device *dev) | |
167 | { | |
168 | struct mtk_mac *mac = netdev_priv(dev); | |
169 | u16 lcl_adv = 0, rmt_adv = 0; | |
170 | u8 flowctrl; | |
171 | u32 mcr = MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG | | |
172 | MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN | | |
173 | MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN | | |
174 | MAC_MCR_BACKPR_EN; | |
175 | ||
176 | if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) | |
177 | return; | |
178 | ||
179 | switch (dev->phydev->speed) { | |
180 | case SPEED_1000: | |
181 | mcr |= MAC_MCR_SPEED_1000; | |
182 | break; | |
183 | case SPEED_100: | |
184 | mcr |= MAC_MCR_SPEED_100; | |
185 | break; | |
186 | }; | |
187 | ||
188 | if (mac->id == 0 && !mac->trgmii) | |
189 | mtk_gmac0_rgmii_adjust(mac->hw, dev->phydev->speed); | |
190 | ||
191 | if (dev->phydev->link) | |
192 | mcr |= MAC_MCR_FORCE_LINK; | |
193 | ||
194 | if (dev->phydev->duplex) { | |
195 | mcr |= MAC_MCR_FORCE_DPX; | |
196 | ||
197 | if (dev->phydev->pause) | |
198 | rmt_adv = LPA_PAUSE_CAP; | |
199 | if (dev->phydev->asym_pause) | |
200 | rmt_adv |= LPA_PAUSE_ASYM; | |
201 | ||
202 | if (dev->phydev->advertising & ADVERTISED_Pause) | |
203 | lcl_adv |= ADVERTISE_PAUSE_CAP; | |
204 | if (dev->phydev->advertising & ADVERTISED_Asym_Pause) | |
205 | lcl_adv |= ADVERTISE_PAUSE_ASYM; | |
206 | ||
207 | flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); | |
208 | ||
209 | if (flowctrl & FLOW_CTRL_TX) | |
210 | mcr |= MAC_MCR_FORCE_TX_FC; | |
211 | if (flowctrl & FLOW_CTRL_RX) | |
212 | mcr |= MAC_MCR_FORCE_RX_FC; | |
213 | ||
214 | netif_dbg(mac->hw, link, dev, "rx pause %s, tx pause %s\n", | |
215 | flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled", | |
216 | flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled"); | |
217 | } | |
218 | ||
219 | mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); | |
220 | ||
221 | if (dev->phydev->link) | |
222 | netif_carrier_on(dev); | |
223 | else | |
224 | netif_carrier_off(dev); | |
225 | ||
226 | if (!of_phy_is_fixed_link(mac->of_node)) | |
227 | phy_print_status(dev->phydev); | |
228 | } | |
229 | ||
230 | static int mtk_phy_connect_node(struct mtk_eth *eth, struct mtk_mac *mac, | |
231 | struct device_node *phy_node) | |
232 | { | |
233 | struct phy_device *phydev; | |
234 | int phy_mode; | |
235 | ||
236 | phy_mode = of_get_phy_mode(phy_node); | |
237 | if (phy_mode < 0) { | |
238 | dev_err(eth->dev, "incorrect phy-mode %d\n", phy_mode); | |
239 | return -EINVAL; | |
240 | } | |
241 | ||
242 | phydev = of_phy_connect(eth->netdev[mac->id], phy_node, | |
243 | mtk_phy_link_adjust, 0, phy_mode); | |
244 | if (!phydev) { | |
245 | dev_err(eth->dev, "could not connect to PHY\n"); | |
246 | return -ENODEV; | |
247 | } | |
248 | ||
249 | dev_info(eth->dev, | |
250 | "connected mac %d to PHY at %s [uid=%08x, driver=%s]\n", | |
251 | mac->id, phydev_name(phydev), phydev->phy_id, | |
252 | phydev->drv->name); | |
253 | ||
254 | return 0; | |
255 | } | |
256 | ||
257 | static int mtk_phy_connect(struct net_device *dev) | |
258 | { | |
259 | struct mtk_mac *mac = netdev_priv(dev); | |
260 | struct mtk_eth *eth; | |
261 | struct device_node *np; | |
262 | u32 val; | |
263 | ||
264 | eth = mac->hw; | |
265 | np = of_parse_phandle(mac->of_node, "phy-handle", 0); | |
266 | if (!np && of_phy_is_fixed_link(mac->of_node)) | |
267 | if (!of_phy_register_fixed_link(mac->of_node)) | |
268 | np = of_node_get(mac->of_node); | |
269 | if (!np) | |
270 | return -ENODEV; | |
271 | ||
272 | switch (of_get_phy_mode(np)) { | |
273 | case PHY_INTERFACE_MODE_TRGMII: | |
274 | mac->trgmii = true; | |
275 | case PHY_INTERFACE_MODE_RGMII_TXID: | |
276 | case PHY_INTERFACE_MODE_RGMII_RXID: | |
277 | case PHY_INTERFACE_MODE_RGMII_ID: | |
278 | case PHY_INTERFACE_MODE_RGMII: | |
279 | mac->ge_mode = 0; | |
280 | break; | |
281 | case PHY_INTERFACE_MODE_MII: | |
282 | mac->ge_mode = 1; | |
283 | break; | |
284 | case PHY_INTERFACE_MODE_REVMII: | |
285 | mac->ge_mode = 2; | |
286 | break; | |
287 | case PHY_INTERFACE_MODE_RMII: | |
288 | if (!mac->id) | |
289 | goto err_phy; | |
290 | mac->ge_mode = 3; | |
291 | break; | |
292 | default: | |
293 | goto err_phy; | |
294 | } | |
295 | ||
296 | /* put the gmac into the right mode */ | |
297 | regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); | |
298 | val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id); | |
299 | val |= SYSCFG0_GE_MODE(mac->ge_mode, mac->id); | |
300 | regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); | |
301 | ||
302 | /* couple phydev to net_device */ | |
303 | if (mtk_phy_connect_node(eth, mac, np)) | |
304 | goto err_phy; | |
305 | ||
306 | dev->phydev->autoneg = AUTONEG_ENABLE; | |
307 | dev->phydev->speed = 0; | |
308 | dev->phydev->duplex = 0; | |
309 | ||
310 | if (of_phy_is_fixed_link(mac->of_node)) | |
311 | dev->phydev->supported |= | |
312 | SUPPORTED_Pause | SUPPORTED_Asym_Pause; | |
313 | ||
314 | dev->phydev->supported &= PHY_GBIT_FEATURES | SUPPORTED_Pause | | |
315 | SUPPORTED_Asym_Pause; | |
316 | dev->phydev->advertising = dev->phydev->supported | | |
317 | ADVERTISED_Autoneg; | |
318 | phy_start_aneg(dev->phydev); | |
319 | ||
320 | of_node_put(np); | |
321 | ||
322 | return 0; | |
323 | ||
324 | err_phy: | |
325 | if (of_phy_is_fixed_link(mac->of_node)) | |
326 | of_phy_deregister_fixed_link(mac->of_node); | |
327 | of_node_put(np); | |
328 | dev_err(eth->dev, "%s: invalid phy\n", __func__); | |
329 | return -EINVAL; | |
330 | } | |
331 | ||
332 | static int mtk_mdio_init(struct mtk_eth *eth) | |
333 | { | |
334 | struct device_node *mii_np; | |
335 | int ret; | |
336 | ||
337 | mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus"); | |
338 | if (!mii_np) { | |
339 | dev_err(eth->dev, "no %s child node found", "mdio-bus"); | |
340 | return -ENODEV; | |
341 | } | |
342 | ||
343 | if (!of_device_is_available(mii_np)) { | |
344 | ret = -ENODEV; | |
345 | goto err_put_node; | |
346 | } | |
347 | ||
348 | eth->mii_bus = devm_mdiobus_alloc(eth->dev); | |
349 | if (!eth->mii_bus) { | |
350 | ret = -ENOMEM; | |
351 | goto err_put_node; | |
352 | } | |
353 | ||
354 | eth->mii_bus->name = "mdio"; | |
355 | eth->mii_bus->read = mtk_mdio_read; | |
356 | eth->mii_bus->write = mtk_mdio_write; | |
357 | eth->mii_bus->priv = eth; | |
358 | eth->mii_bus->parent = eth->dev; | |
359 | ||
360 | snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%s", mii_np->name); | |
361 | ret = of_mdiobus_register(eth->mii_bus, mii_np); | |
362 | ||
363 | err_put_node: | |
364 | of_node_put(mii_np); | |
365 | return ret; | |
366 | } | |
367 | ||
368 | static void mtk_mdio_cleanup(struct mtk_eth *eth) | |
369 | { | |
370 | if (!eth->mii_bus) | |
371 | return; | |
372 | ||
373 | mdiobus_unregister(eth->mii_bus); | |
374 | } | |
375 | ||
376 | static inline void mtk_tx_irq_disable(struct mtk_eth *eth, u32 mask) | |
377 | { | |
378 | unsigned long flags; | |
379 | u32 val; | |
380 | ||
381 | spin_lock_irqsave(ð->tx_irq_lock, flags); | |
382 | val = mtk_r32(eth, MTK_QDMA_INT_MASK); | |
383 | mtk_w32(eth, val & ~mask, MTK_QDMA_INT_MASK); | |
384 | spin_unlock_irqrestore(ð->tx_irq_lock, flags); | |
385 | } | |
386 | ||
387 | static inline void mtk_tx_irq_enable(struct mtk_eth *eth, u32 mask) | |
388 | { | |
389 | unsigned long flags; | |
390 | u32 val; | |
391 | ||
392 | spin_lock_irqsave(ð->tx_irq_lock, flags); | |
393 | val = mtk_r32(eth, MTK_QDMA_INT_MASK); | |
394 | mtk_w32(eth, val | mask, MTK_QDMA_INT_MASK); | |
395 | spin_unlock_irqrestore(ð->tx_irq_lock, flags); | |
396 | } | |
397 | ||
398 | static inline void mtk_rx_irq_disable(struct mtk_eth *eth, u32 mask) | |
399 | { | |
400 | unsigned long flags; | |
401 | u32 val; | |
402 | ||
403 | spin_lock_irqsave(ð->rx_irq_lock, flags); | |
404 | val = mtk_r32(eth, MTK_PDMA_INT_MASK); | |
405 | mtk_w32(eth, val & ~mask, MTK_PDMA_INT_MASK); | |
406 | spin_unlock_irqrestore(ð->rx_irq_lock, flags); | |
407 | } | |
408 | ||
409 | static inline void mtk_rx_irq_enable(struct mtk_eth *eth, u32 mask) | |
410 | { | |
411 | unsigned long flags; | |
412 | u32 val; | |
413 | ||
414 | spin_lock_irqsave(ð->rx_irq_lock, flags); | |
415 | val = mtk_r32(eth, MTK_PDMA_INT_MASK); | |
416 | mtk_w32(eth, val | mask, MTK_PDMA_INT_MASK); | |
417 | spin_unlock_irqrestore(ð->rx_irq_lock, flags); | |
418 | } | |
419 | ||
420 | static int mtk_set_mac_address(struct net_device *dev, void *p) | |
421 | { | |
422 | int ret = eth_mac_addr(dev, p); | |
423 | struct mtk_mac *mac = netdev_priv(dev); | |
424 | const char *macaddr = dev->dev_addr; | |
425 | ||
426 | if (ret) | |
427 | return ret; | |
428 | ||
429 | if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) | |
430 | return -EBUSY; | |
431 | ||
432 | spin_lock_bh(&mac->hw->page_lock); | |
433 | mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], | |
434 | MTK_GDMA_MAC_ADRH(mac->id)); | |
435 | mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | | |
436 | (macaddr[4] << 8) | macaddr[5], | |
437 | MTK_GDMA_MAC_ADRL(mac->id)); | |
438 | spin_unlock_bh(&mac->hw->page_lock); | |
439 | ||
440 | return 0; | |
441 | } | |
442 | ||
443 | void mtk_stats_update_mac(struct mtk_mac *mac) | |
444 | { | |
445 | struct mtk_hw_stats *hw_stats = mac->hw_stats; | |
446 | unsigned int base = MTK_GDM1_TX_GBCNT; | |
447 | u64 stats; | |
448 | ||
449 | base += hw_stats->reg_offset; | |
450 | ||
451 | u64_stats_update_begin(&hw_stats->syncp); | |
452 | ||
453 | hw_stats->rx_bytes += mtk_r32(mac->hw, base); | |
454 | stats = mtk_r32(mac->hw, base + 0x04); | |
455 | if (stats) | |
456 | hw_stats->rx_bytes += (stats << 32); | |
457 | hw_stats->rx_packets += mtk_r32(mac->hw, base + 0x08); | |
458 | hw_stats->rx_overflow += mtk_r32(mac->hw, base + 0x10); | |
459 | hw_stats->rx_fcs_errors += mtk_r32(mac->hw, base + 0x14); | |
460 | hw_stats->rx_short_errors += mtk_r32(mac->hw, base + 0x18); | |
461 | hw_stats->rx_long_errors += mtk_r32(mac->hw, base + 0x1c); | |
462 | hw_stats->rx_checksum_errors += mtk_r32(mac->hw, base + 0x20); | |
463 | hw_stats->rx_flow_control_packets += | |
464 | mtk_r32(mac->hw, base + 0x24); | |
465 | hw_stats->tx_skip += mtk_r32(mac->hw, base + 0x28); | |
466 | hw_stats->tx_collisions += mtk_r32(mac->hw, base + 0x2c); | |
467 | hw_stats->tx_bytes += mtk_r32(mac->hw, base + 0x30); | |
468 | stats = mtk_r32(mac->hw, base + 0x34); | |
469 | if (stats) | |
470 | hw_stats->tx_bytes += (stats << 32); | |
471 | hw_stats->tx_packets += mtk_r32(mac->hw, base + 0x38); | |
472 | u64_stats_update_end(&hw_stats->syncp); | |
473 | } | |
474 | ||
475 | static void mtk_stats_update(struct mtk_eth *eth) | |
476 | { | |
477 | int i; | |
478 | ||
479 | for (i = 0; i < MTK_MAC_COUNT; i++) { | |
480 | if (!eth->mac[i] || !eth->mac[i]->hw_stats) | |
481 | continue; | |
482 | if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) { | |
483 | mtk_stats_update_mac(eth->mac[i]); | |
484 | spin_unlock(ð->mac[i]->hw_stats->stats_lock); | |
485 | } | |
486 | } | |
487 | } | |
488 | ||
489 | static void mtk_get_stats64(struct net_device *dev, | |
490 | struct rtnl_link_stats64 *storage) | |
491 | { | |
492 | struct mtk_mac *mac = netdev_priv(dev); | |
493 | struct mtk_hw_stats *hw_stats = mac->hw_stats; | |
494 | unsigned int start; | |
495 | ||
496 | if (netif_running(dev) && netif_device_present(dev)) { | |
497 | if (spin_trylock_bh(&hw_stats->stats_lock)) { | |
498 | mtk_stats_update_mac(mac); | |
499 | spin_unlock_bh(&hw_stats->stats_lock); | |
500 | } | |
501 | } | |
502 | ||
503 | do { | |
504 | start = u64_stats_fetch_begin_irq(&hw_stats->syncp); | |
505 | storage->rx_packets = hw_stats->rx_packets; | |
506 | storage->tx_packets = hw_stats->tx_packets; | |
507 | storage->rx_bytes = hw_stats->rx_bytes; | |
508 | storage->tx_bytes = hw_stats->tx_bytes; | |
509 | storage->collisions = hw_stats->tx_collisions; | |
510 | storage->rx_length_errors = hw_stats->rx_short_errors + | |
511 | hw_stats->rx_long_errors; | |
512 | storage->rx_over_errors = hw_stats->rx_overflow; | |
513 | storage->rx_crc_errors = hw_stats->rx_fcs_errors; | |
514 | storage->rx_errors = hw_stats->rx_checksum_errors; | |
515 | storage->tx_aborted_errors = hw_stats->tx_skip; | |
516 | } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start)); | |
517 | ||
518 | storage->tx_errors = dev->stats.tx_errors; | |
519 | storage->rx_dropped = dev->stats.rx_dropped; | |
520 | storage->tx_dropped = dev->stats.tx_dropped; | |
521 | } | |
522 | ||
523 | static inline int mtk_max_frag_size(int mtu) | |
524 | { | |
525 | /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */ | |
526 | if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH) | |
527 | mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN; | |
528 | ||
529 | return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) + | |
530 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); | |
531 | } | |
532 | ||
533 | static inline int mtk_max_buf_size(int frag_size) | |
534 | { | |
535 | int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN - | |
536 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); | |
537 | ||
538 | WARN_ON(buf_size < MTK_MAX_RX_LENGTH); | |
539 | ||
540 | return buf_size; | |
541 | } | |
542 | ||
543 | static inline void mtk_rx_get_desc(struct mtk_rx_dma *rxd, | |
544 | struct mtk_rx_dma *dma_rxd) | |
545 | { | |
546 | rxd->rxd1 = READ_ONCE(dma_rxd->rxd1); | |
547 | rxd->rxd2 = READ_ONCE(dma_rxd->rxd2); | |
548 | rxd->rxd3 = READ_ONCE(dma_rxd->rxd3); | |
549 | rxd->rxd4 = READ_ONCE(dma_rxd->rxd4); | |
550 | } | |
551 | ||
552 | /* the qdma core needs scratch memory to be setup */ | |
553 | static int mtk_init_fq_dma(struct mtk_eth *eth) | |
554 | { | |
555 | dma_addr_t phy_ring_tail; | |
556 | int cnt = MTK_DMA_SIZE; | |
557 | dma_addr_t dma_addr; | |
558 | int i; | |
559 | ||
560 | eth->scratch_ring = dma_alloc_coherent(eth->dev, | |
561 | cnt * sizeof(struct mtk_tx_dma), | |
562 | ð->phy_scratch_ring, | |
563 | GFP_ATOMIC | __GFP_ZERO); | |
564 | if (unlikely(!eth->scratch_ring)) | |
565 | return -ENOMEM; | |
566 | ||
567 | eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE, | |
568 | GFP_KERNEL); | |
569 | if (unlikely(!eth->scratch_head)) | |
570 | return -ENOMEM; | |
571 | ||
572 | dma_addr = dma_map_single(eth->dev, | |
573 | eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE, | |
574 | DMA_FROM_DEVICE); | |
575 | if (unlikely(dma_mapping_error(eth->dev, dma_addr))) | |
576 | return -ENOMEM; | |
577 | ||
578 | memset(eth->scratch_ring, 0x0, sizeof(struct mtk_tx_dma) * cnt); | |
579 | phy_ring_tail = eth->phy_scratch_ring + | |
580 | (sizeof(struct mtk_tx_dma) * (cnt - 1)); | |
581 | ||
582 | for (i = 0; i < cnt; i++) { | |
583 | eth->scratch_ring[i].txd1 = | |
584 | (dma_addr + (i * MTK_QDMA_PAGE_SIZE)); | |
585 | if (i < cnt - 1) | |
586 | eth->scratch_ring[i].txd2 = (eth->phy_scratch_ring + | |
587 | ((i + 1) * sizeof(struct mtk_tx_dma))); | |
588 | eth->scratch_ring[i].txd3 = TX_DMA_SDL(MTK_QDMA_PAGE_SIZE); | |
589 | } | |
590 | ||
591 | mtk_w32(eth, eth->phy_scratch_ring, MTK_QDMA_FQ_HEAD); | |
592 | mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL); | |
593 | mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT); | |
594 | mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN); | |
595 | ||
596 | return 0; | |
597 | } | |
598 | ||
599 | static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc) | |
600 | { | |
601 | void *ret = ring->dma; | |
602 | ||
603 | return ret + (desc - ring->phys); | |
604 | } | |
605 | ||
606 | static inline struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring, | |
607 | struct mtk_tx_dma *txd) | |
608 | { | |
609 | int idx = txd - ring->dma; | |
610 | ||
611 | return &ring->buf[idx]; | |
612 | } | |
613 | ||
614 | static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf) | |
615 | { | |
616 | if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) { | |
617 | dma_unmap_single(eth->dev, | |
618 | dma_unmap_addr(tx_buf, dma_addr0), | |
619 | dma_unmap_len(tx_buf, dma_len0), | |
620 | DMA_TO_DEVICE); | |
621 | } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) { | |
622 | dma_unmap_page(eth->dev, | |
623 | dma_unmap_addr(tx_buf, dma_addr0), | |
624 | dma_unmap_len(tx_buf, dma_len0), | |
625 | DMA_TO_DEVICE); | |
626 | } | |
627 | tx_buf->flags = 0; | |
628 | if (tx_buf->skb && | |
629 | (tx_buf->skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC)) | |
630 | dev_kfree_skb_any(tx_buf->skb); | |
631 | tx_buf->skb = NULL; | |
632 | } | |
633 | ||
634 | static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, | |
635 | int tx_num, struct mtk_tx_ring *ring, bool gso) | |
636 | { | |
637 | struct mtk_mac *mac = netdev_priv(dev); | |
638 | struct mtk_eth *eth = mac->hw; | |
639 | struct mtk_tx_dma *itxd, *txd; | |
640 | struct mtk_tx_buf *itx_buf, *tx_buf; | |
641 | dma_addr_t mapped_addr; | |
642 | unsigned int nr_frags; | |
643 | int i, n_desc = 1; | |
644 | u32 txd4 = 0, fport; | |
645 | ||
646 | itxd = ring->next_free; | |
647 | if (itxd == ring->last_free) | |
648 | return -ENOMEM; | |
649 | ||
650 | /* set the forward port */ | |
651 | fport = (mac->id + 1) << TX_DMA_FPORT_SHIFT; | |
652 | txd4 |= fport; | |
653 | ||
654 | itx_buf = mtk_desc_to_tx_buf(ring, itxd); | |
655 | memset(itx_buf, 0, sizeof(*itx_buf)); | |
656 | ||
657 | if (gso) | |
658 | txd4 |= TX_DMA_TSO; | |
659 | ||
660 | /* TX Checksum offload */ | |
661 | if (skb->ip_summed == CHECKSUM_PARTIAL) | |
662 | txd4 |= TX_DMA_CHKSUM; | |
663 | ||
664 | /* VLAN header offload */ | |
665 | if (skb_vlan_tag_present(skb)) | |
666 | txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb); | |
667 | ||
668 | mapped_addr = dma_map_single(eth->dev, skb->data, | |
669 | skb_headlen(skb), DMA_TO_DEVICE); | |
670 | if (unlikely(dma_mapping_error(eth->dev, mapped_addr))) | |
671 | return -ENOMEM; | |
672 | ||
673 | WRITE_ONCE(itxd->txd1, mapped_addr); | |
674 | itx_buf->flags |= MTK_TX_FLAGS_SINGLE0; | |
675 | itx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : | |
676 | MTK_TX_FLAGS_FPORT1; | |
677 | dma_unmap_addr_set(itx_buf, dma_addr0, mapped_addr); | |
678 | dma_unmap_len_set(itx_buf, dma_len0, skb_headlen(skb)); | |
679 | ||
680 | /* TX SG offload */ | |
681 | txd = itxd; | |
682 | nr_frags = skb_shinfo(skb)->nr_frags; | |
683 | for (i = 0; i < nr_frags; i++) { | |
684 | struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i]; | |
685 | unsigned int offset = 0; | |
686 | int frag_size = skb_frag_size(frag); | |
687 | ||
688 | while (frag_size) { | |
689 | bool last_frag = false; | |
690 | unsigned int frag_map_size; | |
691 | ||
692 | txd = mtk_qdma_phys_to_virt(ring, txd->txd2); | |
693 | if (txd == ring->last_free) | |
694 | goto err_dma; | |
695 | ||
696 | n_desc++; | |
697 | frag_map_size = min(frag_size, MTK_TX_DMA_BUF_LEN); | |
698 | mapped_addr = skb_frag_dma_map(eth->dev, frag, offset, | |
699 | frag_map_size, | |
700 | DMA_TO_DEVICE); | |
701 | if (unlikely(dma_mapping_error(eth->dev, mapped_addr))) | |
702 | goto err_dma; | |
703 | ||
704 | if (i == nr_frags - 1 && | |
705 | (frag_size - frag_map_size) == 0) | |
706 | last_frag = true; | |
707 | ||
708 | WRITE_ONCE(txd->txd1, mapped_addr); | |
709 | WRITE_ONCE(txd->txd3, (TX_DMA_SWC | | |
710 | TX_DMA_PLEN0(frag_map_size) | | |
711 | last_frag * TX_DMA_LS0)); | |
712 | WRITE_ONCE(txd->txd4, fport); | |
713 | ||
714 | tx_buf = mtk_desc_to_tx_buf(ring, txd); | |
715 | memset(tx_buf, 0, sizeof(*tx_buf)); | |
716 | tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC; | |
717 | tx_buf->flags |= MTK_TX_FLAGS_PAGE0; | |
718 | tx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : | |
719 | MTK_TX_FLAGS_FPORT1; | |
720 | ||
721 | dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); | |
722 | dma_unmap_len_set(tx_buf, dma_len0, frag_map_size); | |
723 | frag_size -= frag_map_size; | |
724 | offset += frag_map_size; | |
725 | } | |
726 | } | |
727 | ||
728 | /* store skb to cleanup */ | |
729 | itx_buf->skb = skb; | |
730 | ||
731 | WRITE_ONCE(itxd->txd4, txd4); | |
732 | WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) | | |
733 | (!nr_frags * TX_DMA_LS0))); | |
734 | ||
735 | netdev_sent_queue(dev, skb->len); | |
736 | skb_tx_timestamp(skb); | |
737 | ||
738 | ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2); | |
739 | atomic_sub(n_desc, &ring->free_count); | |
740 | ||
741 | /* make sure that all changes to the dma ring are flushed before we | |
742 | * continue | |
743 | */ | |
744 | wmb(); | |
745 | ||
746 | if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !skb->xmit_more) | |
747 | mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR); | |
748 | ||
749 | return 0; | |
750 | ||
751 | err_dma: | |
752 | do { | |
753 | tx_buf = mtk_desc_to_tx_buf(ring, itxd); | |
754 | ||
755 | /* unmap dma */ | |
756 | mtk_tx_unmap(eth, tx_buf); | |
757 | ||
758 | itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; | |
759 | itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2); | |
760 | } while (itxd != txd); | |
761 | ||
762 | return -ENOMEM; | |
763 | } | |
764 | ||
765 | static inline int mtk_cal_txd_req(struct sk_buff *skb) | |
766 | { | |
767 | int i, nfrags; | |
768 | struct skb_frag_struct *frag; | |
769 | ||
770 | nfrags = 1; | |
771 | if (skb_is_gso(skb)) { | |
772 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
773 | frag = &skb_shinfo(skb)->frags[i]; | |
774 | nfrags += DIV_ROUND_UP(frag->size, MTK_TX_DMA_BUF_LEN); | |
775 | } | |
776 | } else { | |
777 | nfrags += skb_shinfo(skb)->nr_frags; | |
778 | } | |
779 | ||
780 | return nfrags; | |
781 | } | |
782 | ||
783 | static int mtk_queue_stopped(struct mtk_eth *eth) | |
784 | { | |
785 | int i; | |
786 | ||
787 | for (i = 0; i < MTK_MAC_COUNT; i++) { | |
788 | if (!eth->netdev[i]) | |
789 | continue; | |
790 | if (netif_queue_stopped(eth->netdev[i])) | |
791 | return 1; | |
792 | } | |
793 | ||
794 | return 0; | |
795 | } | |
796 | ||
797 | static void mtk_wake_queue(struct mtk_eth *eth) | |
798 | { | |
799 | int i; | |
800 | ||
801 | for (i = 0; i < MTK_MAC_COUNT; i++) { | |
802 | if (!eth->netdev[i]) | |
803 | continue; | |
804 | netif_wake_queue(eth->netdev[i]); | |
805 | } | |
806 | } | |
807 | ||
808 | static void mtk_stop_queue(struct mtk_eth *eth) | |
809 | { | |
810 | int i; | |
811 | ||
812 | for (i = 0; i < MTK_MAC_COUNT; i++) { | |
813 | if (!eth->netdev[i]) | |
814 | continue; | |
815 | netif_stop_queue(eth->netdev[i]); | |
816 | } | |
817 | } | |
818 | ||
819 | static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
820 | { | |
821 | struct mtk_mac *mac = netdev_priv(dev); | |
822 | struct mtk_eth *eth = mac->hw; | |
823 | struct mtk_tx_ring *ring = ð->tx_ring; | |
824 | struct net_device_stats *stats = &dev->stats; | |
825 | bool gso = false; | |
826 | int tx_num; | |
827 | ||
828 | /* normally we can rely on the stack not calling this more than once, | |
829 | * however we have 2 queues running on the same ring so we need to lock | |
830 | * the ring access | |
831 | */ | |
832 | spin_lock(ð->page_lock); | |
833 | ||
834 | if (unlikely(test_bit(MTK_RESETTING, ð->state))) | |
835 | goto drop; | |
836 | ||
837 | tx_num = mtk_cal_txd_req(skb); | |
838 | if (unlikely(atomic_read(&ring->free_count) <= tx_num)) { | |
839 | mtk_stop_queue(eth); | |
840 | netif_err(eth, tx_queued, dev, | |
841 | "Tx Ring full when queue awake!\n"); | |
842 | spin_unlock(ð->page_lock); | |
843 | return NETDEV_TX_BUSY; | |
844 | } | |
845 | ||
846 | /* TSO: fill MSS info in tcp checksum field */ | |
847 | if (skb_is_gso(skb)) { | |
848 | if (skb_cow_head(skb, 0)) { | |
849 | netif_warn(eth, tx_err, dev, | |
850 | "GSO expand head fail.\n"); | |
851 | goto drop; | |
852 | } | |
853 | ||
854 | if (skb_shinfo(skb)->gso_type & | |
855 | (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) { | |
856 | gso = true; | |
857 | tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size); | |
858 | } | |
859 | } | |
860 | ||
861 | if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0) | |
862 | goto drop; | |
863 | ||
864 | if (unlikely(atomic_read(&ring->free_count) <= ring->thresh)) | |
865 | mtk_stop_queue(eth); | |
866 | ||
867 | spin_unlock(ð->page_lock); | |
868 | ||
869 | return NETDEV_TX_OK; | |
870 | ||
871 | drop: | |
872 | spin_unlock(ð->page_lock); | |
873 | stats->tx_dropped++; | |
874 | dev_kfree_skb_any(skb); | |
875 | return NETDEV_TX_OK; | |
876 | } | |
877 | ||
878 | static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth) | |
879 | { | |
880 | int i; | |
881 | struct mtk_rx_ring *ring; | |
882 | int idx; | |
883 | ||
884 | if (!eth->hwlro) | |
885 | return ð->rx_ring[0]; | |
886 | ||
887 | for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { | |
888 | ring = ð->rx_ring[i]; | |
889 | idx = NEXT_RX_DESP_IDX(ring->calc_idx, ring->dma_size); | |
890 | if (ring->dma[idx].rxd2 & RX_DMA_DONE) { | |
891 | ring->calc_idx_update = true; | |
892 | return ring; | |
893 | } | |
894 | } | |
895 | ||
896 | return NULL; | |
897 | } | |
898 | ||
899 | static void mtk_update_rx_cpu_idx(struct mtk_eth *eth) | |
900 | { | |
901 | struct mtk_rx_ring *ring; | |
902 | int i; | |
903 | ||
904 | if (!eth->hwlro) { | |
905 | ring = ð->rx_ring[0]; | |
906 | mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); | |
907 | } else { | |
908 | for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { | |
909 | ring = ð->rx_ring[i]; | |
910 | if (ring->calc_idx_update) { | |
911 | ring->calc_idx_update = false; | |
912 | mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); | |
913 | } | |
914 | } | |
915 | } | |
916 | } | |
917 | ||
918 | static int mtk_poll_rx(struct napi_struct *napi, int budget, | |
919 | struct mtk_eth *eth) | |
920 | { | |
921 | struct mtk_rx_ring *ring; | |
922 | int idx; | |
923 | struct sk_buff *skb; | |
924 | u8 *data, *new_data; | |
925 | struct mtk_rx_dma *rxd, trxd; | |
926 | int done = 0; | |
927 | ||
928 | while (done < budget) { | |
929 | struct net_device *netdev; | |
930 | unsigned int pktlen; | |
931 | dma_addr_t dma_addr; | |
932 | int mac = 0; | |
933 | ||
934 | ring = mtk_get_rx_ring(eth); | |
935 | if (unlikely(!ring)) | |
936 | goto rx_done; | |
937 | ||
938 | idx = NEXT_RX_DESP_IDX(ring->calc_idx, ring->dma_size); | |
939 | rxd = &ring->dma[idx]; | |
940 | data = ring->data[idx]; | |
941 | ||
942 | mtk_rx_get_desc(&trxd, rxd); | |
943 | if (!(trxd.rxd2 & RX_DMA_DONE)) | |
944 | break; | |
945 | ||
946 | /* find out which mac the packet come from. values start at 1 */ | |
947 | mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) & | |
948 | RX_DMA_FPORT_MASK; | |
949 | mac--; | |
950 | ||
951 | if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT || | |
952 | !eth->netdev[mac])) | |
953 | goto release_desc; | |
954 | ||
955 | netdev = eth->netdev[mac]; | |
956 | ||
957 | if (unlikely(test_bit(MTK_RESETTING, ð->state))) | |
958 | goto release_desc; | |
959 | ||
960 | /* alloc new buffer */ | |
961 | new_data = napi_alloc_frag(ring->frag_size); | |
962 | if (unlikely(!new_data)) { | |
963 | netdev->stats.rx_dropped++; | |
964 | goto release_desc; | |
965 | } | |
966 | dma_addr = dma_map_single(eth->dev, | |
967 | new_data + NET_SKB_PAD, | |
968 | ring->buf_size, | |
969 | DMA_FROM_DEVICE); | |
970 | if (unlikely(dma_mapping_error(eth->dev, dma_addr))) { | |
971 | skb_free_frag(new_data); | |
972 | netdev->stats.rx_dropped++; | |
973 | goto release_desc; | |
974 | } | |
975 | ||
976 | /* receive data */ | |
977 | skb = build_skb(data, ring->frag_size); | |
978 | if (unlikely(!skb)) { | |
979 | skb_free_frag(new_data); | |
980 | netdev->stats.rx_dropped++; | |
981 | goto release_desc; | |
982 | } | |
983 | skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN); | |
984 | ||
985 | dma_unmap_single(eth->dev, trxd.rxd1, | |
986 | ring->buf_size, DMA_FROM_DEVICE); | |
987 | pktlen = RX_DMA_GET_PLEN0(trxd.rxd2); | |
988 | skb->dev = netdev; | |
989 | skb_put(skb, pktlen); | |
990 | if (trxd.rxd4 & RX_DMA_L4_VALID) | |
991 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
992 | else | |
993 | skb_checksum_none_assert(skb); | |
994 | skb->protocol = eth_type_trans(skb, netdev); | |
995 | ||
996 | if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX && | |
997 | RX_DMA_VID(trxd.rxd3)) | |
998 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), | |
999 | RX_DMA_VID(trxd.rxd3)); | |
1000 | skb_record_rx_queue(skb, 0); | |
1001 | napi_gro_receive(napi, skb); | |
1002 | ||
1003 | ring->data[idx] = new_data; | |
1004 | rxd->rxd1 = (unsigned int)dma_addr; | |
1005 | ||
1006 | release_desc: | |
1007 | rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size); | |
1008 | ||
1009 | ring->calc_idx = idx; | |
1010 | ||
1011 | done++; | |
1012 | } | |
1013 | ||
1014 | rx_done: | |
1015 | if (done) { | |
1016 | /* make sure that all changes to the dma ring are flushed before | |
1017 | * we continue | |
1018 | */ | |
1019 | wmb(); | |
1020 | mtk_update_rx_cpu_idx(eth); | |
1021 | } | |
1022 | ||
1023 | return done; | |
1024 | } | |
1025 | ||
1026 | static int mtk_poll_tx(struct mtk_eth *eth, int budget) | |
1027 | { | |
1028 | struct mtk_tx_ring *ring = ð->tx_ring; | |
1029 | struct mtk_tx_dma *desc; | |
1030 | struct sk_buff *skb; | |
1031 | struct mtk_tx_buf *tx_buf; | |
1032 | unsigned int done[MTK_MAX_DEVS]; | |
1033 | unsigned int bytes[MTK_MAX_DEVS]; | |
1034 | u32 cpu, dma; | |
1035 | static int condition; | |
1036 | int total = 0, i; | |
1037 | ||
1038 | memset(done, 0, sizeof(done)); | |
1039 | memset(bytes, 0, sizeof(bytes)); | |
1040 | ||
1041 | cpu = mtk_r32(eth, MTK_QTX_CRX_PTR); | |
1042 | dma = mtk_r32(eth, MTK_QTX_DRX_PTR); | |
1043 | ||
1044 | desc = mtk_qdma_phys_to_virt(ring, cpu); | |
1045 | ||
1046 | while ((cpu != dma) && budget) { | |
1047 | u32 next_cpu = desc->txd2; | |
1048 | int mac = 0; | |
1049 | ||
1050 | desc = mtk_qdma_phys_to_virt(ring, desc->txd2); | |
1051 | if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0) | |
1052 | break; | |
1053 | ||
1054 | tx_buf = mtk_desc_to_tx_buf(ring, desc); | |
1055 | if (tx_buf->flags & MTK_TX_FLAGS_FPORT1) | |
1056 | mac = 1; | |
1057 | ||
1058 | skb = tx_buf->skb; | |
1059 | if (!skb) { | |
1060 | condition = 1; | |
1061 | break; | |
1062 | } | |
1063 | ||
1064 | if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) { | |
1065 | bytes[mac] += skb->len; | |
1066 | done[mac]++; | |
1067 | budget--; | |
1068 | } | |
1069 | mtk_tx_unmap(eth, tx_buf); | |
1070 | ||
1071 | ring->last_free = desc; | |
1072 | atomic_inc(&ring->free_count); | |
1073 | ||
1074 | cpu = next_cpu; | |
1075 | } | |
1076 | ||
1077 | mtk_w32(eth, cpu, MTK_QTX_CRX_PTR); | |
1078 | ||
1079 | for (i = 0; i < MTK_MAC_COUNT; i++) { | |
1080 | if (!eth->netdev[i] || !done[i]) | |
1081 | continue; | |
1082 | netdev_completed_queue(eth->netdev[i], done[i], bytes[i]); | |
1083 | total += done[i]; | |
1084 | } | |
1085 | ||
1086 | if (mtk_queue_stopped(eth) && | |
1087 | (atomic_read(&ring->free_count) > ring->thresh)) | |
1088 | mtk_wake_queue(eth); | |
1089 | ||
1090 | return total; | |
1091 | } | |
1092 | ||
1093 | static void mtk_handle_status_irq(struct mtk_eth *eth) | |
1094 | { | |
1095 | u32 status2 = mtk_r32(eth, MTK_INT_STATUS2); | |
1096 | ||
1097 | if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) { | |
1098 | mtk_stats_update(eth); | |
1099 | mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF), | |
1100 | MTK_INT_STATUS2); | |
1101 | } | |
1102 | } | |
1103 | ||
1104 | static int mtk_napi_tx(struct napi_struct *napi, int budget) | |
1105 | { | |
1106 | struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi); | |
1107 | u32 status, mask; | |
1108 | int tx_done = 0; | |
1109 | ||
1110 | mtk_handle_status_irq(eth); | |
1111 | mtk_w32(eth, MTK_TX_DONE_INT, MTK_QMTK_INT_STATUS); | |
1112 | tx_done = mtk_poll_tx(eth, budget); | |
1113 | ||
1114 | if (unlikely(netif_msg_intr(eth))) { | |
1115 | status = mtk_r32(eth, MTK_QMTK_INT_STATUS); | |
1116 | mask = mtk_r32(eth, MTK_QDMA_INT_MASK); | |
1117 | dev_info(eth->dev, | |
1118 | "done tx %d, intr 0x%08x/0x%x\n", | |
1119 | tx_done, status, mask); | |
1120 | } | |
1121 | ||
1122 | if (tx_done == budget) | |
1123 | return budget; | |
1124 | ||
1125 | status = mtk_r32(eth, MTK_QMTK_INT_STATUS); | |
1126 | if (status & MTK_TX_DONE_INT) | |
1127 | return budget; | |
1128 | ||
1129 | napi_complete(napi); | |
1130 | mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); | |
1131 | ||
1132 | return tx_done; | |
1133 | } | |
1134 | ||
1135 | static int mtk_napi_rx(struct napi_struct *napi, int budget) | |
1136 | { | |
1137 | struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi); | |
1138 | u32 status, mask; | |
1139 | int rx_done = 0; | |
1140 | int remain_budget = budget; | |
1141 | ||
1142 | mtk_handle_status_irq(eth); | |
1143 | ||
1144 | poll_again: | |
1145 | mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_STATUS); | |
1146 | rx_done = mtk_poll_rx(napi, remain_budget, eth); | |
1147 | ||
1148 | if (unlikely(netif_msg_intr(eth))) { | |
1149 | status = mtk_r32(eth, MTK_PDMA_INT_STATUS); | |
1150 | mask = mtk_r32(eth, MTK_PDMA_INT_MASK); | |
1151 | dev_info(eth->dev, | |
1152 | "done rx %d, intr 0x%08x/0x%x\n", | |
1153 | rx_done, status, mask); | |
1154 | } | |
1155 | if (rx_done == remain_budget) | |
1156 | return budget; | |
1157 | ||
1158 | status = mtk_r32(eth, MTK_PDMA_INT_STATUS); | |
1159 | if (status & MTK_RX_DONE_INT) { | |
1160 | remain_budget -= rx_done; | |
1161 | goto poll_again; | |
1162 | } | |
1163 | napi_complete(napi); | |
1164 | mtk_rx_irq_enable(eth, MTK_RX_DONE_INT); | |
1165 | ||
1166 | return rx_done + budget - remain_budget; | |
1167 | } | |
1168 | ||
1169 | static int mtk_tx_alloc(struct mtk_eth *eth) | |
1170 | { | |
1171 | struct mtk_tx_ring *ring = ð->tx_ring; | |
1172 | int i, sz = sizeof(*ring->dma); | |
1173 | ||
1174 | ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf), | |
1175 | GFP_KERNEL); | |
1176 | if (!ring->buf) | |
1177 | goto no_tx_mem; | |
1178 | ||
1179 | ring->dma = dma_alloc_coherent(eth->dev, | |
1180 | MTK_DMA_SIZE * sz, | |
1181 | &ring->phys, | |
1182 | GFP_ATOMIC | __GFP_ZERO); | |
1183 | if (!ring->dma) | |
1184 | goto no_tx_mem; | |
1185 | ||
1186 | memset(ring->dma, 0, MTK_DMA_SIZE * sz); | |
1187 | for (i = 0; i < MTK_DMA_SIZE; i++) { | |
1188 | int next = (i + 1) % MTK_DMA_SIZE; | |
1189 | u32 next_ptr = ring->phys + next * sz; | |
1190 | ||
1191 | ring->dma[i].txd2 = next_ptr; | |
1192 | ring->dma[i].txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; | |
1193 | } | |
1194 | ||
1195 | atomic_set(&ring->free_count, MTK_DMA_SIZE - 2); | |
1196 | ring->next_free = &ring->dma[0]; | |
1197 | ring->last_free = &ring->dma[MTK_DMA_SIZE - 1]; | |
1198 | ring->thresh = MAX_SKB_FRAGS; | |
1199 | ||
1200 | /* make sure that all changes to the dma ring are flushed before we | |
1201 | * continue | |
1202 | */ | |
1203 | wmb(); | |
1204 | ||
1205 | mtk_w32(eth, ring->phys, MTK_QTX_CTX_PTR); | |
1206 | mtk_w32(eth, ring->phys, MTK_QTX_DTX_PTR); | |
1207 | mtk_w32(eth, | |
1208 | ring->phys + ((MTK_DMA_SIZE - 1) * sz), | |
1209 | MTK_QTX_CRX_PTR); | |
1210 | mtk_w32(eth, | |
1211 | ring->phys + ((MTK_DMA_SIZE - 1) * sz), | |
1212 | MTK_QTX_DRX_PTR); | |
1213 | mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, MTK_QTX_CFG(0)); | |
1214 | ||
1215 | return 0; | |
1216 | ||
1217 | no_tx_mem: | |
1218 | return -ENOMEM; | |
1219 | } | |
1220 | ||
1221 | static void mtk_tx_clean(struct mtk_eth *eth) | |
1222 | { | |
1223 | struct mtk_tx_ring *ring = ð->tx_ring; | |
1224 | int i; | |
1225 | ||
1226 | if (ring->buf) { | |
1227 | for (i = 0; i < MTK_DMA_SIZE; i++) | |
1228 | mtk_tx_unmap(eth, &ring->buf[i]); | |
1229 | kfree(ring->buf); | |
1230 | ring->buf = NULL; | |
1231 | } | |
1232 | ||
1233 | if (ring->dma) { | |
1234 | dma_free_coherent(eth->dev, | |
1235 | MTK_DMA_SIZE * sizeof(*ring->dma), | |
1236 | ring->dma, | |
1237 | ring->phys); | |
1238 | ring->dma = NULL; | |
1239 | } | |
1240 | } | |
1241 | ||
1242 | static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag) | |
1243 | { | |
1244 | struct mtk_rx_ring *ring = ð->rx_ring[ring_no]; | |
1245 | int rx_data_len, rx_dma_size; | |
1246 | int i; | |
1247 | ||
1248 | if (rx_flag == MTK_RX_FLAGS_HWLRO) { | |
1249 | rx_data_len = MTK_MAX_LRO_RX_LENGTH; | |
1250 | rx_dma_size = MTK_HW_LRO_DMA_SIZE; | |
1251 | } else { | |
1252 | rx_data_len = ETH_DATA_LEN; | |
1253 | rx_dma_size = MTK_DMA_SIZE; | |
1254 | } | |
1255 | ||
1256 | ring->frag_size = mtk_max_frag_size(rx_data_len); | |
1257 | ring->buf_size = mtk_max_buf_size(ring->frag_size); | |
1258 | ring->data = kcalloc(rx_dma_size, sizeof(*ring->data), | |
1259 | GFP_KERNEL); | |
1260 | if (!ring->data) | |
1261 | return -ENOMEM; | |
1262 | ||
1263 | for (i = 0; i < rx_dma_size; i++) { | |
1264 | ring->data[i] = netdev_alloc_frag(ring->frag_size); | |
1265 | if (!ring->data[i]) | |
1266 | return -ENOMEM; | |
1267 | } | |
1268 | ||
1269 | ring->dma = dma_alloc_coherent(eth->dev, | |
1270 | rx_dma_size * sizeof(*ring->dma), | |
1271 | &ring->phys, | |
1272 | GFP_ATOMIC | __GFP_ZERO); | |
1273 | if (!ring->dma) | |
1274 | return -ENOMEM; | |
1275 | ||
1276 | for (i = 0; i < rx_dma_size; i++) { | |
1277 | dma_addr_t dma_addr = dma_map_single(eth->dev, | |
1278 | ring->data[i] + NET_SKB_PAD, | |
1279 | ring->buf_size, | |
1280 | DMA_FROM_DEVICE); | |
1281 | if (unlikely(dma_mapping_error(eth->dev, dma_addr))) | |
1282 | return -ENOMEM; | |
1283 | ring->dma[i].rxd1 = (unsigned int)dma_addr; | |
1284 | ||
1285 | ring->dma[i].rxd2 = RX_DMA_PLEN0(ring->buf_size); | |
1286 | } | |
1287 | ring->dma_size = rx_dma_size; | |
1288 | ring->calc_idx_update = false; | |
1289 | ring->calc_idx = rx_dma_size - 1; | |
1290 | ring->crx_idx_reg = MTK_PRX_CRX_IDX_CFG(ring_no); | |
1291 | /* make sure that all changes to the dma ring are flushed before we | |
1292 | * continue | |
1293 | */ | |
1294 | wmb(); | |
1295 | ||
1296 | mtk_w32(eth, ring->phys, MTK_PRX_BASE_PTR_CFG(ring_no)); | |
1297 | mtk_w32(eth, rx_dma_size, MTK_PRX_MAX_CNT_CFG(ring_no)); | |
1298 | mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); | |
1299 | mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), MTK_PDMA_RST_IDX); | |
1300 | ||
1301 | return 0; | |
1302 | } | |
1303 | ||
1304 | static void mtk_rx_clean(struct mtk_eth *eth, int ring_no) | |
1305 | { | |
1306 | struct mtk_rx_ring *ring = ð->rx_ring[ring_no]; | |
1307 | int i; | |
1308 | ||
1309 | if (ring->data && ring->dma) { | |
1310 | for (i = 0; i < ring->dma_size; i++) { | |
1311 | if (!ring->data[i]) | |
1312 | continue; | |
1313 | if (!ring->dma[i].rxd1) | |
1314 | continue; | |
1315 | dma_unmap_single(eth->dev, | |
1316 | ring->dma[i].rxd1, | |
1317 | ring->buf_size, | |
1318 | DMA_FROM_DEVICE); | |
1319 | skb_free_frag(ring->data[i]); | |
1320 | } | |
1321 | kfree(ring->data); | |
1322 | ring->data = NULL; | |
1323 | } | |
1324 | ||
1325 | if (ring->dma) { | |
1326 | dma_free_coherent(eth->dev, | |
1327 | ring->dma_size * sizeof(*ring->dma), | |
1328 | ring->dma, | |
1329 | ring->phys); | |
1330 | ring->dma = NULL; | |
1331 | } | |
1332 | } | |
1333 | ||
1334 | static int mtk_hwlro_rx_init(struct mtk_eth *eth) | |
1335 | { | |
1336 | int i; | |
1337 | u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0; | |
1338 | u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0; | |
1339 | ||
1340 | /* set LRO rings to auto-learn modes */ | |
1341 | ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE; | |
1342 | ||
1343 | /* validate LRO ring */ | |
1344 | ring_ctrl_dw2 |= MTK_RING_VLD; | |
1345 | ||
1346 | /* set AGE timer (unit: 20us) */ | |
1347 | ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H; | |
1348 | ring_ctrl_dw1 |= MTK_RING_AGE_TIME_L; | |
1349 | ||
1350 | /* set max AGG timer (unit: 20us) */ | |
1351 | ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME; | |
1352 | ||
1353 | /* set max LRO AGG count */ | |
1354 | ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L; | |
1355 | ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H; | |
1356 | ||
1357 | for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { | |
1358 | mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i)); | |
1359 | mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i)); | |
1360 | mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i)); | |
1361 | } | |
1362 | ||
1363 | /* IPv4 checksum update enable */ | |
1364 | lro_ctrl_dw0 |= MTK_L3_CKS_UPD_EN; | |
1365 | ||
1366 | /* switch priority comparison to packet count mode */ | |
1367 | lro_ctrl_dw0 |= MTK_LRO_ALT_PKT_CNT_MODE; | |
1368 | ||
1369 | /* bandwidth threshold setting */ | |
1370 | mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2); | |
1371 | ||
1372 | /* auto-learn score delta setting */ | |
1373 | mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA); | |
1374 | ||
1375 | /* set refresh timer for altering flows to 1 sec. (unit: 20us) */ | |
1376 | mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME, | |
1377 | MTK_PDMA_LRO_ALT_REFRESH_TIMER); | |
1378 | ||
1379 | /* set HW LRO mode & the max aggregation count for rx packets */ | |
1380 | lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff); | |
1381 | ||
1382 | /* the minimal remaining room of SDL0 in RXD for lro aggregation */ | |
1383 | lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL; | |
1384 | ||
1385 | /* enable HW LRO */ | |
1386 | lro_ctrl_dw0 |= MTK_LRO_EN; | |
1387 | ||
1388 | mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3); | |
1389 | mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0); | |
1390 | ||
1391 | return 0; | |
1392 | } | |
1393 | ||
1394 | static void mtk_hwlro_rx_uninit(struct mtk_eth *eth) | |
1395 | { | |
1396 | int i; | |
1397 | u32 val; | |
1398 | ||
1399 | /* relinquish lro rings, flush aggregated packets */ | |
1400 | mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0); | |
1401 | ||
1402 | /* wait for relinquishments done */ | |
1403 | for (i = 0; i < 10; i++) { | |
1404 | val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0); | |
1405 | if (val & MTK_LRO_RING_RELINQUISH_DONE) { | |
1406 | msleep(20); | |
1407 | continue; | |
1408 | } | |
1409 | break; | |
1410 | } | |
1411 | ||
1412 | /* invalidate lro rings */ | |
1413 | for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) | |
1414 | mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i)); | |
1415 | ||
1416 | /* disable HW LRO */ | |
1417 | mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0); | |
1418 | } | |
1419 | ||
1420 | static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip) | |
1421 | { | |
1422 | u32 reg_val; | |
1423 | ||
1424 | reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); | |
1425 | ||
1426 | /* invalidate the IP setting */ | |
1427 | mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); | |
1428 | ||
1429 | mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx)); | |
1430 | ||
1431 | /* validate the IP setting */ | |
1432 | mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); | |
1433 | } | |
1434 | ||
1435 | static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx) | |
1436 | { | |
1437 | u32 reg_val; | |
1438 | ||
1439 | reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); | |
1440 | ||
1441 | /* invalidate the IP setting */ | |
1442 | mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); | |
1443 | ||
1444 | mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx)); | |
1445 | } | |
1446 | ||
1447 | static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac) | |
1448 | { | |
1449 | int cnt = 0; | |
1450 | int i; | |
1451 | ||
1452 | for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { | |
1453 | if (mac->hwlro_ip[i]) | |
1454 | cnt++; | |
1455 | } | |
1456 | ||
1457 | return cnt; | |
1458 | } | |
1459 | ||
1460 | static int mtk_hwlro_add_ipaddr(struct net_device *dev, | |
1461 | struct ethtool_rxnfc *cmd) | |
1462 | { | |
1463 | struct ethtool_rx_flow_spec *fsp = | |
1464 | (struct ethtool_rx_flow_spec *)&cmd->fs; | |
1465 | struct mtk_mac *mac = netdev_priv(dev); | |
1466 | struct mtk_eth *eth = mac->hw; | |
1467 | int hwlro_idx; | |
1468 | ||
1469 | if ((fsp->flow_type != TCP_V4_FLOW) || | |
1470 | (!fsp->h_u.tcp_ip4_spec.ip4dst) || | |
1471 | (fsp->location > 1)) | |
1472 | return -EINVAL; | |
1473 | ||
1474 | mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst); | |
1475 | hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; | |
1476 | ||
1477 | mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); | |
1478 | ||
1479 | mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]); | |
1480 | ||
1481 | return 0; | |
1482 | } | |
1483 | ||
1484 | static int mtk_hwlro_del_ipaddr(struct net_device *dev, | |
1485 | struct ethtool_rxnfc *cmd) | |
1486 | { | |
1487 | struct ethtool_rx_flow_spec *fsp = | |
1488 | (struct ethtool_rx_flow_spec *)&cmd->fs; | |
1489 | struct mtk_mac *mac = netdev_priv(dev); | |
1490 | struct mtk_eth *eth = mac->hw; | |
1491 | int hwlro_idx; | |
1492 | ||
1493 | if (fsp->location > 1) | |
1494 | return -EINVAL; | |
1495 | ||
1496 | mac->hwlro_ip[fsp->location] = 0; | |
1497 | hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; | |
1498 | ||
1499 | mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); | |
1500 | ||
1501 | mtk_hwlro_inval_ipaddr(eth, hwlro_idx); | |
1502 | ||
1503 | return 0; | |
1504 | } | |
1505 | ||
1506 | static void mtk_hwlro_netdev_disable(struct net_device *dev) | |
1507 | { | |
1508 | struct mtk_mac *mac = netdev_priv(dev); | |
1509 | struct mtk_eth *eth = mac->hw; | |
1510 | int i, hwlro_idx; | |
1511 | ||
1512 | for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { | |
1513 | mac->hwlro_ip[i] = 0; | |
1514 | hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i; | |
1515 | ||
1516 | mtk_hwlro_inval_ipaddr(eth, hwlro_idx); | |
1517 | } | |
1518 | ||
1519 | mac->hwlro_ip_cnt = 0; | |
1520 | } | |
1521 | ||
1522 | static int mtk_hwlro_get_fdir_entry(struct net_device *dev, | |
1523 | struct ethtool_rxnfc *cmd) | |
1524 | { | |
1525 | struct mtk_mac *mac = netdev_priv(dev); | |
1526 | struct ethtool_rx_flow_spec *fsp = | |
1527 | (struct ethtool_rx_flow_spec *)&cmd->fs; | |
1528 | ||
1529 | /* only tcp dst ipv4 is meaningful, others are meaningless */ | |
1530 | fsp->flow_type = TCP_V4_FLOW; | |
1531 | fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]); | |
1532 | fsp->m_u.tcp_ip4_spec.ip4dst = 0; | |
1533 | ||
1534 | fsp->h_u.tcp_ip4_spec.ip4src = 0; | |
1535 | fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff; | |
1536 | fsp->h_u.tcp_ip4_spec.psrc = 0; | |
1537 | fsp->m_u.tcp_ip4_spec.psrc = 0xffff; | |
1538 | fsp->h_u.tcp_ip4_spec.pdst = 0; | |
1539 | fsp->m_u.tcp_ip4_spec.pdst = 0xffff; | |
1540 | fsp->h_u.tcp_ip4_spec.tos = 0; | |
1541 | fsp->m_u.tcp_ip4_spec.tos = 0xff; | |
1542 | ||
1543 | return 0; | |
1544 | } | |
1545 | ||
1546 | static int mtk_hwlro_get_fdir_all(struct net_device *dev, | |
1547 | struct ethtool_rxnfc *cmd, | |
1548 | u32 *rule_locs) | |
1549 | { | |
1550 | struct mtk_mac *mac = netdev_priv(dev); | |
1551 | int cnt = 0; | |
1552 | int i; | |
1553 | ||
1554 | for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { | |
1555 | if (mac->hwlro_ip[i]) { | |
1556 | rule_locs[cnt] = i; | |
1557 | cnt++; | |
1558 | } | |
1559 | } | |
1560 | ||
1561 | cmd->rule_cnt = cnt; | |
1562 | ||
1563 | return 0; | |
1564 | } | |
1565 | ||
1566 | static netdev_features_t mtk_fix_features(struct net_device *dev, | |
1567 | netdev_features_t features) | |
1568 | { | |
1569 | if (!(features & NETIF_F_LRO)) { | |
1570 | struct mtk_mac *mac = netdev_priv(dev); | |
1571 | int ip_cnt = mtk_hwlro_get_ip_cnt(mac); | |
1572 | ||
1573 | if (ip_cnt) { | |
1574 | netdev_info(dev, "RX flow is programmed, LRO should keep on\n"); | |
1575 | ||
1576 | features |= NETIF_F_LRO; | |
1577 | } | |
1578 | } | |
1579 | ||
1580 | return features; | |
1581 | } | |
1582 | ||
1583 | static int mtk_set_features(struct net_device *dev, netdev_features_t features) | |
1584 | { | |
1585 | int err = 0; | |
1586 | ||
1587 | if (!((dev->features ^ features) & NETIF_F_LRO)) | |
1588 | return 0; | |
1589 | ||
1590 | if (!(features & NETIF_F_LRO)) | |
1591 | mtk_hwlro_netdev_disable(dev); | |
1592 | ||
1593 | return err; | |
1594 | } | |
1595 | ||
1596 | /* wait for DMA to finish whatever it is doing before we start using it again */ | |
1597 | static int mtk_dma_busy_wait(struct mtk_eth *eth) | |
1598 | { | |
1599 | unsigned long t_start = jiffies; | |
1600 | ||
1601 | while (1) { | |
1602 | if (!(mtk_r32(eth, MTK_QDMA_GLO_CFG) & | |
1603 | (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY))) | |
1604 | return 0; | |
1605 | if (time_after(jiffies, t_start + MTK_DMA_BUSY_TIMEOUT)) | |
1606 | break; | |
1607 | } | |
1608 | ||
1609 | dev_err(eth->dev, "DMA init timeout\n"); | |
1610 | return -1; | |
1611 | } | |
1612 | ||
1613 | static int mtk_dma_init(struct mtk_eth *eth) | |
1614 | { | |
1615 | int err; | |
1616 | u32 i; | |
1617 | ||
1618 | if (mtk_dma_busy_wait(eth)) | |
1619 | return -EBUSY; | |
1620 | ||
1621 | /* QDMA needs scratch memory for internal reordering of the | |
1622 | * descriptors | |
1623 | */ | |
1624 | err = mtk_init_fq_dma(eth); | |
1625 | if (err) | |
1626 | return err; | |
1627 | ||
1628 | err = mtk_tx_alloc(eth); | |
1629 | if (err) | |
1630 | return err; | |
1631 | ||
1632 | err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL); | |
1633 | if (err) | |
1634 | return err; | |
1635 | ||
1636 | if (eth->hwlro) { | |
1637 | for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { | |
1638 | err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO); | |
1639 | if (err) | |
1640 | return err; | |
1641 | } | |
1642 | err = mtk_hwlro_rx_init(eth); | |
1643 | if (err) | |
1644 | return err; | |
1645 | } | |
1646 | ||
1647 | /* Enable random early drop and set drop threshold automatically */ | |
1648 | mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | FC_THRES_MIN, | |
1649 | MTK_QDMA_FC_THRES); | |
1650 | mtk_w32(eth, 0x0, MTK_QDMA_HRED2); | |
1651 | ||
1652 | return 0; | |
1653 | } | |
1654 | ||
1655 | static void mtk_dma_free(struct mtk_eth *eth) | |
1656 | { | |
1657 | int i; | |
1658 | ||
1659 | for (i = 0; i < MTK_MAC_COUNT; i++) | |
1660 | if (eth->netdev[i]) | |
1661 | netdev_reset_queue(eth->netdev[i]); | |
1662 | if (eth->scratch_ring) { | |
1663 | dma_free_coherent(eth->dev, | |
1664 | MTK_DMA_SIZE * sizeof(struct mtk_tx_dma), | |
1665 | eth->scratch_ring, | |
1666 | eth->phy_scratch_ring); | |
1667 | eth->scratch_ring = NULL; | |
1668 | eth->phy_scratch_ring = 0; | |
1669 | } | |
1670 | mtk_tx_clean(eth); | |
1671 | mtk_rx_clean(eth, 0); | |
1672 | ||
1673 | if (eth->hwlro) { | |
1674 | mtk_hwlro_rx_uninit(eth); | |
1675 | for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) | |
1676 | mtk_rx_clean(eth, i); | |
1677 | } | |
1678 | ||
1679 | kfree(eth->scratch_head); | |
1680 | } | |
1681 | ||
1682 | static void mtk_tx_timeout(struct net_device *dev) | |
1683 | { | |
1684 | struct mtk_mac *mac = netdev_priv(dev); | |
1685 | struct mtk_eth *eth = mac->hw; | |
1686 | ||
1687 | eth->netdev[mac->id]->stats.tx_errors++; | |
1688 | netif_err(eth, tx_err, dev, | |
1689 | "transmit timed out\n"); | |
1690 | schedule_work(ð->pending_work); | |
1691 | } | |
1692 | ||
1693 | static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth) | |
1694 | { | |
1695 | struct mtk_eth *eth = _eth; | |
1696 | ||
1697 | if (likely(napi_schedule_prep(ð->rx_napi))) { | |
1698 | __napi_schedule(ð->rx_napi); | |
1699 | mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); | |
1700 | } | |
1701 | ||
1702 | return IRQ_HANDLED; | |
1703 | } | |
1704 | ||
1705 | static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth) | |
1706 | { | |
1707 | struct mtk_eth *eth = _eth; | |
1708 | ||
1709 | if (likely(napi_schedule_prep(ð->tx_napi))) { | |
1710 | __napi_schedule(ð->tx_napi); | |
1711 | mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); | |
1712 | } | |
1713 | ||
1714 | return IRQ_HANDLED; | |
1715 | } | |
1716 | ||
1717 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1718 | static void mtk_poll_controller(struct net_device *dev) | |
1719 | { | |
1720 | struct mtk_mac *mac = netdev_priv(dev); | |
1721 | struct mtk_eth *eth = mac->hw; | |
1722 | ||
1723 | mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); | |
1724 | mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); | |
1725 | mtk_handle_irq_rx(eth->irq[2], dev); | |
1726 | mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); | |
1727 | mtk_rx_irq_enable(eth, MTK_RX_DONE_INT); | |
1728 | } | |
1729 | #endif | |
1730 | ||
1731 | static int mtk_start_dma(struct mtk_eth *eth) | |
1732 | { | |
1733 | int err; | |
1734 | ||
1735 | err = mtk_dma_init(eth); | |
1736 | if (err) { | |
1737 | mtk_dma_free(eth); | |
1738 | return err; | |
1739 | } | |
1740 | ||
1741 | mtk_w32(eth, | |
1742 | MTK_TX_WB_DDONE | MTK_TX_DMA_EN | | |
1743 | MTK_DMA_SIZE_16DWORDS | MTK_NDP_CO_PRO, | |
1744 | MTK_QDMA_GLO_CFG); | |
1745 | ||
1746 | mtk_w32(eth, | |
1747 | MTK_RX_DMA_EN | MTK_RX_2B_OFFSET | | |
1748 | MTK_RX_BT_32DWORDS | MTK_MULTI_EN, | |
1749 | MTK_PDMA_GLO_CFG); | |
1750 | ||
1751 | return 0; | |
1752 | } | |
1753 | ||
1754 | static int mtk_open(struct net_device *dev) | |
1755 | { | |
1756 | struct mtk_mac *mac = netdev_priv(dev); | |
1757 | struct mtk_eth *eth = mac->hw; | |
1758 | ||
1759 | /* we run 2 netdevs on the same dma ring so we only bring it up once */ | |
1760 | if (!atomic_read(ð->dma_refcnt)) { | |
1761 | int err = mtk_start_dma(eth); | |
1762 | ||
1763 | if (err) | |
1764 | return err; | |
1765 | ||
1766 | napi_enable(ð->tx_napi); | |
1767 | napi_enable(ð->rx_napi); | |
1768 | mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); | |
1769 | mtk_rx_irq_enable(eth, MTK_RX_DONE_INT); | |
1770 | } | |
1771 | atomic_inc(ð->dma_refcnt); | |
1772 | ||
1773 | phy_start(dev->phydev); | |
1774 | netif_start_queue(dev); | |
1775 | ||
1776 | return 0; | |
1777 | } | |
1778 | ||
1779 | static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg) | |
1780 | { | |
1781 | u32 val; | |
1782 | int i; | |
1783 | ||
1784 | /* stop the dma engine */ | |
1785 | spin_lock_bh(ð->page_lock); | |
1786 | val = mtk_r32(eth, glo_cfg); | |
1787 | mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN), | |
1788 | glo_cfg); | |
1789 | spin_unlock_bh(ð->page_lock); | |
1790 | ||
1791 | /* wait for dma stop */ | |
1792 | for (i = 0; i < 10; i++) { | |
1793 | val = mtk_r32(eth, glo_cfg); | |
1794 | if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) { | |
1795 | msleep(20); | |
1796 | continue; | |
1797 | } | |
1798 | break; | |
1799 | } | |
1800 | } | |
1801 | ||
1802 | static int mtk_stop(struct net_device *dev) | |
1803 | { | |
1804 | struct mtk_mac *mac = netdev_priv(dev); | |
1805 | struct mtk_eth *eth = mac->hw; | |
1806 | ||
1807 | netif_tx_disable(dev); | |
1808 | phy_stop(dev->phydev); | |
1809 | ||
1810 | /* only shutdown DMA if this is the last user */ | |
1811 | if (!atomic_dec_and_test(ð->dma_refcnt)) | |
1812 | return 0; | |
1813 | ||
1814 | mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); | |
1815 | mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); | |
1816 | napi_disable(ð->tx_napi); | |
1817 | napi_disable(ð->rx_napi); | |
1818 | ||
1819 | mtk_stop_dma(eth, MTK_QDMA_GLO_CFG); | |
1820 | mtk_stop_dma(eth, MTK_PDMA_GLO_CFG); | |
1821 | ||
1822 | mtk_dma_free(eth); | |
1823 | ||
1824 | return 0; | |
1825 | } | |
1826 | ||
1827 | static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits) | |
1828 | { | |
1829 | regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, | |
1830 | reset_bits, | |
1831 | reset_bits); | |
1832 | ||
1833 | usleep_range(1000, 1100); | |
1834 | regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, | |
1835 | reset_bits, | |
1836 | ~reset_bits); | |
1837 | mdelay(10); | |
1838 | } | |
1839 | ||
1840 | static int mtk_hw_init(struct mtk_eth *eth) | |
1841 | { | |
1842 | int i, val; | |
1843 | ||
1844 | if (test_and_set_bit(MTK_HW_INIT, ð->state)) | |
1845 | return 0; | |
1846 | ||
1847 | pm_runtime_enable(eth->dev); | |
1848 | pm_runtime_get_sync(eth->dev); | |
1849 | ||
1850 | clk_prepare_enable(eth->clks[MTK_CLK_ETHIF]); | |
1851 | clk_prepare_enable(eth->clks[MTK_CLK_ESW]); | |
1852 | clk_prepare_enable(eth->clks[MTK_CLK_GP1]); | |
1853 | clk_prepare_enable(eth->clks[MTK_CLK_GP2]); | |
1854 | ethsys_reset(eth, RSTCTRL_FE); | |
1855 | ethsys_reset(eth, RSTCTRL_PPE); | |
1856 | ||
1857 | regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); | |
1858 | for (i = 0; i < MTK_MAC_COUNT; i++) { | |
1859 | if (!eth->mac[i]) | |
1860 | continue; | |
1861 | val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, eth->mac[i]->id); | |
1862 | val |= SYSCFG0_GE_MODE(eth->mac[i]->ge_mode, eth->mac[i]->id); | |
1863 | } | |
1864 | regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); | |
1865 | ||
1866 | /* Set GE2 driving and slew rate */ | |
1867 | regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00); | |
1868 | ||
1869 | /* set GE2 TDSEL */ | |
1870 | regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5); | |
1871 | ||
1872 | /* set GE2 TUNE */ | |
1873 | regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0); | |
1874 | ||
1875 | /* GE1, Force 1000M/FD, FC ON */ | |
1876 | mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(0)); | |
1877 | ||
1878 | /* GE2, Force 1000M/FD, FC ON */ | |
1879 | mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(1)); | |
1880 | ||
1881 | /* Indicates CDM to parse the MTK special tag from CPU | |
1882 | * which also is working out for untag packets. | |
1883 | */ | |
1884 | val = mtk_r32(eth, MTK_CDMQ_IG_CTRL); | |
1885 | mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL); | |
1886 | ||
1887 | /* Enable RX VLan Offloading */ | |
1888 | mtk_w32(eth, 1, MTK_CDMP_EG_CTRL); | |
1889 | ||
1890 | /* enable interrupt delay for RX */ | |
1891 | mtk_w32(eth, MTK_PDMA_DELAY_RX_DELAY, MTK_PDMA_DELAY_INT); | |
1892 | ||
1893 | /* disable delay and normal interrupt */ | |
1894 | mtk_w32(eth, 0, MTK_QDMA_DELAY_INT); | |
1895 | mtk_tx_irq_disable(eth, ~0); | |
1896 | mtk_rx_irq_disable(eth, ~0); | |
1897 | mtk_w32(eth, RST_GL_PSE, MTK_RST_GL); | |
1898 | mtk_w32(eth, 0, MTK_RST_GL); | |
1899 | ||
1900 | /* FE int grouping */ | |
1901 | mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1); | |
1902 | mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_GRP2); | |
1903 | mtk_w32(eth, MTK_TX_DONE_INT, MTK_QDMA_INT_GRP1); | |
1904 | mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2); | |
1905 | mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); | |
1906 | ||
1907 | for (i = 0; i < 2; i++) { | |
1908 | u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i)); | |
1909 | ||
1910 | /* setup the forward port to send frame to PDMA */ | |
1911 | val &= ~0xffff; | |
1912 | ||
1913 | /* Enable RX checksum */ | |
1914 | val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN; | |
1915 | ||
1916 | /* setup the mac dma */ | |
1917 | mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i)); | |
1918 | } | |
1919 | ||
1920 | return 0; | |
1921 | } | |
1922 | ||
1923 | static int mtk_hw_deinit(struct mtk_eth *eth) | |
1924 | { | |
1925 | if (!test_and_clear_bit(MTK_HW_INIT, ð->state)) | |
1926 | return 0; | |
1927 | ||
1928 | clk_disable_unprepare(eth->clks[MTK_CLK_GP2]); | |
1929 | clk_disable_unprepare(eth->clks[MTK_CLK_GP1]); | |
1930 | clk_disable_unprepare(eth->clks[MTK_CLK_ESW]); | |
1931 | clk_disable_unprepare(eth->clks[MTK_CLK_ETHIF]); | |
1932 | ||
1933 | pm_runtime_put_sync(eth->dev); | |
1934 | pm_runtime_disable(eth->dev); | |
1935 | ||
1936 | return 0; | |
1937 | } | |
1938 | ||
1939 | static int __init mtk_init(struct net_device *dev) | |
1940 | { | |
1941 | struct mtk_mac *mac = netdev_priv(dev); | |
1942 | struct mtk_eth *eth = mac->hw; | |
1943 | const char *mac_addr; | |
1944 | ||
1945 | mac_addr = of_get_mac_address(mac->of_node); | |
1946 | if (mac_addr) | |
1947 | ether_addr_copy(dev->dev_addr, mac_addr); | |
1948 | ||
1949 | /* If the mac address is invalid, use random mac address */ | |
1950 | if (!is_valid_ether_addr(dev->dev_addr)) { | |
1951 | eth_hw_addr_random(dev); | |
1952 | dev_err(eth->dev, "generated random MAC address %pM\n", | |
1953 | dev->dev_addr); | |
1954 | } | |
1955 | ||
1956 | return mtk_phy_connect(dev); | |
1957 | } | |
1958 | ||
1959 | static void mtk_uninit(struct net_device *dev) | |
1960 | { | |
1961 | struct mtk_mac *mac = netdev_priv(dev); | |
1962 | struct mtk_eth *eth = mac->hw; | |
1963 | ||
1964 | phy_disconnect(dev->phydev); | |
1965 | if (of_phy_is_fixed_link(mac->of_node)) | |
1966 | of_phy_deregister_fixed_link(mac->of_node); | |
1967 | mtk_tx_irq_disable(eth, ~0); | |
1968 | mtk_rx_irq_disable(eth, ~0); | |
1969 | } | |
1970 | ||
1971 | static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
1972 | { | |
1973 | switch (cmd) { | |
1974 | case SIOCGMIIPHY: | |
1975 | case SIOCGMIIREG: | |
1976 | case SIOCSMIIREG: | |
1977 | return phy_mii_ioctl(dev->phydev, ifr, cmd); | |
1978 | default: | |
1979 | break; | |
1980 | } | |
1981 | ||
1982 | return -EOPNOTSUPP; | |
1983 | } | |
1984 | ||
1985 | static void mtk_pending_work(struct work_struct *work) | |
1986 | { | |
1987 | struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work); | |
1988 | int err, i; | |
1989 | unsigned long restart = 0; | |
1990 | ||
1991 | rtnl_lock(); | |
1992 | ||
1993 | dev_dbg(eth->dev, "[%s][%d] reset\n", __func__, __LINE__); | |
1994 | ||
1995 | while (test_and_set_bit_lock(MTK_RESETTING, ð->state)) | |
1996 | cpu_relax(); | |
1997 | ||
1998 | dev_dbg(eth->dev, "[%s][%d] mtk_stop starts\n", __func__, __LINE__); | |
1999 | /* stop all devices to make sure that dma is properly shut down */ | |
2000 | for (i = 0; i < MTK_MAC_COUNT; i++) { | |
2001 | if (!eth->netdev[i]) | |
2002 | continue; | |
2003 | mtk_stop(eth->netdev[i]); | |
2004 | __set_bit(i, &restart); | |
2005 | } | |
2006 | dev_dbg(eth->dev, "[%s][%d] mtk_stop ends\n", __func__, __LINE__); | |
2007 | ||
2008 | /* restart underlying hardware such as power, clock, pin mux | |
2009 | * and the connected phy | |
2010 | */ | |
2011 | mtk_hw_deinit(eth); | |
2012 | ||
2013 | if (eth->dev->pins) | |
2014 | pinctrl_select_state(eth->dev->pins->p, | |
2015 | eth->dev->pins->default_state); | |
2016 | mtk_hw_init(eth); | |
2017 | ||
2018 | for (i = 0; i < MTK_MAC_COUNT; i++) { | |
2019 | if (!eth->mac[i] || | |
2020 | of_phy_is_fixed_link(eth->mac[i]->of_node)) | |
2021 | continue; | |
2022 | err = phy_init_hw(eth->netdev[i]->phydev); | |
2023 | if (err) | |
2024 | dev_err(eth->dev, "%s: PHY init failed.\n", | |
2025 | eth->netdev[i]->name); | |
2026 | } | |
2027 | ||
2028 | /* restart DMA and enable IRQs */ | |
2029 | for (i = 0; i < MTK_MAC_COUNT; i++) { | |
2030 | if (!test_bit(i, &restart)) | |
2031 | continue; | |
2032 | err = mtk_open(eth->netdev[i]); | |
2033 | if (err) { | |
2034 | netif_alert(eth, ifup, eth->netdev[i], | |
2035 | "Driver up/down cycle failed, closing device.\n"); | |
2036 | dev_close(eth->netdev[i]); | |
2037 | } | |
2038 | } | |
2039 | ||
2040 | dev_dbg(eth->dev, "[%s][%d] reset done\n", __func__, __LINE__); | |
2041 | ||
2042 | clear_bit_unlock(MTK_RESETTING, ð->state); | |
2043 | ||
2044 | rtnl_unlock(); | |
2045 | } | |
2046 | ||
2047 | static int mtk_free_dev(struct mtk_eth *eth) | |
2048 | { | |
2049 | int i; | |
2050 | ||
2051 | for (i = 0; i < MTK_MAC_COUNT; i++) { | |
2052 | if (!eth->netdev[i]) | |
2053 | continue; | |
2054 | free_netdev(eth->netdev[i]); | |
2055 | } | |
2056 | ||
2057 | return 0; | |
2058 | } | |
2059 | ||
2060 | static int mtk_unreg_dev(struct mtk_eth *eth) | |
2061 | { | |
2062 | int i; | |
2063 | ||
2064 | for (i = 0; i < MTK_MAC_COUNT; i++) { | |
2065 | if (!eth->netdev[i]) | |
2066 | continue; | |
2067 | unregister_netdev(eth->netdev[i]); | |
2068 | } | |
2069 | ||
2070 | return 0; | |
2071 | } | |
2072 | ||
2073 | static int mtk_cleanup(struct mtk_eth *eth) | |
2074 | { | |
2075 | mtk_unreg_dev(eth); | |
2076 | mtk_free_dev(eth); | |
2077 | cancel_work_sync(ð->pending_work); | |
2078 | ||
2079 | return 0; | |
2080 | } | |
2081 | ||
2082 | static int mtk_get_link_ksettings(struct net_device *ndev, | |
2083 | struct ethtool_link_ksettings *cmd) | |
2084 | { | |
2085 | struct mtk_mac *mac = netdev_priv(ndev); | |
2086 | ||
2087 | if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) | |
2088 | return -EBUSY; | |
2089 | ||
2090 | phy_ethtool_ksettings_get(ndev->phydev, cmd); | |
2091 | ||
2092 | return 0; | |
2093 | } | |
2094 | ||
2095 | static int mtk_set_link_ksettings(struct net_device *ndev, | |
2096 | const struct ethtool_link_ksettings *cmd) | |
2097 | { | |
2098 | struct mtk_mac *mac = netdev_priv(ndev); | |
2099 | ||
2100 | if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) | |
2101 | return -EBUSY; | |
2102 | ||
2103 | return phy_ethtool_ksettings_set(ndev->phydev, cmd); | |
2104 | } | |
2105 | ||
2106 | static void mtk_get_drvinfo(struct net_device *dev, | |
2107 | struct ethtool_drvinfo *info) | |
2108 | { | |
2109 | struct mtk_mac *mac = netdev_priv(dev); | |
2110 | ||
2111 | strlcpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver)); | |
2112 | strlcpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info)); | |
2113 | info->n_stats = ARRAY_SIZE(mtk_ethtool_stats); | |
2114 | } | |
2115 | ||
2116 | static u32 mtk_get_msglevel(struct net_device *dev) | |
2117 | { | |
2118 | struct mtk_mac *mac = netdev_priv(dev); | |
2119 | ||
2120 | return mac->hw->msg_enable; | |
2121 | } | |
2122 | ||
2123 | static void mtk_set_msglevel(struct net_device *dev, u32 value) | |
2124 | { | |
2125 | struct mtk_mac *mac = netdev_priv(dev); | |
2126 | ||
2127 | mac->hw->msg_enable = value; | |
2128 | } | |
2129 | ||
2130 | static int mtk_nway_reset(struct net_device *dev) | |
2131 | { | |
2132 | struct mtk_mac *mac = netdev_priv(dev); | |
2133 | ||
2134 | if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) | |
2135 | return -EBUSY; | |
2136 | ||
2137 | return genphy_restart_aneg(dev->phydev); | |
2138 | } | |
2139 | ||
2140 | static u32 mtk_get_link(struct net_device *dev) | |
2141 | { | |
2142 | struct mtk_mac *mac = netdev_priv(dev); | |
2143 | int err; | |
2144 | ||
2145 | if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) | |
2146 | return -EBUSY; | |
2147 | ||
2148 | err = genphy_update_link(dev->phydev); | |
2149 | if (err) | |
2150 | return ethtool_op_get_link(dev); | |
2151 | ||
2152 | return dev->phydev->link; | |
2153 | } | |
2154 | ||
2155 | static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data) | |
2156 | { | |
2157 | int i; | |
2158 | ||
2159 | switch (stringset) { | |
2160 | case ETH_SS_STATS: | |
2161 | for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) { | |
2162 | memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN); | |
2163 | data += ETH_GSTRING_LEN; | |
2164 | } | |
2165 | break; | |
2166 | } | |
2167 | } | |
2168 | ||
2169 | static int mtk_get_sset_count(struct net_device *dev, int sset) | |
2170 | { | |
2171 | switch (sset) { | |
2172 | case ETH_SS_STATS: | |
2173 | return ARRAY_SIZE(mtk_ethtool_stats); | |
2174 | default: | |
2175 | return -EOPNOTSUPP; | |
2176 | } | |
2177 | } | |
2178 | ||
2179 | static void mtk_get_ethtool_stats(struct net_device *dev, | |
2180 | struct ethtool_stats *stats, u64 *data) | |
2181 | { | |
2182 | struct mtk_mac *mac = netdev_priv(dev); | |
2183 | struct mtk_hw_stats *hwstats = mac->hw_stats; | |
2184 | u64 *data_src, *data_dst; | |
2185 | unsigned int start; | |
2186 | int i; | |
2187 | ||
2188 | if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) | |
2189 | return; | |
2190 | ||
2191 | if (netif_running(dev) && netif_device_present(dev)) { | |
2192 | if (spin_trylock_bh(&hwstats->stats_lock)) { | |
2193 | mtk_stats_update_mac(mac); | |
2194 | spin_unlock_bh(&hwstats->stats_lock); | |
2195 | } | |
2196 | } | |
2197 | ||
2198 | data_src = (u64 *)hwstats; | |
2199 | ||
2200 | do { | |
2201 | data_dst = data; | |
2202 | start = u64_stats_fetch_begin_irq(&hwstats->syncp); | |
2203 | ||
2204 | for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) | |
2205 | *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset); | |
2206 | } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start)); | |
2207 | } | |
2208 | ||
2209 | static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, | |
2210 | u32 *rule_locs) | |
2211 | { | |
2212 | int ret = -EOPNOTSUPP; | |
2213 | ||
2214 | switch (cmd->cmd) { | |
2215 | case ETHTOOL_GRXRINGS: | |
2216 | if (dev->features & NETIF_F_LRO) { | |
2217 | cmd->data = MTK_MAX_RX_RING_NUM; | |
2218 | ret = 0; | |
2219 | } | |
2220 | break; | |
2221 | case ETHTOOL_GRXCLSRLCNT: | |
2222 | if (dev->features & NETIF_F_LRO) { | |
2223 | struct mtk_mac *mac = netdev_priv(dev); | |
2224 | ||
2225 | cmd->rule_cnt = mac->hwlro_ip_cnt; | |
2226 | ret = 0; | |
2227 | } | |
2228 | break; | |
2229 | case ETHTOOL_GRXCLSRULE: | |
2230 | if (dev->features & NETIF_F_LRO) | |
2231 | ret = mtk_hwlro_get_fdir_entry(dev, cmd); | |
2232 | break; | |
2233 | case ETHTOOL_GRXCLSRLALL: | |
2234 | if (dev->features & NETIF_F_LRO) | |
2235 | ret = mtk_hwlro_get_fdir_all(dev, cmd, | |
2236 | rule_locs); | |
2237 | break; | |
2238 | default: | |
2239 | break; | |
2240 | } | |
2241 | ||
2242 | return ret; | |
2243 | } | |
2244 | ||
2245 | static int mtk_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) | |
2246 | { | |
2247 | int ret = -EOPNOTSUPP; | |
2248 | ||
2249 | switch (cmd->cmd) { | |
2250 | case ETHTOOL_SRXCLSRLINS: | |
2251 | if (dev->features & NETIF_F_LRO) | |
2252 | ret = mtk_hwlro_add_ipaddr(dev, cmd); | |
2253 | break; | |
2254 | case ETHTOOL_SRXCLSRLDEL: | |
2255 | if (dev->features & NETIF_F_LRO) | |
2256 | ret = mtk_hwlro_del_ipaddr(dev, cmd); | |
2257 | break; | |
2258 | default: | |
2259 | break; | |
2260 | } | |
2261 | ||
2262 | return ret; | |
2263 | } | |
2264 | ||
2265 | static const struct ethtool_ops mtk_ethtool_ops = { | |
2266 | .get_link_ksettings = mtk_get_link_ksettings, | |
2267 | .set_link_ksettings = mtk_set_link_ksettings, | |
2268 | .get_drvinfo = mtk_get_drvinfo, | |
2269 | .get_msglevel = mtk_get_msglevel, | |
2270 | .set_msglevel = mtk_set_msglevel, | |
2271 | .nway_reset = mtk_nway_reset, | |
2272 | .get_link = mtk_get_link, | |
2273 | .get_strings = mtk_get_strings, | |
2274 | .get_sset_count = mtk_get_sset_count, | |
2275 | .get_ethtool_stats = mtk_get_ethtool_stats, | |
2276 | .get_rxnfc = mtk_get_rxnfc, | |
2277 | .set_rxnfc = mtk_set_rxnfc, | |
2278 | }; | |
2279 | ||
2280 | static const struct net_device_ops mtk_netdev_ops = { | |
2281 | .ndo_init = mtk_init, | |
2282 | .ndo_uninit = mtk_uninit, | |
2283 | .ndo_open = mtk_open, | |
2284 | .ndo_stop = mtk_stop, | |
2285 | .ndo_start_xmit = mtk_start_xmit, | |
2286 | .ndo_set_mac_address = mtk_set_mac_address, | |
2287 | .ndo_validate_addr = eth_validate_addr, | |
2288 | .ndo_do_ioctl = mtk_do_ioctl, | |
2289 | .ndo_tx_timeout = mtk_tx_timeout, | |
2290 | .ndo_get_stats64 = mtk_get_stats64, | |
2291 | .ndo_fix_features = mtk_fix_features, | |
2292 | .ndo_set_features = mtk_set_features, | |
2293 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
2294 | .ndo_poll_controller = mtk_poll_controller, | |
2295 | #endif | |
2296 | }; | |
2297 | ||
2298 | static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np) | |
2299 | { | |
2300 | struct mtk_mac *mac; | |
2301 | const __be32 *_id = of_get_property(np, "reg", NULL); | |
2302 | int id, err; | |
2303 | ||
2304 | if (!_id) { | |
2305 | dev_err(eth->dev, "missing mac id\n"); | |
2306 | return -EINVAL; | |
2307 | } | |
2308 | ||
2309 | id = be32_to_cpup(_id); | |
2310 | if (id >= MTK_MAC_COUNT) { | |
2311 | dev_err(eth->dev, "%d is not a valid mac id\n", id); | |
2312 | return -EINVAL; | |
2313 | } | |
2314 | ||
2315 | if (eth->netdev[id]) { | |
2316 | dev_err(eth->dev, "duplicate mac id found: %d\n", id); | |
2317 | return -EINVAL; | |
2318 | } | |
2319 | ||
2320 | eth->netdev[id] = alloc_etherdev(sizeof(*mac)); | |
2321 | if (!eth->netdev[id]) { | |
2322 | dev_err(eth->dev, "alloc_etherdev failed\n"); | |
2323 | return -ENOMEM; | |
2324 | } | |
2325 | mac = netdev_priv(eth->netdev[id]); | |
2326 | eth->mac[id] = mac; | |
2327 | mac->id = id; | |
2328 | mac->hw = eth; | |
2329 | mac->of_node = np; | |
2330 | ||
2331 | memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip)); | |
2332 | mac->hwlro_ip_cnt = 0; | |
2333 | ||
2334 | mac->hw_stats = devm_kzalloc(eth->dev, | |
2335 | sizeof(*mac->hw_stats), | |
2336 | GFP_KERNEL); | |
2337 | if (!mac->hw_stats) { | |
2338 | dev_err(eth->dev, "failed to allocate counter memory\n"); | |
2339 | err = -ENOMEM; | |
2340 | goto free_netdev; | |
2341 | } | |
2342 | spin_lock_init(&mac->hw_stats->stats_lock); | |
2343 | u64_stats_init(&mac->hw_stats->syncp); | |
2344 | mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET; | |
2345 | ||
2346 | SET_NETDEV_DEV(eth->netdev[id], eth->dev); | |
2347 | eth->netdev[id]->watchdog_timeo = 5 * HZ; | |
2348 | eth->netdev[id]->netdev_ops = &mtk_netdev_ops; | |
2349 | eth->netdev[id]->base_addr = (unsigned long)eth->base; | |
2350 | ||
2351 | eth->netdev[id]->hw_features = MTK_HW_FEATURES; | |
2352 | if (eth->hwlro) | |
2353 | eth->netdev[id]->hw_features |= NETIF_F_LRO; | |
2354 | ||
2355 | eth->netdev[id]->vlan_features = MTK_HW_FEATURES & | |
2356 | ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX); | |
2357 | eth->netdev[id]->features |= MTK_HW_FEATURES; | |
2358 | eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops; | |
2359 | ||
2360 | eth->netdev[id]->irq = eth->irq[0]; | |
2361 | eth->netdev[id]->dev.of_node = np; | |
2362 | ||
2363 | return 0; | |
2364 | ||
2365 | free_netdev: | |
2366 | free_netdev(eth->netdev[id]); | |
2367 | return err; | |
2368 | } | |
2369 | ||
2370 | static int mtk_get_chip_id(struct mtk_eth *eth, u32 *chip_id) | |
2371 | { | |
2372 | u32 val[2], id[4]; | |
2373 | ||
2374 | regmap_read(eth->ethsys, ETHSYS_CHIPID0_3, &val[0]); | |
2375 | regmap_read(eth->ethsys, ETHSYS_CHIPID4_7, &val[1]); | |
2376 | ||
2377 | id[3] = ((val[0] >> 16) & 0xff) - '0'; | |
2378 | id[2] = ((val[0] >> 24) & 0xff) - '0'; | |
2379 | id[1] = (val[1] & 0xff) - '0'; | |
2380 | id[0] = ((val[1] >> 8) & 0xff) - '0'; | |
2381 | ||
2382 | *chip_id = (id[3] * 1000) + (id[2] * 100) + | |
2383 | (id[1] * 10) + id[0]; | |
2384 | ||
2385 | if (!(*chip_id)) { | |
2386 | dev_err(eth->dev, "failed to get chip id\n"); | |
2387 | return -ENODEV; | |
2388 | } | |
2389 | ||
2390 | dev_info(eth->dev, "chip id = %d\n", *chip_id); | |
2391 | ||
2392 | return 0; | |
2393 | } | |
2394 | ||
2395 | static bool mtk_is_hwlro_supported(struct mtk_eth *eth) | |
2396 | { | |
2397 | switch (eth->chip_id) { | |
2398 | case MT7623_ETH: | |
2399 | return true; | |
2400 | } | |
2401 | ||
2402 | return false; | |
2403 | } | |
2404 | ||
2405 | static int mtk_probe(struct platform_device *pdev) | |
2406 | { | |
2407 | struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
2408 | struct device_node *mac_np; | |
2409 | struct mtk_eth *eth; | |
2410 | int err; | |
2411 | int i; | |
2412 | ||
2413 | eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL); | |
2414 | if (!eth) | |
2415 | return -ENOMEM; | |
2416 | ||
2417 | eth->dev = &pdev->dev; | |
2418 | eth->base = devm_ioremap_resource(&pdev->dev, res); | |
2419 | if (IS_ERR(eth->base)) | |
2420 | return PTR_ERR(eth->base); | |
2421 | ||
2422 | spin_lock_init(ð->page_lock); | |
2423 | spin_lock_init(ð->tx_irq_lock); | |
2424 | spin_lock_init(ð->rx_irq_lock); | |
2425 | ||
2426 | eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, | |
2427 | "mediatek,ethsys"); | |
2428 | if (IS_ERR(eth->ethsys)) { | |
2429 | dev_err(&pdev->dev, "no ethsys regmap found\n"); | |
2430 | return PTR_ERR(eth->ethsys); | |
2431 | } | |
2432 | ||
2433 | eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, | |
2434 | "mediatek,pctl"); | |
2435 | if (IS_ERR(eth->pctl)) { | |
2436 | dev_err(&pdev->dev, "no pctl regmap found\n"); | |
2437 | return PTR_ERR(eth->pctl); | |
2438 | } | |
2439 | ||
2440 | for (i = 0; i < 3; i++) { | |
2441 | eth->irq[i] = platform_get_irq(pdev, i); | |
2442 | if (eth->irq[i] < 0) { | |
2443 | dev_err(&pdev->dev, "no IRQ%d resource found\n", i); | |
2444 | return -ENXIO; | |
2445 | } | |
2446 | } | |
2447 | for (i = 0; i < ARRAY_SIZE(eth->clks); i++) { | |
2448 | eth->clks[i] = devm_clk_get(eth->dev, | |
2449 | mtk_clks_source_name[i]); | |
2450 | if (IS_ERR(eth->clks[i])) { | |
2451 | if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER) | |
2452 | return -EPROBE_DEFER; | |
2453 | return -ENODEV; | |
2454 | } | |
2455 | } | |
2456 | ||
2457 | eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE); | |
2458 | INIT_WORK(ð->pending_work, mtk_pending_work); | |
2459 | ||
2460 | err = mtk_hw_init(eth); | |
2461 | if (err) | |
2462 | return err; | |
2463 | ||
2464 | err = mtk_get_chip_id(eth, ð->chip_id); | |
2465 | if (err) | |
2466 | return err; | |
2467 | ||
2468 | eth->hwlro = mtk_is_hwlro_supported(eth); | |
2469 | ||
2470 | for_each_child_of_node(pdev->dev.of_node, mac_np) { | |
2471 | if (!of_device_is_compatible(mac_np, | |
2472 | "mediatek,eth-mac")) | |
2473 | continue; | |
2474 | ||
2475 | if (!of_device_is_available(mac_np)) | |
2476 | continue; | |
2477 | ||
2478 | err = mtk_add_mac(eth, mac_np); | |
2479 | if (err) | |
2480 | goto err_deinit_hw; | |
2481 | } | |
2482 | ||
2483 | err = devm_request_irq(eth->dev, eth->irq[1], mtk_handle_irq_tx, 0, | |
2484 | dev_name(eth->dev), eth); | |
2485 | if (err) | |
2486 | goto err_free_dev; | |
2487 | ||
2488 | err = devm_request_irq(eth->dev, eth->irq[2], mtk_handle_irq_rx, 0, | |
2489 | dev_name(eth->dev), eth); | |
2490 | if (err) | |
2491 | goto err_free_dev; | |
2492 | ||
2493 | err = mtk_mdio_init(eth); | |
2494 | if (err) | |
2495 | goto err_free_dev; | |
2496 | ||
2497 | for (i = 0; i < MTK_MAX_DEVS; i++) { | |
2498 | if (!eth->netdev[i]) | |
2499 | continue; | |
2500 | ||
2501 | err = register_netdev(eth->netdev[i]); | |
2502 | if (err) { | |
2503 | dev_err(eth->dev, "error bringing up device\n"); | |
2504 | goto err_deinit_mdio; | |
2505 | } else | |
2506 | netif_info(eth, probe, eth->netdev[i], | |
2507 | "mediatek frame engine at 0x%08lx, irq %d\n", | |
2508 | eth->netdev[i]->base_addr, eth->irq[0]); | |
2509 | } | |
2510 | ||
2511 | /* we run 2 devices on the same DMA ring so we need a dummy device | |
2512 | * for NAPI to work | |
2513 | */ | |
2514 | init_dummy_netdev(ð->dummy_dev); | |
2515 | netif_napi_add(ð->dummy_dev, ð->tx_napi, mtk_napi_tx, | |
2516 | MTK_NAPI_WEIGHT); | |
2517 | netif_napi_add(ð->dummy_dev, ð->rx_napi, mtk_napi_rx, | |
2518 | MTK_NAPI_WEIGHT); | |
2519 | ||
2520 | platform_set_drvdata(pdev, eth); | |
2521 | ||
2522 | return 0; | |
2523 | ||
2524 | err_deinit_mdio: | |
2525 | mtk_mdio_cleanup(eth); | |
2526 | err_free_dev: | |
2527 | mtk_free_dev(eth); | |
2528 | err_deinit_hw: | |
2529 | mtk_hw_deinit(eth); | |
2530 | ||
2531 | return err; | |
2532 | } | |
2533 | ||
2534 | static int mtk_remove(struct platform_device *pdev) | |
2535 | { | |
2536 | struct mtk_eth *eth = platform_get_drvdata(pdev); | |
2537 | int i; | |
2538 | ||
2539 | /* stop all devices to make sure that dma is properly shut down */ | |
2540 | for (i = 0; i < MTK_MAC_COUNT; i++) { | |
2541 | if (!eth->netdev[i]) | |
2542 | continue; | |
2543 | mtk_stop(eth->netdev[i]); | |
2544 | } | |
2545 | ||
2546 | mtk_hw_deinit(eth); | |
2547 | ||
2548 | netif_napi_del(ð->tx_napi); | |
2549 | netif_napi_del(ð->rx_napi); | |
2550 | mtk_cleanup(eth); | |
2551 | mtk_mdio_cleanup(eth); | |
2552 | ||
2553 | return 0; | |
2554 | } | |
2555 | ||
2556 | const struct of_device_id of_mtk_match[] = { | |
2557 | { .compatible = "mediatek,mt2701-eth" }, | |
2558 | {}, | |
2559 | }; | |
2560 | MODULE_DEVICE_TABLE(of, of_mtk_match); | |
2561 | ||
2562 | static struct platform_driver mtk_driver = { | |
2563 | .probe = mtk_probe, | |
2564 | .remove = mtk_remove, | |
2565 | .driver = { | |
2566 | .name = "mtk_soc_eth", | |
2567 | .of_match_table = of_mtk_match, | |
2568 | }, | |
2569 | }; | |
2570 | ||
2571 | module_platform_driver(mtk_driver); | |
2572 | ||
2573 | MODULE_LICENSE("GPL"); | |
2574 | MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); | |
2575 | MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC"); |