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net/mlx5e: Protect neigh hash encap list with spinlock and rcu
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_tc.c
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1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <net/flow_dissector.h>
34#include <net/sch_generic.h>
35#include <net/pkt_cls.h>
36#include <net/tc_act/tc_gact.h>
37#include <net/tc_act/tc_skbedit.h>
38#include <linux/mlx5/fs.h>
39#include <linux/mlx5/device.h>
40#include <linux/rhashtable.h>
41#include <linux/refcount.h>
42#include <linux/completion.h>
43#include <net/tc_act/tc_mirred.h>
44#include <net/tc_act/tc_vlan.h>
45#include <net/tc_act/tc_tunnel_key.h>
46#include <net/tc_act/tc_pedit.h>
47#include <net/tc_act/tc_csum.h>
48#include <net/arp.h>
49#include <net/ipv6_stubs.h>
50#include "en.h"
51#include "en_rep.h"
52#include "en_tc.h"
53#include "eswitch.h"
54#include "fs_core.h"
55#include "en/port.h"
56#include "en/tc_tun.h"
57#include "lib/devcom.h"
58#include "lib/geneve.h"
59
60struct mlx5_nic_flow_attr {
61 u32 action;
62 u32 flow_tag;
63 u32 mod_hdr_id;
64 u32 hairpin_tirn;
65 u8 match_level;
66 struct mlx5_flow_table *hairpin_ft;
67 struct mlx5_fc *counter;
68};
69
70#define MLX5E_TC_FLOW_BASE (MLX5E_TC_FLAG_LAST_EXPORTED_BIT + 1)
71
72enum {
73 MLX5E_TC_FLOW_FLAG_INGRESS = MLX5E_TC_FLAG_INGRESS_BIT,
74 MLX5E_TC_FLOW_FLAG_EGRESS = MLX5E_TC_FLAG_EGRESS_BIT,
75 MLX5E_TC_FLOW_FLAG_ESWITCH = MLX5E_TC_FLAG_ESW_OFFLOAD_BIT,
76 MLX5E_TC_FLOW_FLAG_NIC = MLX5E_TC_FLAG_NIC_OFFLOAD_BIT,
77 MLX5E_TC_FLOW_FLAG_OFFLOADED = MLX5E_TC_FLOW_BASE,
78 MLX5E_TC_FLOW_FLAG_HAIRPIN = MLX5E_TC_FLOW_BASE + 1,
79 MLX5E_TC_FLOW_FLAG_HAIRPIN_RSS = MLX5E_TC_FLOW_BASE + 2,
80 MLX5E_TC_FLOW_FLAG_SLOW = MLX5E_TC_FLOW_BASE + 3,
81 MLX5E_TC_FLOW_FLAG_DUP = MLX5E_TC_FLOW_BASE + 4,
82 MLX5E_TC_FLOW_FLAG_NOT_READY = MLX5E_TC_FLOW_BASE + 5,
83 MLX5E_TC_FLOW_FLAG_DELETED = MLX5E_TC_FLOW_BASE + 6,
84};
85
86#define MLX5E_TC_MAX_SPLITS 1
87
88/* Helper struct for accessing a struct containing list_head array.
89 * Containing struct
90 * |- Helper array
91 * [0] Helper item 0
92 * |- list_head item 0
93 * |- index (0)
94 * [1] Helper item 1
95 * |- list_head item 1
96 * |- index (1)
97 * To access the containing struct from one of the list_head items:
98 * 1. Get the helper item from the list_head item using
99 * helper item =
100 * container_of(list_head item, helper struct type, list_head field)
101 * 2. Get the contining struct from the helper item and its index in the array:
102 * containing struct =
103 * container_of(helper item, containing struct type, helper field[index])
104 */
105struct encap_flow_item {
106 struct mlx5e_encap_entry *e; /* attached encap instance */
107 struct list_head list;
108 int index;
109};
110
111struct mlx5e_tc_flow {
112 struct rhash_head node;
113 struct mlx5e_priv *priv;
114 u64 cookie;
115 unsigned long flags;
116 struct mlx5_flow_handle *rule[MLX5E_TC_MAX_SPLITS + 1];
117 /* Flow can be associated with multiple encap IDs.
118 * The number of encaps is bounded by the number of supported
119 * destinations.
120 */
121 struct encap_flow_item encaps[MLX5_MAX_FLOW_FWD_VPORTS];
122 struct mlx5e_tc_flow *peer_flow;
123 struct mlx5e_mod_hdr_entry *mh; /* attached mod header instance */
124 struct list_head mod_hdr; /* flows sharing the same mod hdr ID */
125 struct mlx5e_hairpin_entry *hpe; /* attached hairpin instance */
126 struct list_head hairpin; /* flows sharing the same hairpin */
127 struct list_head peer; /* flows with peer flow */
128 struct list_head unready; /* flows not ready to be offloaded (e.g due to missing route) */
129 refcount_t refcnt;
130 struct rcu_head rcu_head;
131 union {
132 struct mlx5_esw_flow_attr esw_attr[0];
133 struct mlx5_nic_flow_attr nic_attr[0];
134 };
135};
136
137struct mlx5e_tc_flow_parse_attr {
138 const struct ip_tunnel_info *tun_info[MLX5_MAX_FLOW_FWD_VPORTS];
139 struct net_device *filter_dev;
140 struct mlx5_flow_spec spec;
141 int num_mod_hdr_actions;
142 int max_mod_hdr_actions;
143 void *mod_hdr_actions;
144 int mirred_ifindex[MLX5_MAX_FLOW_FWD_VPORTS];
145};
146
147#define MLX5E_TC_TABLE_NUM_GROUPS 4
148#define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(16)
149
150struct mlx5e_hairpin {
151 struct mlx5_hairpin *pair;
152
153 struct mlx5_core_dev *func_mdev;
154 struct mlx5e_priv *func_priv;
155 u32 tdn;
156 u32 tirn;
157
158 int num_channels;
159 struct mlx5e_rqt indir_rqt;
160 u32 indir_tirn[MLX5E_NUM_INDIR_TIRS];
161 struct mlx5e_ttc_table ttc;
162};
163
164struct mlx5e_hairpin_entry {
165 /* a node of a hash table which keeps all the hairpin entries */
166 struct hlist_node hairpin_hlist;
167
168 /* protects flows list */
169 spinlock_t flows_lock;
170 /* flows sharing the same hairpin */
171 struct list_head flows;
172 /* hpe's that were not fully initialized when dead peer update event
173 * function traversed them.
174 */
175 struct list_head dead_peer_wait_list;
176
177 u16 peer_vhca_id;
178 u8 prio;
179 struct mlx5e_hairpin *hp;
180 refcount_t refcnt;
181 struct completion res_ready;
182};
183
184struct mod_hdr_key {
185 int num_actions;
186 void *actions;
187};
188
189struct mlx5e_mod_hdr_entry {
190 /* a node of a hash table which keeps all the mod_hdr entries */
191 struct hlist_node mod_hdr_hlist;
192
193 /* protects flows list */
194 spinlock_t flows_lock;
195 /* flows sharing the same mod_hdr entry */
196 struct list_head flows;
197
198 struct mod_hdr_key key;
199
200 u32 mod_hdr_id;
201
202 refcount_t refcnt;
203 struct completion res_ready;
204 int compl_result;
205};
206
207#define MLX5_MH_ACT_SZ MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto)
208
209static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
210 struct mlx5e_tc_flow *flow);
211
212static struct mlx5e_tc_flow *mlx5e_flow_get(struct mlx5e_tc_flow *flow)
213{
214 if (!flow || !refcount_inc_not_zero(&flow->refcnt))
215 return ERR_PTR(-EINVAL);
216 return flow;
217}
218
219static void mlx5e_flow_put(struct mlx5e_priv *priv,
220 struct mlx5e_tc_flow *flow)
221{
222 if (refcount_dec_and_test(&flow->refcnt)) {
223 mlx5e_tc_del_flow(priv, flow);
224 kfree_rcu(flow, rcu_head);
225 }
226}
227
228static void __flow_flag_set(struct mlx5e_tc_flow *flow, unsigned long flag)
229{
230 /* Complete all memory stores before setting bit. */
231 smp_mb__before_atomic();
232 set_bit(flag, &flow->flags);
233}
234
235#define flow_flag_set(flow, flag) __flow_flag_set(flow, MLX5E_TC_FLOW_FLAG_##flag)
236
237static bool __flow_flag_test_and_set(struct mlx5e_tc_flow *flow,
238 unsigned long flag)
239{
240 /* test_and_set_bit() provides all necessary barriers */
241 return test_and_set_bit(flag, &flow->flags);
242}
243
244#define flow_flag_test_and_set(flow, flag) \
245 __flow_flag_test_and_set(flow, \
246 MLX5E_TC_FLOW_FLAG_##flag)
247
248static void __flow_flag_clear(struct mlx5e_tc_flow *flow, unsigned long flag)
249{
250 /* Complete all memory stores before clearing bit. */
251 smp_mb__before_atomic();
252 clear_bit(flag, &flow->flags);
253}
254
255#define flow_flag_clear(flow, flag) __flow_flag_clear(flow, \
256 MLX5E_TC_FLOW_FLAG_##flag)
257
258static bool __flow_flag_test(struct mlx5e_tc_flow *flow, unsigned long flag)
259{
260 bool ret = test_bit(flag, &flow->flags);
261
262 /* Read fields of flow structure only after checking flags. */
263 smp_mb__after_atomic();
264 return ret;
265}
266
267#define flow_flag_test(flow, flag) __flow_flag_test(flow, \
268 MLX5E_TC_FLOW_FLAG_##flag)
269
270static bool mlx5e_is_eswitch_flow(struct mlx5e_tc_flow *flow)
271{
272 return flow_flag_test(flow, ESWITCH);
273}
274
275static bool mlx5e_is_offloaded_flow(struct mlx5e_tc_flow *flow)
276{
277 return flow_flag_test(flow, OFFLOADED);
278}
279
280static inline u32 hash_mod_hdr_info(struct mod_hdr_key *key)
281{
282 return jhash(key->actions,
283 key->num_actions * MLX5_MH_ACT_SZ, 0);
284}
285
286static inline int cmp_mod_hdr_info(struct mod_hdr_key *a,
287 struct mod_hdr_key *b)
288{
289 if (a->num_actions != b->num_actions)
290 return 1;
291
292 return memcmp(a->actions, b->actions, a->num_actions * MLX5_MH_ACT_SZ);
293}
294
295static struct mod_hdr_tbl *
296get_mod_hdr_table(struct mlx5e_priv *priv, int namespace)
297{
298 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
299
300 return namespace == MLX5_FLOW_NAMESPACE_FDB ? &esw->offloads.mod_hdr :
301 &priv->fs.tc.mod_hdr;
302}
303
304static struct mlx5e_mod_hdr_entry *
305mlx5e_mod_hdr_get(struct mod_hdr_tbl *tbl, struct mod_hdr_key *key, u32 hash_key)
306{
307 struct mlx5e_mod_hdr_entry *mh, *found = NULL;
308
309 hash_for_each_possible(tbl->hlist, mh, mod_hdr_hlist, hash_key) {
310 if (!cmp_mod_hdr_info(&mh->key, key)) {
311 refcount_inc(&mh->refcnt);
312 found = mh;
313 break;
314 }
315 }
316
317 return found;
318}
319
320static void mlx5e_mod_hdr_put(struct mlx5e_priv *priv,
321 struct mlx5e_mod_hdr_entry *mh,
322 int namespace)
323{
324 struct mod_hdr_tbl *tbl = get_mod_hdr_table(priv, namespace);
325
326 if (!refcount_dec_and_mutex_lock(&mh->refcnt, &tbl->lock))
327 return;
328 hash_del(&mh->mod_hdr_hlist);
329 mutex_unlock(&tbl->lock);
330
331 WARN_ON(!list_empty(&mh->flows));
332 if (mh->compl_result > 0)
333 mlx5_modify_header_dealloc(priv->mdev, mh->mod_hdr_id);
334
335 kfree(mh);
336}
337
338static int get_flow_name_space(struct mlx5e_tc_flow *flow)
339{
340 return mlx5e_is_eswitch_flow(flow) ?
341 MLX5_FLOW_NAMESPACE_FDB : MLX5_FLOW_NAMESPACE_KERNEL;
342}
343static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv,
344 struct mlx5e_tc_flow *flow,
345 struct mlx5e_tc_flow_parse_attr *parse_attr)
346{
347 int num_actions, actions_size, namespace, err;
348 struct mlx5e_mod_hdr_entry *mh;
349 struct mod_hdr_tbl *tbl;
350 struct mod_hdr_key key;
351 u32 hash_key;
352
353 num_actions = parse_attr->num_mod_hdr_actions;
354 actions_size = MLX5_MH_ACT_SZ * num_actions;
355
356 key.actions = parse_attr->mod_hdr_actions;
357 key.num_actions = num_actions;
358
359 hash_key = hash_mod_hdr_info(&key);
360
361 namespace = get_flow_name_space(flow);
362 tbl = get_mod_hdr_table(priv, namespace);
363
364 mutex_lock(&tbl->lock);
365 mh = mlx5e_mod_hdr_get(tbl, &key, hash_key);
366 if (mh) {
367 mutex_unlock(&tbl->lock);
368 wait_for_completion(&mh->res_ready);
369
370 if (mh->compl_result < 0) {
371 err = -EREMOTEIO;
372 goto attach_header_err;
373 }
374 goto attach_flow;
375 }
376
377 mh = kzalloc(sizeof(*mh) + actions_size, GFP_KERNEL);
378 if (!mh) {
379 mutex_unlock(&tbl->lock);
380 return -ENOMEM;
381 }
382
383 mh->key.actions = (void *)mh + sizeof(*mh);
384 memcpy(mh->key.actions, key.actions, actions_size);
385 mh->key.num_actions = num_actions;
386 spin_lock_init(&mh->flows_lock);
387 INIT_LIST_HEAD(&mh->flows);
388 refcount_set(&mh->refcnt, 1);
389 init_completion(&mh->res_ready);
390
391 hash_add(tbl->hlist, &mh->mod_hdr_hlist, hash_key);
392 mutex_unlock(&tbl->lock);
393
394 err = mlx5_modify_header_alloc(priv->mdev, namespace,
395 mh->key.num_actions,
396 mh->key.actions,
397 &mh->mod_hdr_id);
398 if (err) {
399 mh->compl_result = err;
400 goto alloc_header_err;
401 }
402 mh->compl_result = 1;
403 complete_all(&mh->res_ready);
404
405attach_flow:
406 flow->mh = mh;
407 spin_lock(&mh->flows_lock);
408 list_add(&flow->mod_hdr, &mh->flows);
409 spin_unlock(&mh->flows_lock);
410 if (mlx5e_is_eswitch_flow(flow))
411 flow->esw_attr->mod_hdr_id = mh->mod_hdr_id;
412 else
413 flow->nic_attr->mod_hdr_id = mh->mod_hdr_id;
414
415 return 0;
416
417alloc_header_err:
418 complete_all(&mh->res_ready);
419attach_header_err:
420 mlx5e_mod_hdr_put(priv, mh, namespace);
421 return err;
422}
423
424static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv,
425 struct mlx5e_tc_flow *flow)
426{
427 /* flow wasn't fully initialized */
428 if (!flow->mh)
429 return;
430
431 spin_lock(&flow->mh->flows_lock);
432 list_del(&flow->mod_hdr);
433 spin_unlock(&flow->mh->flows_lock);
434
435 mlx5e_mod_hdr_put(priv, flow->mh, get_flow_name_space(flow));
436 flow->mh = NULL;
437}
438
439static
440struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
441{
442 struct net_device *netdev;
443 struct mlx5e_priv *priv;
444
445 netdev = __dev_get_by_index(net, ifindex);
446 priv = netdev_priv(netdev);
447 return priv->mdev;
448}
449
450static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
451{
452 u32 in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
453 void *tirc;
454 int err;
455
456 err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
457 if (err)
458 goto alloc_tdn_err;
459
460 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
461
462 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
463 MLX5_SET(tirc, tirc, inline_rqn, hp->pair->rqn[0]);
464 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
465
466 err = mlx5_core_create_tir(hp->func_mdev, in, MLX5_ST_SZ_BYTES(create_tir_in), &hp->tirn);
467 if (err)
468 goto create_tir_err;
469
470 return 0;
471
472create_tir_err:
473 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
474alloc_tdn_err:
475 return err;
476}
477
478static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
479{
480 mlx5_core_destroy_tir(hp->func_mdev, hp->tirn);
481 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
482}
483
484static void mlx5e_hairpin_fill_rqt_rqns(struct mlx5e_hairpin *hp, void *rqtc)
485{
486 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE], rqn;
487 struct mlx5e_priv *priv = hp->func_priv;
488 int i, ix, sz = MLX5E_INDIR_RQT_SIZE;
489
490 mlx5e_build_default_indir_rqt(indirection_rqt, sz,
491 hp->num_channels);
492
493 for (i = 0; i < sz; i++) {
494 ix = i;
495 if (priv->rss_params.hfunc == ETH_RSS_HASH_XOR)
496 ix = mlx5e_bits_invert(i, ilog2(sz));
497 ix = indirection_rqt[ix];
498 rqn = hp->pair->rqn[ix];
499 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
500 }
501}
502
503static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp)
504{
505 int inlen, err, sz = MLX5E_INDIR_RQT_SIZE;
506 struct mlx5e_priv *priv = hp->func_priv;
507 struct mlx5_core_dev *mdev = priv->mdev;
508 void *rqtc;
509 u32 *in;
510
511 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
512 in = kvzalloc(inlen, GFP_KERNEL);
513 if (!in)
514 return -ENOMEM;
515
516 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
517
518 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
519 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
520
521 mlx5e_hairpin_fill_rqt_rqns(hp, rqtc);
522
523 err = mlx5_core_create_rqt(mdev, in, inlen, &hp->indir_rqt.rqtn);
524 if (!err)
525 hp->indir_rqt.enabled = true;
526
527 kvfree(in);
528 return err;
529}
530
531static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
532{
533 struct mlx5e_priv *priv = hp->func_priv;
534 u32 in[MLX5_ST_SZ_DW(create_tir_in)];
535 int tt, i, err;
536 void *tirc;
537
538 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
539 struct mlx5e_tirc_config ttconfig = mlx5e_tirc_get_default_config(tt);
540
541 memset(in, 0, MLX5_ST_SZ_BYTES(create_tir_in));
542 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
543
544 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
545 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
546 MLX5_SET(tirc, tirc, indirect_table, hp->indir_rqt.rqtn);
547 mlx5e_build_indir_tir_ctx_hash(&priv->rss_params, &ttconfig, tirc, false);
548
549 err = mlx5_core_create_tir(hp->func_mdev, in,
550 MLX5_ST_SZ_BYTES(create_tir_in), &hp->indir_tirn[tt]);
551 if (err) {
552 mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
553 goto err_destroy_tirs;
554 }
555 }
556 return 0;
557
558err_destroy_tirs:
559 for (i = 0; i < tt; i++)
560 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[i]);
561 return err;
562}
563
564static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp)
565{
566 int tt;
567
568 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
569 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[tt]);
570}
571
572static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp,
573 struct ttc_params *ttc_params)
574{
575 struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr;
576 int tt;
577
578 memset(ttc_params, 0, sizeof(*ttc_params));
579
580 ttc_params->any_tt_tirn = hp->tirn;
581
582 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
583 ttc_params->indir_tirn[tt] = hp->indir_tirn[tt];
584
585 ft_attr->max_fte = MLX5E_NUM_TT;
586 ft_attr->level = MLX5E_TC_TTC_FT_LEVEL;
587 ft_attr->prio = MLX5E_TC_PRIO;
588}
589
590static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp)
591{
592 struct mlx5e_priv *priv = hp->func_priv;
593 struct ttc_params ttc_params;
594 int err;
595
596 err = mlx5e_hairpin_create_indirect_rqt(hp);
597 if (err)
598 return err;
599
600 err = mlx5e_hairpin_create_indirect_tirs(hp);
601 if (err)
602 goto err_create_indirect_tirs;
603
604 mlx5e_hairpin_set_ttc_params(hp, &ttc_params);
605 err = mlx5e_create_ttc_table(priv, &ttc_params, &hp->ttc);
606 if (err)
607 goto err_create_ttc_table;
608
609 netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n",
610 hp->num_channels, hp->ttc.ft.t->id);
611
612 return 0;
613
614err_create_ttc_table:
615 mlx5e_hairpin_destroy_indirect_tirs(hp);
616err_create_indirect_tirs:
617 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
618
619 return err;
620}
621
622static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp)
623{
624 struct mlx5e_priv *priv = hp->func_priv;
625
626 mlx5e_destroy_ttc_table(priv, &hp->ttc);
627 mlx5e_hairpin_destroy_indirect_tirs(hp);
628 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
629}
630
631static struct mlx5e_hairpin *
632mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
633 int peer_ifindex)
634{
635 struct mlx5_core_dev *func_mdev, *peer_mdev;
636 struct mlx5e_hairpin *hp;
637 struct mlx5_hairpin *pair;
638 int err;
639
640 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
641 if (!hp)
642 return ERR_PTR(-ENOMEM);
643
644 func_mdev = priv->mdev;
645 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
646
647 pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
648 if (IS_ERR(pair)) {
649 err = PTR_ERR(pair);
650 goto create_pair_err;
651 }
652 hp->pair = pair;
653 hp->func_mdev = func_mdev;
654 hp->func_priv = priv;
655 hp->num_channels = params->num_channels;
656
657 err = mlx5e_hairpin_create_transport(hp);
658 if (err)
659 goto create_transport_err;
660
661 if (hp->num_channels > 1) {
662 err = mlx5e_hairpin_rss_init(hp);
663 if (err)
664 goto rss_init_err;
665 }
666
667 return hp;
668
669rss_init_err:
670 mlx5e_hairpin_destroy_transport(hp);
671create_transport_err:
672 mlx5_core_hairpin_destroy(hp->pair);
673create_pair_err:
674 kfree(hp);
675 return ERR_PTR(err);
676}
677
678static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
679{
680 if (hp->num_channels > 1)
681 mlx5e_hairpin_rss_cleanup(hp);
682 mlx5e_hairpin_destroy_transport(hp);
683 mlx5_core_hairpin_destroy(hp->pair);
684 kvfree(hp);
685}
686
687static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
688{
689 return (peer_vhca_id << 16 | prio);
690}
691
692static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
693 u16 peer_vhca_id, u8 prio)
694{
695 struct mlx5e_hairpin_entry *hpe;
696 u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
697
698 hash_for_each_possible(priv->fs.tc.hairpin_tbl, hpe,
699 hairpin_hlist, hash_key) {
700 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio) {
701 refcount_inc(&hpe->refcnt);
702 return hpe;
703 }
704 }
705
706 return NULL;
707}
708
709static void mlx5e_hairpin_put(struct mlx5e_priv *priv,
710 struct mlx5e_hairpin_entry *hpe)
711{
712 /* no more hairpin flows for us, release the hairpin pair */
713 if (!refcount_dec_and_mutex_lock(&hpe->refcnt, &priv->fs.tc.hairpin_tbl_lock))
714 return;
715 hash_del(&hpe->hairpin_hlist);
716 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
717
718 if (!IS_ERR_OR_NULL(hpe->hp)) {
719 netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
720 dev_name(hpe->hp->pair->peer_mdev->device));
721
722 mlx5e_hairpin_destroy(hpe->hp);
723 }
724
725 WARN_ON(!list_empty(&hpe->flows));
726 kfree(hpe);
727}
728
729#define UNKNOWN_MATCH_PRIO 8
730
731static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
732 struct mlx5_flow_spec *spec, u8 *match_prio,
733 struct netlink_ext_ack *extack)
734{
735 void *headers_c, *headers_v;
736 u8 prio_val, prio_mask = 0;
737 bool vlan_present;
738
739#ifdef CONFIG_MLX5_CORE_EN_DCB
740 if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
741 NL_SET_ERR_MSG_MOD(extack,
742 "only PCP trust state supported for hairpin");
743 return -EOPNOTSUPP;
744 }
745#endif
746 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
747 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
748
749 vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
750 if (vlan_present) {
751 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
752 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
753 }
754
755 if (!vlan_present || !prio_mask) {
756 prio_val = UNKNOWN_MATCH_PRIO;
757 } else if (prio_mask != 0x7) {
758 NL_SET_ERR_MSG_MOD(extack,
759 "masked priority match not supported for hairpin");
760 return -EOPNOTSUPP;
761 }
762
763 *match_prio = prio_val;
764 return 0;
765}
766
767static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
768 struct mlx5e_tc_flow *flow,
769 struct mlx5e_tc_flow_parse_attr *parse_attr,
770 struct netlink_ext_ack *extack)
771{
772 int peer_ifindex = parse_attr->mirred_ifindex[0];
773 struct mlx5_hairpin_params params;
774 struct mlx5_core_dev *peer_mdev;
775 struct mlx5e_hairpin_entry *hpe;
776 struct mlx5e_hairpin *hp;
777 u64 link_speed64;
778 u32 link_speed;
779 u8 match_prio;
780 u16 peer_id;
781 int err;
782
783 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
784 if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
785 NL_SET_ERR_MSG_MOD(extack, "hairpin is not supported");
786 return -EOPNOTSUPP;
787 }
788
789 peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
790 err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio,
791 extack);
792 if (err)
793 return err;
794
795 mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
796 hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
797 if (hpe) {
798 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
799 wait_for_completion(&hpe->res_ready);
800
801 if (IS_ERR(hpe->hp)) {
802 err = -EREMOTEIO;
803 goto out_err;
804 }
805 goto attach_flow;
806 }
807
808 hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
809 if (!hpe) {
810 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
811 return -ENOMEM;
812 }
813
814 spin_lock_init(&hpe->flows_lock);
815 INIT_LIST_HEAD(&hpe->flows);
816 INIT_LIST_HEAD(&hpe->dead_peer_wait_list);
817 hpe->peer_vhca_id = peer_id;
818 hpe->prio = match_prio;
819 refcount_set(&hpe->refcnt, 1);
820 init_completion(&hpe->res_ready);
821
822 hash_add(priv->fs.tc.hairpin_tbl, &hpe->hairpin_hlist,
823 hash_hairpin_info(peer_id, match_prio));
824 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
825
826 params.log_data_size = 15;
827 params.log_data_size = min_t(u8, params.log_data_size,
828 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
829 params.log_data_size = max_t(u8, params.log_data_size,
830 MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz));
831
832 params.log_num_packets = params.log_data_size -
833 MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev);
834 params.log_num_packets = min_t(u8, params.log_num_packets,
835 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_num_packets));
836
837 params.q_counter = priv->q_counter;
838 /* set hairpin pair per each 50Gbs share of the link */
839 mlx5e_port_max_linkspeed(priv->mdev, &link_speed);
840 link_speed = max_t(u32, link_speed, 50000);
841 link_speed64 = link_speed;
842 do_div(link_speed64, 50000);
843 params.num_channels = link_speed64;
844
845 hp = mlx5e_hairpin_create(priv, &params, peer_ifindex);
846 hpe->hp = hp;
847 complete_all(&hpe->res_ready);
848 if (IS_ERR(hp)) {
849 err = PTR_ERR(hp);
850 goto out_err;
851 }
852
853 netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n",
854 hp->tirn, hp->pair->rqn[0],
855 dev_name(hp->pair->peer_mdev->device),
856 hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets);
857
858attach_flow:
859 if (hpe->hp->num_channels > 1) {
860 flow_flag_set(flow, HAIRPIN_RSS);
861 flow->nic_attr->hairpin_ft = hpe->hp->ttc.ft.t;
862 } else {
863 flow->nic_attr->hairpin_tirn = hpe->hp->tirn;
864 }
865
866 flow->hpe = hpe;
867 spin_lock(&hpe->flows_lock);
868 list_add(&flow->hairpin, &hpe->flows);
869 spin_unlock(&hpe->flows_lock);
870
871 return 0;
872
873out_err:
874 mlx5e_hairpin_put(priv, hpe);
875 return err;
876}
877
878static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
879 struct mlx5e_tc_flow *flow)
880{
881 /* flow wasn't fully initialized */
882 if (!flow->hpe)
883 return;
884
885 spin_lock(&flow->hpe->flows_lock);
886 list_del(&flow->hairpin);
887 spin_unlock(&flow->hpe->flows_lock);
888
889 mlx5e_hairpin_put(priv, flow->hpe);
890 flow->hpe = NULL;
891}
892
893static int
894mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
895 struct mlx5e_tc_flow_parse_attr *parse_attr,
896 struct mlx5e_tc_flow *flow,
897 struct netlink_ext_ack *extack)
898{
899 struct mlx5_flow_context *flow_context = &parse_attr->spec.flow_context;
900 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
901 struct mlx5_core_dev *dev = priv->mdev;
902 struct mlx5_flow_destination dest[2] = {};
903 struct mlx5_flow_act flow_act = {
904 .action = attr->action,
905 .reformat_id = 0,
906 .flags = FLOW_ACT_NO_APPEND,
907 };
908 struct mlx5_fc *counter = NULL;
909 int err, dest_ix = 0;
910
911 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
912 flow_context->flow_tag = attr->flow_tag;
913
914 if (flow_flag_test(flow, HAIRPIN)) {
915 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr, extack);
916 if (err)
917 return err;
918
919 if (flow_flag_test(flow, HAIRPIN_RSS)) {
920 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
921 dest[dest_ix].ft = attr->hairpin_ft;
922 } else {
923 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
924 dest[dest_ix].tir_num = attr->hairpin_tirn;
925 }
926 dest_ix++;
927 } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
928 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
929 dest[dest_ix].ft = priv->fs.vlan.ft.t;
930 dest_ix++;
931 }
932
933 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
934 counter = mlx5_fc_create(dev, true);
935 if (IS_ERR(counter))
936 return PTR_ERR(counter);
937
938 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
939 dest[dest_ix].counter_id = mlx5_fc_id(counter);
940 dest_ix++;
941 attr->counter = counter;
942 }
943
944 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
945 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
946 flow_act.modify_id = attr->mod_hdr_id;
947 kfree(parse_attr->mod_hdr_actions);
948 if (err)
949 return err;
950 }
951
952 mutex_lock(&priv->fs.tc.t_lock);
953 if (IS_ERR_OR_NULL(priv->fs.tc.t)) {
954 int tc_grp_size, tc_tbl_size;
955 u32 max_flow_counter;
956
957 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
958 MLX5_CAP_GEN(dev, max_flow_counter_15_0);
959
960 tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE);
961
962 tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS,
963 BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size)));
964
965 priv->fs.tc.t =
966 mlx5_create_auto_grouped_flow_table(priv->fs.ns,
967 MLX5E_TC_PRIO,
968 tc_tbl_size,
969 MLX5E_TC_TABLE_NUM_GROUPS,
970 MLX5E_TC_FT_LEVEL, 0);
971 if (IS_ERR(priv->fs.tc.t)) {
972 mutex_unlock(&priv->fs.tc.t_lock);
973 NL_SET_ERR_MSG_MOD(extack,
974 "Failed to create tc offload table\n");
975 netdev_err(priv->netdev,
976 "Failed to create tc offload table\n");
977 return PTR_ERR(priv->fs.tc.t);
978 }
979 }
980
981 if (attr->match_level != MLX5_MATCH_NONE)
982 parse_attr->spec.match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
983
984 flow->rule[0] = mlx5_add_flow_rules(priv->fs.tc.t, &parse_attr->spec,
985 &flow_act, dest, dest_ix);
986 mutex_unlock(&priv->fs.tc.t_lock);
987
988 if (IS_ERR(flow->rule[0]))
989 return PTR_ERR(flow->rule[0]);
990
991 return 0;
992}
993
994static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
995 struct mlx5e_tc_flow *flow)
996{
997 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
998 struct mlx5_fc *counter = NULL;
999
1000 counter = attr->counter;
1001 if (!IS_ERR_OR_NULL(flow->rule[0]))
1002 mlx5_del_flow_rules(flow->rule[0]);
1003 mlx5_fc_destroy(priv->mdev, counter);
1004
1005 mutex_lock(&priv->fs.tc.t_lock);
1006 if (!mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD)) && priv->fs.tc.t) {
1007 mlx5_destroy_flow_table(priv->fs.tc.t);
1008 priv->fs.tc.t = NULL;
1009 }
1010 mutex_unlock(&priv->fs.tc.t_lock);
1011
1012 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1013 mlx5e_detach_mod_hdr(priv, flow);
1014
1015 if (flow_flag_test(flow, HAIRPIN))
1016 mlx5e_hairpin_flow_del(priv, flow);
1017}
1018
1019static void mlx5e_detach_encap(struct mlx5e_priv *priv,
1020 struct mlx5e_tc_flow *flow, int out_index);
1021
1022static int mlx5e_attach_encap(struct mlx5e_priv *priv,
1023 struct mlx5e_tc_flow *flow,
1024 struct net_device *mirred_dev,
1025 int out_index,
1026 struct netlink_ext_ack *extack,
1027 struct net_device **encap_dev,
1028 bool *encap_valid);
1029
1030static struct mlx5_flow_handle *
1031mlx5e_tc_offload_fdb_rules(struct mlx5_eswitch *esw,
1032 struct mlx5e_tc_flow *flow,
1033 struct mlx5_flow_spec *spec,
1034 struct mlx5_esw_flow_attr *attr)
1035{
1036 struct mlx5_flow_handle *rule;
1037
1038 rule = mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
1039 if (IS_ERR(rule))
1040 return rule;
1041
1042 if (attr->split_count) {
1043 flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, spec, attr);
1044 if (IS_ERR(flow->rule[1])) {
1045 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
1046 return flow->rule[1];
1047 }
1048 }
1049
1050 return rule;
1051}
1052
1053static void
1054mlx5e_tc_unoffload_fdb_rules(struct mlx5_eswitch *esw,
1055 struct mlx5e_tc_flow *flow,
1056 struct mlx5_esw_flow_attr *attr)
1057{
1058 flow_flag_clear(flow, OFFLOADED);
1059
1060 if (attr->split_count)
1061 mlx5_eswitch_del_fwd_rule(esw, flow->rule[1], attr);
1062
1063 mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
1064}
1065
1066static struct mlx5_flow_handle *
1067mlx5e_tc_offload_to_slow_path(struct mlx5_eswitch *esw,
1068 struct mlx5e_tc_flow *flow,
1069 struct mlx5_flow_spec *spec,
1070 struct mlx5_esw_flow_attr *slow_attr)
1071{
1072 struct mlx5_flow_handle *rule;
1073
1074 memcpy(slow_attr, flow->esw_attr, sizeof(*slow_attr));
1075 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1076 slow_attr->split_count = 0;
1077 slow_attr->dest_chain = FDB_SLOW_PATH_CHAIN;
1078
1079 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, slow_attr);
1080 if (!IS_ERR(rule))
1081 flow_flag_set(flow, SLOW);
1082
1083 return rule;
1084}
1085
1086static void
1087mlx5e_tc_unoffload_from_slow_path(struct mlx5_eswitch *esw,
1088 struct mlx5e_tc_flow *flow,
1089 struct mlx5_esw_flow_attr *slow_attr)
1090{
1091 memcpy(slow_attr, flow->esw_attr, sizeof(*slow_attr));
1092 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1093 slow_attr->split_count = 0;
1094 slow_attr->dest_chain = FDB_SLOW_PATH_CHAIN;
1095 mlx5e_tc_unoffload_fdb_rules(esw, flow, slow_attr);
1096 flow_flag_clear(flow, SLOW);
1097}
1098
1099/* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1100 * function.
1101 */
1102static void unready_flow_add(struct mlx5e_tc_flow *flow,
1103 struct list_head *unready_flows)
1104{
1105 flow_flag_set(flow, NOT_READY);
1106 list_add_tail(&flow->unready, unready_flows);
1107}
1108
1109/* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1110 * function.
1111 */
1112static void unready_flow_del(struct mlx5e_tc_flow *flow)
1113{
1114 list_del(&flow->unready);
1115 flow_flag_clear(flow, NOT_READY);
1116}
1117
1118static void add_unready_flow(struct mlx5e_tc_flow *flow)
1119{
1120 struct mlx5_rep_uplink_priv *uplink_priv;
1121 struct mlx5e_rep_priv *rpriv;
1122 struct mlx5_eswitch *esw;
1123
1124 esw = flow->priv->mdev->priv.eswitch;
1125 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1126 uplink_priv = &rpriv->uplink_priv;
1127
1128 mutex_lock(&uplink_priv->unready_flows_lock);
1129 unready_flow_add(flow, &uplink_priv->unready_flows);
1130 mutex_unlock(&uplink_priv->unready_flows_lock);
1131}
1132
1133static void remove_unready_flow(struct mlx5e_tc_flow *flow)
1134{
1135 struct mlx5_rep_uplink_priv *uplink_priv;
1136 struct mlx5e_rep_priv *rpriv;
1137 struct mlx5_eswitch *esw;
1138
1139 esw = flow->priv->mdev->priv.eswitch;
1140 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1141 uplink_priv = &rpriv->uplink_priv;
1142
1143 mutex_lock(&uplink_priv->unready_flows_lock);
1144 unready_flow_del(flow);
1145 mutex_unlock(&uplink_priv->unready_flows_lock);
1146}
1147
1148static int
1149mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
1150 struct mlx5e_tc_flow *flow,
1151 struct netlink_ext_ack *extack)
1152{
1153 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1154 u32 max_chain = mlx5_eswitch_get_chain_range(esw);
1155 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
1156 struct mlx5e_tc_flow_parse_attr *parse_attr = attr->parse_attr;
1157 u16 max_prio = mlx5_eswitch_get_prio_range(esw);
1158 struct net_device *out_dev, *encap_dev = NULL;
1159 struct mlx5_fc *counter = NULL;
1160 struct mlx5e_rep_priv *rpriv;
1161 struct mlx5e_priv *out_priv;
1162 bool encap_valid = true;
1163 int err = 0;
1164 int out_index;
1165
1166 if (!mlx5_eswitch_prios_supported(esw) && attr->prio != 1) {
1167 NL_SET_ERR_MSG(extack, "E-switch priorities unsupported, upgrade FW");
1168 return -EOPNOTSUPP;
1169 }
1170
1171 if (attr->chain > max_chain) {
1172 NL_SET_ERR_MSG(extack, "Requested chain is out of supported range");
1173 return -EOPNOTSUPP;
1174 }
1175
1176 if (attr->prio > max_prio) {
1177 NL_SET_ERR_MSG(extack, "Requested priority is out of supported range");
1178 return -EOPNOTSUPP;
1179 }
1180
1181 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) {
1182 int mirred_ifindex;
1183
1184 if (!(attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP))
1185 continue;
1186
1187 mirred_ifindex = parse_attr->mirred_ifindex[out_index];
1188 out_dev = __dev_get_by_index(dev_net(priv->netdev),
1189 mirred_ifindex);
1190 err = mlx5e_attach_encap(priv, flow, out_dev, out_index,
1191 extack, &encap_dev, &encap_valid);
1192 if (err)
1193 return err;
1194
1195 out_priv = netdev_priv(encap_dev);
1196 rpriv = out_priv->ppriv;
1197 attr->dests[out_index].rep = rpriv->rep;
1198 attr->dests[out_index].mdev = out_priv->mdev;
1199 }
1200
1201 err = mlx5_eswitch_add_vlan_action(esw, attr);
1202 if (err)
1203 return err;
1204
1205 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1206 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
1207 kfree(parse_attr->mod_hdr_actions);
1208 if (err)
1209 return err;
1210 }
1211
1212 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
1213 counter = mlx5_fc_create(attr->counter_dev, true);
1214 if (IS_ERR(counter))
1215 return PTR_ERR(counter);
1216
1217 attr->counter = counter;
1218 }
1219
1220 /* we get here if one of the following takes place:
1221 * (1) there's no error
1222 * (2) there's an encap action and we don't have valid neigh
1223 */
1224 if (!encap_valid) {
1225 /* continue with goto slow path rule instead */
1226 struct mlx5_esw_flow_attr slow_attr;
1227
1228 flow->rule[0] = mlx5e_tc_offload_to_slow_path(esw, flow, &parse_attr->spec, &slow_attr);
1229 } else {
1230 flow->rule[0] = mlx5e_tc_offload_fdb_rules(esw, flow, &parse_attr->spec, attr);
1231 }
1232
1233 if (IS_ERR(flow->rule[0]))
1234 return PTR_ERR(flow->rule[0]);
1235 else
1236 flow_flag_set(flow, OFFLOADED);
1237
1238 return 0;
1239}
1240
1241static bool mlx5_flow_has_geneve_opt(struct mlx5e_tc_flow *flow)
1242{
1243 struct mlx5_flow_spec *spec = &flow->esw_attr->parse_attr->spec;
1244 void *headers_v = MLX5_ADDR_OF(fte_match_param,
1245 spec->match_value,
1246 misc_parameters_3);
1247 u32 geneve_tlv_opt_0_data = MLX5_GET(fte_match_set_misc3,
1248 headers_v,
1249 geneve_tlv_option_0_data);
1250
1251 return !!geneve_tlv_opt_0_data;
1252}
1253
1254static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
1255 struct mlx5e_tc_flow *flow)
1256{
1257 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1258 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
1259 struct mlx5_esw_flow_attr slow_attr;
1260 int out_index;
1261
1262 if (flow_flag_test(flow, NOT_READY)) {
1263 remove_unready_flow(flow);
1264 kvfree(attr->parse_attr);
1265 return;
1266 }
1267
1268 if (mlx5e_is_offloaded_flow(flow)) {
1269 if (flow_flag_test(flow, SLOW))
1270 mlx5e_tc_unoffload_from_slow_path(esw, flow, &slow_attr);
1271 else
1272 mlx5e_tc_unoffload_fdb_rules(esw, flow, attr);
1273 }
1274
1275 if (mlx5_flow_has_geneve_opt(flow))
1276 mlx5_geneve_tlv_option_del(priv->mdev->geneve);
1277
1278 mlx5_eswitch_del_vlan_action(esw, attr);
1279
1280 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
1281 if (attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP)
1282 mlx5e_detach_encap(priv, flow, out_index);
1283 kvfree(attr->parse_attr);
1284
1285 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1286 mlx5e_detach_mod_hdr(priv, flow);
1287
1288 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
1289 mlx5_fc_destroy(attr->counter_dev, attr->counter);
1290}
1291
1292void mlx5e_tc_encap_flows_add(struct mlx5e_priv *priv,
1293 struct mlx5e_encap_entry *e)
1294{
1295 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1296 struct mlx5_esw_flow_attr slow_attr, *esw_attr;
1297 struct encap_flow_item *efi, *tmp;
1298 struct mlx5_flow_handle *rule;
1299 struct mlx5_flow_spec *spec;
1300 struct mlx5e_tc_flow *flow;
1301 int err;
1302
1303 err = mlx5_packet_reformat_alloc(priv->mdev,
1304 e->reformat_type,
1305 e->encap_size, e->encap_header,
1306 MLX5_FLOW_NAMESPACE_FDB,
1307 &e->encap_id);
1308 if (err) {
1309 mlx5_core_warn(priv->mdev, "Failed to offload cached encapsulation header, %d\n",
1310 err);
1311 return;
1312 }
1313 e->flags |= MLX5_ENCAP_ENTRY_VALID;
1314 mlx5e_rep_queue_neigh_stats_work(priv);
1315
1316 list_for_each_entry_safe(efi, tmp, &e->flows, list) {
1317 bool all_flow_encaps_valid = true;
1318 int i;
1319
1320 flow = container_of(efi, struct mlx5e_tc_flow, encaps[efi->index]);
1321 if (IS_ERR(mlx5e_flow_get(flow)))
1322 continue;
1323
1324 esw_attr = flow->esw_attr;
1325 spec = &esw_attr->parse_attr->spec;
1326
1327 esw_attr->dests[efi->index].encap_id = e->encap_id;
1328 esw_attr->dests[efi->index].flags |= MLX5_ESW_DEST_ENCAP_VALID;
1329 /* Flow can be associated with multiple encap entries.
1330 * Before offloading the flow verify that all of them have
1331 * a valid neighbour.
1332 */
1333 for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) {
1334 if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP))
1335 continue;
1336 if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP_VALID)) {
1337 all_flow_encaps_valid = false;
1338 break;
1339 }
1340 }
1341 /* Do not offload flows with unresolved neighbors */
1342 if (!all_flow_encaps_valid)
1343 goto loop_cont;
1344 /* update from slow path rule to encap rule */
1345 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, esw_attr);
1346 if (IS_ERR(rule)) {
1347 err = PTR_ERR(rule);
1348 mlx5_core_warn(priv->mdev, "Failed to update cached encapsulation flow, %d\n",
1349 err);
1350 goto loop_cont;
1351 }
1352
1353 mlx5e_tc_unoffload_from_slow_path(esw, flow, &slow_attr);
1354 flow->rule[0] = rule;
1355 /* was unset when slow path rule removed */
1356 flow_flag_set(flow, OFFLOADED);
1357
1358loop_cont:
1359 mlx5e_flow_put(priv, flow);
1360 }
1361}
1362
1363void mlx5e_tc_encap_flows_del(struct mlx5e_priv *priv,
1364 struct mlx5e_encap_entry *e)
1365{
1366 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1367 struct mlx5_esw_flow_attr slow_attr;
1368 struct encap_flow_item *efi, *tmp;
1369 struct mlx5_flow_handle *rule;
1370 struct mlx5_flow_spec *spec;
1371 struct mlx5e_tc_flow *flow;
1372 int err;
1373
1374 list_for_each_entry_safe(efi, tmp, &e->flows, list) {
1375 flow = container_of(efi, struct mlx5e_tc_flow, encaps[efi->index]);
1376 if (IS_ERR(mlx5e_flow_get(flow)))
1377 continue;
1378
1379 spec = &flow->esw_attr->parse_attr->spec;
1380
1381 /* update from encap rule to slow path rule */
1382 rule = mlx5e_tc_offload_to_slow_path(esw, flow, spec, &slow_attr);
1383 /* mark the flow's encap dest as non-valid */
1384 flow->esw_attr->dests[efi->index].flags &= ~MLX5_ESW_DEST_ENCAP_VALID;
1385
1386 if (IS_ERR(rule)) {
1387 err = PTR_ERR(rule);
1388 mlx5_core_warn(priv->mdev, "Failed to update slow path (encap) flow, %d\n",
1389 err);
1390 goto loop_cont;
1391 }
1392
1393 mlx5e_tc_unoffload_fdb_rules(esw, flow, flow->esw_attr);
1394 flow->rule[0] = rule;
1395 /* was unset when fast path rule removed */
1396 flow_flag_set(flow, OFFLOADED);
1397
1398loop_cont:
1399 mlx5e_flow_put(priv, flow);
1400 }
1401
1402 /* we know that the encap is valid */
1403 e->flags &= ~MLX5_ENCAP_ENTRY_VALID;
1404 mlx5_packet_reformat_dealloc(priv->mdev, e->encap_id);
1405}
1406
1407static struct mlx5_fc *mlx5e_tc_get_counter(struct mlx5e_tc_flow *flow)
1408{
1409 if (mlx5e_is_eswitch_flow(flow))
1410 return flow->esw_attr->counter;
1411 else
1412 return flow->nic_attr->counter;
1413}
1414
1415static struct mlx5e_encap_entry *
1416mlx5e_get_next_valid_encap(struct mlx5e_neigh_hash_entry *nhe,
1417 struct mlx5e_encap_entry *e)
1418{
1419 struct mlx5e_encap_entry *next = NULL;
1420
1421retry:
1422 rcu_read_lock();
1423
1424 /* find encap with non-zero reference counter value */
1425 for (next = e ?
1426 list_next_or_null_rcu(&nhe->encap_list,
1427 &e->encap_list,
1428 struct mlx5e_encap_entry,
1429 encap_list) :
1430 list_first_or_null_rcu(&nhe->encap_list,
1431 struct mlx5e_encap_entry,
1432 encap_list);
1433 next;
1434 next = list_next_or_null_rcu(&nhe->encap_list,
1435 &next->encap_list,
1436 struct mlx5e_encap_entry,
1437 encap_list))
1438 if (mlx5e_encap_take(next))
1439 break;
1440
1441 rcu_read_unlock();
1442
1443 /* release starting encap */
1444 if (e)
1445 mlx5e_encap_put(netdev_priv(e->out_dev), e);
1446 if (!next)
1447 return next;
1448
1449 /* wait for encap to be fully initialized */
1450 wait_for_completion(&next->res_ready);
1451 /* continue searching if encap entry is not in valid state after completion */
1452 if (!(next->flags & MLX5_ENCAP_ENTRY_VALID)) {
1453 e = next;
1454 goto retry;
1455 }
1456
1457 return next;
1458}
1459
1460void mlx5e_tc_update_neigh_used_value(struct mlx5e_neigh_hash_entry *nhe)
1461{
1462 struct mlx5e_neigh *m_neigh = &nhe->m_neigh;
1463 struct mlx5e_encap_entry *e = NULL;
1464 struct mlx5e_tc_flow *flow;
1465 struct mlx5_fc *counter;
1466 struct neigh_table *tbl;
1467 bool neigh_used = false;
1468 struct neighbour *n;
1469 u64 lastuse;
1470
1471 if (m_neigh->family == AF_INET)
1472 tbl = &arp_tbl;
1473#if IS_ENABLED(CONFIG_IPV6)
1474 else if (m_neigh->family == AF_INET6)
1475 tbl = &nd_tbl;
1476#endif
1477 else
1478 return;
1479
1480 /* mlx5e_get_next_valid_encap() releases previous encap before returning
1481 * next one.
1482 */
1483 while ((e = mlx5e_get_next_valid_encap(nhe, e)) != NULL) {
1484 struct encap_flow_item *efi, *tmp;
1485
1486 list_for_each_entry_safe(efi, tmp, &e->flows, list) {
1487 flow = container_of(efi, struct mlx5e_tc_flow,
1488 encaps[efi->index]);
1489 if (IS_ERR(mlx5e_flow_get(flow)))
1490 continue;
1491
1492 if (mlx5e_is_offloaded_flow(flow)) {
1493 counter = mlx5e_tc_get_counter(flow);
1494 lastuse = mlx5_fc_query_lastuse(counter);
1495 if (time_after((unsigned long)lastuse, nhe->reported_lastuse)) {
1496 mlx5e_flow_put(netdev_priv(e->out_dev), flow);
1497 neigh_used = true;
1498 break;
1499 }
1500 }
1501
1502 mlx5e_flow_put(netdev_priv(e->out_dev), flow);
1503 }
1504
1505 if (neigh_used) {
1506 /* release current encap before breaking the loop */
1507 mlx5e_encap_put(netdev_priv(e->out_dev), e);
1508 break;
1509 }
1510 }
1511
1512 if (neigh_used) {
1513 nhe->reported_lastuse = jiffies;
1514
1515 /* find the relevant neigh according to the cached device and
1516 * dst ip pair
1517 */
1518 n = neigh_lookup(tbl, &m_neigh->dst_ip, m_neigh->dev);
1519 if (!n)
1520 return;
1521
1522 neigh_event_send(n, NULL);
1523 neigh_release(n);
1524 }
1525}
1526
1527static void mlx5e_encap_dealloc(struct mlx5e_priv *priv, struct mlx5e_encap_entry *e)
1528{
1529 WARN_ON(!list_empty(&e->flows));
1530
1531 if (e->compl_result > 0) {
1532 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
1533
1534 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
1535 mlx5_packet_reformat_dealloc(priv->mdev, e->encap_id);
1536 }
1537
1538 kfree(e->encap_header);
1539 kfree_rcu(e, rcu);
1540}
1541
1542void mlx5e_encap_put(struct mlx5e_priv *priv, struct mlx5e_encap_entry *e)
1543{
1544 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1545
1546 if (!refcount_dec_and_mutex_lock(&e->refcnt, &esw->offloads.encap_tbl_lock))
1547 return;
1548 hash_del_rcu(&e->encap_hlist);
1549 mutex_unlock(&esw->offloads.encap_tbl_lock);
1550
1551 mlx5e_encap_dealloc(priv, e);
1552}
1553
1554static void mlx5e_detach_encap(struct mlx5e_priv *priv,
1555 struct mlx5e_tc_flow *flow, int out_index)
1556{
1557 struct mlx5e_encap_entry *e = flow->encaps[out_index].e;
1558 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1559
1560 /* flow wasn't fully initialized */
1561 if (!e)
1562 return;
1563
1564 mutex_lock(&esw->offloads.encap_tbl_lock);
1565 list_del(&flow->encaps[out_index].list);
1566 flow->encaps[out_index].e = NULL;
1567 if (!refcount_dec_and_test(&e->refcnt)) {
1568 mutex_unlock(&esw->offloads.encap_tbl_lock);
1569 return;
1570 }
1571 hash_del_rcu(&e->encap_hlist);
1572 mutex_unlock(&esw->offloads.encap_tbl_lock);
1573
1574 mlx5e_encap_dealloc(priv, e);
1575}
1576
1577static void __mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1578{
1579 struct mlx5_eswitch *esw = flow->priv->mdev->priv.eswitch;
1580
1581 if (!flow_flag_test(flow, ESWITCH) ||
1582 !flow_flag_test(flow, DUP))
1583 return;
1584
1585 mutex_lock(&esw->offloads.peer_mutex);
1586 list_del(&flow->peer);
1587 mutex_unlock(&esw->offloads.peer_mutex);
1588
1589 flow_flag_clear(flow, DUP);
1590
1591 mlx5e_tc_del_fdb_flow(flow->peer_flow->priv, flow->peer_flow);
1592 kvfree(flow->peer_flow);
1593 flow->peer_flow = NULL;
1594}
1595
1596static void mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1597{
1598 struct mlx5_core_dev *dev = flow->priv->mdev;
1599 struct mlx5_devcom *devcom = dev->priv.devcom;
1600 struct mlx5_eswitch *peer_esw;
1601
1602 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1603 if (!peer_esw)
1604 return;
1605
1606 __mlx5e_tc_del_fdb_peer_flow(flow);
1607 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1608}
1609
1610static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
1611 struct mlx5e_tc_flow *flow)
1612{
1613 if (mlx5e_is_eswitch_flow(flow)) {
1614 mlx5e_tc_del_fdb_peer_flow(flow);
1615 mlx5e_tc_del_fdb_flow(priv, flow);
1616 } else {
1617 mlx5e_tc_del_nic_flow(priv, flow);
1618 }
1619}
1620
1621
1622static int parse_tunnel_attr(struct mlx5e_priv *priv,
1623 struct mlx5_flow_spec *spec,
1624 struct flow_cls_offload *f,
1625 struct net_device *filter_dev, u8 *match_level)
1626{
1627 struct netlink_ext_ack *extack = f->common.extack;
1628 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1629 outer_headers);
1630 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1631 outer_headers);
1632 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
1633 int err;
1634
1635 err = mlx5e_tc_tun_parse(filter_dev, priv, spec, f,
1636 headers_c, headers_v, match_level);
1637 if (err) {
1638 NL_SET_ERR_MSG_MOD(extack,
1639 "failed to parse tunnel attributes");
1640 return err;
1641 }
1642
1643 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS)) {
1644 struct flow_match_ipv4_addrs match;
1645
1646 flow_rule_match_enc_ipv4_addrs(rule, &match);
1647 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1648 src_ipv4_src_ipv6.ipv4_layout.ipv4,
1649 ntohl(match.mask->src));
1650 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1651 src_ipv4_src_ipv6.ipv4_layout.ipv4,
1652 ntohl(match.key->src));
1653
1654 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1655 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
1656 ntohl(match.mask->dst));
1657 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1658 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
1659 ntohl(match.key->dst));
1660
1661 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
1662 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IP);
1663 } else if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS)) {
1664 struct flow_match_ipv6_addrs match;
1665
1666 flow_rule_match_enc_ipv6_addrs(rule, &match);
1667 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1668 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1669 &match.mask->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1670 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1671 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1672 &match.key->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1673
1674 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1675 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1676 &match.mask->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1677 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1678 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1679 &match.key->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1680
1681 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
1682 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IPV6);
1683 }
1684
1685 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_IP)) {
1686 struct flow_match_ip match;
1687
1688 flow_rule_match_enc_ip(rule, &match);
1689 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
1690 match.mask->tos & 0x3);
1691 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
1692 match.key->tos & 0x3);
1693
1694 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
1695 match.mask->tos >> 2);
1696 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
1697 match.key->tos >> 2);
1698
1699 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
1700 match.mask->ttl);
1701 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
1702 match.key->ttl);
1703
1704 if (match.mask->ttl &&
1705 !MLX5_CAP_ESW_FLOWTABLE_FDB
1706 (priv->mdev,
1707 ft_field_support.outer_ipv4_ttl)) {
1708 NL_SET_ERR_MSG_MOD(extack,
1709 "Matching on TTL is not supported");
1710 return -EOPNOTSUPP;
1711 }
1712
1713 }
1714
1715 /* Enforce DMAC when offloading incoming tunneled flows.
1716 * Flow counters require a match on the DMAC.
1717 */
1718 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_47_16);
1719 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_15_0);
1720 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1721 dmac_47_16), priv->netdev->dev_addr);
1722
1723 /* let software handle IP fragments */
1724 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
1725 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
1726
1727 return 0;
1728}
1729
1730static void *get_match_headers_criteria(u32 flags,
1731 struct mlx5_flow_spec *spec)
1732{
1733 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
1734 MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1735 inner_headers) :
1736 MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1737 outer_headers);
1738}
1739
1740static void *get_match_headers_value(u32 flags,
1741 struct mlx5_flow_spec *spec)
1742{
1743 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
1744 MLX5_ADDR_OF(fte_match_param, spec->match_value,
1745 inner_headers) :
1746 MLX5_ADDR_OF(fte_match_param, spec->match_value,
1747 outer_headers);
1748}
1749
1750static int __parse_cls_flower(struct mlx5e_priv *priv,
1751 struct mlx5_flow_spec *spec,
1752 struct flow_cls_offload *f,
1753 struct net_device *filter_dev,
1754 u8 *inner_match_level, u8 *outer_match_level)
1755{
1756 struct netlink_ext_ack *extack = f->common.extack;
1757 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1758 outer_headers);
1759 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1760 outer_headers);
1761 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1762 misc_parameters);
1763 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1764 misc_parameters);
1765 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
1766 struct flow_dissector *dissector = rule->match.dissector;
1767 u16 addr_type = 0;
1768 u8 ip_proto = 0;
1769 u8 *match_level;
1770
1771 match_level = outer_match_level;
1772
1773 if (dissector->used_keys &
1774 ~(BIT(FLOW_DISSECTOR_KEY_META) |
1775 BIT(FLOW_DISSECTOR_KEY_CONTROL) |
1776 BIT(FLOW_DISSECTOR_KEY_BASIC) |
1777 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
1778 BIT(FLOW_DISSECTOR_KEY_VLAN) |
1779 BIT(FLOW_DISSECTOR_KEY_CVLAN) |
1780 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
1781 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
1782 BIT(FLOW_DISSECTOR_KEY_PORTS) |
1783 BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
1784 BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
1785 BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
1786 BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
1787 BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
1788 BIT(FLOW_DISSECTOR_KEY_TCP) |
1789 BIT(FLOW_DISSECTOR_KEY_IP) |
1790 BIT(FLOW_DISSECTOR_KEY_ENC_IP) |
1791 BIT(FLOW_DISSECTOR_KEY_ENC_OPTS))) {
1792 NL_SET_ERR_MSG_MOD(extack, "Unsupported key");
1793 netdev_warn(priv->netdev, "Unsupported key used: 0x%x\n",
1794 dissector->used_keys);
1795 return -EOPNOTSUPP;
1796 }
1797
1798 if (mlx5e_get_tc_tun(filter_dev)) {
1799 if (parse_tunnel_attr(priv, spec, f, filter_dev,
1800 outer_match_level))
1801 return -EOPNOTSUPP;
1802
1803 /* At this point, header pointers should point to the inner
1804 * headers, outer header were already set by parse_tunnel_attr
1805 */
1806 match_level = inner_match_level;
1807 headers_c = get_match_headers_criteria(MLX5_FLOW_CONTEXT_ACTION_DECAP,
1808 spec);
1809 headers_v = get_match_headers_value(MLX5_FLOW_CONTEXT_ACTION_DECAP,
1810 spec);
1811 }
1812
1813 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
1814 struct flow_match_basic match;
1815
1816 flow_rule_match_basic(rule, &match);
1817 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
1818 ntohs(match.mask->n_proto));
1819 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
1820 ntohs(match.key->n_proto));
1821
1822 if (match.mask->n_proto)
1823 *match_level = MLX5_MATCH_L2;
1824 }
1825 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN) ||
1826 is_vlan_dev(filter_dev)) {
1827 struct flow_dissector_key_vlan filter_dev_mask;
1828 struct flow_dissector_key_vlan filter_dev_key;
1829 struct flow_match_vlan match;
1830
1831 if (is_vlan_dev(filter_dev)) {
1832 match.key = &filter_dev_key;
1833 match.key->vlan_id = vlan_dev_vlan_id(filter_dev);
1834 match.key->vlan_tpid = vlan_dev_vlan_proto(filter_dev);
1835 match.key->vlan_priority = 0;
1836 match.mask = &filter_dev_mask;
1837 memset(match.mask, 0xff, sizeof(*match.mask));
1838 match.mask->vlan_priority = 0;
1839 } else {
1840 flow_rule_match_vlan(rule, &match);
1841 }
1842 if (match.mask->vlan_id ||
1843 match.mask->vlan_priority ||
1844 match.mask->vlan_tpid) {
1845 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
1846 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1847 svlan_tag, 1);
1848 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1849 svlan_tag, 1);
1850 } else {
1851 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1852 cvlan_tag, 1);
1853 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1854 cvlan_tag, 1);
1855 }
1856
1857 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid,
1858 match.mask->vlan_id);
1859 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid,
1860 match.key->vlan_id);
1861
1862 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio,
1863 match.mask->vlan_priority);
1864 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio,
1865 match.key->vlan_priority);
1866
1867 *match_level = MLX5_MATCH_L2;
1868 }
1869 } else if (*match_level != MLX5_MATCH_NONE) {
1870 MLX5_SET(fte_match_set_lyr_2_4, headers_c, svlan_tag, 1);
1871 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
1872 *match_level = MLX5_MATCH_L2;
1873 }
1874
1875 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CVLAN)) {
1876 struct flow_match_vlan match;
1877
1878 flow_rule_match_cvlan(rule, &match);
1879 if (match.mask->vlan_id ||
1880 match.mask->vlan_priority ||
1881 match.mask->vlan_tpid) {
1882 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
1883 MLX5_SET(fte_match_set_misc, misc_c,
1884 outer_second_svlan_tag, 1);
1885 MLX5_SET(fte_match_set_misc, misc_v,
1886 outer_second_svlan_tag, 1);
1887 } else {
1888 MLX5_SET(fte_match_set_misc, misc_c,
1889 outer_second_cvlan_tag, 1);
1890 MLX5_SET(fte_match_set_misc, misc_v,
1891 outer_second_cvlan_tag, 1);
1892 }
1893
1894 MLX5_SET(fte_match_set_misc, misc_c, outer_second_vid,
1895 match.mask->vlan_id);
1896 MLX5_SET(fte_match_set_misc, misc_v, outer_second_vid,
1897 match.key->vlan_id);
1898 MLX5_SET(fte_match_set_misc, misc_c, outer_second_prio,
1899 match.mask->vlan_priority);
1900 MLX5_SET(fte_match_set_misc, misc_v, outer_second_prio,
1901 match.key->vlan_priority);
1902
1903 *match_level = MLX5_MATCH_L2;
1904 }
1905 }
1906
1907 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
1908 struct flow_match_eth_addrs match;
1909
1910 flow_rule_match_eth_addrs(rule, &match);
1911 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1912 dmac_47_16),
1913 match.mask->dst);
1914 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1915 dmac_47_16),
1916 match.key->dst);
1917
1918 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1919 smac_47_16),
1920 match.mask->src);
1921 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1922 smac_47_16),
1923 match.key->src);
1924
1925 if (!is_zero_ether_addr(match.mask->src) ||
1926 !is_zero_ether_addr(match.mask->dst))
1927 *match_level = MLX5_MATCH_L2;
1928 }
1929
1930 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CONTROL)) {
1931 struct flow_match_control match;
1932
1933 flow_rule_match_control(rule, &match);
1934 addr_type = match.key->addr_type;
1935
1936 /* the HW doesn't support frag first/later */
1937 if (match.mask->flags & FLOW_DIS_FIRST_FRAG)
1938 return -EOPNOTSUPP;
1939
1940 if (match.mask->flags & FLOW_DIS_IS_FRAGMENT) {
1941 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
1942 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
1943 match.key->flags & FLOW_DIS_IS_FRAGMENT);
1944
1945 /* the HW doesn't need L3 inline to match on frag=no */
1946 if (!(match.key->flags & FLOW_DIS_IS_FRAGMENT))
1947 *match_level = MLX5_MATCH_L2;
1948 /* *** L2 attributes parsing up to here *** */
1949 else
1950 *match_level = MLX5_MATCH_L3;
1951 }
1952 }
1953
1954 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
1955 struct flow_match_basic match;
1956
1957 flow_rule_match_basic(rule, &match);
1958 ip_proto = match.key->ip_proto;
1959
1960 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
1961 match.mask->ip_proto);
1962 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
1963 match.key->ip_proto);
1964
1965 if (match.mask->ip_proto)
1966 *match_level = MLX5_MATCH_L3;
1967 }
1968
1969 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
1970 struct flow_match_ipv4_addrs match;
1971
1972 flow_rule_match_ipv4_addrs(rule, &match);
1973 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1974 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1975 &match.mask->src, sizeof(match.mask->src));
1976 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1977 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1978 &match.key->src, sizeof(match.key->src));
1979 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1980 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1981 &match.mask->dst, sizeof(match.mask->dst));
1982 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1983 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1984 &match.key->dst, sizeof(match.key->dst));
1985
1986 if (match.mask->src || match.mask->dst)
1987 *match_level = MLX5_MATCH_L3;
1988 }
1989
1990 if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
1991 struct flow_match_ipv6_addrs match;
1992
1993 flow_rule_match_ipv6_addrs(rule, &match);
1994 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1995 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1996 &match.mask->src, sizeof(match.mask->src));
1997 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1998 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1999 &match.key->src, sizeof(match.key->src));
2000
2001 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2002 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2003 &match.mask->dst, sizeof(match.mask->dst));
2004 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2005 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2006 &match.key->dst, sizeof(match.key->dst));
2007
2008 if (ipv6_addr_type(&match.mask->src) != IPV6_ADDR_ANY ||
2009 ipv6_addr_type(&match.mask->dst) != IPV6_ADDR_ANY)
2010 *match_level = MLX5_MATCH_L3;
2011 }
2012
2013 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) {
2014 struct flow_match_ip match;
2015
2016 flow_rule_match_ip(rule, &match);
2017 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
2018 match.mask->tos & 0x3);
2019 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
2020 match.key->tos & 0x3);
2021
2022 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
2023 match.mask->tos >> 2);
2024 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
2025 match.key->tos >> 2);
2026
2027 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
2028 match.mask->ttl);
2029 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
2030 match.key->ttl);
2031
2032 if (match.mask->ttl &&
2033 !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
2034 ft_field_support.outer_ipv4_ttl)) {
2035 NL_SET_ERR_MSG_MOD(extack,
2036 "Matching on TTL is not supported");
2037 return -EOPNOTSUPP;
2038 }
2039
2040 if (match.mask->tos || match.mask->ttl)
2041 *match_level = MLX5_MATCH_L3;
2042 }
2043
2044 /* *** L3 attributes parsing up to here *** */
2045
2046 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) {
2047 struct flow_match_ports match;
2048
2049 flow_rule_match_ports(rule, &match);
2050 switch (ip_proto) {
2051 case IPPROTO_TCP:
2052 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2053 tcp_sport, ntohs(match.mask->src));
2054 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2055 tcp_sport, ntohs(match.key->src));
2056
2057 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2058 tcp_dport, ntohs(match.mask->dst));
2059 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2060 tcp_dport, ntohs(match.key->dst));
2061 break;
2062
2063 case IPPROTO_UDP:
2064 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2065 udp_sport, ntohs(match.mask->src));
2066 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2067 udp_sport, ntohs(match.key->src));
2068
2069 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2070 udp_dport, ntohs(match.mask->dst));
2071 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2072 udp_dport, ntohs(match.key->dst));
2073 break;
2074 default:
2075 NL_SET_ERR_MSG_MOD(extack,
2076 "Only UDP and TCP transports are supported for L4 matching");
2077 netdev_err(priv->netdev,
2078 "Only UDP and TCP transport are supported\n");
2079 return -EINVAL;
2080 }
2081
2082 if (match.mask->src || match.mask->dst)
2083 *match_level = MLX5_MATCH_L4;
2084 }
2085
2086 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_TCP)) {
2087 struct flow_match_tcp match;
2088
2089 flow_rule_match_tcp(rule, &match);
2090 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
2091 ntohs(match.mask->flags));
2092 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
2093 ntohs(match.key->flags));
2094
2095 if (match.mask->flags)
2096 *match_level = MLX5_MATCH_L4;
2097 }
2098
2099 return 0;
2100}
2101
2102static int parse_cls_flower(struct mlx5e_priv *priv,
2103 struct mlx5e_tc_flow *flow,
2104 struct mlx5_flow_spec *spec,
2105 struct flow_cls_offload *f,
2106 struct net_device *filter_dev)
2107{
2108 u8 inner_match_level, outer_match_level, non_tunnel_match_level;
2109 struct netlink_ext_ack *extack = f->common.extack;
2110 struct mlx5_core_dev *dev = priv->mdev;
2111 struct mlx5_eswitch *esw = dev->priv.eswitch;
2112 struct mlx5e_rep_priv *rpriv = priv->ppriv;
2113 struct mlx5_eswitch_rep *rep;
2114 bool is_eswitch_flow;
2115 int err;
2116
2117 inner_match_level = MLX5_MATCH_NONE;
2118 outer_match_level = MLX5_MATCH_NONE;
2119
2120 err = __parse_cls_flower(priv, spec, f, filter_dev, &inner_match_level,
2121 &outer_match_level);
2122 non_tunnel_match_level = (inner_match_level == MLX5_MATCH_NONE) ?
2123 outer_match_level : inner_match_level;
2124
2125 is_eswitch_flow = mlx5e_is_eswitch_flow(flow);
2126 if (!err && is_eswitch_flow) {
2127 rep = rpriv->rep;
2128 if (rep->vport != MLX5_VPORT_UPLINK &&
2129 (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
2130 esw->offloads.inline_mode < non_tunnel_match_level)) {
2131 NL_SET_ERR_MSG_MOD(extack,
2132 "Flow is not offloaded due to min inline setting");
2133 netdev_warn(priv->netdev,
2134 "Flow is not offloaded due to min inline setting, required %d actual %d\n",
2135 non_tunnel_match_level, esw->offloads.inline_mode);
2136 return -EOPNOTSUPP;
2137 }
2138 }
2139
2140 if (is_eswitch_flow) {
2141 flow->esw_attr->inner_match_level = inner_match_level;
2142 flow->esw_attr->outer_match_level = outer_match_level;
2143 } else {
2144 flow->nic_attr->match_level = non_tunnel_match_level;
2145 }
2146
2147 return err;
2148}
2149
2150struct pedit_headers {
2151 struct ethhdr eth;
2152 struct vlan_hdr vlan;
2153 struct iphdr ip4;
2154 struct ipv6hdr ip6;
2155 struct tcphdr tcp;
2156 struct udphdr udp;
2157};
2158
2159struct pedit_headers_action {
2160 struct pedit_headers vals;
2161 struct pedit_headers masks;
2162 u32 pedits;
2163};
2164
2165static int pedit_header_offsets[] = {
2166 [FLOW_ACT_MANGLE_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth),
2167 [FLOW_ACT_MANGLE_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4),
2168 [FLOW_ACT_MANGLE_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6),
2169 [FLOW_ACT_MANGLE_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp),
2170 [FLOW_ACT_MANGLE_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp),
2171};
2172
2173#define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype])
2174
2175static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset,
2176 struct pedit_headers_action *hdrs)
2177{
2178 u32 *curr_pmask, *curr_pval;
2179
2180 curr_pmask = (u32 *)(pedit_header(&hdrs->masks, hdr_type) + offset);
2181 curr_pval = (u32 *)(pedit_header(&hdrs->vals, hdr_type) + offset);
2182
2183 if (*curr_pmask & mask) /* disallow acting twice on the same location */
2184 goto out_err;
2185
2186 *curr_pmask |= mask;
2187 *curr_pval |= (val & mask);
2188
2189 return 0;
2190
2191out_err:
2192 return -EOPNOTSUPP;
2193}
2194
2195struct mlx5_fields {
2196 u8 field;
2197 u8 size;
2198 u32 offset;
2199 u32 match_offset;
2200};
2201
2202#define OFFLOAD(fw_field, size, field, off, match_field) \
2203 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, size, \
2204 offsetof(struct pedit_headers, field) + (off), \
2205 MLX5_BYTE_OFF(fte_match_set_lyr_2_4, match_field)}
2206
2207/* masked values are the same and there are no rewrites that do not have a
2208 * match.
2209 */
2210#define SAME_VAL_MASK(type, valp, maskp, matchvalp, matchmaskp) ({ \
2211 type matchmaskx = *(type *)(matchmaskp); \
2212 type matchvalx = *(type *)(matchvalp); \
2213 type maskx = *(type *)(maskp); \
2214 type valx = *(type *)(valp); \
2215 \
2216 (valx & maskx) == (matchvalx & matchmaskx) && !(maskx & (maskx ^ \
2217 matchmaskx)); \
2218})
2219
2220static bool cmp_val_mask(void *valp, void *maskp, void *matchvalp,
2221 void *matchmaskp, int size)
2222{
2223 bool same = false;
2224
2225 switch (size) {
2226 case sizeof(u8):
2227 same = SAME_VAL_MASK(u8, valp, maskp, matchvalp, matchmaskp);
2228 break;
2229 case sizeof(u16):
2230 same = SAME_VAL_MASK(u16, valp, maskp, matchvalp, matchmaskp);
2231 break;
2232 case sizeof(u32):
2233 same = SAME_VAL_MASK(u32, valp, maskp, matchvalp, matchmaskp);
2234 break;
2235 }
2236
2237 return same;
2238}
2239
2240static struct mlx5_fields fields[] = {
2241 OFFLOAD(DMAC_47_16, 4, eth.h_dest[0], 0, dmac_47_16),
2242 OFFLOAD(DMAC_15_0, 2, eth.h_dest[4], 0, dmac_15_0),
2243 OFFLOAD(SMAC_47_16, 4, eth.h_source[0], 0, smac_47_16),
2244 OFFLOAD(SMAC_15_0, 2, eth.h_source[4], 0, smac_15_0),
2245 OFFLOAD(ETHERTYPE, 2, eth.h_proto, 0, ethertype),
2246 OFFLOAD(FIRST_VID, 2, vlan.h_vlan_TCI, 0, first_vid),
2247
2248 OFFLOAD(IP_TTL, 1, ip4.ttl, 0, ttl_hoplimit),
2249 OFFLOAD(SIPV4, 4, ip4.saddr, 0, src_ipv4_src_ipv6.ipv4_layout.ipv4),
2250 OFFLOAD(DIPV4, 4, ip4.daddr, 0, dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2251
2252 OFFLOAD(SIPV6_127_96, 4, ip6.saddr.s6_addr32[0], 0,
2253 src_ipv4_src_ipv6.ipv6_layout.ipv6[0]),
2254 OFFLOAD(SIPV6_95_64, 4, ip6.saddr.s6_addr32[1], 0,
2255 src_ipv4_src_ipv6.ipv6_layout.ipv6[4]),
2256 OFFLOAD(SIPV6_63_32, 4, ip6.saddr.s6_addr32[2], 0,
2257 src_ipv4_src_ipv6.ipv6_layout.ipv6[8]),
2258 OFFLOAD(SIPV6_31_0, 4, ip6.saddr.s6_addr32[3], 0,
2259 src_ipv4_src_ipv6.ipv6_layout.ipv6[12]),
2260 OFFLOAD(DIPV6_127_96, 4, ip6.daddr.s6_addr32[0], 0,
2261 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[0]),
2262 OFFLOAD(DIPV6_95_64, 4, ip6.daddr.s6_addr32[1], 0,
2263 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[4]),
2264 OFFLOAD(DIPV6_63_32, 4, ip6.daddr.s6_addr32[2], 0,
2265 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[8]),
2266 OFFLOAD(DIPV6_31_0, 4, ip6.daddr.s6_addr32[3], 0,
2267 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[12]),
2268 OFFLOAD(IPV6_HOPLIMIT, 1, ip6.hop_limit, 0, ttl_hoplimit),
2269
2270 OFFLOAD(TCP_SPORT, 2, tcp.source, 0, tcp_sport),
2271 OFFLOAD(TCP_DPORT, 2, tcp.dest, 0, tcp_dport),
2272 OFFLOAD(TCP_FLAGS, 1, tcp.ack_seq, 5, tcp_flags),
2273
2274 OFFLOAD(UDP_SPORT, 2, udp.source, 0, udp_sport),
2275 OFFLOAD(UDP_DPORT, 2, udp.dest, 0, udp_dport),
2276};
2277
2278/* On input attr->max_mod_hdr_actions tells how many HW actions can be parsed at
2279 * max from the SW pedit action. On success, attr->num_mod_hdr_actions
2280 * says how many HW actions were actually parsed.
2281 */
2282static int offload_pedit_fields(struct pedit_headers_action *hdrs,
2283 struct mlx5e_tc_flow_parse_attr *parse_attr,
2284 u32 *action_flags,
2285 struct netlink_ext_ack *extack)
2286{
2287 struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
2288 void *headers_c = get_match_headers_criteria(*action_flags,
2289 &parse_attr->spec);
2290 void *headers_v = get_match_headers_value(*action_flags,
2291 &parse_attr->spec);
2292 int i, action_size, nactions, max_actions, first, last, next_z;
2293 void *s_masks_p, *a_masks_p, *vals_p;
2294 struct mlx5_fields *f;
2295 u8 cmd, field_bsize;
2296 u32 s_mask, a_mask;
2297 unsigned long mask;
2298 __be32 mask_be32;
2299 __be16 mask_be16;
2300 void *action;
2301
2302 set_masks = &hdrs[0].masks;
2303 add_masks = &hdrs[1].masks;
2304 set_vals = &hdrs[0].vals;
2305 add_vals = &hdrs[1].vals;
2306
2307 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
2308 action = parse_attr->mod_hdr_actions +
2309 parse_attr->num_mod_hdr_actions * action_size;
2310
2311 max_actions = parse_attr->max_mod_hdr_actions;
2312 nactions = parse_attr->num_mod_hdr_actions;
2313
2314 for (i = 0; i < ARRAY_SIZE(fields); i++) {
2315 bool skip;
2316
2317 f = &fields[i];
2318 /* avoid seeing bits set from previous iterations */
2319 s_mask = 0;
2320 a_mask = 0;
2321
2322 s_masks_p = (void *)set_masks + f->offset;
2323 a_masks_p = (void *)add_masks + f->offset;
2324
2325 memcpy(&s_mask, s_masks_p, f->size);
2326 memcpy(&a_mask, a_masks_p, f->size);
2327
2328 if (!s_mask && !a_mask) /* nothing to offload here */
2329 continue;
2330
2331 if (s_mask && a_mask) {
2332 NL_SET_ERR_MSG_MOD(extack,
2333 "can't set and add to the same HW field");
2334 printk(KERN_WARNING "mlx5: can't set and add to the same HW field (%x)\n", f->field);
2335 return -EOPNOTSUPP;
2336 }
2337
2338 if (nactions == max_actions) {
2339 NL_SET_ERR_MSG_MOD(extack,
2340 "too many pedit actions, can't offload");
2341 printk(KERN_WARNING "mlx5: parsed %d pedit actions, can't do more\n", nactions);
2342 return -EOPNOTSUPP;
2343 }
2344
2345 skip = false;
2346 if (s_mask) {
2347 void *match_mask = headers_c + f->match_offset;
2348 void *match_val = headers_v + f->match_offset;
2349
2350 cmd = MLX5_ACTION_TYPE_SET;
2351 mask = s_mask;
2352 vals_p = (void *)set_vals + f->offset;
2353 /* don't rewrite if we have a match on the same value */
2354 if (cmp_val_mask(vals_p, s_masks_p, match_val,
2355 match_mask, f->size))
2356 skip = true;
2357 /* clear to denote we consumed this field */
2358 memset(s_masks_p, 0, f->size);
2359 } else {
2360 u32 zero = 0;
2361
2362 cmd = MLX5_ACTION_TYPE_ADD;
2363 mask = a_mask;
2364 vals_p = (void *)add_vals + f->offset;
2365 /* add 0 is no change */
2366 if (!memcmp(vals_p, &zero, f->size))
2367 skip = true;
2368 /* clear to denote we consumed this field */
2369 memset(a_masks_p, 0, f->size);
2370 }
2371 if (skip)
2372 continue;
2373
2374 field_bsize = f->size * BITS_PER_BYTE;
2375
2376 if (field_bsize == 32) {
2377 mask_be32 = *(__be32 *)&mask;
2378 mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
2379 } else if (field_bsize == 16) {
2380 mask_be16 = *(__be16 *)&mask;
2381 mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
2382 }
2383
2384 first = find_first_bit(&mask, field_bsize);
2385 next_z = find_next_zero_bit(&mask, field_bsize, first);
2386 last = find_last_bit(&mask, field_bsize);
2387 if (first < next_z && next_z < last) {
2388 NL_SET_ERR_MSG_MOD(extack,
2389 "rewrite of few sub-fields isn't supported");
2390 printk(KERN_WARNING "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
2391 mask);
2392 return -EOPNOTSUPP;
2393 }
2394
2395 MLX5_SET(set_action_in, action, action_type, cmd);
2396 MLX5_SET(set_action_in, action, field, f->field);
2397
2398 if (cmd == MLX5_ACTION_TYPE_SET) {
2399 MLX5_SET(set_action_in, action, offset, first);
2400 /* length is num of bits to be written, zero means length of 32 */
2401 MLX5_SET(set_action_in, action, length, (last - first + 1));
2402 }
2403
2404 if (field_bsize == 32)
2405 MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
2406 else if (field_bsize == 16)
2407 MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
2408 else if (field_bsize == 8)
2409 MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
2410
2411 action += action_size;
2412 nactions++;
2413 }
2414
2415 parse_attr->num_mod_hdr_actions = nactions;
2416 return 0;
2417}
2418
2419static int mlx5e_flow_namespace_max_modify_action(struct mlx5_core_dev *mdev,
2420 int namespace)
2421{
2422 if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */
2423 return MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, max_modify_header_actions);
2424 else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */
2425 return MLX5_CAP_FLOWTABLE_NIC_RX(mdev, max_modify_header_actions);
2426}
2427
2428static int alloc_mod_hdr_actions(struct mlx5e_priv *priv,
2429 struct pedit_headers_action *hdrs,
2430 int namespace,
2431 struct mlx5e_tc_flow_parse_attr *parse_attr)
2432{
2433 int nkeys, action_size, max_actions;
2434
2435 nkeys = hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits +
2436 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits;
2437 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
2438
2439 max_actions = mlx5e_flow_namespace_max_modify_action(priv->mdev, namespace);
2440 /* can get up to crazingly 16 HW actions in 32 bits pedit SW key */
2441 max_actions = min(max_actions, nkeys * 16);
2442
2443 parse_attr->mod_hdr_actions = kcalloc(max_actions, action_size, GFP_KERNEL);
2444 if (!parse_attr->mod_hdr_actions)
2445 return -ENOMEM;
2446
2447 parse_attr->max_mod_hdr_actions = max_actions;
2448 return 0;
2449}
2450
2451static const struct pedit_headers zero_masks = {};
2452
2453static int parse_tc_pedit_action(struct mlx5e_priv *priv,
2454 const struct flow_action_entry *act, int namespace,
2455 struct mlx5e_tc_flow_parse_attr *parse_attr,
2456 struct pedit_headers_action *hdrs,
2457 struct netlink_ext_ack *extack)
2458{
2459 u8 cmd = (act->id == FLOW_ACTION_MANGLE) ? 0 : 1;
2460 int err = -EOPNOTSUPP;
2461 u32 mask, val, offset;
2462 u8 htype;
2463
2464 htype = act->mangle.htype;
2465 err = -EOPNOTSUPP; /* can't be all optimistic */
2466
2467 if (htype == FLOW_ACT_MANGLE_UNSPEC) {
2468 NL_SET_ERR_MSG_MOD(extack, "legacy pedit isn't offloaded");
2469 goto out_err;
2470 }
2471
2472 if (!mlx5e_flow_namespace_max_modify_action(priv->mdev, namespace)) {
2473 NL_SET_ERR_MSG_MOD(extack,
2474 "The pedit offload action is not supported");
2475 goto out_err;
2476 }
2477
2478 mask = act->mangle.mask;
2479 val = act->mangle.val;
2480 offset = act->mangle.offset;
2481
2482 err = set_pedit_val(htype, ~mask, val, offset, &hdrs[cmd]);
2483 if (err)
2484 goto out_err;
2485
2486 hdrs[cmd].pedits++;
2487
2488 return 0;
2489out_err:
2490 return err;
2491}
2492
2493static int alloc_tc_pedit_action(struct mlx5e_priv *priv, int namespace,
2494 struct mlx5e_tc_flow_parse_attr *parse_attr,
2495 struct pedit_headers_action *hdrs,
2496 u32 *action_flags,
2497 struct netlink_ext_ack *extack)
2498{
2499 struct pedit_headers *cmd_masks;
2500 int err;
2501 u8 cmd;
2502
2503 if (!parse_attr->mod_hdr_actions) {
2504 err = alloc_mod_hdr_actions(priv, hdrs, namespace, parse_attr);
2505 if (err)
2506 goto out_err;
2507 }
2508
2509 err = offload_pedit_fields(hdrs, parse_attr, action_flags, extack);
2510 if (err < 0)
2511 goto out_dealloc_parsed_actions;
2512
2513 for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
2514 cmd_masks = &hdrs[cmd].masks;
2515 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
2516 NL_SET_ERR_MSG_MOD(extack,
2517 "attempt to offload an unsupported field");
2518 netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd);
2519 print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
2520 16, 1, cmd_masks, sizeof(zero_masks), true);
2521 err = -EOPNOTSUPP;
2522 goto out_dealloc_parsed_actions;
2523 }
2524 }
2525
2526 return 0;
2527
2528out_dealloc_parsed_actions:
2529 kfree(parse_attr->mod_hdr_actions);
2530out_err:
2531 return err;
2532}
2533
2534static bool csum_offload_supported(struct mlx5e_priv *priv,
2535 u32 action,
2536 u32 update_flags,
2537 struct netlink_ext_ack *extack)
2538{
2539 u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP |
2540 TCA_CSUM_UPDATE_FLAG_UDP;
2541
2542 /* The HW recalcs checksums only if re-writing headers */
2543 if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) {
2544 NL_SET_ERR_MSG_MOD(extack,
2545 "TC csum action is only offloaded with pedit");
2546 netdev_warn(priv->netdev,
2547 "TC csum action is only offloaded with pedit\n");
2548 return false;
2549 }
2550
2551 if (update_flags & ~prot_flags) {
2552 NL_SET_ERR_MSG_MOD(extack,
2553 "can't offload TC csum action for some header/s");
2554 netdev_warn(priv->netdev,
2555 "can't offload TC csum action for some header/s - flags %#x\n",
2556 update_flags);
2557 return false;
2558 }
2559
2560 return true;
2561}
2562
2563struct ip_ttl_word {
2564 __u8 ttl;
2565 __u8 protocol;
2566 __sum16 check;
2567};
2568
2569struct ipv6_hoplimit_word {
2570 __be16 payload_len;
2571 __u8 nexthdr;
2572 __u8 hop_limit;
2573};
2574
2575static bool is_action_keys_supported(const struct flow_action_entry *act)
2576{
2577 u32 mask, offset;
2578 u8 htype;
2579
2580 htype = act->mangle.htype;
2581 offset = act->mangle.offset;
2582 mask = ~act->mangle.mask;
2583 /* For IPv4 & IPv6 header check 4 byte word,
2584 * to determine that modified fields
2585 * are NOT ttl & hop_limit only.
2586 */
2587 if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP4) {
2588 struct ip_ttl_word *ttl_word =
2589 (struct ip_ttl_word *)&mask;
2590
2591 if (offset != offsetof(struct iphdr, ttl) ||
2592 ttl_word->protocol ||
2593 ttl_word->check) {
2594 return true;
2595 }
2596 } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP6) {
2597 struct ipv6_hoplimit_word *hoplimit_word =
2598 (struct ipv6_hoplimit_word *)&mask;
2599
2600 if (offset != offsetof(struct ipv6hdr, payload_len) ||
2601 hoplimit_word->payload_len ||
2602 hoplimit_word->nexthdr) {
2603 return true;
2604 }
2605 }
2606 return false;
2607}
2608
2609static bool modify_header_match_supported(struct mlx5_flow_spec *spec,
2610 struct flow_action *flow_action,
2611 u32 actions,
2612 struct netlink_ext_ack *extack)
2613{
2614 const struct flow_action_entry *act;
2615 bool modify_ip_header;
2616 void *headers_v;
2617 u16 ethertype;
2618 u8 ip_proto;
2619 int i;
2620
2621 headers_v = get_match_headers_value(actions, spec);
2622 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
2623
2624 /* for non-IP we only re-write MACs, so we're okay */
2625 if (ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
2626 goto out_ok;
2627
2628 modify_ip_header = false;
2629 flow_action_for_each(i, act, flow_action) {
2630 if (act->id != FLOW_ACTION_MANGLE &&
2631 act->id != FLOW_ACTION_ADD)
2632 continue;
2633
2634 if (is_action_keys_supported(act)) {
2635 modify_ip_header = true;
2636 break;
2637 }
2638 }
2639
2640 ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
2641 if (modify_ip_header && ip_proto != IPPROTO_TCP &&
2642 ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) {
2643 NL_SET_ERR_MSG_MOD(extack,
2644 "can't offload re-write of non TCP/UDP");
2645 pr_info("can't offload re-write of ip proto %d\n", ip_proto);
2646 return false;
2647 }
2648
2649out_ok:
2650 return true;
2651}
2652
2653static bool actions_match_supported(struct mlx5e_priv *priv,
2654 struct flow_action *flow_action,
2655 struct mlx5e_tc_flow_parse_attr *parse_attr,
2656 struct mlx5e_tc_flow *flow,
2657 struct netlink_ext_ack *extack)
2658{
2659 u32 actions;
2660
2661 if (mlx5e_is_eswitch_flow(flow))
2662 actions = flow->esw_attr->action;
2663 else
2664 actions = flow->nic_attr->action;
2665
2666 if (flow_flag_test(flow, EGRESS) &&
2667 !((actions & MLX5_FLOW_CONTEXT_ACTION_DECAP) ||
2668 (actions & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) ||
2669 (actions & MLX5_FLOW_CONTEXT_ACTION_DROP)))
2670 return false;
2671
2672 if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2673 return modify_header_match_supported(&parse_attr->spec,
2674 flow_action, actions,
2675 extack);
2676
2677 return true;
2678}
2679
2680static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
2681{
2682 struct mlx5_core_dev *fmdev, *pmdev;
2683 u64 fsystem_guid, psystem_guid;
2684
2685 fmdev = priv->mdev;
2686 pmdev = peer_priv->mdev;
2687
2688 fsystem_guid = mlx5_query_nic_system_image_guid(fmdev);
2689 psystem_guid = mlx5_query_nic_system_image_guid(pmdev);
2690
2691 return (fsystem_guid == psystem_guid);
2692}
2693
2694static int add_vlan_rewrite_action(struct mlx5e_priv *priv, int namespace,
2695 const struct flow_action_entry *act,
2696 struct mlx5e_tc_flow_parse_attr *parse_attr,
2697 struct pedit_headers_action *hdrs,
2698 u32 *action, struct netlink_ext_ack *extack)
2699{
2700 u16 mask16 = VLAN_VID_MASK;
2701 u16 val16 = act->vlan.vid & VLAN_VID_MASK;
2702 const struct flow_action_entry pedit_act = {
2703 .id = FLOW_ACTION_MANGLE,
2704 .mangle.htype = FLOW_ACT_MANGLE_HDR_TYPE_ETH,
2705 .mangle.offset = offsetof(struct vlan_ethhdr, h_vlan_TCI),
2706 .mangle.mask = ~(u32)be16_to_cpu(*(__be16 *)&mask16),
2707 .mangle.val = (u32)be16_to_cpu(*(__be16 *)&val16),
2708 };
2709 u8 match_prio_mask, match_prio_val;
2710 void *headers_c, *headers_v;
2711 int err;
2712
2713 headers_c = get_match_headers_criteria(*action, &parse_attr->spec);
2714 headers_v = get_match_headers_value(*action, &parse_attr->spec);
2715
2716 if (!(MLX5_GET(fte_match_set_lyr_2_4, headers_c, cvlan_tag) &&
2717 MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag))) {
2718 NL_SET_ERR_MSG_MOD(extack,
2719 "VLAN rewrite action must have VLAN protocol match");
2720 return -EOPNOTSUPP;
2721 }
2722
2723 match_prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
2724 match_prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
2725 if (act->vlan.prio != (match_prio_val & match_prio_mask)) {
2726 NL_SET_ERR_MSG_MOD(extack,
2727 "Changing VLAN prio is not supported");
2728 return -EOPNOTSUPP;
2729 }
2730
2731 err = parse_tc_pedit_action(priv, &pedit_act, namespace, parse_attr,
2732 hdrs, NULL);
2733 *action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2734
2735 return err;
2736}
2737
2738static int
2739add_vlan_prio_tag_rewrite_action(struct mlx5e_priv *priv,
2740 struct mlx5e_tc_flow_parse_attr *parse_attr,
2741 struct pedit_headers_action *hdrs,
2742 u32 *action, struct netlink_ext_ack *extack)
2743{
2744 const struct flow_action_entry prio_tag_act = {
2745 .vlan.vid = 0,
2746 .vlan.prio =
2747 MLX5_GET(fte_match_set_lyr_2_4,
2748 get_match_headers_value(*action,
2749 &parse_attr->spec),
2750 first_prio) &
2751 MLX5_GET(fte_match_set_lyr_2_4,
2752 get_match_headers_criteria(*action,
2753 &parse_attr->spec),
2754 first_prio),
2755 };
2756
2757 return add_vlan_rewrite_action(priv, MLX5_FLOW_NAMESPACE_FDB,
2758 &prio_tag_act, parse_attr, hdrs, action,
2759 extack);
2760}
2761
2762static int parse_tc_nic_actions(struct mlx5e_priv *priv,
2763 struct flow_action *flow_action,
2764 struct mlx5e_tc_flow_parse_attr *parse_attr,
2765 struct mlx5e_tc_flow *flow,
2766 struct netlink_ext_ack *extack)
2767{
2768 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
2769 struct pedit_headers_action hdrs[2] = {};
2770 const struct flow_action_entry *act;
2771 u32 action = 0;
2772 int err, i;
2773
2774 if (!flow_action_has_entries(flow_action))
2775 return -EINVAL;
2776
2777 attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
2778
2779 flow_action_for_each(i, act, flow_action) {
2780 switch (act->id) {
2781 case FLOW_ACTION_DROP:
2782 action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
2783 if (MLX5_CAP_FLOWTABLE(priv->mdev,
2784 flow_table_properties_nic_receive.flow_counter))
2785 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
2786 break;
2787 case FLOW_ACTION_MANGLE:
2788 case FLOW_ACTION_ADD:
2789 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_KERNEL,
2790 parse_attr, hdrs, extack);
2791 if (err)
2792 return err;
2793
2794 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR |
2795 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2796 break;
2797 case FLOW_ACTION_VLAN_MANGLE:
2798 err = add_vlan_rewrite_action(priv,
2799 MLX5_FLOW_NAMESPACE_KERNEL,
2800 act, parse_attr, hdrs,
2801 &action, extack);
2802 if (err)
2803 return err;
2804
2805 break;
2806 case FLOW_ACTION_CSUM:
2807 if (csum_offload_supported(priv, action,
2808 act->csum_flags,
2809 extack))
2810 break;
2811
2812 return -EOPNOTSUPP;
2813 case FLOW_ACTION_REDIRECT: {
2814 struct net_device *peer_dev = act->dev;
2815
2816 if (priv->netdev->netdev_ops == peer_dev->netdev_ops &&
2817 same_hw_devs(priv, netdev_priv(peer_dev))) {
2818 parse_attr->mirred_ifindex[0] = peer_dev->ifindex;
2819 flow_flag_set(flow, HAIRPIN);
2820 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2821 MLX5_FLOW_CONTEXT_ACTION_COUNT;
2822 } else {
2823 NL_SET_ERR_MSG_MOD(extack,
2824 "device is not on same HW, can't offload");
2825 netdev_warn(priv->netdev, "device %s not on same HW, can't offload\n",
2826 peer_dev->name);
2827 return -EINVAL;
2828 }
2829 }
2830 break;
2831 case FLOW_ACTION_MARK: {
2832 u32 mark = act->mark;
2833
2834 if (mark & ~MLX5E_TC_FLOW_ID_MASK) {
2835 NL_SET_ERR_MSG_MOD(extack,
2836 "Bad flow mark - only 16 bit is supported");
2837 return -EINVAL;
2838 }
2839
2840 attr->flow_tag = mark;
2841 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2842 }
2843 break;
2844 default:
2845 NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
2846 return -EOPNOTSUPP;
2847 }
2848 }
2849
2850 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
2851 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
2852 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_KERNEL,
2853 parse_attr, hdrs, &action, extack);
2854 if (err)
2855 return err;
2856 /* in case all pedit actions are skipped, remove the MOD_HDR
2857 * flag.
2858 */
2859 if (parse_attr->num_mod_hdr_actions == 0) {
2860 action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2861 kfree(parse_attr->mod_hdr_actions);
2862 }
2863 }
2864
2865 attr->action = action;
2866 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
2867 return -EOPNOTSUPP;
2868
2869 return 0;
2870}
2871
2872struct encap_key {
2873 const struct ip_tunnel_key *ip_tun_key;
2874 struct mlx5e_tc_tunnel *tc_tunnel;
2875};
2876
2877static inline int cmp_encap_info(struct encap_key *a,
2878 struct encap_key *b)
2879{
2880 return memcmp(a->ip_tun_key, b->ip_tun_key, sizeof(*a->ip_tun_key)) ||
2881 a->tc_tunnel->tunnel_type != b->tc_tunnel->tunnel_type;
2882}
2883
2884static inline int hash_encap_info(struct encap_key *key)
2885{
2886 return jhash(key->ip_tun_key, sizeof(*key->ip_tun_key),
2887 key->tc_tunnel->tunnel_type);
2888}
2889
2890
2891static bool is_merged_eswitch_dev(struct mlx5e_priv *priv,
2892 struct net_device *peer_netdev)
2893{
2894 struct mlx5e_priv *peer_priv;
2895
2896 peer_priv = netdev_priv(peer_netdev);
2897
2898 return (MLX5_CAP_ESW(priv->mdev, merged_eswitch) &&
2899 mlx5e_eswitch_rep(priv->netdev) &&
2900 mlx5e_eswitch_rep(peer_netdev) &&
2901 same_hw_devs(priv, peer_priv));
2902}
2903
2904
2905
2906bool mlx5e_encap_take(struct mlx5e_encap_entry *e)
2907{
2908 return refcount_inc_not_zero(&e->refcnt);
2909}
2910
2911static struct mlx5e_encap_entry *
2912mlx5e_encap_get(struct mlx5e_priv *priv, struct encap_key *key,
2913 uintptr_t hash_key)
2914{
2915 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2916 struct mlx5e_encap_entry *e;
2917 struct encap_key e_key;
2918
2919 hash_for_each_possible_rcu(esw->offloads.encap_tbl, e,
2920 encap_hlist, hash_key) {
2921 e_key.ip_tun_key = &e->tun_info->key;
2922 e_key.tc_tunnel = e->tunnel;
2923 if (!cmp_encap_info(&e_key, key) &&
2924 mlx5e_encap_take(e))
2925 return e;
2926 }
2927
2928 return NULL;
2929}
2930
2931static int mlx5e_attach_encap(struct mlx5e_priv *priv,
2932 struct mlx5e_tc_flow *flow,
2933 struct net_device *mirred_dev,
2934 int out_index,
2935 struct netlink_ext_ack *extack,
2936 struct net_device **encap_dev,
2937 bool *encap_valid)
2938{
2939 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2940 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
2941 struct mlx5e_tc_flow_parse_attr *parse_attr;
2942 const struct ip_tunnel_info *tun_info;
2943 struct encap_key key;
2944 struct mlx5e_encap_entry *e;
2945 unsigned short family;
2946 uintptr_t hash_key;
2947 int err = 0;
2948
2949 parse_attr = attr->parse_attr;
2950 tun_info = parse_attr->tun_info[out_index];
2951 family = ip_tunnel_info_af(tun_info);
2952 key.ip_tun_key = &tun_info->key;
2953 key.tc_tunnel = mlx5e_get_tc_tun(mirred_dev);
2954 if (!key.tc_tunnel) {
2955 NL_SET_ERR_MSG_MOD(extack, "Unsupported tunnel");
2956 return -EOPNOTSUPP;
2957 }
2958
2959 hash_key = hash_encap_info(&key);
2960
2961 mutex_lock(&esw->offloads.encap_tbl_lock);
2962 e = mlx5e_encap_get(priv, &key, hash_key);
2963
2964 /* must verify if encap is valid or not */
2965 if (e) {
2966 mutex_unlock(&esw->offloads.encap_tbl_lock);
2967 wait_for_completion(&e->res_ready);
2968
2969 /* Protect against concurrent neigh update. */
2970 mutex_lock(&esw->offloads.encap_tbl_lock);
2971 if (e->compl_result < 0) {
2972 err = -EREMOTEIO;
2973 goto out_err;
2974 }
2975 goto attach_flow;
2976 }
2977
2978 e = kzalloc(sizeof(*e), GFP_KERNEL);
2979 if (!e) {
2980 err = -ENOMEM;
2981 goto out_err;
2982 }
2983
2984 refcount_set(&e->refcnt, 1);
2985 init_completion(&e->res_ready);
2986
2987 e->tun_info = tun_info;
2988 err = mlx5e_tc_tun_init_encap_attr(mirred_dev, priv, e, extack);
2989 if (err) {
2990 kfree(e);
2991 e = NULL;
2992 goto out_err;
2993 }
2994
2995 INIT_LIST_HEAD(&e->flows);
2996 hash_add_rcu(esw->offloads.encap_tbl, &e->encap_hlist, hash_key);
2997 mutex_unlock(&esw->offloads.encap_tbl_lock);
2998
2999 if (family == AF_INET)
3000 err = mlx5e_tc_tun_create_header_ipv4(priv, mirred_dev, e);
3001 else if (family == AF_INET6)
3002 err = mlx5e_tc_tun_create_header_ipv6(priv, mirred_dev, e);
3003
3004 /* Protect against concurrent neigh update. */
3005 mutex_lock(&esw->offloads.encap_tbl_lock);
3006 complete_all(&e->res_ready);
3007 if (err) {
3008 e->compl_result = err;
3009 goto out_err;
3010 }
3011 e->compl_result = 1;
3012
3013attach_flow:
3014 flow->encaps[out_index].e = e;
3015 list_add(&flow->encaps[out_index].list, &e->flows);
3016 flow->encaps[out_index].index = out_index;
3017 *encap_dev = e->out_dev;
3018 if (e->flags & MLX5_ENCAP_ENTRY_VALID) {
3019 attr->dests[out_index].encap_id = e->encap_id;
3020 attr->dests[out_index].flags |= MLX5_ESW_DEST_ENCAP_VALID;
3021 *encap_valid = true;
3022 } else {
3023 *encap_valid = false;
3024 }
3025 mutex_unlock(&esw->offloads.encap_tbl_lock);
3026
3027 return err;
3028
3029out_err:
3030 mutex_unlock(&esw->offloads.encap_tbl_lock);
3031 if (e)
3032 mlx5e_encap_put(priv, e);
3033 return err;
3034}
3035
3036static int parse_tc_vlan_action(struct mlx5e_priv *priv,
3037 const struct flow_action_entry *act,
3038 struct mlx5_esw_flow_attr *attr,
3039 u32 *action)
3040{
3041 u8 vlan_idx = attr->total_vlan;
3042
3043 if (vlan_idx >= MLX5_FS_VLAN_DEPTH)
3044 return -EOPNOTSUPP;
3045
3046 switch (act->id) {
3047 case FLOW_ACTION_VLAN_POP:
3048 if (vlan_idx) {
3049 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
3050 MLX5_FS_VLAN_DEPTH))
3051 return -EOPNOTSUPP;
3052
3053 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2;
3054 } else {
3055 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3056 }
3057 break;
3058 case FLOW_ACTION_VLAN_PUSH:
3059 attr->vlan_vid[vlan_idx] = act->vlan.vid;
3060 attr->vlan_prio[vlan_idx] = act->vlan.prio;
3061 attr->vlan_proto[vlan_idx] = act->vlan.proto;
3062 if (!attr->vlan_proto[vlan_idx])
3063 attr->vlan_proto[vlan_idx] = htons(ETH_P_8021Q);
3064
3065 if (vlan_idx) {
3066 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
3067 MLX5_FS_VLAN_DEPTH))
3068 return -EOPNOTSUPP;
3069
3070 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2;
3071 } else {
3072 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev, 1) &&
3073 (act->vlan.proto != htons(ETH_P_8021Q) ||
3074 act->vlan.prio))
3075 return -EOPNOTSUPP;
3076
3077 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
3078 }
3079 break;
3080 default:
3081 return -EINVAL;
3082 }
3083
3084 attr->total_vlan = vlan_idx + 1;
3085
3086 return 0;
3087}
3088
3089static int add_vlan_push_action(struct mlx5e_priv *priv,
3090 struct mlx5_esw_flow_attr *attr,
3091 struct net_device **out_dev,
3092 u32 *action)
3093{
3094 struct net_device *vlan_dev = *out_dev;
3095 struct flow_action_entry vlan_act = {
3096 .id = FLOW_ACTION_VLAN_PUSH,
3097 .vlan.vid = vlan_dev_vlan_id(vlan_dev),
3098 .vlan.proto = vlan_dev_vlan_proto(vlan_dev),
3099 .vlan.prio = 0,
3100 };
3101 int err;
3102
3103 err = parse_tc_vlan_action(priv, &vlan_act, attr, action);
3104 if (err)
3105 return err;
3106
3107 *out_dev = dev_get_by_index_rcu(dev_net(vlan_dev),
3108 dev_get_iflink(vlan_dev));
3109 if (is_vlan_dev(*out_dev))
3110 err = add_vlan_push_action(priv, attr, out_dev, action);
3111
3112 return err;
3113}
3114
3115static int add_vlan_pop_action(struct mlx5e_priv *priv,
3116 struct mlx5_esw_flow_attr *attr,
3117 u32 *action)
3118{
3119 int nest_level = vlan_get_encap_level(attr->parse_attr->filter_dev);
3120 struct flow_action_entry vlan_act = {
3121 .id = FLOW_ACTION_VLAN_POP,
3122 };
3123 int err = 0;
3124
3125 while (nest_level--) {
3126 err = parse_tc_vlan_action(priv, &vlan_act, attr, action);
3127 if (err)
3128 return err;
3129 }
3130
3131 return err;
3132}
3133
3134bool mlx5e_is_valid_eswitch_fwd_dev(struct mlx5e_priv *priv,
3135 struct net_device *out_dev)
3136{
3137 if (is_merged_eswitch_dev(priv, out_dev))
3138 return true;
3139
3140 return mlx5e_eswitch_rep(out_dev) &&
3141 same_hw_devs(priv, netdev_priv(out_dev));
3142}
3143
3144static int parse_tc_fdb_actions(struct mlx5e_priv *priv,
3145 struct flow_action *flow_action,
3146 struct mlx5e_tc_flow *flow,
3147 struct netlink_ext_ack *extack)
3148{
3149 struct pedit_headers_action hdrs[2] = {};
3150 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3151 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
3152 struct mlx5e_tc_flow_parse_attr *parse_attr = attr->parse_attr;
3153 struct mlx5e_rep_priv *rpriv = priv->ppriv;
3154 const struct ip_tunnel_info *info = NULL;
3155 const struct flow_action_entry *act;
3156 bool encap = false;
3157 u32 action = 0;
3158 int err, i;
3159
3160 if (!flow_action_has_entries(flow_action))
3161 return -EINVAL;
3162
3163 flow_action_for_each(i, act, flow_action) {
3164 switch (act->id) {
3165 case FLOW_ACTION_DROP:
3166 action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
3167 MLX5_FLOW_CONTEXT_ACTION_COUNT;
3168 break;
3169 case FLOW_ACTION_MANGLE:
3170 case FLOW_ACTION_ADD:
3171 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_FDB,
3172 parse_attr, hdrs, extack);
3173 if (err)
3174 return err;
3175
3176 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
3177 attr->split_count = attr->out_count;
3178 break;
3179 case FLOW_ACTION_CSUM:
3180 if (csum_offload_supported(priv, action,
3181 act->csum_flags, extack))
3182 break;
3183
3184 return -EOPNOTSUPP;
3185 case FLOW_ACTION_REDIRECT:
3186 case FLOW_ACTION_MIRRED: {
3187 struct mlx5e_priv *out_priv;
3188 struct net_device *out_dev;
3189
3190 out_dev = act->dev;
3191 if (!out_dev) {
3192 /* out_dev is NULL when filters with
3193 * non-existing mirred device are replayed to
3194 * the driver.
3195 */
3196 return -EINVAL;
3197 }
3198
3199 if (attr->out_count >= MLX5_MAX_FLOW_FWD_VPORTS) {
3200 NL_SET_ERR_MSG_MOD(extack,
3201 "can't support more output ports, can't offload forwarding");
3202 pr_err("can't support more than %d output ports, can't offload forwarding\n",
3203 attr->out_count);
3204 return -EOPNOTSUPP;
3205 }
3206
3207 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3208 MLX5_FLOW_CONTEXT_ACTION_COUNT;
3209 if (netdev_port_same_parent_id(priv->netdev, out_dev)) {
3210 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3211 struct net_device *uplink_dev = mlx5_eswitch_uplink_get_proto_dev(esw, REP_ETH);
3212 struct net_device *uplink_upper;
3213
3214 rcu_read_lock();
3215 uplink_upper =
3216 netdev_master_upper_dev_get_rcu(uplink_dev);
3217 if (uplink_upper &&
3218 netif_is_lag_master(uplink_upper) &&
3219 uplink_upper == out_dev)
3220 out_dev = uplink_dev;
3221 rcu_read_unlock();
3222
3223 if (is_vlan_dev(out_dev)) {
3224 err = add_vlan_push_action(priv, attr,
3225 &out_dev,
3226 &action);
3227 if (err)
3228 return err;
3229 }
3230
3231 if (is_vlan_dev(parse_attr->filter_dev)) {
3232 err = add_vlan_pop_action(priv, attr,
3233 &action);
3234 if (err)
3235 return err;
3236 }
3237
3238 if (!mlx5e_is_valid_eswitch_fwd_dev(priv, out_dev)) {
3239 NL_SET_ERR_MSG_MOD(extack,
3240 "devices are not on same switch HW, can't offload forwarding");
3241 pr_err("devices %s %s not on same switch HW, can't offload forwarding\n",
3242 priv->netdev->name, out_dev->name);
3243 return -EOPNOTSUPP;
3244 }
3245
3246 out_priv = netdev_priv(out_dev);
3247 rpriv = out_priv->ppriv;
3248 attr->dests[attr->out_count].rep = rpriv->rep;
3249 attr->dests[attr->out_count].mdev = out_priv->mdev;
3250 attr->out_count++;
3251 } else if (encap) {
3252 parse_attr->mirred_ifindex[attr->out_count] =
3253 out_dev->ifindex;
3254 parse_attr->tun_info[attr->out_count] = info;
3255 encap = false;
3256 attr->dests[attr->out_count].flags |=
3257 MLX5_ESW_DEST_ENCAP;
3258 attr->out_count++;
3259 /* attr->dests[].rep is resolved when we
3260 * handle encap
3261 */
3262 } else if (parse_attr->filter_dev != priv->netdev) {
3263 /* All mlx5 devices are called to configure
3264 * high level device filters. Therefore, the
3265 * *attempt* to install a filter on invalid
3266 * eswitch should not trigger an explicit error
3267 */
3268 return -EINVAL;
3269 } else {
3270 NL_SET_ERR_MSG_MOD(extack,
3271 "devices are not on same switch HW, can't offload forwarding");
3272 pr_err("devices %s %s not on same switch HW, can't offload forwarding\n",
3273 priv->netdev->name, out_dev->name);
3274 return -EINVAL;
3275 }
3276 }
3277 break;
3278 case FLOW_ACTION_TUNNEL_ENCAP:
3279 info = act->tunnel;
3280 if (info)
3281 encap = true;
3282 else
3283 return -EOPNOTSUPP;
3284
3285 break;
3286 case FLOW_ACTION_VLAN_PUSH:
3287 case FLOW_ACTION_VLAN_POP:
3288 if (act->id == FLOW_ACTION_VLAN_PUSH &&
3289 (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP)) {
3290 /* Replace vlan pop+push with vlan modify */
3291 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3292 err = add_vlan_rewrite_action(priv,
3293 MLX5_FLOW_NAMESPACE_FDB,
3294 act, parse_attr, hdrs,
3295 &action, extack);
3296 } else {
3297 err = parse_tc_vlan_action(priv, act, attr, &action);
3298 }
3299 if (err)
3300 return err;
3301
3302 attr->split_count = attr->out_count;
3303 break;
3304 case FLOW_ACTION_VLAN_MANGLE:
3305 err = add_vlan_rewrite_action(priv,
3306 MLX5_FLOW_NAMESPACE_FDB,
3307 act, parse_attr, hdrs,
3308 &action, extack);
3309 if (err)
3310 return err;
3311
3312 attr->split_count = attr->out_count;
3313 break;
3314 case FLOW_ACTION_TUNNEL_DECAP:
3315 action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
3316 break;
3317 case FLOW_ACTION_GOTO: {
3318 u32 dest_chain = act->chain_index;
3319 u32 max_chain = mlx5_eswitch_get_chain_range(esw);
3320
3321 if (dest_chain <= attr->chain) {
3322 NL_SET_ERR_MSG(extack, "Goto earlier chain isn't supported");
3323 return -EOPNOTSUPP;
3324 }
3325 if (dest_chain > max_chain) {
3326 NL_SET_ERR_MSG(extack, "Requested destination chain is out of supported range");
3327 return -EOPNOTSUPP;
3328 }
3329 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
3330 attr->dest_chain = dest_chain;
3331 break;
3332 }
3333 default:
3334 NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
3335 return -EOPNOTSUPP;
3336 }
3337 }
3338
3339 if (MLX5_CAP_GEN(esw->dev, prio_tag_required) &&
3340 action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) {
3341 /* For prio tag mode, replace vlan pop with rewrite vlan prio
3342 * tag rewrite.
3343 */
3344 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3345 err = add_vlan_prio_tag_rewrite_action(priv, parse_attr, hdrs,
3346 &action, extack);
3347 if (err)
3348 return err;
3349 }
3350
3351 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
3352 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
3353 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_FDB,
3354 parse_attr, hdrs, &action, extack);
3355 if (err)
3356 return err;
3357 /* in case all pedit actions are skipped, remove the MOD_HDR
3358 * flag. we might have set split_count either by pedit or
3359 * pop/push. if there is no pop/push either, reset it too.
3360 */
3361 if (parse_attr->num_mod_hdr_actions == 0) {
3362 action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
3363 kfree(parse_attr->mod_hdr_actions);
3364 if (!((action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) ||
3365 (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH)))
3366 attr->split_count = 0;
3367 }
3368 }
3369
3370 attr->action = action;
3371 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
3372 return -EOPNOTSUPP;
3373
3374 if (attr->dest_chain) {
3375 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
3376 NL_SET_ERR_MSG(extack, "Mirroring goto chain rules isn't supported");
3377 return -EOPNOTSUPP;
3378 }
3379 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3380 }
3381
3382 if (attr->split_count > 0 && !mlx5_esw_has_fwd_fdb(priv->mdev)) {
3383 NL_SET_ERR_MSG_MOD(extack,
3384 "current firmware doesn't support split rule for port mirroring");
3385 netdev_warn_once(priv->netdev, "current firmware doesn't support split rule for port mirroring\n");
3386 return -EOPNOTSUPP;
3387 }
3388
3389 return 0;
3390}
3391
3392static void get_flags(int flags, unsigned long *flow_flags)
3393{
3394 unsigned long __flow_flags = 0;
3395
3396 if (flags & MLX5_TC_FLAG(INGRESS))
3397 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_INGRESS);
3398 if (flags & MLX5_TC_FLAG(EGRESS))
3399 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_EGRESS);
3400
3401 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD))
3402 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
3403 if (flags & MLX5_TC_FLAG(NIC_OFFLOAD))
3404 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
3405
3406 *flow_flags = __flow_flags;
3407}
3408
3409static const struct rhashtable_params tc_ht_params = {
3410 .head_offset = offsetof(struct mlx5e_tc_flow, node),
3411 .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
3412 .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
3413 .automatic_shrinking = true,
3414};
3415
3416static struct rhashtable *get_tc_ht(struct mlx5e_priv *priv,
3417 unsigned long flags)
3418{
3419 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3420 struct mlx5e_rep_priv *uplink_rpriv;
3421
3422 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD)) {
3423 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
3424 return &uplink_rpriv->uplink_priv.tc_ht;
3425 } else /* NIC offload */
3426 return &priv->fs.tc.ht;
3427}
3428
3429static bool is_peer_flow_needed(struct mlx5e_tc_flow *flow)
3430{
3431 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
3432 bool is_rep_ingress = attr->in_rep->vport != MLX5_VPORT_UPLINK &&
3433 flow_flag_test(flow, INGRESS);
3434 bool act_is_encap = !!(attr->action &
3435 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT);
3436 bool esw_paired = mlx5_devcom_is_paired(attr->in_mdev->priv.devcom,
3437 MLX5_DEVCOM_ESW_OFFLOADS);
3438
3439 if (!esw_paired)
3440 return false;
3441
3442 if ((mlx5_lag_is_sriov(attr->in_mdev) ||
3443 mlx5_lag_is_multipath(attr->in_mdev)) &&
3444 (is_rep_ingress || act_is_encap))
3445 return true;
3446
3447 return false;
3448}
3449
3450static int
3451mlx5e_alloc_flow(struct mlx5e_priv *priv, int attr_size,
3452 struct flow_cls_offload *f, unsigned long flow_flags,
3453 struct mlx5e_tc_flow_parse_attr **__parse_attr,
3454 struct mlx5e_tc_flow **__flow)
3455{
3456 struct mlx5e_tc_flow_parse_attr *parse_attr;
3457 struct mlx5e_tc_flow *flow;
3458 int out_index, err;
3459
3460 flow = kzalloc(sizeof(*flow) + attr_size, GFP_KERNEL);
3461 parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
3462 if (!parse_attr || !flow) {
3463 err = -ENOMEM;
3464 goto err_free;
3465 }
3466
3467 flow->cookie = f->cookie;
3468 flow->flags = flow_flags;
3469 flow->priv = priv;
3470 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
3471 INIT_LIST_HEAD(&flow->encaps[out_index].list);
3472 INIT_LIST_HEAD(&flow->mod_hdr);
3473 INIT_LIST_HEAD(&flow->hairpin);
3474 refcount_set(&flow->refcnt, 1);
3475
3476 *__flow = flow;
3477 *__parse_attr = parse_attr;
3478
3479 return 0;
3480
3481err_free:
3482 kfree(flow);
3483 kvfree(parse_attr);
3484 return err;
3485}
3486
3487static void
3488mlx5e_flow_esw_attr_init(struct mlx5_esw_flow_attr *esw_attr,
3489 struct mlx5e_priv *priv,
3490 struct mlx5e_tc_flow_parse_attr *parse_attr,
3491 struct flow_cls_offload *f,
3492 struct mlx5_eswitch_rep *in_rep,
3493 struct mlx5_core_dev *in_mdev)
3494{
3495 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3496
3497 esw_attr->parse_attr = parse_attr;
3498 esw_attr->chain = f->common.chain_index;
3499 esw_attr->prio = f->common.prio;
3500
3501 esw_attr->in_rep = in_rep;
3502 esw_attr->in_mdev = in_mdev;
3503
3504 if (MLX5_CAP_ESW(esw->dev, counter_eswitch_affinity) ==
3505 MLX5_COUNTER_SOURCE_ESWITCH)
3506 esw_attr->counter_dev = in_mdev;
3507 else
3508 esw_attr->counter_dev = priv->mdev;
3509}
3510
3511static struct mlx5e_tc_flow *
3512__mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
3513 struct flow_cls_offload *f,
3514 unsigned long flow_flags,
3515 struct net_device *filter_dev,
3516 struct mlx5_eswitch_rep *in_rep,
3517 struct mlx5_core_dev *in_mdev)
3518{
3519 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
3520 struct netlink_ext_ack *extack = f->common.extack;
3521 struct mlx5e_tc_flow_parse_attr *parse_attr;
3522 struct mlx5e_tc_flow *flow;
3523 int attr_size, err;
3524
3525 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
3526 attr_size = sizeof(struct mlx5_esw_flow_attr);
3527 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
3528 &parse_attr, &flow);
3529 if (err)
3530 goto out;
3531
3532 parse_attr->filter_dev = filter_dev;
3533 mlx5e_flow_esw_attr_init(flow->esw_attr,
3534 priv, parse_attr,
3535 f, in_rep, in_mdev);
3536
3537 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
3538 f, filter_dev);
3539 if (err)
3540 goto err_free;
3541
3542 err = parse_tc_fdb_actions(priv, &rule->action, flow, extack);
3543 if (err)
3544 goto err_free;
3545
3546 err = mlx5e_tc_add_fdb_flow(priv, flow, extack);
3547 if (err) {
3548 if (!(err == -ENETUNREACH && mlx5_lag_is_multipath(in_mdev)))
3549 goto err_free;
3550
3551 add_unready_flow(flow);
3552 }
3553
3554 return flow;
3555
3556err_free:
3557 mlx5e_flow_put(priv, flow);
3558out:
3559 return ERR_PTR(err);
3560}
3561
3562static int mlx5e_tc_add_fdb_peer_flow(struct flow_cls_offload *f,
3563 struct mlx5e_tc_flow *flow,
3564 unsigned long flow_flags)
3565{
3566 struct mlx5e_priv *priv = flow->priv, *peer_priv;
3567 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch, *peer_esw;
3568 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
3569 struct mlx5e_tc_flow_parse_attr *parse_attr;
3570 struct mlx5e_rep_priv *peer_urpriv;
3571 struct mlx5e_tc_flow *peer_flow;
3572 struct mlx5_core_dev *in_mdev;
3573 int err = 0;
3574
3575 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
3576 if (!peer_esw)
3577 return -ENODEV;
3578
3579 peer_urpriv = mlx5_eswitch_get_uplink_priv(peer_esw, REP_ETH);
3580 peer_priv = netdev_priv(peer_urpriv->netdev);
3581
3582 /* in_mdev is assigned of which the packet originated from.
3583 * So packets redirected to uplink use the same mdev of the
3584 * original flow and packets redirected from uplink use the
3585 * peer mdev.
3586 */
3587 if (flow->esw_attr->in_rep->vport == MLX5_VPORT_UPLINK)
3588 in_mdev = peer_priv->mdev;
3589 else
3590 in_mdev = priv->mdev;
3591
3592 parse_attr = flow->esw_attr->parse_attr;
3593 peer_flow = __mlx5e_add_fdb_flow(peer_priv, f, flow_flags,
3594 parse_attr->filter_dev,
3595 flow->esw_attr->in_rep, in_mdev);
3596 if (IS_ERR(peer_flow)) {
3597 err = PTR_ERR(peer_flow);
3598 goto out;
3599 }
3600
3601 flow->peer_flow = peer_flow;
3602 flow_flag_set(flow, DUP);
3603 mutex_lock(&esw->offloads.peer_mutex);
3604 list_add_tail(&flow->peer, &esw->offloads.peer_flows);
3605 mutex_unlock(&esw->offloads.peer_mutex);
3606
3607out:
3608 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
3609 return err;
3610}
3611
3612static int
3613mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
3614 struct flow_cls_offload *f,
3615 unsigned long flow_flags,
3616 struct net_device *filter_dev,
3617 struct mlx5e_tc_flow **__flow)
3618{
3619 struct mlx5e_rep_priv *rpriv = priv->ppriv;
3620 struct mlx5_eswitch_rep *in_rep = rpriv->rep;
3621 struct mlx5_core_dev *in_mdev = priv->mdev;
3622 struct mlx5e_tc_flow *flow;
3623 int err;
3624
3625 flow = __mlx5e_add_fdb_flow(priv, f, flow_flags, filter_dev, in_rep,
3626 in_mdev);
3627 if (IS_ERR(flow))
3628 return PTR_ERR(flow);
3629
3630 if (is_peer_flow_needed(flow)) {
3631 err = mlx5e_tc_add_fdb_peer_flow(f, flow, flow_flags);
3632 if (err) {
3633 mlx5e_tc_del_fdb_flow(priv, flow);
3634 goto out;
3635 }
3636 }
3637
3638 *__flow = flow;
3639
3640 return 0;
3641
3642out:
3643 return err;
3644}
3645
3646static int
3647mlx5e_add_nic_flow(struct mlx5e_priv *priv,
3648 struct flow_cls_offload *f,
3649 unsigned long flow_flags,
3650 struct net_device *filter_dev,
3651 struct mlx5e_tc_flow **__flow)
3652{
3653 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
3654 struct netlink_ext_ack *extack = f->common.extack;
3655 struct mlx5e_tc_flow_parse_attr *parse_attr;
3656 struct mlx5e_tc_flow *flow;
3657 int attr_size, err;
3658
3659 /* multi-chain not supported for NIC rules */
3660 if (!tc_cls_can_offload_and_chain0(priv->netdev, &f->common))
3661 return -EOPNOTSUPP;
3662
3663 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
3664 attr_size = sizeof(struct mlx5_nic_flow_attr);
3665 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
3666 &parse_attr, &flow);
3667 if (err)
3668 goto out;
3669
3670 parse_attr->filter_dev = filter_dev;
3671 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
3672 f, filter_dev);
3673 if (err)
3674 goto err_free;
3675
3676 err = parse_tc_nic_actions(priv, &rule->action, parse_attr, flow, extack);
3677 if (err)
3678 goto err_free;
3679
3680 err = mlx5e_tc_add_nic_flow(priv, parse_attr, flow, extack);
3681 if (err)
3682 goto err_free;
3683
3684 flow_flag_set(flow, OFFLOADED);
3685 kvfree(parse_attr);
3686 *__flow = flow;
3687
3688 return 0;
3689
3690err_free:
3691 mlx5e_flow_put(priv, flow);
3692 kvfree(parse_attr);
3693out:
3694 return err;
3695}
3696
3697static int
3698mlx5e_tc_add_flow(struct mlx5e_priv *priv,
3699 struct flow_cls_offload *f,
3700 unsigned long flags,
3701 struct net_device *filter_dev,
3702 struct mlx5e_tc_flow **flow)
3703{
3704 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3705 unsigned long flow_flags;
3706 int err;
3707
3708 get_flags(flags, &flow_flags);
3709
3710 if (!tc_can_offload_extack(priv->netdev, f->common.extack))
3711 return -EOPNOTSUPP;
3712
3713 if (esw && esw->mode == MLX5_ESWITCH_OFFLOADS)
3714 err = mlx5e_add_fdb_flow(priv, f, flow_flags,
3715 filter_dev, flow);
3716 else
3717 err = mlx5e_add_nic_flow(priv, f, flow_flags,
3718 filter_dev, flow);
3719
3720 return err;
3721}
3722
3723int mlx5e_configure_flower(struct net_device *dev, struct mlx5e_priv *priv,
3724 struct flow_cls_offload *f, unsigned long flags)
3725{
3726 struct netlink_ext_ack *extack = f->common.extack;
3727 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
3728 struct mlx5e_tc_flow *flow;
3729 int err = 0;
3730
3731 rcu_read_lock();
3732 flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
3733 rcu_read_unlock();
3734 if (flow) {
3735 NL_SET_ERR_MSG_MOD(extack,
3736 "flow cookie already exists, ignoring");
3737 netdev_warn_once(priv->netdev,
3738 "flow cookie %lx already exists, ignoring\n",
3739 f->cookie);
3740 err = -EEXIST;
3741 goto out;
3742 }
3743
3744 err = mlx5e_tc_add_flow(priv, f, flags, dev, &flow);
3745 if (err)
3746 goto out;
3747
3748 err = rhashtable_lookup_insert_fast(tc_ht, &flow->node, tc_ht_params);
3749 if (err)
3750 goto err_free;
3751
3752 return 0;
3753
3754err_free:
3755 mlx5e_flow_put(priv, flow);
3756out:
3757 return err;
3758}
3759
3760static bool same_flow_direction(struct mlx5e_tc_flow *flow, int flags)
3761{
3762 bool dir_ingress = !!(flags & MLX5_TC_FLAG(INGRESS));
3763 bool dir_egress = !!(flags & MLX5_TC_FLAG(EGRESS));
3764
3765 return flow_flag_test(flow, INGRESS) == dir_ingress &&
3766 flow_flag_test(flow, EGRESS) == dir_egress;
3767}
3768
3769int mlx5e_delete_flower(struct net_device *dev, struct mlx5e_priv *priv,
3770 struct flow_cls_offload *f, unsigned long flags)
3771{
3772 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
3773 struct mlx5e_tc_flow *flow;
3774 int err;
3775
3776 rcu_read_lock();
3777 flow = rhashtable_lookup_fast(tc_ht, &f->cookie, tc_ht_params);
3778 if (!flow || !same_flow_direction(flow, flags)) {
3779 err = -EINVAL;
3780 goto errout;
3781 }
3782
3783 /* Only delete the flow if it doesn't have MLX5E_TC_FLOW_DELETED flag
3784 * set.
3785 */
3786 if (flow_flag_test_and_set(flow, DELETED)) {
3787 err = -EINVAL;
3788 goto errout;
3789 }
3790 rhashtable_remove_fast(tc_ht, &flow->node, tc_ht_params);
3791 rcu_read_unlock();
3792
3793 mlx5e_flow_put(priv, flow);
3794
3795 return 0;
3796
3797errout:
3798 rcu_read_unlock();
3799 return err;
3800}
3801
3802int mlx5e_stats_flower(struct net_device *dev, struct mlx5e_priv *priv,
3803 struct flow_cls_offload *f, unsigned long flags)
3804{
3805 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
3806 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
3807 struct mlx5_eswitch *peer_esw;
3808 struct mlx5e_tc_flow *flow;
3809 struct mlx5_fc *counter;
3810 u64 lastuse = 0;
3811 u64 packets = 0;
3812 u64 bytes = 0;
3813 int err = 0;
3814
3815 rcu_read_lock();
3816 flow = mlx5e_flow_get(rhashtable_lookup(tc_ht, &f->cookie,
3817 tc_ht_params));
3818 rcu_read_unlock();
3819 if (IS_ERR(flow))
3820 return PTR_ERR(flow);
3821
3822 if (!same_flow_direction(flow, flags)) {
3823 err = -EINVAL;
3824 goto errout;
3825 }
3826
3827 if (mlx5e_is_offloaded_flow(flow)) {
3828 counter = mlx5e_tc_get_counter(flow);
3829 if (!counter)
3830 goto errout;
3831
3832 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
3833 }
3834
3835 /* Under multipath it's possible for one rule to be currently
3836 * un-offloaded while the other rule is offloaded.
3837 */
3838 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
3839 if (!peer_esw)
3840 goto out;
3841
3842 if (flow_flag_test(flow, DUP) &&
3843 flow_flag_test(flow->peer_flow, OFFLOADED)) {
3844 u64 bytes2;
3845 u64 packets2;
3846 u64 lastuse2;
3847
3848 counter = mlx5e_tc_get_counter(flow->peer_flow);
3849 if (!counter)
3850 goto no_peer_counter;
3851 mlx5_fc_query_cached(counter, &bytes2, &packets2, &lastuse2);
3852
3853 bytes += bytes2;
3854 packets += packets2;
3855 lastuse = max_t(u64, lastuse, lastuse2);
3856 }
3857
3858no_peer_counter:
3859 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
3860out:
3861 flow_stats_update(&f->stats, bytes, packets, lastuse);
3862errout:
3863 mlx5e_flow_put(priv, flow);
3864 return err;
3865}
3866
3867static int apply_police_params(struct mlx5e_priv *priv, u32 rate,
3868 struct netlink_ext_ack *extack)
3869{
3870 struct mlx5e_rep_priv *rpriv = priv->ppriv;
3871 struct mlx5_eswitch *esw;
3872 u16 vport_num;
3873 u32 rate_mbps;
3874 int err;
3875
3876 esw = priv->mdev->priv.eswitch;
3877 /* rate is given in bytes/sec.
3878 * First convert to bits/sec and then round to the nearest mbit/secs.
3879 * mbit means million bits.
3880 * Moreover, if rate is non zero we choose to configure to a minimum of
3881 * 1 mbit/sec.
3882 */
3883 rate_mbps = rate ? max_t(u32, (rate * 8 + 500000) / 1000000, 1) : 0;
3884 vport_num = rpriv->rep->vport;
3885
3886 err = mlx5_esw_modify_vport_rate(esw, vport_num, rate_mbps);
3887 if (err)
3888 NL_SET_ERR_MSG_MOD(extack, "failed applying action to hardware");
3889
3890 return err;
3891}
3892
3893static int scan_tc_matchall_fdb_actions(struct mlx5e_priv *priv,
3894 struct flow_action *flow_action,
3895 struct netlink_ext_ack *extack)
3896{
3897 struct mlx5e_rep_priv *rpriv = priv->ppriv;
3898 const struct flow_action_entry *act;
3899 int err;
3900 int i;
3901
3902 if (!flow_action_has_entries(flow_action)) {
3903 NL_SET_ERR_MSG_MOD(extack, "matchall called with no action");
3904 return -EINVAL;
3905 }
3906
3907 if (!flow_offload_has_one_action(flow_action)) {
3908 NL_SET_ERR_MSG_MOD(extack, "matchall policing support only a single action");
3909 return -EOPNOTSUPP;
3910 }
3911
3912 flow_action_for_each(i, act, flow_action) {
3913 switch (act->id) {
3914 case FLOW_ACTION_POLICE:
3915 err = apply_police_params(priv, act->police.rate_bytes_ps, extack);
3916 if (err)
3917 return err;
3918
3919 rpriv->prev_vf_vport_stats = priv->stats.vf_vport;
3920 break;
3921 default:
3922 NL_SET_ERR_MSG_MOD(extack, "mlx5 supports only police action for matchall");
3923 return -EOPNOTSUPP;
3924 }
3925 }
3926
3927 return 0;
3928}
3929
3930int mlx5e_tc_configure_matchall(struct mlx5e_priv *priv,
3931 struct tc_cls_matchall_offload *ma)
3932{
3933 struct netlink_ext_ack *extack = ma->common.extack;
3934 int prio = TC_H_MAJ(ma->common.prio) >> 16;
3935
3936 if (prio != 1) {
3937 NL_SET_ERR_MSG_MOD(extack, "only priority 1 is supported");
3938 return -EINVAL;
3939 }
3940
3941 return scan_tc_matchall_fdb_actions(priv, &ma->rule->action, extack);
3942}
3943
3944int mlx5e_tc_delete_matchall(struct mlx5e_priv *priv,
3945 struct tc_cls_matchall_offload *ma)
3946{
3947 struct netlink_ext_ack *extack = ma->common.extack;
3948
3949 return apply_police_params(priv, 0, extack);
3950}
3951
3952void mlx5e_tc_stats_matchall(struct mlx5e_priv *priv,
3953 struct tc_cls_matchall_offload *ma)
3954{
3955 struct mlx5e_rep_priv *rpriv = priv->ppriv;
3956 struct rtnl_link_stats64 cur_stats;
3957 u64 dbytes;
3958 u64 dpkts;
3959
3960 cur_stats = priv->stats.vf_vport;
3961 dpkts = cur_stats.rx_packets - rpriv->prev_vf_vport_stats.rx_packets;
3962 dbytes = cur_stats.rx_bytes - rpriv->prev_vf_vport_stats.rx_bytes;
3963 rpriv->prev_vf_vport_stats = cur_stats;
3964 flow_stats_update(&ma->stats, dpkts, dbytes, jiffies);
3965}
3966
3967static void mlx5e_tc_hairpin_update_dead_peer(struct mlx5e_priv *priv,
3968 struct mlx5e_priv *peer_priv)
3969{
3970 struct mlx5_core_dev *peer_mdev = peer_priv->mdev;
3971 struct mlx5e_hairpin_entry *hpe, *tmp;
3972 LIST_HEAD(init_wait_list);
3973 u16 peer_vhca_id;
3974 int bkt;
3975
3976 if (!same_hw_devs(priv, peer_priv))
3977 return;
3978
3979 peer_vhca_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
3980
3981 mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
3982 hash_for_each(priv->fs.tc.hairpin_tbl, bkt, hpe, hairpin_hlist)
3983 if (refcount_inc_not_zero(&hpe->refcnt))
3984 list_add(&hpe->dead_peer_wait_list, &init_wait_list);
3985 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
3986
3987 list_for_each_entry_safe(hpe, tmp, &init_wait_list, dead_peer_wait_list) {
3988 wait_for_completion(&hpe->res_ready);
3989 if (!IS_ERR_OR_NULL(hpe->hp) && hpe->peer_vhca_id == peer_vhca_id)
3990 hpe->hp->pair->peer_gone = true;
3991
3992 mlx5e_hairpin_put(priv, hpe);
3993 }
3994}
3995
3996static int mlx5e_tc_netdev_event(struct notifier_block *this,
3997 unsigned long event, void *ptr)
3998{
3999 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
4000 struct mlx5e_flow_steering *fs;
4001 struct mlx5e_priv *peer_priv;
4002 struct mlx5e_tc_table *tc;
4003 struct mlx5e_priv *priv;
4004
4005 if (ndev->netdev_ops != &mlx5e_netdev_ops ||
4006 event != NETDEV_UNREGISTER ||
4007 ndev->reg_state == NETREG_REGISTERED)
4008 return NOTIFY_DONE;
4009
4010 tc = container_of(this, struct mlx5e_tc_table, netdevice_nb);
4011 fs = container_of(tc, struct mlx5e_flow_steering, tc);
4012 priv = container_of(fs, struct mlx5e_priv, fs);
4013 peer_priv = netdev_priv(ndev);
4014 if (priv == peer_priv ||
4015 !(priv->netdev->features & NETIF_F_HW_TC))
4016 return NOTIFY_DONE;
4017
4018 mlx5e_tc_hairpin_update_dead_peer(priv, peer_priv);
4019
4020 return NOTIFY_DONE;
4021}
4022
4023int mlx5e_tc_nic_init(struct mlx5e_priv *priv)
4024{
4025 struct mlx5e_tc_table *tc = &priv->fs.tc;
4026 int err;
4027
4028 mutex_init(&tc->t_lock);
4029 mutex_init(&tc->mod_hdr.lock);
4030 hash_init(tc->mod_hdr.hlist);
4031 mutex_init(&tc->hairpin_tbl_lock);
4032 hash_init(tc->hairpin_tbl);
4033
4034 err = rhashtable_init(&tc->ht, &tc_ht_params);
4035 if (err)
4036 return err;
4037
4038 tc->netdevice_nb.notifier_call = mlx5e_tc_netdev_event;
4039 if (register_netdevice_notifier(&tc->netdevice_nb)) {
4040 tc->netdevice_nb.notifier_call = NULL;
4041 mlx5_core_warn(priv->mdev, "Failed to register netdev notifier\n");
4042 }
4043
4044 return err;
4045}
4046
4047static void _mlx5e_tc_del_flow(void *ptr, void *arg)
4048{
4049 struct mlx5e_tc_flow *flow = ptr;
4050 struct mlx5e_priv *priv = flow->priv;
4051
4052 mlx5e_tc_del_flow(priv, flow);
4053 kfree(flow);
4054}
4055
4056void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv)
4057{
4058 struct mlx5e_tc_table *tc = &priv->fs.tc;
4059
4060 if (tc->netdevice_nb.notifier_call)
4061 unregister_netdevice_notifier(&tc->netdevice_nb);
4062
4063 mutex_destroy(&tc->mod_hdr.lock);
4064 mutex_destroy(&tc->hairpin_tbl_lock);
4065
4066 rhashtable_destroy(&tc->ht);
4067
4068 if (!IS_ERR_OR_NULL(tc->t)) {
4069 mlx5_destroy_flow_table(tc->t);
4070 tc->t = NULL;
4071 }
4072 mutex_destroy(&tc->t_lock);
4073}
4074
4075int mlx5e_tc_esw_init(struct rhashtable *tc_ht)
4076{
4077 return rhashtable_init(tc_ht, &tc_ht_params);
4078}
4079
4080void mlx5e_tc_esw_cleanup(struct rhashtable *tc_ht)
4081{
4082 rhashtable_free_and_destroy(tc_ht, _mlx5e_tc_del_flow, NULL);
4083}
4084
4085int mlx5e_tc_num_filters(struct mlx5e_priv *priv, unsigned long flags)
4086{
4087 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
4088
4089 return atomic_read(&tc_ht->nelems);
4090}
4091
4092void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw)
4093{
4094 struct mlx5e_tc_flow *flow, *tmp;
4095
4096 list_for_each_entry_safe(flow, tmp, &esw->offloads.peer_flows, peer)
4097 __mlx5e_tc_del_fdb_peer_flow(flow);
4098}
4099
4100void mlx5e_tc_reoffload_flows_work(struct work_struct *work)
4101{
4102 struct mlx5_rep_uplink_priv *rpriv =
4103 container_of(work, struct mlx5_rep_uplink_priv,
4104 reoffload_flows_work);
4105 struct mlx5e_tc_flow *flow, *tmp;
4106
4107 mutex_lock(&rpriv->unready_flows_lock);
4108 list_for_each_entry_safe(flow, tmp, &rpriv->unready_flows, unready) {
4109 if (!mlx5e_tc_add_fdb_flow(flow->priv, flow, NULL))
4110 unready_flow_del(flow);
4111 }
4112 mutex_unlock(&rpriv->unready_flows_lock);
4113}
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