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UBUNTU: Ubuntu-4.10.0-37.41
[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / realtek / r8169.c
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1/*
2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/interrupt.h>
25#include <linux/dma-mapping.h>
26#include <linux/pm_runtime.h>
27#include <linux/firmware.h>
28#include <linux/pci-aspm.h>
29#include <linux/prefetch.h>
30#include <linux/ipv6.h>
31#include <net/ip6_checksum.h>
32
33#include <asm/io.h>
34#include <asm/irq.h>
35
36#define RTL8169_VERSION "2.3LK-NAPI"
37#define MODULENAME "r8169"
38#define PFX MODULENAME ": "
39
40#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
41#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
42#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
43#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
44#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
45#define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
46#define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
47#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
48#define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
49#define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
50#define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
51#define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
52#define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
53#define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
54#define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
55#define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
56#define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
57#define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
58#define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
59
60#ifdef RTL8169_DEBUG
61#define assert(expr) \
62 if (!(expr)) { \
63 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
64 #expr,__FILE__,__func__,__LINE__); \
65 }
66#define dprintk(fmt, args...) \
67 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
68#else
69#define assert(expr) do {} while (0)
70#define dprintk(fmt, args...) do {} while (0)
71#endif /* RTL8169_DEBUG */
72
73#define R8169_MSG_DEFAULT \
74 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
75
76#define TX_SLOTS_AVAIL(tp) \
77 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
78
79/* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
80#define TX_FRAGS_READY_FOR(tp,nr_frags) \
81 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
82
83/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
84 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
85static const int multicast_filter_limit = 32;
86
87#define MAX_READ_REQUEST_SHIFT 12
88#define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
89#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
90
91#define R8169_REGS_SIZE 256
92#define R8169_NAPI_WEIGHT 64
93#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
94#define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
95#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
96#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
97
98#define RTL8169_TX_TIMEOUT (6*HZ)
99#define RTL8169_PHY_TIMEOUT (10*HZ)
100
101/* write/read MMIO register */
102#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
103#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
104#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
105#define RTL_R8(reg) readb (ioaddr + (reg))
106#define RTL_R16(reg) readw (ioaddr + (reg))
107#define RTL_R32(reg) readl (ioaddr + (reg))
108
109enum mac_version {
110 RTL_GIGA_MAC_VER_01 = 0,
111 RTL_GIGA_MAC_VER_02,
112 RTL_GIGA_MAC_VER_03,
113 RTL_GIGA_MAC_VER_04,
114 RTL_GIGA_MAC_VER_05,
115 RTL_GIGA_MAC_VER_06,
116 RTL_GIGA_MAC_VER_07,
117 RTL_GIGA_MAC_VER_08,
118 RTL_GIGA_MAC_VER_09,
119 RTL_GIGA_MAC_VER_10,
120 RTL_GIGA_MAC_VER_11,
121 RTL_GIGA_MAC_VER_12,
122 RTL_GIGA_MAC_VER_13,
123 RTL_GIGA_MAC_VER_14,
124 RTL_GIGA_MAC_VER_15,
125 RTL_GIGA_MAC_VER_16,
126 RTL_GIGA_MAC_VER_17,
127 RTL_GIGA_MAC_VER_18,
128 RTL_GIGA_MAC_VER_19,
129 RTL_GIGA_MAC_VER_20,
130 RTL_GIGA_MAC_VER_21,
131 RTL_GIGA_MAC_VER_22,
132 RTL_GIGA_MAC_VER_23,
133 RTL_GIGA_MAC_VER_24,
134 RTL_GIGA_MAC_VER_25,
135 RTL_GIGA_MAC_VER_26,
136 RTL_GIGA_MAC_VER_27,
137 RTL_GIGA_MAC_VER_28,
138 RTL_GIGA_MAC_VER_29,
139 RTL_GIGA_MAC_VER_30,
140 RTL_GIGA_MAC_VER_31,
141 RTL_GIGA_MAC_VER_32,
142 RTL_GIGA_MAC_VER_33,
143 RTL_GIGA_MAC_VER_34,
144 RTL_GIGA_MAC_VER_35,
145 RTL_GIGA_MAC_VER_36,
146 RTL_GIGA_MAC_VER_37,
147 RTL_GIGA_MAC_VER_38,
148 RTL_GIGA_MAC_VER_39,
149 RTL_GIGA_MAC_VER_40,
150 RTL_GIGA_MAC_VER_41,
151 RTL_GIGA_MAC_VER_42,
152 RTL_GIGA_MAC_VER_43,
153 RTL_GIGA_MAC_VER_44,
154 RTL_GIGA_MAC_VER_45,
155 RTL_GIGA_MAC_VER_46,
156 RTL_GIGA_MAC_VER_47,
157 RTL_GIGA_MAC_VER_48,
158 RTL_GIGA_MAC_VER_49,
159 RTL_GIGA_MAC_VER_50,
160 RTL_GIGA_MAC_VER_51,
161 RTL_GIGA_MAC_NONE = 0xff,
162};
163
164enum rtl_tx_desc_version {
165 RTL_TD_0 = 0,
166 RTL_TD_1 = 1,
167};
168
169#define JUMBO_1K ETH_DATA_LEN
170#define JUMBO_4K (4*1024 - ETH_HLEN - 2)
171#define JUMBO_6K (6*1024 - ETH_HLEN - 2)
172#define JUMBO_7K (7*1024 - ETH_HLEN - 2)
173#define JUMBO_9K (9*1024 - ETH_HLEN - 2)
174
175#define _R(NAME,TD,FW,SZ,B) { \
176 .name = NAME, \
177 .txd_version = TD, \
178 .fw_name = FW, \
179 .jumbo_max = SZ, \
180 .jumbo_tx_csum = B \
181}
182
183static const struct {
184 const char *name;
185 enum rtl_tx_desc_version txd_version;
186 const char *fw_name;
187 u16 jumbo_max;
188 bool jumbo_tx_csum;
189} rtl_chip_infos[] = {
190 /* PCI devices. */
191 [RTL_GIGA_MAC_VER_01] =
192 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
193 [RTL_GIGA_MAC_VER_02] =
194 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
195 [RTL_GIGA_MAC_VER_03] =
196 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
197 [RTL_GIGA_MAC_VER_04] =
198 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
199 [RTL_GIGA_MAC_VER_05] =
200 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
201 [RTL_GIGA_MAC_VER_06] =
202 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
203 /* PCI-E devices. */
204 [RTL_GIGA_MAC_VER_07] =
205 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
206 [RTL_GIGA_MAC_VER_08] =
207 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
208 [RTL_GIGA_MAC_VER_09] =
209 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
210 [RTL_GIGA_MAC_VER_10] =
211 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
212 [RTL_GIGA_MAC_VER_11] =
213 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
214 [RTL_GIGA_MAC_VER_12] =
215 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
216 [RTL_GIGA_MAC_VER_13] =
217 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
218 [RTL_GIGA_MAC_VER_14] =
219 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
220 [RTL_GIGA_MAC_VER_15] =
221 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
222 [RTL_GIGA_MAC_VER_16] =
223 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
224 [RTL_GIGA_MAC_VER_17] =
225 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
226 [RTL_GIGA_MAC_VER_18] =
227 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
228 [RTL_GIGA_MAC_VER_19] =
229 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
230 [RTL_GIGA_MAC_VER_20] =
231 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
232 [RTL_GIGA_MAC_VER_21] =
233 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
234 [RTL_GIGA_MAC_VER_22] =
235 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
236 [RTL_GIGA_MAC_VER_23] =
237 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
238 [RTL_GIGA_MAC_VER_24] =
239 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
240 [RTL_GIGA_MAC_VER_25] =
241 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
242 JUMBO_9K, false),
243 [RTL_GIGA_MAC_VER_26] =
244 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
245 JUMBO_9K, false),
246 [RTL_GIGA_MAC_VER_27] =
247 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
248 [RTL_GIGA_MAC_VER_28] =
249 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
250 [RTL_GIGA_MAC_VER_29] =
251 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
252 JUMBO_1K, true),
253 [RTL_GIGA_MAC_VER_30] =
254 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
255 JUMBO_1K, true),
256 [RTL_GIGA_MAC_VER_31] =
257 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
258 [RTL_GIGA_MAC_VER_32] =
259 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
260 JUMBO_9K, false),
261 [RTL_GIGA_MAC_VER_33] =
262 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
263 JUMBO_9K, false),
264 [RTL_GIGA_MAC_VER_34] =
265 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
266 JUMBO_9K, false),
267 [RTL_GIGA_MAC_VER_35] =
268 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1,
269 JUMBO_9K, false),
270 [RTL_GIGA_MAC_VER_36] =
271 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
272 JUMBO_9K, false),
273 [RTL_GIGA_MAC_VER_37] =
274 _R("RTL8402", RTL_TD_1, FIRMWARE_8402_1,
275 JUMBO_1K, true),
276 [RTL_GIGA_MAC_VER_38] =
277 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_1,
278 JUMBO_9K, false),
279 [RTL_GIGA_MAC_VER_39] =
280 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_1,
281 JUMBO_1K, true),
282 [RTL_GIGA_MAC_VER_40] =
283 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_2,
284 JUMBO_9K, false),
285 [RTL_GIGA_MAC_VER_41] =
286 _R("RTL8168g/8111g", RTL_TD_1, NULL, JUMBO_9K, false),
287 [RTL_GIGA_MAC_VER_42] =
288 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_3,
289 JUMBO_9K, false),
290 [RTL_GIGA_MAC_VER_43] =
291 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_2,
292 JUMBO_1K, true),
293 [RTL_GIGA_MAC_VER_44] =
294 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_2,
295 JUMBO_9K, false),
296 [RTL_GIGA_MAC_VER_45] =
297 _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_1,
298 JUMBO_9K, false),
299 [RTL_GIGA_MAC_VER_46] =
300 _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_2,
301 JUMBO_9K, false),
302 [RTL_GIGA_MAC_VER_47] =
303 _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_1,
304 JUMBO_1K, false),
305 [RTL_GIGA_MAC_VER_48] =
306 _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_2,
307 JUMBO_1K, false),
308 [RTL_GIGA_MAC_VER_49] =
309 _R("RTL8168ep/8111ep", RTL_TD_1, NULL,
310 JUMBO_9K, false),
311 [RTL_GIGA_MAC_VER_50] =
312 _R("RTL8168ep/8111ep", RTL_TD_1, NULL,
313 JUMBO_9K, false),
314 [RTL_GIGA_MAC_VER_51] =
315 _R("RTL8168ep/8111ep", RTL_TD_1, NULL,
316 JUMBO_9K, false),
317};
318#undef _R
319
320enum cfg_version {
321 RTL_CFG_0 = 0x00,
322 RTL_CFG_1,
323 RTL_CFG_2
324};
325
326static const struct pci_device_id rtl8169_pci_tbl[] = {
327 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
328 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
329 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8161), 0, 0, RTL_CFG_1 },
330 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
331 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
332 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
333 { PCI_VENDOR_ID_DLINK, 0x4300,
334 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
335 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
336 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
337 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
338 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
339 { PCI_VENDOR_ID_LINKSYS, 0x1032,
340 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
341 { 0x0001, 0x8168,
342 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
343 {0,},
344};
345
346MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
347
348static int rx_buf_sz = 16383;
349static int use_dac = -1;
350static struct {
351 u32 msg_enable;
352} debug = { -1 };
353
354enum rtl_registers {
355 MAC0 = 0, /* Ethernet hardware address. */
356 MAC4 = 4,
357 MAR0 = 8, /* Multicast filter. */
358 CounterAddrLow = 0x10,
359 CounterAddrHigh = 0x14,
360 TxDescStartAddrLow = 0x20,
361 TxDescStartAddrHigh = 0x24,
362 TxHDescStartAddrLow = 0x28,
363 TxHDescStartAddrHigh = 0x2c,
364 FLASH = 0x30,
365 ERSR = 0x36,
366 ChipCmd = 0x37,
367 TxPoll = 0x38,
368 IntrMask = 0x3c,
369 IntrStatus = 0x3e,
370
371 TxConfig = 0x40,
372#define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
373#define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
374
375 RxConfig = 0x44,
376#define RX128_INT_EN (1 << 15) /* 8111c and later */
377#define RX_MULTI_EN (1 << 14) /* 8111c only */
378#define RXCFG_FIFO_SHIFT 13
379 /* No threshold before first PCI xfer */
380#define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
381#define RX_EARLY_OFF (1 << 11)
382#define RXCFG_DMA_SHIFT 8
383 /* Unlimited maximum PCI burst. */
384#define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
385
386 RxMissed = 0x4c,
387 Cfg9346 = 0x50,
388 Config0 = 0x51,
389 Config1 = 0x52,
390 Config2 = 0x53,
391#define PME_SIGNAL (1 << 5) /* 8168c and later */
392
393 Config3 = 0x54,
394 Config4 = 0x55,
395 Config5 = 0x56,
396 MultiIntr = 0x5c,
397 PHYAR = 0x60,
398 PHYstatus = 0x6c,
399 RxMaxSize = 0xda,
400 CPlusCmd = 0xe0,
401 IntrMitigate = 0xe2,
402 RxDescAddrLow = 0xe4,
403 RxDescAddrHigh = 0xe8,
404 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
405
406#define NoEarlyTx 0x3f /* Max value : no early transmit. */
407
408 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
409
410#define TxPacketMax (8064 >> 7)
411#define EarlySize 0x27
412
413 FuncEvent = 0xf0,
414 FuncEventMask = 0xf4,
415 FuncPresetState = 0xf8,
416 IBCR0 = 0xf8,
417 IBCR2 = 0xf9,
418 IBIMR0 = 0xfa,
419 IBISR0 = 0xfb,
420 FuncForceEvent = 0xfc,
421};
422
423enum rtl8110_registers {
424 TBICSR = 0x64,
425 TBI_ANAR = 0x68,
426 TBI_LPAR = 0x6a,
427};
428
429enum rtl8168_8101_registers {
430 CSIDR = 0x64,
431 CSIAR = 0x68,
432#define CSIAR_FLAG 0x80000000
433#define CSIAR_WRITE_CMD 0x80000000
434#define CSIAR_BYTE_ENABLE 0x0f
435#define CSIAR_BYTE_ENABLE_SHIFT 12
436#define CSIAR_ADDR_MASK 0x0fff
437#define CSIAR_FUNC_CARD 0x00000000
438#define CSIAR_FUNC_SDIO 0x00010000
439#define CSIAR_FUNC_NIC 0x00020000
440#define CSIAR_FUNC_NIC2 0x00010000
441 PMCH = 0x6f,
442 EPHYAR = 0x80,
443#define EPHYAR_FLAG 0x80000000
444#define EPHYAR_WRITE_CMD 0x80000000
445#define EPHYAR_REG_MASK 0x1f
446#define EPHYAR_REG_SHIFT 16
447#define EPHYAR_DATA_MASK 0xffff
448 DLLPR = 0xd0,
449#define PFM_EN (1 << 6)
450#define TX_10M_PS_EN (1 << 7)
451 DBG_REG = 0xd1,
452#define FIX_NAK_1 (1 << 4)
453#define FIX_NAK_2 (1 << 3)
454 TWSI = 0xd2,
455 MCU = 0xd3,
456#define NOW_IS_OOB (1 << 7)
457#define TX_EMPTY (1 << 5)
458#define RX_EMPTY (1 << 4)
459#define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
460#define EN_NDP (1 << 3)
461#define EN_OOB_RESET (1 << 2)
462#define LINK_LIST_RDY (1 << 1)
463 EFUSEAR = 0xdc,
464#define EFUSEAR_FLAG 0x80000000
465#define EFUSEAR_WRITE_CMD 0x80000000
466#define EFUSEAR_READ_CMD 0x00000000
467#define EFUSEAR_REG_MASK 0x03ff
468#define EFUSEAR_REG_SHIFT 8
469#define EFUSEAR_DATA_MASK 0xff
470 MISC_1 = 0xf2,
471#define PFM_D3COLD_EN (1 << 6)
472};
473
474enum rtl8168_registers {
475 LED_FREQ = 0x1a,
476 EEE_LED = 0x1b,
477 ERIDR = 0x70,
478 ERIAR = 0x74,
479#define ERIAR_FLAG 0x80000000
480#define ERIAR_WRITE_CMD 0x80000000
481#define ERIAR_READ_CMD 0x00000000
482#define ERIAR_ADDR_BYTE_ALIGN 4
483#define ERIAR_TYPE_SHIFT 16
484#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
485#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
486#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
487#define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
488#define ERIAR_MASK_SHIFT 12
489#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
490#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
491#define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
492#define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
493#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
494 EPHY_RXER_NUM = 0x7c,
495 OCPDR = 0xb0, /* OCP GPHY access */
496#define OCPDR_WRITE_CMD 0x80000000
497#define OCPDR_READ_CMD 0x00000000
498#define OCPDR_REG_MASK 0x7f
499#define OCPDR_GPHY_REG_SHIFT 16
500#define OCPDR_DATA_MASK 0xffff
501 OCPAR = 0xb4,
502#define OCPAR_FLAG 0x80000000
503#define OCPAR_GPHY_WRITE_CMD 0x8000f060
504#define OCPAR_GPHY_READ_CMD 0x0000f060
505 GPHY_OCP = 0xb8,
506 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
507 MISC = 0xf0, /* 8168e only. */
508#define TXPLA_RST (1 << 29)
509#define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
510#define PWM_EN (1 << 22)
511#define RXDV_GATED_EN (1 << 19)
512#define EARLY_TALLY_EN (1 << 16)
513};
514
515enum rtl_register_content {
516 /* InterruptStatusBits */
517 SYSErr = 0x8000,
518 PCSTimeout = 0x4000,
519 SWInt = 0x0100,
520 TxDescUnavail = 0x0080,
521 RxFIFOOver = 0x0040,
522 LinkChg = 0x0020,
523 RxOverflow = 0x0010,
524 TxErr = 0x0008,
525 TxOK = 0x0004,
526 RxErr = 0x0002,
527 RxOK = 0x0001,
528
529 /* RxStatusDesc */
530 RxBOVF = (1 << 24),
531 RxFOVF = (1 << 23),
532 RxRWT = (1 << 22),
533 RxRES = (1 << 21),
534 RxRUNT = (1 << 20),
535 RxCRC = (1 << 19),
536
537 /* ChipCmdBits */
538 StopReq = 0x80,
539 CmdReset = 0x10,
540 CmdRxEnb = 0x08,
541 CmdTxEnb = 0x04,
542 RxBufEmpty = 0x01,
543
544 /* TXPoll register p.5 */
545 HPQ = 0x80, /* Poll cmd on the high prio queue */
546 NPQ = 0x40, /* Poll cmd on the low prio queue */
547 FSWInt = 0x01, /* Forced software interrupt */
548
549 /* Cfg9346Bits */
550 Cfg9346_Lock = 0x00,
551 Cfg9346_Unlock = 0xc0,
552
553 /* rx_mode_bits */
554 AcceptErr = 0x20,
555 AcceptRunt = 0x10,
556 AcceptBroadcast = 0x08,
557 AcceptMulticast = 0x04,
558 AcceptMyPhys = 0x02,
559 AcceptAllPhys = 0x01,
560#define RX_CONFIG_ACCEPT_MASK 0x3f
561
562 /* TxConfigBits */
563 TxInterFrameGapShift = 24,
564 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
565
566 /* Config1 register p.24 */
567 LEDS1 = (1 << 7),
568 LEDS0 = (1 << 6),
569 Speed_down = (1 << 4),
570 MEMMAP = (1 << 3),
571 IOMAP = (1 << 2),
572 VPD = (1 << 1),
573 PMEnable = (1 << 0), /* Power Management Enable */
574
575 /* Config2 register p. 25 */
576 ClkReqEn = (1 << 7), /* Clock Request Enable */
577 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
578 PCI_Clock_66MHz = 0x01,
579 PCI_Clock_33MHz = 0x00,
580
581 /* Config3 register p.25 */
582 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
583 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
584 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
585 Rdy_to_L23 = (1 << 1), /* L23 Enable */
586 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
587
588 /* Config4 register */
589 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
590
591 /* Config5 register p.27 */
592 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
593 MWF = (1 << 5), /* Accept Multicast wakeup frame */
594 UWF = (1 << 4), /* Accept Unicast wakeup frame */
595 Spi_en = (1 << 3),
596 LanWake = (1 << 1), /* LanWake enable/disable */
597 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
598 ASPM_en = (1 << 0), /* ASPM enable */
599
600 /* TBICSR p.28 */
601 TBIReset = 0x80000000,
602 TBILoopback = 0x40000000,
603 TBINwEnable = 0x20000000,
604 TBINwRestart = 0x10000000,
605 TBILinkOk = 0x02000000,
606 TBINwComplete = 0x01000000,
607
608 /* CPlusCmd p.31 */
609 EnableBist = (1 << 15), // 8168 8101
610 Mac_dbgo_oe = (1 << 14), // 8168 8101
611 Normal_mode = (1 << 13), // unused
612 Force_half_dup = (1 << 12), // 8168 8101
613 Force_rxflow_en = (1 << 11), // 8168 8101
614 Force_txflow_en = (1 << 10), // 8168 8101
615 Cxpl_dbg_sel = (1 << 9), // 8168 8101
616 ASF = (1 << 8), // 8168 8101
617 PktCntrDisable = (1 << 7), // 8168 8101
618 Mac_dbgo_sel = 0x001c, // 8168
619 RxVlan = (1 << 6),
620 RxChkSum = (1 << 5),
621 PCIDAC = (1 << 4),
622 PCIMulRW = (1 << 3),
623 INTT_0 = 0x0000, // 8168
624 INTT_1 = 0x0001, // 8168
625 INTT_2 = 0x0002, // 8168
626 INTT_3 = 0x0003, // 8168
627
628 /* rtl8169_PHYstatus */
629 TBI_Enable = 0x80,
630 TxFlowCtrl = 0x40,
631 RxFlowCtrl = 0x20,
632 _1000bpsF = 0x10,
633 _100bps = 0x08,
634 _10bps = 0x04,
635 LinkStatus = 0x02,
636 FullDup = 0x01,
637
638 /* _TBICSRBit */
639 TBILinkOK = 0x02000000,
640
641 /* ResetCounterCommand */
642 CounterReset = 0x1,
643
644 /* DumpCounterCommand */
645 CounterDump = 0x8,
646
647 /* magic enable v2 */
648 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
649};
650
651enum rtl_desc_bit {
652 /* First doubleword. */
653 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
654 RingEnd = (1 << 30), /* End of descriptor ring */
655 FirstFrag = (1 << 29), /* First segment of a packet */
656 LastFrag = (1 << 28), /* Final segment of a packet */
657};
658
659/* Generic case. */
660enum rtl_tx_desc_bit {
661 /* First doubleword. */
662 TD_LSO = (1 << 27), /* Large Send Offload */
663#define TD_MSS_MAX 0x07ffu /* MSS value */
664
665 /* Second doubleword. */
666 TxVlanTag = (1 << 17), /* Add VLAN tag */
667};
668
669/* 8169, 8168b and 810x except 8102e. */
670enum rtl_tx_desc_bit_0 {
671 /* First doubleword. */
672#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
673 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
674 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
675 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
676};
677
678/* 8102e, 8168c and beyond. */
679enum rtl_tx_desc_bit_1 {
680 /* First doubleword. */
681 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
682 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
683#define GTTCPHO_SHIFT 18
684#define GTTCPHO_MAX 0x7fU
685
686 /* Second doubleword. */
687#define TCPHO_SHIFT 18
688#define TCPHO_MAX 0x3ffU
689#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
690 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
691 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
692 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
693 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
694};
695
696enum rtl_rx_desc_bit {
697 /* Rx private */
698 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
699 PID0 = (1 << 17), /* Protocol ID bit 0/2 */
700
701#define RxProtoUDP (PID1)
702#define RxProtoTCP (PID0)
703#define RxProtoIP (PID1 | PID0)
704#define RxProtoMask RxProtoIP
705
706 IPFail = (1 << 16), /* IP checksum failed */
707 UDPFail = (1 << 15), /* UDP/IP checksum failed */
708 TCPFail = (1 << 14), /* TCP/IP checksum failed */
709 RxVlanTag = (1 << 16), /* VLAN tag available */
710};
711
712#define RsvdMask 0x3fffc000
713
714struct TxDesc {
715 __le32 opts1;
716 __le32 opts2;
717 __le64 addr;
718};
719
720struct RxDesc {
721 __le32 opts1;
722 __le32 opts2;
723 __le64 addr;
724};
725
726struct ring_info {
727 struct sk_buff *skb;
728 u32 len;
729 u8 __pad[sizeof(void *) - sizeof(u32)];
730};
731
732enum features {
733 RTL_FEATURE_WOL = (1 << 0),
734 RTL_FEATURE_MSI = (1 << 1),
735 RTL_FEATURE_GMII = (1 << 2),
736};
737
738struct rtl8169_counters {
739 __le64 tx_packets;
740 __le64 rx_packets;
741 __le64 tx_errors;
742 __le32 rx_errors;
743 __le16 rx_missed;
744 __le16 align_errors;
745 __le32 tx_one_collision;
746 __le32 tx_multi_collision;
747 __le64 rx_unicast;
748 __le64 rx_broadcast;
749 __le32 rx_multicast;
750 __le16 tx_aborted;
751 __le16 tx_underun;
752};
753
754struct rtl8169_tc_offsets {
755 bool inited;
756 __le64 tx_errors;
757 __le32 tx_multi_collision;
758 __le16 tx_aborted;
759};
760
761enum rtl_flag {
762 RTL_FLAG_TASK_ENABLED,
763 RTL_FLAG_TASK_SLOW_PENDING,
764 RTL_FLAG_TASK_RESET_PENDING,
765 RTL_FLAG_TASK_PHY_PENDING,
766 RTL_FLAG_MAX
767};
768
769struct rtl8169_stats {
770 u64 packets;
771 u64 bytes;
772 struct u64_stats_sync syncp;
773};
774
775struct rtl8169_private {
776 void __iomem *mmio_addr; /* memory map physical address */
777 struct pci_dev *pci_dev;
778 struct net_device *dev;
779 struct napi_struct napi;
780 u32 msg_enable;
781 u16 txd_version;
782 u16 mac_version;
783 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
784 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
785 u32 dirty_tx;
786 struct rtl8169_stats rx_stats;
787 struct rtl8169_stats tx_stats;
788 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
789 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
790 dma_addr_t TxPhyAddr;
791 dma_addr_t RxPhyAddr;
792 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
793 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
794 struct timer_list timer;
795 u16 cp_cmd;
796
797 u16 event_slow;
798
799 struct mdio_ops {
800 void (*write)(struct rtl8169_private *, int, int);
801 int (*read)(struct rtl8169_private *, int);
802 } mdio_ops;
803
804 struct pll_power_ops {
805 void (*down)(struct rtl8169_private *);
806 void (*up)(struct rtl8169_private *);
807 } pll_power_ops;
808
809 struct jumbo_ops {
810 void (*enable)(struct rtl8169_private *);
811 void (*disable)(struct rtl8169_private *);
812 } jumbo_ops;
813
814 struct csi_ops {
815 void (*write)(struct rtl8169_private *, int, int);
816 u32 (*read)(struct rtl8169_private *, int);
817 } csi_ops;
818
819 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
820 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
821 void (*phy_reset_enable)(struct rtl8169_private *tp);
822 void (*hw_start)(struct net_device *);
823 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
824 unsigned int (*link_ok)(void __iomem *);
825 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
826 bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
827
828 struct {
829 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
830 struct mutex mutex;
831 struct work_struct work;
832 } wk;
833
834 unsigned features;
835
836 struct mii_if_info mii;
837 dma_addr_t counters_phys_addr;
838 struct rtl8169_counters *counters;
839 struct rtl8169_tc_offsets tc_offset;
840 u32 saved_wolopts;
841 u32 opts1_mask;
842
843 struct rtl_fw {
844 const struct firmware *fw;
845
846#define RTL_VER_SIZE 32
847
848 char version[RTL_VER_SIZE];
849
850 struct rtl_fw_phy_action {
851 __le32 *code;
852 size_t size;
853 } phy_action;
854 } *rtl_fw;
855#define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
856
857 u32 ocp_base;
858};
859
860MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
861MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
862module_param(use_dac, int, 0);
863MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
864module_param_named(debug, debug.msg_enable, int, 0);
865MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
866MODULE_LICENSE("GPL");
867MODULE_VERSION(RTL8169_VERSION);
868MODULE_FIRMWARE(FIRMWARE_8168D_1);
869MODULE_FIRMWARE(FIRMWARE_8168D_2);
870MODULE_FIRMWARE(FIRMWARE_8168E_1);
871MODULE_FIRMWARE(FIRMWARE_8168E_2);
872MODULE_FIRMWARE(FIRMWARE_8168E_3);
873MODULE_FIRMWARE(FIRMWARE_8105E_1);
874MODULE_FIRMWARE(FIRMWARE_8168F_1);
875MODULE_FIRMWARE(FIRMWARE_8168F_2);
876MODULE_FIRMWARE(FIRMWARE_8402_1);
877MODULE_FIRMWARE(FIRMWARE_8411_1);
878MODULE_FIRMWARE(FIRMWARE_8411_2);
879MODULE_FIRMWARE(FIRMWARE_8106E_1);
880MODULE_FIRMWARE(FIRMWARE_8106E_2);
881MODULE_FIRMWARE(FIRMWARE_8168G_2);
882MODULE_FIRMWARE(FIRMWARE_8168G_3);
883MODULE_FIRMWARE(FIRMWARE_8168H_1);
884MODULE_FIRMWARE(FIRMWARE_8168H_2);
885MODULE_FIRMWARE(FIRMWARE_8107E_1);
886MODULE_FIRMWARE(FIRMWARE_8107E_2);
887
888static void rtl_lock_work(struct rtl8169_private *tp)
889{
890 mutex_lock(&tp->wk.mutex);
891}
892
893static void rtl_unlock_work(struct rtl8169_private *tp)
894{
895 mutex_unlock(&tp->wk.mutex);
896}
897
898static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
899{
900 pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
901 PCI_EXP_DEVCTL_READRQ, force);
902}
903
904struct rtl_cond {
905 bool (*check)(struct rtl8169_private *);
906 const char *msg;
907};
908
909static void rtl_udelay(unsigned int d)
910{
911 udelay(d);
912}
913
914static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
915 void (*delay)(unsigned int), unsigned int d, int n,
916 bool high)
917{
918 int i;
919
920 for (i = 0; i < n; i++) {
921 delay(d);
922 if (c->check(tp) == high)
923 return true;
924 }
925 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
926 c->msg, !high, n, d);
927 return false;
928}
929
930static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
931 const struct rtl_cond *c,
932 unsigned int d, int n)
933{
934 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
935}
936
937static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
938 const struct rtl_cond *c,
939 unsigned int d, int n)
940{
941 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
942}
943
944static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
945 const struct rtl_cond *c,
946 unsigned int d, int n)
947{
948 return rtl_loop_wait(tp, c, msleep, d, n, true);
949}
950
951static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
952 const struct rtl_cond *c,
953 unsigned int d, int n)
954{
955 return rtl_loop_wait(tp, c, msleep, d, n, false);
956}
957
958#define DECLARE_RTL_COND(name) \
959static bool name ## _check(struct rtl8169_private *); \
960 \
961static const struct rtl_cond name = { \
962 .check = name ## _check, \
963 .msg = #name \
964}; \
965 \
966static bool name ## _check(struct rtl8169_private *tp)
967
968static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
969{
970 if (reg & 0xffff0001) {
971 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
972 return true;
973 }
974 return false;
975}
976
977DECLARE_RTL_COND(rtl_ocp_gphy_cond)
978{
979 void __iomem *ioaddr = tp->mmio_addr;
980
981 return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
982}
983
984static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
985{
986 void __iomem *ioaddr = tp->mmio_addr;
987
988 if (rtl_ocp_reg_failure(tp, reg))
989 return;
990
991 RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
992
993 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
994}
995
996static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
997{
998 void __iomem *ioaddr = tp->mmio_addr;
999
1000 if (rtl_ocp_reg_failure(tp, reg))
1001 return 0;
1002
1003 RTL_W32(GPHY_OCP, reg << 15);
1004
1005 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1006 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
1007}
1008
1009static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1010{
1011 void __iomem *ioaddr = tp->mmio_addr;
1012
1013 if (rtl_ocp_reg_failure(tp, reg))
1014 return;
1015
1016 RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
1017}
1018
1019static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1020{
1021 void __iomem *ioaddr = tp->mmio_addr;
1022
1023 if (rtl_ocp_reg_failure(tp, reg))
1024 return 0;
1025
1026 RTL_W32(OCPDR, reg << 15);
1027
1028 return RTL_R32(OCPDR);
1029}
1030
1031#define OCP_STD_PHY_BASE 0xa400
1032
1033static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1034{
1035 if (reg == 0x1f) {
1036 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1037 return;
1038 }
1039
1040 if (tp->ocp_base != OCP_STD_PHY_BASE)
1041 reg -= 0x10;
1042
1043 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1044}
1045
1046static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1047{
1048 if (tp->ocp_base != OCP_STD_PHY_BASE)
1049 reg -= 0x10;
1050
1051 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1052}
1053
1054static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1055{
1056 if (reg == 0x1f) {
1057 tp->ocp_base = value << 4;
1058 return;
1059 }
1060
1061 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1062}
1063
1064static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1065{
1066 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1067}
1068
1069DECLARE_RTL_COND(rtl_phyar_cond)
1070{
1071 void __iomem *ioaddr = tp->mmio_addr;
1072
1073 return RTL_R32(PHYAR) & 0x80000000;
1074}
1075
1076static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1077{
1078 void __iomem *ioaddr = tp->mmio_addr;
1079
1080 RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1081
1082 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
1083 /*
1084 * According to hardware specs a 20us delay is required after write
1085 * complete indication, but before sending next command.
1086 */
1087 udelay(20);
1088}
1089
1090static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1091{
1092 void __iomem *ioaddr = tp->mmio_addr;
1093 int value;
1094
1095 RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
1096
1097 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1098 RTL_R32(PHYAR) & 0xffff : ~0;
1099
1100 /*
1101 * According to hardware specs a 20us delay is required after read
1102 * complete indication, but before sending next command.
1103 */
1104 udelay(20);
1105
1106 return value;
1107}
1108
1109DECLARE_RTL_COND(rtl_ocpar_cond)
1110{
1111 void __iomem *ioaddr = tp->mmio_addr;
1112
1113 return RTL_R32(OCPAR) & OCPAR_FLAG;
1114}
1115
1116static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
1117{
1118 void __iomem *ioaddr = tp->mmio_addr;
1119
1120 RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
1121 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
1122 RTL_W32(EPHY_RXER_NUM, 0);
1123
1124 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
1125}
1126
1127static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
1128{
1129 r8168dp_1_mdio_access(tp, reg,
1130 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
1131}
1132
1133static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
1134{
1135 void __iomem *ioaddr = tp->mmio_addr;
1136
1137 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
1138
1139 mdelay(1);
1140 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1141 RTL_W32(EPHY_RXER_NUM, 0);
1142
1143 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1144 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
1145}
1146
1147#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1148
1149static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1150{
1151 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1152}
1153
1154static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1155{
1156 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1157}
1158
1159static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1160{
1161 void __iomem *ioaddr = tp->mmio_addr;
1162
1163 r8168dp_2_mdio_start(ioaddr);
1164
1165 r8169_mdio_write(tp, reg, value);
1166
1167 r8168dp_2_mdio_stop(ioaddr);
1168}
1169
1170static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1171{
1172 void __iomem *ioaddr = tp->mmio_addr;
1173 int value;
1174
1175 r8168dp_2_mdio_start(ioaddr);
1176
1177 value = r8169_mdio_read(tp, reg);
1178
1179 r8168dp_2_mdio_stop(ioaddr);
1180
1181 return value;
1182}
1183
1184static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1185{
1186 tp->mdio_ops.write(tp, location, val);
1187}
1188
1189static int rtl_readphy(struct rtl8169_private *tp, int location)
1190{
1191 return tp->mdio_ops.read(tp, location);
1192}
1193
1194static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1195{
1196 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1197}
1198
1199static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1200{
1201 int val;
1202
1203 val = rtl_readphy(tp, reg_addr);
1204 rtl_writephy(tp, reg_addr, (val & ~m) | p);
1205}
1206
1207static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1208 int val)
1209{
1210 struct rtl8169_private *tp = netdev_priv(dev);
1211
1212 rtl_writephy(tp, location, val);
1213}
1214
1215static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1216{
1217 struct rtl8169_private *tp = netdev_priv(dev);
1218
1219 return rtl_readphy(tp, location);
1220}
1221
1222DECLARE_RTL_COND(rtl_ephyar_cond)
1223{
1224 void __iomem *ioaddr = tp->mmio_addr;
1225
1226 return RTL_R32(EPHYAR) & EPHYAR_FLAG;
1227}
1228
1229static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1230{
1231 void __iomem *ioaddr = tp->mmio_addr;
1232
1233 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1234 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1235
1236 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1237
1238 udelay(10);
1239}
1240
1241static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1242{
1243 void __iomem *ioaddr = tp->mmio_addr;
1244
1245 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1246
1247 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1248 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
1249}
1250
1251DECLARE_RTL_COND(rtl_eriar_cond)
1252{
1253 void __iomem *ioaddr = tp->mmio_addr;
1254
1255 return RTL_R32(ERIAR) & ERIAR_FLAG;
1256}
1257
1258static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1259 u32 val, int type)
1260{
1261 void __iomem *ioaddr = tp->mmio_addr;
1262
1263 BUG_ON((addr & 3) || (mask == 0));
1264 RTL_W32(ERIDR, val);
1265 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1266
1267 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1268}
1269
1270static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1271{
1272 void __iomem *ioaddr = tp->mmio_addr;
1273
1274 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1275
1276 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1277 RTL_R32(ERIDR) : ~0;
1278}
1279
1280static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1281 u32 m, int type)
1282{
1283 u32 val;
1284
1285 val = rtl_eri_read(tp, addr, type);
1286 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1287}
1288
1289static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1290{
1291 void __iomem *ioaddr = tp->mmio_addr;
1292
1293 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1294 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1295 RTL_R32(OCPDR) : ~0;
1296}
1297
1298static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1299{
1300 return rtl_eri_read(tp, reg, ERIAR_OOB);
1301}
1302
1303static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1304{
1305 switch (tp->mac_version) {
1306 case RTL_GIGA_MAC_VER_27:
1307 case RTL_GIGA_MAC_VER_28:
1308 case RTL_GIGA_MAC_VER_31:
1309 return r8168dp_ocp_read(tp, mask, reg);
1310 case RTL_GIGA_MAC_VER_49:
1311 case RTL_GIGA_MAC_VER_50:
1312 case RTL_GIGA_MAC_VER_51:
1313 return r8168ep_ocp_read(tp, mask, reg);
1314 default:
1315 BUG();
1316 return ~0;
1317 }
1318}
1319
1320static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1321 u32 data)
1322{
1323 void __iomem *ioaddr = tp->mmio_addr;
1324
1325 RTL_W32(OCPDR, data);
1326 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1327 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1328}
1329
1330static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1331 u32 data)
1332{
1333 rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1334 data, ERIAR_OOB);
1335}
1336
1337static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
1338{
1339 switch (tp->mac_version) {
1340 case RTL_GIGA_MAC_VER_27:
1341 case RTL_GIGA_MAC_VER_28:
1342 case RTL_GIGA_MAC_VER_31:
1343 r8168dp_ocp_write(tp, mask, reg, data);
1344 break;
1345 case RTL_GIGA_MAC_VER_49:
1346 case RTL_GIGA_MAC_VER_50:
1347 case RTL_GIGA_MAC_VER_51:
1348 r8168ep_ocp_write(tp, mask, reg, data);
1349 break;
1350 default:
1351 BUG();
1352 break;
1353 }
1354}
1355
1356static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
1357{
1358 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1359
1360 ocp_write(tp, 0x1, 0x30, 0x00000001);
1361}
1362
1363#define OOB_CMD_RESET 0x00
1364#define OOB_CMD_DRIVER_START 0x05
1365#define OOB_CMD_DRIVER_STOP 0x06
1366
1367static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1368{
1369 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1370}
1371
1372DECLARE_RTL_COND(rtl_ocp_read_cond)
1373{
1374 u16 reg;
1375
1376 reg = rtl8168_get_ocp_reg(tp);
1377
1378 return ocp_read(tp, 0x0f, reg) & 0x00000800;
1379}
1380
1381DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1382{
1383 return ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1384}
1385
1386DECLARE_RTL_COND(rtl_ocp_tx_cond)
1387{
1388 void __iomem *ioaddr = tp->mmio_addr;
1389
1390 return RTL_R8(IBISR0) & 0x02;
1391}
1392
1393static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1394{
1395 void __iomem *ioaddr = tp->mmio_addr;
1396
1397 RTL_W8(IBCR2, RTL_R8(IBCR2) & ~0x01);
1398 rtl_msleep_loop_wait_low(tp, &rtl_ocp_tx_cond, 50, 2000);
1399 RTL_W8(IBISR0, RTL_R8(IBISR0) | 0x20);
1400 RTL_W8(IBCR0, RTL_R8(IBCR0) & ~0x01);
1401}
1402
1403static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1404{
1405 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
1406 rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1407}
1408
1409static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1410{
1411 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1412 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1413 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1414}
1415
1416static void rtl8168_driver_start(struct rtl8169_private *tp)
1417{
1418 switch (tp->mac_version) {
1419 case RTL_GIGA_MAC_VER_27:
1420 case RTL_GIGA_MAC_VER_28:
1421 case RTL_GIGA_MAC_VER_31:
1422 rtl8168dp_driver_start(tp);
1423 break;
1424 case RTL_GIGA_MAC_VER_49:
1425 case RTL_GIGA_MAC_VER_50:
1426 case RTL_GIGA_MAC_VER_51:
1427 rtl8168ep_driver_start(tp);
1428 break;
1429 default:
1430 BUG();
1431 break;
1432 }
1433}
1434
1435static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1436{
1437 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1438 rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1439}
1440
1441static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1442{
1443 rtl8168ep_stop_cmac(tp);
1444 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1445 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1446 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1447}
1448
1449static void rtl8168_driver_stop(struct rtl8169_private *tp)
1450{
1451 switch (tp->mac_version) {
1452 case RTL_GIGA_MAC_VER_27:
1453 case RTL_GIGA_MAC_VER_28:
1454 case RTL_GIGA_MAC_VER_31:
1455 rtl8168dp_driver_stop(tp);
1456 break;
1457 case RTL_GIGA_MAC_VER_49:
1458 case RTL_GIGA_MAC_VER_50:
1459 case RTL_GIGA_MAC_VER_51:
1460 rtl8168ep_driver_stop(tp);
1461 break;
1462 default:
1463 BUG();
1464 break;
1465 }
1466}
1467
1468static int r8168dp_check_dash(struct rtl8169_private *tp)
1469{
1470 u16 reg = rtl8168_get_ocp_reg(tp);
1471
1472 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
1473}
1474
1475static int r8168ep_check_dash(struct rtl8169_private *tp)
1476{
1477 return (ocp_read(tp, 0x0f, 0x128) & 0x00000001) ? 1 : 0;
1478}
1479
1480static int r8168_check_dash(struct rtl8169_private *tp)
1481{
1482 switch (tp->mac_version) {
1483 case RTL_GIGA_MAC_VER_27:
1484 case RTL_GIGA_MAC_VER_28:
1485 case RTL_GIGA_MAC_VER_31:
1486 return r8168dp_check_dash(tp);
1487 case RTL_GIGA_MAC_VER_49:
1488 case RTL_GIGA_MAC_VER_50:
1489 case RTL_GIGA_MAC_VER_51:
1490 return r8168ep_check_dash(tp);
1491 default:
1492 return 0;
1493 }
1494}
1495
1496struct exgmac_reg {
1497 u16 addr;
1498 u16 mask;
1499 u32 val;
1500};
1501
1502static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1503 const struct exgmac_reg *r, int len)
1504{
1505 while (len-- > 0) {
1506 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1507 r++;
1508 }
1509}
1510
1511DECLARE_RTL_COND(rtl_efusear_cond)
1512{
1513 void __iomem *ioaddr = tp->mmio_addr;
1514
1515 return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
1516}
1517
1518static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1519{
1520 void __iomem *ioaddr = tp->mmio_addr;
1521
1522 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1523
1524 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1525 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1526}
1527
1528static u16 rtl_get_events(struct rtl8169_private *tp)
1529{
1530 void __iomem *ioaddr = tp->mmio_addr;
1531
1532 return RTL_R16(IntrStatus);
1533}
1534
1535static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1536{
1537 void __iomem *ioaddr = tp->mmio_addr;
1538
1539 RTL_W16(IntrStatus, bits);
1540 mmiowb();
1541}
1542
1543static void rtl_irq_disable(struct rtl8169_private *tp)
1544{
1545 void __iomem *ioaddr = tp->mmio_addr;
1546
1547 RTL_W16(IntrMask, 0);
1548 mmiowb();
1549}
1550
1551static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1552{
1553 void __iomem *ioaddr = tp->mmio_addr;
1554
1555 RTL_W16(IntrMask, bits);
1556}
1557
1558#define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1559#define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1560#define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1561
1562static void rtl_irq_enable_all(struct rtl8169_private *tp)
1563{
1564 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1565}
1566
1567static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1568{
1569 void __iomem *ioaddr = tp->mmio_addr;
1570
1571 rtl_irq_disable(tp);
1572 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1573 RTL_R8(ChipCmd);
1574}
1575
1576static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1577{
1578 void __iomem *ioaddr = tp->mmio_addr;
1579
1580 return RTL_R32(TBICSR) & TBIReset;
1581}
1582
1583static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1584{
1585 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1586}
1587
1588static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1589{
1590 return RTL_R32(TBICSR) & TBILinkOk;
1591}
1592
1593static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1594{
1595 return RTL_R8(PHYstatus) & LinkStatus;
1596}
1597
1598static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1599{
1600 void __iomem *ioaddr = tp->mmio_addr;
1601
1602 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1603}
1604
1605static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1606{
1607 unsigned int val;
1608
1609 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1610 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1611}
1612
1613static void rtl_link_chg_patch(struct rtl8169_private *tp)
1614{
1615 void __iomem *ioaddr = tp->mmio_addr;
1616 struct net_device *dev = tp->dev;
1617
1618 if (!netif_running(dev))
1619 return;
1620
1621 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1622 tp->mac_version == RTL_GIGA_MAC_VER_38) {
1623 if (RTL_R8(PHYstatus) & _1000bpsF) {
1624 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1625 ERIAR_EXGMAC);
1626 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1627 ERIAR_EXGMAC);
1628 } else if (RTL_R8(PHYstatus) & _100bps) {
1629 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1630 ERIAR_EXGMAC);
1631 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1632 ERIAR_EXGMAC);
1633 } else {
1634 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1635 ERIAR_EXGMAC);
1636 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1637 ERIAR_EXGMAC);
1638 }
1639 /* Reset packet filter */
1640 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1641 ERIAR_EXGMAC);
1642 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1643 ERIAR_EXGMAC);
1644 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1645 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1646 if (RTL_R8(PHYstatus) & _1000bpsF) {
1647 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1648 ERIAR_EXGMAC);
1649 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1650 ERIAR_EXGMAC);
1651 } else {
1652 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1653 ERIAR_EXGMAC);
1654 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1655 ERIAR_EXGMAC);
1656 }
1657 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1658 if (RTL_R8(PHYstatus) & _10bps) {
1659 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1660 ERIAR_EXGMAC);
1661 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1662 ERIAR_EXGMAC);
1663 } else {
1664 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1665 ERIAR_EXGMAC);
1666 }
1667 }
1668}
1669
1670static void __rtl8169_check_link_status(struct net_device *dev,
1671 struct rtl8169_private *tp,
1672 void __iomem *ioaddr, bool pm)
1673{
1674 if (tp->link_ok(ioaddr)) {
1675 rtl_link_chg_patch(tp);
1676 /* This is to cancel a scheduled suspend if there's one. */
1677 if (pm)
1678 pm_request_resume(&tp->pci_dev->dev);
1679 netif_carrier_on(dev);
1680 if (net_ratelimit())
1681 netif_info(tp, ifup, dev, "link up\n");
1682 } else {
1683 netif_carrier_off(dev);
1684 netif_info(tp, ifdown, dev, "link down\n");
1685 if (pm)
1686 pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1687 }
1688}
1689
1690static void rtl8169_check_link_status(struct net_device *dev,
1691 struct rtl8169_private *tp,
1692 void __iomem *ioaddr)
1693{
1694 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1695}
1696
1697#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1698
1699static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1700{
1701 void __iomem *ioaddr = tp->mmio_addr;
1702 u8 options;
1703 u32 wolopts = 0;
1704
1705 options = RTL_R8(Config1);
1706 if (!(options & PMEnable))
1707 return 0;
1708
1709 options = RTL_R8(Config3);
1710 if (options & LinkUp)
1711 wolopts |= WAKE_PHY;
1712 switch (tp->mac_version) {
1713 case RTL_GIGA_MAC_VER_34:
1714 case RTL_GIGA_MAC_VER_35:
1715 case RTL_GIGA_MAC_VER_36:
1716 case RTL_GIGA_MAC_VER_37:
1717 case RTL_GIGA_MAC_VER_38:
1718 case RTL_GIGA_MAC_VER_40:
1719 case RTL_GIGA_MAC_VER_41:
1720 case RTL_GIGA_MAC_VER_42:
1721 case RTL_GIGA_MAC_VER_43:
1722 case RTL_GIGA_MAC_VER_44:
1723 case RTL_GIGA_MAC_VER_45:
1724 case RTL_GIGA_MAC_VER_46:
1725 case RTL_GIGA_MAC_VER_47:
1726 case RTL_GIGA_MAC_VER_48:
1727 case RTL_GIGA_MAC_VER_49:
1728 case RTL_GIGA_MAC_VER_50:
1729 case RTL_GIGA_MAC_VER_51:
1730 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1731 wolopts |= WAKE_MAGIC;
1732 break;
1733 default:
1734 if (options & MagicPacket)
1735 wolopts |= WAKE_MAGIC;
1736 break;
1737 }
1738
1739 options = RTL_R8(Config5);
1740 if (options & UWF)
1741 wolopts |= WAKE_UCAST;
1742 if (options & BWF)
1743 wolopts |= WAKE_BCAST;
1744 if (options & MWF)
1745 wolopts |= WAKE_MCAST;
1746
1747 return wolopts;
1748}
1749
1750static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1751{
1752 struct rtl8169_private *tp = netdev_priv(dev);
1753 struct device *d = &tp->pci_dev->dev;
1754
1755 pm_runtime_get_noresume(d);
1756
1757 rtl_lock_work(tp);
1758
1759 wol->supported = WAKE_ANY;
1760 if (pm_runtime_active(d))
1761 wol->wolopts = __rtl8169_get_wol(tp);
1762 else
1763 wol->wolopts = tp->saved_wolopts;
1764
1765 rtl_unlock_work(tp);
1766
1767 pm_runtime_put_noidle(d);
1768}
1769
1770static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1771{
1772 void __iomem *ioaddr = tp->mmio_addr;
1773 unsigned int i, tmp;
1774 static const struct {
1775 u32 opt;
1776 u16 reg;
1777 u8 mask;
1778 } cfg[] = {
1779 { WAKE_PHY, Config3, LinkUp },
1780 { WAKE_UCAST, Config5, UWF },
1781 { WAKE_BCAST, Config5, BWF },
1782 { WAKE_MCAST, Config5, MWF },
1783 { WAKE_ANY, Config5, LanWake },
1784 { WAKE_MAGIC, Config3, MagicPacket }
1785 };
1786 u8 options;
1787
1788 RTL_W8(Cfg9346, Cfg9346_Unlock);
1789
1790 switch (tp->mac_version) {
1791 case RTL_GIGA_MAC_VER_34:
1792 case RTL_GIGA_MAC_VER_35:
1793 case RTL_GIGA_MAC_VER_36:
1794 case RTL_GIGA_MAC_VER_37:
1795 case RTL_GIGA_MAC_VER_38:
1796 case RTL_GIGA_MAC_VER_40:
1797 case RTL_GIGA_MAC_VER_41:
1798 case RTL_GIGA_MAC_VER_42:
1799 case RTL_GIGA_MAC_VER_43:
1800 case RTL_GIGA_MAC_VER_44:
1801 case RTL_GIGA_MAC_VER_45:
1802 case RTL_GIGA_MAC_VER_46:
1803 case RTL_GIGA_MAC_VER_47:
1804 case RTL_GIGA_MAC_VER_48:
1805 case RTL_GIGA_MAC_VER_49:
1806 case RTL_GIGA_MAC_VER_50:
1807 case RTL_GIGA_MAC_VER_51:
1808 tmp = ARRAY_SIZE(cfg) - 1;
1809 if (wolopts & WAKE_MAGIC)
1810 rtl_w0w1_eri(tp,
1811 0x0dc,
1812 ERIAR_MASK_0100,
1813 MagicPacket_v2,
1814 0x0000,
1815 ERIAR_EXGMAC);
1816 else
1817 rtl_w0w1_eri(tp,
1818 0x0dc,
1819 ERIAR_MASK_0100,
1820 0x0000,
1821 MagicPacket_v2,
1822 ERIAR_EXGMAC);
1823 break;
1824 default:
1825 tmp = ARRAY_SIZE(cfg);
1826 break;
1827 }
1828
1829 for (i = 0; i < tmp; i++) {
1830 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1831 if (wolopts & cfg[i].opt)
1832 options |= cfg[i].mask;
1833 RTL_W8(cfg[i].reg, options);
1834 }
1835
1836 switch (tp->mac_version) {
1837 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1838 options = RTL_R8(Config1) & ~PMEnable;
1839 if (wolopts)
1840 options |= PMEnable;
1841 RTL_W8(Config1, options);
1842 break;
1843 default:
1844 options = RTL_R8(Config2) & ~PME_SIGNAL;
1845 if (wolopts)
1846 options |= PME_SIGNAL;
1847 RTL_W8(Config2, options);
1848 break;
1849 }
1850
1851 RTL_W8(Cfg9346, Cfg9346_Lock);
1852}
1853
1854static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1855{
1856 struct rtl8169_private *tp = netdev_priv(dev);
1857 struct device *d = &tp->pci_dev->dev;
1858
1859 pm_runtime_get_noresume(d);
1860
1861 rtl_lock_work(tp);
1862
1863 if (wol->wolopts)
1864 tp->features |= RTL_FEATURE_WOL;
1865 else
1866 tp->features &= ~RTL_FEATURE_WOL;
1867 if (pm_runtime_active(d))
1868 __rtl8169_set_wol(tp, wol->wolopts);
1869 else
1870 tp->saved_wolopts = wol->wolopts;
1871
1872 rtl_unlock_work(tp);
1873
1874 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1875
1876 pm_runtime_put_noidle(d);
1877
1878 return 0;
1879}
1880
1881static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1882{
1883 return rtl_chip_infos[tp->mac_version].fw_name;
1884}
1885
1886static void rtl8169_get_drvinfo(struct net_device *dev,
1887 struct ethtool_drvinfo *info)
1888{
1889 struct rtl8169_private *tp = netdev_priv(dev);
1890 struct rtl_fw *rtl_fw = tp->rtl_fw;
1891
1892 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1893 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1894 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1895 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1896 if (!IS_ERR_OR_NULL(rtl_fw))
1897 strlcpy(info->fw_version, rtl_fw->version,
1898 sizeof(info->fw_version));
1899}
1900
1901static int rtl8169_get_regs_len(struct net_device *dev)
1902{
1903 return R8169_REGS_SIZE;
1904}
1905
1906static int rtl8169_set_speed_tbi(struct net_device *dev,
1907 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1908{
1909 struct rtl8169_private *tp = netdev_priv(dev);
1910 void __iomem *ioaddr = tp->mmio_addr;
1911 int ret = 0;
1912 u32 reg;
1913
1914 reg = RTL_R32(TBICSR);
1915 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1916 (duplex == DUPLEX_FULL)) {
1917 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1918 } else if (autoneg == AUTONEG_ENABLE)
1919 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1920 else {
1921 netif_warn(tp, link, dev,
1922 "incorrect speed setting refused in TBI mode\n");
1923 ret = -EOPNOTSUPP;
1924 }
1925
1926 return ret;
1927}
1928
1929static int rtl8169_set_speed_xmii(struct net_device *dev,
1930 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1931{
1932 struct rtl8169_private *tp = netdev_priv(dev);
1933 int giga_ctrl, bmcr;
1934 int rc = -EINVAL;
1935
1936 rtl_writephy(tp, 0x1f, 0x0000);
1937
1938 if (autoneg == AUTONEG_ENABLE) {
1939 int auto_nego;
1940
1941 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1942 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1943 ADVERTISE_100HALF | ADVERTISE_100FULL);
1944
1945 if (adv & ADVERTISED_10baseT_Half)
1946 auto_nego |= ADVERTISE_10HALF;
1947 if (adv & ADVERTISED_10baseT_Full)
1948 auto_nego |= ADVERTISE_10FULL;
1949 if (adv & ADVERTISED_100baseT_Half)
1950 auto_nego |= ADVERTISE_100HALF;
1951 if (adv & ADVERTISED_100baseT_Full)
1952 auto_nego |= ADVERTISE_100FULL;
1953
1954 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1955
1956 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1957 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1958
1959 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1960 if (tp->mii.supports_gmii) {
1961 if (adv & ADVERTISED_1000baseT_Half)
1962 giga_ctrl |= ADVERTISE_1000HALF;
1963 if (adv & ADVERTISED_1000baseT_Full)
1964 giga_ctrl |= ADVERTISE_1000FULL;
1965 } else if (adv & (ADVERTISED_1000baseT_Half |
1966 ADVERTISED_1000baseT_Full)) {
1967 netif_info(tp, link, dev,
1968 "PHY does not support 1000Mbps\n");
1969 goto out;
1970 }
1971
1972 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1973
1974 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1975 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1976 } else {
1977 giga_ctrl = 0;
1978
1979 if (speed == SPEED_10)
1980 bmcr = 0;
1981 else if (speed == SPEED_100)
1982 bmcr = BMCR_SPEED100;
1983 else
1984 goto out;
1985
1986 if (duplex == DUPLEX_FULL)
1987 bmcr |= BMCR_FULLDPLX;
1988 }
1989
1990 rtl_writephy(tp, MII_BMCR, bmcr);
1991
1992 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1993 tp->mac_version == RTL_GIGA_MAC_VER_03) {
1994 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1995 rtl_writephy(tp, 0x17, 0x2138);
1996 rtl_writephy(tp, 0x0e, 0x0260);
1997 } else {
1998 rtl_writephy(tp, 0x17, 0x2108);
1999 rtl_writephy(tp, 0x0e, 0x0000);
2000 }
2001 }
2002
2003 rc = 0;
2004out:
2005 return rc;
2006}
2007
2008static int rtl8169_set_speed(struct net_device *dev,
2009 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
2010{
2011 struct rtl8169_private *tp = netdev_priv(dev);
2012 int ret;
2013
2014 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
2015 if (ret < 0)
2016 goto out;
2017
2018 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
2019 (advertising & ADVERTISED_1000baseT_Full) &&
2020 !pci_is_pcie(tp->pci_dev)) {
2021 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
2022 }
2023out:
2024 return ret;
2025}
2026
2027static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2028{
2029 struct rtl8169_private *tp = netdev_priv(dev);
2030 int ret;
2031
2032 del_timer_sync(&tp->timer);
2033
2034 rtl_lock_work(tp);
2035 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
2036 cmd->duplex, cmd->advertising);
2037 rtl_unlock_work(tp);
2038
2039 return ret;
2040}
2041
2042static netdev_features_t rtl8169_fix_features(struct net_device *dev,
2043 netdev_features_t features)
2044{
2045 struct rtl8169_private *tp = netdev_priv(dev);
2046
2047 if (dev->mtu > TD_MSS_MAX)
2048 features &= ~NETIF_F_ALL_TSO;
2049
2050 if (dev->mtu > JUMBO_1K &&
2051 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
2052 features &= ~NETIF_F_IP_CSUM;
2053
2054 return features;
2055}
2056
2057static void __rtl8169_set_features(struct net_device *dev,
2058 netdev_features_t features)
2059{
2060 struct rtl8169_private *tp = netdev_priv(dev);
2061 void __iomem *ioaddr = tp->mmio_addr;
2062 u32 rx_config;
2063
2064 rx_config = RTL_R32(RxConfig);
2065 if (features & NETIF_F_RXALL)
2066 rx_config |= (AcceptErr | AcceptRunt);
2067 else
2068 rx_config &= ~(AcceptErr | AcceptRunt);
2069
2070 RTL_W32(RxConfig, rx_config);
2071
2072 if (features & NETIF_F_RXCSUM)
2073 tp->cp_cmd |= RxChkSum;
2074 else
2075 tp->cp_cmd &= ~RxChkSum;
2076
2077 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2078 tp->cp_cmd |= RxVlan;
2079 else
2080 tp->cp_cmd &= ~RxVlan;
2081
2082 tp->cp_cmd |= RTL_R16(CPlusCmd) & ~(RxVlan | RxChkSum);
2083
2084 RTL_W16(CPlusCmd, tp->cp_cmd);
2085 RTL_R16(CPlusCmd);
2086}
2087
2088static int rtl8169_set_features(struct net_device *dev,
2089 netdev_features_t features)
2090{
2091 struct rtl8169_private *tp = netdev_priv(dev);
2092
2093 features &= NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX;
2094
2095 rtl_lock_work(tp);
2096 if (features ^ dev->features)
2097 __rtl8169_set_features(dev, features);
2098 rtl_unlock_work(tp);
2099
2100 return 0;
2101}
2102
2103
2104static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
2105{
2106 return (skb_vlan_tag_present(skb)) ?
2107 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
2108}
2109
2110static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
2111{
2112 u32 opts2 = le32_to_cpu(desc->opts2);
2113
2114 if (opts2 & RxVlanTag)
2115 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
2116}
2117
2118static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
2119{
2120 struct rtl8169_private *tp = netdev_priv(dev);
2121 void __iomem *ioaddr = tp->mmio_addr;
2122 u32 status;
2123
2124 cmd->supported =
2125 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
2126 cmd->port = PORT_FIBRE;
2127 cmd->transceiver = XCVR_INTERNAL;
2128
2129 status = RTL_R32(TBICSR);
2130 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
2131 cmd->autoneg = !!(status & TBINwEnable);
2132
2133 ethtool_cmd_speed_set(cmd, SPEED_1000);
2134 cmd->duplex = DUPLEX_FULL; /* Always set */
2135
2136 return 0;
2137}
2138
2139static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
2140{
2141 struct rtl8169_private *tp = netdev_priv(dev);
2142
2143 return mii_ethtool_gset(&tp->mii, cmd);
2144}
2145
2146static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2147{
2148 struct rtl8169_private *tp = netdev_priv(dev);
2149 int rc;
2150
2151 rtl_lock_work(tp);
2152 rc = tp->get_settings(dev, cmd);
2153 rtl_unlock_work(tp);
2154
2155 return rc;
2156}
2157
2158static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2159 void *p)
2160{
2161 struct rtl8169_private *tp = netdev_priv(dev);
2162 u32 __iomem *data = tp->mmio_addr;
2163 u32 *dw = p;
2164 int i;
2165
2166 rtl_lock_work(tp);
2167 for (i = 0; i < R8169_REGS_SIZE; i += 4)
2168 memcpy_fromio(dw++, data++, 4);
2169 rtl_unlock_work(tp);
2170}
2171
2172static u32 rtl8169_get_msglevel(struct net_device *dev)
2173{
2174 struct rtl8169_private *tp = netdev_priv(dev);
2175
2176 return tp->msg_enable;
2177}
2178
2179static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
2180{
2181 struct rtl8169_private *tp = netdev_priv(dev);
2182
2183 tp->msg_enable = value;
2184}
2185
2186static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
2187 "tx_packets",
2188 "rx_packets",
2189 "tx_errors",
2190 "rx_errors",
2191 "rx_missed",
2192 "align_errors",
2193 "tx_single_collisions",
2194 "tx_multi_collisions",
2195 "unicast",
2196 "broadcast",
2197 "multicast",
2198 "tx_aborted",
2199 "tx_underrun",
2200};
2201
2202static int rtl8169_get_sset_count(struct net_device *dev, int sset)
2203{
2204 switch (sset) {
2205 case ETH_SS_STATS:
2206 return ARRAY_SIZE(rtl8169_gstrings);
2207 default:
2208 return -EOPNOTSUPP;
2209 }
2210}
2211
2212DECLARE_RTL_COND(rtl_counters_cond)
2213{
2214 void __iomem *ioaddr = tp->mmio_addr;
2215
2216 return RTL_R32(CounterAddrLow) & (CounterReset | CounterDump);
2217}
2218
2219static bool rtl8169_do_counters(struct net_device *dev, u32 counter_cmd)
2220{
2221 struct rtl8169_private *tp = netdev_priv(dev);
2222 void __iomem *ioaddr = tp->mmio_addr;
2223 dma_addr_t paddr = tp->counters_phys_addr;
2224 u32 cmd;
2225 bool ret;
2226
2227 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
2228 cmd = (u64)paddr & DMA_BIT_MASK(32);
2229 RTL_W32(CounterAddrLow, cmd);
2230 RTL_W32(CounterAddrLow, cmd | counter_cmd);
2231
2232 ret = rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
2233
2234 RTL_W32(CounterAddrLow, 0);
2235 RTL_W32(CounterAddrHigh, 0);
2236
2237 return ret;
2238}
2239
2240static bool rtl8169_reset_counters(struct net_device *dev)
2241{
2242 struct rtl8169_private *tp = netdev_priv(dev);
2243
2244 /*
2245 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
2246 * tally counters.
2247 */
2248 if (tp->mac_version < RTL_GIGA_MAC_VER_19)
2249 return true;
2250
2251 return rtl8169_do_counters(dev, CounterReset);
2252}
2253
2254static bool rtl8169_update_counters(struct net_device *dev)
2255{
2256 struct rtl8169_private *tp = netdev_priv(dev);
2257 void __iomem *ioaddr = tp->mmio_addr;
2258
2259 /*
2260 * Some chips are unable to dump tally counters when the receiver
2261 * is disabled.
2262 */
2263 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
2264 return true;
2265
2266 return rtl8169_do_counters(dev, CounterDump);
2267}
2268
2269static bool rtl8169_init_counter_offsets(struct net_device *dev)
2270{
2271 struct rtl8169_private *tp = netdev_priv(dev);
2272 struct rtl8169_counters *counters = tp->counters;
2273 bool ret = false;
2274
2275 /*
2276 * rtl8169_init_counter_offsets is called from rtl_open. On chip
2277 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
2278 * reset by a power cycle, while the counter values collected by the
2279 * driver are reset at every driver unload/load cycle.
2280 *
2281 * To make sure the HW values returned by @get_stats64 match the SW
2282 * values, we collect the initial values at first open(*) and use them
2283 * as offsets to normalize the values returned by @get_stats64.
2284 *
2285 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
2286 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
2287 * set at open time by rtl_hw_start.
2288 */
2289
2290 if (tp->tc_offset.inited)
2291 return true;
2292
2293 /* If both, reset and update fail, propagate to caller. */
2294 if (rtl8169_reset_counters(dev))
2295 ret = true;
2296
2297 if (rtl8169_update_counters(dev))
2298 ret = true;
2299
2300 tp->tc_offset.tx_errors = counters->tx_errors;
2301 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
2302 tp->tc_offset.tx_aborted = counters->tx_aborted;
2303 tp->tc_offset.inited = true;
2304
2305 return ret;
2306}
2307
2308static void rtl8169_get_ethtool_stats(struct net_device *dev,
2309 struct ethtool_stats *stats, u64 *data)
2310{
2311 struct rtl8169_private *tp = netdev_priv(dev);
2312 struct device *d = &tp->pci_dev->dev;
2313 struct rtl8169_counters *counters = tp->counters;
2314
2315 ASSERT_RTNL();
2316
2317 pm_runtime_get_noresume(d);
2318
2319 if (pm_runtime_active(d))
2320 rtl8169_update_counters(dev);
2321
2322 pm_runtime_put_noidle(d);
2323
2324 data[0] = le64_to_cpu(counters->tx_packets);
2325 data[1] = le64_to_cpu(counters->rx_packets);
2326 data[2] = le64_to_cpu(counters->tx_errors);
2327 data[3] = le32_to_cpu(counters->rx_errors);
2328 data[4] = le16_to_cpu(counters->rx_missed);
2329 data[5] = le16_to_cpu(counters->align_errors);
2330 data[6] = le32_to_cpu(counters->tx_one_collision);
2331 data[7] = le32_to_cpu(counters->tx_multi_collision);
2332 data[8] = le64_to_cpu(counters->rx_unicast);
2333 data[9] = le64_to_cpu(counters->rx_broadcast);
2334 data[10] = le32_to_cpu(counters->rx_multicast);
2335 data[11] = le16_to_cpu(counters->tx_aborted);
2336 data[12] = le16_to_cpu(counters->tx_underun);
2337}
2338
2339static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2340{
2341 switch(stringset) {
2342 case ETH_SS_STATS:
2343 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
2344 break;
2345 }
2346}
2347
2348static int rtl8169_nway_reset(struct net_device *dev)
2349{
2350 struct rtl8169_private *tp = netdev_priv(dev);
2351
2352 return mii_nway_restart(&tp->mii);
2353}
2354
2355static const struct ethtool_ops rtl8169_ethtool_ops = {
2356 .get_drvinfo = rtl8169_get_drvinfo,
2357 .get_regs_len = rtl8169_get_regs_len,
2358 .get_link = ethtool_op_get_link,
2359 .get_settings = rtl8169_get_settings,
2360 .set_settings = rtl8169_set_settings,
2361 .get_msglevel = rtl8169_get_msglevel,
2362 .set_msglevel = rtl8169_set_msglevel,
2363 .get_regs = rtl8169_get_regs,
2364 .get_wol = rtl8169_get_wol,
2365 .set_wol = rtl8169_set_wol,
2366 .get_strings = rtl8169_get_strings,
2367 .get_sset_count = rtl8169_get_sset_count,
2368 .get_ethtool_stats = rtl8169_get_ethtool_stats,
2369 .get_ts_info = ethtool_op_get_ts_info,
2370 .nway_reset = rtl8169_nway_reset,
2371};
2372
2373static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2374 struct net_device *dev, u8 default_version)
2375{
2376 void __iomem *ioaddr = tp->mmio_addr;
2377 /*
2378 * The driver currently handles the 8168Bf and the 8168Be identically
2379 * but they can be identified more specifically through the test below
2380 * if needed:
2381 *
2382 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2383 *
2384 * Same thing for the 8101Eb and the 8101Ec:
2385 *
2386 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2387 */
2388 static const struct rtl_mac_info {
2389 u32 mask;
2390 u32 val;
2391 int mac_version;
2392 } mac_info[] = {
2393 /* 8168EP family. */
2394 { 0x7cf00000, 0x50200000, RTL_GIGA_MAC_VER_51 },
2395 { 0x7cf00000, 0x50100000, RTL_GIGA_MAC_VER_50 },
2396 { 0x7cf00000, 0x50000000, RTL_GIGA_MAC_VER_49 },
2397
2398 /* 8168H family. */
2399 { 0x7cf00000, 0x54100000, RTL_GIGA_MAC_VER_46 },
2400 { 0x7cf00000, 0x54000000, RTL_GIGA_MAC_VER_45 },
2401
2402 /* 8168G family. */
2403 { 0x7cf00000, 0x5c800000, RTL_GIGA_MAC_VER_44 },
2404 { 0x7cf00000, 0x50900000, RTL_GIGA_MAC_VER_42 },
2405 { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 },
2406 { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 },
2407
2408 /* 8168F family. */
2409 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 },
2410 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
2411 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
2412
2413 /* 8168E family. */
2414 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
2415 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
2416 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
2417 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
2418
2419 /* 8168D family. */
2420 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
2421 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
2422 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
2423
2424 /* 8168DP family. */
2425 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
2426 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
2427 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
2428
2429 /* 8168C family. */
2430 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
2431 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
2432 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
2433 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
2434 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
2435 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
2436 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
2437 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
2438 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
2439
2440 /* 8168B family. */
2441 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
2442 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
2443 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
2444 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
2445
2446 /* 8101 family. */
2447 { 0x7cf00000, 0x44900000, RTL_GIGA_MAC_VER_39 },
2448 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 },
2449 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
2450 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
2451 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
2452 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
2453 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2454 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
2455 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
2456 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
2457 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
2458 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
2459 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
2460 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2461 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
2462 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2463 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
2464 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
2465 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
2466 /* FIXME: where did these entries come from ? -- FR */
2467 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
2468 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
2469
2470 /* 8110 family. */
2471 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
2472 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
2473 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
2474 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
2475 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
2476 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
2477
2478 /* Catch-all */
2479 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
2480 };
2481 const struct rtl_mac_info *p = mac_info;
2482 u32 reg;
2483
2484 reg = RTL_R32(TxConfig);
2485 while ((reg & p->mask) != p->val)
2486 p++;
2487 tp->mac_version = p->mac_version;
2488
2489 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2490 netif_notice(tp, probe, dev,
2491 "unknown MAC, using family default\n");
2492 tp->mac_version = default_version;
2493 } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2494 tp->mac_version = tp->mii.supports_gmii ?
2495 RTL_GIGA_MAC_VER_42 :
2496 RTL_GIGA_MAC_VER_43;
2497 } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
2498 tp->mac_version = tp->mii.supports_gmii ?
2499 RTL_GIGA_MAC_VER_45 :
2500 RTL_GIGA_MAC_VER_47;
2501 } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
2502 tp->mac_version = tp->mii.supports_gmii ?
2503 RTL_GIGA_MAC_VER_46 :
2504 RTL_GIGA_MAC_VER_48;
2505 }
2506}
2507
2508static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2509{
2510 dprintk("mac_version = 0x%02x\n", tp->mac_version);
2511}
2512
2513struct phy_reg {
2514 u16 reg;
2515 u16 val;
2516};
2517
2518static void rtl_writephy_batch(struct rtl8169_private *tp,
2519 const struct phy_reg *regs, int len)
2520{
2521 while (len-- > 0) {
2522 rtl_writephy(tp, regs->reg, regs->val);
2523 regs++;
2524 }
2525}
2526
2527#define PHY_READ 0x00000000
2528#define PHY_DATA_OR 0x10000000
2529#define PHY_DATA_AND 0x20000000
2530#define PHY_BJMPN 0x30000000
2531#define PHY_MDIO_CHG 0x40000000
2532#define PHY_CLEAR_READCOUNT 0x70000000
2533#define PHY_WRITE 0x80000000
2534#define PHY_READCOUNT_EQ_SKIP 0x90000000
2535#define PHY_COMP_EQ_SKIPN 0xa0000000
2536#define PHY_COMP_NEQ_SKIPN 0xb0000000
2537#define PHY_WRITE_PREVIOUS 0xc0000000
2538#define PHY_SKIPN 0xd0000000
2539#define PHY_DELAY_MS 0xe0000000
2540
2541struct fw_info {
2542 u32 magic;
2543 char version[RTL_VER_SIZE];
2544 __le32 fw_start;
2545 __le32 fw_len;
2546 u8 chksum;
2547} __packed;
2548
2549#define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2550
2551static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2552{
2553 const struct firmware *fw = rtl_fw->fw;
2554 struct fw_info *fw_info = (struct fw_info *)fw->data;
2555 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2556 char *version = rtl_fw->version;
2557 bool rc = false;
2558
2559 if (fw->size < FW_OPCODE_SIZE)
2560 goto out;
2561
2562 if (!fw_info->magic) {
2563 size_t i, size, start;
2564 u8 checksum = 0;
2565
2566 if (fw->size < sizeof(*fw_info))
2567 goto out;
2568
2569 for (i = 0; i < fw->size; i++)
2570 checksum += fw->data[i];
2571 if (checksum != 0)
2572 goto out;
2573
2574 start = le32_to_cpu(fw_info->fw_start);
2575 if (start > fw->size)
2576 goto out;
2577
2578 size = le32_to_cpu(fw_info->fw_len);
2579 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2580 goto out;
2581
2582 memcpy(version, fw_info->version, RTL_VER_SIZE);
2583
2584 pa->code = (__le32 *)(fw->data + start);
2585 pa->size = size;
2586 } else {
2587 if (fw->size % FW_OPCODE_SIZE)
2588 goto out;
2589
2590 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2591
2592 pa->code = (__le32 *)fw->data;
2593 pa->size = fw->size / FW_OPCODE_SIZE;
2594 }
2595 version[RTL_VER_SIZE - 1] = 0;
2596
2597 rc = true;
2598out:
2599 return rc;
2600}
2601
2602static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2603 struct rtl_fw_phy_action *pa)
2604{
2605 bool rc = false;
2606 size_t index;
2607
2608 for (index = 0; index < pa->size; index++) {
2609 u32 action = le32_to_cpu(pa->code[index]);
2610 u32 regno = (action & 0x0fff0000) >> 16;
2611
2612 switch(action & 0xf0000000) {
2613 case PHY_READ:
2614 case PHY_DATA_OR:
2615 case PHY_DATA_AND:
2616 case PHY_MDIO_CHG:
2617 case PHY_CLEAR_READCOUNT:
2618 case PHY_WRITE:
2619 case PHY_WRITE_PREVIOUS:
2620 case PHY_DELAY_MS:
2621 break;
2622
2623 case PHY_BJMPN:
2624 if (regno > index) {
2625 netif_err(tp, ifup, tp->dev,
2626 "Out of range of firmware\n");
2627 goto out;
2628 }
2629 break;
2630 case PHY_READCOUNT_EQ_SKIP:
2631 if (index + 2 >= pa->size) {
2632 netif_err(tp, ifup, tp->dev,
2633 "Out of range of firmware\n");
2634 goto out;
2635 }
2636 break;
2637 case PHY_COMP_EQ_SKIPN:
2638 case PHY_COMP_NEQ_SKIPN:
2639 case PHY_SKIPN:
2640 if (index + 1 + regno >= pa->size) {
2641 netif_err(tp, ifup, tp->dev,
2642 "Out of range of firmware\n");
2643 goto out;
2644 }
2645 break;
2646
2647 default:
2648 netif_err(tp, ifup, tp->dev,
2649 "Invalid action 0x%08x\n", action);
2650 goto out;
2651 }
2652 }
2653 rc = true;
2654out:
2655 return rc;
2656}
2657
2658static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2659{
2660 struct net_device *dev = tp->dev;
2661 int rc = -EINVAL;
2662
2663 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2664 netif_err(tp, ifup, dev, "invalid firmware\n");
2665 goto out;
2666 }
2667
2668 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2669 rc = 0;
2670out:
2671 return rc;
2672}
2673
2674static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2675{
2676 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2677 struct mdio_ops org, *ops = &tp->mdio_ops;
2678 u32 predata, count;
2679 size_t index;
2680
2681 predata = count = 0;
2682 org.write = ops->write;
2683 org.read = ops->read;
2684
2685 for (index = 0; index < pa->size; ) {
2686 u32 action = le32_to_cpu(pa->code[index]);
2687 u32 data = action & 0x0000ffff;
2688 u32 regno = (action & 0x0fff0000) >> 16;
2689
2690 if (!action)
2691 break;
2692
2693 switch(action & 0xf0000000) {
2694 case PHY_READ:
2695 predata = rtl_readphy(tp, regno);
2696 count++;
2697 index++;
2698 break;
2699 case PHY_DATA_OR:
2700 predata |= data;
2701 index++;
2702 break;
2703 case PHY_DATA_AND:
2704 predata &= data;
2705 index++;
2706 break;
2707 case PHY_BJMPN:
2708 index -= regno;
2709 break;
2710 case PHY_MDIO_CHG:
2711 if (data == 0) {
2712 ops->write = org.write;
2713 ops->read = org.read;
2714 } else if (data == 1) {
2715 ops->write = mac_mcu_write;
2716 ops->read = mac_mcu_read;
2717 }
2718
2719 index++;
2720 break;
2721 case PHY_CLEAR_READCOUNT:
2722 count = 0;
2723 index++;
2724 break;
2725 case PHY_WRITE:
2726 rtl_writephy(tp, regno, data);
2727 index++;
2728 break;
2729 case PHY_READCOUNT_EQ_SKIP:
2730 index += (count == data) ? 2 : 1;
2731 break;
2732 case PHY_COMP_EQ_SKIPN:
2733 if (predata == data)
2734 index += regno;
2735 index++;
2736 break;
2737 case PHY_COMP_NEQ_SKIPN:
2738 if (predata != data)
2739 index += regno;
2740 index++;
2741 break;
2742 case PHY_WRITE_PREVIOUS:
2743 rtl_writephy(tp, regno, predata);
2744 index++;
2745 break;
2746 case PHY_SKIPN:
2747 index += regno + 1;
2748 break;
2749 case PHY_DELAY_MS:
2750 mdelay(data);
2751 index++;
2752 break;
2753
2754 default:
2755 BUG();
2756 }
2757 }
2758
2759 ops->write = org.write;
2760 ops->read = org.read;
2761}
2762
2763static void rtl_release_firmware(struct rtl8169_private *tp)
2764{
2765 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2766 release_firmware(tp->rtl_fw->fw);
2767 kfree(tp->rtl_fw);
2768 }
2769 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2770}
2771
2772static void rtl_apply_firmware(struct rtl8169_private *tp)
2773{
2774 struct rtl_fw *rtl_fw = tp->rtl_fw;
2775
2776 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2777 if (!IS_ERR_OR_NULL(rtl_fw))
2778 rtl_phy_write_fw(tp, rtl_fw);
2779}
2780
2781static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2782{
2783 if (rtl_readphy(tp, reg) != val)
2784 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2785 else
2786 rtl_apply_firmware(tp);
2787}
2788
2789static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2790{
2791 static const struct phy_reg phy_reg_init[] = {
2792 { 0x1f, 0x0001 },
2793 { 0x06, 0x006e },
2794 { 0x08, 0x0708 },
2795 { 0x15, 0x4000 },
2796 { 0x18, 0x65c7 },
2797
2798 { 0x1f, 0x0001 },
2799 { 0x03, 0x00a1 },
2800 { 0x02, 0x0008 },
2801 { 0x01, 0x0120 },
2802 { 0x00, 0x1000 },
2803 { 0x04, 0x0800 },
2804 { 0x04, 0x0000 },
2805
2806 { 0x03, 0xff41 },
2807 { 0x02, 0xdf60 },
2808 { 0x01, 0x0140 },
2809 { 0x00, 0x0077 },
2810 { 0x04, 0x7800 },
2811 { 0x04, 0x7000 },
2812
2813 { 0x03, 0x802f },
2814 { 0x02, 0x4f02 },
2815 { 0x01, 0x0409 },
2816 { 0x00, 0xf0f9 },
2817 { 0x04, 0x9800 },
2818 { 0x04, 0x9000 },
2819
2820 { 0x03, 0xdf01 },
2821 { 0x02, 0xdf20 },
2822 { 0x01, 0xff95 },
2823 { 0x00, 0xba00 },
2824 { 0x04, 0xa800 },
2825 { 0x04, 0xa000 },
2826
2827 { 0x03, 0xff41 },
2828 { 0x02, 0xdf20 },
2829 { 0x01, 0x0140 },
2830 { 0x00, 0x00bb },
2831 { 0x04, 0xb800 },
2832 { 0x04, 0xb000 },
2833
2834 { 0x03, 0xdf41 },
2835 { 0x02, 0xdc60 },
2836 { 0x01, 0x6340 },
2837 { 0x00, 0x007d },
2838 { 0x04, 0xd800 },
2839 { 0x04, 0xd000 },
2840
2841 { 0x03, 0xdf01 },
2842 { 0x02, 0xdf20 },
2843 { 0x01, 0x100a },
2844 { 0x00, 0xa0ff },
2845 { 0x04, 0xf800 },
2846 { 0x04, 0xf000 },
2847
2848 { 0x1f, 0x0000 },
2849 { 0x0b, 0x0000 },
2850 { 0x00, 0x9200 }
2851 };
2852
2853 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2854}
2855
2856static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2857{
2858 static const struct phy_reg phy_reg_init[] = {
2859 { 0x1f, 0x0002 },
2860 { 0x01, 0x90d0 },
2861 { 0x1f, 0x0000 }
2862 };
2863
2864 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2865}
2866
2867static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2868{
2869 struct pci_dev *pdev = tp->pci_dev;
2870
2871 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2872 (pdev->subsystem_device != 0xe000))
2873 return;
2874
2875 rtl_writephy(tp, 0x1f, 0x0001);
2876 rtl_writephy(tp, 0x10, 0xf01b);
2877 rtl_writephy(tp, 0x1f, 0x0000);
2878}
2879
2880static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2881{
2882 static const struct phy_reg phy_reg_init[] = {
2883 { 0x1f, 0x0001 },
2884 { 0x04, 0x0000 },
2885 { 0x03, 0x00a1 },
2886 { 0x02, 0x0008 },
2887 { 0x01, 0x0120 },
2888 { 0x00, 0x1000 },
2889 { 0x04, 0x0800 },
2890 { 0x04, 0x9000 },
2891 { 0x03, 0x802f },
2892 { 0x02, 0x4f02 },
2893 { 0x01, 0x0409 },
2894 { 0x00, 0xf099 },
2895 { 0x04, 0x9800 },
2896 { 0x04, 0xa000 },
2897 { 0x03, 0xdf01 },
2898 { 0x02, 0xdf20 },
2899 { 0x01, 0xff95 },
2900 { 0x00, 0xba00 },
2901 { 0x04, 0xa800 },
2902 { 0x04, 0xf000 },
2903 { 0x03, 0xdf01 },
2904 { 0x02, 0xdf20 },
2905 { 0x01, 0x101a },
2906 { 0x00, 0xa0ff },
2907 { 0x04, 0xf800 },
2908 { 0x04, 0x0000 },
2909 { 0x1f, 0x0000 },
2910
2911 { 0x1f, 0x0001 },
2912 { 0x10, 0xf41b },
2913 { 0x14, 0xfb54 },
2914 { 0x18, 0xf5c7 },
2915 { 0x1f, 0x0000 },
2916
2917 { 0x1f, 0x0001 },
2918 { 0x17, 0x0cc0 },
2919 { 0x1f, 0x0000 }
2920 };
2921
2922 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2923
2924 rtl8169scd_hw_phy_config_quirk(tp);
2925}
2926
2927static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2928{
2929 static const struct phy_reg phy_reg_init[] = {
2930 { 0x1f, 0x0001 },
2931 { 0x04, 0x0000 },
2932 { 0x03, 0x00a1 },
2933 { 0x02, 0x0008 },
2934 { 0x01, 0x0120 },
2935 { 0x00, 0x1000 },
2936 { 0x04, 0x0800 },
2937 { 0x04, 0x9000 },
2938 { 0x03, 0x802f },
2939 { 0x02, 0x4f02 },
2940 { 0x01, 0x0409 },
2941 { 0x00, 0xf099 },
2942 { 0x04, 0x9800 },
2943 { 0x04, 0xa000 },
2944 { 0x03, 0xdf01 },
2945 { 0x02, 0xdf20 },
2946 { 0x01, 0xff95 },
2947 { 0x00, 0xba00 },
2948 { 0x04, 0xa800 },
2949 { 0x04, 0xf000 },
2950 { 0x03, 0xdf01 },
2951 { 0x02, 0xdf20 },
2952 { 0x01, 0x101a },
2953 { 0x00, 0xa0ff },
2954 { 0x04, 0xf800 },
2955 { 0x04, 0x0000 },
2956 { 0x1f, 0x0000 },
2957
2958 { 0x1f, 0x0001 },
2959 { 0x0b, 0x8480 },
2960 { 0x1f, 0x0000 },
2961
2962 { 0x1f, 0x0001 },
2963 { 0x18, 0x67c7 },
2964 { 0x04, 0x2000 },
2965 { 0x03, 0x002f },
2966 { 0x02, 0x4360 },
2967 { 0x01, 0x0109 },
2968 { 0x00, 0x3022 },
2969 { 0x04, 0x2800 },
2970 { 0x1f, 0x0000 },
2971
2972 { 0x1f, 0x0001 },
2973 { 0x17, 0x0cc0 },
2974 { 0x1f, 0x0000 }
2975 };
2976
2977 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2978}
2979
2980static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2981{
2982 static const struct phy_reg phy_reg_init[] = {
2983 { 0x10, 0xf41b },
2984 { 0x1f, 0x0000 }
2985 };
2986
2987 rtl_writephy(tp, 0x1f, 0x0001);
2988 rtl_patchphy(tp, 0x16, 1 << 0);
2989
2990 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2991}
2992
2993static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2994{
2995 static const struct phy_reg phy_reg_init[] = {
2996 { 0x1f, 0x0001 },
2997 { 0x10, 0xf41b },
2998 { 0x1f, 0x0000 }
2999 };
3000
3001 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3002}
3003
3004static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
3005{
3006 static const struct phy_reg phy_reg_init[] = {
3007 { 0x1f, 0x0000 },
3008 { 0x1d, 0x0f00 },
3009 { 0x1f, 0x0002 },
3010 { 0x0c, 0x1ec8 },
3011 { 0x1f, 0x0000 }
3012 };
3013
3014 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3015}
3016
3017static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
3018{
3019 static const struct phy_reg phy_reg_init[] = {
3020 { 0x1f, 0x0001 },
3021 { 0x1d, 0x3d98 },
3022 { 0x1f, 0x0000 }
3023 };
3024
3025 rtl_writephy(tp, 0x1f, 0x0000);
3026 rtl_patchphy(tp, 0x14, 1 << 5);
3027 rtl_patchphy(tp, 0x0d, 1 << 5);
3028
3029 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3030}
3031
3032static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
3033{
3034 static const struct phy_reg phy_reg_init[] = {
3035 { 0x1f, 0x0001 },
3036 { 0x12, 0x2300 },
3037 { 0x1f, 0x0002 },
3038 { 0x00, 0x88d4 },
3039 { 0x01, 0x82b1 },
3040 { 0x03, 0x7002 },
3041 { 0x08, 0x9e30 },
3042 { 0x09, 0x01f0 },
3043 { 0x0a, 0x5500 },
3044 { 0x0c, 0x00c8 },
3045 { 0x1f, 0x0003 },
3046 { 0x12, 0xc096 },
3047 { 0x16, 0x000a },
3048 { 0x1f, 0x0000 },
3049 { 0x1f, 0x0000 },
3050 { 0x09, 0x2000 },
3051 { 0x09, 0x0000 }
3052 };
3053
3054 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3055
3056 rtl_patchphy(tp, 0x14, 1 << 5);
3057 rtl_patchphy(tp, 0x0d, 1 << 5);
3058 rtl_writephy(tp, 0x1f, 0x0000);
3059}
3060
3061static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
3062{
3063 static const struct phy_reg phy_reg_init[] = {
3064 { 0x1f, 0x0001 },
3065 { 0x12, 0x2300 },
3066 { 0x03, 0x802f },
3067 { 0x02, 0x4f02 },
3068 { 0x01, 0x0409 },
3069 { 0x00, 0xf099 },
3070 { 0x04, 0x9800 },
3071 { 0x04, 0x9000 },
3072 { 0x1d, 0x3d98 },
3073 { 0x1f, 0x0002 },
3074 { 0x0c, 0x7eb8 },
3075 { 0x06, 0x0761 },
3076 { 0x1f, 0x0003 },
3077 { 0x16, 0x0f0a },
3078 { 0x1f, 0x0000 }
3079 };
3080
3081 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3082
3083 rtl_patchphy(tp, 0x16, 1 << 0);
3084 rtl_patchphy(tp, 0x14, 1 << 5);
3085 rtl_patchphy(tp, 0x0d, 1 << 5);
3086 rtl_writephy(tp, 0x1f, 0x0000);
3087}
3088
3089static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
3090{
3091 static const struct phy_reg phy_reg_init[] = {
3092 { 0x1f, 0x0001 },
3093 { 0x12, 0x2300 },
3094 { 0x1d, 0x3d98 },
3095 { 0x1f, 0x0002 },
3096 { 0x0c, 0x7eb8 },
3097 { 0x06, 0x5461 },
3098 { 0x1f, 0x0003 },
3099 { 0x16, 0x0f0a },
3100 { 0x1f, 0x0000 }
3101 };
3102
3103 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3104
3105 rtl_patchphy(tp, 0x16, 1 << 0);
3106 rtl_patchphy(tp, 0x14, 1 << 5);
3107 rtl_patchphy(tp, 0x0d, 1 << 5);
3108 rtl_writephy(tp, 0x1f, 0x0000);
3109}
3110
3111static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
3112{
3113 rtl8168c_3_hw_phy_config(tp);
3114}
3115
3116static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
3117{
3118 static const struct phy_reg phy_reg_init_0[] = {
3119 /* Channel Estimation */
3120 { 0x1f, 0x0001 },
3121 { 0x06, 0x4064 },
3122 { 0x07, 0x2863 },
3123 { 0x08, 0x059c },
3124 { 0x09, 0x26b4 },
3125 { 0x0a, 0x6a19 },
3126 { 0x0b, 0xdcc8 },
3127 { 0x10, 0xf06d },
3128 { 0x14, 0x7f68 },
3129 { 0x18, 0x7fd9 },
3130 { 0x1c, 0xf0ff },
3131 { 0x1d, 0x3d9c },
3132 { 0x1f, 0x0003 },
3133 { 0x12, 0xf49f },
3134 { 0x13, 0x070b },
3135 { 0x1a, 0x05ad },
3136 { 0x14, 0x94c0 },
3137
3138 /*
3139 * Tx Error Issue
3140 * Enhance line driver power
3141 */
3142 { 0x1f, 0x0002 },
3143 { 0x06, 0x5561 },
3144 { 0x1f, 0x0005 },
3145 { 0x05, 0x8332 },
3146 { 0x06, 0x5561 },
3147
3148 /*
3149 * Can not link to 1Gbps with bad cable
3150 * Decrease SNR threshold form 21.07dB to 19.04dB
3151 */
3152 { 0x1f, 0x0001 },
3153 { 0x17, 0x0cc0 },
3154
3155 { 0x1f, 0x0000 },
3156 { 0x0d, 0xf880 }
3157 };
3158
3159 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
3160
3161 /*
3162 * Rx Error Issue
3163 * Fine Tune Switching regulator parameter
3164 */
3165 rtl_writephy(tp, 0x1f, 0x0002);
3166 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
3167 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
3168
3169 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3170 static const struct phy_reg phy_reg_init[] = {
3171 { 0x1f, 0x0002 },
3172 { 0x05, 0x669a },
3173 { 0x1f, 0x0005 },
3174 { 0x05, 0x8330 },
3175 { 0x06, 0x669a },
3176 { 0x1f, 0x0002 }
3177 };
3178 int val;
3179
3180 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3181
3182 val = rtl_readphy(tp, 0x0d);
3183
3184 if ((val & 0x00ff) != 0x006c) {
3185 static const u32 set[] = {
3186 0x0065, 0x0066, 0x0067, 0x0068,
3187 0x0069, 0x006a, 0x006b, 0x006c
3188 };
3189 int i;
3190
3191 rtl_writephy(tp, 0x1f, 0x0002);
3192
3193 val &= 0xff00;
3194 for (i = 0; i < ARRAY_SIZE(set); i++)
3195 rtl_writephy(tp, 0x0d, val | set[i]);
3196 }
3197 } else {
3198 static const struct phy_reg phy_reg_init[] = {
3199 { 0x1f, 0x0002 },
3200 { 0x05, 0x6662 },
3201 { 0x1f, 0x0005 },
3202 { 0x05, 0x8330 },
3203 { 0x06, 0x6662 }
3204 };
3205
3206 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3207 }
3208
3209 /* RSET couple improve */
3210 rtl_writephy(tp, 0x1f, 0x0002);
3211 rtl_patchphy(tp, 0x0d, 0x0300);
3212 rtl_patchphy(tp, 0x0f, 0x0010);
3213
3214 /* Fine tune PLL performance */
3215 rtl_writephy(tp, 0x1f, 0x0002);
3216 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3217 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3218
3219 rtl_writephy(tp, 0x1f, 0x0005);
3220 rtl_writephy(tp, 0x05, 0x001b);
3221
3222 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
3223
3224 rtl_writephy(tp, 0x1f, 0x0000);
3225}
3226
3227static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
3228{
3229 static const struct phy_reg phy_reg_init_0[] = {
3230 /* Channel Estimation */
3231 { 0x1f, 0x0001 },
3232 { 0x06, 0x4064 },
3233 { 0x07, 0x2863 },
3234 { 0x08, 0x059c },
3235 { 0x09, 0x26b4 },
3236 { 0x0a, 0x6a19 },
3237 { 0x0b, 0xdcc8 },
3238 { 0x10, 0xf06d },
3239 { 0x14, 0x7f68 },
3240 { 0x18, 0x7fd9 },
3241 { 0x1c, 0xf0ff },
3242 { 0x1d, 0x3d9c },
3243 { 0x1f, 0x0003 },
3244 { 0x12, 0xf49f },
3245 { 0x13, 0x070b },
3246 { 0x1a, 0x05ad },
3247 { 0x14, 0x94c0 },
3248
3249 /*
3250 * Tx Error Issue
3251 * Enhance line driver power
3252 */
3253 { 0x1f, 0x0002 },
3254 { 0x06, 0x5561 },
3255 { 0x1f, 0x0005 },
3256 { 0x05, 0x8332 },
3257 { 0x06, 0x5561 },
3258
3259 /*
3260 * Can not link to 1Gbps with bad cable
3261 * Decrease SNR threshold form 21.07dB to 19.04dB
3262 */
3263 { 0x1f, 0x0001 },
3264 { 0x17, 0x0cc0 },
3265
3266 { 0x1f, 0x0000 },
3267 { 0x0d, 0xf880 }
3268 };
3269
3270 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
3271
3272 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3273 static const struct phy_reg phy_reg_init[] = {
3274 { 0x1f, 0x0002 },
3275 { 0x05, 0x669a },
3276 { 0x1f, 0x0005 },
3277 { 0x05, 0x8330 },
3278 { 0x06, 0x669a },
3279
3280 { 0x1f, 0x0002 }
3281 };
3282 int val;
3283
3284 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3285
3286 val = rtl_readphy(tp, 0x0d);
3287 if ((val & 0x00ff) != 0x006c) {
3288 static const u32 set[] = {
3289 0x0065, 0x0066, 0x0067, 0x0068,
3290 0x0069, 0x006a, 0x006b, 0x006c
3291 };
3292 int i;
3293
3294 rtl_writephy(tp, 0x1f, 0x0002);
3295
3296 val &= 0xff00;
3297 for (i = 0; i < ARRAY_SIZE(set); i++)
3298 rtl_writephy(tp, 0x0d, val | set[i]);
3299 }
3300 } else {
3301 static const struct phy_reg phy_reg_init[] = {
3302 { 0x1f, 0x0002 },
3303 { 0x05, 0x2642 },
3304 { 0x1f, 0x0005 },
3305 { 0x05, 0x8330 },
3306 { 0x06, 0x2642 }
3307 };
3308
3309 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3310 }
3311
3312 /* Fine tune PLL performance */
3313 rtl_writephy(tp, 0x1f, 0x0002);
3314 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3315 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3316
3317 /* Switching regulator Slew rate */
3318 rtl_writephy(tp, 0x1f, 0x0002);
3319 rtl_patchphy(tp, 0x0f, 0x0017);
3320
3321 rtl_writephy(tp, 0x1f, 0x0005);
3322 rtl_writephy(tp, 0x05, 0x001b);
3323
3324 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
3325
3326 rtl_writephy(tp, 0x1f, 0x0000);
3327}
3328
3329static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
3330{
3331 static const struct phy_reg phy_reg_init[] = {
3332 { 0x1f, 0x0002 },
3333 { 0x10, 0x0008 },
3334 { 0x0d, 0x006c },
3335
3336 { 0x1f, 0x0000 },
3337 { 0x0d, 0xf880 },
3338
3339 { 0x1f, 0x0001 },
3340 { 0x17, 0x0cc0 },
3341
3342 { 0x1f, 0x0001 },
3343 { 0x0b, 0xa4d8 },
3344 { 0x09, 0x281c },
3345 { 0x07, 0x2883 },
3346 { 0x0a, 0x6b35 },
3347 { 0x1d, 0x3da4 },
3348 { 0x1c, 0xeffd },
3349 { 0x14, 0x7f52 },
3350 { 0x18, 0x7fc6 },
3351 { 0x08, 0x0601 },
3352 { 0x06, 0x4063 },
3353 { 0x10, 0xf074 },
3354 { 0x1f, 0x0003 },
3355 { 0x13, 0x0789 },
3356 { 0x12, 0xf4bd },
3357 { 0x1a, 0x04fd },
3358 { 0x14, 0x84b0 },
3359 { 0x1f, 0x0000 },
3360 { 0x00, 0x9200 },
3361
3362 { 0x1f, 0x0005 },
3363 { 0x01, 0x0340 },
3364 { 0x1f, 0x0001 },
3365 { 0x04, 0x4000 },
3366 { 0x03, 0x1d21 },
3367 { 0x02, 0x0c32 },
3368 { 0x01, 0x0200 },
3369 { 0x00, 0x5554 },
3370 { 0x04, 0x4800 },
3371 { 0x04, 0x4000 },
3372 { 0x04, 0xf000 },
3373 { 0x03, 0xdf01 },
3374 { 0x02, 0xdf20 },
3375 { 0x01, 0x101a },
3376 { 0x00, 0xa0ff },
3377 { 0x04, 0xf800 },
3378 { 0x04, 0xf000 },
3379 { 0x1f, 0x0000 },
3380
3381 { 0x1f, 0x0007 },
3382 { 0x1e, 0x0023 },
3383 { 0x16, 0x0000 },
3384 { 0x1f, 0x0000 }
3385 };
3386
3387 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3388}
3389
3390static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3391{
3392 static const struct phy_reg phy_reg_init[] = {
3393 { 0x1f, 0x0001 },
3394 { 0x17, 0x0cc0 },
3395
3396 { 0x1f, 0x0007 },
3397 { 0x1e, 0x002d },
3398 { 0x18, 0x0040 },
3399 { 0x1f, 0x0000 }
3400 };
3401
3402 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3403 rtl_patchphy(tp, 0x0d, 1 << 5);
3404}
3405
3406static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3407{
3408 static const struct phy_reg phy_reg_init[] = {
3409 /* Enable Delay cap */
3410 { 0x1f, 0x0005 },
3411 { 0x05, 0x8b80 },
3412 { 0x06, 0xc896 },
3413 { 0x1f, 0x0000 },
3414
3415 /* Channel estimation fine tune */
3416 { 0x1f, 0x0001 },
3417 { 0x0b, 0x6c20 },
3418 { 0x07, 0x2872 },
3419 { 0x1c, 0xefff },
3420 { 0x1f, 0x0003 },
3421 { 0x14, 0x6420 },
3422 { 0x1f, 0x0000 },
3423
3424 /* Update PFM & 10M TX idle timer */
3425 { 0x1f, 0x0007 },
3426 { 0x1e, 0x002f },
3427 { 0x15, 0x1919 },
3428 { 0x1f, 0x0000 },
3429
3430 { 0x1f, 0x0007 },
3431 { 0x1e, 0x00ac },
3432 { 0x18, 0x0006 },
3433 { 0x1f, 0x0000 }
3434 };
3435
3436 rtl_apply_firmware(tp);
3437
3438 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3439
3440 /* DCO enable for 10M IDLE Power */
3441 rtl_writephy(tp, 0x1f, 0x0007);
3442 rtl_writephy(tp, 0x1e, 0x0023);
3443 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3444 rtl_writephy(tp, 0x1f, 0x0000);
3445
3446 /* For impedance matching */
3447 rtl_writephy(tp, 0x1f, 0x0002);
3448 rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3449 rtl_writephy(tp, 0x1f, 0x0000);
3450
3451 /* PHY auto speed down */
3452 rtl_writephy(tp, 0x1f, 0x0007);
3453 rtl_writephy(tp, 0x1e, 0x002d);
3454 rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3455 rtl_writephy(tp, 0x1f, 0x0000);
3456 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3457
3458 rtl_writephy(tp, 0x1f, 0x0005);
3459 rtl_writephy(tp, 0x05, 0x8b86);
3460 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3461 rtl_writephy(tp, 0x1f, 0x0000);
3462
3463 rtl_writephy(tp, 0x1f, 0x0005);
3464 rtl_writephy(tp, 0x05, 0x8b85);
3465 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3466 rtl_writephy(tp, 0x1f, 0x0007);
3467 rtl_writephy(tp, 0x1e, 0x0020);
3468 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3469 rtl_writephy(tp, 0x1f, 0x0006);
3470 rtl_writephy(tp, 0x00, 0x5a00);
3471 rtl_writephy(tp, 0x1f, 0x0000);
3472 rtl_writephy(tp, 0x0d, 0x0007);
3473 rtl_writephy(tp, 0x0e, 0x003c);
3474 rtl_writephy(tp, 0x0d, 0x4007);
3475 rtl_writephy(tp, 0x0e, 0x0000);
3476 rtl_writephy(tp, 0x0d, 0x0000);
3477}
3478
3479static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3480{
3481 const u16 w[] = {
3482 addr[0] | (addr[1] << 8),
3483 addr[2] | (addr[3] << 8),
3484 addr[4] | (addr[5] << 8)
3485 };
3486 const struct exgmac_reg e[] = {
3487 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3488 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3489 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3490 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3491 };
3492
3493 rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3494}
3495
3496static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3497{
3498 static const struct phy_reg phy_reg_init[] = {
3499 /* Enable Delay cap */
3500 { 0x1f, 0x0004 },
3501 { 0x1f, 0x0007 },
3502 { 0x1e, 0x00ac },
3503 { 0x18, 0x0006 },
3504 { 0x1f, 0x0002 },
3505 { 0x1f, 0x0000 },
3506 { 0x1f, 0x0000 },
3507
3508 /* Channel estimation fine tune */
3509 { 0x1f, 0x0003 },
3510 { 0x09, 0xa20f },
3511 { 0x1f, 0x0000 },
3512 { 0x1f, 0x0000 },
3513
3514 /* Green Setting */
3515 { 0x1f, 0x0005 },
3516 { 0x05, 0x8b5b },
3517 { 0x06, 0x9222 },
3518 { 0x05, 0x8b6d },
3519 { 0x06, 0x8000 },
3520 { 0x05, 0x8b76 },
3521 { 0x06, 0x8000 },
3522 { 0x1f, 0x0000 }
3523 };
3524
3525 rtl_apply_firmware(tp);
3526
3527 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3528
3529 /* For 4-corner performance improve */
3530 rtl_writephy(tp, 0x1f, 0x0005);
3531 rtl_writephy(tp, 0x05, 0x8b80);
3532 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3533 rtl_writephy(tp, 0x1f, 0x0000);
3534
3535 /* PHY auto speed down */
3536 rtl_writephy(tp, 0x1f, 0x0004);
3537 rtl_writephy(tp, 0x1f, 0x0007);
3538 rtl_writephy(tp, 0x1e, 0x002d);
3539 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3540 rtl_writephy(tp, 0x1f, 0x0002);
3541 rtl_writephy(tp, 0x1f, 0x0000);
3542 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3543
3544 /* improve 10M EEE waveform */
3545 rtl_writephy(tp, 0x1f, 0x0005);
3546 rtl_writephy(tp, 0x05, 0x8b86);
3547 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3548 rtl_writephy(tp, 0x1f, 0x0000);
3549
3550 /* Improve 2-pair detection performance */
3551 rtl_writephy(tp, 0x1f, 0x0005);
3552 rtl_writephy(tp, 0x05, 0x8b85);
3553 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3554 rtl_writephy(tp, 0x1f, 0x0000);
3555
3556 /* EEE setting */
3557 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
3558 rtl_writephy(tp, 0x1f, 0x0005);
3559 rtl_writephy(tp, 0x05, 0x8b85);
3560 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3561 rtl_writephy(tp, 0x1f, 0x0004);
3562 rtl_writephy(tp, 0x1f, 0x0007);
3563 rtl_writephy(tp, 0x1e, 0x0020);
3564 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3565 rtl_writephy(tp, 0x1f, 0x0002);
3566 rtl_writephy(tp, 0x1f, 0x0000);
3567 rtl_writephy(tp, 0x0d, 0x0007);
3568 rtl_writephy(tp, 0x0e, 0x003c);
3569 rtl_writephy(tp, 0x0d, 0x4007);
3570 rtl_writephy(tp, 0x0e, 0x0000);
3571 rtl_writephy(tp, 0x0d, 0x0000);
3572
3573 /* Green feature */
3574 rtl_writephy(tp, 0x1f, 0x0003);
3575 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3576 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3577 rtl_writephy(tp, 0x1f, 0x0000);
3578
3579 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3580 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3581}
3582
3583static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3584{
3585 /* For 4-corner performance improve */
3586 rtl_writephy(tp, 0x1f, 0x0005);
3587 rtl_writephy(tp, 0x05, 0x8b80);
3588 rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3589 rtl_writephy(tp, 0x1f, 0x0000);
3590
3591 /* PHY auto speed down */
3592 rtl_writephy(tp, 0x1f, 0x0007);
3593 rtl_writephy(tp, 0x1e, 0x002d);
3594 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3595 rtl_writephy(tp, 0x1f, 0x0000);
3596 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3597
3598 /* Improve 10M EEE waveform */
3599 rtl_writephy(tp, 0x1f, 0x0005);
3600 rtl_writephy(tp, 0x05, 0x8b86);
3601 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3602 rtl_writephy(tp, 0x1f, 0x0000);
3603}
3604
3605static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3606{
3607 static const struct phy_reg phy_reg_init[] = {
3608 /* Channel estimation fine tune */
3609 { 0x1f, 0x0003 },
3610 { 0x09, 0xa20f },
3611 { 0x1f, 0x0000 },
3612
3613 /* Modify green table for giga & fnet */
3614 { 0x1f, 0x0005 },
3615 { 0x05, 0x8b55 },
3616 { 0x06, 0x0000 },
3617 { 0x05, 0x8b5e },
3618 { 0x06, 0x0000 },
3619 { 0x05, 0x8b67 },
3620 { 0x06, 0x0000 },
3621 { 0x05, 0x8b70 },
3622 { 0x06, 0x0000 },
3623 { 0x1f, 0x0000 },
3624 { 0x1f, 0x0007 },
3625 { 0x1e, 0x0078 },
3626 { 0x17, 0x0000 },
3627 { 0x19, 0x00fb },
3628 { 0x1f, 0x0000 },
3629
3630 /* Modify green table for 10M */
3631 { 0x1f, 0x0005 },
3632 { 0x05, 0x8b79 },
3633 { 0x06, 0xaa00 },
3634 { 0x1f, 0x0000 },
3635
3636 /* Disable hiimpedance detection (RTCT) */
3637 { 0x1f, 0x0003 },
3638 { 0x01, 0x328a },
3639 { 0x1f, 0x0000 }
3640 };
3641
3642 rtl_apply_firmware(tp);
3643
3644 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3645
3646 rtl8168f_hw_phy_config(tp);
3647
3648 /* Improve 2-pair detection performance */
3649 rtl_writephy(tp, 0x1f, 0x0005);
3650 rtl_writephy(tp, 0x05, 0x8b85);
3651 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3652 rtl_writephy(tp, 0x1f, 0x0000);
3653}
3654
3655static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3656{
3657 rtl_apply_firmware(tp);
3658
3659 rtl8168f_hw_phy_config(tp);
3660}
3661
3662static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3663{
3664 static const struct phy_reg phy_reg_init[] = {
3665 /* Channel estimation fine tune */
3666 { 0x1f, 0x0003 },
3667 { 0x09, 0xa20f },
3668 { 0x1f, 0x0000 },
3669
3670 /* Modify green table for giga & fnet */
3671 { 0x1f, 0x0005 },
3672 { 0x05, 0x8b55 },
3673 { 0x06, 0x0000 },
3674 { 0x05, 0x8b5e },
3675 { 0x06, 0x0000 },
3676 { 0x05, 0x8b67 },
3677 { 0x06, 0x0000 },
3678 { 0x05, 0x8b70 },
3679 { 0x06, 0x0000 },
3680 { 0x1f, 0x0000 },
3681 { 0x1f, 0x0007 },
3682 { 0x1e, 0x0078 },
3683 { 0x17, 0x0000 },
3684 { 0x19, 0x00aa },
3685 { 0x1f, 0x0000 },
3686
3687 /* Modify green table for 10M */
3688 { 0x1f, 0x0005 },
3689 { 0x05, 0x8b79 },
3690 { 0x06, 0xaa00 },
3691 { 0x1f, 0x0000 },
3692
3693 /* Disable hiimpedance detection (RTCT) */
3694 { 0x1f, 0x0003 },
3695 { 0x01, 0x328a },
3696 { 0x1f, 0x0000 }
3697 };
3698
3699
3700 rtl_apply_firmware(tp);
3701
3702 rtl8168f_hw_phy_config(tp);
3703
3704 /* Improve 2-pair detection performance */
3705 rtl_writephy(tp, 0x1f, 0x0005);
3706 rtl_writephy(tp, 0x05, 0x8b85);
3707 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3708 rtl_writephy(tp, 0x1f, 0x0000);
3709
3710 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3711
3712 /* Modify green table for giga */
3713 rtl_writephy(tp, 0x1f, 0x0005);
3714 rtl_writephy(tp, 0x05, 0x8b54);
3715 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3716 rtl_writephy(tp, 0x05, 0x8b5d);
3717 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3718 rtl_writephy(tp, 0x05, 0x8a7c);
3719 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3720 rtl_writephy(tp, 0x05, 0x8a7f);
3721 rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3722 rtl_writephy(tp, 0x05, 0x8a82);
3723 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3724 rtl_writephy(tp, 0x05, 0x8a85);
3725 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3726 rtl_writephy(tp, 0x05, 0x8a88);
3727 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3728 rtl_writephy(tp, 0x1f, 0x0000);
3729
3730 /* uc same-seed solution */
3731 rtl_writephy(tp, 0x1f, 0x0005);
3732 rtl_writephy(tp, 0x05, 0x8b85);
3733 rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3734 rtl_writephy(tp, 0x1f, 0x0000);
3735
3736 /* eee setting */
3737 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3738 rtl_writephy(tp, 0x1f, 0x0005);
3739 rtl_writephy(tp, 0x05, 0x8b85);
3740 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3741 rtl_writephy(tp, 0x1f, 0x0004);
3742 rtl_writephy(tp, 0x1f, 0x0007);
3743 rtl_writephy(tp, 0x1e, 0x0020);
3744 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3745 rtl_writephy(tp, 0x1f, 0x0000);
3746 rtl_writephy(tp, 0x0d, 0x0007);
3747 rtl_writephy(tp, 0x0e, 0x003c);
3748 rtl_writephy(tp, 0x0d, 0x4007);
3749 rtl_writephy(tp, 0x0e, 0x0000);
3750 rtl_writephy(tp, 0x0d, 0x0000);
3751
3752 /* Green feature */
3753 rtl_writephy(tp, 0x1f, 0x0003);
3754 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3755 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3756 rtl_writephy(tp, 0x1f, 0x0000);
3757}
3758
3759static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3760{
3761 rtl_apply_firmware(tp);
3762
3763 rtl_writephy(tp, 0x1f, 0x0a46);
3764 if (rtl_readphy(tp, 0x10) & 0x0100) {
3765 rtl_writephy(tp, 0x1f, 0x0bcc);
3766 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
3767 } else {
3768 rtl_writephy(tp, 0x1f, 0x0bcc);
3769 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
3770 }
3771
3772 rtl_writephy(tp, 0x1f, 0x0a46);
3773 if (rtl_readphy(tp, 0x13) & 0x0100) {
3774 rtl_writephy(tp, 0x1f, 0x0c41);
3775 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
3776 } else {
3777 rtl_writephy(tp, 0x1f, 0x0c41);
3778 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
3779 }
3780
3781 /* Enable PHY auto speed down */
3782 rtl_writephy(tp, 0x1f, 0x0a44);
3783 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3784
3785 rtl_writephy(tp, 0x1f, 0x0bcc);
3786 rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
3787 rtl_writephy(tp, 0x1f, 0x0a44);
3788 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3789 rtl_writephy(tp, 0x1f, 0x0a43);
3790 rtl_writephy(tp, 0x13, 0x8084);
3791 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3792 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3793
3794 /* EEE auto-fallback function */
3795 rtl_writephy(tp, 0x1f, 0x0a4b);
3796 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3797
3798 /* Enable UC LPF tune function */
3799 rtl_writephy(tp, 0x1f, 0x0a43);
3800 rtl_writephy(tp, 0x13, 0x8012);
3801 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3802
3803 rtl_writephy(tp, 0x1f, 0x0c42);
3804 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3805
3806 /* Improve SWR Efficiency */
3807 rtl_writephy(tp, 0x1f, 0x0bcd);
3808 rtl_writephy(tp, 0x14, 0x5065);
3809 rtl_writephy(tp, 0x14, 0xd065);
3810 rtl_writephy(tp, 0x1f, 0x0bc8);
3811 rtl_writephy(tp, 0x11, 0x5655);
3812 rtl_writephy(tp, 0x1f, 0x0bcd);
3813 rtl_writephy(tp, 0x14, 0x1065);
3814 rtl_writephy(tp, 0x14, 0x9065);
3815 rtl_writephy(tp, 0x14, 0x1065);
3816
3817 /* Check ALDPS bit, disable it if enabled */
3818 rtl_writephy(tp, 0x1f, 0x0a43);
3819 if (rtl_readphy(tp, 0x10) & 0x0004)
3820 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3821
3822 rtl_writephy(tp, 0x1f, 0x0000);
3823}
3824
3825static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3826{
3827 rtl_apply_firmware(tp);
3828}
3829
3830static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3831{
3832 u16 dout_tapbin;
3833 u32 data;
3834
3835 rtl_apply_firmware(tp);
3836
3837 /* CHN EST parameters adjust - giga master */
3838 rtl_writephy(tp, 0x1f, 0x0a43);
3839 rtl_writephy(tp, 0x13, 0x809b);
3840 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3841 rtl_writephy(tp, 0x13, 0x80a2);
3842 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3843 rtl_writephy(tp, 0x13, 0x80a4);
3844 rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3845 rtl_writephy(tp, 0x13, 0x809c);
3846 rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3847 rtl_writephy(tp, 0x1f, 0x0000);
3848
3849 /* CHN EST parameters adjust - giga slave */
3850 rtl_writephy(tp, 0x1f, 0x0a43);
3851 rtl_writephy(tp, 0x13, 0x80ad);
3852 rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3853 rtl_writephy(tp, 0x13, 0x80b4);
3854 rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3855 rtl_writephy(tp, 0x13, 0x80ac);
3856 rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3857 rtl_writephy(tp, 0x1f, 0x0000);
3858
3859 /* CHN EST parameters adjust - fnet */
3860 rtl_writephy(tp, 0x1f, 0x0a43);
3861 rtl_writephy(tp, 0x13, 0x808e);
3862 rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3863 rtl_writephy(tp, 0x13, 0x8090);
3864 rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3865 rtl_writephy(tp, 0x13, 0x8092);
3866 rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3867 rtl_writephy(tp, 0x1f, 0x0000);
3868
3869 /* enable R-tune & PGA-retune function */
3870 dout_tapbin = 0;
3871 rtl_writephy(tp, 0x1f, 0x0a46);
3872 data = rtl_readphy(tp, 0x13);
3873 data &= 3;
3874 data <<= 2;
3875 dout_tapbin |= data;
3876 data = rtl_readphy(tp, 0x12);
3877 data &= 0xc000;
3878 data >>= 14;
3879 dout_tapbin |= data;
3880 dout_tapbin = ~(dout_tapbin^0x08);
3881 dout_tapbin <<= 12;
3882 dout_tapbin &= 0xf000;
3883 rtl_writephy(tp, 0x1f, 0x0a43);
3884 rtl_writephy(tp, 0x13, 0x827a);
3885 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3886 rtl_writephy(tp, 0x13, 0x827b);
3887 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3888 rtl_writephy(tp, 0x13, 0x827c);
3889 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3890 rtl_writephy(tp, 0x13, 0x827d);
3891 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3892
3893 rtl_writephy(tp, 0x1f, 0x0a43);
3894 rtl_writephy(tp, 0x13, 0x0811);
3895 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3896 rtl_writephy(tp, 0x1f, 0x0a42);
3897 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3898 rtl_writephy(tp, 0x1f, 0x0000);
3899
3900 /* enable GPHY 10M */
3901 rtl_writephy(tp, 0x1f, 0x0a44);
3902 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3903 rtl_writephy(tp, 0x1f, 0x0000);
3904
3905 /* SAR ADC performance */
3906 rtl_writephy(tp, 0x1f, 0x0bca);
3907 rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
3908 rtl_writephy(tp, 0x1f, 0x0000);
3909
3910 rtl_writephy(tp, 0x1f, 0x0a43);
3911 rtl_writephy(tp, 0x13, 0x803f);
3912 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3913 rtl_writephy(tp, 0x13, 0x8047);
3914 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3915 rtl_writephy(tp, 0x13, 0x804f);
3916 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3917 rtl_writephy(tp, 0x13, 0x8057);
3918 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3919 rtl_writephy(tp, 0x13, 0x805f);
3920 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3921 rtl_writephy(tp, 0x13, 0x8067);
3922 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3923 rtl_writephy(tp, 0x13, 0x806f);
3924 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3925 rtl_writephy(tp, 0x1f, 0x0000);
3926
3927 /* disable phy pfm mode */
3928 rtl_writephy(tp, 0x1f, 0x0a44);
3929 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3930 rtl_writephy(tp, 0x1f, 0x0000);
3931
3932 /* Check ALDPS bit, disable it if enabled */
3933 rtl_writephy(tp, 0x1f, 0x0a43);
3934 if (rtl_readphy(tp, 0x10) & 0x0004)
3935 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3936
3937 rtl_writephy(tp, 0x1f, 0x0000);
3938}
3939
3940static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3941{
3942 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3943 u16 rlen;
3944 u32 data;
3945
3946 rtl_apply_firmware(tp);
3947
3948 /* CHIN EST parameter update */
3949 rtl_writephy(tp, 0x1f, 0x0a43);
3950 rtl_writephy(tp, 0x13, 0x808a);
3951 rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3952 rtl_writephy(tp, 0x1f, 0x0000);
3953
3954 /* enable R-tune & PGA-retune function */
3955 rtl_writephy(tp, 0x1f, 0x0a43);
3956 rtl_writephy(tp, 0x13, 0x0811);
3957 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3958 rtl_writephy(tp, 0x1f, 0x0a42);
3959 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3960 rtl_writephy(tp, 0x1f, 0x0000);
3961
3962 /* enable GPHY 10M */
3963 rtl_writephy(tp, 0x1f, 0x0a44);
3964 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3965 rtl_writephy(tp, 0x1f, 0x0000);
3966
3967 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3968 data = r8168_mac_ocp_read(tp, 0xdd02);
3969 ioffset_p3 = ((data & 0x80)>>7);
3970 ioffset_p3 <<= 3;
3971
3972 data = r8168_mac_ocp_read(tp, 0xdd00);
3973 ioffset_p3 |= ((data & (0xe000))>>13);
3974 ioffset_p2 = ((data & (0x1e00))>>9);
3975 ioffset_p1 = ((data & (0x01e0))>>5);
3976 ioffset_p0 = ((data & 0x0010)>>4);
3977 ioffset_p0 <<= 3;
3978 ioffset_p0 |= (data & (0x07));
3979 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3980
3981 if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3982 (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
3983 rtl_writephy(tp, 0x1f, 0x0bcf);
3984 rtl_writephy(tp, 0x16, data);
3985 rtl_writephy(tp, 0x1f, 0x0000);
3986 }
3987
3988 /* Modify rlen (TX LPF corner frequency) level */
3989 rtl_writephy(tp, 0x1f, 0x0bcd);
3990 data = rtl_readphy(tp, 0x16);
3991 data &= 0x000f;
3992 rlen = 0;
3993 if (data > 3)
3994 rlen = data - 3;
3995 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3996 rtl_writephy(tp, 0x17, data);
3997 rtl_writephy(tp, 0x1f, 0x0bcd);
3998 rtl_writephy(tp, 0x1f, 0x0000);
3999
4000 /* disable phy pfm mode */
4001 rtl_writephy(tp, 0x1f, 0x0a44);
4002 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
4003 rtl_writephy(tp, 0x1f, 0x0000);
4004
4005 /* Check ALDPS bit, disable it if enabled */
4006 rtl_writephy(tp, 0x1f, 0x0a43);
4007 if (rtl_readphy(tp, 0x10) & 0x0004)
4008 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4009
4010 rtl_writephy(tp, 0x1f, 0x0000);
4011}
4012
4013static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
4014{
4015 /* Enable PHY auto speed down */
4016 rtl_writephy(tp, 0x1f, 0x0a44);
4017 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
4018 rtl_writephy(tp, 0x1f, 0x0000);
4019
4020 /* patch 10M & ALDPS */
4021 rtl_writephy(tp, 0x1f, 0x0bcc);
4022 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
4023 rtl_writephy(tp, 0x1f, 0x0a44);
4024 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
4025 rtl_writephy(tp, 0x1f, 0x0a43);
4026 rtl_writephy(tp, 0x13, 0x8084);
4027 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
4028 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
4029 rtl_writephy(tp, 0x1f, 0x0000);
4030
4031 /* Enable EEE auto-fallback function */
4032 rtl_writephy(tp, 0x1f, 0x0a4b);
4033 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
4034 rtl_writephy(tp, 0x1f, 0x0000);
4035
4036 /* Enable UC LPF tune function */
4037 rtl_writephy(tp, 0x1f, 0x0a43);
4038 rtl_writephy(tp, 0x13, 0x8012);
4039 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
4040 rtl_writephy(tp, 0x1f, 0x0000);
4041
4042 /* set rg_sel_sdm_rate */
4043 rtl_writephy(tp, 0x1f, 0x0c42);
4044 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
4045 rtl_writephy(tp, 0x1f, 0x0000);
4046
4047 /* Check ALDPS bit, disable it if enabled */
4048 rtl_writephy(tp, 0x1f, 0x0a43);
4049 if (rtl_readphy(tp, 0x10) & 0x0004)
4050 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4051
4052 rtl_writephy(tp, 0x1f, 0x0000);
4053}
4054
4055static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
4056{
4057 /* patch 10M & ALDPS */
4058 rtl_writephy(tp, 0x1f, 0x0bcc);
4059 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
4060 rtl_writephy(tp, 0x1f, 0x0a44);
4061 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
4062 rtl_writephy(tp, 0x1f, 0x0a43);
4063 rtl_writephy(tp, 0x13, 0x8084);
4064 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
4065 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
4066 rtl_writephy(tp, 0x1f, 0x0000);
4067
4068 /* Enable UC LPF tune function */
4069 rtl_writephy(tp, 0x1f, 0x0a43);
4070 rtl_writephy(tp, 0x13, 0x8012);
4071 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
4072 rtl_writephy(tp, 0x1f, 0x0000);
4073
4074 /* Set rg_sel_sdm_rate */
4075 rtl_writephy(tp, 0x1f, 0x0c42);
4076 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
4077 rtl_writephy(tp, 0x1f, 0x0000);
4078
4079 /* Channel estimation parameters */
4080 rtl_writephy(tp, 0x1f, 0x0a43);
4081 rtl_writephy(tp, 0x13, 0x80f3);
4082 rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
4083 rtl_writephy(tp, 0x13, 0x80f0);
4084 rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
4085 rtl_writephy(tp, 0x13, 0x80ef);
4086 rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
4087 rtl_writephy(tp, 0x13, 0x80f6);
4088 rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
4089 rtl_writephy(tp, 0x13, 0x80ec);
4090 rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
4091 rtl_writephy(tp, 0x13, 0x80ed);
4092 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4093 rtl_writephy(tp, 0x13, 0x80f2);
4094 rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
4095 rtl_writephy(tp, 0x13, 0x80f4);
4096 rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
4097 rtl_writephy(tp, 0x1f, 0x0a43);
4098 rtl_writephy(tp, 0x13, 0x8110);
4099 rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
4100 rtl_writephy(tp, 0x13, 0x810f);
4101 rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
4102 rtl_writephy(tp, 0x13, 0x8111);
4103 rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
4104 rtl_writephy(tp, 0x13, 0x8113);
4105 rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
4106 rtl_writephy(tp, 0x13, 0x8115);
4107 rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
4108 rtl_writephy(tp, 0x13, 0x810e);
4109 rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
4110 rtl_writephy(tp, 0x13, 0x810c);
4111 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4112 rtl_writephy(tp, 0x13, 0x810b);
4113 rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
4114 rtl_writephy(tp, 0x1f, 0x0a43);
4115 rtl_writephy(tp, 0x13, 0x80d1);
4116 rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
4117 rtl_writephy(tp, 0x13, 0x80cd);
4118 rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
4119 rtl_writephy(tp, 0x13, 0x80d3);
4120 rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
4121 rtl_writephy(tp, 0x13, 0x80d5);
4122 rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
4123 rtl_writephy(tp, 0x13, 0x80d7);
4124 rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
4125
4126 /* Force PWM-mode */
4127 rtl_writephy(tp, 0x1f, 0x0bcd);
4128 rtl_writephy(tp, 0x14, 0x5065);
4129 rtl_writephy(tp, 0x14, 0xd065);
4130 rtl_writephy(tp, 0x1f, 0x0bc8);
4131 rtl_writephy(tp, 0x12, 0x00ed);
4132 rtl_writephy(tp, 0x1f, 0x0bcd);
4133 rtl_writephy(tp, 0x14, 0x1065);
4134 rtl_writephy(tp, 0x14, 0x9065);
4135 rtl_writephy(tp, 0x14, 0x1065);
4136 rtl_writephy(tp, 0x1f, 0x0000);
4137
4138 /* Check ALDPS bit, disable it if enabled */
4139 rtl_writephy(tp, 0x1f, 0x0a43);
4140 if (rtl_readphy(tp, 0x10) & 0x0004)
4141 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4142
4143 rtl_writephy(tp, 0x1f, 0x0000);
4144}
4145
4146static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
4147{
4148 static const struct phy_reg phy_reg_init[] = {
4149 { 0x1f, 0x0003 },
4150 { 0x08, 0x441d },
4151 { 0x01, 0x9100 },
4152 { 0x1f, 0x0000 }
4153 };
4154
4155 rtl_writephy(tp, 0x1f, 0x0000);
4156 rtl_patchphy(tp, 0x11, 1 << 12);
4157 rtl_patchphy(tp, 0x19, 1 << 13);
4158 rtl_patchphy(tp, 0x10, 1 << 15);
4159
4160 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4161}
4162
4163static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
4164{
4165 static const struct phy_reg phy_reg_init[] = {
4166 { 0x1f, 0x0005 },
4167 { 0x1a, 0x0000 },
4168 { 0x1f, 0x0000 },
4169
4170 { 0x1f, 0x0004 },
4171 { 0x1c, 0x0000 },
4172 { 0x1f, 0x0000 },
4173
4174 { 0x1f, 0x0001 },
4175 { 0x15, 0x7701 },
4176 { 0x1f, 0x0000 }
4177 };
4178
4179 /* Disable ALDPS before ram code */
4180 rtl_writephy(tp, 0x1f, 0x0000);
4181 rtl_writephy(tp, 0x18, 0x0310);
4182 msleep(100);
4183
4184 rtl_apply_firmware(tp);
4185
4186 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4187}
4188
4189static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
4190{
4191 /* Disable ALDPS before setting firmware */
4192 rtl_writephy(tp, 0x1f, 0x0000);
4193 rtl_writephy(tp, 0x18, 0x0310);
4194 msleep(20);
4195
4196 rtl_apply_firmware(tp);
4197
4198 /* EEE setting */
4199 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4200 rtl_writephy(tp, 0x1f, 0x0004);
4201 rtl_writephy(tp, 0x10, 0x401f);
4202 rtl_writephy(tp, 0x19, 0x7030);
4203 rtl_writephy(tp, 0x1f, 0x0000);
4204}
4205
4206static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
4207{
4208 static const struct phy_reg phy_reg_init[] = {
4209 { 0x1f, 0x0004 },
4210 { 0x10, 0xc07f },
4211 { 0x19, 0x7030 },
4212 { 0x1f, 0x0000 }
4213 };
4214
4215 /* Disable ALDPS before ram code */
4216 rtl_writephy(tp, 0x1f, 0x0000);
4217 rtl_writephy(tp, 0x18, 0x0310);
4218 msleep(100);
4219
4220 rtl_apply_firmware(tp);
4221
4222 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4223 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4224
4225 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4226}
4227
4228static void rtl_hw_phy_config(struct net_device *dev)
4229{
4230 struct rtl8169_private *tp = netdev_priv(dev);
4231
4232 rtl8169_print_mac_version(tp);
4233
4234 switch (tp->mac_version) {
4235 case RTL_GIGA_MAC_VER_01:
4236 break;
4237 case RTL_GIGA_MAC_VER_02:
4238 case RTL_GIGA_MAC_VER_03:
4239 rtl8169s_hw_phy_config(tp);
4240 break;
4241 case RTL_GIGA_MAC_VER_04:
4242 rtl8169sb_hw_phy_config(tp);
4243 break;
4244 case RTL_GIGA_MAC_VER_05:
4245 rtl8169scd_hw_phy_config(tp);
4246 break;
4247 case RTL_GIGA_MAC_VER_06:
4248 rtl8169sce_hw_phy_config(tp);
4249 break;
4250 case RTL_GIGA_MAC_VER_07:
4251 case RTL_GIGA_MAC_VER_08:
4252 case RTL_GIGA_MAC_VER_09:
4253 rtl8102e_hw_phy_config(tp);
4254 break;
4255 case RTL_GIGA_MAC_VER_11:
4256 rtl8168bb_hw_phy_config(tp);
4257 break;
4258 case RTL_GIGA_MAC_VER_12:
4259 rtl8168bef_hw_phy_config(tp);
4260 break;
4261 case RTL_GIGA_MAC_VER_17:
4262 rtl8168bef_hw_phy_config(tp);
4263 break;
4264 case RTL_GIGA_MAC_VER_18:
4265 rtl8168cp_1_hw_phy_config(tp);
4266 break;
4267 case RTL_GIGA_MAC_VER_19:
4268 rtl8168c_1_hw_phy_config(tp);
4269 break;
4270 case RTL_GIGA_MAC_VER_20:
4271 rtl8168c_2_hw_phy_config(tp);
4272 break;
4273 case RTL_GIGA_MAC_VER_21:
4274 rtl8168c_3_hw_phy_config(tp);
4275 break;
4276 case RTL_GIGA_MAC_VER_22:
4277 rtl8168c_4_hw_phy_config(tp);
4278 break;
4279 case RTL_GIGA_MAC_VER_23:
4280 case RTL_GIGA_MAC_VER_24:
4281 rtl8168cp_2_hw_phy_config(tp);
4282 break;
4283 case RTL_GIGA_MAC_VER_25:
4284 rtl8168d_1_hw_phy_config(tp);
4285 break;
4286 case RTL_GIGA_MAC_VER_26:
4287 rtl8168d_2_hw_phy_config(tp);
4288 break;
4289 case RTL_GIGA_MAC_VER_27:
4290 rtl8168d_3_hw_phy_config(tp);
4291 break;
4292 case RTL_GIGA_MAC_VER_28:
4293 rtl8168d_4_hw_phy_config(tp);
4294 break;
4295 case RTL_GIGA_MAC_VER_29:
4296 case RTL_GIGA_MAC_VER_30:
4297 rtl8105e_hw_phy_config(tp);
4298 break;
4299 case RTL_GIGA_MAC_VER_31:
4300 /* None. */
4301 break;
4302 case RTL_GIGA_MAC_VER_32:
4303 case RTL_GIGA_MAC_VER_33:
4304 rtl8168e_1_hw_phy_config(tp);
4305 break;
4306 case RTL_GIGA_MAC_VER_34:
4307 rtl8168e_2_hw_phy_config(tp);
4308 break;
4309 case RTL_GIGA_MAC_VER_35:
4310 rtl8168f_1_hw_phy_config(tp);
4311 break;
4312 case RTL_GIGA_MAC_VER_36:
4313 rtl8168f_2_hw_phy_config(tp);
4314 break;
4315
4316 case RTL_GIGA_MAC_VER_37:
4317 rtl8402_hw_phy_config(tp);
4318 break;
4319
4320 case RTL_GIGA_MAC_VER_38:
4321 rtl8411_hw_phy_config(tp);
4322 break;
4323
4324 case RTL_GIGA_MAC_VER_39:
4325 rtl8106e_hw_phy_config(tp);
4326 break;
4327
4328 case RTL_GIGA_MAC_VER_40:
4329 rtl8168g_1_hw_phy_config(tp);
4330 break;
4331 case RTL_GIGA_MAC_VER_42:
4332 case RTL_GIGA_MAC_VER_43:
4333 case RTL_GIGA_MAC_VER_44:
4334 rtl8168g_2_hw_phy_config(tp);
4335 break;
4336 case RTL_GIGA_MAC_VER_45:
4337 case RTL_GIGA_MAC_VER_47:
4338 rtl8168h_1_hw_phy_config(tp);
4339 break;
4340 case RTL_GIGA_MAC_VER_46:
4341 case RTL_GIGA_MAC_VER_48:
4342 rtl8168h_2_hw_phy_config(tp);
4343 break;
4344
4345 case RTL_GIGA_MAC_VER_49:
4346 rtl8168ep_1_hw_phy_config(tp);
4347 break;
4348 case RTL_GIGA_MAC_VER_50:
4349 case RTL_GIGA_MAC_VER_51:
4350 rtl8168ep_2_hw_phy_config(tp);
4351 break;
4352
4353 case RTL_GIGA_MAC_VER_41:
4354 default:
4355 break;
4356 }
4357}
4358
4359static void rtl_phy_work(struct rtl8169_private *tp)
4360{
4361 struct timer_list *timer = &tp->timer;
4362 void __iomem *ioaddr = tp->mmio_addr;
4363 unsigned long timeout = RTL8169_PHY_TIMEOUT;
4364
4365 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
4366
4367 if (tp->phy_reset_pending(tp)) {
4368 /*
4369 * A busy loop could burn quite a few cycles on nowadays CPU.
4370 * Let's delay the execution of the timer for a few ticks.
4371 */
4372 timeout = HZ/10;
4373 goto out_mod_timer;
4374 }
4375
4376 if (tp->link_ok(ioaddr))
4377 return;
4378
4379 netif_dbg(tp, link, tp->dev, "PHY reset until link up\n");
4380
4381 tp->phy_reset_enable(tp);
4382
4383out_mod_timer:
4384 mod_timer(timer, jiffies + timeout);
4385}
4386
4387static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4388{
4389 if (!test_and_set_bit(flag, tp->wk.flags))
4390 schedule_work(&tp->wk.work);
4391}
4392
4393static void rtl8169_phy_timer(unsigned long __opaque)
4394{
4395 struct net_device *dev = (struct net_device *)__opaque;
4396 struct rtl8169_private *tp = netdev_priv(dev);
4397
4398 rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
4399}
4400
4401static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
4402 void __iomem *ioaddr)
4403{
4404 iounmap(ioaddr);
4405 pci_release_regions(pdev);
4406 pci_clear_mwi(pdev);
4407 pci_disable_device(pdev);
4408 free_netdev(dev);
4409}
4410
4411DECLARE_RTL_COND(rtl_phy_reset_cond)
4412{
4413 return tp->phy_reset_pending(tp);
4414}
4415
4416static void rtl8169_phy_reset(struct net_device *dev,
4417 struct rtl8169_private *tp)
4418{
4419 tp->phy_reset_enable(tp);
4420 rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
4421}
4422
4423static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4424{
4425 void __iomem *ioaddr = tp->mmio_addr;
4426
4427 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
4428 (RTL_R8(PHYstatus) & TBI_Enable);
4429}
4430
4431static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4432{
4433 void __iomem *ioaddr = tp->mmio_addr;
4434
4435 rtl_hw_phy_config(dev);
4436
4437 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4438 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4439 RTL_W8(0x82, 0x01);
4440 }
4441
4442 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4443
4444 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4445 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4446
4447 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4448 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4449 RTL_W8(0x82, 0x01);
4450 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4451 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4452 }
4453
4454 rtl8169_phy_reset(dev, tp);
4455
4456 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4457 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4458 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4459 (tp->mii.supports_gmii ?
4460 ADVERTISED_1000baseT_Half |
4461 ADVERTISED_1000baseT_Full : 0));
4462
4463 if (rtl_tbi_enabled(tp))
4464 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4465}
4466
4467static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4468{
4469 void __iomem *ioaddr = tp->mmio_addr;
4470
4471 rtl_lock_work(tp);
4472
4473 RTL_W8(Cfg9346, Cfg9346_Unlock);
4474
4475 RTL_W32(MAC4, addr[4] | addr[5] << 8);
4476 RTL_R32(MAC4);
4477
4478 RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4479 RTL_R32(MAC0);
4480
4481 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4482 rtl_rar_exgmac_set(tp, addr);
4483
4484 RTL_W8(Cfg9346, Cfg9346_Lock);
4485
4486 rtl_unlock_work(tp);
4487}
4488
4489static int rtl_set_mac_address(struct net_device *dev, void *p)
4490{
4491 struct rtl8169_private *tp = netdev_priv(dev);
4492 struct device *d = &tp->pci_dev->dev;
4493 struct sockaddr *addr = p;
4494
4495 if (!is_valid_ether_addr(addr->sa_data))
4496 return -EADDRNOTAVAIL;
4497
4498 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
4499
4500 pm_runtime_get_noresume(d);
4501
4502 if (pm_runtime_active(d))
4503 rtl_rar_set(tp, dev->dev_addr);
4504
4505 pm_runtime_put_noidle(d);
4506
4507 return 0;
4508}
4509
4510static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4511{
4512 struct rtl8169_private *tp = netdev_priv(dev);
4513 struct mii_ioctl_data *data = if_mii(ifr);
4514
4515 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
4516}
4517
4518static int rtl_xmii_ioctl(struct rtl8169_private *tp,
4519 struct mii_ioctl_data *data, int cmd)
4520{
4521 switch (cmd) {
4522 case SIOCGMIIPHY:
4523 data->phy_id = 32; /* Internal PHY */
4524 return 0;
4525
4526 case SIOCGMIIREG:
4527 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
4528 return 0;
4529
4530 case SIOCSMIIREG:
4531 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
4532 return 0;
4533 }
4534 return -EOPNOTSUPP;
4535}
4536
4537static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
4538{
4539 return -EOPNOTSUPP;
4540}
4541
4542static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
4543{
4544 if (tp->features & RTL_FEATURE_MSI) {
4545 pci_disable_msi(pdev);
4546 tp->features &= ~RTL_FEATURE_MSI;
4547 }
4548}
4549
4550static void rtl_init_mdio_ops(struct rtl8169_private *tp)
4551{
4552 struct mdio_ops *ops = &tp->mdio_ops;
4553
4554 switch (tp->mac_version) {
4555 case RTL_GIGA_MAC_VER_27:
4556 ops->write = r8168dp_1_mdio_write;
4557 ops->read = r8168dp_1_mdio_read;
4558 break;
4559 case RTL_GIGA_MAC_VER_28:
4560 case RTL_GIGA_MAC_VER_31:
4561 ops->write = r8168dp_2_mdio_write;
4562 ops->read = r8168dp_2_mdio_read;
4563 break;
4564 case RTL_GIGA_MAC_VER_40:
4565 case RTL_GIGA_MAC_VER_41:
4566 case RTL_GIGA_MAC_VER_42:
4567 case RTL_GIGA_MAC_VER_43:
4568 case RTL_GIGA_MAC_VER_44:
4569 case RTL_GIGA_MAC_VER_45:
4570 case RTL_GIGA_MAC_VER_46:
4571 case RTL_GIGA_MAC_VER_47:
4572 case RTL_GIGA_MAC_VER_48:
4573 case RTL_GIGA_MAC_VER_49:
4574 case RTL_GIGA_MAC_VER_50:
4575 case RTL_GIGA_MAC_VER_51:
4576 ops->write = r8168g_mdio_write;
4577 ops->read = r8168g_mdio_read;
4578 break;
4579 default:
4580 ops->write = r8169_mdio_write;
4581 ops->read = r8169_mdio_read;
4582 break;
4583 }
4584}
4585
4586static void rtl_speed_down(struct rtl8169_private *tp)
4587{
4588 u32 adv;
4589 int lpa;
4590
4591 rtl_writephy(tp, 0x1f, 0x0000);
4592 lpa = rtl_readphy(tp, MII_LPA);
4593
4594 if (lpa & (LPA_10HALF | LPA_10FULL))
4595 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
4596 else if (lpa & (LPA_100HALF | LPA_100FULL))
4597 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4598 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4599 else
4600 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4601 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4602 (tp->mii.supports_gmii ?
4603 ADVERTISED_1000baseT_Half |
4604 ADVERTISED_1000baseT_Full : 0);
4605
4606 rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4607 adv);
4608}
4609
4610static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4611{
4612 void __iomem *ioaddr = tp->mmio_addr;
4613
4614 switch (tp->mac_version) {
4615 case RTL_GIGA_MAC_VER_25:
4616 case RTL_GIGA_MAC_VER_26:
4617 case RTL_GIGA_MAC_VER_29:
4618 case RTL_GIGA_MAC_VER_30:
4619 case RTL_GIGA_MAC_VER_32:
4620 case RTL_GIGA_MAC_VER_33:
4621 case RTL_GIGA_MAC_VER_34:
4622 case RTL_GIGA_MAC_VER_37:
4623 case RTL_GIGA_MAC_VER_38:
4624 case RTL_GIGA_MAC_VER_39:
4625 case RTL_GIGA_MAC_VER_40:
4626 case RTL_GIGA_MAC_VER_41:
4627 case RTL_GIGA_MAC_VER_42:
4628 case RTL_GIGA_MAC_VER_43:
4629 case RTL_GIGA_MAC_VER_44:
4630 case RTL_GIGA_MAC_VER_45:
4631 case RTL_GIGA_MAC_VER_46:
4632 case RTL_GIGA_MAC_VER_47:
4633 case RTL_GIGA_MAC_VER_48:
4634 case RTL_GIGA_MAC_VER_49:
4635 case RTL_GIGA_MAC_VER_50:
4636 case RTL_GIGA_MAC_VER_51:
4637 RTL_W32(RxConfig, RTL_R32(RxConfig) |
4638 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4639 break;
4640 default:
4641 break;
4642 }
4643}
4644
4645static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4646{
4647 if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
4648 return false;
4649
4650 rtl_speed_down(tp);
4651 rtl_wol_suspend_quirk(tp);
4652
4653 return true;
4654}
4655
4656static void r810x_phy_power_down(struct rtl8169_private *tp)
4657{
4658 rtl_writephy(tp, 0x1f, 0x0000);
4659 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4660}
4661
4662static void r810x_phy_power_up(struct rtl8169_private *tp)
4663{
4664 rtl_writephy(tp, 0x1f, 0x0000);
4665 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4666}
4667
4668static void r810x_pll_power_down(struct rtl8169_private *tp)
4669{
4670 void __iomem *ioaddr = tp->mmio_addr;
4671
4672 if (rtl_wol_pll_power_down(tp))
4673 return;
4674
4675 r810x_phy_power_down(tp);
4676
4677 switch (tp->mac_version) {
4678 case RTL_GIGA_MAC_VER_07:
4679 case RTL_GIGA_MAC_VER_08:
4680 case RTL_GIGA_MAC_VER_09:
4681 case RTL_GIGA_MAC_VER_10:
4682 case RTL_GIGA_MAC_VER_13:
4683 case RTL_GIGA_MAC_VER_16:
4684 break;
4685 default:
4686 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4687 break;
4688 }
4689}
4690
4691static void r810x_pll_power_up(struct rtl8169_private *tp)
4692{
4693 void __iomem *ioaddr = tp->mmio_addr;
4694
4695 r810x_phy_power_up(tp);
4696
4697 switch (tp->mac_version) {
4698 case RTL_GIGA_MAC_VER_07:
4699 case RTL_GIGA_MAC_VER_08:
4700 case RTL_GIGA_MAC_VER_09:
4701 case RTL_GIGA_MAC_VER_10:
4702 case RTL_GIGA_MAC_VER_13:
4703 case RTL_GIGA_MAC_VER_16:
4704 break;
4705 case RTL_GIGA_MAC_VER_47:
4706 case RTL_GIGA_MAC_VER_48:
4707 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4708 break;
4709 default:
4710 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4711 break;
4712 }
4713}
4714
4715static void r8168_phy_power_up(struct rtl8169_private *tp)
4716{
4717 rtl_writephy(tp, 0x1f, 0x0000);
4718 switch (tp->mac_version) {
4719 case RTL_GIGA_MAC_VER_11:
4720 case RTL_GIGA_MAC_VER_12:
4721 case RTL_GIGA_MAC_VER_17:
4722 case RTL_GIGA_MAC_VER_18:
4723 case RTL_GIGA_MAC_VER_19:
4724 case RTL_GIGA_MAC_VER_20:
4725 case RTL_GIGA_MAC_VER_21:
4726 case RTL_GIGA_MAC_VER_22:
4727 case RTL_GIGA_MAC_VER_23:
4728 case RTL_GIGA_MAC_VER_24:
4729 case RTL_GIGA_MAC_VER_25:
4730 case RTL_GIGA_MAC_VER_26:
4731 case RTL_GIGA_MAC_VER_27:
4732 case RTL_GIGA_MAC_VER_28:
4733 case RTL_GIGA_MAC_VER_31:
4734 rtl_writephy(tp, 0x0e, 0x0000);
4735 break;
4736 default:
4737 break;
4738 }
4739 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4740}
4741
4742static void r8168_phy_power_down(struct rtl8169_private *tp)
4743{
4744 rtl_writephy(tp, 0x1f, 0x0000);
4745 switch (tp->mac_version) {
4746 case RTL_GIGA_MAC_VER_32:
4747 case RTL_GIGA_MAC_VER_33:
4748 case RTL_GIGA_MAC_VER_40:
4749 case RTL_GIGA_MAC_VER_41:
4750 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
4751 break;
4752
4753 case RTL_GIGA_MAC_VER_11:
4754 case RTL_GIGA_MAC_VER_12:
4755 case RTL_GIGA_MAC_VER_17:
4756 case RTL_GIGA_MAC_VER_18:
4757 case RTL_GIGA_MAC_VER_19:
4758 case RTL_GIGA_MAC_VER_20:
4759 case RTL_GIGA_MAC_VER_21:
4760 case RTL_GIGA_MAC_VER_22:
4761 case RTL_GIGA_MAC_VER_23:
4762 case RTL_GIGA_MAC_VER_24:
4763 case RTL_GIGA_MAC_VER_25:
4764 case RTL_GIGA_MAC_VER_26:
4765 case RTL_GIGA_MAC_VER_27:
4766 case RTL_GIGA_MAC_VER_28:
4767 case RTL_GIGA_MAC_VER_31:
4768 rtl_writephy(tp, 0x0e, 0x0200);
4769 default:
4770 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4771 break;
4772 }
4773}
4774
4775static void r8168_pll_power_down(struct rtl8169_private *tp)
4776{
4777 void __iomem *ioaddr = tp->mmio_addr;
4778
4779 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4780 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4781 tp->mac_version == RTL_GIGA_MAC_VER_31 ||
4782 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
4783 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
4784 tp->mac_version == RTL_GIGA_MAC_VER_51) &&
4785 r8168_check_dash(tp)) {
4786 return;
4787 }
4788
4789 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
4790 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
4791 (RTL_R16(CPlusCmd) & ASF)) {
4792 return;
4793 }
4794
4795 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4796 tp->mac_version == RTL_GIGA_MAC_VER_33)
4797 rtl_ephy_write(tp, 0x19, 0xff64);
4798
4799 if (rtl_wol_pll_power_down(tp))
4800 return;
4801
4802 r8168_phy_power_down(tp);
4803
4804 switch (tp->mac_version) {
4805 case RTL_GIGA_MAC_VER_25:
4806 case RTL_GIGA_MAC_VER_26:
4807 case RTL_GIGA_MAC_VER_27:
4808 case RTL_GIGA_MAC_VER_28:
4809 case RTL_GIGA_MAC_VER_31:
4810 case RTL_GIGA_MAC_VER_32:
4811 case RTL_GIGA_MAC_VER_33:
4812 case RTL_GIGA_MAC_VER_44:
4813 case RTL_GIGA_MAC_VER_45:
4814 case RTL_GIGA_MAC_VER_46:
4815 case RTL_GIGA_MAC_VER_50:
4816 case RTL_GIGA_MAC_VER_51:
4817 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4818 break;
4819 case RTL_GIGA_MAC_VER_40:
4820 case RTL_GIGA_MAC_VER_41:
4821 case RTL_GIGA_MAC_VER_49:
4822 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4823 0xfc000000, ERIAR_EXGMAC);
4824 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4825 break;
4826 }
4827}
4828
4829static void r8168_pll_power_up(struct rtl8169_private *tp)
4830{
4831 void __iomem *ioaddr = tp->mmio_addr;
4832
4833 switch (tp->mac_version) {
4834 case RTL_GIGA_MAC_VER_25:
4835 case RTL_GIGA_MAC_VER_26:
4836 case RTL_GIGA_MAC_VER_27:
4837 case RTL_GIGA_MAC_VER_28:
4838 case RTL_GIGA_MAC_VER_31:
4839 case RTL_GIGA_MAC_VER_32:
4840 case RTL_GIGA_MAC_VER_33:
4841 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4842 break;
4843 case RTL_GIGA_MAC_VER_44:
4844 case RTL_GIGA_MAC_VER_45:
4845 case RTL_GIGA_MAC_VER_46:
4846 case RTL_GIGA_MAC_VER_50:
4847 case RTL_GIGA_MAC_VER_51:
4848 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4849 break;
4850 case RTL_GIGA_MAC_VER_40:
4851 case RTL_GIGA_MAC_VER_41:
4852 case RTL_GIGA_MAC_VER_49:
4853 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4854 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4855 0x00000000, ERIAR_EXGMAC);
4856 break;
4857 }
4858
4859 r8168_phy_power_up(tp);
4860}
4861
4862static void rtl_generic_op(struct rtl8169_private *tp,
4863 void (*op)(struct rtl8169_private *))
4864{
4865 if (op)
4866 op(tp);
4867}
4868
4869static void rtl_pll_power_down(struct rtl8169_private *tp)
4870{
4871 rtl_generic_op(tp, tp->pll_power_ops.down);
4872}
4873
4874static void rtl_pll_power_up(struct rtl8169_private *tp)
4875{
4876 rtl_generic_op(tp, tp->pll_power_ops.up);
4877}
4878
4879static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
4880{
4881 struct pll_power_ops *ops = &tp->pll_power_ops;
4882
4883 switch (tp->mac_version) {
4884 case RTL_GIGA_MAC_VER_07:
4885 case RTL_GIGA_MAC_VER_08:
4886 case RTL_GIGA_MAC_VER_09:
4887 case RTL_GIGA_MAC_VER_10:
4888 case RTL_GIGA_MAC_VER_16:
4889 case RTL_GIGA_MAC_VER_29:
4890 case RTL_GIGA_MAC_VER_30:
4891 case RTL_GIGA_MAC_VER_37:
4892 case RTL_GIGA_MAC_VER_39:
4893 case RTL_GIGA_MAC_VER_43:
4894 case RTL_GIGA_MAC_VER_47:
4895 case RTL_GIGA_MAC_VER_48:
4896 ops->down = r810x_pll_power_down;
4897 ops->up = r810x_pll_power_up;
4898 break;
4899
4900 case RTL_GIGA_MAC_VER_11:
4901 case RTL_GIGA_MAC_VER_12:
4902 case RTL_GIGA_MAC_VER_17:
4903 case RTL_GIGA_MAC_VER_18:
4904 case RTL_GIGA_MAC_VER_19:
4905 case RTL_GIGA_MAC_VER_20:
4906 case RTL_GIGA_MAC_VER_21:
4907 case RTL_GIGA_MAC_VER_22:
4908 case RTL_GIGA_MAC_VER_23:
4909 case RTL_GIGA_MAC_VER_24:
4910 case RTL_GIGA_MAC_VER_25:
4911 case RTL_GIGA_MAC_VER_26:
4912 case RTL_GIGA_MAC_VER_27:
4913 case RTL_GIGA_MAC_VER_28:
4914 case RTL_GIGA_MAC_VER_31:
4915 case RTL_GIGA_MAC_VER_32:
4916 case RTL_GIGA_MAC_VER_33:
4917 case RTL_GIGA_MAC_VER_34:
4918 case RTL_GIGA_MAC_VER_35:
4919 case RTL_GIGA_MAC_VER_36:
4920 case RTL_GIGA_MAC_VER_38:
4921 case RTL_GIGA_MAC_VER_40:
4922 case RTL_GIGA_MAC_VER_41:
4923 case RTL_GIGA_MAC_VER_42:
4924 case RTL_GIGA_MAC_VER_44:
4925 case RTL_GIGA_MAC_VER_45:
4926 case RTL_GIGA_MAC_VER_46:
4927 case RTL_GIGA_MAC_VER_49:
4928 case RTL_GIGA_MAC_VER_50:
4929 case RTL_GIGA_MAC_VER_51:
4930 ops->down = r8168_pll_power_down;
4931 ops->up = r8168_pll_power_up;
4932 break;
4933
4934 default:
4935 ops->down = NULL;
4936 ops->up = NULL;
4937 break;
4938 }
4939}
4940
4941static void rtl_init_rxcfg(struct rtl8169_private *tp)
4942{
4943 void __iomem *ioaddr = tp->mmio_addr;
4944
4945 switch (tp->mac_version) {
4946 case RTL_GIGA_MAC_VER_01:
4947 case RTL_GIGA_MAC_VER_02:
4948 case RTL_GIGA_MAC_VER_03:
4949 case RTL_GIGA_MAC_VER_04:
4950 case RTL_GIGA_MAC_VER_05:
4951 case RTL_GIGA_MAC_VER_06:
4952 case RTL_GIGA_MAC_VER_10:
4953 case RTL_GIGA_MAC_VER_11:
4954 case RTL_GIGA_MAC_VER_12:
4955 case RTL_GIGA_MAC_VER_13:
4956 case RTL_GIGA_MAC_VER_14:
4957 case RTL_GIGA_MAC_VER_15:
4958 case RTL_GIGA_MAC_VER_16:
4959 case RTL_GIGA_MAC_VER_17:
4960 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4961 break;
4962 case RTL_GIGA_MAC_VER_18:
4963 case RTL_GIGA_MAC_VER_19:
4964 case RTL_GIGA_MAC_VER_20:
4965 case RTL_GIGA_MAC_VER_21:
4966 case RTL_GIGA_MAC_VER_22:
4967 case RTL_GIGA_MAC_VER_23:
4968 case RTL_GIGA_MAC_VER_24:
4969 case RTL_GIGA_MAC_VER_34:
4970 case RTL_GIGA_MAC_VER_35:
4971 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4972 break;
4973 case RTL_GIGA_MAC_VER_40:
4974 case RTL_GIGA_MAC_VER_41:
4975 case RTL_GIGA_MAC_VER_42:
4976 case RTL_GIGA_MAC_VER_43:
4977 case RTL_GIGA_MAC_VER_44:
4978 case RTL_GIGA_MAC_VER_45:
4979 case RTL_GIGA_MAC_VER_46:
4980 case RTL_GIGA_MAC_VER_47:
4981 case RTL_GIGA_MAC_VER_48:
4982 case RTL_GIGA_MAC_VER_49:
4983 case RTL_GIGA_MAC_VER_50:
4984 case RTL_GIGA_MAC_VER_51:
4985 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4986 break;
4987 default:
4988 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
4989 break;
4990 }
4991}
4992
4993static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4994{
4995 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4996}
4997
4998static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4999{
5000 void __iomem *ioaddr = tp->mmio_addr;
5001
5002 RTL_W8(Cfg9346, Cfg9346_Unlock);
5003 rtl_generic_op(tp, tp->jumbo_ops.enable);
5004 RTL_W8(Cfg9346, Cfg9346_Lock);
5005}
5006
5007static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
5008{
5009 void __iomem *ioaddr = tp->mmio_addr;
5010
5011 RTL_W8(Cfg9346, Cfg9346_Unlock);
5012 rtl_generic_op(tp, tp->jumbo_ops.disable);
5013 RTL_W8(Cfg9346, Cfg9346_Lock);
5014}
5015
5016static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
5017{
5018 void __iomem *ioaddr = tp->mmio_addr;
5019
5020 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
5021 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
5022 rtl_tx_performance_tweak(tp->pci_dev, PCI_EXP_DEVCTL_READRQ_512B);
5023}
5024
5025static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
5026{
5027 void __iomem *ioaddr = tp->mmio_addr;
5028
5029 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
5030 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
5031 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5032}
5033
5034static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
5035{
5036 void __iomem *ioaddr = tp->mmio_addr;
5037
5038 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
5039}
5040
5041static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
5042{
5043 void __iomem *ioaddr = tp->mmio_addr;
5044
5045 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
5046}
5047
5048static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
5049{
5050 void __iomem *ioaddr = tp->mmio_addr;
5051
5052 RTL_W8(MaxTxPacketSize, 0x3f);
5053 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
5054 RTL_W8(Config4, RTL_R8(Config4) | 0x01);
5055 rtl_tx_performance_tweak(tp->pci_dev, PCI_EXP_DEVCTL_READRQ_512B);
5056}
5057
5058static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
5059{
5060 void __iomem *ioaddr = tp->mmio_addr;
5061
5062 RTL_W8(MaxTxPacketSize, 0x0c);
5063 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
5064 RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
5065 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5066}
5067
5068static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
5069{
5070 rtl_tx_performance_tweak(tp->pci_dev,
5071 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
5072}
5073
5074static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
5075{
5076 rtl_tx_performance_tweak(tp->pci_dev,
5077 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
5078}
5079
5080static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
5081{
5082 void __iomem *ioaddr = tp->mmio_addr;
5083
5084 r8168b_0_hw_jumbo_enable(tp);
5085
5086 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
5087}
5088
5089static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
5090{
5091 void __iomem *ioaddr = tp->mmio_addr;
5092
5093 r8168b_0_hw_jumbo_disable(tp);
5094
5095 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
5096}
5097
5098static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
5099{
5100 struct jumbo_ops *ops = &tp->jumbo_ops;
5101
5102 switch (tp->mac_version) {
5103 case RTL_GIGA_MAC_VER_11:
5104 ops->disable = r8168b_0_hw_jumbo_disable;
5105 ops->enable = r8168b_0_hw_jumbo_enable;
5106 break;
5107 case RTL_GIGA_MAC_VER_12:
5108 case RTL_GIGA_MAC_VER_17:
5109 ops->disable = r8168b_1_hw_jumbo_disable;
5110 ops->enable = r8168b_1_hw_jumbo_enable;
5111 break;
5112 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
5113 case RTL_GIGA_MAC_VER_19:
5114 case RTL_GIGA_MAC_VER_20:
5115 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
5116 case RTL_GIGA_MAC_VER_22:
5117 case RTL_GIGA_MAC_VER_23:
5118 case RTL_GIGA_MAC_VER_24:
5119 case RTL_GIGA_MAC_VER_25:
5120 case RTL_GIGA_MAC_VER_26:
5121 ops->disable = r8168c_hw_jumbo_disable;
5122 ops->enable = r8168c_hw_jumbo_enable;
5123 break;
5124 case RTL_GIGA_MAC_VER_27:
5125 case RTL_GIGA_MAC_VER_28:
5126 ops->disable = r8168dp_hw_jumbo_disable;
5127 ops->enable = r8168dp_hw_jumbo_enable;
5128 break;
5129 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
5130 case RTL_GIGA_MAC_VER_32:
5131 case RTL_GIGA_MAC_VER_33:
5132 case RTL_GIGA_MAC_VER_34:
5133 ops->disable = r8168e_hw_jumbo_disable;
5134 ops->enable = r8168e_hw_jumbo_enable;
5135 break;
5136
5137 /*
5138 * No action needed for jumbo frames with 8169.
5139 * No jumbo for 810x at all.
5140 */
5141 case RTL_GIGA_MAC_VER_40:
5142 case RTL_GIGA_MAC_VER_41:
5143 case RTL_GIGA_MAC_VER_42:
5144 case RTL_GIGA_MAC_VER_43:
5145 case RTL_GIGA_MAC_VER_44:
5146 case RTL_GIGA_MAC_VER_45:
5147 case RTL_GIGA_MAC_VER_46:
5148 case RTL_GIGA_MAC_VER_47:
5149 case RTL_GIGA_MAC_VER_48:
5150 case RTL_GIGA_MAC_VER_49:
5151 case RTL_GIGA_MAC_VER_50:
5152 case RTL_GIGA_MAC_VER_51:
5153 default:
5154 ops->disable = NULL;
5155 ops->enable = NULL;
5156 break;
5157 }
5158}
5159
5160DECLARE_RTL_COND(rtl_chipcmd_cond)
5161{
5162 void __iomem *ioaddr = tp->mmio_addr;
5163
5164 return RTL_R8(ChipCmd) & CmdReset;
5165}
5166
5167static void rtl_hw_reset(struct rtl8169_private *tp)
5168{
5169 void __iomem *ioaddr = tp->mmio_addr;
5170
5171 RTL_W8(ChipCmd, CmdReset);
5172
5173 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
5174}
5175
5176static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
5177{
5178 struct rtl_fw *rtl_fw;
5179 const char *name;
5180 int rc = -ENOMEM;
5181
5182 name = rtl_lookup_firmware_name(tp);
5183 if (!name)
5184 goto out_no_firmware;
5185
5186 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
5187 if (!rtl_fw)
5188 goto err_warn;
5189
5190 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
5191 if (rc < 0)
5192 goto err_free;
5193
5194 rc = rtl_check_firmware(tp, rtl_fw);
5195 if (rc < 0)
5196 goto err_release_firmware;
5197
5198 tp->rtl_fw = rtl_fw;
5199out:
5200 return;
5201
5202err_release_firmware:
5203 release_firmware(rtl_fw->fw);
5204err_free:
5205 kfree(rtl_fw);
5206err_warn:
5207 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
5208 name, rc);
5209out_no_firmware:
5210 tp->rtl_fw = NULL;
5211 goto out;
5212}
5213
5214static void rtl_request_firmware(struct rtl8169_private *tp)
5215{
5216 if (IS_ERR(tp->rtl_fw))
5217 rtl_request_uncached_firmware(tp);
5218}
5219
5220static void rtl_rx_close(struct rtl8169_private *tp)
5221{
5222 void __iomem *ioaddr = tp->mmio_addr;
5223
5224 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
5225}
5226
5227DECLARE_RTL_COND(rtl_npq_cond)
5228{
5229 void __iomem *ioaddr = tp->mmio_addr;
5230
5231 return RTL_R8(TxPoll) & NPQ;
5232}
5233
5234DECLARE_RTL_COND(rtl_txcfg_empty_cond)
5235{
5236 void __iomem *ioaddr = tp->mmio_addr;
5237
5238 return RTL_R32(TxConfig) & TXCFG_EMPTY;
5239}
5240
5241static void rtl8169_hw_reset(struct rtl8169_private *tp)
5242{
5243 void __iomem *ioaddr = tp->mmio_addr;
5244
5245 /* Disable interrupts */
5246 rtl8169_irq_mask_and_ack(tp);
5247
5248 rtl_rx_close(tp);
5249
5250 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
5251 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
5252 tp->mac_version == RTL_GIGA_MAC_VER_31) {
5253 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
5254 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
5255 tp->mac_version == RTL_GIGA_MAC_VER_35 ||
5256 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
5257 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
5258 tp->mac_version == RTL_GIGA_MAC_VER_38 ||
5259 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
5260 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
5261 tp->mac_version == RTL_GIGA_MAC_VER_42 ||
5262 tp->mac_version == RTL_GIGA_MAC_VER_43 ||
5263 tp->mac_version == RTL_GIGA_MAC_VER_44 ||
5264 tp->mac_version == RTL_GIGA_MAC_VER_45 ||
5265 tp->mac_version == RTL_GIGA_MAC_VER_46 ||
5266 tp->mac_version == RTL_GIGA_MAC_VER_47 ||
5267 tp->mac_version == RTL_GIGA_MAC_VER_48 ||
5268 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
5269 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
5270 tp->mac_version == RTL_GIGA_MAC_VER_51) {
5271 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
5272 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
5273 } else {
5274 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
5275 udelay(100);
5276 }
5277
5278 rtl_hw_reset(tp);
5279}
5280
5281static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
5282{
5283 void __iomem *ioaddr = tp->mmio_addr;
5284
5285 /* Set DMA burst size and Interframe Gap Time */
5286 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
5287 (InterFrameGap << TxInterFrameGapShift));
5288}
5289
5290static void rtl_hw_start(struct net_device *dev)
5291{
5292 struct rtl8169_private *tp = netdev_priv(dev);
5293
5294 tp->hw_start(dev);
5295
5296 rtl_irq_enable_all(tp);
5297}
5298
5299static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
5300 void __iomem *ioaddr)
5301{
5302 /*
5303 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
5304 * register to be written before TxDescAddrLow to work.
5305 * Switching from MMIO to I/O access fixes the issue as well.
5306 */
5307 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
5308 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
5309 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
5310 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
5311}
5312
5313static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
5314{
5315 u16 cmd;
5316
5317 cmd = RTL_R16(CPlusCmd);
5318 RTL_W16(CPlusCmd, cmd);
5319 return cmd;
5320}
5321
5322static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
5323{
5324 /* Low hurts. Let's disable the filtering. */
5325 RTL_W16(RxMaxSize, rx_buf_sz + 1);
5326}
5327
5328static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
5329{
5330 static const struct rtl_cfg2_info {
5331 u32 mac_version;
5332 u32 clk;
5333 u32 val;
5334 } cfg2_info [] = {
5335 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
5336 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
5337 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
5338 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
5339 };
5340 const struct rtl_cfg2_info *p = cfg2_info;
5341 unsigned int i;
5342 u32 clk;
5343
5344 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
5345 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
5346 if ((p->mac_version == mac_version) && (p->clk == clk)) {
5347 RTL_W32(0x7c, p->val);
5348 break;
5349 }
5350 }
5351}
5352
5353static void rtl_set_rx_mode(struct net_device *dev)
5354{
5355 struct rtl8169_private *tp = netdev_priv(dev);
5356 void __iomem *ioaddr = tp->mmio_addr;
5357 u32 mc_filter[2]; /* Multicast hash filter */
5358 int rx_mode;
5359 u32 tmp = 0;
5360
5361 if (dev->flags & IFF_PROMISC) {
5362 /* Unconditionally log net taps. */
5363 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5364 rx_mode =
5365 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5366 AcceptAllPhys;
5367 mc_filter[1] = mc_filter[0] = 0xffffffff;
5368 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5369 (dev->flags & IFF_ALLMULTI)) {
5370 /* Too many to filter perfectly -- accept all multicasts. */
5371 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5372 mc_filter[1] = mc_filter[0] = 0xffffffff;
5373 } else {
5374 struct netdev_hw_addr *ha;
5375
5376 rx_mode = AcceptBroadcast | AcceptMyPhys;
5377 mc_filter[1] = mc_filter[0] = 0;
5378 netdev_for_each_mc_addr(ha, dev) {
5379 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
5380 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5381 rx_mode |= AcceptMulticast;
5382 }
5383 }
5384
5385 if (dev->features & NETIF_F_RXALL)
5386 rx_mode |= (AcceptErr | AcceptRunt);
5387
5388 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
5389
5390 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5391 u32 data = mc_filter[0];
5392
5393 mc_filter[0] = swab32(mc_filter[1]);
5394 mc_filter[1] = swab32(data);
5395 }
5396
5397 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
5398 mc_filter[1] = mc_filter[0] = 0xffffffff;
5399
5400 RTL_W32(MAR0 + 4, mc_filter[1]);
5401 RTL_W32(MAR0 + 0, mc_filter[0]);
5402
5403 RTL_W32(RxConfig, tmp);
5404}
5405
5406static void rtl_hw_start_8169(struct net_device *dev)
5407{
5408 struct rtl8169_private *tp = netdev_priv(dev);
5409 void __iomem *ioaddr = tp->mmio_addr;
5410 struct pci_dev *pdev = tp->pci_dev;
5411
5412 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
5413 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
5414 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
5415 }
5416
5417 RTL_W8(Cfg9346, Cfg9346_Unlock);
5418 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
5419 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5420 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
5421 tp->mac_version == RTL_GIGA_MAC_VER_04)
5422 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5423
5424 rtl_init_rxcfg(tp);
5425
5426 RTL_W8(EarlyTxThres, NoEarlyTx);
5427
5428 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5429
5430 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
5431 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5432 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
5433 tp->mac_version == RTL_GIGA_MAC_VER_04)
5434 rtl_set_rx_tx_config_registers(tp);
5435
5436 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
5437
5438 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5439 tp->mac_version == RTL_GIGA_MAC_VER_03) {
5440 dprintk("Set MAC Reg C+CR Offset 0xe0. "
5441 "Bit-3 and bit-14 MUST be 1\n");
5442 tp->cp_cmd |= (1 << 14);
5443 }
5444
5445 RTL_W16(CPlusCmd, tp->cp_cmd);
5446
5447 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
5448
5449 /*
5450 * Undocumented corner. Supposedly:
5451 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
5452 */
5453 RTL_W16(IntrMitigate, 0x0000);
5454
5455 rtl_set_rx_tx_desc_registers(tp, ioaddr);
5456
5457 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
5458 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
5459 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
5460 tp->mac_version != RTL_GIGA_MAC_VER_04) {
5461 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5462 rtl_set_rx_tx_config_registers(tp);
5463 }
5464
5465 RTL_W8(Cfg9346, Cfg9346_Lock);
5466
5467 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
5468 RTL_R8(IntrMask);
5469
5470 RTL_W32(RxMissed, 0);
5471
5472 rtl_set_rx_mode(dev);
5473
5474 /* no early-rx interrupts */
5475 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
5476}
5477
5478static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
5479{
5480 if (tp->csi_ops.write)
5481 tp->csi_ops.write(tp, addr, value);
5482}
5483
5484static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
5485{
5486 return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
5487}
5488
5489static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
5490{
5491 u32 csi;
5492
5493 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
5494 rtl_csi_write(tp, 0x070c, csi | bits);
5495}
5496
5497static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
5498{
5499 rtl_csi_access_enable(tp, 0x17000000);
5500}
5501
5502static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
5503{
5504 rtl_csi_access_enable(tp, 0x27000000);
5505}
5506
5507DECLARE_RTL_COND(rtl_csiar_cond)
5508{
5509 void __iomem *ioaddr = tp->mmio_addr;
5510
5511 return RTL_R32(CSIAR) & CSIAR_FLAG;
5512}
5513
5514static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
5515{
5516 void __iomem *ioaddr = tp->mmio_addr;
5517
5518 RTL_W32(CSIDR, value);
5519 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5520 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5521
5522 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5523}
5524
5525static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
5526{
5527 void __iomem *ioaddr = tp->mmio_addr;
5528
5529 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
5530 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5531
5532 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5533 RTL_R32(CSIDR) : ~0;
5534}
5535
5536static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
5537{
5538 void __iomem *ioaddr = tp->mmio_addr;
5539
5540 RTL_W32(CSIDR, value);
5541 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5542 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5543 CSIAR_FUNC_NIC);
5544
5545 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5546}
5547
5548static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
5549{
5550 void __iomem *ioaddr = tp->mmio_addr;
5551
5552 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
5553 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5554
5555 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5556 RTL_R32(CSIDR) : ~0;
5557}
5558
5559static void r8411_csi_write(struct rtl8169_private *tp, int addr, int value)
5560{
5561 void __iomem *ioaddr = tp->mmio_addr;
5562
5563 RTL_W32(CSIDR, value);
5564 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5565 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5566 CSIAR_FUNC_NIC2);
5567
5568 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5569}
5570
5571static u32 r8411_csi_read(struct rtl8169_private *tp, int addr)
5572{
5573 void __iomem *ioaddr = tp->mmio_addr;
5574
5575 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC2 |
5576 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5577
5578 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5579 RTL_R32(CSIDR) : ~0;
5580}
5581
5582static void rtl_init_csi_ops(struct rtl8169_private *tp)
5583{
5584 struct csi_ops *ops = &tp->csi_ops;
5585
5586 switch (tp->mac_version) {
5587 case RTL_GIGA_MAC_VER_01:
5588 case RTL_GIGA_MAC_VER_02:
5589 case RTL_GIGA_MAC_VER_03:
5590 case RTL_GIGA_MAC_VER_04:
5591 case RTL_GIGA_MAC_VER_05:
5592 case RTL_GIGA_MAC_VER_06:
5593 case RTL_GIGA_MAC_VER_10:
5594 case RTL_GIGA_MAC_VER_11:
5595 case RTL_GIGA_MAC_VER_12:
5596 case RTL_GIGA_MAC_VER_13:
5597 case RTL_GIGA_MAC_VER_14:
5598 case RTL_GIGA_MAC_VER_15:
5599 case RTL_GIGA_MAC_VER_16:
5600 case RTL_GIGA_MAC_VER_17:
5601 ops->write = NULL;
5602 ops->read = NULL;
5603 break;
5604
5605 case RTL_GIGA_MAC_VER_37:
5606 case RTL_GIGA_MAC_VER_38:
5607 ops->write = r8402_csi_write;
5608 ops->read = r8402_csi_read;
5609 break;
5610
5611 case RTL_GIGA_MAC_VER_44:
5612 ops->write = r8411_csi_write;
5613 ops->read = r8411_csi_read;
5614 break;
5615
5616 default:
5617 ops->write = r8169_csi_write;
5618 ops->read = r8169_csi_read;
5619 break;
5620 }
5621}
5622
5623struct ephy_info {
5624 unsigned int offset;
5625 u16 mask;
5626 u16 bits;
5627};
5628
5629static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
5630 int len)
5631{
5632 u16 w;
5633
5634 while (len-- > 0) {
5635 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
5636 rtl_ephy_write(tp, e->offset, w);
5637 e++;
5638 }
5639}
5640
5641static void rtl_disable_clock_request(struct pci_dev *pdev)
5642{
5643 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
5644 PCI_EXP_LNKCTL_CLKREQ_EN);
5645}
5646
5647static void rtl_enable_clock_request(struct pci_dev *pdev)
5648{
5649 pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
5650 PCI_EXP_LNKCTL_CLKREQ_EN);
5651}
5652
5653static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
5654{
5655 void __iomem *ioaddr = tp->mmio_addr;
5656 u8 data;
5657
5658 data = RTL_R8(Config3);
5659
5660 if (enable)
5661 data |= Rdy_to_L23;
5662 else
5663 data &= ~Rdy_to_L23;
5664
5665 RTL_W8(Config3, data);
5666}
5667
5668#define R8168_CPCMD_QUIRK_MASK (\
5669 EnableBist | \
5670 Mac_dbgo_oe | \
5671 Force_half_dup | \
5672 Force_rxflow_en | \
5673 Force_txflow_en | \
5674 Cxpl_dbg_sel | \
5675 ASF | \
5676 PktCntrDisable | \
5677 Mac_dbgo_sel)
5678
5679static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
5680{
5681 void __iomem *ioaddr = tp->mmio_addr;
5682 struct pci_dev *pdev = tp->pci_dev;
5683
5684 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5685
5686 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5687
5688 if (tp->dev->mtu <= ETH_DATA_LEN) {
5689 rtl_tx_performance_tweak(pdev, (0x5 << MAX_READ_REQUEST_SHIFT) |
5690 PCI_EXP_DEVCTL_NOSNOOP_EN);
5691 }
5692}
5693
5694static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
5695{
5696 void __iomem *ioaddr = tp->mmio_addr;
5697
5698 rtl_hw_start_8168bb(tp);
5699
5700 RTL_W8(MaxTxPacketSize, TxPacketMax);
5701
5702 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
5703}
5704
5705static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
5706{
5707 void __iomem *ioaddr = tp->mmio_addr;
5708 struct pci_dev *pdev = tp->pci_dev;
5709
5710 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
5711
5712 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5713
5714 if (tp->dev->mtu <= ETH_DATA_LEN)
5715 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5716
5717 rtl_disable_clock_request(pdev);
5718
5719 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5720}
5721
5722static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
5723{
5724 static const struct ephy_info e_info_8168cp[] = {
5725 { 0x01, 0, 0x0001 },
5726 { 0x02, 0x0800, 0x1000 },
5727 { 0x03, 0, 0x0042 },
5728 { 0x06, 0x0080, 0x0000 },
5729 { 0x07, 0, 0x2000 }
5730 };
5731
5732 rtl_csi_access_enable_2(tp);
5733
5734 rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
5735
5736 __rtl_hw_start_8168cp(tp);
5737}
5738
5739static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
5740{
5741 void __iomem *ioaddr = tp->mmio_addr;
5742 struct pci_dev *pdev = tp->pci_dev;
5743
5744 rtl_csi_access_enable_2(tp);
5745
5746 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5747
5748 if (tp->dev->mtu <= ETH_DATA_LEN)
5749 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5750
5751 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5752}
5753
5754static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
5755{
5756 void __iomem *ioaddr = tp->mmio_addr;
5757 struct pci_dev *pdev = tp->pci_dev;
5758
5759 rtl_csi_access_enable_2(tp);
5760
5761 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5762
5763 /* Magic. */
5764 RTL_W8(DBG_REG, 0x20);
5765
5766 RTL_W8(MaxTxPacketSize, TxPacketMax);
5767
5768 if (tp->dev->mtu <= ETH_DATA_LEN)
5769 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5770
5771 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5772}
5773
5774static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
5775{
5776 void __iomem *ioaddr = tp->mmio_addr;
5777 static const struct ephy_info e_info_8168c_1[] = {
5778 { 0x02, 0x0800, 0x1000 },
5779 { 0x03, 0, 0x0002 },
5780 { 0x06, 0x0080, 0x0000 }
5781 };
5782
5783 rtl_csi_access_enable_2(tp);
5784
5785 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
5786
5787 rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
5788
5789 __rtl_hw_start_8168cp(tp);
5790}
5791
5792static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
5793{
5794 static const struct ephy_info e_info_8168c_2[] = {
5795 { 0x01, 0, 0x0001 },
5796 { 0x03, 0x0400, 0x0220 }
5797 };
5798
5799 rtl_csi_access_enable_2(tp);
5800
5801 rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
5802
5803 __rtl_hw_start_8168cp(tp);
5804}
5805
5806static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
5807{
5808 rtl_hw_start_8168c_2(tp);
5809}
5810
5811static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
5812{
5813 rtl_csi_access_enable_2(tp);
5814
5815 __rtl_hw_start_8168cp(tp);
5816}
5817
5818static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5819{
5820 void __iomem *ioaddr = tp->mmio_addr;
5821 struct pci_dev *pdev = tp->pci_dev;
5822
5823 rtl_csi_access_enable_2(tp);
5824
5825 rtl_disable_clock_request(pdev);
5826
5827 RTL_W8(MaxTxPacketSize, TxPacketMax);
5828
5829 if (tp->dev->mtu <= ETH_DATA_LEN)
5830 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5831
5832 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5833}
5834
5835static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
5836{
5837 void __iomem *ioaddr = tp->mmio_addr;
5838 struct pci_dev *pdev = tp->pci_dev;
5839
5840 rtl_csi_access_enable_1(tp);
5841
5842 if (tp->dev->mtu <= ETH_DATA_LEN)
5843 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5844
5845 RTL_W8(MaxTxPacketSize, TxPacketMax);
5846
5847 rtl_disable_clock_request(pdev);
5848}
5849
5850static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
5851{
5852 void __iomem *ioaddr = tp->mmio_addr;
5853 struct pci_dev *pdev = tp->pci_dev;
5854 static const struct ephy_info e_info_8168d_4[] = {
5855 { 0x0b, 0x0000, 0x0048 },
5856 { 0x19, 0x0020, 0x0050 },
5857 { 0x0c, 0x0100, 0x0020 }
5858 };
5859
5860 rtl_csi_access_enable_1(tp);
5861
5862 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5863
5864 RTL_W8(MaxTxPacketSize, TxPacketMax);
5865
5866 rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4));
5867
5868 rtl_enable_clock_request(pdev);
5869}
5870
5871static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
5872{
5873 void __iomem *ioaddr = tp->mmio_addr;
5874 struct pci_dev *pdev = tp->pci_dev;
5875 static const struct ephy_info e_info_8168e_1[] = {
5876 { 0x00, 0x0200, 0x0100 },
5877 { 0x00, 0x0000, 0x0004 },
5878 { 0x06, 0x0002, 0x0001 },
5879 { 0x06, 0x0000, 0x0030 },
5880 { 0x07, 0x0000, 0x2000 },
5881 { 0x00, 0x0000, 0x0020 },
5882 { 0x03, 0x5800, 0x2000 },
5883 { 0x03, 0x0000, 0x0001 },
5884 { 0x01, 0x0800, 0x1000 },
5885 { 0x07, 0x0000, 0x4000 },
5886 { 0x1e, 0x0000, 0x2000 },
5887 { 0x19, 0xffff, 0xfe6c },
5888 { 0x0a, 0x0000, 0x0040 }
5889 };
5890
5891 rtl_csi_access_enable_2(tp);
5892
5893 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
5894
5895 if (tp->dev->mtu <= ETH_DATA_LEN)
5896 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5897
5898 RTL_W8(MaxTxPacketSize, TxPacketMax);
5899
5900 rtl_disable_clock_request(pdev);
5901
5902 /* Reset tx FIFO pointer */
5903 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
5904 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
5905
5906 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5907}
5908
5909static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
5910{
5911 void __iomem *ioaddr = tp->mmio_addr;
5912 struct pci_dev *pdev = tp->pci_dev;
5913 static const struct ephy_info e_info_8168e_2[] = {
5914 { 0x09, 0x0000, 0x0080 },
5915 { 0x19, 0x0000, 0x0224 }
5916 };
5917
5918 rtl_csi_access_enable_1(tp);
5919
5920 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
5921
5922 if (tp->dev->mtu <= ETH_DATA_LEN)
5923 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5924
5925 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5926 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5927 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5928 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5929 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5930 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5931 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5932 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5933
5934 RTL_W8(MaxTxPacketSize, EarlySize);
5935
5936 rtl_disable_clock_request(pdev);
5937
5938 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5939 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5940
5941 /* Adjust EEE LED frequency */
5942 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5943
5944 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5945 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5946 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5947}
5948
5949static void rtl_hw_start_8168f(struct rtl8169_private *tp)
5950{
5951 void __iomem *ioaddr = tp->mmio_addr;
5952 struct pci_dev *pdev = tp->pci_dev;
5953
5954 rtl_csi_access_enable_2(tp);
5955
5956 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5957
5958 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5959 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5960 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5961 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5962 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5963 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5964 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5965 rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5966 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5967 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
5968
5969 RTL_W8(MaxTxPacketSize, EarlySize);
5970
5971 rtl_disable_clock_request(pdev);
5972
5973 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5974 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5975 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5976 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5977 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5978}
5979
5980static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5981{
5982 void __iomem *ioaddr = tp->mmio_addr;
5983 static const struct ephy_info e_info_8168f_1[] = {
5984 { 0x06, 0x00c0, 0x0020 },
5985 { 0x08, 0x0001, 0x0002 },
5986 { 0x09, 0x0000, 0x0080 },
5987 { 0x19, 0x0000, 0x0224 }
5988 };
5989
5990 rtl_hw_start_8168f(tp);
5991
5992 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5993
5994 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5995
5996 /* Adjust EEE LED frequency */
5997 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5998}
5999
6000static void rtl_hw_start_8411(struct rtl8169_private *tp)
6001{
6002 static const struct ephy_info e_info_8168f_1[] = {
6003 { 0x06, 0x00c0, 0x0020 },
6004 { 0x0f, 0xffff, 0x5200 },
6005 { 0x1e, 0x0000, 0x4000 },
6006 { 0x19, 0x0000, 0x0224 }
6007 };
6008
6009 rtl_hw_start_8168f(tp);
6010 rtl_pcie_state_l2l3_enable(tp, false);
6011
6012 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
6013
6014 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
6015}
6016
6017static void rtl_hw_start_8168g(struct rtl8169_private *tp)
6018{
6019 void __iomem *ioaddr = tp->mmio_addr;
6020 struct pci_dev *pdev = tp->pci_dev;
6021
6022 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6023
6024 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
6025 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
6026 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
6027 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6028
6029 rtl_csi_access_enable_1(tp);
6030
6031 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6032
6033 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6034 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6035 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
6036
6037 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6038 RTL_W8(MaxTxPacketSize, EarlySize);
6039
6040 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6041 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6042
6043 /* Adjust EEE LED frequency */
6044 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6045
6046 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
6047 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
6048
6049 rtl_pcie_state_l2l3_enable(tp, false);
6050}
6051
6052static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
6053{
6054 void __iomem *ioaddr = tp->mmio_addr;
6055 static const struct ephy_info e_info_8168g_1[] = {
6056 { 0x00, 0x0000, 0x0008 },
6057 { 0x0c, 0x37d0, 0x0820 },
6058 { 0x1e, 0x0000, 0x0001 },
6059 { 0x19, 0x8000, 0x0000 }
6060 };
6061
6062 rtl_hw_start_8168g(tp);
6063
6064 /* disable aspm and clock request before access ephy */
6065 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6066 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6067 rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
6068}
6069
6070static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
6071{
6072 void __iomem *ioaddr = tp->mmio_addr;
6073 static const struct ephy_info e_info_8168g_2[] = {
6074 { 0x00, 0x0000, 0x0008 },
6075 { 0x0c, 0x3df0, 0x0200 },
6076 { 0x19, 0xffff, 0xfc00 },
6077 { 0x1e, 0xffff, 0x20eb }
6078 };
6079
6080 rtl_hw_start_8168g(tp);
6081
6082 /* disable aspm and clock request before access ephy */
6083 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6084 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6085 rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
6086}
6087
6088static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
6089{
6090 void __iomem *ioaddr = tp->mmio_addr;
6091 static const struct ephy_info e_info_8411_2[] = {
6092 { 0x00, 0x0000, 0x0008 },
6093 { 0x0c, 0x3df0, 0x0200 },
6094 { 0x0f, 0xffff, 0x5200 },
6095 { 0x19, 0x0020, 0x0000 },
6096 { 0x1e, 0x0000, 0x2000 }
6097 };
6098
6099 rtl_hw_start_8168g(tp);
6100
6101 /* disable aspm and clock request before access ephy */
6102 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6103 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6104 rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
6105}
6106
6107static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
6108{
6109 void __iomem *ioaddr = tp->mmio_addr;
6110 struct pci_dev *pdev = tp->pci_dev;
6111 int rg_saw_cnt;
6112 u32 data;
6113 static const struct ephy_info e_info_8168h_1[] = {
6114 { 0x1e, 0x0800, 0x0001 },
6115 { 0x1d, 0x0000, 0x0800 },
6116 { 0x05, 0xffff, 0x2089 },
6117 { 0x06, 0xffff, 0x5881 },
6118 { 0x04, 0xffff, 0x154a },
6119 { 0x01, 0xffff, 0x068b }
6120 };
6121
6122 /* disable aspm and clock request before access ephy */
6123 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6124 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6125 rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
6126
6127 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6128
6129 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6130 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
6131 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
6132 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6133
6134 rtl_csi_access_enable_1(tp);
6135
6136 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6137
6138 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6139 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6140
6141 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
6142
6143 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
6144
6145 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6146
6147 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6148 RTL_W8(MaxTxPacketSize, EarlySize);
6149
6150 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6151 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6152
6153 /* Adjust EEE LED frequency */
6154 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6155
6156 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6157 RTL_W8(MISC_1, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6158
6159 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
6160
6161 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
6162
6163 rtl_pcie_state_l2l3_enable(tp, false);
6164
6165 rtl_writephy(tp, 0x1f, 0x0c42);
6166 rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
6167 rtl_writephy(tp, 0x1f, 0x0000);
6168 if (rg_saw_cnt > 0) {
6169 u16 sw_cnt_1ms_ini;
6170
6171 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
6172 sw_cnt_1ms_ini &= 0x0fff;
6173 data = r8168_mac_ocp_read(tp, 0xd412);
6174 data &= ~0x0fff;
6175 data |= sw_cnt_1ms_ini;
6176 r8168_mac_ocp_write(tp, 0xd412, data);
6177 }
6178
6179 data = r8168_mac_ocp_read(tp, 0xe056);
6180 data &= ~0xf0;
6181 data |= 0x70;
6182 r8168_mac_ocp_write(tp, 0xe056, data);
6183
6184 data = r8168_mac_ocp_read(tp, 0xe052);
6185 data &= ~0x6000;
6186 data |= 0x8008;
6187 r8168_mac_ocp_write(tp, 0xe052, data);
6188
6189 data = r8168_mac_ocp_read(tp, 0xe0d6);
6190 data &= ~0x01ff;
6191 data |= 0x017f;
6192 r8168_mac_ocp_write(tp, 0xe0d6, data);
6193
6194 data = r8168_mac_ocp_read(tp, 0xd420);
6195 data &= ~0x0fff;
6196 data |= 0x047f;
6197 r8168_mac_ocp_write(tp, 0xd420, data);
6198
6199 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
6200 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
6201 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
6202 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
6203}
6204
6205static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
6206{
6207 void __iomem *ioaddr = tp->mmio_addr;
6208 struct pci_dev *pdev = tp->pci_dev;
6209
6210 rtl8168ep_stop_cmac(tp);
6211
6212 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6213
6214 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6215 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
6216 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
6217 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6218
6219 rtl_csi_access_enable_1(tp);
6220
6221 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6222
6223 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6224 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6225
6226 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
6227
6228 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6229
6230 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6231 RTL_W8(MaxTxPacketSize, EarlySize);
6232
6233 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6234 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6235
6236 /* Adjust EEE LED frequency */
6237 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6238
6239 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
6240
6241 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
6242
6243 rtl_pcie_state_l2l3_enable(tp, false);
6244}
6245
6246static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
6247{
6248 void __iomem *ioaddr = tp->mmio_addr;
6249 static const struct ephy_info e_info_8168ep_1[] = {
6250 { 0x00, 0xffff, 0x10ab },
6251 { 0x06, 0xffff, 0xf030 },
6252 { 0x08, 0xffff, 0x2006 },
6253 { 0x0d, 0xffff, 0x1666 },
6254 { 0x0c, 0x3ff0, 0x0000 }
6255 };
6256
6257 /* disable aspm and clock request before access ephy */
6258 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6259 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6260 rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
6261
6262 rtl_hw_start_8168ep(tp);
6263}
6264
6265static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
6266{
6267 void __iomem *ioaddr = tp->mmio_addr;
6268 static const struct ephy_info e_info_8168ep_2[] = {
6269 { 0x00, 0xffff, 0x10a3 },
6270 { 0x19, 0xffff, 0xfc00 },
6271 { 0x1e, 0xffff, 0x20ea }
6272 };
6273
6274 /* disable aspm and clock request before access ephy */
6275 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6276 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6277 rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
6278
6279 rtl_hw_start_8168ep(tp);
6280
6281 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6282 RTL_W8(MISC_1, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6283}
6284
6285static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
6286{
6287 void __iomem *ioaddr = tp->mmio_addr;
6288 u32 data;
6289 static const struct ephy_info e_info_8168ep_3[] = {
6290 { 0x00, 0xffff, 0x10a3 },
6291 { 0x19, 0xffff, 0x7c00 },
6292 { 0x1e, 0xffff, 0x20eb },
6293 { 0x0d, 0xffff, 0x1666 }
6294 };
6295
6296 /* disable aspm and clock request before access ephy */
6297 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6298 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6299 rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
6300
6301 rtl_hw_start_8168ep(tp);
6302
6303 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6304 RTL_W8(MISC_1, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6305
6306 data = r8168_mac_ocp_read(tp, 0xd3e2);
6307 data &= 0xf000;
6308 data |= 0x0271;
6309 r8168_mac_ocp_write(tp, 0xd3e2, data);
6310
6311 data = r8168_mac_ocp_read(tp, 0xd3e4);
6312 data &= 0xff00;
6313 r8168_mac_ocp_write(tp, 0xd3e4, data);
6314
6315 data = r8168_mac_ocp_read(tp, 0xe860);
6316 data |= 0x0080;
6317 r8168_mac_ocp_write(tp, 0xe860, data);
6318}
6319
6320static void rtl_hw_start_8168(struct net_device *dev)
6321{
6322 struct rtl8169_private *tp = netdev_priv(dev);
6323 void __iomem *ioaddr = tp->mmio_addr;
6324
6325 RTL_W8(Cfg9346, Cfg9346_Unlock);
6326
6327 RTL_W8(MaxTxPacketSize, TxPacketMax);
6328
6329 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
6330
6331 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
6332
6333 RTL_W16(CPlusCmd, tp->cp_cmd);
6334
6335 RTL_W16(IntrMitigate, 0x5151);
6336
6337 /* Work around for RxFIFO overflow. */
6338 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
6339 tp->event_slow |= RxFIFOOver | PCSTimeout;
6340 tp->event_slow &= ~RxOverflow;
6341 }
6342
6343 rtl_set_rx_tx_desc_registers(tp, ioaddr);
6344
6345 rtl_set_rx_tx_config_registers(tp);
6346
6347 RTL_R8(IntrMask);
6348
6349 switch (tp->mac_version) {
6350 case RTL_GIGA_MAC_VER_11:
6351 rtl_hw_start_8168bb(tp);
6352 break;
6353
6354 case RTL_GIGA_MAC_VER_12:
6355 case RTL_GIGA_MAC_VER_17:
6356 rtl_hw_start_8168bef(tp);
6357 break;
6358
6359 case RTL_GIGA_MAC_VER_18:
6360 rtl_hw_start_8168cp_1(tp);
6361 break;
6362
6363 case RTL_GIGA_MAC_VER_19:
6364 rtl_hw_start_8168c_1(tp);
6365 break;
6366
6367 case RTL_GIGA_MAC_VER_20:
6368 rtl_hw_start_8168c_2(tp);
6369 break;
6370
6371 case RTL_GIGA_MAC_VER_21:
6372 rtl_hw_start_8168c_3(tp);
6373 break;
6374
6375 case RTL_GIGA_MAC_VER_22:
6376 rtl_hw_start_8168c_4(tp);
6377 break;
6378
6379 case RTL_GIGA_MAC_VER_23:
6380 rtl_hw_start_8168cp_2(tp);
6381 break;
6382
6383 case RTL_GIGA_MAC_VER_24:
6384 rtl_hw_start_8168cp_3(tp);
6385 break;
6386
6387 case RTL_GIGA_MAC_VER_25:
6388 case RTL_GIGA_MAC_VER_26:
6389 case RTL_GIGA_MAC_VER_27:
6390 rtl_hw_start_8168d(tp);
6391 break;
6392
6393 case RTL_GIGA_MAC_VER_28:
6394 rtl_hw_start_8168d_4(tp);
6395 break;
6396
6397 case RTL_GIGA_MAC_VER_31:
6398 rtl_hw_start_8168dp(tp);
6399 break;
6400
6401 case RTL_GIGA_MAC_VER_32:
6402 case RTL_GIGA_MAC_VER_33:
6403 rtl_hw_start_8168e_1(tp);
6404 break;
6405 case RTL_GIGA_MAC_VER_34:
6406 rtl_hw_start_8168e_2(tp);
6407 break;
6408
6409 case RTL_GIGA_MAC_VER_35:
6410 case RTL_GIGA_MAC_VER_36:
6411 rtl_hw_start_8168f_1(tp);
6412 break;
6413
6414 case RTL_GIGA_MAC_VER_38:
6415 rtl_hw_start_8411(tp);
6416 break;
6417
6418 case RTL_GIGA_MAC_VER_40:
6419 case RTL_GIGA_MAC_VER_41:
6420 rtl_hw_start_8168g_1(tp);
6421 break;
6422 case RTL_GIGA_MAC_VER_42:
6423 rtl_hw_start_8168g_2(tp);
6424 break;
6425
6426 case RTL_GIGA_MAC_VER_44:
6427 rtl_hw_start_8411_2(tp);
6428 break;
6429
6430 case RTL_GIGA_MAC_VER_45:
6431 case RTL_GIGA_MAC_VER_46:
6432 rtl_hw_start_8168h_1(tp);
6433 break;
6434
6435 case RTL_GIGA_MAC_VER_49:
6436 rtl_hw_start_8168ep_1(tp);
6437 break;
6438
6439 case RTL_GIGA_MAC_VER_50:
6440 rtl_hw_start_8168ep_2(tp);
6441 break;
6442
6443 case RTL_GIGA_MAC_VER_51:
6444 rtl_hw_start_8168ep_3(tp);
6445 break;
6446
6447 default:
6448 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
6449 dev->name, tp->mac_version);
6450 break;
6451 }
6452
6453 RTL_W8(Cfg9346, Cfg9346_Lock);
6454
6455 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
6456
6457 rtl_set_rx_mode(dev);
6458
6459 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6460}
6461
6462#define R810X_CPCMD_QUIRK_MASK (\
6463 EnableBist | \
6464 Mac_dbgo_oe | \
6465 Force_half_dup | \
6466 Force_rxflow_en | \
6467 Force_txflow_en | \
6468 Cxpl_dbg_sel | \
6469 ASF | \
6470 PktCntrDisable | \
6471 Mac_dbgo_sel)
6472
6473static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
6474{
6475 void __iomem *ioaddr = tp->mmio_addr;
6476 struct pci_dev *pdev = tp->pci_dev;
6477 static const struct ephy_info e_info_8102e_1[] = {
6478 { 0x01, 0, 0x6e65 },
6479 { 0x02, 0, 0x091f },
6480 { 0x03, 0, 0xc2f9 },
6481 { 0x06, 0, 0xafb5 },
6482 { 0x07, 0, 0x0e00 },
6483 { 0x19, 0, 0xec80 },
6484 { 0x01, 0, 0x2e65 },
6485 { 0x01, 0, 0x6e65 }
6486 };
6487 u8 cfg1;
6488
6489 rtl_csi_access_enable_2(tp);
6490
6491 RTL_W8(DBG_REG, FIX_NAK_1);
6492
6493 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6494
6495 RTL_W8(Config1,
6496 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
6497 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
6498
6499 cfg1 = RTL_R8(Config1);
6500 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
6501 RTL_W8(Config1, cfg1 & ~LEDS0);
6502
6503 rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
6504}
6505
6506static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
6507{
6508 void __iomem *ioaddr = tp->mmio_addr;
6509 struct pci_dev *pdev = tp->pci_dev;
6510
6511 rtl_csi_access_enable_2(tp);
6512
6513 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6514
6515 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
6516 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
6517}
6518
6519static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
6520{
6521 rtl_hw_start_8102e_2(tp);
6522
6523 rtl_ephy_write(tp, 0x03, 0xc2f9);
6524}
6525
6526static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
6527{
6528 void __iomem *ioaddr = tp->mmio_addr;
6529 static const struct ephy_info e_info_8105e_1[] = {
6530 { 0x07, 0, 0x4000 },
6531 { 0x19, 0, 0x0200 },
6532 { 0x19, 0, 0x0020 },
6533 { 0x1e, 0, 0x2000 },
6534 { 0x03, 0, 0x0001 },
6535 { 0x19, 0, 0x0100 },
6536 { 0x19, 0, 0x0004 },
6537 { 0x0a, 0, 0x0020 }
6538 };
6539
6540 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6541 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6542
6543 /* Disable Early Tally Counter */
6544 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
6545
6546 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
6547 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
6548
6549 rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
6550
6551 rtl_pcie_state_l2l3_enable(tp, false);
6552}
6553
6554static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
6555{
6556 rtl_hw_start_8105e_1(tp);
6557 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
6558}
6559
6560static void rtl_hw_start_8402(struct rtl8169_private *tp)
6561{
6562 void __iomem *ioaddr = tp->mmio_addr;
6563 static const struct ephy_info e_info_8402[] = {
6564 { 0x19, 0xffff, 0xff64 },
6565 { 0x1e, 0, 0x4000 }
6566 };
6567
6568 rtl_csi_access_enable_2(tp);
6569
6570 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6571 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6572
6573 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6574 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
6575
6576 rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
6577
6578 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
6579
6580 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
6581 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
6582 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6583 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6584 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6585 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6586 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
6587
6588 rtl_pcie_state_l2l3_enable(tp, false);
6589}
6590
6591static void rtl_hw_start_8106(struct rtl8169_private *tp)
6592{
6593 void __iomem *ioaddr = tp->mmio_addr;
6594
6595 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6596 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6597
6598 RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
6599 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
6600 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6601
6602 rtl_pcie_state_l2l3_enable(tp, false);
6603}
6604
6605static void rtl_hw_start_8101(struct net_device *dev)
6606{
6607 struct rtl8169_private *tp = netdev_priv(dev);
6608 void __iomem *ioaddr = tp->mmio_addr;
6609 struct pci_dev *pdev = tp->pci_dev;
6610
6611 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
6612 tp->event_slow &= ~RxFIFOOver;
6613
6614 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
6615 tp->mac_version == RTL_GIGA_MAC_VER_16)
6616 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
6617 PCI_EXP_DEVCTL_NOSNOOP_EN);
6618
6619 RTL_W8(Cfg9346, Cfg9346_Unlock);
6620
6621 RTL_W8(MaxTxPacketSize, TxPacketMax);
6622
6623 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
6624
6625 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
6626 RTL_W16(CPlusCmd, tp->cp_cmd);
6627
6628 rtl_set_rx_tx_desc_registers(tp, ioaddr);
6629
6630 rtl_set_rx_tx_config_registers(tp);
6631
6632 switch (tp->mac_version) {
6633 case RTL_GIGA_MAC_VER_07:
6634 rtl_hw_start_8102e_1(tp);
6635 break;
6636
6637 case RTL_GIGA_MAC_VER_08:
6638 rtl_hw_start_8102e_3(tp);
6639 break;
6640
6641 case RTL_GIGA_MAC_VER_09:
6642 rtl_hw_start_8102e_2(tp);
6643 break;
6644
6645 case RTL_GIGA_MAC_VER_29:
6646 rtl_hw_start_8105e_1(tp);
6647 break;
6648 case RTL_GIGA_MAC_VER_30:
6649 rtl_hw_start_8105e_2(tp);
6650 break;
6651
6652 case RTL_GIGA_MAC_VER_37:
6653 rtl_hw_start_8402(tp);
6654 break;
6655
6656 case RTL_GIGA_MAC_VER_39:
6657 rtl_hw_start_8106(tp);
6658 break;
6659 case RTL_GIGA_MAC_VER_43:
6660 rtl_hw_start_8168g_2(tp);
6661 break;
6662 case RTL_GIGA_MAC_VER_47:
6663 case RTL_GIGA_MAC_VER_48:
6664 rtl_hw_start_8168h_1(tp);
6665 break;
6666 }
6667
6668 RTL_W8(Cfg9346, Cfg9346_Lock);
6669
6670 RTL_W16(IntrMitigate, 0x0000);
6671
6672 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
6673
6674 rtl_set_rx_mode(dev);
6675
6676 RTL_R8(IntrMask);
6677
6678 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6679}
6680
6681static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
6682{
6683 struct rtl8169_private *tp = netdev_priv(dev);
6684
6685 if (new_mtu > ETH_DATA_LEN)
6686 rtl_hw_jumbo_enable(tp);
6687 else
6688 rtl_hw_jumbo_disable(tp);
6689
6690 dev->mtu = new_mtu;
6691 netdev_update_features(dev);
6692
6693 return 0;
6694}
6695
6696static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
6697{
6698 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
6699 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
6700}
6701
6702static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
6703 void **data_buff, struct RxDesc *desc)
6704{
6705 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
6706 DMA_FROM_DEVICE);
6707
6708 kfree(*data_buff);
6709 *data_buff = NULL;
6710 rtl8169_make_unusable_by_asic(desc);
6711}
6712
6713static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
6714{
6715 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
6716
6717 /* Force memory writes to complete before releasing descriptor */
6718 dma_wmb();
6719
6720 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
6721}
6722
6723static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
6724 u32 rx_buf_sz)
6725{
6726 desc->addr = cpu_to_le64(mapping);
6727 rtl8169_mark_to_asic(desc, rx_buf_sz);
6728}
6729
6730static inline void *rtl8169_align(void *data)
6731{
6732 return (void *)ALIGN((long)data, 16);
6733}
6734
6735static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
6736 struct RxDesc *desc)
6737{
6738 void *data;
6739 dma_addr_t mapping;
6740 struct device *d = &tp->pci_dev->dev;
6741 struct net_device *dev = tp->dev;
6742 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
6743
6744 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
6745 if (!data)
6746 return NULL;
6747
6748 if (rtl8169_align(data) != data) {
6749 kfree(data);
6750 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
6751 if (!data)
6752 return NULL;
6753 }
6754
6755 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
6756 DMA_FROM_DEVICE);
6757 if (unlikely(dma_mapping_error(d, mapping))) {
6758 if (net_ratelimit())
6759 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
6760 goto err_out;
6761 }
6762
6763 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6764 return data;
6765
6766err_out:
6767 kfree(data);
6768 return NULL;
6769}
6770
6771static void rtl8169_rx_clear(struct rtl8169_private *tp)
6772{
6773 unsigned int i;
6774
6775 for (i = 0; i < NUM_RX_DESC; i++) {
6776 if (tp->Rx_databuff[i]) {
6777 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
6778 tp->RxDescArray + i);
6779 }
6780 }
6781}
6782
6783static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
6784{
6785 desc->opts1 |= cpu_to_le32(RingEnd);
6786}
6787
6788static int rtl8169_rx_fill(struct rtl8169_private *tp)
6789{
6790 unsigned int i;
6791
6792 for (i = 0; i < NUM_RX_DESC; i++) {
6793 void *data;
6794
6795 if (tp->Rx_databuff[i])
6796 continue;
6797
6798 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6799 if (!data) {
6800 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
6801 goto err_out;
6802 }
6803 tp->Rx_databuff[i] = data;
6804 }
6805
6806 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
6807 return 0;
6808
6809err_out:
6810 rtl8169_rx_clear(tp);
6811 return -ENOMEM;
6812}
6813
6814static int rtl8169_init_ring(struct net_device *dev)
6815{
6816 struct rtl8169_private *tp = netdev_priv(dev);
6817
6818 rtl8169_init_ring_indexes(tp);
6819
6820 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6821 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
6822
6823 return rtl8169_rx_fill(tp);
6824}
6825
6826static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
6827 struct TxDesc *desc)
6828{
6829 unsigned int len = tx_skb->len;
6830
6831 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
6832
6833 desc->opts1 = 0x00;
6834 desc->opts2 = 0x00;
6835 desc->addr = 0x00;
6836 tx_skb->len = 0;
6837}
6838
6839static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
6840 unsigned int n)
6841{
6842 unsigned int i;
6843
6844 for (i = 0; i < n; i++) {
6845 unsigned int entry = (start + i) % NUM_TX_DESC;
6846 struct ring_info *tx_skb = tp->tx_skb + entry;
6847 unsigned int len = tx_skb->len;
6848
6849 if (len) {
6850 struct sk_buff *skb = tx_skb->skb;
6851
6852 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
6853 tp->TxDescArray + entry);
6854 if (skb) {
6855 tp->dev->stats.tx_dropped++;
6856 dev_kfree_skb_any(skb);
6857 tx_skb->skb = NULL;
6858 }
6859 }
6860 }
6861}
6862
6863static void rtl8169_tx_clear(struct rtl8169_private *tp)
6864{
6865 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
6866 tp->cur_tx = tp->dirty_tx = 0;
6867}
6868
6869static void rtl_reset_work(struct rtl8169_private *tp)
6870{
6871 struct net_device *dev = tp->dev;
6872 int i;
6873
6874 napi_disable(&tp->napi);
6875 netif_stop_queue(dev);
6876 synchronize_sched();
6877
6878 rtl8169_hw_reset(tp);
6879
6880 for (i = 0; i < NUM_RX_DESC; i++)
6881 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
6882
6883 rtl8169_tx_clear(tp);
6884 rtl8169_init_ring_indexes(tp);
6885
6886 napi_enable(&tp->napi);
6887 rtl_hw_start(dev);
6888 netif_wake_queue(dev);
6889 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
6890}
6891
6892static void rtl8169_tx_timeout(struct net_device *dev)
6893{
6894 struct rtl8169_private *tp = netdev_priv(dev);
6895
6896 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6897}
6898
6899static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
6900 u32 *opts)
6901{
6902 struct skb_shared_info *info = skb_shinfo(skb);
6903 unsigned int cur_frag, entry;
6904 struct TxDesc *uninitialized_var(txd);
6905 struct device *d = &tp->pci_dev->dev;
6906
6907 entry = tp->cur_tx;
6908 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
6909 const skb_frag_t *frag = info->frags + cur_frag;
6910 dma_addr_t mapping;
6911 u32 status, len;
6912 void *addr;
6913
6914 entry = (entry + 1) % NUM_TX_DESC;
6915
6916 txd = tp->TxDescArray + entry;
6917 len = skb_frag_size(frag);
6918 addr = skb_frag_address(frag);
6919 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
6920 if (unlikely(dma_mapping_error(d, mapping))) {
6921 if (net_ratelimit())
6922 netif_err(tp, drv, tp->dev,
6923 "Failed to map TX fragments DMA!\n");
6924 goto err_out;
6925 }
6926
6927 /* Anti gcc 2.95.3 bugware (sic) */
6928 status = opts[0] | len |
6929 (RingEnd * !((entry + 1) % NUM_TX_DESC));
6930
6931 txd->opts1 = cpu_to_le32(status);
6932 txd->opts2 = cpu_to_le32(opts[1]);
6933 txd->addr = cpu_to_le64(mapping);
6934
6935 tp->tx_skb[entry].len = len;
6936 }
6937
6938 if (cur_frag) {
6939 tp->tx_skb[entry].skb = skb;
6940 txd->opts1 |= cpu_to_le32(LastFrag);
6941 }
6942
6943 return cur_frag;
6944
6945err_out:
6946 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
6947 return -EIO;
6948}
6949
6950static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
6951{
6952 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
6953}
6954
6955static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6956 struct net_device *dev);
6957/* r8169_csum_workaround()
6958 * The hw limites the value the transport offset. When the offset is out of the
6959 * range, calculate the checksum by sw.
6960 */
6961static void r8169_csum_workaround(struct rtl8169_private *tp,
6962 struct sk_buff *skb)
6963{
6964 if (skb_shinfo(skb)->gso_size) {
6965 netdev_features_t features = tp->dev->features;
6966 struct sk_buff *segs, *nskb;
6967
6968 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
6969 segs = skb_gso_segment(skb, features);
6970 if (IS_ERR(segs) || !segs)
6971 goto drop;
6972
6973 do {
6974 nskb = segs;
6975 segs = segs->next;
6976 nskb->next = NULL;
6977 rtl8169_start_xmit(nskb, tp->dev);
6978 } while (segs);
6979
6980 dev_consume_skb_any(skb);
6981 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6982 if (skb_checksum_help(skb) < 0)
6983 goto drop;
6984
6985 rtl8169_start_xmit(skb, tp->dev);
6986 } else {
6987 struct net_device_stats *stats;
6988
6989drop:
6990 stats = &tp->dev->stats;
6991 stats->tx_dropped++;
6992 dev_kfree_skb_any(skb);
6993 }
6994}
6995
6996/* msdn_giant_send_check()
6997 * According to the document of microsoft, the TCP Pseudo Header excludes the
6998 * packet length for IPv6 TCP large packets.
6999 */
7000static int msdn_giant_send_check(struct sk_buff *skb)
7001{
7002 const struct ipv6hdr *ipv6h;
7003 struct tcphdr *th;
7004 int ret;
7005
7006 ret = skb_cow_head(skb, 0);
7007 if (ret)
7008 return ret;
7009
7010 ipv6h = ipv6_hdr(skb);
7011 th = tcp_hdr(skb);
7012
7013 th->check = 0;
7014 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
7015
7016 return ret;
7017}
7018
7019static inline __be16 get_protocol(struct sk_buff *skb)
7020{
7021 __be16 protocol;
7022
7023 if (skb->protocol == htons(ETH_P_8021Q))
7024 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
7025 else
7026 protocol = skb->protocol;
7027
7028 return protocol;
7029}
7030
7031static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
7032 struct sk_buff *skb, u32 *opts)
7033{
7034 u32 mss = skb_shinfo(skb)->gso_size;
7035
7036 if (mss) {
7037 opts[0] |= TD_LSO;
7038 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
7039 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
7040 const struct iphdr *ip = ip_hdr(skb);
7041
7042 if (ip->protocol == IPPROTO_TCP)
7043 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
7044 else if (ip->protocol == IPPROTO_UDP)
7045 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
7046 else
7047 WARN_ON_ONCE(1);
7048 }
7049
7050 return true;
7051}
7052
7053static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
7054 struct sk_buff *skb, u32 *opts)
7055{
7056 u32 transport_offset = (u32)skb_transport_offset(skb);
7057 u32 mss = skb_shinfo(skb)->gso_size;
7058
7059 if (mss) {
7060 if (transport_offset > GTTCPHO_MAX) {
7061 netif_warn(tp, tx_err, tp->dev,
7062 "Invalid transport offset 0x%x for TSO\n",
7063 transport_offset);
7064 return false;
7065 }
7066
7067 switch (get_protocol(skb)) {
7068 case htons(ETH_P_IP):
7069 opts[0] |= TD1_GTSENV4;
7070 break;
7071
7072 case htons(ETH_P_IPV6):
7073 if (msdn_giant_send_check(skb))
7074 return false;
7075
7076 opts[0] |= TD1_GTSENV6;
7077 break;
7078
7079 default:
7080 WARN_ON_ONCE(1);
7081 break;
7082 }
7083
7084 opts[0] |= transport_offset << GTTCPHO_SHIFT;
7085 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
7086 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
7087 u8 ip_protocol;
7088
7089 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
7090 return !(skb_checksum_help(skb) || eth_skb_pad(skb));
7091
7092 if (transport_offset > TCPHO_MAX) {
7093 netif_warn(tp, tx_err, tp->dev,
7094 "Invalid transport offset 0x%x\n",
7095 transport_offset);
7096 return false;
7097 }
7098
7099 switch (get_protocol(skb)) {
7100 case htons(ETH_P_IP):
7101 opts[1] |= TD1_IPv4_CS;
7102 ip_protocol = ip_hdr(skb)->protocol;
7103 break;
7104
7105 case htons(ETH_P_IPV6):
7106 opts[1] |= TD1_IPv6_CS;
7107 ip_protocol = ipv6_hdr(skb)->nexthdr;
7108 break;
7109
7110 default:
7111 ip_protocol = IPPROTO_RAW;
7112 break;
7113 }
7114
7115 if (ip_protocol == IPPROTO_TCP)
7116 opts[1] |= TD1_TCP_CS;
7117 else if (ip_protocol == IPPROTO_UDP)
7118 opts[1] |= TD1_UDP_CS;
7119 else
7120 WARN_ON_ONCE(1);
7121
7122 opts[1] |= transport_offset << TCPHO_SHIFT;
7123 } else {
7124 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
7125 return !eth_skb_pad(skb);
7126 }
7127
7128 return true;
7129}
7130
7131static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
7132 struct net_device *dev)
7133{
7134 struct rtl8169_private *tp = netdev_priv(dev);
7135 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
7136 struct TxDesc *txd = tp->TxDescArray + entry;
7137 void __iomem *ioaddr = tp->mmio_addr;
7138 struct device *d = &tp->pci_dev->dev;
7139 dma_addr_t mapping;
7140 u32 status, len;
7141 u32 opts[2];
7142 int frags;
7143
7144 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
7145 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
7146 goto err_stop_0;
7147 }
7148
7149 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
7150 goto err_stop_0;
7151
7152 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
7153 opts[0] = DescOwn;
7154
7155 if (!tp->tso_csum(tp, skb, opts)) {
7156 r8169_csum_workaround(tp, skb);
7157 return NETDEV_TX_OK;
7158 }
7159
7160 len = skb_headlen(skb);
7161 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
7162 if (unlikely(dma_mapping_error(d, mapping))) {
7163 if (net_ratelimit())
7164 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
7165 goto err_dma_0;
7166 }
7167
7168 tp->tx_skb[entry].len = len;
7169 txd->addr = cpu_to_le64(mapping);
7170
7171 frags = rtl8169_xmit_frags(tp, skb, opts);
7172 if (frags < 0)
7173 goto err_dma_1;
7174 else if (frags)
7175 opts[0] |= FirstFrag;
7176 else {
7177 opts[0] |= FirstFrag | LastFrag;
7178 tp->tx_skb[entry].skb = skb;
7179 }
7180
7181 txd->opts2 = cpu_to_le32(opts[1]);
7182
7183 skb_tx_timestamp(skb);
7184
7185 /* Force memory writes to complete before releasing descriptor */
7186 dma_wmb();
7187
7188 /* Anti gcc 2.95.3 bugware (sic) */
7189 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
7190 txd->opts1 = cpu_to_le32(status);
7191
7192 /* Force all memory writes to complete before notifying device */
7193 wmb();
7194
7195 tp->cur_tx += frags + 1;
7196
7197 RTL_W8(TxPoll, NPQ);
7198
7199 mmiowb();
7200
7201 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
7202 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
7203 * not miss a ring update when it notices a stopped queue.
7204 */
7205 smp_wmb();
7206 netif_stop_queue(dev);
7207 /* Sync with rtl_tx:
7208 * - publish queue status and cur_tx ring index (write barrier)
7209 * - refresh dirty_tx ring index (read barrier).
7210 * May the current thread have a pessimistic view of the ring
7211 * status and forget to wake up queue, a racing rtl_tx thread
7212 * can't.
7213 */
7214 smp_mb();
7215 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
7216 netif_wake_queue(dev);
7217 }
7218
7219 return NETDEV_TX_OK;
7220
7221err_dma_1:
7222 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
7223err_dma_0:
7224 dev_kfree_skb_any(skb);
7225 dev->stats.tx_dropped++;
7226 return NETDEV_TX_OK;
7227
7228err_stop_0:
7229 netif_stop_queue(dev);
7230 dev->stats.tx_dropped++;
7231 return NETDEV_TX_BUSY;
7232}
7233
7234static void rtl8169_pcierr_interrupt(struct net_device *dev)
7235{
7236 struct rtl8169_private *tp = netdev_priv(dev);
7237 struct pci_dev *pdev = tp->pci_dev;
7238 u16 pci_status, pci_cmd;
7239
7240 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
7241 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
7242
7243 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
7244 pci_cmd, pci_status);
7245
7246 /*
7247 * The recovery sequence below admits a very elaborated explanation:
7248 * - it seems to work;
7249 * - I did not see what else could be done;
7250 * - it makes iop3xx happy.
7251 *
7252 * Feel free to adjust to your needs.
7253 */
7254 if (pdev->broken_parity_status)
7255 pci_cmd &= ~PCI_COMMAND_PARITY;
7256 else
7257 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
7258
7259 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
7260
7261 pci_write_config_word(pdev, PCI_STATUS,
7262 pci_status & (PCI_STATUS_DETECTED_PARITY |
7263 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
7264 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
7265
7266 /* The infamous DAC f*ckup only happens at boot time */
7267 if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
7268 void __iomem *ioaddr = tp->mmio_addr;
7269
7270 netif_info(tp, intr, dev, "disabling PCI DAC\n");
7271 tp->cp_cmd &= ~PCIDAC;
7272 RTL_W16(CPlusCmd, tp->cp_cmd);
7273 dev->features &= ~NETIF_F_HIGHDMA;
7274 }
7275
7276 rtl8169_hw_reset(tp);
7277
7278 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7279}
7280
7281static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
7282{
7283 unsigned int dirty_tx, tx_left;
7284
7285 dirty_tx = tp->dirty_tx;
7286 smp_rmb();
7287 tx_left = tp->cur_tx - dirty_tx;
7288
7289 while (tx_left > 0) {
7290 unsigned int entry = dirty_tx % NUM_TX_DESC;
7291 struct ring_info *tx_skb = tp->tx_skb + entry;
7292 u32 status;
7293
7294 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
7295 if (status & DescOwn)
7296 break;
7297
7298 /* This barrier is needed to keep us from reading
7299 * any other fields out of the Tx descriptor until
7300 * we know the status of DescOwn
7301 */
7302 dma_rmb();
7303
7304 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
7305 tp->TxDescArray + entry);
7306 if (status & LastFrag) {
7307 u64_stats_update_begin(&tp->tx_stats.syncp);
7308 tp->tx_stats.packets++;
7309 tp->tx_stats.bytes += tx_skb->skb->len;
7310 u64_stats_update_end(&tp->tx_stats.syncp);
7311 dev_kfree_skb_any(tx_skb->skb);
7312 tx_skb->skb = NULL;
7313 }
7314 dirty_tx++;
7315 tx_left--;
7316 }
7317
7318 if (tp->dirty_tx != dirty_tx) {
7319 tp->dirty_tx = dirty_tx;
7320 /* Sync with rtl8169_start_xmit:
7321 * - publish dirty_tx ring index (write barrier)
7322 * - refresh cur_tx ring index and queue status (read barrier)
7323 * May the current thread miss the stopped queue condition,
7324 * a racing xmit thread can only have a right view of the
7325 * ring status.
7326 */
7327 smp_mb();
7328 if (netif_queue_stopped(dev) &&
7329 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
7330 netif_wake_queue(dev);
7331 }
7332 /*
7333 * 8168 hack: TxPoll requests are lost when the Tx packets are
7334 * too close. Let's kick an extra TxPoll request when a burst
7335 * of start_xmit activity is detected (if it is not detected,
7336 * it is slow enough). -- FR
7337 */
7338 if (tp->cur_tx != dirty_tx) {
7339 void __iomem *ioaddr = tp->mmio_addr;
7340
7341 RTL_W8(TxPoll, NPQ);
7342 }
7343 }
7344}
7345
7346static inline int rtl8169_fragmented_frame(u32 status)
7347{
7348 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
7349}
7350
7351static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
7352{
7353 u32 status = opts1 & RxProtoMask;
7354
7355 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
7356 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
7357 skb->ip_summed = CHECKSUM_UNNECESSARY;
7358 else
7359 skb_checksum_none_assert(skb);
7360}
7361
7362static struct sk_buff *rtl8169_try_rx_copy(void *data,
7363 struct rtl8169_private *tp,
7364 int pkt_size,
7365 dma_addr_t addr)
7366{
7367 struct sk_buff *skb;
7368 struct device *d = &tp->pci_dev->dev;
7369
7370 data = rtl8169_align(data);
7371 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
7372 prefetch(data);
7373 skb = napi_alloc_skb(&tp->napi, pkt_size);
7374 if (skb)
7375 memcpy(skb->data, data, pkt_size);
7376 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
7377
7378 return skb;
7379}
7380
7381static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
7382{
7383 unsigned int cur_rx, rx_left;
7384 unsigned int count;
7385
7386 cur_rx = tp->cur_rx;
7387
7388 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
7389 unsigned int entry = cur_rx % NUM_RX_DESC;
7390 struct RxDesc *desc = tp->RxDescArray + entry;
7391 u32 status;
7392
7393 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
7394 if (status & DescOwn)
7395 break;
7396
7397 /* This barrier is needed to keep us from reading
7398 * any other fields out of the Rx descriptor until
7399 * we know the status of DescOwn
7400 */
7401 dma_rmb();
7402
7403 if (unlikely(status & RxRES)) {
7404 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
7405 status);
7406 dev->stats.rx_errors++;
7407 if (status & (RxRWT | RxRUNT))
7408 dev->stats.rx_length_errors++;
7409 if (status & RxCRC)
7410 dev->stats.rx_crc_errors++;
7411 if (status & RxFOVF) {
7412 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7413 dev->stats.rx_fifo_errors++;
7414 }
7415 if ((status & (RxRUNT | RxCRC)) &&
7416 !(status & (RxRWT | RxFOVF)) &&
7417 (dev->features & NETIF_F_RXALL))
7418 goto process_pkt;
7419 } else {
7420 struct sk_buff *skb;
7421 dma_addr_t addr;
7422 int pkt_size;
7423
7424process_pkt:
7425 addr = le64_to_cpu(desc->addr);
7426 if (likely(!(dev->features & NETIF_F_RXFCS)))
7427 pkt_size = (status & 0x00003fff) - 4;
7428 else
7429 pkt_size = status & 0x00003fff;
7430
7431 /*
7432 * The driver does not support incoming fragmented
7433 * frames. They are seen as a symptom of over-mtu
7434 * sized frames.
7435 */
7436 if (unlikely(rtl8169_fragmented_frame(status))) {
7437 dev->stats.rx_dropped++;
7438 dev->stats.rx_length_errors++;
7439 goto release_descriptor;
7440 }
7441
7442 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
7443 tp, pkt_size, addr);
7444 if (!skb) {
7445 dev->stats.rx_dropped++;
7446 goto release_descriptor;
7447 }
7448
7449 rtl8169_rx_csum(skb, status);
7450 skb_put(skb, pkt_size);
7451 skb->protocol = eth_type_trans(skb, dev);
7452
7453 rtl8169_rx_vlan_tag(desc, skb);
7454
7455 if (skb->pkt_type == PACKET_MULTICAST)
7456 dev->stats.multicast++;
7457
7458 napi_gro_receive(&tp->napi, skb);
7459
7460 u64_stats_update_begin(&tp->rx_stats.syncp);
7461 tp->rx_stats.packets++;
7462 tp->rx_stats.bytes += pkt_size;
7463 u64_stats_update_end(&tp->rx_stats.syncp);
7464 }
7465release_descriptor:
7466 desc->opts2 = 0;
7467 rtl8169_mark_to_asic(desc, rx_buf_sz);
7468 }
7469
7470 count = cur_rx - tp->cur_rx;
7471 tp->cur_rx = cur_rx;
7472
7473 return count;
7474}
7475
7476static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
7477{
7478 struct net_device *dev = dev_instance;
7479 struct rtl8169_private *tp = netdev_priv(dev);
7480 int handled = 0;
7481 u16 status;
7482
7483 status = rtl_get_events(tp);
7484 if (status && status != 0xffff) {
7485 status &= RTL_EVENT_NAPI | tp->event_slow;
7486 if (status) {
7487 handled = 1;
7488
7489 rtl_irq_disable(tp);
7490 napi_schedule(&tp->napi);
7491 }
7492 }
7493 return IRQ_RETVAL(handled);
7494}
7495
7496/*
7497 * Workqueue context.
7498 */
7499static void rtl_slow_event_work(struct rtl8169_private *tp)
7500{
7501 struct net_device *dev = tp->dev;
7502 u16 status;
7503
7504 status = rtl_get_events(tp) & tp->event_slow;
7505 rtl_ack_events(tp, status);
7506
7507 if (unlikely(status & RxFIFOOver)) {
7508 switch (tp->mac_version) {
7509 /* Work around for rx fifo overflow */
7510 case RTL_GIGA_MAC_VER_11:
7511 netif_stop_queue(dev);
7512 /* XXX - Hack alert. See rtl_task(). */
7513 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
7514 default:
7515 break;
7516 }
7517 }
7518
7519 if (unlikely(status & SYSErr))
7520 rtl8169_pcierr_interrupt(dev);
7521
7522 if (status & LinkChg)
7523 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
7524
7525 rtl_irq_enable_all(tp);
7526}
7527
7528static void rtl_task(struct work_struct *work)
7529{
7530 static const struct {
7531 int bitnr;
7532 void (*action)(struct rtl8169_private *);
7533 } rtl_work[] = {
7534 /* XXX - keep rtl_slow_event_work() as first element. */
7535 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
7536 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
7537 { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work }
7538 };
7539 struct rtl8169_private *tp =
7540 container_of(work, struct rtl8169_private, wk.work);
7541 struct net_device *dev = tp->dev;
7542 int i;
7543
7544 rtl_lock_work(tp);
7545
7546 if (!netif_running(dev) ||
7547 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
7548 goto out_unlock;
7549
7550 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
7551 bool pending;
7552
7553 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
7554 if (pending)
7555 rtl_work[i].action(tp);
7556 }
7557
7558out_unlock:
7559 rtl_unlock_work(tp);
7560}
7561
7562static int rtl8169_poll(struct napi_struct *napi, int budget)
7563{
7564 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
7565 struct net_device *dev = tp->dev;
7566 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
7567 int work_done= 0;
7568 u16 status;
7569
7570 status = rtl_get_events(tp);
7571 rtl_ack_events(tp, status & ~tp->event_slow);
7572
7573 if (status & RTL_EVENT_NAPI_RX)
7574 work_done = rtl_rx(dev, tp, (u32) budget);
7575
7576 if (status & RTL_EVENT_NAPI_TX)
7577 rtl_tx(dev, tp);
7578
7579 if (status & tp->event_slow) {
7580 enable_mask &= ~tp->event_slow;
7581
7582 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
7583 }
7584
7585 if (work_done < budget) {
7586 napi_complete(napi);
7587
7588 rtl_irq_enable(tp, enable_mask);
7589 mmiowb();
7590 }
7591
7592 return work_done;
7593}
7594
7595static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
7596{
7597 struct rtl8169_private *tp = netdev_priv(dev);
7598
7599 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
7600 return;
7601
7602 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
7603 RTL_W32(RxMissed, 0);
7604}
7605
7606static void rtl8169_down(struct net_device *dev)
7607{
7608 struct rtl8169_private *tp = netdev_priv(dev);
7609 void __iomem *ioaddr = tp->mmio_addr;
7610
7611 del_timer_sync(&tp->timer);
7612
7613 napi_disable(&tp->napi);
7614 netif_stop_queue(dev);
7615
7616 rtl8169_hw_reset(tp);
7617 /*
7618 * At this point device interrupts can not be enabled in any function,
7619 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
7620 * and napi is disabled (rtl8169_poll).
7621 */
7622 rtl8169_rx_missed(dev, ioaddr);
7623
7624 /* Give a racing hard_start_xmit a few cycles to complete. */
7625 synchronize_sched();
7626
7627 rtl8169_tx_clear(tp);
7628
7629 rtl8169_rx_clear(tp);
7630
7631 rtl_pll_power_down(tp);
7632}
7633
7634static int rtl8169_close(struct net_device *dev)
7635{
7636 struct rtl8169_private *tp = netdev_priv(dev);
7637 struct pci_dev *pdev = tp->pci_dev;
7638
7639 pm_runtime_get_sync(&pdev->dev);
7640
7641 /* Update counters before going down */
7642 rtl8169_update_counters(dev);
7643
7644 rtl_lock_work(tp);
7645 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7646
7647 rtl8169_down(dev);
7648 rtl_unlock_work(tp);
7649
7650 cancel_work_sync(&tp->wk.work);
7651
7652 free_irq(pdev->irq, dev);
7653
7654 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7655 tp->RxPhyAddr);
7656 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7657 tp->TxPhyAddr);
7658 tp->TxDescArray = NULL;
7659 tp->RxDescArray = NULL;
7660
7661 pm_runtime_put_sync(&pdev->dev);
7662
7663 return 0;
7664}
7665
7666#ifdef CONFIG_NET_POLL_CONTROLLER
7667static void rtl8169_netpoll(struct net_device *dev)
7668{
7669 struct rtl8169_private *tp = netdev_priv(dev);
7670
7671 rtl8169_interrupt(tp->pci_dev->irq, dev);
7672}
7673#endif
7674
7675static int rtl_open(struct net_device *dev)
7676{
7677 struct rtl8169_private *tp = netdev_priv(dev);
7678 void __iomem *ioaddr = tp->mmio_addr;
7679 struct pci_dev *pdev = tp->pci_dev;
7680 int retval = -ENOMEM;
7681
7682 pm_runtime_get_sync(&pdev->dev);
7683
7684 /*
7685 * Rx and Tx descriptors needs 256 bytes alignment.
7686 * dma_alloc_coherent provides more.
7687 */
7688 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
7689 &tp->TxPhyAddr, GFP_KERNEL);
7690 if (!tp->TxDescArray)
7691 goto err_pm_runtime_put;
7692
7693 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
7694 &tp->RxPhyAddr, GFP_KERNEL);
7695 if (!tp->RxDescArray)
7696 goto err_free_tx_0;
7697
7698 retval = rtl8169_init_ring(dev);
7699 if (retval < 0)
7700 goto err_free_rx_1;
7701
7702 INIT_WORK(&tp->wk.work, rtl_task);
7703
7704 smp_mb();
7705
7706 rtl_request_firmware(tp);
7707
7708 retval = request_irq(pdev->irq, rtl8169_interrupt,
7709 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
7710 dev->name, dev);
7711 if (retval < 0)
7712 goto err_release_fw_2;
7713
7714 rtl_lock_work(tp);
7715
7716 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7717
7718 napi_enable(&tp->napi);
7719
7720 rtl8169_init_phy(dev, tp);
7721
7722 __rtl8169_set_features(dev, dev->features);
7723
7724 rtl_pll_power_up(tp);
7725
7726 rtl_hw_start(dev);
7727
7728 if (!rtl8169_init_counter_offsets(dev))
7729 netif_warn(tp, hw, dev, "counter reset/update failed\n");
7730
7731 netif_start_queue(dev);
7732
7733 rtl_unlock_work(tp);
7734
7735 tp->saved_wolopts = 0;
7736 pm_runtime_put_noidle(&pdev->dev);
7737
7738 rtl8169_check_link_status(dev, tp, ioaddr);
7739out:
7740 return retval;
7741
7742err_release_fw_2:
7743 rtl_release_firmware(tp);
7744 rtl8169_rx_clear(tp);
7745err_free_rx_1:
7746 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7747 tp->RxPhyAddr);
7748 tp->RxDescArray = NULL;
7749err_free_tx_0:
7750 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7751 tp->TxPhyAddr);
7752 tp->TxDescArray = NULL;
7753err_pm_runtime_put:
7754 pm_runtime_put_noidle(&pdev->dev);
7755 goto out;
7756}
7757
7758static struct rtnl_link_stats64 *
7759rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
7760{
7761 struct rtl8169_private *tp = netdev_priv(dev);
7762 void __iomem *ioaddr = tp->mmio_addr;
7763 struct pci_dev *pdev = tp->pci_dev;
7764 struct rtl8169_counters *counters = tp->counters;
7765 unsigned int start;
7766
7767 pm_runtime_get_noresume(&pdev->dev);
7768
7769 if (netif_running(dev) && pm_runtime_active(&pdev->dev))
7770 rtl8169_rx_missed(dev, ioaddr);
7771
7772 do {
7773 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
7774 stats->rx_packets = tp->rx_stats.packets;
7775 stats->rx_bytes = tp->rx_stats.bytes;
7776 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
7777
7778 do {
7779 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
7780 stats->tx_packets = tp->tx_stats.packets;
7781 stats->tx_bytes = tp->tx_stats.bytes;
7782 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
7783
7784 stats->rx_dropped = dev->stats.rx_dropped;
7785 stats->tx_dropped = dev->stats.tx_dropped;
7786 stats->rx_length_errors = dev->stats.rx_length_errors;
7787 stats->rx_errors = dev->stats.rx_errors;
7788 stats->rx_crc_errors = dev->stats.rx_crc_errors;
7789 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
7790 stats->rx_missed_errors = dev->stats.rx_missed_errors;
7791 stats->multicast = dev->stats.multicast;
7792
7793 /*
7794 * Fetch additonal counter values missing in stats collected by driver
7795 * from tally counters.
7796 */
7797 if (pm_runtime_active(&pdev->dev))
7798 rtl8169_update_counters(dev);
7799
7800 /*
7801 * Subtract values fetched during initalization.
7802 * See rtl8169_init_counter_offsets for a description why we do that.
7803 */
7804 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
7805 le64_to_cpu(tp->tc_offset.tx_errors);
7806 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
7807 le32_to_cpu(tp->tc_offset.tx_multi_collision);
7808 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
7809 le16_to_cpu(tp->tc_offset.tx_aborted);
7810
7811 pm_runtime_put_noidle(&pdev->dev);
7812
7813 return stats;
7814}
7815
7816static void rtl8169_net_suspend(struct net_device *dev)
7817{
7818 struct rtl8169_private *tp = netdev_priv(dev);
7819
7820 if (!netif_running(dev))
7821 return;
7822
7823 netif_device_detach(dev);
7824 netif_stop_queue(dev);
7825
7826 rtl_lock_work(tp);
7827 napi_disable(&tp->napi);
7828 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7829 rtl_unlock_work(tp);
7830
7831 rtl_pll_power_down(tp);
7832}
7833
7834#ifdef CONFIG_PM
7835
7836static int rtl8169_suspend(struct device *device)
7837{
7838 struct pci_dev *pdev = to_pci_dev(device);
7839 struct net_device *dev = pci_get_drvdata(pdev);
7840
7841 rtl8169_net_suspend(dev);
7842
7843 return 0;
7844}
7845
7846static void __rtl8169_resume(struct net_device *dev)
7847{
7848 struct rtl8169_private *tp = netdev_priv(dev);
7849
7850 netif_device_attach(dev);
7851
7852 rtl_pll_power_up(tp);
7853
7854 rtl_lock_work(tp);
7855 napi_enable(&tp->napi);
7856 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7857 rtl_unlock_work(tp);
7858
7859 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7860}
7861
7862static int rtl8169_resume(struct device *device)
7863{
7864 struct pci_dev *pdev = to_pci_dev(device);
7865 struct net_device *dev = pci_get_drvdata(pdev);
7866 struct rtl8169_private *tp = netdev_priv(dev);
7867
7868 rtl8169_init_phy(dev, tp);
7869
7870 if (netif_running(dev))
7871 __rtl8169_resume(dev);
7872
7873 return 0;
7874}
7875
7876static int rtl8169_runtime_suspend(struct device *device)
7877{
7878 struct pci_dev *pdev = to_pci_dev(device);
7879 struct net_device *dev = pci_get_drvdata(pdev);
7880 struct rtl8169_private *tp = netdev_priv(dev);
7881
7882 if (!tp->TxDescArray)
7883 return 0;
7884
7885 rtl_lock_work(tp);
7886 tp->saved_wolopts = __rtl8169_get_wol(tp);
7887 __rtl8169_set_wol(tp, WAKE_ANY);
7888 rtl_unlock_work(tp);
7889
7890 rtl8169_net_suspend(dev);
7891
7892 /* Update counters before going runtime suspend */
7893 rtl8169_rx_missed(dev, tp->mmio_addr);
7894 rtl8169_update_counters(dev);
7895
7896 return 0;
7897}
7898
7899static int rtl8169_runtime_resume(struct device *device)
7900{
7901 struct pci_dev *pdev = to_pci_dev(device);
7902 struct net_device *dev = pci_get_drvdata(pdev);
7903 struct rtl8169_private *tp = netdev_priv(dev);
7904 rtl_rar_set(tp, dev->dev_addr);
7905
7906 if (!tp->TxDescArray)
7907 return 0;
7908
7909 rtl_lock_work(tp);
7910 __rtl8169_set_wol(tp, tp->saved_wolopts);
7911 tp->saved_wolopts = 0;
7912 rtl_unlock_work(tp);
7913
7914 rtl8169_init_phy(dev, tp);
7915
7916 __rtl8169_resume(dev);
7917
7918 return 0;
7919}
7920
7921static int rtl8169_runtime_idle(struct device *device)
7922{
7923 struct pci_dev *pdev = to_pci_dev(device);
7924 struct net_device *dev = pci_get_drvdata(pdev);
7925 struct rtl8169_private *tp = netdev_priv(dev);
7926
7927 return tp->TxDescArray ? -EBUSY : 0;
7928}
7929
7930static const struct dev_pm_ops rtl8169_pm_ops = {
7931 .suspend = rtl8169_suspend,
7932 .resume = rtl8169_resume,
7933 .freeze = rtl8169_suspend,
7934 .thaw = rtl8169_resume,
7935 .poweroff = rtl8169_suspend,
7936 .restore = rtl8169_resume,
7937 .runtime_suspend = rtl8169_runtime_suspend,
7938 .runtime_resume = rtl8169_runtime_resume,
7939 .runtime_idle = rtl8169_runtime_idle,
7940};
7941
7942#define RTL8169_PM_OPS (&rtl8169_pm_ops)
7943
7944#else /* !CONFIG_PM */
7945
7946#define RTL8169_PM_OPS NULL
7947
7948#endif /* !CONFIG_PM */
7949
7950static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
7951{
7952 void __iomem *ioaddr = tp->mmio_addr;
7953
7954 /* WoL fails with 8168b when the receiver is disabled. */
7955 switch (tp->mac_version) {
7956 case RTL_GIGA_MAC_VER_11:
7957 case RTL_GIGA_MAC_VER_12:
7958 case RTL_GIGA_MAC_VER_17:
7959 pci_clear_master(tp->pci_dev);
7960
7961 RTL_W8(ChipCmd, CmdRxEnb);
7962 /* PCI commit */
7963 RTL_R8(ChipCmd);
7964 break;
7965 default:
7966 break;
7967 }
7968}
7969
7970static void rtl_shutdown(struct pci_dev *pdev)
7971{
7972 struct net_device *dev = pci_get_drvdata(pdev);
7973 struct rtl8169_private *tp = netdev_priv(dev);
7974 struct device *d = &pdev->dev;
7975
7976 pm_runtime_get_sync(d);
7977
7978 rtl8169_net_suspend(dev);
7979
7980 /* Restore original MAC address */
7981 rtl_rar_set(tp, dev->perm_addr);
7982
7983 rtl8169_hw_reset(tp);
7984
7985 if (system_state == SYSTEM_POWER_OFF) {
7986 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
7987 rtl_wol_suspend_quirk(tp);
7988 rtl_wol_shutdown_quirk(tp);
7989 }
7990
7991 pci_wake_from_d3(pdev, true);
7992 pci_set_power_state(pdev, PCI_D3hot);
7993 }
7994
7995 pm_runtime_put_noidle(d);
7996}
7997
7998static void rtl_remove_one(struct pci_dev *pdev)
7999{
8000 struct net_device *dev = pci_get_drvdata(pdev);
8001 struct rtl8169_private *tp = netdev_priv(dev);
8002
8003 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
8004 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
8005 tp->mac_version == RTL_GIGA_MAC_VER_31 ||
8006 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8007 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8008 tp->mac_version == RTL_GIGA_MAC_VER_51) &&
8009 r8168_check_dash(tp)) {
8010 rtl8168_driver_stop(tp);
8011 }
8012
8013 netif_napi_del(&tp->napi);
8014
8015 unregister_netdev(dev);
8016
8017 dma_free_coherent(&tp->pci_dev->dev, sizeof(*tp->counters),
8018 tp->counters, tp->counters_phys_addr);
8019
8020 rtl_release_firmware(tp);
8021
8022 if (pci_dev_run_wake(pdev))
8023 pm_runtime_get_noresume(&pdev->dev);
8024
8025 /* restore original MAC address */
8026 rtl_rar_set(tp, dev->perm_addr);
8027
8028 rtl_disable_msi(pdev, tp);
8029 rtl8169_release_board(pdev, dev, tp->mmio_addr);
8030}
8031
8032static const struct net_device_ops rtl_netdev_ops = {
8033 .ndo_open = rtl_open,
8034 .ndo_stop = rtl8169_close,
8035 .ndo_get_stats64 = rtl8169_get_stats64,
8036 .ndo_start_xmit = rtl8169_start_xmit,
8037 .ndo_tx_timeout = rtl8169_tx_timeout,
8038 .ndo_validate_addr = eth_validate_addr,
8039 .ndo_change_mtu = rtl8169_change_mtu,
8040 .ndo_fix_features = rtl8169_fix_features,
8041 .ndo_set_features = rtl8169_set_features,
8042 .ndo_set_mac_address = rtl_set_mac_address,
8043 .ndo_do_ioctl = rtl8169_ioctl,
8044 .ndo_set_rx_mode = rtl_set_rx_mode,
8045#ifdef CONFIG_NET_POLL_CONTROLLER
8046 .ndo_poll_controller = rtl8169_netpoll,
8047#endif
8048
8049};
8050
8051static const struct rtl_cfg_info {
8052 void (*hw_start)(struct net_device *);
8053 unsigned int region;
8054 unsigned int align;
8055 u16 event_slow;
8056 unsigned features;
8057 u8 default_ver;
8058} rtl_cfg_infos [] = {
8059 [RTL_CFG_0] = {
8060 .hw_start = rtl_hw_start_8169,
8061 .region = 1,
8062 .align = 0,
8063 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
8064 .features = RTL_FEATURE_GMII,
8065 .default_ver = RTL_GIGA_MAC_VER_01,
8066 },
8067 [RTL_CFG_1] = {
8068 .hw_start = rtl_hw_start_8168,
8069 .region = 2,
8070 .align = 8,
8071 .event_slow = SYSErr | LinkChg | RxOverflow,
8072 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
8073 .default_ver = RTL_GIGA_MAC_VER_11,
8074 },
8075 [RTL_CFG_2] = {
8076 .hw_start = rtl_hw_start_8101,
8077 .region = 2,
8078 .align = 8,
8079 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
8080 PCSTimeout,
8081 .features = RTL_FEATURE_MSI,
8082 .default_ver = RTL_GIGA_MAC_VER_13,
8083 }
8084};
8085
8086/* Cfg9346_Unlock assumed. */
8087static unsigned rtl_try_msi(struct rtl8169_private *tp,
8088 const struct rtl_cfg_info *cfg)
8089{
8090 void __iomem *ioaddr = tp->mmio_addr;
8091 unsigned msi = 0;
8092 u8 cfg2;
8093
8094 cfg2 = RTL_R8(Config2) & ~MSIEnable;
8095 if (cfg->features & RTL_FEATURE_MSI) {
8096 if (pci_enable_msi(tp->pci_dev)) {
8097 netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
8098 } else {
8099 cfg2 |= MSIEnable;
8100 msi = RTL_FEATURE_MSI;
8101 }
8102 }
8103 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
8104 RTL_W8(Config2, cfg2);
8105 return msi;
8106}
8107
8108DECLARE_RTL_COND(rtl_link_list_ready_cond)
8109{
8110 void __iomem *ioaddr = tp->mmio_addr;
8111
8112 return RTL_R8(MCU) & LINK_LIST_RDY;
8113}
8114
8115DECLARE_RTL_COND(rtl_rxtx_empty_cond)
8116{
8117 void __iomem *ioaddr = tp->mmio_addr;
8118
8119 return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
8120}
8121
8122static void rtl_hw_init_8168g(struct rtl8169_private *tp)
8123{
8124 void __iomem *ioaddr = tp->mmio_addr;
8125 u32 data;
8126
8127 tp->ocp_base = OCP_STD_PHY_BASE;
8128
8129 RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
8130
8131 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
8132 return;
8133
8134 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
8135 return;
8136
8137 RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
8138 msleep(1);
8139 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
8140
8141 data = r8168_mac_ocp_read(tp, 0xe8de);
8142 data &= ~(1 << 14);
8143 r8168_mac_ocp_write(tp, 0xe8de, data);
8144
8145 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
8146 return;
8147
8148 data = r8168_mac_ocp_read(tp, 0xe8de);
8149 data |= (1 << 15);
8150 r8168_mac_ocp_write(tp, 0xe8de, data);
8151
8152 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
8153 return;
8154}
8155
8156static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
8157{
8158 rtl8168ep_stop_cmac(tp);
8159 rtl_hw_init_8168g(tp);
8160}
8161
8162static void rtl_hw_initialize(struct rtl8169_private *tp)
8163{
8164 switch (tp->mac_version) {
8165 case RTL_GIGA_MAC_VER_40:
8166 case RTL_GIGA_MAC_VER_41:
8167 case RTL_GIGA_MAC_VER_42:
8168 case RTL_GIGA_MAC_VER_43:
8169 case RTL_GIGA_MAC_VER_44:
8170 case RTL_GIGA_MAC_VER_45:
8171 case RTL_GIGA_MAC_VER_46:
8172 case RTL_GIGA_MAC_VER_47:
8173 case RTL_GIGA_MAC_VER_48:
8174 rtl_hw_init_8168g(tp);
8175 break;
8176 case RTL_GIGA_MAC_VER_49:
8177 case RTL_GIGA_MAC_VER_50:
8178 case RTL_GIGA_MAC_VER_51:
8179 rtl_hw_init_8168ep(tp);
8180 break;
8181 default:
8182 break;
8183 }
8184}
8185
8186static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
8187{
8188 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
8189 const unsigned int region = cfg->region;
8190 struct rtl8169_private *tp;
8191 struct mii_if_info *mii;
8192 struct net_device *dev;
8193 void __iomem *ioaddr;
8194 int chipset, i;
8195 int rc;
8196
8197 if (netif_msg_drv(&debug)) {
8198 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
8199 MODULENAME, RTL8169_VERSION);
8200 }
8201
8202 dev = alloc_etherdev(sizeof (*tp));
8203 if (!dev) {
8204 rc = -ENOMEM;
8205 goto out;
8206 }
8207
8208 SET_NETDEV_DEV(dev, &pdev->dev);
8209 dev->netdev_ops = &rtl_netdev_ops;
8210 tp = netdev_priv(dev);
8211 tp->dev = dev;
8212 tp->pci_dev = pdev;
8213 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
8214
8215 mii = &tp->mii;
8216 mii->dev = dev;
8217 mii->mdio_read = rtl_mdio_read;
8218 mii->mdio_write = rtl_mdio_write;
8219 mii->phy_id_mask = 0x1f;
8220 mii->reg_num_mask = 0x1f;
8221 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
8222
8223 /* disable ASPM completely as that cause random device stop working
8224 * problems as well as full system hangs for some PCIe devices users */
8225 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
8226 PCIE_LINK_STATE_CLKPM);
8227
8228 /* enable device (incl. PCI PM wakeup and hotplug setup) */
8229 rc = pci_enable_device(pdev);
8230 if (rc < 0) {
8231 netif_err(tp, probe, dev, "enable failure\n");
8232 goto err_out_free_dev_1;
8233 }
8234
8235 if (pci_set_mwi(pdev) < 0)
8236 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
8237
8238 /* make sure PCI base addr 1 is MMIO */
8239 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
8240 netif_err(tp, probe, dev,
8241 "region #%d not an MMIO resource, aborting\n",
8242 region);
8243 rc = -ENODEV;
8244 goto err_out_mwi_2;
8245 }
8246
8247 /* check for weird/broken PCI region reporting */
8248 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
8249 netif_err(tp, probe, dev,
8250 "Invalid PCI region size(s), aborting\n");
8251 rc = -ENODEV;
8252 goto err_out_mwi_2;
8253 }
8254
8255 rc = pci_request_regions(pdev, MODULENAME);
8256 if (rc < 0) {
8257 netif_err(tp, probe, dev, "could not request regions\n");
8258 goto err_out_mwi_2;
8259 }
8260
8261 /* ioremap MMIO region */
8262 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
8263 if (!ioaddr) {
8264 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
8265 rc = -EIO;
8266 goto err_out_free_res_3;
8267 }
8268 tp->mmio_addr = ioaddr;
8269
8270 if (!pci_is_pcie(pdev))
8271 netif_info(tp, probe, dev, "not PCI Express\n");
8272
8273 /* Identify chip attached to board */
8274 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
8275
8276 tp->cp_cmd = 0;
8277
8278 if ((sizeof(dma_addr_t) > 4) &&
8279 (use_dac == 1 || (use_dac == -1 && pci_is_pcie(pdev) &&
8280 tp->mac_version >= RTL_GIGA_MAC_VER_18)) &&
8281 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
8282 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
8283
8284 /* CPlusCmd Dual Access Cycle is only needed for non-PCIe */
8285 if (!pci_is_pcie(pdev))
8286 tp->cp_cmd |= PCIDAC;
8287 dev->features |= NETIF_F_HIGHDMA;
8288 } else {
8289 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
8290 if (rc < 0) {
8291 netif_err(tp, probe, dev, "DMA configuration failed\n");
8292 goto err_out_unmap_4;
8293 }
8294 }
8295
8296 rtl_init_rxcfg(tp);
8297
8298 rtl_irq_disable(tp);
8299
8300 rtl_hw_initialize(tp);
8301
8302 rtl_hw_reset(tp);
8303
8304 rtl_ack_events(tp, 0xffff);
8305
8306 pci_set_master(pdev);
8307
8308 rtl_init_mdio_ops(tp);
8309 rtl_init_pll_power_ops(tp);
8310 rtl_init_jumbo_ops(tp);
8311 rtl_init_csi_ops(tp);
8312
8313 rtl8169_print_mac_version(tp);
8314
8315 chipset = tp->mac_version;
8316 tp->txd_version = rtl_chip_infos[chipset].txd_version;
8317
8318 RTL_W8(Cfg9346, Cfg9346_Unlock);
8319 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
8320 RTL_W8(Config5, RTL_R8(Config5) & (BWF | MWF | UWF | LanWake | PMEStatus));
8321 switch (tp->mac_version) {
8322 case RTL_GIGA_MAC_VER_34:
8323 case RTL_GIGA_MAC_VER_35:
8324 case RTL_GIGA_MAC_VER_36:
8325 case RTL_GIGA_MAC_VER_37:
8326 case RTL_GIGA_MAC_VER_38:
8327 case RTL_GIGA_MAC_VER_40:
8328 case RTL_GIGA_MAC_VER_41:
8329 case RTL_GIGA_MAC_VER_42:
8330 case RTL_GIGA_MAC_VER_43:
8331 case RTL_GIGA_MAC_VER_44:
8332 case RTL_GIGA_MAC_VER_45:
8333 case RTL_GIGA_MAC_VER_46:
8334 case RTL_GIGA_MAC_VER_47:
8335 case RTL_GIGA_MAC_VER_48:
8336 case RTL_GIGA_MAC_VER_49:
8337 case RTL_GIGA_MAC_VER_50:
8338 case RTL_GIGA_MAC_VER_51:
8339 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
8340 tp->features |= RTL_FEATURE_WOL;
8341 if ((RTL_R8(Config3) & LinkUp) != 0)
8342 tp->features |= RTL_FEATURE_WOL;
8343 break;
8344 default:
8345 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
8346 tp->features |= RTL_FEATURE_WOL;
8347 break;
8348 }
8349 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
8350 tp->features |= RTL_FEATURE_WOL;
8351 tp->features |= rtl_try_msi(tp, cfg);
8352 RTL_W8(Cfg9346, Cfg9346_Lock);
8353
8354 if (rtl_tbi_enabled(tp)) {
8355 tp->set_speed = rtl8169_set_speed_tbi;
8356 tp->get_settings = rtl8169_gset_tbi;
8357 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
8358 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
8359 tp->link_ok = rtl8169_tbi_link_ok;
8360 tp->do_ioctl = rtl_tbi_ioctl;
8361 } else {
8362 tp->set_speed = rtl8169_set_speed_xmii;
8363 tp->get_settings = rtl8169_gset_xmii;
8364 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
8365 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
8366 tp->link_ok = rtl8169_xmii_link_ok;
8367 tp->do_ioctl = rtl_xmii_ioctl;
8368 }
8369
8370 mutex_init(&tp->wk.mutex);
8371 u64_stats_init(&tp->rx_stats.syncp);
8372 u64_stats_init(&tp->tx_stats.syncp);
8373
8374 /* Get MAC address */
8375 if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
8376 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
8377 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
8378 tp->mac_version == RTL_GIGA_MAC_VER_38 ||
8379 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
8380 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
8381 tp->mac_version == RTL_GIGA_MAC_VER_42 ||
8382 tp->mac_version == RTL_GIGA_MAC_VER_43 ||
8383 tp->mac_version == RTL_GIGA_MAC_VER_44 ||
8384 tp->mac_version == RTL_GIGA_MAC_VER_45 ||
8385 tp->mac_version == RTL_GIGA_MAC_VER_46 ||
8386 tp->mac_version == RTL_GIGA_MAC_VER_47 ||
8387 tp->mac_version == RTL_GIGA_MAC_VER_48 ||
8388 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8389 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8390 tp->mac_version == RTL_GIGA_MAC_VER_51) {
8391 u16 mac_addr[3];
8392
8393 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
8394 *(u16 *)&mac_addr[2] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
8395
8396 if (is_valid_ether_addr((u8 *)mac_addr))
8397 rtl_rar_set(tp, (u8 *)mac_addr);
8398 }
8399 for (i = 0; i < ETH_ALEN; i++)
8400 dev->dev_addr[i] = RTL_R8(MAC0 + i);
8401
8402 dev->ethtool_ops = &rtl8169_ethtool_ops;
8403 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
8404
8405 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
8406
8407 /* don't enable SG, IP_CSUM and TSO by default - it might not work
8408 * properly for all devices */
8409 dev->features |= NETIF_F_RXCSUM |
8410 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
8411
8412 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
8413 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
8414 NETIF_F_HW_VLAN_CTAG_RX;
8415 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
8416 NETIF_F_HIGHDMA;
8417
8418 tp->cp_cmd |= RxChkSum | RxVlan;
8419
8420 /*
8421 * Pretend we are using VLANs; This bypasses a nasty bug where
8422 * Interrupts stop flowing on high load on 8110SCd controllers.
8423 */
8424 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
8425 /* Disallow toggling */
8426 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
8427
8428 if (tp->txd_version == RTL_TD_0)
8429 tp->tso_csum = rtl8169_tso_csum_v1;
8430 else if (tp->txd_version == RTL_TD_1) {
8431 tp->tso_csum = rtl8169_tso_csum_v2;
8432 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
8433 } else
8434 WARN_ON_ONCE(1);
8435
8436 dev->hw_features |= NETIF_F_RXALL;
8437 dev->hw_features |= NETIF_F_RXFCS;
8438
8439 /* MTU range: 60 - hw-specific max */
8440 dev->min_mtu = ETH_ZLEN;
8441 dev->max_mtu = rtl_chip_infos[chipset].jumbo_max;
8442
8443 tp->hw_start = cfg->hw_start;
8444 tp->event_slow = cfg->event_slow;
8445
8446 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
8447 ~(RxBOVF | RxFOVF) : ~0;
8448
8449 init_timer(&tp->timer);
8450 tp->timer.data = (unsigned long) dev;
8451 tp->timer.function = rtl8169_phy_timer;
8452
8453 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
8454
8455 tp->counters = dma_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
8456 &tp->counters_phys_addr, GFP_KERNEL);
8457 if (!tp->counters) {
8458 rc = -ENOMEM;
8459 goto err_out_msi_5;
8460 }
8461
8462 rc = register_netdev(dev);
8463 if (rc < 0)
8464 goto err_out_cnt_6;
8465
8466 pci_set_drvdata(pdev, dev);
8467
8468 netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
8469 rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
8470 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
8471 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
8472 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
8473 "tx checksumming: %s]\n",
8474 rtl_chip_infos[chipset].jumbo_max,
8475 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
8476 }
8477
8478 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
8479 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
8480 tp->mac_version == RTL_GIGA_MAC_VER_31 ||
8481 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8482 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8483 tp->mac_version == RTL_GIGA_MAC_VER_51) &&
8484 r8168_check_dash(tp)) {
8485 rtl8168_driver_start(tp);
8486 }
8487
8488 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
8489
8490 if (pci_dev_run_wake(pdev))
8491 pm_runtime_put_noidle(&pdev->dev);
8492
8493 netif_carrier_off(dev);
8494
8495out:
8496 return rc;
8497
8498err_out_cnt_6:
8499 dma_free_coherent(&pdev->dev, sizeof(*tp->counters), tp->counters,
8500 tp->counters_phys_addr);
8501err_out_msi_5:
8502 netif_napi_del(&tp->napi);
8503 rtl_disable_msi(pdev, tp);
8504err_out_unmap_4:
8505 iounmap(ioaddr);
8506err_out_free_res_3:
8507 pci_release_regions(pdev);
8508err_out_mwi_2:
8509 pci_clear_mwi(pdev);
8510 pci_disable_device(pdev);
8511err_out_free_dev_1:
8512 free_netdev(dev);
8513 goto out;
8514}
8515
8516static struct pci_driver rtl8169_pci_driver = {
8517 .name = MODULENAME,
8518 .id_table = rtl8169_pci_tbl,
8519 .probe = rtl_init_one,
8520 .remove = rtl_remove_one,
8521 .shutdown = rtl_shutdown,
8522 .driver.pm = RTL8169_PM_OPS,
8523};
8524
8525module_pci_driver(rtl8169_pci_driver);
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