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1 | /* | |
2 | * tg3.c: Broadcom Tigon3 ethernet driver. | |
3 | * | |
4 | * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com) | |
5 | * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com) | |
6 | * Copyright (C) 2004 Sun Microsystems Inc. | |
7 | * Copyright (C) 2005-2011 Broadcom Corporation. | |
8 | * | |
9 | * Firmware is: | |
10 | * Derived from proprietary unpublished source code, | |
11 | * Copyright (C) 2000-2003 Broadcom Corporation. | |
12 | * | |
13 | * Permission is hereby granted for the distribution of this firmware | |
14 | * data in hexadecimal or equivalent format, provided this copyright | |
15 | * notice is accompanying it. | |
16 | */ | |
17 | ||
18 | ||
19 | #include <linux/module.h> | |
20 | #include <linux/moduleparam.h> | |
21 | #include <linux/stringify.h> | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/types.h> | |
24 | #include <linux/compiler.h> | |
25 | #include <linux/slab.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/in.h> | |
28 | #include <linux/init.h> | |
29 | #include <linux/interrupt.h> | |
30 | #include <linux/ioport.h> | |
31 | #include <linux/pci.h> | |
32 | #include <linux/netdevice.h> | |
33 | #include <linux/etherdevice.h> | |
34 | #include <linux/skbuff.h> | |
35 | #include <linux/ethtool.h> | |
36 | #include <linux/mdio.h> | |
37 | #include <linux/mii.h> | |
38 | #include <linux/phy.h> | |
39 | #include <linux/brcmphy.h> | |
40 | #include <linux/if_vlan.h> | |
41 | #include <linux/ip.h> | |
42 | #include <linux/tcp.h> | |
43 | #include <linux/workqueue.h> | |
44 | #include <linux/prefetch.h> | |
45 | #include <linux/dma-mapping.h> | |
46 | #include <linux/firmware.h> | |
47 | ||
48 | #include <net/checksum.h> | |
49 | #include <net/ip.h> | |
50 | ||
51 | #include <asm/system.h> | |
52 | #include <linux/io.h> | |
53 | #include <asm/byteorder.h> | |
54 | #include <linux/uaccess.h> | |
55 | ||
56 | #ifdef CONFIG_SPARC | |
57 | #include <asm/idprom.h> | |
58 | #include <asm/prom.h> | |
59 | #endif | |
60 | ||
61 | #define BAR_0 0 | |
62 | #define BAR_2 2 | |
63 | ||
64 | #include "tg3.h" | |
65 | ||
66 | /* Functions & macros to verify TG3_FLAGS types */ | |
67 | ||
68 | static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits) | |
69 | { | |
70 | return test_bit(flag, bits); | |
71 | } | |
72 | ||
73 | static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits) | |
74 | { | |
75 | set_bit(flag, bits); | |
76 | } | |
77 | ||
78 | static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits) | |
79 | { | |
80 | clear_bit(flag, bits); | |
81 | } | |
82 | ||
83 | #define tg3_flag(tp, flag) \ | |
84 | _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags) | |
85 | #define tg3_flag_set(tp, flag) \ | |
86 | _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags) | |
87 | #define tg3_flag_clear(tp, flag) \ | |
88 | _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags) | |
89 | ||
90 | #define DRV_MODULE_NAME "tg3" | |
91 | #define TG3_MAJ_NUM 3 | |
92 | #define TG3_MIN_NUM 119 | |
93 | #define DRV_MODULE_VERSION \ | |
94 | __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM) | |
95 | #define DRV_MODULE_RELDATE "May 18, 2011" | |
96 | ||
97 | #define TG3_DEF_MAC_MODE 0 | |
98 | #define TG3_DEF_RX_MODE 0 | |
99 | #define TG3_DEF_TX_MODE 0 | |
100 | #define TG3_DEF_MSG_ENABLE \ | |
101 | (NETIF_MSG_DRV | \ | |
102 | NETIF_MSG_PROBE | \ | |
103 | NETIF_MSG_LINK | \ | |
104 | NETIF_MSG_TIMER | \ | |
105 | NETIF_MSG_IFDOWN | \ | |
106 | NETIF_MSG_IFUP | \ | |
107 | NETIF_MSG_RX_ERR | \ | |
108 | NETIF_MSG_TX_ERR) | |
109 | ||
110 | /* length of time before we decide the hardware is borked, | |
111 | * and dev->tx_timeout() should be called to fix the problem | |
112 | */ | |
113 | ||
114 | #define TG3_TX_TIMEOUT (5 * HZ) | |
115 | ||
116 | /* hardware minimum and maximum for a single frame's data payload */ | |
117 | #define TG3_MIN_MTU 60 | |
118 | #define TG3_MAX_MTU(tp) \ | |
119 | (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500) | |
120 | ||
121 | /* These numbers seem to be hard coded in the NIC firmware somehow. | |
122 | * You can't change the ring sizes, but you can change where you place | |
123 | * them in the NIC onboard memory. | |
124 | */ | |
125 | #define TG3_RX_STD_RING_SIZE(tp) \ | |
126 | (tg3_flag(tp, LRG_PROD_RING_CAP) ? \ | |
127 | TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700) | |
128 | #define TG3_DEF_RX_RING_PENDING 200 | |
129 | #define TG3_RX_JMB_RING_SIZE(tp) \ | |
130 | (tg3_flag(tp, LRG_PROD_RING_CAP) ? \ | |
131 | TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700) | |
132 | #define TG3_DEF_RX_JUMBO_RING_PENDING 100 | |
133 | #define TG3_RSS_INDIR_TBL_SIZE 128 | |
134 | ||
135 | /* Do not place this n-ring entries value into the tp struct itself, | |
136 | * we really want to expose these constants to GCC so that modulo et | |
137 | * al. operations are done with shifts and masks instead of with | |
138 | * hw multiply/modulo instructions. Another solution would be to | |
139 | * replace things like '% foo' with '& (foo - 1)'. | |
140 | */ | |
141 | ||
142 | #define TG3_TX_RING_SIZE 512 | |
143 | #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1) | |
144 | ||
145 | #define TG3_RX_STD_RING_BYTES(tp) \ | |
146 | (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp)) | |
147 | #define TG3_RX_JMB_RING_BYTES(tp) \ | |
148 | (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp)) | |
149 | #define TG3_RX_RCB_RING_BYTES(tp) \ | |
150 | (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1)) | |
151 | #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \ | |
152 | TG3_TX_RING_SIZE) | |
153 | #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1)) | |
154 | ||
155 | #define TG3_DMA_BYTE_ENAB 64 | |
156 | ||
157 | #define TG3_RX_STD_DMA_SZ 1536 | |
158 | #define TG3_RX_JMB_DMA_SZ 9046 | |
159 | ||
160 | #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB) | |
161 | ||
162 | #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ) | |
163 | #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ) | |
164 | ||
165 | #define TG3_RX_STD_BUFF_RING_SIZE(tp) \ | |
166 | (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp)) | |
167 | ||
168 | #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \ | |
169 | (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp)) | |
170 | ||
171 | /* Due to a hardware bug, the 5701 can only DMA to memory addresses | |
172 | * that are at least dword aligned when used in PCIX mode. The driver | |
173 | * works around this bug by double copying the packet. This workaround | |
174 | * is built into the normal double copy length check for efficiency. | |
175 | * | |
176 | * However, the double copy is only necessary on those architectures | |
177 | * where unaligned memory accesses are inefficient. For those architectures | |
178 | * where unaligned memory accesses incur little penalty, we can reintegrate | |
179 | * the 5701 in the normal rx path. Doing so saves a device structure | |
180 | * dereference by hardcoding the double copy threshold in place. | |
181 | */ | |
182 | #define TG3_RX_COPY_THRESHOLD 256 | |
183 | #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS) | |
184 | #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD | |
185 | #else | |
186 | #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh) | |
187 | #endif | |
188 | ||
189 | /* minimum number of free TX descriptors required to wake up TX process */ | |
190 | #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4) | |
191 | ||
192 | #define TG3_RAW_IP_ALIGN 2 | |
193 | ||
194 | #define TG3_FW_UPDATE_TIMEOUT_SEC 5 | |
195 | ||
196 | #define FIRMWARE_TG3 "tigon/tg3.bin" | |
197 | #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin" | |
198 | #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin" | |
199 | ||
200 | static char version[] __devinitdata = | |
201 | DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")"; | |
202 | ||
203 | MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)"); | |
204 | MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver"); | |
205 | MODULE_LICENSE("GPL"); | |
206 | MODULE_VERSION(DRV_MODULE_VERSION); | |
207 | MODULE_FIRMWARE(FIRMWARE_TG3); | |
208 | MODULE_FIRMWARE(FIRMWARE_TG3TSO); | |
209 | MODULE_FIRMWARE(FIRMWARE_TG3TSO5); | |
210 | ||
211 | static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */ | |
212 | module_param(tg3_debug, int, 0); | |
213 | MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value"); | |
214 | ||
215 | static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = { | |
216 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)}, | |
217 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)}, | |
218 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)}, | |
219 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)}, | |
220 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)}, | |
221 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)}, | |
222 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)}, | |
223 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)}, | |
224 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)}, | |
225 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)}, | |
226 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)}, | |
227 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)}, | |
228 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)}, | |
229 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)}, | |
230 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)}, | |
231 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)}, | |
232 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)}, | |
233 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)}, | |
234 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)}, | |
235 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)}, | |
236 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)}, | |
237 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)}, | |
238 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)}, | |
239 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)}, | |
240 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)}, | |
241 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)}, | |
242 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)}, | |
243 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)}, | |
244 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)}, | |
245 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)}, | |
246 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)}, | |
247 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)}, | |
248 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)}, | |
249 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)}, | |
250 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)}, | |
251 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)}, | |
252 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)}, | |
253 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)}, | |
254 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)}, | |
255 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)}, | |
256 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)}, | |
257 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)}, | |
258 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)}, | |
259 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)}, | |
260 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)}, | |
261 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)}, | |
262 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)}, | |
263 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)}, | |
264 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)}, | |
265 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)}, | |
266 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)}, | |
267 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)}, | |
268 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)}, | |
269 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)}, | |
270 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)}, | |
271 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)}, | |
272 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)}, | |
273 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)}, | |
274 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)}, | |
275 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)}, | |
276 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)}, | |
277 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)}, | |
278 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)}, | |
279 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)}, | |
280 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)}, | |
281 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)}, | |
282 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)}, | |
283 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)}, | |
284 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)}, | |
285 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)}, | |
286 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)}, | |
287 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)}, | |
288 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)}, | |
289 | {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)}, | |
290 | {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)}, | |
291 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)}, | |
292 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)}, | |
293 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)}, | |
294 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)}, | |
295 | {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)}, | |
296 | {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */ | |
297 | {} | |
298 | }; | |
299 | ||
300 | MODULE_DEVICE_TABLE(pci, tg3_pci_tbl); | |
301 | ||
302 | static const struct { | |
303 | const char string[ETH_GSTRING_LEN]; | |
304 | } ethtool_stats_keys[] = { | |
305 | { "rx_octets" }, | |
306 | { "rx_fragments" }, | |
307 | { "rx_ucast_packets" }, | |
308 | { "rx_mcast_packets" }, | |
309 | { "rx_bcast_packets" }, | |
310 | { "rx_fcs_errors" }, | |
311 | { "rx_align_errors" }, | |
312 | { "rx_xon_pause_rcvd" }, | |
313 | { "rx_xoff_pause_rcvd" }, | |
314 | { "rx_mac_ctrl_rcvd" }, | |
315 | { "rx_xoff_entered" }, | |
316 | { "rx_frame_too_long_errors" }, | |
317 | { "rx_jabbers" }, | |
318 | { "rx_undersize_packets" }, | |
319 | { "rx_in_length_errors" }, | |
320 | { "rx_out_length_errors" }, | |
321 | { "rx_64_or_less_octet_packets" }, | |
322 | { "rx_65_to_127_octet_packets" }, | |
323 | { "rx_128_to_255_octet_packets" }, | |
324 | { "rx_256_to_511_octet_packets" }, | |
325 | { "rx_512_to_1023_octet_packets" }, | |
326 | { "rx_1024_to_1522_octet_packets" }, | |
327 | { "rx_1523_to_2047_octet_packets" }, | |
328 | { "rx_2048_to_4095_octet_packets" }, | |
329 | { "rx_4096_to_8191_octet_packets" }, | |
330 | { "rx_8192_to_9022_octet_packets" }, | |
331 | ||
332 | { "tx_octets" }, | |
333 | { "tx_collisions" }, | |
334 | ||
335 | { "tx_xon_sent" }, | |
336 | { "tx_xoff_sent" }, | |
337 | { "tx_flow_control" }, | |
338 | { "tx_mac_errors" }, | |
339 | { "tx_single_collisions" }, | |
340 | { "tx_mult_collisions" }, | |
341 | { "tx_deferred" }, | |
342 | { "tx_excessive_collisions" }, | |
343 | { "tx_late_collisions" }, | |
344 | { "tx_collide_2times" }, | |
345 | { "tx_collide_3times" }, | |
346 | { "tx_collide_4times" }, | |
347 | { "tx_collide_5times" }, | |
348 | { "tx_collide_6times" }, | |
349 | { "tx_collide_7times" }, | |
350 | { "tx_collide_8times" }, | |
351 | { "tx_collide_9times" }, | |
352 | { "tx_collide_10times" }, | |
353 | { "tx_collide_11times" }, | |
354 | { "tx_collide_12times" }, | |
355 | { "tx_collide_13times" }, | |
356 | { "tx_collide_14times" }, | |
357 | { "tx_collide_15times" }, | |
358 | { "tx_ucast_packets" }, | |
359 | { "tx_mcast_packets" }, | |
360 | { "tx_bcast_packets" }, | |
361 | { "tx_carrier_sense_errors" }, | |
362 | { "tx_discards" }, | |
363 | { "tx_errors" }, | |
364 | ||
365 | { "dma_writeq_full" }, | |
366 | { "dma_write_prioq_full" }, | |
367 | { "rxbds_empty" }, | |
368 | { "rx_discards" }, | |
369 | { "rx_errors" }, | |
370 | { "rx_threshold_hit" }, | |
371 | ||
372 | { "dma_readq_full" }, | |
373 | { "dma_read_prioq_full" }, | |
374 | { "tx_comp_queue_full" }, | |
375 | ||
376 | { "ring_set_send_prod_index" }, | |
377 | { "ring_status_update" }, | |
378 | { "nic_irqs" }, | |
379 | { "nic_avoided_irqs" }, | |
380 | { "nic_tx_threshold_hit" }, | |
381 | ||
382 | { "mbuf_lwm_thresh_hit" }, | |
383 | }; | |
384 | ||
385 | #define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys) | |
386 | ||
387 | ||
388 | static const struct { | |
389 | const char string[ETH_GSTRING_LEN]; | |
390 | } ethtool_test_keys[] = { | |
391 | { "nvram test (online) " }, | |
392 | { "link test (online) " }, | |
393 | { "register test (offline)" }, | |
394 | { "memory test (offline)" }, | |
395 | { "loopback test (offline)" }, | |
396 | { "interrupt test (offline)" }, | |
397 | }; | |
398 | ||
399 | #define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys) | |
400 | ||
401 | ||
402 | static void tg3_write32(struct tg3 *tp, u32 off, u32 val) | |
403 | { | |
404 | writel(val, tp->regs + off); | |
405 | } | |
406 | ||
407 | static u32 tg3_read32(struct tg3 *tp, u32 off) | |
408 | { | |
409 | return readl(tp->regs + off); | |
410 | } | |
411 | ||
412 | static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val) | |
413 | { | |
414 | writel(val, tp->aperegs + off); | |
415 | } | |
416 | ||
417 | static u32 tg3_ape_read32(struct tg3 *tp, u32 off) | |
418 | { | |
419 | return readl(tp->aperegs + off); | |
420 | } | |
421 | ||
422 | static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val) | |
423 | { | |
424 | unsigned long flags; | |
425 | ||
426 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
427 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); | |
428 | pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); | |
429 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
430 | } | |
431 | ||
432 | static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val) | |
433 | { | |
434 | writel(val, tp->regs + off); | |
435 | readl(tp->regs + off); | |
436 | } | |
437 | ||
438 | static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off) | |
439 | { | |
440 | unsigned long flags; | |
441 | u32 val; | |
442 | ||
443 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
444 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); | |
445 | pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); | |
446 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
447 | return val; | |
448 | } | |
449 | ||
450 | static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val) | |
451 | { | |
452 | unsigned long flags; | |
453 | ||
454 | if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) { | |
455 | pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX + | |
456 | TG3_64BIT_REG_LOW, val); | |
457 | return; | |
458 | } | |
459 | if (off == TG3_RX_STD_PROD_IDX_REG) { | |
460 | pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX + | |
461 | TG3_64BIT_REG_LOW, val); | |
462 | return; | |
463 | } | |
464 | ||
465 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
466 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); | |
467 | pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); | |
468 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
469 | ||
470 | /* In indirect mode when disabling interrupts, we also need | |
471 | * to clear the interrupt bit in the GRC local ctrl register. | |
472 | */ | |
473 | if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) && | |
474 | (val == 0x1)) { | |
475 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL, | |
476 | tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT); | |
477 | } | |
478 | } | |
479 | ||
480 | static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off) | |
481 | { | |
482 | unsigned long flags; | |
483 | u32 val; | |
484 | ||
485 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
486 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); | |
487 | pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); | |
488 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
489 | return val; | |
490 | } | |
491 | ||
492 | /* usec_wait specifies the wait time in usec when writing to certain registers | |
493 | * where it is unsafe to read back the register without some delay. | |
494 | * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power. | |
495 | * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed. | |
496 | */ | |
497 | static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait) | |
498 | { | |
499 | if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND)) | |
500 | /* Non-posted methods */ | |
501 | tp->write32(tp, off, val); | |
502 | else { | |
503 | /* Posted method */ | |
504 | tg3_write32(tp, off, val); | |
505 | if (usec_wait) | |
506 | udelay(usec_wait); | |
507 | tp->read32(tp, off); | |
508 | } | |
509 | /* Wait again after the read for the posted method to guarantee that | |
510 | * the wait time is met. | |
511 | */ | |
512 | if (usec_wait) | |
513 | udelay(usec_wait); | |
514 | } | |
515 | ||
516 | static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val) | |
517 | { | |
518 | tp->write32_mbox(tp, off, val); | |
519 | if (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND)) | |
520 | tp->read32_mbox(tp, off); | |
521 | } | |
522 | ||
523 | static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val) | |
524 | { | |
525 | void __iomem *mbox = tp->regs + off; | |
526 | writel(val, mbox); | |
527 | if (tg3_flag(tp, TXD_MBOX_HWBUG)) | |
528 | writel(val, mbox); | |
529 | if (tg3_flag(tp, MBOX_WRITE_REORDER)) | |
530 | readl(mbox); | |
531 | } | |
532 | ||
533 | static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off) | |
534 | { | |
535 | return readl(tp->regs + off + GRCMBOX_BASE); | |
536 | } | |
537 | ||
538 | static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val) | |
539 | { | |
540 | writel(val, tp->regs + off + GRCMBOX_BASE); | |
541 | } | |
542 | ||
543 | #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val) | |
544 | #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val)) | |
545 | #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val) | |
546 | #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val) | |
547 | #define tr32_mailbox(reg) tp->read32_mbox(tp, reg) | |
548 | ||
549 | #define tw32(reg, val) tp->write32(tp, reg, val) | |
550 | #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0) | |
551 | #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us)) | |
552 | #define tr32(reg) tp->read32(tp, reg) | |
553 | ||
554 | static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val) | |
555 | { | |
556 | unsigned long flags; | |
557 | ||
558 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 && | |
559 | (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) | |
560 | return; | |
561 | ||
562 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
563 | if (tg3_flag(tp, SRAM_USE_CONFIG)) { | |
564 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); | |
565 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); | |
566 | ||
567 | /* Always leave this as zero. */ | |
568 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
569 | } else { | |
570 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off); | |
571 | tw32_f(TG3PCI_MEM_WIN_DATA, val); | |
572 | ||
573 | /* Always leave this as zero. */ | |
574 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
575 | } | |
576 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
577 | } | |
578 | ||
579 | static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val) | |
580 | { | |
581 | unsigned long flags; | |
582 | ||
583 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 && | |
584 | (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) { | |
585 | *val = 0; | |
586 | return; | |
587 | } | |
588 | ||
589 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
590 | if (tg3_flag(tp, SRAM_USE_CONFIG)) { | |
591 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); | |
592 | pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); | |
593 | ||
594 | /* Always leave this as zero. */ | |
595 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
596 | } else { | |
597 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off); | |
598 | *val = tr32(TG3PCI_MEM_WIN_DATA); | |
599 | ||
600 | /* Always leave this as zero. */ | |
601 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
602 | } | |
603 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
604 | } | |
605 | ||
606 | static void tg3_ape_lock_init(struct tg3 *tp) | |
607 | { | |
608 | int i; | |
609 | u32 regbase; | |
610 | ||
611 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) | |
612 | regbase = TG3_APE_LOCK_GRANT; | |
613 | else | |
614 | regbase = TG3_APE_PER_LOCK_GRANT; | |
615 | ||
616 | /* Make sure the driver hasn't any stale locks. */ | |
617 | for (i = 0; i < 8; i++) | |
618 | tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER); | |
619 | } | |
620 | ||
621 | static int tg3_ape_lock(struct tg3 *tp, int locknum) | |
622 | { | |
623 | int i, off; | |
624 | int ret = 0; | |
625 | u32 status, req, gnt; | |
626 | ||
627 | if (!tg3_flag(tp, ENABLE_APE)) | |
628 | return 0; | |
629 | ||
630 | switch (locknum) { | |
631 | case TG3_APE_LOCK_GRC: | |
632 | case TG3_APE_LOCK_MEM: | |
633 | break; | |
634 | default: | |
635 | return -EINVAL; | |
636 | } | |
637 | ||
638 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) { | |
639 | req = TG3_APE_LOCK_REQ; | |
640 | gnt = TG3_APE_LOCK_GRANT; | |
641 | } else { | |
642 | req = TG3_APE_PER_LOCK_REQ; | |
643 | gnt = TG3_APE_PER_LOCK_GRANT; | |
644 | } | |
645 | ||
646 | off = 4 * locknum; | |
647 | ||
648 | tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER); | |
649 | ||
650 | /* Wait for up to 1 millisecond to acquire lock. */ | |
651 | for (i = 0; i < 100; i++) { | |
652 | status = tg3_ape_read32(tp, gnt + off); | |
653 | if (status == APE_LOCK_GRANT_DRIVER) | |
654 | break; | |
655 | udelay(10); | |
656 | } | |
657 | ||
658 | if (status != APE_LOCK_GRANT_DRIVER) { | |
659 | /* Revoke the lock request. */ | |
660 | tg3_ape_write32(tp, gnt + off, | |
661 | APE_LOCK_GRANT_DRIVER); | |
662 | ||
663 | ret = -EBUSY; | |
664 | } | |
665 | ||
666 | return ret; | |
667 | } | |
668 | ||
669 | static void tg3_ape_unlock(struct tg3 *tp, int locknum) | |
670 | { | |
671 | u32 gnt; | |
672 | ||
673 | if (!tg3_flag(tp, ENABLE_APE)) | |
674 | return; | |
675 | ||
676 | switch (locknum) { | |
677 | case TG3_APE_LOCK_GRC: | |
678 | case TG3_APE_LOCK_MEM: | |
679 | break; | |
680 | default: | |
681 | return; | |
682 | } | |
683 | ||
684 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) | |
685 | gnt = TG3_APE_LOCK_GRANT; | |
686 | else | |
687 | gnt = TG3_APE_PER_LOCK_GRANT; | |
688 | ||
689 | tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER); | |
690 | } | |
691 | ||
692 | static void tg3_disable_ints(struct tg3 *tp) | |
693 | { | |
694 | int i; | |
695 | ||
696 | tw32(TG3PCI_MISC_HOST_CTRL, | |
697 | (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT)); | |
698 | for (i = 0; i < tp->irq_max; i++) | |
699 | tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001); | |
700 | } | |
701 | ||
702 | static void tg3_enable_ints(struct tg3 *tp) | |
703 | { | |
704 | int i; | |
705 | ||
706 | tp->irq_sync = 0; | |
707 | wmb(); | |
708 | ||
709 | tw32(TG3PCI_MISC_HOST_CTRL, | |
710 | (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT)); | |
711 | ||
712 | tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE; | |
713 | for (i = 0; i < tp->irq_cnt; i++) { | |
714 | struct tg3_napi *tnapi = &tp->napi[i]; | |
715 | ||
716 | tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); | |
717 | if (tg3_flag(tp, 1SHOT_MSI)) | |
718 | tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); | |
719 | ||
720 | tp->coal_now |= tnapi->coal_now; | |
721 | } | |
722 | ||
723 | /* Force an initial interrupt */ | |
724 | if (!tg3_flag(tp, TAGGED_STATUS) && | |
725 | (tp->napi[0].hw_status->status & SD_STATUS_UPDATED)) | |
726 | tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); | |
727 | else | |
728 | tw32(HOSTCC_MODE, tp->coal_now); | |
729 | ||
730 | tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now); | |
731 | } | |
732 | ||
733 | static inline unsigned int tg3_has_work(struct tg3_napi *tnapi) | |
734 | { | |
735 | struct tg3 *tp = tnapi->tp; | |
736 | struct tg3_hw_status *sblk = tnapi->hw_status; | |
737 | unsigned int work_exists = 0; | |
738 | ||
739 | /* check for phy events */ | |
740 | if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) { | |
741 | if (sblk->status & SD_STATUS_LINK_CHG) | |
742 | work_exists = 1; | |
743 | } | |
744 | /* check for RX/TX work to do */ | |
745 | if (sblk->idx[0].tx_consumer != tnapi->tx_cons || | |
746 | *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr) | |
747 | work_exists = 1; | |
748 | ||
749 | return work_exists; | |
750 | } | |
751 | ||
752 | /* tg3_int_reenable | |
753 | * similar to tg3_enable_ints, but it accurately determines whether there | |
754 | * is new work pending and can return without flushing the PIO write | |
755 | * which reenables interrupts | |
756 | */ | |
757 | static void tg3_int_reenable(struct tg3_napi *tnapi) | |
758 | { | |
759 | struct tg3 *tp = tnapi->tp; | |
760 | ||
761 | tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24); | |
762 | mmiowb(); | |
763 | ||
764 | /* When doing tagged status, this work check is unnecessary. | |
765 | * The last_tag we write above tells the chip which piece of | |
766 | * work we've completed. | |
767 | */ | |
768 | if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi)) | |
769 | tw32(HOSTCC_MODE, tp->coalesce_mode | | |
770 | HOSTCC_MODE_ENABLE | tnapi->coal_now); | |
771 | } | |
772 | ||
773 | static void tg3_switch_clocks(struct tg3 *tp) | |
774 | { | |
775 | u32 clock_ctrl; | |
776 | u32 orig_clock_ctrl; | |
777 | ||
778 | if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS)) | |
779 | return; | |
780 | ||
781 | clock_ctrl = tr32(TG3PCI_CLOCK_CTRL); | |
782 | ||
783 | orig_clock_ctrl = clock_ctrl; | |
784 | clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN | | |
785 | CLOCK_CTRL_CLKRUN_OENABLE | | |
786 | 0x1f); | |
787 | tp->pci_clock_ctrl = clock_ctrl; | |
788 | ||
789 | if (tg3_flag(tp, 5705_PLUS)) { | |
790 | if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) { | |
791 | tw32_wait_f(TG3PCI_CLOCK_CTRL, | |
792 | clock_ctrl | CLOCK_CTRL_625_CORE, 40); | |
793 | } | |
794 | } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) { | |
795 | tw32_wait_f(TG3PCI_CLOCK_CTRL, | |
796 | clock_ctrl | | |
797 | (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK), | |
798 | 40); | |
799 | tw32_wait_f(TG3PCI_CLOCK_CTRL, | |
800 | clock_ctrl | (CLOCK_CTRL_ALTCLK), | |
801 | 40); | |
802 | } | |
803 | tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40); | |
804 | } | |
805 | ||
806 | #define PHY_BUSY_LOOPS 5000 | |
807 | ||
808 | static int tg3_readphy(struct tg3 *tp, int reg, u32 *val) | |
809 | { | |
810 | u32 frame_val; | |
811 | unsigned int loops; | |
812 | int ret; | |
813 | ||
814 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | |
815 | tw32_f(MAC_MI_MODE, | |
816 | (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); | |
817 | udelay(80); | |
818 | } | |
819 | ||
820 | *val = 0x0; | |
821 | ||
822 | frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) & | |
823 | MI_COM_PHY_ADDR_MASK); | |
824 | frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) & | |
825 | MI_COM_REG_ADDR_MASK); | |
826 | frame_val |= (MI_COM_CMD_READ | MI_COM_START); | |
827 | ||
828 | tw32_f(MAC_MI_COM, frame_val); | |
829 | ||
830 | loops = PHY_BUSY_LOOPS; | |
831 | while (loops != 0) { | |
832 | udelay(10); | |
833 | frame_val = tr32(MAC_MI_COM); | |
834 | ||
835 | if ((frame_val & MI_COM_BUSY) == 0) { | |
836 | udelay(5); | |
837 | frame_val = tr32(MAC_MI_COM); | |
838 | break; | |
839 | } | |
840 | loops -= 1; | |
841 | } | |
842 | ||
843 | ret = -EBUSY; | |
844 | if (loops != 0) { | |
845 | *val = frame_val & MI_COM_DATA_MASK; | |
846 | ret = 0; | |
847 | } | |
848 | ||
849 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | |
850 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
851 | udelay(80); | |
852 | } | |
853 | ||
854 | return ret; | |
855 | } | |
856 | ||
857 | static int tg3_writephy(struct tg3 *tp, int reg, u32 val) | |
858 | { | |
859 | u32 frame_val; | |
860 | unsigned int loops; | |
861 | int ret; | |
862 | ||
863 | if ((tp->phy_flags & TG3_PHYFLG_IS_FET) && | |
864 | (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL)) | |
865 | return 0; | |
866 | ||
867 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | |
868 | tw32_f(MAC_MI_MODE, | |
869 | (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); | |
870 | udelay(80); | |
871 | } | |
872 | ||
873 | frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) & | |
874 | MI_COM_PHY_ADDR_MASK); | |
875 | frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) & | |
876 | MI_COM_REG_ADDR_MASK); | |
877 | frame_val |= (val & MI_COM_DATA_MASK); | |
878 | frame_val |= (MI_COM_CMD_WRITE | MI_COM_START); | |
879 | ||
880 | tw32_f(MAC_MI_COM, frame_val); | |
881 | ||
882 | loops = PHY_BUSY_LOOPS; | |
883 | while (loops != 0) { | |
884 | udelay(10); | |
885 | frame_val = tr32(MAC_MI_COM); | |
886 | if ((frame_val & MI_COM_BUSY) == 0) { | |
887 | udelay(5); | |
888 | frame_val = tr32(MAC_MI_COM); | |
889 | break; | |
890 | } | |
891 | loops -= 1; | |
892 | } | |
893 | ||
894 | ret = -EBUSY; | |
895 | if (loops != 0) | |
896 | ret = 0; | |
897 | ||
898 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | |
899 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
900 | udelay(80); | |
901 | } | |
902 | ||
903 | return ret; | |
904 | } | |
905 | ||
906 | static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val) | |
907 | { | |
908 | int err; | |
909 | ||
910 | err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad); | |
911 | if (err) | |
912 | goto done; | |
913 | ||
914 | err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr); | |
915 | if (err) | |
916 | goto done; | |
917 | ||
918 | err = tg3_writephy(tp, MII_TG3_MMD_CTRL, | |
919 | MII_TG3_MMD_CTRL_DATA_NOINC | devad); | |
920 | if (err) | |
921 | goto done; | |
922 | ||
923 | err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val); | |
924 | ||
925 | done: | |
926 | return err; | |
927 | } | |
928 | ||
929 | static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val) | |
930 | { | |
931 | int err; | |
932 | ||
933 | err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad); | |
934 | if (err) | |
935 | goto done; | |
936 | ||
937 | err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr); | |
938 | if (err) | |
939 | goto done; | |
940 | ||
941 | err = tg3_writephy(tp, MII_TG3_MMD_CTRL, | |
942 | MII_TG3_MMD_CTRL_DATA_NOINC | devad); | |
943 | if (err) | |
944 | goto done; | |
945 | ||
946 | err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val); | |
947 | ||
948 | done: | |
949 | return err; | |
950 | } | |
951 | ||
952 | static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val) | |
953 | { | |
954 | int err; | |
955 | ||
956 | err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg); | |
957 | if (!err) | |
958 | err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val); | |
959 | ||
960 | return err; | |
961 | } | |
962 | ||
963 | static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val) | |
964 | { | |
965 | int err; | |
966 | ||
967 | err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg); | |
968 | if (!err) | |
969 | err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val); | |
970 | ||
971 | return err; | |
972 | } | |
973 | ||
974 | static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val) | |
975 | { | |
976 | int err; | |
977 | ||
978 | err = tg3_writephy(tp, MII_TG3_AUX_CTRL, | |
979 | (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) | | |
980 | MII_TG3_AUXCTL_SHDWSEL_MISC); | |
981 | if (!err) | |
982 | err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val); | |
983 | ||
984 | return err; | |
985 | } | |
986 | ||
987 | static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set) | |
988 | { | |
989 | if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC) | |
990 | set |= MII_TG3_AUXCTL_MISC_WREN; | |
991 | ||
992 | return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg); | |
993 | } | |
994 | ||
995 | #define TG3_PHY_AUXCTL_SMDSP_ENABLE(tp) \ | |
996 | tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \ | |
997 | MII_TG3_AUXCTL_ACTL_SMDSP_ENA | \ | |
998 | MII_TG3_AUXCTL_ACTL_TX_6DB) | |
999 | ||
1000 | #define TG3_PHY_AUXCTL_SMDSP_DISABLE(tp) \ | |
1001 | tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \ | |
1002 | MII_TG3_AUXCTL_ACTL_TX_6DB); | |
1003 | ||
1004 | static int tg3_bmcr_reset(struct tg3 *tp) | |
1005 | { | |
1006 | u32 phy_control; | |
1007 | int limit, err; | |
1008 | ||
1009 | /* OK, reset it, and poll the BMCR_RESET bit until it | |
1010 | * clears or we time out. | |
1011 | */ | |
1012 | phy_control = BMCR_RESET; | |
1013 | err = tg3_writephy(tp, MII_BMCR, phy_control); | |
1014 | if (err != 0) | |
1015 | return -EBUSY; | |
1016 | ||
1017 | limit = 5000; | |
1018 | while (limit--) { | |
1019 | err = tg3_readphy(tp, MII_BMCR, &phy_control); | |
1020 | if (err != 0) | |
1021 | return -EBUSY; | |
1022 | ||
1023 | if ((phy_control & BMCR_RESET) == 0) { | |
1024 | udelay(40); | |
1025 | break; | |
1026 | } | |
1027 | udelay(10); | |
1028 | } | |
1029 | if (limit < 0) | |
1030 | return -EBUSY; | |
1031 | ||
1032 | return 0; | |
1033 | } | |
1034 | ||
1035 | static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg) | |
1036 | { | |
1037 | struct tg3 *tp = bp->priv; | |
1038 | u32 val; | |
1039 | ||
1040 | spin_lock_bh(&tp->lock); | |
1041 | ||
1042 | if (tg3_readphy(tp, reg, &val)) | |
1043 | val = -EIO; | |
1044 | ||
1045 | spin_unlock_bh(&tp->lock); | |
1046 | ||
1047 | return val; | |
1048 | } | |
1049 | ||
1050 | static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val) | |
1051 | { | |
1052 | struct tg3 *tp = bp->priv; | |
1053 | u32 ret = 0; | |
1054 | ||
1055 | spin_lock_bh(&tp->lock); | |
1056 | ||
1057 | if (tg3_writephy(tp, reg, val)) | |
1058 | ret = -EIO; | |
1059 | ||
1060 | spin_unlock_bh(&tp->lock); | |
1061 | ||
1062 | return ret; | |
1063 | } | |
1064 | ||
1065 | static int tg3_mdio_reset(struct mii_bus *bp) | |
1066 | { | |
1067 | return 0; | |
1068 | } | |
1069 | ||
1070 | static void tg3_mdio_config_5785(struct tg3 *tp) | |
1071 | { | |
1072 | u32 val; | |
1073 | struct phy_device *phydev; | |
1074 | ||
1075 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; | |
1076 | switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) { | |
1077 | case PHY_ID_BCM50610: | |
1078 | case PHY_ID_BCM50610M: | |
1079 | val = MAC_PHYCFG2_50610_LED_MODES; | |
1080 | break; | |
1081 | case PHY_ID_BCMAC131: | |
1082 | val = MAC_PHYCFG2_AC131_LED_MODES; | |
1083 | break; | |
1084 | case PHY_ID_RTL8211C: | |
1085 | val = MAC_PHYCFG2_RTL8211C_LED_MODES; | |
1086 | break; | |
1087 | case PHY_ID_RTL8201E: | |
1088 | val = MAC_PHYCFG2_RTL8201E_LED_MODES; | |
1089 | break; | |
1090 | default: | |
1091 | return; | |
1092 | } | |
1093 | ||
1094 | if (phydev->interface != PHY_INTERFACE_MODE_RGMII) { | |
1095 | tw32(MAC_PHYCFG2, val); | |
1096 | ||
1097 | val = tr32(MAC_PHYCFG1); | |
1098 | val &= ~(MAC_PHYCFG1_RGMII_INT | | |
1099 | MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK); | |
1100 | val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT; | |
1101 | tw32(MAC_PHYCFG1, val); | |
1102 | ||
1103 | return; | |
1104 | } | |
1105 | ||
1106 | if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) | |
1107 | val |= MAC_PHYCFG2_EMODE_MASK_MASK | | |
1108 | MAC_PHYCFG2_FMODE_MASK_MASK | | |
1109 | MAC_PHYCFG2_GMODE_MASK_MASK | | |
1110 | MAC_PHYCFG2_ACT_MASK_MASK | | |
1111 | MAC_PHYCFG2_QUAL_MASK_MASK | | |
1112 | MAC_PHYCFG2_INBAND_ENABLE; | |
1113 | ||
1114 | tw32(MAC_PHYCFG2, val); | |
1115 | ||
1116 | val = tr32(MAC_PHYCFG1); | |
1117 | val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK | | |
1118 | MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN); | |
1119 | if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) { | |
1120 | if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN)) | |
1121 | val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC; | |
1122 | if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN)) | |
1123 | val |= MAC_PHYCFG1_RGMII_SND_STAT_EN; | |
1124 | } | |
1125 | val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT | | |
1126 | MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV; | |
1127 | tw32(MAC_PHYCFG1, val); | |
1128 | ||
1129 | val = tr32(MAC_EXT_RGMII_MODE); | |
1130 | val &= ~(MAC_RGMII_MODE_RX_INT_B | | |
1131 | MAC_RGMII_MODE_RX_QUALITY | | |
1132 | MAC_RGMII_MODE_RX_ACTIVITY | | |
1133 | MAC_RGMII_MODE_RX_ENG_DET | | |
1134 | MAC_RGMII_MODE_TX_ENABLE | | |
1135 | MAC_RGMII_MODE_TX_LOWPWR | | |
1136 | MAC_RGMII_MODE_TX_RESET); | |
1137 | if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) { | |
1138 | if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN)) | |
1139 | val |= MAC_RGMII_MODE_RX_INT_B | | |
1140 | MAC_RGMII_MODE_RX_QUALITY | | |
1141 | MAC_RGMII_MODE_RX_ACTIVITY | | |
1142 | MAC_RGMII_MODE_RX_ENG_DET; | |
1143 | if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN)) | |
1144 | val |= MAC_RGMII_MODE_TX_ENABLE | | |
1145 | MAC_RGMII_MODE_TX_LOWPWR | | |
1146 | MAC_RGMII_MODE_TX_RESET; | |
1147 | } | |
1148 | tw32(MAC_EXT_RGMII_MODE, val); | |
1149 | } | |
1150 | ||
1151 | static void tg3_mdio_start(struct tg3 *tp) | |
1152 | { | |
1153 | tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL; | |
1154 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
1155 | udelay(80); | |
1156 | ||
1157 | if (tg3_flag(tp, MDIOBUS_INITED) && | |
1158 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | |
1159 | tg3_mdio_config_5785(tp); | |
1160 | } | |
1161 | ||
1162 | static int tg3_mdio_init(struct tg3 *tp) | |
1163 | { | |
1164 | int i; | |
1165 | u32 reg; | |
1166 | struct phy_device *phydev; | |
1167 | ||
1168 | if (tg3_flag(tp, 5717_PLUS)) { | |
1169 | u32 is_serdes; | |
1170 | ||
1171 | tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1; | |
1172 | ||
1173 | if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) | |
1174 | is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES; | |
1175 | else | |
1176 | is_serdes = tr32(TG3_CPMU_PHY_STRAP) & | |
1177 | TG3_CPMU_PHY_STRAP_IS_SERDES; | |
1178 | if (is_serdes) | |
1179 | tp->phy_addr += 7; | |
1180 | } else | |
1181 | tp->phy_addr = TG3_PHY_MII_ADDR; | |
1182 | ||
1183 | tg3_mdio_start(tp); | |
1184 | ||
1185 | if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED)) | |
1186 | return 0; | |
1187 | ||
1188 | tp->mdio_bus = mdiobus_alloc(); | |
1189 | if (tp->mdio_bus == NULL) | |
1190 | return -ENOMEM; | |
1191 | ||
1192 | tp->mdio_bus->name = "tg3 mdio bus"; | |
1193 | snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x", | |
1194 | (tp->pdev->bus->number << 8) | tp->pdev->devfn); | |
1195 | tp->mdio_bus->priv = tp; | |
1196 | tp->mdio_bus->parent = &tp->pdev->dev; | |
1197 | tp->mdio_bus->read = &tg3_mdio_read; | |
1198 | tp->mdio_bus->write = &tg3_mdio_write; | |
1199 | tp->mdio_bus->reset = &tg3_mdio_reset; | |
1200 | tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR); | |
1201 | tp->mdio_bus->irq = &tp->mdio_irq[0]; | |
1202 | ||
1203 | for (i = 0; i < PHY_MAX_ADDR; i++) | |
1204 | tp->mdio_bus->irq[i] = PHY_POLL; | |
1205 | ||
1206 | /* The bus registration will look for all the PHYs on the mdio bus. | |
1207 | * Unfortunately, it does not ensure the PHY is powered up before | |
1208 | * accessing the PHY ID registers. A chip reset is the | |
1209 | * quickest way to bring the device back to an operational state.. | |
1210 | */ | |
1211 | if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN)) | |
1212 | tg3_bmcr_reset(tp); | |
1213 | ||
1214 | i = mdiobus_register(tp->mdio_bus); | |
1215 | if (i) { | |
1216 | dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i); | |
1217 | mdiobus_free(tp->mdio_bus); | |
1218 | return i; | |
1219 | } | |
1220 | ||
1221 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; | |
1222 | ||
1223 | if (!phydev || !phydev->drv) { | |
1224 | dev_warn(&tp->pdev->dev, "No PHY devices\n"); | |
1225 | mdiobus_unregister(tp->mdio_bus); | |
1226 | mdiobus_free(tp->mdio_bus); | |
1227 | return -ENODEV; | |
1228 | } | |
1229 | ||
1230 | switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) { | |
1231 | case PHY_ID_BCM57780: | |
1232 | phydev->interface = PHY_INTERFACE_MODE_GMII; | |
1233 | phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE; | |
1234 | break; | |
1235 | case PHY_ID_BCM50610: | |
1236 | case PHY_ID_BCM50610M: | |
1237 | phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE | | |
1238 | PHY_BRCM_RX_REFCLK_UNUSED | | |
1239 | PHY_BRCM_DIS_TXCRXC_NOENRGY | | |
1240 | PHY_BRCM_AUTO_PWRDWN_ENABLE; | |
1241 | if (tg3_flag(tp, RGMII_INBAND_DISABLE)) | |
1242 | phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE; | |
1243 | if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN)) | |
1244 | phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE; | |
1245 | if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN)) | |
1246 | phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE; | |
1247 | /* fallthru */ | |
1248 | case PHY_ID_RTL8211C: | |
1249 | phydev->interface = PHY_INTERFACE_MODE_RGMII; | |
1250 | break; | |
1251 | case PHY_ID_RTL8201E: | |
1252 | case PHY_ID_BCMAC131: | |
1253 | phydev->interface = PHY_INTERFACE_MODE_MII; | |
1254 | phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE; | |
1255 | tp->phy_flags |= TG3_PHYFLG_IS_FET; | |
1256 | break; | |
1257 | } | |
1258 | ||
1259 | tg3_flag_set(tp, MDIOBUS_INITED); | |
1260 | ||
1261 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | |
1262 | tg3_mdio_config_5785(tp); | |
1263 | ||
1264 | return 0; | |
1265 | } | |
1266 | ||
1267 | static void tg3_mdio_fini(struct tg3 *tp) | |
1268 | { | |
1269 | if (tg3_flag(tp, MDIOBUS_INITED)) { | |
1270 | tg3_flag_clear(tp, MDIOBUS_INITED); | |
1271 | mdiobus_unregister(tp->mdio_bus); | |
1272 | mdiobus_free(tp->mdio_bus); | |
1273 | } | |
1274 | } | |
1275 | ||
1276 | /* tp->lock is held. */ | |
1277 | static inline void tg3_generate_fw_event(struct tg3 *tp) | |
1278 | { | |
1279 | u32 val; | |
1280 | ||
1281 | val = tr32(GRC_RX_CPU_EVENT); | |
1282 | val |= GRC_RX_CPU_DRIVER_EVENT; | |
1283 | tw32_f(GRC_RX_CPU_EVENT, val); | |
1284 | ||
1285 | tp->last_event_jiffies = jiffies; | |
1286 | } | |
1287 | ||
1288 | #define TG3_FW_EVENT_TIMEOUT_USEC 2500 | |
1289 | ||
1290 | /* tp->lock is held. */ | |
1291 | static void tg3_wait_for_event_ack(struct tg3 *tp) | |
1292 | { | |
1293 | int i; | |
1294 | unsigned int delay_cnt; | |
1295 | long time_remain; | |
1296 | ||
1297 | /* If enough time has passed, no wait is necessary. */ | |
1298 | time_remain = (long)(tp->last_event_jiffies + 1 + | |
1299 | usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) - | |
1300 | (long)jiffies; | |
1301 | if (time_remain < 0) | |
1302 | return; | |
1303 | ||
1304 | /* Check if we can shorten the wait time. */ | |
1305 | delay_cnt = jiffies_to_usecs(time_remain); | |
1306 | if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC) | |
1307 | delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC; | |
1308 | delay_cnt = (delay_cnt >> 3) + 1; | |
1309 | ||
1310 | for (i = 0; i < delay_cnt; i++) { | |
1311 | if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT)) | |
1312 | break; | |
1313 | udelay(8); | |
1314 | } | |
1315 | } | |
1316 | ||
1317 | /* tp->lock is held. */ | |
1318 | static void tg3_ump_link_report(struct tg3 *tp) | |
1319 | { | |
1320 | u32 reg; | |
1321 | u32 val; | |
1322 | ||
1323 | if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF)) | |
1324 | return; | |
1325 | ||
1326 | tg3_wait_for_event_ack(tp); | |
1327 | ||
1328 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE); | |
1329 | ||
1330 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14); | |
1331 | ||
1332 | val = 0; | |
1333 | if (!tg3_readphy(tp, MII_BMCR, ®)) | |
1334 | val = reg << 16; | |
1335 | if (!tg3_readphy(tp, MII_BMSR, ®)) | |
1336 | val |= (reg & 0xffff); | |
1337 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val); | |
1338 | ||
1339 | val = 0; | |
1340 | if (!tg3_readphy(tp, MII_ADVERTISE, ®)) | |
1341 | val = reg << 16; | |
1342 | if (!tg3_readphy(tp, MII_LPA, ®)) | |
1343 | val |= (reg & 0xffff); | |
1344 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val); | |
1345 | ||
1346 | val = 0; | |
1347 | if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) { | |
1348 | if (!tg3_readphy(tp, MII_CTRL1000, ®)) | |
1349 | val = reg << 16; | |
1350 | if (!tg3_readphy(tp, MII_STAT1000, ®)) | |
1351 | val |= (reg & 0xffff); | |
1352 | } | |
1353 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val); | |
1354 | ||
1355 | if (!tg3_readphy(tp, MII_PHYADDR, ®)) | |
1356 | val = reg << 16; | |
1357 | else | |
1358 | val = 0; | |
1359 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val); | |
1360 | ||
1361 | tg3_generate_fw_event(tp); | |
1362 | } | |
1363 | ||
1364 | static void tg3_link_report(struct tg3 *tp) | |
1365 | { | |
1366 | if (!netif_carrier_ok(tp->dev)) { | |
1367 | netif_info(tp, link, tp->dev, "Link is down\n"); | |
1368 | tg3_ump_link_report(tp); | |
1369 | } else if (netif_msg_link(tp)) { | |
1370 | netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n", | |
1371 | (tp->link_config.active_speed == SPEED_1000 ? | |
1372 | 1000 : | |
1373 | (tp->link_config.active_speed == SPEED_100 ? | |
1374 | 100 : 10)), | |
1375 | (tp->link_config.active_duplex == DUPLEX_FULL ? | |
1376 | "full" : "half")); | |
1377 | ||
1378 | netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n", | |
1379 | (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ? | |
1380 | "on" : "off", | |
1381 | (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ? | |
1382 | "on" : "off"); | |
1383 | ||
1384 | if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) | |
1385 | netdev_info(tp->dev, "EEE is %s\n", | |
1386 | tp->setlpicnt ? "enabled" : "disabled"); | |
1387 | ||
1388 | tg3_ump_link_report(tp); | |
1389 | } | |
1390 | } | |
1391 | ||
1392 | static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl) | |
1393 | { | |
1394 | u16 miireg; | |
1395 | ||
1396 | if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX)) | |
1397 | miireg = ADVERTISE_PAUSE_CAP; | |
1398 | else if (flow_ctrl & FLOW_CTRL_TX) | |
1399 | miireg = ADVERTISE_PAUSE_ASYM; | |
1400 | else if (flow_ctrl & FLOW_CTRL_RX) | |
1401 | miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; | |
1402 | else | |
1403 | miireg = 0; | |
1404 | ||
1405 | return miireg; | |
1406 | } | |
1407 | ||
1408 | static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl) | |
1409 | { | |
1410 | u16 miireg; | |
1411 | ||
1412 | if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX)) | |
1413 | miireg = ADVERTISE_1000XPAUSE; | |
1414 | else if (flow_ctrl & FLOW_CTRL_TX) | |
1415 | miireg = ADVERTISE_1000XPSE_ASYM; | |
1416 | else if (flow_ctrl & FLOW_CTRL_RX) | |
1417 | miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM; | |
1418 | else | |
1419 | miireg = 0; | |
1420 | ||
1421 | return miireg; | |
1422 | } | |
1423 | ||
1424 | static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv) | |
1425 | { | |
1426 | u8 cap = 0; | |
1427 | ||
1428 | if (lcladv & ADVERTISE_1000XPAUSE) { | |
1429 | if (lcladv & ADVERTISE_1000XPSE_ASYM) { | |
1430 | if (rmtadv & LPA_1000XPAUSE) | |
1431 | cap = FLOW_CTRL_TX | FLOW_CTRL_RX; | |
1432 | else if (rmtadv & LPA_1000XPAUSE_ASYM) | |
1433 | cap = FLOW_CTRL_RX; | |
1434 | } else { | |
1435 | if (rmtadv & LPA_1000XPAUSE) | |
1436 | cap = FLOW_CTRL_TX | FLOW_CTRL_RX; | |
1437 | } | |
1438 | } else if (lcladv & ADVERTISE_1000XPSE_ASYM) { | |
1439 | if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM)) | |
1440 | cap = FLOW_CTRL_TX; | |
1441 | } | |
1442 | ||
1443 | return cap; | |
1444 | } | |
1445 | ||
1446 | static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv) | |
1447 | { | |
1448 | u8 autoneg; | |
1449 | u8 flowctrl = 0; | |
1450 | u32 old_rx_mode = tp->rx_mode; | |
1451 | u32 old_tx_mode = tp->tx_mode; | |
1452 | ||
1453 | if (tg3_flag(tp, USE_PHYLIB)) | |
1454 | autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg; | |
1455 | else | |
1456 | autoneg = tp->link_config.autoneg; | |
1457 | ||
1458 | if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) { | |
1459 | if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) | |
1460 | flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv); | |
1461 | else | |
1462 | flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv); | |
1463 | } else | |
1464 | flowctrl = tp->link_config.flowctrl; | |
1465 | ||
1466 | tp->link_config.active_flowctrl = flowctrl; | |
1467 | ||
1468 | if (flowctrl & FLOW_CTRL_RX) | |
1469 | tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE; | |
1470 | else | |
1471 | tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE; | |
1472 | ||
1473 | if (old_rx_mode != tp->rx_mode) | |
1474 | tw32_f(MAC_RX_MODE, tp->rx_mode); | |
1475 | ||
1476 | if (flowctrl & FLOW_CTRL_TX) | |
1477 | tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE; | |
1478 | else | |
1479 | tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE; | |
1480 | ||
1481 | if (old_tx_mode != tp->tx_mode) | |
1482 | tw32_f(MAC_TX_MODE, tp->tx_mode); | |
1483 | } | |
1484 | ||
1485 | static void tg3_adjust_link(struct net_device *dev) | |
1486 | { | |
1487 | u8 oldflowctrl, linkmesg = 0; | |
1488 | u32 mac_mode, lcl_adv, rmt_adv; | |
1489 | struct tg3 *tp = netdev_priv(dev); | |
1490 | struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; | |
1491 | ||
1492 | spin_lock_bh(&tp->lock); | |
1493 | ||
1494 | mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK | | |
1495 | MAC_MODE_HALF_DUPLEX); | |
1496 | ||
1497 | oldflowctrl = tp->link_config.active_flowctrl; | |
1498 | ||
1499 | if (phydev->link) { | |
1500 | lcl_adv = 0; | |
1501 | rmt_adv = 0; | |
1502 | ||
1503 | if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10) | |
1504 | mac_mode |= MAC_MODE_PORT_MODE_MII; | |
1505 | else if (phydev->speed == SPEED_1000 || | |
1506 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) | |
1507 | mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
1508 | else | |
1509 | mac_mode |= MAC_MODE_PORT_MODE_MII; | |
1510 | ||
1511 | if (phydev->duplex == DUPLEX_HALF) | |
1512 | mac_mode |= MAC_MODE_HALF_DUPLEX; | |
1513 | else { | |
1514 | lcl_adv = tg3_advert_flowctrl_1000T( | |
1515 | tp->link_config.flowctrl); | |
1516 | ||
1517 | if (phydev->pause) | |
1518 | rmt_adv = LPA_PAUSE_CAP; | |
1519 | if (phydev->asym_pause) | |
1520 | rmt_adv |= LPA_PAUSE_ASYM; | |
1521 | } | |
1522 | ||
1523 | tg3_setup_flow_control(tp, lcl_adv, rmt_adv); | |
1524 | } else | |
1525 | mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
1526 | ||
1527 | if (mac_mode != tp->mac_mode) { | |
1528 | tp->mac_mode = mac_mode; | |
1529 | tw32_f(MAC_MODE, tp->mac_mode); | |
1530 | udelay(40); | |
1531 | } | |
1532 | ||
1533 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) { | |
1534 | if (phydev->speed == SPEED_10) | |
1535 | tw32(MAC_MI_STAT, | |
1536 | MAC_MI_STAT_10MBPS_MODE | | |
1537 | MAC_MI_STAT_LNKSTAT_ATTN_ENAB); | |
1538 | else | |
1539 | tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB); | |
1540 | } | |
1541 | ||
1542 | if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF) | |
1543 | tw32(MAC_TX_LENGTHS, | |
1544 | ((2 << TX_LENGTHS_IPG_CRS_SHIFT) | | |
1545 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
1546 | (0xff << TX_LENGTHS_SLOT_TIME_SHIFT))); | |
1547 | else | |
1548 | tw32(MAC_TX_LENGTHS, | |
1549 | ((2 << TX_LENGTHS_IPG_CRS_SHIFT) | | |
1550 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
1551 | (32 << TX_LENGTHS_SLOT_TIME_SHIFT))); | |
1552 | ||
1553 | if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) || | |
1554 | (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) || | |
1555 | phydev->speed != tp->link_config.active_speed || | |
1556 | phydev->duplex != tp->link_config.active_duplex || | |
1557 | oldflowctrl != tp->link_config.active_flowctrl) | |
1558 | linkmesg = 1; | |
1559 | ||
1560 | tp->link_config.active_speed = phydev->speed; | |
1561 | tp->link_config.active_duplex = phydev->duplex; | |
1562 | ||
1563 | spin_unlock_bh(&tp->lock); | |
1564 | ||
1565 | if (linkmesg) | |
1566 | tg3_link_report(tp); | |
1567 | } | |
1568 | ||
1569 | static int tg3_phy_init(struct tg3 *tp) | |
1570 | { | |
1571 | struct phy_device *phydev; | |
1572 | ||
1573 | if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) | |
1574 | return 0; | |
1575 | ||
1576 | /* Bring the PHY back to a known state. */ | |
1577 | tg3_bmcr_reset(tp); | |
1578 | ||
1579 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; | |
1580 | ||
1581 | /* Attach the MAC to the PHY. */ | |
1582 | phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link, | |
1583 | phydev->dev_flags, phydev->interface); | |
1584 | if (IS_ERR(phydev)) { | |
1585 | dev_err(&tp->pdev->dev, "Could not attach to PHY\n"); | |
1586 | return PTR_ERR(phydev); | |
1587 | } | |
1588 | ||
1589 | /* Mask with MAC supported features. */ | |
1590 | switch (phydev->interface) { | |
1591 | case PHY_INTERFACE_MODE_GMII: | |
1592 | case PHY_INTERFACE_MODE_RGMII: | |
1593 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { | |
1594 | phydev->supported &= (PHY_GBIT_FEATURES | | |
1595 | SUPPORTED_Pause | | |
1596 | SUPPORTED_Asym_Pause); | |
1597 | break; | |
1598 | } | |
1599 | /* fallthru */ | |
1600 | case PHY_INTERFACE_MODE_MII: | |
1601 | phydev->supported &= (PHY_BASIC_FEATURES | | |
1602 | SUPPORTED_Pause | | |
1603 | SUPPORTED_Asym_Pause); | |
1604 | break; | |
1605 | default: | |
1606 | phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); | |
1607 | return -EINVAL; | |
1608 | } | |
1609 | ||
1610 | tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED; | |
1611 | ||
1612 | phydev->advertising = phydev->supported; | |
1613 | ||
1614 | return 0; | |
1615 | } | |
1616 | ||
1617 | static void tg3_phy_start(struct tg3 *tp) | |
1618 | { | |
1619 | struct phy_device *phydev; | |
1620 | ||
1621 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) | |
1622 | return; | |
1623 | ||
1624 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; | |
1625 | ||
1626 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { | |
1627 | tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER; | |
1628 | phydev->speed = tp->link_config.orig_speed; | |
1629 | phydev->duplex = tp->link_config.orig_duplex; | |
1630 | phydev->autoneg = tp->link_config.orig_autoneg; | |
1631 | phydev->advertising = tp->link_config.orig_advertising; | |
1632 | } | |
1633 | ||
1634 | phy_start(phydev); | |
1635 | ||
1636 | phy_start_aneg(phydev); | |
1637 | } | |
1638 | ||
1639 | static void tg3_phy_stop(struct tg3 *tp) | |
1640 | { | |
1641 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) | |
1642 | return; | |
1643 | ||
1644 | phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); | |
1645 | } | |
1646 | ||
1647 | static void tg3_phy_fini(struct tg3 *tp) | |
1648 | { | |
1649 | if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { | |
1650 | phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); | |
1651 | tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED; | |
1652 | } | |
1653 | } | |
1654 | ||
1655 | static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable) | |
1656 | { | |
1657 | u32 phytest; | |
1658 | ||
1659 | if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) { | |
1660 | u32 phy; | |
1661 | ||
1662 | tg3_writephy(tp, MII_TG3_FET_TEST, | |
1663 | phytest | MII_TG3_FET_SHADOW_EN); | |
1664 | if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) { | |
1665 | if (enable) | |
1666 | phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD; | |
1667 | else | |
1668 | phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD; | |
1669 | tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy); | |
1670 | } | |
1671 | tg3_writephy(tp, MII_TG3_FET_TEST, phytest); | |
1672 | } | |
1673 | } | |
1674 | ||
1675 | static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable) | |
1676 | { | |
1677 | u32 reg; | |
1678 | ||
1679 | if (!tg3_flag(tp, 5705_PLUS) || | |
1680 | (tg3_flag(tp, 5717_PLUS) && | |
1681 | (tp->phy_flags & TG3_PHYFLG_MII_SERDES))) | |
1682 | return; | |
1683 | ||
1684 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { | |
1685 | tg3_phy_fet_toggle_apd(tp, enable); | |
1686 | return; | |
1687 | } | |
1688 | ||
1689 | reg = MII_TG3_MISC_SHDW_WREN | | |
1690 | MII_TG3_MISC_SHDW_SCR5_SEL | | |
1691 | MII_TG3_MISC_SHDW_SCR5_LPED | | |
1692 | MII_TG3_MISC_SHDW_SCR5_DLPTLM | | |
1693 | MII_TG3_MISC_SHDW_SCR5_SDTL | | |
1694 | MII_TG3_MISC_SHDW_SCR5_C125OE; | |
1695 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable) | |
1696 | reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD; | |
1697 | ||
1698 | tg3_writephy(tp, MII_TG3_MISC_SHDW, reg); | |
1699 | ||
1700 | ||
1701 | reg = MII_TG3_MISC_SHDW_WREN | | |
1702 | MII_TG3_MISC_SHDW_APD_SEL | | |
1703 | MII_TG3_MISC_SHDW_APD_WKTM_84MS; | |
1704 | if (enable) | |
1705 | reg |= MII_TG3_MISC_SHDW_APD_ENABLE; | |
1706 | ||
1707 | tg3_writephy(tp, MII_TG3_MISC_SHDW, reg); | |
1708 | } | |
1709 | ||
1710 | static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable) | |
1711 | { | |
1712 | u32 phy; | |
1713 | ||
1714 | if (!tg3_flag(tp, 5705_PLUS) || | |
1715 | (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) | |
1716 | return; | |
1717 | ||
1718 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { | |
1719 | u32 ephy; | |
1720 | ||
1721 | if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) { | |
1722 | u32 reg = MII_TG3_FET_SHDW_MISCCTRL; | |
1723 | ||
1724 | tg3_writephy(tp, MII_TG3_FET_TEST, | |
1725 | ephy | MII_TG3_FET_SHADOW_EN); | |
1726 | if (!tg3_readphy(tp, reg, &phy)) { | |
1727 | if (enable) | |
1728 | phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX; | |
1729 | else | |
1730 | phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX; | |
1731 | tg3_writephy(tp, reg, phy); | |
1732 | } | |
1733 | tg3_writephy(tp, MII_TG3_FET_TEST, ephy); | |
1734 | } | |
1735 | } else { | |
1736 | int ret; | |
1737 | ||
1738 | ret = tg3_phy_auxctl_read(tp, | |
1739 | MII_TG3_AUXCTL_SHDWSEL_MISC, &phy); | |
1740 | if (!ret) { | |
1741 | if (enable) | |
1742 | phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX; | |
1743 | else | |
1744 | phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX; | |
1745 | tg3_phy_auxctl_write(tp, | |
1746 | MII_TG3_AUXCTL_SHDWSEL_MISC, phy); | |
1747 | } | |
1748 | } | |
1749 | } | |
1750 | ||
1751 | static void tg3_phy_set_wirespeed(struct tg3 *tp) | |
1752 | { | |
1753 | int ret; | |
1754 | u32 val; | |
1755 | ||
1756 | if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) | |
1757 | return; | |
1758 | ||
1759 | ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val); | |
1760 | if (!ret) | |
1761 | tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, | |
1762 | val | MII_TG3_AUXCTL_MISC_WIRESPD_EN); | |
1763 | } | |
1764 | ||
1765 | static void tg3_phy_apply_otp(struct tg3 *tp) | |
1766 | { | |
1767 | u32 otp, phy; | |
1768 | ||
1769 | if (!tp->phy_otp) | |
1770 | return; | |
1771 | ||
1772 | otp = tp->phy_otp; | |
1773 | ||
1774 | if (TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) | |
1775 | return; | |
1776 | ||
1777 | phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT); | |
1778 | phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT; | |
1779 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy); | |
1780 | ||
1781 | phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) | | |
1782 | ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT); | |
1783 | tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy); | |
1784 | ||
1785 | phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT); | |
1786 | phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ; | |
1787 | tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy); | |
1788 | ||
1789 | phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT); | |
1790 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy); | |
1791 | ||
1792 | phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT); | |
1793 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy); | |
1794 | ||
1795 | phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) | | |
1796 | ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT); | |
1797 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy); | |
1798 | ||
1799 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); | |
1800 | } | |
1801 | ||
1802 | static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up) | |
1803 | { | |
1804 | u32 val; | |
1805 | ||
1806 | if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) | |
1807 | return; | |
1808 | ||
1809 | tp->setlpicnt = 0; | |
1810 | ||
1811 | if (tp->link_config.autoneg == AUTONEG_ENABLE && | |
1812 | current_link_up == 1 && | |
1813 | tp->link_config.active_duplex == DUPLEX_FULL && | |
1814 | (tp->link_config.active_speed == SPEED_100 || | |
1815 | tp->link_config.active_speed == SPEED_1000)) { | |
1816 | u32 eeectl; | |
1817 | ||
1818 | if (tp->link_config.active_speed == SPEED_1000) | |
1819 | eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US; | |
1820 | else | |
1821 | eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US; | |
1822 | ||
1823 | tw32(TG3_CPMU_EEE_CTRL, eeectl); | |
1824 | ||
1825 | tg3_phy_cl45_read(tp, MDIO_MMD_AN, | |
1826 | TG3_CL45_D7_EEERES_STAT, &val); | |
1827 | ||
1828 | if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T || | |
1829 | val == TG3_CL45_D7_EEERES_STAT_LP_100TX) | |
1830 | tp->setlpicnt = 2; | |
1831 | } | |
1832 | ||
1833 | if (!tp->setlpicnt) { | |
1834 | val = tr32(TG3_CPMU_EEE_MODE); | |
1835 | tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE); | |
1836 | } | |
1837 | } | |
1838 | ||
1839 | static void tg3_phy_eee_enable(struct tg3 *tp) | |
1840 | { | |
1841 | u32 val; | |
1842 | ||
1843 | if (tp->link_config.active_speed == SPEED_1000 && | |
1844 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | |
1845 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | |
1846 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) && | |
1847 | !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) { | |
1848 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0003); | |
1849 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); | |
1850 | } | |
1851 | ||
1852 | val = tr32(TG3_CPMU_EEE_MODE); | |
1853 | tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE); | |
1854 | } | |
1855 | ||
1856 | static int tg3_wait_macro_done(struct tg3 *tp) | |
1857 | { | |
1858 | int limit = 100; | |
1859 | ||
1860 | while (limit--) { | |
1861 | u32 tmp32; | |
1862 | ||
1863 | if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) { | |
1864 | if ((tmp32 & 0x1000) == 0) | |
1865 | break; | |
1866 | } | |
1867 | } | |
1868 | if (limit < 0) | |
1869 | return -EBUSY; | |
1870 | ||
1871 | return 0; | |
1872 | } | |
1873 | ||
1874 | static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp) | |
1875 | { | |
1876 | static const u32 test_pat[4][6] = { | |
1877 | { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 }, | |
1878 | { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 }, | |
1879 | { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 }, | |
1880 | { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 } | |
1881 | }; | |
1882 | int chan; | |
1883 | ||
1884 | for (chan = 0; chan < 4; chan++) { | |
1885 | int i; | |
1886 | ||
1887 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, | |
1888 | (chan * 0x2000) | 0x0200); | |
1889 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002); | |
1890 | ||
1891 | for (i = 0; i < 6; i++) | |
1892 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, | |
1893 | test_pat[chan][i]); | |
1894 | ||
1895 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202); | |
1896 | if (tg3_wait_macro_done(tp)) { | |
1897 | *resetp = 1; | |
1898 | return -EBUSY; | |
1899 | } | |
1900 | ||
1901 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, | |
1902 | (chan * 0x2000) | 0x0200); | |
1903 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082); | |
1904 | if (tg3_wait_macro_done(tp)) { | |
1905 | *resetp = 1; | |
1906 | return -EBUSY; | |
1907 | } | |
1908 | ||
1909 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802); | |
1910 | if (tg3_wait_macro_done(tp)) { | |
1911 | *resetp = 1; | |
1912 | return -EBUSY; | |
1913 | } | |
1914 | ||
1915 | for (i = 0; i < 6; i += 2) { | |
1916 | u32 low, high; | |
1917 | ||
1918 | if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) || | |
1919 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) || | |
1920 | tg3_wait_macro_done(tp)) { | |
1921 | *resetp = 1; | |
1922 | return -EBUSY; | |
1923 | } | |
1924 | low &= 0x7fff; | |
1925 | high &= 0x000f; | |
1926 | if (low != test_pat[chan][i] || | |
1927 | high != test_pat[chan][i+1]) { | |
1928 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b); | |
1929 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001); | |
1930 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005); | |
1931 | ||
1932 | return -EBUSY; | |
1933 | } | |
1934 | } | |
1935 | } | |
1936 | ||
1937 | return 0; | |
1938 | } | |
1939 | ||
1940 | static int tg3_phy_reset_chanpat(struct tg3 *tp) | |
1941 | { | |
1942 | int chan; | |
1943 | ||
1944 | for (chan = 0; chan < 4; chan++) { | |
1945 | int i; | |
1946 | ||
1947 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, | |
1948 | (chan * 0x2000) | 0x0200); | |
1949 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002); | |
1950 | for (i = 0; i < 6; i++) | |
1951 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000); | |
1952 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202); | |
1953 | if (tg3_wait_macro_done(tp)) | |
1954 | return -EBUSY; | |
1955 | } | |
1956 | ||
1957 | return 0; | |
1958 | } | |
1959 | ||
1960 | static int tg3_phy_reset_5703_4_5(struct tg3 *tp) | |
1961 | { | |
1962 | u32 reg32, phy9_orig; | |
1963 | int retries, do_phy_reset, err; | |
1964 | ||
1965 | retries = 10; | |
1966 | do_phy_reset = 1; | |
1967 | do { | |
1968 | if (do_phy_reset) { | |
1969 | err = tg3_bmcr_reset(tp); | |
1970 | if (err) | |
1971 | return err; | |
1972 | do_phy_reset = 0; | |
1973 | } | |
1974 | ||
1975 | /* Disable transmitter and interrupt. */ | |
1976 | if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) | |
1977 | continue; | |
1978 | ||
1979 | reg32 |= 0x3000; | |
1980 | tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); | |
1981 | ||
1982 | /* Set full-duplex, 1000 mbps. */ | |
1983 | tg3_writephy(tp, MII_BMCR, | |
1984 | BMCR_FULLDPLX | TG3_BMCR_SPEED1000); | |
1985 | ||
1986 | /* Set to master mode. */ | |
1987 | if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig)) | |
1988 | continue; | |
1989 | ||
1990 | tg3_writephy(tp, MII_TG3_CTRL, | |
1991 | (MII_TG3_CTRL_AS_MASTER | | |
1992 | MII_TG3_CTRL_ENABLE_AS_MASTER)); | |
1993 | ||
1994 | err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp); | |
1995 | if (err) | |
1996 | return err; | |
1997 | ||
1998 | /* Block the PHY control access. */ | |
1999 | tg3_phydsp_write(tp, 0x8005, 0x0800); | |
2000 | ||
2001 | err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset); | |
2002 | if (!err) | |
2003 | break; | |
2004 | } while (--retries); | |
2005 | ||
2006 | err = tg3_phy_reset_chanpat(tp); | |
2007 | if (err) | |
2008 | return err; | |
2009 | ||
2010 | tg3_phydsp_write(tp, 0x8005, 0x0000); | |
2011 | ||
2012 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200); | |
2013 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000); | |
2014 | ||
2015 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); | |
2016 | ||
2017 | tg3_writephy(tp, MII_TG3_CTRL, phy9_orig); | |
2018 | ||
2019 | if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) { | |
2020 | reg32 &= ~0x3000; | |
2021 | tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); | |
2022 | } else if (!err) | |
2023 | err = -EBUSY; | |
2024 | ||
2025 | return err; | |
2026 | } | |
2027 | ||
2028 | /* This will reset the tigon3 PHY if there is no valid | |
2029 | * link unless the FORCE argument is non-zero. | |
2030 | */ | |
2031 | static int tg3_phy_reset(struct tg3 *tp) | |
2032 | { | |
2033 | u32 val, cpmuctrl; | |
2034 | int err; | |
2035 | ||
2036 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | |
2037 | val = tr32(GRC_MISC_CFG); | |
2038 | tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ); | |
2039 | udelay(40); | |
2040 | } | |
2041 | err = tg3_readphy(tp, MII_BMSR, &val); | |
2042 | err |= tg3_readphy(tp, MII_BMSR, &val); | |
2043 | if (err != 0) | |
2044 | return -EBUSY; | |
2045 | ||
2046 | if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) { | |
2047 | netif_carrier_off(tp->dev); | |
2048 | tg3_link_report(tp); | |
2049 | } | |
2050 | ||
2051 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
2052 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
2053 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | |
2054 | err = tg3_phy_reset_5703_4_5(tp); | |
2055 | if (err) | |
2056 | return err; | |
2057 | goto out; | |
2058 | } | |
2059 | ||
2060 | cpmuctrl = 0; | |
2061 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && | |
2062 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) { | |
2063 | cpmuctrl = tr32(TG3_CPMU_CTRL); | |
2064 | if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) | |
2065 | tw32(TG3_CPMU_CTRL, | |
2066 | cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY); | |
2067 | } | |
2068 | ||
2069 | err = tg3_bmcr_reset(tp); | |
2070 | if (err) | |
2071 | return err; | |
2072 | ||
2073 | if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) { | |
2074 | val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz; | |
2075 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val); | |
2076 | ||
2077 | tw32(TG3_CPMU_CTRL, cpmuctrl); | |
2078 | } | |
2079 | ||
2080 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX || | |
2081 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) { | |
2082 | val = tr32(TG3_CPMU_LSPD_1000MB_CLK); | |
2083 | if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) == | |
2084 | CPMU_LSPD_1000MB_MACCLK_12_5) { | |
2085 | val &= ~CPMU_LSPD_1000MB_MACCLK_MASK; | |
2086 | udelay(40); | |
2087 | tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val); | |
2088 | } | |
2089 | } | |
2090 | ||
2091 | if (tg3_flag(tp, 5717_PLUS) && | |
2092 | (tp->phy_flags & TG3_PHYFLG_MII_SERDES)) | |
2093 | return 0; | |
2094 | ||
2095 | tg3_phy_apply_otp(tp); | |
2096 | ||
2097 | if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) | |
2098 | tg3_phy_toggle_apd(tp, true); | |
2099 | else | |
2100 | tg3_phy_toggle_apd(tp, false); | |
2101 | ||
2102 | out: | |
2103 | if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) && | |
2104 | !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) { | |
2105 | tg3_phydsp_write(tp, 0x201f, 0x2aaa); | |
2106 | tg3_phydsp_write(tp, 0x000a, 0x0323); | |
2107 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); | |
2108 | } | |
2109 | ||
2110 | if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) { | |
2111 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); | |
2112 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); | |
2113 | } | |
2114 | ||
2115 | if (tp->phy_flags & TG3_PHYFLG_BER_BUG) { | |
2116 | if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) { | |
2117 | tg3_phydsp_write(tp, 0x000a, 0x310b); | |
2118 | tg3_phydsp_write(tp, 0x201f, 0x9506); | |
2119 | tg3_phydsp_write(tp, 0x401f, 0x14e2); | |
2120 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); | |
2121 | } | |
2122 | } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) { | |
2123 | if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) { | |
2124 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a); | |
2125 | if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) { | |
2126 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b); | |
2127 | tg3_writephy(tp, MII_TG3_TEST1, | |
2128 | MII_TG3_TEST1_TRIM_EN | 0x4); | |
2129 | } else | |
2130 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b); | |
2131 | ||
2132 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); | |
2133 | } | |
2134 | } | |
2135 | ||
2136 | /* Set Extended packet length bit (bit 14) on all chips that */ | |
2137 | /* support jumbo frames */ | |
2138 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { | |
2139 | /* Cannot do read-modify-write on 5401 */ | |
2140 | tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20); | |
2141 | } else if (tg3_flag(tp, JUMBO_CAPABLE)) { | |
2142 | /* Set bit 14 with read-modify-write to preserve other bits */ | |
2143 | err = tg3_phy_auxctl_read(tp, | |
2144 | MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val); | |
2145 | if (!err) | |
2146 | tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, | |
2147 | val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN); | |
2148 | } | |
2149 | ||
2150 | /* Set phy register 0x10 bit 0 to high fifo elasticity to support | |
2151 | * jumbo frames transmission. | |
2152 | */ | |
2153 | if (tg3_flag(tp, JUMBO_CAPABLE)) { | |
2154 | if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val)) | |
2155 | tg3_writephy(tp, MII_TG3_EXT_CTRL, | |
2156 | val | MII_TG3_EXT_CTRL_FIFO_ELASTIC); | |
2157 | } | |
2158 | ||
2159 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | |
2160 | /* adjust output voltage */ | |
2161 | tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12); | |
2162 | } | |
2163 | ||
2164 | tg3_phy_toggle_automdix(tp, 1); | |
2165 | tg3_phy_set_wirespeed(tp); | |
2166 | return 0; | |
2167 | } | |
2168 | ||
2169 | static void tg3_frob_aux_power(struct tg3 *tp) | |
2170 | { | |
2171 | bool need_vaux = false; | |
2172 | ||
2173 | /* The GPIOs do something completely different on 57765. */ | |
2174 | if (!tg3_flag(tp, IS_NIC) || | |
2175 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | |
2176 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
2177 | return; | |
2178 | ||
2179 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
2180 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 || | |
2181 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | |
2182 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) && | |
2183 | tp->pdev_peer != tp->pdev) { | |
2184 | struct net_device *dev_peer; | |
2185 | ||
2186 | dev_peer = pci_get_drvdata(tp->pdev_peer); | |
2187 | ||
2188 | /* remove_one() may have been run on the peer. */ | |
2189 | if (dev_peer) { | |
2190 | struct tg3 *tp_peer = netdev_priv(dev_peer); | |
2191 | ||
2192 | if (tg3_flag(tp_peer, INIT_COMPLETE)) | |
2193 | return; | |
2194 | ||
2195 | if (tg3_flag(tp_peer, WOL_ENABLE) || | |
2196 | tg3_flag(tp_peer, ENABLE_ASF)) | |
2197 | need_vaux = true; | |
2198 | } | |
2199 | } | |
2200 | ||
2201 | if (tg3_flag(tp, WOL_ENABLE) || tg3_flag(tp, ENABLE_ASF)) | |
2202 | need_vaux = true; | |
2203 | ||
2204 | if (need_vaux) { | |
2205 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2206 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
2207 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | | |
2208 | (GRC_LCLCTRL_GPIO_OE0 | | |
2209 | GRC_LCLCTRL_GPIO_OE1 | | |
2210 | GRC_LCLCTRL_GPIO_OE2 | | |
2211 | GRC_LCLCTRL_GPIO_OUTPUT0 | | |
2212 | GRC_LCLCTRL_GPIO_OUTPUT1), | |
2213 | 100); | |
2214 | } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || | |
2215 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { | |
2216 | /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */ | |
2217 | u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 | | |
2218 | GRC_LCLCTRL_GPIO_OE1 | | |
2219 | GRC_LCLCTRL_GPIO_OE2 | | |
2220 | GRC_LCLCTRL_GPIO_OUTPUT0 | | |
2221 | GRC_LCLCTRL_GPIO_OUTPUT1 | | |
2222 | tp->grc_local_ctrl; | |
2223 | tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100); | |
2224 | ||
2225 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2; | |
2226 | tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100); | |
2227 | ||
2228 | grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0; | |
2229 | tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100); | |
2230 | } else { | |
2231 | u32 no_gpio2; | |
2232 | u32 grc_local_ctrl = 0; | |
2233 | ||
2234 | /* Workaround to prevent overdrawing Amps. */ | |
2235 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == | |
2236 | ASIC_REV_5714) { | |
2237 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3; | |
2238 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | | |
2239 | grc_local_ctrl, 100); | |
2240 | } | |
2241 | ||
2242 | /* On 5753 and variants, GPIO2 cannot be used. */ | |
2243 | no_gpio2 = tp->nic_sram_data_cfg & | |
2244 | NIC_SRAM_DATA_CFG_NO_GPIO2; | |
2245 | ||
2246 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 | | |
2247 | GRC_LCLCTRL_GPIO_OE1 | | |
2248 | GRC_LCLCTRL_GPIO_OE2 | | |
2249 | GRC_LCLCTRL_GPIO_OUTPUT1 | | |
2250 | GRC_LCLCTRL_GPIO_OUTPUT2; | |
2251 | if (no_gpio2) { | |
2252 | grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 | | |
2253 | GRC_LCLCTRL_GPIO_OUTPUT2); | |
2254 | } | |
2255 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | | |
2256 | grc_local_ctrl, 100); | |
2257 | ||
2258 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0; | |
2259 | ||
2260 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | | |
2261 | grc_local_ctrl, 100); | |
2262 | ||
2263 | if (!no_gpio2) { | |
2264 | grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2; | |
2265 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | | |
2266 | grc_local_ctrl, 100); | |
2267 | } | |
2268 | } | |
2269 | } else { | |
2270 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | |
2271 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) { | |
2272 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | | |
2273 | (GRC_LCLCTRL_GPIO_OE1 | | |
2274 | GRC_LCLCTRL_GPIO_OUTPUT1), 100); | |
2275 | ||
2276 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | | |
2277 | GRC_LCLCTRL_GPIO_OE1, 100); | |
2278 | ||
2279 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | | |
2280 | (GRC_LCLCTRL_GPIO_OE1 | | |
2281 | GRC_LCLCTRL_GPIO_OUTPUT1), 100); | |
2282 | } | |
2283 | } | |
2284 | } | |
2285 | ||
2286 | static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed) | |
2287 | { | |
2288 | if (tp->led_ctrl == LED_CTRL_MODE_PHY_2) | |
2289 | return 1; | |
2290 | else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) { | |
2291 | if (speed != SPEED_10) | |
2292 | return 1; | |
2293 | } else if (speed == SPEED_10) | |
2294 | return 1; | |
2295 | ||
2296 | return 0; | |
2297 | } | |
2298 | ||
2299 | static int tg3_setup_phy(struct tg3 *, int); | |
2300 | ||
2301 | #define RESET_KIND_SHUTDOWN 0 | |
2302 | #define RESET_KIND_INIT 1 | |
2303 | #define RESET_KIND_SUSPEND 2 | |
2304 | ||
2305 | static void tg3_write_sig_post_reset(struct tg3 *, int); | |
2306 | static int tg3_halt_cpu(struct tg3 *, u32); | |
2307 | ||
2308 | static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power) | |
2309 | { | |
2310 | u32 val; | |
2311 | ||
2312 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { | |
2313 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { | |
2314 | u32 sg_dig_ctrl = tr32(SG_DIG_CTRL); | |
2315 | u32 serdes_cfg = tr32(MAC_SERDES_CFG); | |
2316 | ||
2317 | sg_dig_ctrl |= | |
2318 | SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET; | |
2319 | tw32(SG_DIG_CTRL, sg_dig_ctrl); | |
2320 | tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15)); | |
2321 | } | |
2322 | return; | |
2323 | } | |
2324 | ||
2325 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | |
2326 | tg3_bmcr_reset(tp); | |
2327 | val = tr32(GRC_MISC_CFG); | |
2328 | tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ); | |
2329 | udelay(40); | |
2330 | return; | |
2331 | } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) { | |
2332 | u32 phytest; | |
2333 | if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) { | |
2334 | u32 phy; | |
2335 | ||
2336 | tg3_writephy(tp, MII_ADVERTISE, 0); | |
2337 | tg3_writephy(tp, MII_BMCR, | |
2338 | BMCR_ANENABLE | BMCR_ANRESTART); | |
2339 | ||
2340 | tg3_writephy(tp, MII_TG3_FET_TEST, | |
2341 | phytest | MII_TG3_FET_SHADOW_EN); | |
2342 | if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) { | |
2343 | phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD; | |
2344 | tg3_writephy(tp, | |
2345 | MII_TG3_FET_SHDW_AUXMODE4, | |
2346 | phy); | |
2347 | } | |
2348 | tg3_writephy(tp, MII_TG3_FET_TEST, phytest); | |
2349 | } | |
2350 | return; | |
2351 | } else if (do_low_power) { | |
2352 | tg3_writephy(tp, MII_TG3_EXT_CTRL, | |
2353 | MII_TG3_EXT_CTRL_FORCE_LED_OFF); | |
2354 | ||
2355 | val = MII_TG3_AUXCTL_PCTL_100TX_LPWR | | |
2356 | MII_TG3_AUXCTL_PCTL_SPR_ISOLATE | | |
2357 | MII_TG3_AUXCTL_PCTL_VREG_11V; | |
2358 | tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val); | |
2359 | } | |
2360 | ||
2361 | /* The PHY should not be powered down on some chips because | |
2362 | * of bugs. | |
2363 | */ | |
2364 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2365 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
2366 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 && | |
2367 | (tp->phy_flags & TG3_PHYFLG_MII_SERDES))) | |
2368 | return; | |
2369 | ||
2370 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX || | |
2371 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) { | |
2372 | val = tr32(TG3_CPMU_LSPD_1000MB_CLK); | |
2373 | val &= ~CPMU_LSPD_1000MB_MACCLK_MASK; | |
2374 | val |= CPMU_LSPD_1000MB_MACCLK_12_5; | |
2375 | tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val); | |
2376 | } | |
2377 | ||
2378 | tg3_writephy(tp, MII_BMCR, BMCR_PDOWN); | |
2379 | } | |
2380 | ||
2381 | /* tp->lock is held. */ | |
2382 | static int tg3_nvram_lock(struct tg3 *tp) | |
2383 | { | |
2384 | if (tg3_flag(tp, NVRAM)) { | |
2385 | int i; | |
2386 | ||
2387 | if (tp->nvram_lock_cnt == 0) { | |
2388 | tw32(NVRAM_SWARB, SWARB_REQ_SET1); | |
2389 | for (i = 0; i < 8000; i++) { | |
2390 | if (tr32(NVRAM_SWARB) & SWARB_GNT1) | |
2391 | break; | |
2392 | udelay(20); | |
2393 | } | |
2394 | if (i == 8000) { | |
2395 | tw32(NVRAM_SWARB, SWARB_REQ_CLR1); | |
2396 | return -ENODEV; | |
2397 | } | |
2398 | } | |
2399 | tp->nvram_lock_cnt++; | |
2400 | } | |
2401 | return 0; | |
2402 | } | |
2403 | ||
2404 | /* tp->lock is held. */ | |
2405 | static void tg3_nvram_unlock(struct tg3 *tp) | |
2406 | { | |
2407 | if (tg3_flag(tp, NVRAM)) { | |
2408 | if (tp->nvram_lock_cnt > 0) | |
2409 | tp->nvram_lock_cnt--; | |
2410 | if (tp->nvram_lock_cnt == 0) | |
2411 | tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1); | |
2412 | } | |
2413 | } | |
2414 | ||
2415 | /* tp->lock is held. */ | |
2416 | static void tg3_enable_nvram_access(struct tg3 *tp) | |
2417 | { | |
2418 | if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) { | |
2419 | u32 nvaccess = tr32(NVRAM_ACCESS); | |
2420 | ||
2421 | tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE); | |
2422 | } | |
2423 | } | |
2424 | ||
2425 | /* tp->lock is held. */ | |
2426 | static void tg3_disable_nvram_access(struct tg3 *tp) | |
2427 | { | |
2428 | if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) { | |
2429 | u32 nvaccess = tr32(NVRAM_ACCESS); | |
2430 | ||
2431 | tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE); | |
2432 | } | |
2433 | } | |
2434 | ||
2435 | static int tg3_nvram_read_using_eeprom(struct tg3 *tp, | |
2436 | u32 offset, u32 *val) | |
2437 | { | |
2438 | u32 tmp; | |
2439 | int i; | |
2440 | ||
2441 | if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0) | |
2442 | return -EINVAL; | |
2443 | ||
2444 | tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK | | |
2445 | EEPROM_ADDR_DEVID_MASK | | |
2446 | EEPROM_ADDR_READ); | |
2447 | tw32(GRC_EEPROM_ADDR, | |
2448 | tmp | | |
2449 | (0 << EEPROM_ADDR_DEVID_SHIFT) | | |
2450 | ((offset << EEPROM_ADDR_ADDR_SHIFT) & | |
2451 | EEPROM_ADDR_ADDR_MASK) | | |
2452 | EEPROM_ADDR_READ | EEPROM_ADDR_START); | |
2453 | ||
2454 | for (i = 0; i < 1000; i++) { | |
2455 | tmp = tr32(GRC_EEPROM_ADDR); | |
2456 | ||
2457 | if (tmp & EEPROM_ADDR_COMPLETE) | |
2458 | break; | |
2459 | msleep(1); | |
2460 | } | |
2461 | if (!(tmp & EEPROM_ADDR_COMPLETE)) | |
2462 | return -EBUSY; | |
2463 | ||
2464 | tmp = tr32(GRC_EEPROM_DATA); | |
2465 | ||
2466 | /* | |
2467 | * The data will always be opposite the native endian | |
2468 | * format. Perform a blind byteswap to compensate. | |
2469 | */ | |
2470 | *val = swab32(tmp); | |
2471 | ||
2472 | return 0; | |
2473 | } | |
2474 | ||
2475 | #define NVRAM_CMD_TIMEOUT 10000 | |
2476 | ||
2477 | static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd) | |
2478 | { | |
2479 | int i; | |
2480 | ||
2481 | tw32(NVRAM_CMD, nvram_cmd); | |
2482 | for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) { | |
2483 | udelay(10); | |
2484 | if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) { | |
2485 | udelay(10); | |
2486 | break; | |
2487 | } | |
2488 | } | |
2489 | ||
2490 | if (i == NVRAM_CMD_TIMEOUT) | |
2491 | return -EBUSY; | |
2492 | ||
2493 | return 0; | |
2494 | } | |
2495 | ||
2496 | static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr) | |
2497 | { | |
2498 | if (tg3_flag(tp, NVRAM) && | |
2499 | tg3_flag(tp, NVRAM_BUFFERED) && | |
2500 | tg3_flag(tp, FLASH) && | |
2501 | !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) && | |
2502 | (tp->nvram_jedecnum == JEDEC_ATMEL)) | |
2503 | ||
2504 | addr = ((addr / tp->nvram_pagesize) << | |
2505 | ATMEL_AT45DB0X1B_PAGE_POS) + | |
2506 | (addr % tp->nvram_pagesize); | |
2507 | ||
2508 | return addr; | |
2509 | } | |
2510 | ||
2511 | static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr) | |
2512 | { | |
2513 | if (tg3_flag(tp, NVRAM) && | |
2514 | tg3_flag(tp, NVRAM_BUFFERED) && | |
2515 | tg3_flag(tp, FLASH) && | |
2516 | !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) && | |
2517 | (tp->nvram_jedecnum == JEDEC_ATMEL)) | |
2518 | ||
2519 | addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) * | |
2520 | tp->nvram_pagesize) + | |
2521 | (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1)); | |
2522 | ||
2523 | return addr; | |
2524 | } | |
2525 | ||
2526 | /* NOTE: Data read in from NVRAM is byteswapped according to | |
2527 | * the byteswapping settings for all other register accesses. | |
2528 | * tg3 devices are BE devices, so on a BE machine, the data | |
2529 | * returned will be exactly as it is seen in NVRAM. On a LE | |
2530 | * machine, the 32-bit value will be byteswapped. | |
2531 | */ | |
2532 | static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val) | |
2533 | { | |
2534 | int ret; | |
2535 | ||
2536 | if (!tg3_flag(tp, NVRAM)) | |
2537 | return tg3_nvram_read_using_eeprom(tp, offset, val); | |
2538 | ||
2539 | offset = tg3_nvram_phys_addr(tp, offset); | |
2540 | ||
2541 | if (offset > NVRAM_ADDR_MSK) | |
2542 | return -EINVAL; | |
2543 | ||
2544 | ret = tg3_nvram_lock(tp); | |
2545 | if (ret) | |
2546 | return ret; | |
2547 | ||
2548 | tg3_enable_nvram_access(tp); | |
2549 | ||
2550 | tw32(NVRAM_ADDR, offset); | |
2551 | ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO | | |
2552 | NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE); | |
2553 | ||
2554 | if (ret == 0) | |
2555 | *val = tr32(NVRAM_RDDATA); | |
2556 | ||
2557 | tg3_disable_nvram_access(tp); | |
2558 | ||
2559 | tg3_nvram_unlock(tp); | |
2560 | ||
2561 | return ret; | |
2562 | } | |
2563 | ||
2564 | /* Ensures NVRAM data is in bytestream format. */ | |
2565 | static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val) | |
2566 | { | |
2567 | u32 v; | |
2568 | int res = tg3_nvram_read(tp, offset, &v); | |
2569 | if (!res) | |
2570 | *val = cpu_to_be32(v); | |
2571 | return res; | |
2572 | } | |
2573 | ||
2574 | /* tp->lock is held. */ | |
2575 | static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1) | |
2576 | { | |
2577 | u32 addr_high, addr_low; | |
2578 | int i; | |
2579 | ||
2580 | addr_high = ((tp->dev->dev_addr[0] << 8) | | |
2581 | tp->dev->dev_addr[1]); | |
2582 | addr_low = ((tp->dev->dev_addr[2] << 24) | | |
2583 | (tp->dev->dev_addr[3] << 16) | | |
2584 | (tp->dev->dev_addr[4] << 8) | | |
2585 | (tp->dev->dev_addr[5] << 0)); | |
2586 | for (i = 0; i < 4; i++) { | |
2587 | if (i == 1 && skip_mac_1) | |
2588 | continue; | |
2589 | tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high); | |
2590 | tw32(MAC_ADDR_0_LOW + (i * 8), addr_low); | |
2591 | } | |
2592 | ||
2593 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
2594 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { | |
2595 | for (i = 0; i < 12; i++) { | |
2596 | tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high); | |
2597 | tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low); | |
2598 | } | |
2599 | } | |
2600 | ||
2601 | addr_high = (tp->dev->dev_addr[0] + | |
2602 | tp->dev->dev_addr[1] + | |
2603 | tp->dev->dev_addr[2] + | |
2604 | tp->dev->dev_addr[3] + | |
2605 | tp->dev->dev_addr[4] + | |
2606 | tp->dev->dev_addr[5]) & | |
2607 | TX_BACKOFF_SEED_MASK; | |
2608 | tw32(MAC_TX_BACKOFF_SEED, addr_high); | |
2609 | } | |
2610 | ||
2611 | static void tg3_enable_register_access(struct tg3 *tp) | |
2612 | { | |
2613 | /* | |
2614 | * Make sure register accesses (indirect or otherwise) will function | |
2615 | * correctly. | |
2616 | */ | |
2617 | pci_write_config_dword(tp->pdev, | |
2618 | TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl); | |
2619 | } | |
2620 | ||
2621 | static int tg3_power_up(struct tg3 *tp) | |
2622 | { | |
2623 | tg3_enable_register_access(tp); | |
2624 | ||
2625 | pci_set_power_state(tp->pdev, PCI_D0); | |
2626 | ||
2627 | /* Switch out of Vaux if it is a NIC */ | |
2628 | if (tg3_flag(tp, IS_NIC)) | |
2629 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100); | |
2630 | ||
2631 | return 0; | |
2632 | } | |
2633 | ||
2634 | static int tg3_power_down_prepare(struct tg3 *tp) | |
2635 | { | |
2636 | u32 misc_host_ctrl; | |
2637 | bool device_should_wake, do_low_power; | |
2638 | ||
2639 | tg3_enable_register_access(tp); | |
2640 | ||
2641 | /* Restore the CLKREQ setting. */ | |
2642 | if (tg3_flag(tp, CLKREQ_BUG)) { | |
2643 | u16 lnkctl; | |
2644 | ||
2645 | pci_read_config_word(tp->pdev, | |
2646 | tp->pcie_cap + PCI_EXP_LNKCTL, | |
2647 | &lnkctl); | |
2648 | lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN; | |
2649 | pci_write_config_word(tp->pdev, | |
2650 | tp->pcie_cap + PCI_EXP_LNKCTL, | |
2651 | lnkctl); | |
2652 | } | |
2653 | ||
2654 | misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL); | |
2655 | tw32(TG3PCI_MISC_HOST_CTRL, | |
2656 | misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT); | |
2657 | ||
2658 | device_should_wake = device_may_wakeup(&tp->pdev->dev) && | |
2659 | tg3_flag(tp, WOL_ENABLE); | |
2660 | ||
2661 | if (tg3_flag(tp, USE_PHYLIB)) { | |
2662 | do_low_power = false; | |
2663 | if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) && | |
2664 | !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { | |
2665 | struct phy_device *phydev; | |
2666 | u32 phyid, advertising; | |
2667 | ||
2668 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; | |
2669 | ||
2670 | tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER; | |
2671 | ||
2672 | tp->link_config.orig_speed = phydev->speed; | |
2673 | tp->link_config.orig_duplex = phydev->duplex; | |
2674 | tp->link_config.orig_autoneg = phydev->autoneg; | |
2675 | tp->link_config.orig_advertising = phydev->advertising; | |
2676 | ||
2677 | advertising = ADVERTISED_TP | | |
2678 | ADVERTISED_Pause | | |
2679 | ADVERTISED_Autoneg | | |
2680 | ADVERTISED_10baseT_Half; | |
2681 | ||
2682 | if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) { | |
2683 | if (tg3_flag(tp, WOL_SPEED_100MB)) | |
2684 | advertising |= | |
2685 | ADVERTISED_100baseT_Half | | |
2686 | ADVERTISED_100baseT_Full | | |
2687 | ADVERTISED_10baseT_Full; | |
2688 | else | |
2689 | advertising |= ADVERTISED_10baseT_Full; | |
2690 | } | |
2691 | ||
2692 | phydev->advertising = advertising; | |
2693 | ||
2694 | phy_start_aneg(phydev); | |
2695 | ||
2696 | phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask; | |
2697 | if (phyid != PHY_ID_BCMAC131) { | |
2698 | phyid &= PHY_BCM_OUI_MASK; | |
2699 | if (phyid == PHY_BCM_OUI_1 || | |
2700 | phyid == PHY_BCM_OUI_2 || | |
2701 | phyid == PHY_BCM_OUI_3) | |
2702 | do_low_power = true; | |
2703 | } | |
2704 | } | |
2705 | } else { | |
2706 | do_low_power = true; | |
2707 | ||
2708 | if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { | |
2709 | tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER; | |
2710 | tp->link_config.orig_speed = tp->link_config.speed; | |
2711 | tp->link_config.orig_duplex = tp->link_config.duplex; | |
2712 | tp->link_config.orig_autoneg = tp->link_config.autoneg; | |
2713 | } | |
2714 | ||
2715 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { | |
2716 | tp->link_config.speed = SPEED_10; | |
2717 | tp->link_config.duplex = DUPLEX_HALF; | |
2718 | tp->link_config.autoneg = AUTONEG_ENABLE; | |
2719 | tg3_setup_phy(tp, 0); | |
2720 | } | |
2721 | } | |
2722 | ||
2723 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | |
2724 | u32 val; | |
2725 | ||
2726 | val = tr32(GRC_VCPU_EXT_CTRL); | |
2727 | tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL); | |
2728 | } else if (!tg3_flag(tp, ENABLE_ASF)) { | |
2729 | int i; | |
2730 | u32 val; | |
2731 | ||
2732 | for (i = 0; i < 200; i++) { | |
2733 | tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val); | |
2734 | if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1) | |
2735 | break; | |
2736 | msleep(1); | |
2737 | } | |
2738 | } | |
2739 | if (tg3_flag(tp, WOL_CAP)) | |
2740 | tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE | | |
2741 | WOL_DRV_STATE_SHUTDOWN | | |
2742 | WOL_DRV_WOL | | |
2743 | WOL_SET_MAGIC_PKT); | |
2744 | ||
2745 | if (device_should_wake) { | |
2746 | u32 mac_mode; | |
2747 | ||
2748 | if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { | |
2749 | if (do_low_power && | |
2750 | !(tp->phy_flags & TG3_PHYFLG_IS_FET)) { | |
2751 | tg3_phy_auxctl_write(tp, | |
2752 | MII_TG3_AUXCTL_SHDWSEL_PWRCTL, | |
2753 | MII_TG3_AUXCTL_PCTL_WOL_EN | | |
2754 | MII_TG3_AUXCTL_PCTL_100TX_LPWR | | |
2755 | MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC); | |
2756 | udelay(40); | |
2757 | } | |
2758 | ||
2759 | if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) | |
2760 | mac_mode = MAC_MODE_PORT_MODE_GMII; | |
2761 | else | |
2762 | mac_mode = MAC_MODE_PORT_MODE_MII; | |
2763 | ||
2764 | mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY; | |
2765 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == | |
2766 | ASIC_REV_5700) { | |
2767 | u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ? | |
2768 | SPEED_100 : SPEED_10; | |
2769 | if (tg3_5700_link_polarity(tp, speed)) | |
2770 | mac_mode |= MAC_MODE_LINK_POLARITY; | |
2771 | else | |
2772 | mac_mode &= ~MAC_MODE_LINK_POLARITY; | |
2773 | } | |
2774 | } else { | |
2775 | mac_mode = MAC_MODE_PORT_MODE_TBI; | |
2776 | } | |
2777 | ||
2778 | if (!tg3_flag(tp, 5750_PLUS)) | |
2779 | tw32(MAC_LED_CTRL, tp->led_ctrl); | |
2780 | ||
2781 | mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE; | |
2782 | if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) && | |
2783 | (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE))) | |
2784 | mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL; | |
2785 | ||
2786 | if (tg3_flag(tp, ENABLE_APE)) | |
2787 | mac_mode |= MAC_MODE_APE_TX_EN | | |
2788 | MAC_MODE_APE_RX_EN | | |
2789 | MAC_MODE_TDE_ENABLE; | |
2790 | ||
2791 | tw32_f(MAC_MODE, mac_mode); | |
2792 | udelay(100); | |
2793 | ||
2794 | tw32_f(MAC_RX_MODE, RX_MODE_ENABLE); | |
2795 | udelay(10); | |
2796 | } | |
2797 | ||
2798 | if (!tg3_flag(tp, WOL_SPEED_100MB) && | |
2799 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2800 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) { | |
2801 | u32 base_val; | |
2802 | ||
2803 | base_val = tp->pci_clock_ctrl; | |
2804 | base_val |= (CLOCK_CTRL_RXCLK_DISABLE | | |
2805 | CLOCK_CTRL_TXCLK_DISABLE); | |
2806 | ||
2807 | tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK | | |
2808 | CLOCK_CTRL_PWRDOWN_PLL133, 40); | |
2809 | } else if (tg3_flag(tp, 5780_CLASS) || | |
2810 | tg3_flag(tp, CPMU_PRESENT) || | |
2811 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | |
2812 | /* do nothing */ | |
2813 | } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) { | |
2814 | u32 newbits1, newbits2; | |
2815 | ||
2816 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2817 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
2818 | newbits1 = (CLOCK_CTRL_RXCLK_DISABLE | | |
2819 | CLOCK_CTRL_TXCLK_DISABLE | | |
2820 | CLOCK_CTRL_ALTCLK); | |
2821 | newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE; | |
2822 | } else if (tg3_flag(tp, 5705_PLUS)) { | |
2823 | newbits1 = CLOCK_CTRL_625_CORE; | |
2824 | newbits2 = newbits1 | CLOCK_CTRL_ALTCLK; | |
2825 | } else { | |
2826 | newbits1 = CLOCK_CTRL_ALTCLK; | |
2827 | newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE; | |
2828 | } | |
2829 | ||
2830 | tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1, | |
2831 | 40); | |
2832 | ||
2833 | tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2, | |
2834 | 40); | |
2835 | ||
2836 | if (!tg3_flag(tp, 5705_PLUS)) { | |
2837 | u32 newbits3; | |
2838 | ||
2839 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2840 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
2841 | newbits3 = (CLOCK_CTRL_RXCLK_DISABLE | | |
2842 | CLOCK_CTRL_TXCLK_DISABLE | | |
2843 | CLOCK_CTRL_44MHZ_CORE); | |
2844 | } else { | |
2845 | newbits3 = CLOCK_CTRL_44MHZ_CORE; | |
2846 | } | |
2847 | ||
2848 | tw32_wait_f(TG3PCI_CLOCK_CTRL, | |
2849 | tp->pci_clock_ctrl | newbits3, 40); | |
2850 | } | |
2851 | } | |
2852 | ||
2853 | if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF)) | |
2854 | tg3_power_down_phy(tp, do_low_power); | |
2855 | ||
2856 | tg3_frob_aux_power(tp); | |
2857 | ||
2858 | /* Workaround for unstable PLL clock */ | |
2859 | if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) || | |
2860 | (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) { | |
2861 | u32 val = tr32(0x7d00); | |
2862 | ||
2863 | val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1); | |
2864 | tw32(0x7d00, val); | |
2865 | if (!tg3_flag(tp, ENABLE_ASF)) { | |
2866 | int err; | |
2867 | ||
2868 | err = tg3_nvram_lock(tp); | |
2869 | tg3_halt_cpu(tp, RX_CPU_BASE); | |
2870 | if (!err) | |
2871 | tg3_nvram_unlock(tp); | |
2872 | } | |
2873 | } | |
2874 | ||
2875 | tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN); | |
2876 | ||
2877 | return 0; | |
2878 | } | |
2879 | ||
2880 | static void tg3_power_down(struct tg3 *tp) | |
2881 | { | |
2882 | tg3_power_down_prepare(tp); | |
2883 | ||
2884 | pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE)); | |
2885 | pci_set_power_state(tp->pdev, PCI_D3hot); | |
2886 | } | |
2887 | ||
2888 | static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex) | |
2889 | { | |
2890 | switch (val & MII_TG3_AUX_STAT_SPDMASK) { | |
2891 | case MII_TG3_AUX_STAT_10HALF: | |
2892 | *speed = SPEED_10; | |
2893 | *duplex = DUPLEX_HALF; | |
2894 | break; | |
2895 | ||
2896 | case MII_TG3_AUX_STAT_10FULL: | |
2897 | *speed = SPEED_10; | |
2898 | *duplex = DUPLEX_FULL; | |
2899 | break; | |
2900 | ||
2901 | case MII_TG3_AUX_STAT_100HALF: | |
2902 | *speed = SPEED_100; | |
2903 | *duplex = DUPLEX_HALF; | |
2904 | break; | |
2905 | ||
2906 | case MII_TG3_AUX_STAT_100FULL: | |
2907 | *speed = SPEED_100; | |
2908 | *duplex = DUPLEX_FULL; | |
2909 | break; | |
2910 | ||
2911 | case MII_TG3_AUX_STAT_1000HALF: | |
2912 | *speed = SPEED_1000; | |
2913 | *duplex = DUPLEX_HALF; | |
2914 | break; | |
2915 | ||
2916 | case MII_TG3_AUX_STAT_1000FULL: | |
2917 | *speed = SPEED_1000; | |
2918 | *duplex = DUPLEX_FULL; | |
2919 | break; | |
2920 | ||
2921 | default: | |
2922 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { | |
2923 | *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 : | |
2924 | SPEED_10; | |
2925 | *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL : | |
2926 | DUPLEX_HALF; | |
2927 | break; | |
2928 | } | |
2929 | *speed = SPEED_INVALID; | |
2930 | *duplex = DUPLEX_INVALID; | |
2931 | break; | |
2932 | } | |
2933 | } | |
2934 | ||
2935 | static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl) | |
2936 | { | |
2937 | int err = 0; | |
2938 | u32 val, new_adv; | |
2939 | ||
2940 | new_adv = ADVERTISE_CSMA; | |
2941 | if (advertise & ADVERTISED_10baseT_Half) | |
2942 | new_adv |= ADVERTISE_10HALF; | |
2943 | if (advertise & ADVERTISED_10baseT_Full) | |
2944 | new_adv |= ADVERTISE_10FULL; | |
2945 | if (advertise & ADVERTISED_100baseT_Half) | |
2946 | new_adv |= ADVERTISE_100HALF; | |
2947 | if (advertise & ADVERTISED_100baseT_Full) | |
2948 | new_adv |= ADVERTISE_100FULL; | |
2949 | ||
2950 | new_adv |= tg3_advert_flowctrl_1000T(flowctrl); | |
2951 | ||
2952 | err = tg3_writephy(tp, MII_ADVERTISE, new_adv); | |
2953 | if (err) | |
2954 | goto done; | |
2955 | ||
2956 | if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) | |
2957 | goto done; | |
2958 | ||
2959 | new_adv = 0; | |
2960 | if (advertise & ADVERTISED_1000baseT_Half) | |
2961 | new_adv |= MII_TG3_CTRL_ADV_1000_HALF; | |
2962 | if (advertise & ADVERTISED_1000baseT_Full) | |
2963 | new_adv |= MII_TG3_CTRL_ADV_1000_FULL; | |
2964 | ||
2965 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
2966 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) | |
2967 | new_adv |= (MII_TG3_CTRL_AS_MASTER | | |
2968 | MII_TG3_CTRL_ENABLE_AS_MASTER); | |
2969 | ||
2970 | err = tg3_writephy(tp, MII_TG3_CTRL, new_adv); | |
2971 | if (err) | |
2972 | goto done; | |
2973 | ||
2974 | if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) | |
2975 | goto done; | |
2976 | ||
2977 | tw32(TG3_CPMU_EEE_MODE, | |
2978 | tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE); | |
2979 | ||
2980 | err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp); | |
2981 | if (!err) { | |
2982 | u32 err2; | |
2983 | ||
2984 | switch (GET_ASIC_REV(tp->pci_chip_rev_id)) { | |
2985 | case ASIC_REV_5717: | |
2986 | case ASIC_REV_57765: | |
2987 | if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val)) | |
2988 | tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val | | |
2989 | MII_TG3_DSP_CH34TP2_HIBW01); | |
2990 | /* Fall through */ | |
2991 | case ASIC_REV_5719: | |
2992 | val = MII_TG3_DSP_TAP26_ALNOKO | | |
2993 | MII_TG3_DSP_TAP26_RMRXSTO | | |
2994 | MII_TG3_DSP_TAP26_OPCSINPT; | |
2995 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val); | |
2996 | } | |
2997 | ||
2998 | val = 0; | |
2999 | /* Advertise 100-BaseTX EEE ability */ | |
3000 | if (advertise & ADVERTISED_100baseT_Full) | |
3001 | val |= MDIO_AN_EEE_ADV_100TX; | |
3002 | /* Advertise 1000-BaseT EEE ability */ | |
3003 | if (advertise & ADVERTISED_1000baseT_Full) | |
3004 | val |= MDIO_AN_EEE_ADV_1000T; | |
3005 | err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val); | |
3006 | ||
3007 | err2 = TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); | |
3008 | if (!err) | |
3009 | err = err2; | |
3010 | } | |
3011 | ||
3012 | done: | |
3013 | return err; | |
3014 | } | |
3015 | ||
3016 | static void tg3_phy_copper_begin(struct tg3 *tp) | |
3017 | { | |
3018 | u32 new_adv; | |
3019 | int i; | |
3020 | ||
3021 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { | |
3022 | new_adv = ADVERTISED_10baseT_Half | | |
3023 | ADVERTISED_10baseT_Full; | |
3024 | if (tg3_flag(tp, WOL_SPEED_100MB)) | |
3025 | new_adv |= ADVERTISED_100baseT_Half | | |
3026 | ADVERTISED_100baseT_Full; | |
3027 | ||
3028 | tg3_phy_autoneg_cfg(tp, new_adv, | |
3029 | FLOW_CTRL_TX | FLOW_CTRL_RX); | |
3030 | } else if (tp->link_config.speed == SPEED_INVALID) { | |
3031 | if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) | |
3032 | tp->link_config.advertising &= | |
3033 | ~(ADVERTISED_1000baseT_Half | | |
3034 | ADVERTISED_1000baseT_Full); | |
3035 | ||
3036 | tg3_phy_autoneg_cfg(tp, tp->link_config.advertising, | |
3037 | tp->link_config.flowctrl); | |
3038 | } else { | |
3039 | /* Asking for a specific link mode. */ | |
3040 | if (tp->link_config.speed == SPEED_1000) { | |
3041 | if (tp->link_config.duplex == DUPLEX_FULL) | |
3042 | new_adv = ADVERTISED_1000baseT_Full; | |
3043 | else | |
3044 | new_adv = ADVERTISED_1000baseT_Half; | |
3045 | } else if (tp->link_config.speed == SPEED_100) { | |
3046 | if (tp->link_config.duplex == DUPLEX_FULL) | |
3047 | new_adv = ADVERTISED_100baseT_Full; | |
3048 | else | |
3049 | new_adv = ADVERTISED_100baseT_Half; | |
3050 | } else { | |
3051 | if (tp->link_config.duplex == DUPLEX_FULL) | |
3052 | new_adv = ADVERTISED_10baseT_Full; | |
3053 | else | |
3054 | new_adv = ADVERTISED_10baseT_Half; | |
3055 | } | |
3056 | ||
3057 | tg3_phy_autoneg_cfg(tp, new_adv, | |
3058 | tp->link_config.flowctrl); | |
3059 | } | |
3060 | ||
3061 | if (tp->link_config.autoneg == AUTONEG_DISABLE && | |
3062 | tp->link_config.speed != SPEED_INVALID) { | |
3063 | u32 bmcr, orig_bmcr; | |
3064 | ||
3065 | tp->link_config.active_speed = tp->link_config.speed; | |
3066 | tp->link_config.active_duplex = tp->link_config.duplex; | |
3067 | ||
3068 | bmcr = 0; | |
3069 | switch (tp->link_config.speed) { | |
3070 | default: | |
3071 | case SPEED_10: | |
3072 | break; | |
3073 | ||
3074 | case SPEED_100: | |
3075 | bmcr |= BMCR_SPEED100; | |
3076 | break; | |
3077 | ||
3078 | case SPEED_1000: | |
3079 | bmcr |= TG3_BMCR_SPEED1000; | |
3080 | break; | |
3081 | } | |
3082 | ||
3083 | if (tp->link_config.duplex == DUPLEX_FULL) | |
3084 | bmcr |= BMCR_FULLDPLX; | |
3085 | ||
3086 | if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) && | |
3087 | (bmcr != orig_bmcr)) { | |
3088 | tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK); | |
3089 | for (i = 0; i < 1500; i++) { | |
3090 | u32 tmp; | |
3091 | ||
3092 | udelay(10); | |
3093 | if (tg3_readphy(tp, MII_BMSR, &tmp) || | |
3094 | tg3_readphy(tp, MII_BMSR, &tmp)) | |
3095 | continue; | |
3096 | if (!(tmp & BMSR_LSTATUS)) { | |
3097 | udelay(40); | |
3098 | break; | |
3099 | } | |
3100 | } | |
3101 | tg3_writephy(tp, MII_BMCR, bmcr); | |
3102 | udelay(40); | |
3103 | } | |
3104 | } else { | |
3105 | tg3_writephy(tp, MII_BMCR, | |
3106 | BMCR_ANENABLE | BMCR_ANRESTART); | |
3107 | } | |
3108 | } | |
3109 | ||
3110 | static int tg3_init_5401phy_dsp(struct tg3 *tp) | |
3111 | { | |
3112 | int err; | |
3113 | ||
3114 | /* Turn off tap power management. */ | |
3115 | /* Set Extended packet length bit */ | |
3116 | err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20); | |
3117 | ||
3118 | err |= tg3_phydsp_write(tp, 0x0012, 0x1804); | |
3119 | err |= tg3_phydsp_write(tp, 0x0013, 0x1204); | |
3120 | err |= tg3_phydsp_write(tp, 0x8006, 0x0132); | |
3121 | err |= tg3_phydsp_write(tp, 0x8006, 0x0232); | |
3122 | err |= tg3_phydsp_write(tp, 0x201f, 0x0a20); | |
3123 | ||
3124 | udelay(40); | |
3125 | ||
3126 | return err; | |
3127 | } | |
3128 | ||
3129 | static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask) | |
3130 | { | |
3131 | u32 adv_reg, all_mask = 0; | |
3132 | ||
3133 | if (mask & ADVERTISED_10baseT_Half) | |
3134 | all_mask |= ADVERTISE_10HALF; | |
3135 | if (mask & ADVERTISED_10baseT_Full) | |
3136 | all_mask |= ADVERTISE_10FULL; | |
3137 | if (mask & ADVERTISED_100baseT_Half) | |
3138 | all_mask |= ADVERTISE_100HALF; | |
3139 | if (mask & ADVERTISED_100baseT_Full) | |
3140 | all_mask |= ADVERTISE_100FULL; | |
3141 | ||
3142 | if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg)) | |
3143 | return 0; | |
3144 | ||
3145 | if ((adv_reg & all_mask) != all_mask) | |
3146 | return 0; | |
3147 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { | |
3148 | u32 tg3_ctrl; | |
3149 | ||
3150 | all_mask = 0; | |
3151 | if (mask & ADVERTISED_1000baseT_Half) | |
3152 | all_mask |= ADVERTISE_1000HALF; | |
3153 | if (mask & ADVERTISED_1000baseT_Full) | |
3154 | all_mask |= ADVERTISE_1000FULL; | |
3155 | ||
3156 | if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl)) | |
3157 | return 0; | |
3158 | ||
3159 | if ((tg3_ctrl & all_mask) != all_mask) | |
3160 | return 0; | |
3161 | } | |
3162 | return 1; | |
3163 | } | |
3164 | ||
3165 | static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv) | |
3166 | { | |
3167 | u32 curadv, reqadv; | |
3168 | ||
3169 | if (tg3_readphy(tp, MII_ADVERTISE, lcladv)) | |
3170 | return 1; | |
3171 | ||
3172 | curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); | |
3173 | reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl); | |
3174 | ||
3175 | if (tp->link_config.active_duplex == DUPLEX_FULL) { | |
3176 | if (curadv != reqadv) | |
3177 | return 0; | |
3178 | ||
3179 | if (tg3_flag(tp, PAUSE_AUTONEG)) | |
3180 | tg3_readphy(tp, MII_LPA, rmtadv); | |
3181 | } else { | |
3182 | /* Reprogram the advertisement register, even if it | |
3183 | * does not affect the current link. If the link | |
3184 | * gets renegotiated in the future, we can save an | |
3185 | * additional renegotiation cycle by advertising | |
3186 | * it correctly in the first place. | |
3187 | */ | |
3188 | if (curadv != reqadv) { | |
3189 | *lcladv &= ~(ADVERTISE_PAUSE_CAP | | |
3190 | ADVERTISE_PAUSE_ASYM); | |
3191 | tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv); | |
3192 | } | |
3193 | } | |
3194 | ||
3195 | return 1; | |
3196 | } | |
3197 | ||
3198 | static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset) | |
3199 | { | |
3200 | int current_link_up; | |
3201 | u32 bmsr, val; | |
3202 | u32 lcl_adv, rmt_adv; | |
3203 | u16 current_speed; | |
3204 | u8 current_duplex; | |
3205 | int i, err; | |
3206 | ||
3207 | tw32(MAC_EVENT, 0); | |
3208 | ||
3209 | tw32_f(MAC_STATUS, | |
3210 | (MAC_STATUS_SYNC_CHANGED | | |
3211 | MAC_STATUS_CFG_CHANGED | | |
3212 | MAC_STATUS_MI_COMPLETION | | |
3213 | MAC_STATUS_LNKSTATE_CHANGED)); | |
3214 | udelay(40); | |
3215 | ||
3216 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | |
3217 | tw32_f(MAC_MI_MODE, | |
3218 | (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); | |
3219 | udelay(80); | |
3220 | } | |
3221 | ||
3222 | tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0); | |
3223 | ||
3224 | /* Some third-party PHYs need to be reset on link going | |
3225 | * down. | |
3226 | */ | |
3227 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
3228 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
3229 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) && | |
3230 | netif_carrier_ok(tp->dev)) { | |
3231 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
3232 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
3233 | !(bmsr & BMSR_LSTATUS)) | |
3234 | force_reset = 1; | |
3235 | } | |
3236 | if (force_reset) | |
3237 | tg3_phy_reset(tp); | |
3238 | ||
3239 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { | |
3240 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
3241 | if (tg3_readphy(tp, MII_BMSR, &bmsr) || | |
3242 | !tg3_flag(tp, INIT_COMPLETE)) | |
3243 | bmsr = 0; | |
3244 | ||
3245 | if (!(bmsr & BMSR_LSTATUS)) { | |
3246 | err = tg3_init_5401phy_dsp(tp); | |
3247 | if (err) | |
3248 | return err; | |
3249 | ||
3250 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
3251 | for (i = 0; i < 1000; i++) { | |
3252 | udelay(10); | |
3253 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
3254 | (bmsr & BMSR_LSTATUS)) { | |
3255 | udelay(40); | |
3256 | break; | |
3257 | } | |
3258 | } | |
3259 | ||
3260 | if ((tp->phy_id & TG3_PHY_ID_REV_MASK) == | |
3261 | TG3_PHY_REV_BCM5401_B0 && | |
3262 | !(bmsr & BMSR_LSTATUS) && | |
3263 | tp->link_config.active_speed == SPEED_1000) { | |
3264 | err = tg3_phy_reset(tp); | |
3265 | if (!err) | |
3266 | err = tg3_init_5401phy_dsp(tp); | |
3267 | if (err) | |
3268 | return err; | |
3269 | } | |
3270 | } | |
3271 | } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
3272 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) { | |
3273 | /* 5701 {A0,B0} CRC bug workaround */ | |
3274 | tg3_writephy(tp, 0x15, 0x0a75); | |
3275 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68); | |
3276 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); | |
3277 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68); | |
3278 | } | |
3279 | ||
3280 | /* Clear pending interrupts... */ | |
3281 | tg3_readphy(tp, MII_TG3_ISTAT, &val); | |
3282 | tg3_readphy(tp, MII_TG3_ISTAT, &val); | |
3283 | ||
3284 | if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) | |
3285 | tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG); | |
3286 | else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) | |
3287 | tg3_writephy(tp, MII_TG3_IMASK, ~0); | |
3288 | ||
3289 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
3290 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
3291 | if (tp->led_ctrl == LED_CTRL_MODE_PHY_1) | |
3292 | tg3_writephy(tp, MII_TG3_EXT_CTRL, | |
3293 | MII_TG3_EXT_CTRL_LNK3_LED_MODE); | |
3294 | else | |
3295 | tg3_writephy(tp, MII_TG3_EXT_CTRL, 0); | |
3296 | } | |
3297 | ||
3298 | current_link_up = 0; | |
3299 | current_speed = SPEED_INVALID; | |
3300 | current_duplex = DUPLEX_INVALID; | |
3301 | ||
3302 | if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) { | |
3303 | err = tg3_phy_auxctl_read(tp, | |
3304 | MII_TG3_AUXCTL_SHDWSEL_MISCTEST, | |
3305 | &val); | |
3306 | if (!err && !(val & (1 << 10))) { | |
3307 | tg3_phy_auxctl_write(tp, | |
3308 | MII_TG3_AUXCTL_SHDWSEL_MISCTEST, | |
3309 | val | (1 << 10)); | |
3310 | goto relink; | |
3311 | } | |
3312 | } | |
3313 | ||
3314 | bmsr = 0; | |
3315 | for (i = 0; i < 100; i++) { | |
3316 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
3317 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
3318 | (bmsr & BMSR_LSTATUS)) | |
3319 | break; | |
3320 | udelay(40); | |
3321 | } | |
3322 | ||
3323 | if (bmsr & BMSR_LSTATUS) { | |
3324 | u32 aux_stat, bmcr; | |
3325 | ||
3326 | tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat); | |
3327 | for (i = 0; i < 2000; i++) { | |
3328 | udelay(10); | |
3329 | if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) && | |
3330 | aux_stat) | |
3331 | break; | |
3332 | } | |
3333 | ||
3334 | tg3_aux_stat_to_speed_duplex(tp, aux_stat, | |
3335 | ¤t_speed, | |
3336 | ¤t_duplex); | |
3337 | ||
3338 | bmcr = 0; | |
3339 | for (i = 0; i < 200; i++) { | |
3340 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
3341 | if (tg3_readphy(tp, MII_BMCR, &bmcr)) | |
3342 | continue; | |
3343 | if (bmcr && bmcr != 0x7fff) | |
3344 | break; | |
3345 | udelay(10); | |
3346 | } | |
3347 | ||
3348 | lcl_adv = 0; | |
3349 | rmt_adv = 0; | |
3350 | ||
3351 | tp->link_config.active_speed = current_speed; | |
3352 | tp->link_config.active_duplex = current_duplex; | |
3353 | ||
3354 | if (tp->link_config.autoneg == AUTONEG_ENABLE) { | |
3355 | if ((bmcr & BMCR_ANENABLE) && | |
3356 | tg3_copper_is_advertising_all(tp, | |
3357 | tp->link_config.advertising)) { | |
3358 | if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv, | |
3359 | &rmt_adv)) | |
3360 | current_link_up = 1; | |
3361 | } | |
3362 | } else { | |
3363 | if (!(bmcr & BMCR_ANENABLE) && | |
3364 | tp->link_config.speed == current_speed && | |
3365 | tp->link_config.duplex == current_duplex && | |
3366 | tp->link_config.flowctrl == | |
3367 | tp->link_config.active_flowctrl) { | |
3368 | current_link_up = 1; | |
3369 | } | |
3370 | } | |
3371 | ||
3372 | if (current_link_up == 1 && | |
3373 | tp->link_config.active_duplex == DUPLEX_FULL) | |
3374 | tg3_setup_flow_control(tp, lcl_adv, rmt_adv); | |
3375 | } | |
3376 | ||
3377 | relink: | |
3378 | if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { | |
3379 | tg3_phy_copper_begin(tp); | |
3380 | ||
3381 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
3382 | if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) || | |
3383 | (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)) | |
3384 | current_link_up = 1; | |
3385 | } | |
3386 | ||
3387 | tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK; | |
3388 | if (current_link_up == 1) { | |
3389 | if (tp->link_config.active_speed == SPEED_100 || | |
3390 | tp->link_config.active_speed == SPEED_10) | |
3391 | tp->mac_mode |= MAC_MODE_PORT_MODE_MII; | |
3392 | else | |
3393 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
3394 | } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) | |
3395 | tp->mac_mode |= MAC_MODE_PORT_MODE_MII; | |
3396 | else | |
3397 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
3398 | ||
3399 | tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; | |
3400 | if (tp->link_config.active_duplex == DUPLEX_HALF) | |
3401 | tp->mac_mode |= MAC_MODE_HALF_DUPLEX; | |
3402 | ||
3403 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) { | |
3404 | if (current_link_up == 1 && | |
3405 | tg3_5700_link_polarity(tp, tp->link_config.active_speed)) | |
3406 | tp->mac_mode |= MAC_MODE_LINK_POLARITY; | |
3407 | else | |
3408 | tp->mac_mode &= ~MAC_MODE_LINK_POLARITY; | |
3409 | } | |
3410 | ||
3411 | /* ??? Without this setting Netgear GA302T PHY does not | |
3412 | * ??? send/receive packets... | |
3413 | */ | |
3414 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 && | |
3415 | tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) { | |
3416 | tp->mi_mode |= MAC_MI_MODE_AUTO_POLL; | |
3417 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
3418 | udelay(80); | |
3419 | } | |
3420 | ||
3421 | tw32_f(MAC_MODE, tp->mac_mode); | |
3422 | udelay(40); | |
3423 | ||
3424 | tg3_phy_eee_adjust(tp, current_link_up); | |
3425 | ||
3426 | if (tg3_flag(tp, USE_LINKCHG_REG)) { | |
3427 | /* Polled via timer. */ | |
3428 | tw32_f(MAC_EVENT, 0); | |
3429 | } else { | |
3430 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
3431 | } | |
3432 | udelay(40); | |
3433 | ||
3434 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 && | |
3435 | current_link_up == 1 && | |
3436 | tp->link_config.active_speed == SPEED_1000 && | |
3437 | (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) { | |
3438 | udelay(120); | |
3439 | tw32_f(MAC_STATUS, | |
3440 | (MAC_STATUS_SYNC_CHANGED | | |
3441 | MAC_STATUS_CFG_CHANGED)); | |
3442 | udelay(40); | |
3443 | tg3_write_mem(tp, | |
3444 | NIC_SRAM_FIRMWARE_MBOX, | |
3445 | NIC_SRAM_FIRMWARE_MBOX_MAGIC2); | |
3446 | } | |
3447 | ||
3448 | /* Prevent send BD corruption. */ | |
3449 | if (tg3_flag(tp, CLKREQ_BUG)) { | |
3450 | u16 oldlnkctl, newlnkctl; | |
3451 | ||
3452 | pci_read_config_word(tp->pdev, | |
3453 | tp->pcie_cap + PCI_EXP_LNKCTL, | |
3454 | &oldlnkctl); | |
3455 | if (tp->link_config.active_speed == SPEED_100 || | |
3456 | tp->link_config.active_speed == SPEED_10) | |
3457 | newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN; | |
3458 | else | |
3459 | newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN; | |
3460 | if (newlnkctl != oldlnkctl) | |
3461 | pci_write_config_word(tp->pdev, | |
3462 | tp->pcie_cap + PCI_EXP_LNKCTL, | |
3463 | newlnkctl); | |
3464 | } | |
3465 | ||
3466 | if (current_link_up != netif_carrier_ok(tp->dev)) { | |
3467 | if (current_link_up) | |
3468 | netif_carrier_on(tp->dev); | |
3469 | else | |
3470 | netif_carrier_off(tp->dev); | |
3471 | tg3_link_report(tp); | |
3472 | } | |
3473 | ||
3474 | return 0; | |
3475 | } | |
3476 | ||
3477 | struct tg3_fiber_aneginfo { | |
3478 | int state; | |
3479 | #define ANEG_STATE_UNKNOWN 0 | |
3480 | #define ANEG_STATE_AN_ENABLE 1 | |
3481 | #define ANEG_STATE_RESTART_INIT 2 | |
3482 | #define ANEG_STATE_RESTART 3 | |
3483 | #define ANEG_STATE_DISABLE_LINK_OK 4 | |
3484 | #define ANEG_STATE_ABILITY_DETECT_INIT 5 | |
3485 | #define ANEG_STATE_ABILITY_DETECT 6 | |
3486 | #define ANEG_STATE_ACK_DETECT_INIT 7 | |
3487 | #define ANEG_STATE_ACK_DETECT 8 | |
3488 | #define ANEG_STATE_COMPLETE_ACK_INIT 9 | |
3489 | #define ANEG_STATE_COMPLETE_ACK 10 | |
3490 | #define ANEG_STATE_IDLE_DETECT_INIT 11 | |
3491 | #define ANEG_STATE_IDLE_DETECT 12 | |
3492 | #define ANEG_STATE_LINK_OK 13 | |
3493 | #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14 | |
3494 | #define ANEG_STATE_NEXT_PAGE_WAIT 15 | |
3495 | ||
3496 | u32 flags; | |
3497 | #define MR_AN_ENABLE 0x00000001 | |
3498 | #define MR_RESTART_AN 0x00000002 | |
3499 | #define MR_AN_COMPLETE 0x00000004 | |
3500 | #define MR_PAGE_RX 0x00000008 | |
3501 | #define MR_NP_LOADED 0x00000010 | |
3502 | #define MR_TOGGLE_TX 0x00000020 | |
3503 | #define MR_LP_ADV_FULL_DUPLEX 0x00000040 | |
3504 | #define MR_LP_ADV_HALF_DUPLEX 0x00000080 | |
3505 | #define MR_LP_ADV_SYM_PAUSE 0x00000100 | |
3506 | #define MR_LP_ADV_ASYM_PAUSE 0x00000200 | |
3507 | #define MR_LP_ADV_REMOTE_FAULT1 0x00000400 | |
3508 | #define MR_LP_ADV_REMOTE_FAULT2 0x00000800 | |
3509 | #define MR_LP_ADV_NEXT_PAGE 0x00001000 | |
3510 | #define MR_TOGGLE_RX 0x00002000 | |
3511 | #define MR_NP_RX 0x00004000 | |
3512 | ||
3513 | #define MR_LINK_OK 0x80000000 | |
3514 | ||
3515 | unsigned long link_time, cur_time; | |
3516 | ||
3517 | u32 ability_match_cfg; | |
3518 | int ability_match_count; | |
3519 | ||
3520 | char ability_match, idle_match, ack_match; | |
3521 | ||
3522 | u32 txconfig, rxconfig; | |
3523 | #define ANEG_CFG_NP 0x00000080 | |
3524 | #define ANEG_CFG_ACK 0x00000040 | |
3525 | #define ANEG_CFG_RF2 0x00000020 | |
3526 | #define ANEG_CFG_RF1 0x00000010 | |
3527 | #define ANEG_CFG_PS2 0x00000001 | |
3528 | #define ANEG_CFG_PS1 0x00008000 | |
3529 | #define ANEG_CFG_HD 0x00004000 | |
3530 | #define ANEG_CFG_FD 0x00002000 | |
3531 | #define ANEG_CFG_INVAL 0x00001f06 | |
3532 | ||
3533 | }; | |
3534 | #define ANEG_OK 0 | |
3535 | #define ANEG_DONE 1 | |
3536 | #define ANEG_TIMER_ENAB 2 | |
3537 | #define ANEG_FAILED -1 | |
3538 | ||
3539 | #define ANEG_STATE_SETTLE_TIME 10000 | |
3540 | ||
3541 | static int tg3_fiber_aneg_smachine(struct tg3 *tp, | |
3542 | struct tg3_fiber_aneginfo *ap) | |
3543 | { | |
3544 | u16 flowctrl; | |
3545 | unsigned long delta; | |
3546 | u32 rx_cfg_reg; | |
3547 | int ret; | |
3548 | ||
3549 | if (ap->state == ANEG_STATE_UNKNOWN) { | |
3550 | ap->rxconfig = 0; | |
3551 | ap->link_time = 0; | |
3552 | ap->cur_time = 0; | |
3553 | ap->ability_match_cfg = 0; | |
3554 | ap->ability_match_count = 0; | |
3555 | ap->ability_match = 0; | |
3556 | ap->idle_match = 0; | |
3557 | ap->ack_match = 0; | |
3558 | } | |
3559 | ap->cur_time++; | |
3560 | ||
3561 | if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) { | |
3562 | rx_cfg_reg = tr32(MAC_RX_AUTO_NEG); | |
3563 | ||
3564 | if (rx_cfg_reg != ap->ability_match_cfg) { | |
3565 | ap->ability_match_cfg = rx_cfg_reg; | |
3566 | ap->ability_match = 0; | |
3567 | ap->ability_match_count = 0; | |
3568 | } else { | |
3569 | if (++ap->ability_match_count > 1) { | |
3570 | ap->ability_match = 1; | |
3571 | ap->ability_match_cfg = rx_cfg_reg; | |
3572 | } | |
3573 | } | |
3574 | if (rx_cfg_reg & ANEG_CFG_ACK) | |
3575 | ap->ack_match = 1; | |
3576 | else | |
3577 | ap->ack_match = 0; | |
3578 | ||
3579 | ap->idle_match = 0; | |
3580 | } else { | |
3581 | ap->idle_match = 1; | |
3582 | ap->ability_match_cfg = 0; | |
3583 | ap->ability_match_count = 0; | |
3584 | ap->ability_match = 0; | |
3585 | ap->ack_match = 0; | |
3586 | ||
3587 | rx_cfg_reg = 0; | |
3588 | } | |
3589 | ||
3590 | ap->rxconfig = rx_cfg_reg; | |
3591 | ret = ANEG_OK; | |
3592 | ||
3593 | switch (ap->state) { | |
3594 | case ANEG_STATE_UNKNOWN: | |
3595 | if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN)) | |
3596 | ap->state = ANEG_STATE_AN_ENABLE; | |
3597 | ||
3598 | /* fallthru */ | |
3599 | case ANEG_STATE_AN_ENABLE: | |
3600 | ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX); | |
3601 | if (ap->flags & MR_AN_ENABLE) { | |
3602 | ap->link_time = 0; | |
3603 | ap->cur_time = 0; | |
3604 | ap->ability_match_cfg = 0; | |
3605 | ap->ability_match_count = 0; | |
3606 | ap->ability_match = 0; | |
3607 | ap->idle_match = 0; | |
3608 | ap->ack_match = 0; | |
3609 | ||
3610 | ap->state = ANEG_STATE_RESTART_INIT; | |
3611 | } else { | |
3612 | ap->state = ANEG_STATE_DISABLE_LINK_OK; | |
3613 | } | |
3614 | break; | |
3615 | ||
3616 | case ANEG_STATE_RESTART_INIT: | |
3617 | ap->link_time = ap->cur_time; | |
3618 | ap->flags &= ~(MR_NP_LOADED); | |
3619 | ap->txconfig = 0; | |
3620 | tw32(MAC_TX_AUTO_NEG, 0); | |
3621 | tp->mac_mode |= MAC_MODE_SEND_CONFIGS; | |
3622 | tw32_f(MAC_MODE, tp->mac_mode); | |
3623 | udelay(40); | |
3624 | ||
3625 | ret = ANEG_TIMER_ENAB; | |
3626 | ap->state = ANEG_STATE_RESTART; | |
3627 | ||
3628 | /* fallthru */ | |
3629 | case ANEG_STATE_RESTART: | |
3630 | delta = ap->cur_time - ap->link_time; | |
3631 | if (delta > ANEG_STATE_SETTLE_TIME) | |
3632 | ap->state = ANEG_STATE_ABILITY_DETECT_INIT; | |
3633 | else | |
3634 | ret = ANEG_TIMER_ENAB; | |
3635 | break; | |
3636 | ||
3637 | case ANEG_STATE_DISABLE_LINK_OK: | |
3638 | ret = ANEG_DONE; | |
3639 | break; | |
3640 | ||
3641 | case ANEG_STATE_ABILITY_DETECT_INIT: | |
3642 | ap->flags &= ~(MR_TOGGLE_TX); | |
3643 | ap->txconfig = ANEG_CFG_FD; | |
3644 | flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); | |
3645 | if (flowctrl & ADVERTISE_1000XPAUSE) | |
3646 | ap->txconfig |= ANEG_CFG_PS1; | |
3647 | if (flowctrl & ADVERTISE_1000XPSE_ASYM) | |
3648 | ap->txconfig |= ANEG_CFG_PS2; | |
3649 | tw32(MAC_TX_AUTO_NEG, ap->txconfig); | |
3650 | tp->mac_mode |= MAC_MODE_SEND_CONFIGS; | |
3651 | tw32_f(MAC_MODE, tp->mac_mode); | |
3652 | udelay(40); | |
3653 | ||
3654 | ap->state = ANEG_STATE_ABILITY_DETECT; | |
3655 | break; | |
3656 | ||
3657 | case ANEG_STATE_ABILITY_DETECT: | |
3658 | if (ap->ability_match != 0 && ap->rxconfig != 0) | |
3659 | ap->state = ANEG_STATE_ACK_DETECT_INIT; | |
3660 | break; | |
3661 | ||
3662 | case ANEG_STATE_ACK_DETECT_INIT: | |
3663 | ap->txconfig |= ANEG_CFG_ACK; | |
3664 | tw32(MAC_TX_AUTO_NEG, ap->txconfig); | |
3665 | tp->mac_mode |= MAC_MODE_SEND_CONFIGS; | |
3666 | tw32_f(MAC_MODE, tp->mac_mode); | |
3667 | udelay(40); | |
3668 | ||
3669 | ap->state = ANEG_STATE_ACK_DETECT; | |
3670 | ||
3671 | /* fallthru */ | |
3672 | case ANEG_STATE_ACK_DETECT: | |
3673 | if (ap->ack_match != 0) { | |
3674 | if ((ap->rxconfig & ~ANEG_CFG_ACK) == | |
3675 | (ap->ability_match_cfg & ~ANEG_CFG_ACK)) { | |
3676 | ap->state = ANEG_STATE_COMPLETE_ACK_INIT; | |
3677 | } else { | |
3678 | ap->state = ANEG_STATE_AN_ENABLE; | |
3679 | } | |
3680 | } else if (ap->ability_match != 0 && | |
3681 | ap->rxconfig == 0) { | |
3682 | ap->state = ANEG_STATE_AN_ENABLE; | |
3683 | } | |
3684 | break; | |
3685 | ||
3686 | case ANEG_STATE_COMPLETE_ACK_INIT: | |
3687 | if (ap->rxconfig & ANEG_CFG_INVAL) { | |
3688 | ret = ANEG_FAILED; | |
3689 | break; | |
3690 | } | |
3691 | ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX | | |
3692 | MR_LP_ADV_HALF_DUPLEX | | |
3693 | MR_LP_ADV_SYM_PAUSE | | |
3694 | MR_LP_ADV_ASYM_PAUSE | | |
3695 | MR_LP_ADV_REMOTE_FAULT1 | | |
3696 | MR_LP_ADV_REMOTE_FAULT2 | | |
3697 | MR_LP_ADV_NEXT_PAGE | | |
3698 | MR_TOGGLE_RX | | |
3699 | MR_NP_RX); | |
3700 | if (ap->rxconfig & ANEG_CFG_FD) | |
3701 | ap->flags |= MR_LP_ADV_FULL_DUPLEX; | |
3702 | if (ap->rxconfig & ANEG_CFG_HD) | |
3703 | ap->flags |= MR_LP_ADV_HALF_DUPLEX; | |
3704 | if (ap->rxconfig & ANEG_CFG_PS1) | |
3705 | ap->flags |= MR_LP_ADV_SYM_PAUSE; | |
3706 | if (ap->rxconfig & ANEG_CFG_PS2) | |
3707 | ap->flags |= MR_LP_ADV_ASYM_PAUSE; | |
3708 | if (ap->rxconfig & ANEG_CFG_RF1) | |
3709 | ap->flags |= MR_LP_ADV_REMOTE_FAULT1; | |
3710 | if (ap->rxconfig & ANEG_CFG_RF2) | |
3711 | ap->flags |= MR_LP_ADV_REMOTE_FAULT2; | |
3712 | if (ap->rxconfig & ANEG_CFG_NP) | |
3713 | ap->flags |= MR_LP_ADV_NEXT_PAGE; | |
3714 | ||
3715 | ap->link_time = ap->cur_time; | |
3716 | ||
3717 | ap->flags ^= (MR_TOGGLE_TX); | |
3718 | if (ap->rxconfig & 0x0008) | |
3719 | ap->flags |= MR_TOGGLE_RX; | |
3720 | if (ap->rxconfig & ANEG_CFG_NP) | |
3721 | ap->flags |= MR_NP_RX; | |
3722 | ap->flags |= MR_PAGE_RX; | |
3723 | ||
3724 | ap->state = ANEG_STATE_COMPLETE_ACK; | |
3725 | ret = ANEG_TIMER_ENAB; | |
3726 | break; | |
3727 | ||
3728 | case ANEG_STATE_COMPLETE_ACK: | |
3729 | if (ap->ability_match != 0 && | |
3730 | ap->rxconfig == 0) { | |
3731 | ap->state = ANEG_STATE_AN_ENABLE; | |
3732 | break; | |
3733 | } | |
3734 | delta = ap->cur_time - ap->link_time; | |
3735 | if (delta > ANEG_STATE_SETTLE_TIME) { | |
3736 | if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) { | |
3737 | ap->state = ANEG_STATE_IDLE_DETECT_INIT; | |
3738 | } else { | |
3739 | if ((ap->txconfig & ANEG_CFG_NP) == 0 && | |
3740 | !(ap->flags & MR_NP_RX)) { | |
3741 | ap->state = ANEG_STATE_IDLE_DETECT_INIT; | |
3742 | } else { | |
3743 | ret = ANEG_FAILED; | |
3744 | } | |
3745 | } | |
3746 | } | |
3747 | break; | |
3748 | ||
3749 | case ANEG_STATE_IDLE_DETECT_INIT: | |
3750 | ap->link_time = ap->cur_time; | |
3751 | tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; | |
3752 | tw32_f(MAC_MODE, tp->mac_mode); | |
3753 | udelay(40); | |
3754 | ||
3755 | ap->state = ANEG_STATE_IDLE_DETECT; | |
3756 | ret = ANEG_TIMER_ENAB; | |
3757 | break; | |
3758 | ||
3759 | case ANEG_STATE_IDLE_DETECT: | |
3760 | if (ap->ability_match != 0 && | |
3761 | ap->rxconfig == 0) { | |
3762 | ap->state = ANEG_STATE_AN_ENABLE; | |
3763 | break; | |
3764 | } | |
3765 | delta = ap->cur_time - ap->link_time; | |
3766 | if (delta > ANEG_STATE_SETTLE_TIME) { | |
3767 | /* XXX another gem from the Broadcom driver :( */ | |
3768 | ap->state = ANEG_STATE_LINK_OK; | |
3769 | } | |
3770 | break; | |
3771 | ||
3772 | case ANEG_STATE_LINK_OK: | |
3773 | ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK); | |
3774 | ret = ANEG_DONE; | |
3775 | break; | |
3776 | ||
3777 | case ANEG_STATE_NEXT_PAGE_WAIT_INIT: | |
3778 | /* ??? unimplemented */ | |
3779 | break; | |
3780 | ||
3781 | case ANEG_STATE_NEXT_PAGE_WAIT: | |
3782 | /* ??? unimplemented */ | |
3783 | break; | |
3784 | ||
3785 | default: | |
3786 | ret = ANEG_FAILED; | |
3787 | break; | |
3788 | } | |
3789 | ||
3790 | return ret; | |
3791 | } | |
3792 | ||
3793 | static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags) | |
3794 | { | |
3795 | int res = 0; | |
3796 | struct tg3_fiber_aneginfo aninfo; | |
3797 | int status = ANEG_FAILED; | |
3798 | unsigned int tick; | |
3799 | u32 tmp; | |
3800 | ||
3801 | tw32_f(MAC_TX_AUTO_NEG, 0); | |
3802 | ||
3803 | tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK; | |
3804 | tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII); | |
3805 | udelay(40); | |
3806 | ||
3807 | tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS); | |
3808 | udelay(40); | |
3809 | ||
3810 | memset(&aninfo, 0, sizeof(aninfo)); | |
3811 | aninfo.flags |= MR_AN_ENABLE; | |
3812 | aninfo.state = ANEG_STATE_UNKNOWN; | |
3813 | aninfo.cur_time = 0; | |
3814 | tick = 0; | |
3815 | while (++tick < 195000) { | |
3816 | status = tg3_fiber_aneg_smachine(tp, &aninfo); | |
3817 | if (status == ANEG_DONE || status == ANEG_FAILED) | |
3818 | break; | |
3819 | ||
3820 | udelay(1); | |
3821 | } | |
3822 | ||
3823 | tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; | |
3824 | tw32_f(MAC_MODE, tp->mac_mode); | |
3825 | udelay(40); | |
3826 | ||
3827 | *txflags = aninfo.txconfig; | |
3828 | *rxflags = aninfo.flags; | |
3829 | ||
3830 | if (status == ANEG_DONE && | |
3831 | (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK | | |
3832 | MR_LP_ADV_FULL_DUPLEX))) | |
3833 | res = 1; | |
3834 | ||
3835 | return res; | |
3836 | } | |
3837 | ||
3838 | static void tg3_init_bcm8002(struct tg3 *tp) | |
3839 | { | |
3840 | u32 mac_status = tr32(MAC_STATUS); | |
3841 | int i; | |
3842 | ||
3843 | /* Reset when initting first time or we have a link. */ | |
3844 | if (tg3_flag(tp, INIT_COMPLETE) && | |
3845 | !(mac_status & MAC_STATUS_PCS_SYNCED)) | |
3846 | return; | |
3847 | ||
3848 | /* Set PLL lock range. */ | |
3849 | tg3_writephy(tp, 0x16, 0x8007); | |
3850 | ||
3851 | /* SW reset */ | |
3852 | tg3_writephy(tp, MII_BMCR, BMCR_RESET); | |
3853 | ||
3854 | /* Wait for reset to complete. */ | |
3855 | /* XXX schedule_timeout() ... */ | |
3856 | for (i = 0; i < 500; i++) | |
3857 | udelay(10); | |
3858 | ||
3859 | /* Config mode; select PMA/Ch 1 regs. */ | |
3860 | tg3_writephy(tp, 0x10, 0x8411); | |
3861 | ||
3862 | /* Enable auto-lock and comdet, select txclk for tx. */ | |
3863 | tg3_writephy(tp, 0x11, 0x0a10); | |
3864 | ||
3865 | tg3_writephy(tp, 0x18, 0x00a0); | |
3866 | tg3_writephy(tp, 0x16, 0x41ff); | |
3867 | ||
3868 | /* Assert and deassert POR. */ | |
3869 | tg3_writephy(tp, 0x13, 0x0400); | |
3870 | udelay(40); | |
3871 | tg3_writephy(tp, 0x13, 0x0000); | |
3872 | ||
3873 | tg3_writephy(tp, 0x11, 0x0a50); | |
3874 | udelay(40); | |
3875 | tg3_writephy(tp, 0x11, 0x0a10); | |
3876 | ||
3877 | /* Wait for signal to stabilize */ | |
3878 | /* XXX schedule_timeout() ... */ | |
3879 | for (i = 0; i < 15000; i++) | |
3880 | udelay(10); | |
3881 | ||
3882 | /* Deselect the channel register so we can read the PHYID | |
3883 | * later. | |
3884 | */ | |
3885 | tg3_writephy(tp, 0x10, 0x8011); | |
3886 | } | |
3887 | ||
3888 | static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status) | |
3889 | { | |
3890 | u16 flowctrl; | |
3891 | u32 sg_dig_ctrl, sg_dig_status; | |
3892 | u32 serdes_cfg, expected_sg_dig_ctrl; | |
3893 | int workaround, port_a; | |
3894 | int current_link_up; | |
3895 | ||
3896 | serdes_cfg = 0; | |
3897 | expected_sg_dig_ctrl = 0; | |
3898 | workaround = 0; | |
3899 | port_a = 1; | |
3900 | current_link_up = 0; | |
3901 | ||
3902 | if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 && | |
3903 | tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) { | |
3904 | workaround = 1; | |
3905 | if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID) | |
3906 | port_a = 0; | |
3907 | ||
3908 | /* preserve bits 0-11,13,14 for signal pre-emphasis */ | |
3909 | /* preserve bits 20-23 for voltage regulator */ | |
3910 | serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff; | |
3911 | } | |
3912 | ||
3913 | sg_dig_ctrl = tr32(SG_DIG_CTRL); | |
3914 | ||
3915 | if (tp->link_config.autoneg != AUTONEG_ENABLE) { | |
3916 | if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) { | |
3917 | if (workaround) { | |
3918 | u32 val = serdes_cfg; | |
3919 | ||
3920 | if (port_a) | |
3921 | val |= 0xc010000; | |
3922 | else | |
3923 | val |= 0x4010000; | |
3924 | tw32_f(MAC_SERDES_CFG, val); | |
3925 | } | |
3926 | ||
3927 | tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP); | |
3928 | } | |
3929 | if (mac_status & MAC_STATUS_PCS_SYNCED) { | |
3930 | tg3_setup_flow_control(tp, 0, 0); | |
3931 | current_link_up = 1; | |
3932 | } | |
3933 | goto out; | |
3934 | } | |
3935 | ||
3936 | /* Want auto-negotiation. */ | |
3937 | expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP; | |
3938 | ||
3939 | flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); | |
3940 | if (flowctrl & ADVERTISE_1000XPAUSE) | |
3941 | expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP; | |
3942 | if (flowctrl & ADVERTISE_1000XPSE_ASYM) | |
3943 | expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE; | |
3944 | ||
3945 | if (sg_dig_ctrl != expected_sg_dig_ctrl) { | |
3946 | if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) && | |
3947 | tp->serdes_counter && | |
3948 | ((mac_status & (MAC_STATUS_PCS_SYNCED | | |
3949 | MAC_STATUS_RCVD_CFG)) == | |
3950 | MAC_STATUS_PCS_SYNCED)) { | |
3951 | tp->serdes_counter--; | |
3952 | current_link_up = 1; | |
3953 | goto out; | |
3954 | } | |
3955 | restart_autoneg: | |
3956 | if (workaround) | |
3957 | tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000); | |
3958 | tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET); | |
3959 | udelay(5); | |
3960 | tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl); | |
3961 | ||
3962 | tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; | |
3963 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; | |
3964 | } else if (mac_status & (MAC_STATUS_PCS_SYNCED | | |
3965 | MAC_STATUS_SIGNAL_DET)) { | |
3966 | sg_dig_status = tr32(SG_DIG_STATUS); | |
3967 | mac_status = tr32(MAC_STATUS); | |
3968 | ||
3969 | if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) && | |
3970 | (mac_status & MAC_STATUS_PCS_SYNCED)) { | |
3971 | u32 local_adv = 0, remote_adv = 0; | |
3972 | ||
3973 | if (sg_dig_ctrl & SG_DIG_PAUSE_CAP) | |
3974 | local_adv |= ADVERTISE_1000XPAUSE; | |
3975 | if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE) | |
3976 | local_adv |= ADVERTISE_1000XPSE_ASYM; | |
3977 | ||
3978 | if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE) | |
3979 | remote_adv |= LPA_1000XPAUSE; | |
3980 | if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE) | |
3981 | remote_adv |= LPA_1000XPAUSE_ASYM; | |
3982 | ||
3983 | tg3_setup_flow_control(tp, local_adv, remote_adv); | |
3984 | current_link_up = 1; | |
3985 | tp->serdes_counter = 0; | |
3986 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; | |
3987 | } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) { | |
3988 | if (tp->serdes_counter) | |
3989 | tp->serdes_counter--; | |
3990 | else { | |
3991 | if (workaround) { | |
3992 | u32 val = serdes_cfg; | |
3993 | ||
3994 | if (port_a) | |
3995 | val |= 0xc010000; | |
3996 | else | |
3997 | val |= 0x4010000; | |
3998 | ||
3999 | tw32_f(MAC_SERDES_CFG, val); | |
4000 | } | |
4001 | ||
4002 | tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP); | |
4003 | udelay(40); | |
4004 | ||
4005 | /* Link parallel detection - link is up */ | |
4006 | /* only if we have PCS_SYNC and not */ | |
4007 | /* receiving config code words */ | |
4008 | mac_status = tr32(MAC_STATUS); | |
4009 | if ((mac_status & MAC_STATUS_PCS_SYNCED) && | |
4010 | !(mac_status & MAC_STATUS_RCVD_CFG)) { | |
4011 | tg3_setup_flow_control(tp, 0, 0); | |
4012 | current_link_up = 1; | |
4013 | tp->phy_flags |= | |
4014 | TG3_PHYFLG_PARALLEL_DETECT; | |
4015 | tp->serdes_counter = | |
4016 | SERDES_PARALLEL_DET_TIMEOUT; | |
4017 | } else | |
4018 | goto restart_autoneg; | |
4019 | } | |
4020 | } | |
4021 | } else { | |
4022 | tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; | |
4023 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; | |
4024 | } | |
4025 | ||
4026 | out: | |
4027 | return current_link_up; | |
4028 | } | |
4029 | ||
4030 | static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status) | |
4031 | { | |
4032 | int current_link_up = 0; | |
4033 | ||
4034 | if (!(mac_status & MAC_STATUS_PCS_SYNCED)) | |
4035 | goto out; | |
4036 | ||
4037 | if (tp->link_config.autoneg == AUTONEG_ENABLE) { | |
4038 | u32 txflags, rxflags; | |
4039 | int i; | |
4040 | ||
4041 | if (fiber_autoneg(tp, &txflags, &rxflags)) { | |
4042 | u32 local_adv = 0, remote_adv = 0; | |
4043 | ||
4044 | if (txflags & ANEG_CFG_PS1) | |
4045 | local_adv |= ADVERTISE_1000XPAUSE; | |
4046 | if (txflags & ANEG_CFG_PS2) | |
4047 | local_adv |= ADVERTISE_1000XPSE_ASYM; | |
4048 | ||
4049 | if (rxflags & MR_LP_ADV_SYM_PAUSE) | |
4050 | remote_adv |= LPA_1000XPAUSE; | |
4051 | if (rxflags & MR_LP_ADV_ASYM_PAUSE) | |
4052 | remote_adv |= LPA_1000XPAUSE_ASYM; | |
4053 | ||
4054 | tg3_setup_flow_control(tp, local_adv, remote_adv); | |
4055 | ||
4056 | current_link_up = 1; | |
4057 | } | |
4058 | for (i = 0; i < 30; i++) { | |
4059 | udelay(20); | |
4060 | tw32_f(MAC_STATUS, | |
4061 | (MAC_STATUS_SYNC_CHANGED | | |
4062 | MAC_STATUS_CFG_CHANGED)); | |
4063 | udelay(40); | |
4064 | if ((tr32(MAC_STATUS) & | |
4065 | (MAC_STATUS_SYNC_CHANGED | | |
4066 | MAC_STATUS_CFG_CHANGED)) == 0) | |
4067 | break; | |
4068 | } | |
4069 | ||
4070 | mac_status = tr32(MAC_STATUS); | |
4071 | if (current_link_up == 0 && | |
4072 | (mac_status & MAC_STATUS_PCS_SYNCED) && | |
4073 | !(mac_status & MAC_STATUS_RCVD_CFG)) | |
4074 | current_link_up = 1; | |
4075 | } else { | |
4076 | tg3_setup_flow_control(tp, 0, 0); | |
4077 | ||
4078 | /* Forcing 1000FD link up. */ | |
4079 | current_link_up = 1; | |
4080 | ||
4081 | tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS)); | |
4082 | udelay(40); | |
4083 | ||
4084 | tw32_f(MAC_MODE, tp->mac_mode); | |
4085 | udelay(40); | |
4086 | } | |
4087 | ||
4088 | out: | |
4089 | return current_link_up; | |
4090 | } | |
4091 | ||
4092 | static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset) | |
4093 | { | |
4094 | u32 orig_pause_cfg; | |
4095 | u16 orig_active_speed; | |
4096 | u8 orig_active_duplex; | |
4097 | u32 mac_status; | |
4098 | int current_link_up; | |
4099 | int i; | |
4100 | ||
4101 | orig_pause_cfg = tp->link_config.active_flowctrl; | |
4102 | orig_active_speed = tp->link_config.active_speed; | |
4103 | orig_active_duplex = tp->link_config.active_duplex; | |
4104 | ||
4105 | if (!tg3_flag(tp, HW_AUTONEG) && | |
4106 | netif_carrier_ok(tp->dev) && | |
4107 | tg3_flag(tp, INIT_COMPLETE)) { | |
4108 | mac_status = tr32(MAC_STATUS); | |
4109 | mac_status &= (MAC_STATUS_PCS_SYNCED | | |
4110 | MAC_STATUS_SIGNAL_DET | | |
4111 | MAC_STATUS_CFG_CHANGED | | |
4112 | MAC_STATUS_RCVD_CFG); | |
4113 | if (mac_status == (MAC_STATUS_PCS_SYNCED | | |
4114 | MAC_STATUS_SIGNAL_DET)) { | |
4115 | tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED | | |
4116 | MAC_STATUS_CFG_CHANGED)); | |
4117 | return 0; | |
4118 | } | |
4119 | } | |
4120 | ||
4121 | tw32_f(MAC_TX_AUTO_NEG, 0); | |
4122 | ||
4123 | tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX); | |
4124 | tp->mac_mode |= MAC_MODE_PORT_MODE_TBI; | |
4125 | tw32_f(MAC_MODE, tp->mac_mode); | |
4126 | udelay(40); | |
4127 | ||
4128 | if (tp->phy_id == TG3_PHY_ID_BCM8002) | |
4129 | tg3_init_bcm8002(tp); | |
4130 | ||
4131 | /* Enable link change event even when serdes polling. */ | |
4132 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
4133 | udelay(40); | |
4134 | ||
4135 | current_link_up = 0; | |
4136 | mac_status = tr32(MAC_STATUS); | |
4137 | ||
4138 | if (tg3_flag(tp, HW_AUTONEG)) | |
4139 | current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status); | |
4140 | else | |
4141 | current_link_up = tg3_setup_fiber_by_hand(tp, mac_status); | |
4142 | ||
4143 | tp->napi[0].hw_status->status = | |
4144 | (SD_STATUS_UPDATED | | |
4145 | (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG)); | |
4146 | ||
4147 | for (i = 0; i < 100; i++) { | |
4148 | tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED | | |
4149 | MAC_STATUS_CFG_CHANGED)); | |
4150 | udelay(5); | |
4151 | if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED | | |
4152 | MAC_STATUS_CFG_CHANGED | | |
4153 | MAC_STATUS_LNKSTATE_CHANGED)) == 0) | |
4154 | break; | |
4155 | } | |
4156 | ||
4157 | mac_status = tr32(MAC_STATUS); | |
4158 | if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) { | |
4159 | current_link_up = 0; | |
4160 | if (tp->link_config.autoneg == AUTONEG_ENABLE && | |
4161 | tp->serdes_counter == 0) { | |
4162 | tw32_f(MAC_MODE, (tp->mac_mode | | |
4163 | MAC_MODE_SEND_CONFIGS)); | |
4164 | udelay(1); | |
4165 | tw32_f(MAC_MODE, tp->mac_mode); | |
4166 | } | |
4167 | } | |
4168 | ||
4169 | if (current_link_up == 1) { | |
4170 | tp->link_config.active_speed = SPEED_1000; | |
4171 | tp->link_config.active_duplex = DUPLEX_FULL; | |
4172 | tw32(MAC_LED_CTRL, (tp->led_ctrl | | |
4173 | LED_CTRL_LNKLED_OVERRIDE | | |
4174 | LED_CTRL_1000MBPS_ON)); | |
4175 | } else { | |
4176 | tp->link_config.active_speed = SPEED_INVALID; | |
4177 | tp->link_config.active_duplex = DUPLEX_INVALID; | |
4178 | tw32(MAC_LED_CTRL, (tp->led_ctrl | | |
4179 | LED_CTRL_LNKLED_OVERRIDE | | |
4180 | LED_CTRL_TRAFFIC_OVERRIDE)); | |
4181 | } | |
4182 | ||
4183 | if (current_link_up != netif_carrier_ok(tp->dev)) { | |
4184 | if (current_link_up) | |
4185 | netif_carrier_on(tp->dev); | |
4186 | else | |
4187 | netif_carrier_off(tp->dev); | |
4188 | tg3_link_report(tp); | |
4189 | } else { | |
4190 | u32 now_pause_cfg = tp->link_config.active_flowctrl; | |
4191 | if (orig_pause_cfg != now_pause_cfg || | |
4192 | orig_active_speed != tp->link_config.active_speed || | |
4193 | orig_active_duplex != tp->link_config.active_duplex) | |
4194 | tg3_link_report(tp); | |
4195 | } | |
4196 | ||
4197 | return 0; | |
4198 | } | |
4199 | ||
4200 | static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset) | |
4201 | { | |
4202 | int current_link_up, err = 0; | |
4203 | u32 bmsr, bmcr; | |
4204 | u16 current_speed; | |
4205 | u8 current_duplex; | |
4206 | u32 local_adv, remote_adv; | |
4207 | ||
4208 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
4209 | tw32_f(MAC_MODE, tp->mac_mode); | |
4210 | udelay(40); | |
4211 | ||
4212 | tw32(MAC_EVENT, 0); | |
4213 | ||
4214 | tw32_f(MAC_STATUS, | |
4215 | (MAC_STATUS_SYNC_CHANGED | | |
4216 | MAC_STATUS_CFG_CHANGED | | |
4217 | MAC_STATUS_MI_COMPLETION | | |
4218 | MAC_STATUS_LNKSTATE_CHANGED)); | |
4219 | udelay(40); | |
4220 | ||
4221 | if (force_reset) | |
4222 | tg3_phy_reset(tp); | |
4223 | ||
4224 | current_link_up = 0; | |
4225 | current_speed = SPEED_INVALID; | |
4226 | current_duplex = DUPLEX_INVALID; | |
4227 | ||
4228 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
4229 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
4230 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { | |
4231 | if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) | |
4232 | bmsr |= BMSR_LSTATUS; | |
4233 | else | |
4234 | bmsr &= ~BMSR_LSTATUS; | |
4235 | } | |
4236 | ||
4237 | err |= tg3_readphy(tp, MII_BMCR, &bmcr); | |
4238 | ||
4239 | if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset && | |
4240 | (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) { | |
4241 | /* do nothing, just check for link up at the end */ | |
4242 | } else if (tp->link_config.autoneg == AUTONEG_ENABLE) { | |
4243 | u32 adv, new_adv; | |
4244 | ||
4245 | err |= tg3_readphy(tp, MII_ADVERTISE, &adv); | |
4246 | new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF | | |
4247 | ADVERTISE_1000XPAUSE | | |
4248 | ADVERTISE_1000XPSE_ASYM | | |
4249 | ADVERTISE_SLCT); | |
4250 | ||
4251 | new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); | |
4252 | ||
4253 | if (tp->link_config.advertising & ADVERTISED_1000baseT_Half) | |
4254 | new_adv |= ADVERTISE_1000XHALF; | |
4255 | if (tp->link_config.advertising & ADVERTISED_1000baseT_Full) | |
4256 | new_adv |= ADVERTISE_1000XFULL; | |
4257 | ||
4258 | if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) { | |
4259 | tg3_writephy(tp, MII_ADVERTISE, new_adv); | |
4260 | bmcr |= BMCR_ANENABLE | BMCR_ANRESTART; | |
4261 | tg3_writephy(tp, MII_BMCR, bmcr); | |
4262 | ||
4263 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
4264 | tp->serdes_counter = SERDES_AN_TIMEOUT_5714S; | |
4265 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; | |
4266 | ||
4267 | return err; | |
4268 | } | |
4269 | } else { | |
4270 | u32 new_bmcr; | |
4271 | ||
4272 | bmcr &= ~BMCR_SPEED1000; | |
4273 | new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX); | |
4274 | ||
4275 | if (tp->link_config.duplex == DUPLEX_FULL) | |
4276 | new_bmcr |= BMCR_FULLDPLX; | |
4277 | ||
4278 | if (new_bmcr != bmcr) { | |
4279 | /* BMCR_SPEED1000 is a reserved bit that needs | |
4280 | * to be set on write. | |
4281 | */ | |
4282 | new_bmcr |= BMCR_SPEED1000; | |
4283 | ||
4284 | /* Force a linkdown */ | |
4285 | if (netif_carrier_ok(tp->dev)) { | |
4286 | u32 adv; | |
4287 | ||
4288 | err |= tg3_readphy(tp, MII_ADVERTISE, &adv); | |
4289 | adv &= ~(ADVERTISE_1000XFULL | | |
4290 | ADVERTISE_1000XHALF | | |
4291 | ADVERTISE_SLCT); | |
4292 | tg3_writephy(tp, MII_ADVERTISE, adv); | |
4293 | tg3_writephy(tp, MII_BMCR, bmcr | | |
4294 | BMCR_ANRESTART | | |
4295 | BMCR_ANENABLE); | |
4296 | udelay(10); | |
4297 | netif_carrier_off(tp->dev); | |
4298 | } | |
4299 | tg3_writephy(tp, MII_BMCR, new_bmcr); | |
4300 | bmcr = new_bmcr; | |
4301 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
4302 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
4303 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == | |
4304 | ASIC_REV_5714) { | |
4305 | if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) | |
4306 | bmsr |= BMSR_LSTATUS; | |
4307 | else | |
4308 | bmsr &= ~BMSR_LSTATUS; | |
4309 | } | |
4310 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; | |
4311 | } | |
4312 | } | |
4313 | ||
4314 | if (bmsr & BMSR_LSTATUS) { | |
4315 | current_speed = SPEED_1000; | |
4316 | current_link_up = 1; | |
4317 | if (bmcr & BMCR_FULLDPLX) | |
4318 | current_duplex = DUPLEX_FULL; | |
4319 | else | |
4320 | current_duplex = DUPLEX_HALF; | |
4321 | ||
4322 | local_adv = 0; | |
4323 | remote_adv = 0; | |
4324 | ||
4325 | if (bmcr & BMCR_ANENABLE) { | |
4326 | u32 common; | |
4327 | ||
4328 | err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv); | |
4329 | err |= tg3_readphy(tp, MII_LPA, &remote_adv); | |
4330 | common = local_adv & remote_adv; | |
4331 | if (common & (ADVERTISE_1000XHALF | | |
4332 | ADVERTISE_1000XFULL)) { | |
4333 | if (common & ADVERTISE_1000XFULL) | |
4334 | current_duplex = DUPLEX_FULL; | |
4335 | else | |
4336 | current_duplex = DUPLEX_HALF; | |
4337 | } else if (!tg3_flag(tp, 5780_CLASS)) { | |
4338 | /* Link is up via parallel detect */ | |
4339 | } else { | |
4340 | current_link_up = 0; | |
4341 | } | |
4342 | } | |
4343 | } | |
4344 | ||
4345 | if (current_link_up == 1 && current_duplex == DUPLEX_FULL) | |
4346 | tg3_setup_flow_control(tp, local_adv, remote_adv); | |
4347 | ||
4348 | tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; | |
4349 | if (tp->link_config.active_duplex == DUPLEX_HALF) | |
4350 | tp->mac_mode |= MAC_MODE_HALF_DUPLEX; | |
4351 | ||
4352 | tw32_f(MAC_MODE, tp->mac_mode); | |
4353 | udelay(40); | |
4354 | ||
4355 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
4356 | ||
4357 | tp->link_config.active_speed = current_speed; | |
4358 | tp->link_config.active_duplex = current_duplex; | |
4359 | ||
4360 | if (current_link_up != netif_carrier_ok(tp->dev)) { | |
4361 | if (current_link_up) | |
4362 | netif_carrier_on(tp->dev); | |
4363 | else { | |
4364 | netif_carrier_off(tp->dev); | |
4365 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; | |
4366 | } | |
4367 | tg3_link_report(tp); | |
4368 | } | |
4369 | return err; | |
4370 | } | |
4371 | ||
4372 | static void tg3_serdes_parallel_detect(struct tg3 *tp) | |
4373 | { | |
4374 | if (tp->serdes_counter) { | |
4375 | /* Give autoneg time to complete. */ | |
4376 | tp->serdes_counter--; | |
4377 | return; | |
4378 | } | |
4379 | ||
4380 | if (!netif_carrier_ok(tp->dev) && | |
4381 | (tp->link_config.autoneg == AUTONEG_ENABLE)) { | |
4382 | u32 bmcr; | |
4383 | ||
4384 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
4385 | if (bmcr & BMCR_ANENABLE) { | |
4386 | u32 phy1, phy2; | |
4387 | ||
4388 | /* Select shadow register 0x1f */ | |
4389 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00); | |
4390 | tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1); | |
4391 | ||
4392 | /* Select expansion interrupt status register */ | |
4393 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, | |
4394 | MII_TG3_DSP_EXP1_INT_STAT); | |
4395 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2); | |
4396 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2); | |
4397 | ||
4398 | if ((phy1 & 0x10) && !(phy2 & 0x20)) { | |
4399 | /* We have signal detect and not receiving | |
4400 | * config code words, link is up by parallel | |
4401 | * detection. | |
4402 | */ | |
4403 | ||
4404 | bmcr &= ~BMCR_ANENABLE; | |
4405 | bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX; | |
4406 | tg3_writephy(tp, MII_BMCR, bmcr); | |
4407 | tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT; | |
4408 | } | |
4409 | } | |
4410 | } else if (netif_carrier_ok(tp->dev) && | |
4411 | (tp->link_config.autoneg == AUTONEG_ENABLE) && | |
4412 | (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) { | |
4413 | u32 phy2; | |
4414 | ||
4415 | /* Select expansion interrupt status register */ | |
4416 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, | |
4417 | MII_TG3_DSP_EXP1_INT_STAT); | |
4418 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2); | |
4419 | if (phy2 & 0x20) { | |
4420 | u32 bmcr; | |
4421 | ||
4422 | /* Config code words received, turn on autoneg. */ | |
4423 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
4424 | tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE); | |
4425 | ||
4426 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; | |
4427 | ||
4428 | } | |
4429 | } | |
4430 | } | |
4431 | ||
4432 | static int tg3_setup_phy(struct tg3 *tp, int force_reset) | |
4433 | { | |
4434 | u32 val; | |
4435 | int err; | |
4436 | ||
4437 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) | |
4438 | err = tg3_setup_fiber_phy(tp, force_reset); | |
4439 | else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) | |
4440 | err = tg3_setup_fiber_mii_phy(tp, force_reset); | |
4441 | else | |
4442 | err = tg3_setup_copper_phy(tp, force_reset); | |
4443 | ||
4444 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) { | |
4445 | u32 scale; | |
4446 | ||
4447 | val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK; | |
4448 | if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5) | |
4449 | scale = 65; | |
4450 | else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25) | |
4451 | scale = 6; | |
4452 | else | |
4453 | scale = 12; | |
4454 | ||
4455 | val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK; | |
4456 | val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT); | |
4457 | tw32(GRC_MISC_CFG, val); | |
4458 | } | |
4459 | ||
4460 | val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) | | |
4461 | (6 << TX_LENGTHS_IPG_SHIFT); | |
4462 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) | |
4463 | val |= tr32(MAC_TX_LENGTHS) & | |
4464 | (TX_LENGTHS_JMB_FRM_LEN_MSK | | |
4465 | TX_LENGTHS_CNT_DWN_VAL_MSK); | |
4466 | ||
4467 | if (tp->link_config.active_speed == SPEED_1000 && | |
4468 | tp->link_config.active_duplex == DUPLEX_HALF) | |
4469 | tw32(MAC_TX_LENGTHS, val | | |
4470 | (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)); | |
4471 | else | |
4472 | tw32(MAC_TX_LENGTHS, val | | |
4473 | (32 << TX_LENGTHS_SLOT_TIME_SHIFT)); | |
4474 | ||
4475 | if (!tg3_flag(tp, 5705_PLUS)) { | |
4476 | if (netif_carrier_ok(tp->dev)) { | |
4477 | tw32(HOSTCC_STAT_COAL_TICKS, | |
4478 | tp->coal.stats_block_coalesce_usecs); | |
4479 | } else { | |
4480 | tw32(HOSTCC_STAT_COAL_TICKS, 0); | |
4481 | } | |
4482 | } | |
4483 | ||
4484 | if (tg3_flag(tp, ASPM_WORKAROUND)) { | |
4485 | val = tr32(PCIE_PWR_MGMT_THRESH); | |
4486 | if (!netif_carrier_ok(tp->dev)) | |
4487 | val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) | | |
4488 | tp->pwrmgmt_thresh; | |
4489 | else | |
4490 | val |= PCIE_PWR_MGMT_L1_THRESH_MSK; | |
4491 | tw32(PCIE_PWR_MGMT_THRESH, val); | |
4492 | } | |
4493 | ||
4494 | return err; | |
4495 | } | |
4496 | ||
4497 | static inline int tg3_irq_sync(struct tg3 *tp) | |
4498 | { | |
4499 | return tp->irq_sync; | |
4500 | } | |
4501 | ||
4502 | static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len) | |
4503 | { | |
4504 | int i; | |
4505 | ||
4506 | dst = (u32 *)((u8 *)dst + off); | |
4507 | for (i = 0; i < len; i += sizeof(u32)) | |
4508 | *dst++ = tr32(off + i); | |
4509 | } | |
4510 | ||
4511 | static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs) | |
4512 | { | |
4513 | tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0); | |
4514 | tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200); | |
4515 | tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0); | |
4516 | tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0); | |
4517 | tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04); | |
4518 | tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80); | |
4519 | tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48); | |
4520 | tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04); | |
4521 | tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20); | |
4522 | tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c); | |
4523 | tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c); | |
4524 | tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c); | |
4525 | tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44); | |
4526 | tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04); | |
4527 | tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20); | |
4528 | tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14); | |
4529 | tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08); | |
4530 | tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08); | |
4531 | tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100); | |
4532 | ||
4533 | if (tg3_flag(tp, SUPPORT_MSIX)) | |
4534 | tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180); | |
4535 | ||
4536 | tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10); | |
4537 | tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58); | |
4538 | tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08); | |
4539 | tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08); | |
4540 | tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04); | |
4541 | tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04); | |
4542 | tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04); | |
4543 | tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04); | |
4544 | ||
4545 | if (!tg3_flag(tp, 5705_PLUS)) { | |
4546 | tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04); | |
4547 | tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04); | |
4548 | tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04); | |
4549 | } | |
4550 | ||
4551 | tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110); | |
4552 | tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120); | |
4553 | tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c); | |
4554 | tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04); | |
4555 | tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c); | |
4556 | ||
4557 | if (tg3_flag(tp, NVRAM)) | |
4558 | tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24); | |
4559 | } | |
4560 | ||
4561 | static void tg3_dump_state(struct tg3 *tp) | |
4562 | { | |
4563 | int i; | |
4564 | u32 *regs; | |
4565 | ||
4566 | regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC); | |
4567 | if (!regs) { | |
4568 | netdev_err(tp->dev, "Failed allocating register dump buffer\n"); | |
4569 | return; | |
4570 | } | |
4571 | ||
4572 | if (tg3_flag(tp, PCI_EXPRESS)) { | |
4573 | /* Read up to but not including private PCI registers */ | |
4574 | for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32)) | |
4575 | regs[i / sizeof(u32)] = tr32(i); | |
4576 | } else | |
4577 | tg3_dump_legacy_regs(tp, regs); | |
4578 | ||
4579 | for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) { | |
4580 | if (!regs[i + 0] && !regs[i + 1] && | |
4581 | !regs[i + 2] && !regs[i + 3]) | |
4582 | continue; | |
4583 | ||
4584 | netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n", | |
4585 | i * 4, | |
4586 | regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]); | |
4587 | } | |
4588 | ||
4589 | kfree(regs); | |
4590 | ||
4591 | for (i = 0; i < tp->irq_cnt; i++) { | |
4592 | struct tg3_napi *tnapi = &tp->napi[i]; | |
4593 | ||
4594 | /* SW status block */ | |
4595 | netdev_err(tp->dev, | |
4596 | "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n", | |
4597 | i, | |
4598 | tnapi->hw_status->status, | |
4599 | tnapi->hw_status->status_tag, | |
4600 | tnapi->hw_status->rx_jumbo_consumer, | |
4601 | tnapi->hw_status->rx_consumer, | |
4602 | tnapi->hw_status->rx_mini_consumer, | |
4603 | tnapi->hw_status->idx[0].rx_producer, | |
4604 | tnapi->hw_status->idx[0].tx_consumer); | |
4605 | ||
4606 | netdev_err(tp->dev, | |
4607 | "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n", | |
4608 | i, | |
4609 | tnapi->last_tag, tnapi->last_irq_tag, | |
4610 | tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending, | |
4611 | tnapi->rx_rcb_ptr, | |
4612 | tnapi->prodring.rx_std_prod_idx, | |
4613 | tnapi->prodring.rx_std_cons_idx, | |
4614 | tnapi->prodring.rx_jmb_prod_idx, | |
4615 | tnapi->prodring.rx_jmb_cons_idx); | |
4616 | } | |
4617 | } | |
4618 | ||
4619 | /* This is called whenever we suspect that the system chipset is re- | |
4620 | * ordering the sequence of MMIO to the tx send mailbox. The symptom | |
4621 | * is bogus tx completions. We try to recover by setting the | |
4622 | * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later | |
4623 | * in the workqueue. | |
4624 | */ | |
4625 | static void tg3_tx_recover(struct tg3 *tp) | |
4626 | { | |
4627 | BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) || | |
4628 | tp->write32_tx_mbox == tg3_write_indirect_mbox); | |
4629 | ||
4630 | netdev_warn(tp->dev, | |
4631 | "The system may be re-ordering memory-mapped I/O " | |
4632 | "cycles to the network device, attempting to recover. " | |
4633 | "Please report the problem to the driver maintainer " | |
4634 | "and include system chipset information.\n"); | |
4635 | ||
4636 | spin_lock(&tp->lock); | |
4637 | tg3_flag_set(tp, TX_RECOVERY_PENDING); | |
4638 | spin_unlock(&tp->lock); | |
4639 | } | |
4640 | ||
4641 | static inline u32 tg3_tx_avail(struct tg3_napi *tnapi) | |
4642 | { | |
4643 | /* Tell compiler to fetch tx indices from memory. */ | |
4644 | barrier(); | |
4645 | return tnapi->tx_pending - | |
4646 | ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1)); | |
4647 | } | |
4648 | ||
4649 | /* Tigon3 never reports partial packet sends. So we do not | |
4650 | * need special logic to handle SKBs that have not had all | |
4651 | * of their frags sent yet, like SunGEM does. | |
4652 | */ | |
4653 | static void tg3_tx(struct tg3_napi *tnapi) | |
4654 | { | |
4655 | struct tg3 *tp = tnapi->tp; | |
4656 | u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer; | |
4657 | u32 sw_idx = tnapi->tx_cons; | |
4658 | struct netdev_queue *txq; | |
4659 | int index = tnapi - tp->napi; | |
4660 | ||
4661 | if (tg3_flag(tp, ENABLE_TSS)) | |
4662 | index--; | |
4663 | ||
4664 | txq = netdev_get_tx_queue(tp->dev, index); | |
4665 | ||
4666 | while (sw_idx != hw_idx) { | |
4667 | struct ring_info *ri = &tnapi->tx_buffers[sw_idx]; | |
4668 | struct sk_buff *skb = ri->skb; | |
4669 | int i, tx_bug = 0; | |
4670 | ||
4671 | if (unlikely(skb == NULL)) { | |
4672 | tg3_tx_recover(tp); | |
4673 | return; | |
4674 | } | |
4675 | ||
4676 | pci_unmap_single(tp->pdev, | |
4677 | dma_unmap_addr(ri, mapping), | |
4678 | skb_headlen(skb), | |
4679 | PCI_DMA_TODEVICE); | |
4680 | ||
4681 | ri->skb = NULL; | |
4682 | ||
4683 | sw_idx = NEXT_TX(sw_idx); | |
4684 | ||
4685 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
4686 | ri = &tnapi->tx_buffers[sw_idx]; | |
4687 | if (unlikely(ri->skb != NULL || sw_idx == hw_idx)) | |
4688 | tx_bug = 1; | |
4689 | ||
4690 | pci_unmap_page(tp->pdev, | |
4691 | dma_unmap_addr(ri, mapping), | |
4692 | skb_shinfo(skb)->frags[i].size, | |
4693 | PCI_DMA_TODEVICE); | |
4694 | sw_idx = NEXT_TX(sw_idx); | |
4695 | } | |
4696 | ||
4697 | dev_kfree_skb(skb); | |
4698 | ||
4699 | if (unlikely(tx_bug)) { | |
4700 | tg3_tx_recover(tp); | |
4701 | return; | |
4702 | } | |
4703 | } | |
4704 | ||
4705 | tnapi->tx_cons = sw_idx; | |
4706 | ||
4707 | /* Need to make the tx_cons update visible to tg3_start_xmit() | |
4708 | * before checking for netif_queue_stopped(). Without the | |
4709 | * memory barrier, there is a small possibility that tg3_start_xmit() | |
4710 | * will miss it and cause the queue to be stopped forever. | |
4711 | */ | |
4712 | smp_mb(); | |
4713 | ||
4714 | if (unlikely(netif_tx_queue_stopped(txq) && | |
4715 | (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) { | |
4716 | __netif_tx_lock(txq, smp_processor_id()); | |
4717 | if (netif_tx_queue_stopped(txq) && | |
4718 | (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))) | |
4719 | netif_tx_wake_queue(txq); | |
4720 | __netif_tx_unlock(txq); | |
4721 | } | |
4722 | } | |
4723 | ||
4724 | static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz) | |
4725 | { | |
4726 | if (!ri->skb) | |
4727 | return; | |
4728 | ||
4729 | pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping), | |
4730 | map_sz, PCI_DMA_FROMDEVICE); | |
4731 | dev_kfree_skb_any(ri->skb); | |
4732 | ri->skb = NULL; | |
4733 | } | |
4734 | ||
4735 | /* Returns size of skb allocated or < 0 on error. | |
4736 | * | |
4737 | * We only need to fill in the address because the other members | |
4738 | * of the RX descriptor are invariant, see tg3_init_rings. | |
4739 | * | |
4740 | * Note the purposeful assymetry of cpu vs. chip accesses. For | |
4741 | * posting buffers we only dirty the first cache line of the RX | |
4742 | * descriptor (containing the address). Whereas for the RX status | |
4743 | * buffers the cpu only reads the last cacheline of the RX descriptor | |
4744 | * (to fetch the error flags, vlan tag, checksum, and opaque cookie). | |
4745 | */ | |
4746 | static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr, | |
4747 | u32 opaque_key, u32 dest_idx_unmasked) | |
4748 | { | |
4749 | struct tg3_rx_buffer_desc *desc; | |
4750 | struct ring_info *map; | |
4751 | struct sk_buff *skb; | |
4752 | dma_addr_t mapping; | |
4753 | int skb_size, dest_idx; | |
4754 | ||
4755 | switch (opaque_key) { | |
4756 | case RXD_OPAQUE_RING_STD: | |
4757 | dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask; | |
4758 | desc = &tpr->rx_std[dest_idx]; | |
4759 | map = &tpr->rx_std_buffers[dest_idx]; | |
4760 | skb_size = tp->rx_pkt_map_sz; | |
4761 | break; | |
4762 | ||
4763 | case RXD_OPAQUE_RING_JUMBO: | |
4764 | dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask; | |
4765 | desc = &tpr->rx_jmb[dest_idx].std; | |
4766 | map = &tpr->rx_jmb_buffers[dest_idx]; | |
4767 | skb_size = TG3_RX_JMB_MAP_SZ; | |
4768 | break; | |
4769 | ||
4770 | default: | |
4771 | return -EINVAL; | |
4772 | } | |
4773 | ||
4774 | /* Do not overwrite any of the map or rp information | |
4775 | * until we are sure we can commit to a new buffer. | |
4776 | * | |
4777 | * Callers depend upon this behavior and assume that | |
4778 | * we leave everything unchanged if we fail. | |
4779 | */ | |
4780 | skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset); | |
4781 | if (skb == NULL) | |
4782 | return -ENOMEM; | |
4783 | ||
4784 | skb_reserve(skb, tp->rx_offset); | |
4785 | ||
4786 | mapping = pci_map_single(tp->pdev, skb->data, skb_size, | |
4787 | PCI_DMA_FROMDEVICE); | |
4788 | if (pci_dma_mapping_error(tp->pdev, mapping)) { | |
4789 | dev_kfree_skb(skb); | |
4790 | return -EIO; | |
4791 | } | |
4792 | ||
4793 | map->skb = skb; | |
4794 | dma_unmap_addr_set(map, mapping, mapping); | |
4795 | ||
4796 | desc->addr_hi = ((u64)mapping >> 32); | |
4797 | desc->addr_lo = ((u64)mapping & 0xffffffff); | |
4798 | ||
4799 | return skb_size; | |
4800 | } | |
4801 | ||
4802 | /* We only need to move over in the address because the other | |
4803 | * members of the RX descriptor are invariant. See notes above | |
4804 | * tg3_alloc_rx_skb for full details. | |
4805 | */ | |
4806 | static void tg3_recycle_rx(struct tg3_napi *tnapi, | |
4807 | struct tg3_rx_prodring_set *dpr, | |
4808 | u32 opaque_key, int src_idx, | |
4809 | u32 dest_idx_unmasked) | |
4810 | { | |
4811 | struct tg3 *tp = tnapi->tp; | |
4812 | struct tg3_rx_buffer_desc *src_desc, *dest_desc; | |
4813 | struct ring_info *src_map, *dest_map; | |
4814 | struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring; | |
4815 | int dest_idx; | |
4816 | ||
4817 | switch (opaque_key) { | |
4818 | case RXD_OPAQUE_RING_STD: | |
4819 | dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask; | |
4820 | dest_desc = &dpr->rx_std[dest_idx]; | |
4821 | dest_map = &dpr->rx_std_buffers[dest_idx]; | |
4822 | src_desc = &spr->rx_std[src_idx]; | |
4823 | src_map = &spr->rx_std_buffers[src_idx]; | |
4824 | break; | |
4825 | ||
4826 | case RXD_OPAQUE_RING_JUMBO: | |
4827 | dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask; | |
4828 | dest_desc = &dpr->rx_jmb[dest_idx].std; | |
4829 | dest_map = &dpr->rx_jmb_buffers[dest_idx]; | |
4830 | src_desc = &spr->rx_jmb[src_idx].std; | |
4831 | src_map = &spr->rx_jmb_buffers[src_idx]; | |
4832 | break; | |
4833 | ||
4834 | default: | |
4835 | return; | |
4836 | } | |
4837 | ||
4838 | dest_map->skb = src_map->skb; | |
4839 | dma_unmap_addr_set(dest_map, mapping, | |
4840 | dma_unmap_addr(src_map, mapping)); | |
4841 | dest_desc->addr_hi = src_desc->addr_hi; | |
4842 | dest_desc->addr_lo = src_desc->addr_lo; | |
4843 | ||
4844 | /* Ensure that the update to the skb happens after the physical | |
4845 | * addresses have been transferred to the new BD location. | |
4846 | */ | |
4847 | smp_wmb(); | |
4848 | ||
4849 | src_map->skb = NULL; | |
4850 | } | |
4851 | ||
4852 | /* The RX ring scheme is composed of multiple rings which post fresh | |
4853 | * buffers to the chip, and one special ring the chip uses to report | |
4854 | * status back to the host. | |
4855 | * | |
4856 | * The special ring reports the status of received packets to the | |
4857 | * host. The chip does not write into the original descriptor the | |
4858 | * RX buffer was obtained from. The chip simply takes the original | |
4859 | * descriptor as provided by the host, updates the status and length | |
4860 | * field, then writes this into the next status ring entry. | |
4861 | * | |
4862 | * Each ring the host uses to post buffers to the chip is described | |
4863 | * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives, | |
4864 | * it is first placed into the on-chip ram. When the packet's length | |
4865 | * is known, it walks down the TG3_BDINFO entries to select the ring. | |
4866 | * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO | |
4867 | * which is within the range of the new packet's length is chosen. | |
4868 | * | |
4869 | * The "separate ring for rx status" scheme may sound queer, but it makes | |
4870 | * sense from a cache coherency perspective. If only the host writes | |
4871 | * to the buffer post rings, and only the chip writes to the rx status | |
4872 | * rings, then cache lines never move beyond shared-modified state. | |
4873 | * If both the host and chip were to write into the same ring, cache line | |
4874 | * eviction could occur since both entities want it in an exclusive state. | |
4875 | */ | |
4876 | static int tg3_rx(struct tg3_napi *tnapi, int budget) | |
4877 | { | |
4878 | struct tg3 *tp = tnapi->tp; | |
4879 | u32 work_mask, rx_std_posted = 0; | |
4880 | u32 std_prod_idx, jmb_prod_idx; | |
4881 | u32 sw_idx = tnapi->rx_rcb_ptr; | |
4882 | u16 hw_idx; | |
4883 | int received; | |
4884 | struct tg3_rx_prodring_set *tpr = &tnapi->prodring; | |
4885 | ||
4886 | hw_idx = *(tnapi->rx_rcb_prod_idx); | |
4887 | /* | |
4888 | * We need to order the read of hw_idx and the read of | |
4889 | * the opaque cookie. | |
4890 | */ | |
4891 | rmb(); | |
4892 | work_mask = 0; | |
4893 | received = 0; | |
4894 | std_prod_idx = tpr->rx_std_prod_idx; | |
4895 | jmb_prod_idx = tpr->rx_jmb_prod_idx; | |
4896 | while (sw_idx != hw_idx && budget > 0) { | |
4897 | struct ring_info *ri; | |
4898 | struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx]; | |
4899 | unsigned int len; | |
4900 | struct sk_buff *skb; | |
4901 | dma_addr_t dma_addr; | |
4902 | u32 opaque_key, desc_idx, *post_ptr; | |
4903 | ||
4904 | desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK; | |
4905 | opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK; | |
4906 | if (opaque_key == RXD_OPAQUE_RING_STD) { | |
4907 | ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx]; | |
4908 | dma_addr = dma_unmap_addr(ri, mapping); | |
4909 | skb = ri->skb; | |
4910 | post_ptr = &std_prod_idx; | |
4911 | rx_std_posted++; | |
4912 | } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) { | |
4913 | ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx]; | |
4914 | dma_addr = dma_unmap_addr(ri, mapping); | |
4915 | skb = ri->skb; | |
4916 | post_ptr = &jmb_prod_idx; | |
4917 | } else | |
4918 | goto next_pkt_nopost; | |
4919 | ||
4920 | work_mask |= opaque_key; | |
4921 | ||
4922 | if ((desc->err_vlan & RXD_ERR_MASK) != 0 && | |
4923 | (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) { | |
4924 | drop_it: | |
4925 | tg3_recycle_rx(tnapi, tpr, opaque_key, | |
4926 | desc_idx, *post_ptr); | |
4927 | drop_it_no_recycle: | |
4928 | /* Other statistics kept track of by card. */ | |
4929 | tp->rx_dropped++; | |
4930 | goto next_pkt; | |
4931 | } | |
4932 | ||
4933 | len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - | |
4934 | ETH_FCS_LEN; | |
4935 | ||
4936 | if (len > TG3_RX_COPY_THRESH(tp)) { | |
4937 | int skb_size; | |
4938 | ||
4939 | skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key, | |
4940 | *post_ptr); | |
4941 | if (skb_size < 0) | |
4942 | goto drop_it; | |
4943 | ||
4944 | pci_unmap_single(tp->pdev, dma_addr, skb_size, | |
4945 | PCI_DMA_FROMDEVICE); | |
4946 | ||
4947 | /* Ensure that the update to the skb happens | |
4948 | * after the usage of the old DMA mapping. | |
4949 | */ | |
4950 | smp_wmb(); | |
4951 | ||
4952 | ri->skb = NULL; | |
4953 | ||
4954 | skb_put(skb, len); | |
4955 | } else { | |
4956 | struct sk_buff *copy_skb; | |
4957 | ||
4958 | tg3_recycle_rx(tnapi, tpr, opaque_key, | |
4959 | desc_idx, *post_ptr); | |
4960 | ||
4961 | copy_skb = netdev_alloc_skb(tp->dev, len + | |
4962 | TG3_RAW_IP_ALIGN); | |
4963 | if (copy_skb == NULL) | |
4964 | goto drop_it_no_recycle; | |
4965 | ||
4966 | skb_reserve(copy_skb, TG3_RAW_IP_ALIGN); | |
4967 | skb_put(copy_skb, len); | |
4968 | pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); | |
4969 | skb_copy_from_linear_data(skb, copy_skb->data, len); | |
4970 | pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); | |
4971 | ||
4972 | /* We'll reuse the original ring buffer. */ | |
4973 | skb = copy_skb; | |
4974 | } | |
4975 | ||
4976 | if ((tp->dev->features & NETIF_F_RXCSUM) && | |
4977 | (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) && | |
4978 | (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK) | |
4979 | >> RXD_TCPCSUM_SHIFT) == 0xffff)) | |
4980 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
4981 | else | |
4982 | skb_checksum_none_assert(skb); | |
4983 | ||
4984 | skb->protocol = eth_type_trans(skb, tp->dev); | |
4985 | ||
4986 | if (len > (tp->dev->mtu + ETH_HLEN) && | |
4987 | skb->protocol != htons(ETH_P_8021Q)) { | |
4988 | dev_kfree_skb(skb); | |
4989 | goto drop_it_no_recycle; | |
4990 | } | |
4991 | ||
4992 | if (desc->type_flags & RXD_FLAG_VLAN && | |
4993 | !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) | |
4994 | __vlan_hwaccel_put_tag(skb, | |
4995 | desc->err_vlan & RXD_VLAN_MASK); | |
4996 | ||
4997 | napi_gro_receive(&tnapi->napi, skb); | |
4998 | ||
4999 | received++; | |
5000 | budget--; | |
5001 | ||
5002 | next_pkt: | |
5003 | (*post_ptr)++; | |
5004 | ||
5005 | if (unlikely(rx_std_posted >= tp->rx_std_max_post)) { | |
5006 | tpr->rx_std_prod_idx = std_prod_idx & | |
5007 | tp->rx_std_ring_mask; | |
5008 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, | |
5009 | tpr->rx_std_prod_idx); | |
5010 | work_mask &= ~RXD_OPAQUE_RING_STD; | |
5011 | rx_std_posted = 0; | |
5012 | } | |
5013 | next_pkt_nopost: | |
5014 | sw_idx++; | |
5015 | sw_idx &= tp->rx_ret_ring_mask; | |
5016 | ||
5017 | /* Refresh hw_idx to see if there is new work */ | |
5018 | if (sw_idx == hw_idx) { | |
5019 | hw_idx = *(tnapi->rx_rcb_prod_idx); | |
5020 | rmb(); | |
5021 | } | |
5022 | } | |
5023 | ||
5024 | /* ACK the status ring. */ | |
5025 | tnapi->rx_rcb_ptr = sw_idx; | |
5026 | tw32_rx_mbox(tnapi->consmbox, sw_idx); | |
5027 | ||
5028 | /* Refill RX ring(s). */ | |
5029 | if (!tg3_flag(tp, ENABLE_RSS)) { | |
5030 | if (work_mask & RXD_OPAQUE_RING_STD) { | |
5031 | tpr->rx_std_prod_idx = std_prod_idx & | |
5032 | tp->rx_std_ring_mask; | |
5033 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, | |
5034 | tpr->rx_std_prod_idx); | |
5035 | } | |
5036 | if (work_mask & RXD_OPAQUE_RING_JUMBO) { | |
5037 | tpr->rx_jmb_prod_idx = jmb_prod_idx & | |
5038 | tp->rx_jmb_ring_mask; | |
5039 | tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, | |
5040 | tpr->rx_jmb_prod_idx); | |
5041 | } | |
5042 | mmiowb(); | |
5043 | } else if (work_mask) { | |
5044 | /* rx_std_buffers[] and rx_jmb_buffers[] entries must be | |
5045 | * updated before the producer indices can be updated. | |
5046 | */ | |
5047 | smp_wmb(); | |
5048 | ||
5049 | tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask; | |
5050 | tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask; | |
5051 | ||
5052 | if (tnapi != &tp->napi[1]) | |
5053 | napi_schedule(&tp->napi[1].napi); | |
5054 | } | |
5055 | ||
5056 | return received; | |
5057 | } | |
5058 | ||
5059 | static void tg3_poll_link(struct tg3 *tp) | |
5060 | { | |
5061 | /* handle link change and other phy events */ | |
5062 | if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) { | |
5063 | struct tg3_hw_status *sblk = tp->napi[0].hw_status; | |
5064 | ||
5065 | if (sblk->status & SD_STATUS_LINK_CHG) { | |
5066 | sblk->status = SD_STATUS_UPDATED | | |
5067 | (sblk->status & ~SD_STATUS_LINK_CHG); | |
5068 | spin_lock(&tp->lock); | |
5069 | if (tg3_flag(tp, USE_PHYLIB)) { | |
5070 | tw32_f(MAC_STATUS, | |
5071 | (MAC_STATUS_SYNC_CHANGED | | |
5072 | MAC_STATUS_CFG_CHANGED | | |
5073 | MAC_STATUS_MI_COMPLETION | | |
5074 | MAC_STATUS_LNKSTATE_CHANGED)); | |
5075 | udelay(40); | |
5076 | } else | |
5077 | tg3_setup_phy(tp, 0); | |
5078 | spin_unlock(&tp->lock); | |
5079 | } | |
5080 | } | |
5081 | } | |
5082 | ||
5083 | static int tg3_rx_prodring_xfer(struct tg3 *tp, | |
5084 | struct tg3_rx_prodring_set *dpr, | |
5085 | struct tg3_rx_prodring_set *spr) | |
5086 | { | |
5087 | u32 si, di, cpycnt, src_prod_idx; | |
5088 | int i, err = 0; | |
5089 | ||
5090 | while (1) { | |
5091 | src_prod_idx = spr->rx_std_prod_idx; | |
5092 | ||
5093 | /* Make sure updates to the rx_std_buffers[] entries and the | |
5094 | * standard producer index are seen in the correct order. | |
5095 | */ | |
5096 | smp_rmb(); | |
5097 | ||
5098 | if (spr->rx_std_cons_idx == src_prod_idx) | |
5099 | break; | |
5100 | ||
5101 | if (spr->rx_std_cons_idx < src_prod_idx) | |
5102 | cpycnt = src_prod_idx - spr->rx_std_cons_idx; | |
5103 | else | |
5104 | cpycnt = tp->rx_std_ring_mask + 1 - | |
5105 | spr->rx_std_cons_idx; | |
5106 | ||
5107 | cpycnt = min(cpycnt, | |
5108 | tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx); | |
5109 | ||
5110 | si = spr->rx_std_cons_idx; | |
5111 | di = dpr->rx_std_prod_idx; | |
5112 | ||
5113 | for (i = di; i < di + cpycnt; i++) { | |
5114 | if (dpr->rx_std_buffers[i].skb) { | |
5115 | cpycnt = i - di; | |
5116 | err = -ENOSPC; | |
5117 | break; | |
5118 | } | |
5119 | } | |
5120 | ||
5121 | if (!cpycnt) | |
5122 | break; | |
5123 | ||
5124 | /* Ensure that updates to the rx_std_buffers ring and the | |
5125 | * shadowed hardware producer ring from tg3_recycle_skb() are | |
5126 | * ordered correctly WRT the skb check above. | |
5127 | */ | |
5128 | smp_rmb(); | |
5129 | ||
5130 | memcpy(&dpr->rx_std_buffers[di], | |
5131 | &spr->rx_std_buffers[si], | |
5132 | cpycnt * sizeof(struct ring_info)); | |
5133 | ||
5134 | for (i = 0; i < cpycnt; i++, di++, si++) { | |
5135 | struct tg3_rx_buffer_desc *sbd, *dbd; | |
5136 | sbd = &spr->rx_std[si]; | |
5137 | dbd = &dpr->rx_std[di]; | |
5138 | dbd->addr_hi = sbd->addr_hi; | |
5139 | dbd->addr_lo = sbd->addr_lo; | |
5140 | } | |
5141 | ||
5142 | spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) & | |
5143 | tp->rx_std_ring_mask; | |
5144 | dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) & | |
5145 | tp->rx_std_ring_mask; | |
5146 | } | |
5147 | ||
5148 | while (1) { | |
5149 | src_prod_idx = spr->rx_jmb_prod_idx; | |
5150 | ||
5151 | /* Make sure updates to the rx_jmb_buffers[] entries and | |
5152 | * the jumbo producer index are seen in the correct order. | |
5153 | */ | |
5154 | smp_rmb(); | |
5155 | ||
5156 | if (spr->rx_jmb_cons_idx == src_prod_idx) | |
5157 | break; | |
5158 | ||
5159 | if (spr->rx_jmb_cons_idx < src_prod_idx) | |
5160 | cpycnt = src_prod_idx - spr->rx_jmb_cons_idx; | |
5161 | else | |
5162 | cpycnt = tp->rx_jmb_ring_mask + 1 - | |
5163 | spr->rx_jmb_cons_idx; | |
5164 | ||
5165 | cpycnt = min(cpycnt, | |
5166 | tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx); | |
5167 | ||
5168 | si = spr->rx_jmb_cons_idx; | |
5169 | di = dpr->rx_jmb_prod_idx; | |
5170 | ||
5171 | for (i = di; i < di + cpycnt; i++) { | |
5172 | if (dpr->rx_jmb_buffers[i].skb) { | |
5173 | cpycnt = i - di; | |
5174 | err = -ENOSPC; | |
5175 | break; | |
5176 | } | |
5177 | } | |
5178 | ||
5179 | if (!cpycnt) | |
5180 | break; | |
5181 | ||
5182 | /* Ensure that updates to the rx_jmb_buffers ring and the | |
5183 | * shadowed hardware producer ring from tg3_recycle_skb() are | |
5184 | * ordered correctly WRT the skb check above. | |
5185 | */ | |
5186 | smp_rmb(); | |
5187 | ||
5188 | memcpy(&dpr->rx_jmb_buffers[di], | |
5189 | &spr->rx_jmb_buffers[si], | |
5190 | cpycnt * sizeof(struct ring_info)); | |
5191 | ||
5192 | for (i = 0; i < cpycnt; i++, di++, si++) { | |
5193 | struct tg3_rx_buffer_desc *sbd, *dbd; | |
5194 | sbd = &spr->rx_jmb[si].std; | |
5195 | dbd = &dpr->rx_jmb[di].std; | |
5196 | dbd->addr_hi = sbd->addr_hi; | |
5197 | dbd->addr_lo = sbd->addr_lo; | |
5198 | } | |
5199 | ||
5200 | spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) & | |
5201 | tp->rx_jmb_ring_mask; | |
5202 | dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) & | |
5203 | tp->rx_jmb_ring_mask; | |
5204 | } | |
5205 | ||
5206 | return err; | |
5207 | } | |
5208 | ||
5209 | static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget) | |
5210 | { | |
5211 | struct tg3 *tp = tnapi->tp; | |
5212 | ||
5213 | /* run TX completion thread */ | |
5214 | if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) { | |
5215 | tg3_tx(tnapi); | |
5216 | if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING))) | |
5217 | return work_done; | |
5218 | } | |
5219 | ||
5220 | /* run RX thread, within the bounds set by NAPI. | |
5221 | * All RX "locking" is done by ensuring outside | |
5222 | * code synchronizes with tg3->napi.poll() | |
5223 | */ | |
5224 | if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr) | |
5225 | work_done += tg3_rx(tnapi, budget - work_done); | |
5226 | ||
5227 | if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) { | |
5228 | struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring; | |
5229 | int i, err = 0; | |
5230 | u32 std_prod_idx = dpr->rx_std_prod_idx; | |
5231 | u32 jmb_prod_idx = dpr->rx_jmb_prod_idx; | |
5232 | ||
5233 | for (i = 1; i < tp->irq_cnt; i++) | |
5234 | err |= tg3_rx_prodring_xfer(tp, dpr, | |
5235 | &tp->napi[i].prodring); | |
5236 | ||
5237 | wmb(); | |
5238 | ||
5239 | if (std_prod_idx != dpr->rx_std_prod_idx) | |
5240 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, | |
5241 | dpr->rx_std_prod_idx); | |
5242 | ||
5243 | if (jmb_prod_idx != dpr->rx_jmb_prod_idx) | |
5244 | tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, | |
5245 | dpr->rx_jmb_prod_idx); | |
5246 | ||
5247 | mmiowb(); | |
5248 | ||
5249 | if (err) | |
5250 | tw32_f(HOSTCC_MODE, tp->coal_now); | |
5251 | } | |
5252 | ||
5253 | return work_done; | |
5254 | } | |
5255 | ||
5256 | static int tg3_poll_msix(struct napi_struct *napi, int budget) | |
5257 | { | |
5258 | struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi); | |
5259 | struct tg3 *tp = tnapi->tp; | |
5260 | int work_done = 0; | |
5261 | struct tg3_hw_status *sblk = tnapi->hw_status; | |
5262 | ||
5263 | while (1) { | |
5264 | work_done = tg3_poll_work(tnapi, work_done, budget); | |
5265 | ||
5266 | if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING))) | |
5267 | goto tx_recovery; | |
5268 | ||
5269 | if (unlikely(work_done >= budget)) | |
5270 | break; | |
5271 | ||
5272 | /* tp->last_tag is used in tg3_int_reenable() below | |
5273 | * to tell the hw how much work has been processed, | |
5274 | * so we must read it before checking for more work. | |
5275 | */ | |
5276 | tnapi->last_tag = sblk->status_tag; | |
5277 | tnapi->last_irq_tag = tnapi->last_tag; | |
5278 | rmb(); | |
5279 | ||
5280 | /* check for RX/TX work to do */ | |
5281 | if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons && | |
5282 | *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) { | |
5283 | napi_complete(napi); | |
5284 | /* Reenable interrupts. */ | |
5285 | tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24); | |
5286 | mmiowb(); | |
5287 | break; | |
5288 | } | |
5289 | } | |
5290 | ||
5291 | return work_done; | |
5292 | ||
5293 | tx_recovery: | |
5294 | /* work_done is guaranteed to be less than budget. */ | |
5295 | napi_complete(napi); | |
5296 | schedule_work(&tp->reset_task); | |
5297 | return work_done; | |
5298 | } | |
5299 | ||
5300 | static void tg3_process_error(struct tg3 *tp) | |
5301 | { | |
5302 | u32 val; | |
5303 | bool real_error = false; | |
5304 | ||
5305 | if (tg3_flag(tp, ERROR_PROCESSED)) | |
5306 | return; | |
5307 | ||
5308 | /* Check Flow Attention register */ | |
5309 | val = tr32(HOSTCC_FLOW_ATTN); | |
5310 | if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) { | |
5311 | netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n"); | |
5312 | real_error = true; | |
5313 | } | |
5314 | ||
5315 | if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) { | |
5316 | netdev_err(tp->dev, "MSI Status error. Resetting chip.\n"); | |
5317 | real_error = true; | |
5318 | } | |
5319 | ||
5320 | if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) { | |
5321 | netdev_err(tp->dev, "DMA Status error. Resetting chip.\n"); | |
5322 | real_error = true; | |
5323 | } | |
5324 | ||
5325 | if (!real_error) | |
5326 | return; | |
5327 | ||
5328 | tg3_dump_state(tp); | |
5329 | ||
5330 | tg3_flag_set(tp, ERROR_PROCESSED); | |
5331 | schedule_work(&tp->reset_task); | |
5332 | } | |
5333 | ||
5334 | static int tg3_poll(struct napi_struct *napi, int budget) | |
5335 | { | |
5336 | struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi); | |
5337 | struct tg3 *tp = tnapi->tp; | |
5338 | int work_done = 0; | |
5339 | struct tg3_hw_status *sblk = tnapi->hw_status; | |
5340 | ||
5341 | while (1) { | |
5342 | if (sblk->status & SD_STATUS_ERROR) | |
5343 | tg3_process_error(tp); | |
5344 | ||
5345 | tg3_poll_link(tp); | |
5346 | ||
5347 | work_done = tg3_poll_work(tnapi, work_done, budget); | |
5348 | ||
5349 | if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING))) | |
5350 | goto tx_recovery; | |
5351 | ||
5352 | if (unlikely(work_done >= budget)) | |
5353 | break; | |
5354 | ||
5355 | if (tg3_flag(tp, TAGGED_STATUS)) { | |
5356 | /* tp->last_tag is used in tg3_int_reenable() below | |
5357 | * to tell the hw how much work has been processed, | |
5358 | * so we must read it before checking for more work. | |
5359 | */ | |
5360 | tnapi->last_tag = sblk->status_tag; | |
5361 | tnapi->last_irq_tag = tnapi->last_tag; | |
5362 | rmb(); | |
5363 | } else | |
5364 | sblk->status &= ~SD_STATUS_UPDATED; | |
5365 | ||
5366 | if (likely(!tg3_has_work(tnapi))) { | |
5367 | napi_complete(napi); | |
5368 | tg3_int_reenable(tnapi); | |
5369 | break; | |
5370 | } | |
5371 | } | |
5372 | ||
5373 | return work_done; | |
5374 | ||
5375 | tx_recovery: | |
5376 | /* work_done is guaranteed to be less than budget. */ | |
5377 | napi_complete(napi); | |
5378 | schedule_work(&tp->reset_task); | |
5379 | return work_done; | |
5380 | } | |
5381 | ||
5382 | static void tg3_napi_disable(struct tg3 *tp) | |
5383 | { | |
5384 | int i; | |
5385 | ||
5386 | for (i = tp->irq_cnt - 1; i >= 0; i--) | |
5387 | napi_disable(&tp->napi[i].napi); | |
5388 | } | |
5389 | ||
5390 | static void tg3_napi_enable(struct tg3 *tp) | |
5391 | { | |
5392 | int i; | |
5393 | ||
5394 | for (i = 0; i < tp->irq_cnt; i++) | |
5395 | napi_enable(&tp->napi[i].napi); | |
5396 | } | |
5397 | ||
5398 | static void tg3_napi_init(struct tg3 *tp) | |
5399 | { | |
5400 | int i; | |
5401 | ||
5402 | netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64); | |
5403 | for (i = 1; i < tp->irq_cnt; i++) | |
5404 | netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64); | |
5405 | } | |
5406 | ||
5407 | static void tg3_napi_fini(struct tg3 *tp) | |
5408 | { | |
5409 | int i; | |
5410 | ||
5411 | for (i = 0; i < tp->irq_cnt; i++) | |
5412 | netif_napi_del(&tp->napi[i].napi); | |
5413 | } | |
5414 | ||
5415 | static inline void tg3_netif_stop(struct tg3 *tp) | |
5416 | { | |
5417 | tp->dev->trans_start = jiffies; /* prevent tx timeout */ | |
5418 | tg3_napi_disable(tp); | |
5419 | netif_tx_disable(tp->dev); | |
5420 | } | |
5421 | ||
5422 | static inline void tg3_netif_start(struct tg3 *tp) | |
5423 | { | |
5424 | /* NOTE: unconditional netif_tx_wake_all_queues is only | |
5425 | * appropriate so long as all callers are assured to | |
5426 | * have free tx slots (such as after tg3_init_hw) | |
5427 | */ | |
5428 | netif_tx_wake_all_queues(tp->dev); | |
5429 | ||
5430 | tg3_napi_enable(tp); | |
5431 | tp->napi[0].hw_status->status |= SD_STATUS_UPDATED; | |
5432 | tg3_enable_ints(tp); | |
5433 | } | |
5434 | ||
5435 | static void tg3_irq_quiesce(struct tg3 *tp) | |
5436 | { | |
5437 | int i; | |
5438 | ||
5439 | BUG_ON(tp->irq_sync); | |
5440 | ||
5441 | tp->irq_sync = 1; | |
5442 | smp_mb(); | |
5443 | ||
5444 | for (i = 0; i < tp->irq_cnt; i++) | |
5445 | synchronize_irq(tp->napi[i].irq_vec); | |
5446 | } | |
5447 | ||
5448 | /* Fully shutdown all tg3 driver activity elsewhere in the system. | |
5449 | * If irq_sync is non-zero, then the IRQ handler must be synchronized | |
5450 | * with as well. Most of the time, this is not necessary except when | |
5451 | * shutting down the device. | |
5452 | */ | |
5453 | static inline void tg3_full_lock(struct tg3 *tp, int irq_sync) | |
5454 | { | |
5455 | spin_lock_bh(&tp->lock); | |
5456 | if (irq_sync) | |
5457 | tg3_irq_quiesce(tp); | |
5458 | } | |
5459 | ||
5460 | static inline void tg3_full_unlock(struct tg3 *tp) | |
5461 | { | |
5462 | spin_unlock_bh(&tp->lock); | |
5463 | } | |
5464 | ||
5465 | /* One-shot MSI handler - Chip automatically disables interrupt | |
5466 | * after sending MSI so driver doesn't have to do it. | |
5467 | */ | |
5468 | static irqreturn_t tg3_msi_1shot(int irq, void *dev_id) | |
5469 | { | |
5470 | struct tg3_napi *tnapi = dev_id; | |
5471 | struct tg3 *tp = tnapi->tp; | |
5472 | ||
5473 | prefetch(tnapi->hw_status); | |
5474 | if (tnapi->rx_rcb) | |
5475 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); | |
5476 | ||
5477 | if (likely(!tg3_irq_sync(tp))) | |
5478 | napi_schedule(&tnapi->napi); | |
5479 | ||
5480 | return IRQ_HANDLED; | |
5481 | } | |
5482 | ||
5483 | /* MSI ISR - No need to check for interrupt sharing and no need to | |
5484 | * flush status block and interrupt mailbox. PCI ordering rules | |
5485 | * guarantee that MSI will arrive after the status block. | |
5486 | */ | |
5487 | static irqreturn_t tg3_msi(int irq, void *dev_id) | |
5488 | { | |
5489 | struct tg3_napi *tnapi = dev_id; | |
5490 | struct tg3 *tp = tnapi->tp; | |
5491 | ||
5492 | prefetch(tnapi->hw_status); | |
5493 | if (tnapi->rx_rcb) | |
5494 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); | |
5495 | /* | |
5496 | * Writing any value to intr-mbox-0 clears PCI INTA# and | |
5497 | * chip-internal interrupt pending events. | |
5498 | * Writing non-zero to intr-mbox-0 additional tells the | |
5499 | * NIC to stop sending us irqs, engaging "in-intr-handler" | |
5500 | * event coalescing. | |
5501 | */ | |
5502 | tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); | |
5503 | if (likely(!tg3_irq_sync(tp))) | |
5504 | napi_schedule(&tnapi->napi); | |
5505 | ||
5506 | return IRQ_RETVAL(1); | |
5507 | } | |
5508 | ||
5509 | static irqreturn_t tg3_interrupt(int irq, void *dev_id) | |
5510 | { | |
5511 | struct tg3_napi *tnapi = dev_id; | |
5512 | struct tg3 *tp = tnapi->tp; | |
5513 | struct tg3_hw_status *sblk = tnapi->hw_status; | |
5514 | unsigned int handled = 1; | |
5515 | ||
5516 | /* In INTx mode, it is possible for the interrupt to arrive at | |
5517 | * the CPU before the status block posted prior to the interrupt. | |
5518 | * Reading the PCI State register will confirm whether the | |
5519 | * interrupt is ours and will flush the status block. | |
5520 | */ | |
5521 | if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) { | |
5522 | if (tg3_flag(tp, CHIP_RESETTING) || | |
5523 | (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { | |
5524 | handled = 0; | |
5525 | goto out; | |
5526 | } | |
5527 | } | |
5528 | ||
5529 | /* | |
5530 | * Writing any value to intr-mbox-0 clears PCI INTA# and | |
5531 | * chip-internal interrupt pending events. | |
5532 | * Writing non-zero to intr-mbox-0 additional tells the | |
5533 | * NIC to stop sending us irqs, engaging "in-intr-handler" | |
5534 | * event coalescing. | |
5535 | * | |
5536 | * Flush the mailbox to de-assert the IRQ immediately to prevent | |
5537 | * spurious interrupts. The flush impacts performance but | |
5538 | * excessive spurious interrupts can be worse in some cases. | |
5539 | */ | |
5540 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); | |
5541 | if (tg3_irq_sync(tp)) | |
5542 | goto out; | |
5543 | sblk->status &= ~SD_STATUS_UPDATED; | |
5544 | if (likely(tg3_has_work(tnapi))) { | |
5545 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); | |
5546 | napi_schedule(&tnapi->napi); | |
5547 | } else { | |
5548 | /* No work, shared interrupt perhaps? re-enable | |
5549 | * interrupts, and flush that PCI write | |
5550 | */ | |
5551 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, | |
5552 | 0x00000000); | |
5553 | } | |
5554 | out: | |
5555 | return IRQ_RETVAL(handled); | |
5556 | } | |
5557 | ||
5558 | static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id) | |
5559 | { | |
5560 | struct tg3_napi *tnapi = dev_id; | |
5561 | struct tg3 *tp = tnapi->tp; | |
5562 | struct tg3_hw_status *sblk = tnapi->hw_status; | |
5563 | unsigned int handled = 1; | |
5564 | ||
5565 | /* In INTx mode, it is possible for the interrupt to arrive at | |
5566 | * the CPU before the status block posted prior to the interrupt. | |
5567 | * Reading the PCI State register will confirm whether the | |
5568 | * interrupt is ours and will flush the status block. | |
5569 | */ | |
5570 | if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) { | |
5571 | if (tg3_flag(tp, CHIP_RESETTING) || | |
5572 | (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { | |
5573 | handled = 0; | |
5574 | goto out; | |
5575 | } | |
5576 | } | |
5577 | ||
5578 | /* | |
5579 | * writing any value to intr-mbox-0 clears PCI INTA# and | |
5580 | * chip-internal interrupt pending events. | |
5581 | * writing non-zero to intr-mbox-0 additional tells the | |
5582 | * NIC to stop sending us irqs, engaging "in-intr-handler" | |
5583 | * event coalescing. | |
5584 | * | |
5585 | * Flush the mailbox to de-assert the IRQ immediately to prevent | |
5586 | * spurious interrupts. The flush impacts performance but | |
5587 | * excessive spurious interrupts can be worse in some cases. | |
5588 | */ | |
5589 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); | |
5590 | ||
5591 | /* | |
5592 | * In a shared interrupt configuration, sometimes other devices' | |
5593 | * interrupts will scream. We record the current status tag here | |
5594 | * so that the above check can report that the screaming interrupts | |
5595 | * are unhandled. Eventually they will be silenced. | |
5596 | */ | |
5597 | tnapi->last_irq_tag = sblk->status_tag; | |
5598 | ||
5599 | if (tg3_irq_sync(tp)) | |
5600 | goto out; | |
5601 | ||
5602 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); | |
5603 | ||
5604 | napi_schedule(&tnapi->napi); | |
5605 | ||
5606 | out: | |
5607 | return IRQ_RETVAL(handled); | |
5608 | } | |
5609 | ||
5610 | /* ISR for interrupt test */ | |
5611 | static irqreturn_t tg3_test_isr(int irq, void *dev_id) | |
5612 | { | |
5613 | struct tg3_napi *tnapi = dev_id; | |
5614 | struct tg3 *tp = tnapi->tp; | |
5615 | struct tg3_hw_status *sblk = tnapi->hw_status; | |
5616 | ||
5617 | if ((sblk->status & SD_STATUS_UPDATED) || | |
5618 | !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { | |
5619 | tg3_disable_ints(tp); | |
5620 | return IRQ_RETVAL(1); | |
5621 | } | |
5622 | return IRQ_RETVAL(0); | |
5623 | } | |
5624 | ||
5625 | static int tg3_init_hw(struct tg3 *, int); | |
5626 | static int tg3_halt(struct tg3 *, int, int); | |
5627 | ||
5628 | /* Restart hardware after configuration changes, self-test, etc. | |
5629 | * Invoked with tp->lock held. | |
5630 | */ | |
5631 | static int tg3_restart_hw(struct tg3 *tp, int reset_phy) | |
5632 | __releases(tp->lock) | |
5633 | __acquires(tp->lock) | |
5634 | { | |
5635 | int err; | |
5636 | ||
5637 | err = tg3_init_hw(tp, reset_phy); | |
5638 | if (err) { | |
5639 | netdev_err(tp->dev, | |
5640 | "Failed to re-initialize device, aborting\n"); | |
5641 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | |
5642 | tg3_full_unlock(tp); | |
5643 | del_timer_sync(&tp->timer); | |
5644 | tp->irq_sync = 0; | |
5645 | tg3_napi_enable(tp); | |
5646 | dev_close(tp->dev); | |
5647 | tg3_full_lock(tp, 0); | |
5648 | } | |
5649 | return err; | |
5650 | } | |
5651 | ||
5652 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
5653 | static void tg3_poll_controller(struct net_device *dev) | |
5654 | { | |
5655 | int i; | |
5656 | struct tg3 *tp = netdev_priv(dev); | |
5657 | ||
5658 | for (i = 0; i < tp->irq_cnt; i++) | |
5659 | tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]); | |
5660 | } | |
5661 | #endif | |
5662 | ||
5663 | static void tg3_reset_task(struct work_struct *work) | |
5664 | { | |
5665 | struct tg3 *tp = container_of(work, struct tg3, reset_task); | |
5666 | int err; | |
5667 | unsigned int restart_timer; | |
5668 | ||
5669 | tg3_full_lock(tp, 0); | |
5670 | ||
5671 | if (!netif_running(tp->dev)) { | |
5672 | tg3_full_unlock(tp); | |
5673 | return; | |
5674 | } | |
5675 | ||
5676 | tg3_full_unlock(tp); | |
5677 | ||
5678 | tg3_phy_stop(tp); | |
5679 | ||
5680 | tg3_netif_stop(tp); | |
5681 | ||
5682 | tg3_full_lock(tp, 1); | |
5683 | ||
5684 | restart_timer = tg3_flag(tp, RESTART_TIMER); | |
5685 | tg3_flag_clear(tp, RESTART_TIMER); | |
5686 | ||
5687 | if (tg3_flag(tp, TX_RECOVERY_PENDING)) { | |
5688 | tp->write32_tx_mbox = tg3_write32_tx_mbox; | |
5689 | tp->write32_rx_mbox = tg3_write_flush_reg32; | |
5690 | tg3_flag_set(tp, MBOX_WRITE_REORDER); | |
5691 | tg3_flag_clear(tp, TX_RECOVERY_PENDING); | |
5692 | } | |
5693 | ||
5694 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 0); | |
5695 | err = tg3_init_hw(tp, 1); | |
5696 | if (err) | |
5697 | goto out; | |
5698 | ||
5699 | tg3_netif_start(tp); | |
5700 | ||
5701 | if (restart_timer) | |
5702 | mod_timer(&tp->timer, jiffies + 1); | |
5703 | ||
5704 | out: | |
5705 | tg3_full_unlock(tp); | |
5706 | ||
5707 | if (!err) | |
5708 | tg3_phy_start(tp); | |
5709 | } | |
5710 | ||
5711 | static void tg3_tx_timeout(struct net_device *dev) | |
5712 | { | |
5713 | struct tg3 *tp = netdev_priv(dev); | |
5714 | ||
5715 | if (netif_msg_tx_err(tp)) { | |
5716 | netdev_err(dev, "transmit timed out, resetting\n"); | |
5717 | tg3_dump_state(tp); | |
5718 | } | |
5719 | ||
5720 | schedule_work(&tp->reset_task); | |
5721 | } | |
5722 | ||
5723 | /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */ | |
5724 | static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len) | |
5725 | { | |
5726 | u32 base = (u32) mapping & 0xffffffff; | |
5727 | ||
5728 | return (base > 0xffffdcc0) && (base + len + 8 < base); | |
5729 | } | |
5730 | ||
5731 | /* Test for DMA addresses > 40-bit */ | |
5732 | static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping, | |
5733 | int len) | |
5734 | { | |
5735 | #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64) | |
5736 | if (tg3_flag(tp, 40BIT_DMA_BUG)) | |
5737 | return ((u64) mapping + len) > DMA_BIT_MASK(40); | |
5738 | return 0; | |
5739 | #else | |
5740 | return 0; | |
5741 | #endif | |
5742 | } | |
5743 | ||
5744 | static void tg3_set_txd(struct tg3_napi *tnapi, int entry, | |
5745 | dma_addr_t mapping, int len, u32 flags, | |
5746 | u32 mss_and_is_end) | |
5747 | { | |
5748 | struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry]; | |
5749 | int is_end = (mss_and_is_end & 0x1); | |
5750 | u32 mss = (mss_and_is_end >> 1); | |
5751 | u32 vlan_tag = 0; | |
5752 | ||
5753 | if (is_end) | |
5754 | flags |= TXD_FLAG_END; | |
5755 | if (flags & TXD_FLAG_VLAN) { | |
5756 | vlan_tag = flags >> 16; | |
5757 | flags &= 0xffff; | |
5758 | } | |
5759 | vlan_tag |= (mss << TXD_MSS_SHIFT); | |
5760 | ||
5761 | txd->addr_hi = ((u64) mapping >> 32); | |
5762 | txd->addr_lo = ((u64) mapping & 0xffffffff); | |
5763 | txd->len_flags = (len << TXD_LEN_SHIFT) | flags; | |
5764 | txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT; | |
5765 | } | |
5766 | ||
5767 | static void tg3_skb_error_unmap(struct tg3_napi *tnapi, | |
5768 | struct sk_buff *skb, int last) | |
5769 | { | |
5770 | int i; | |
5771 | u32 entry = tnapi->tx_prod; | |
5772 | struct ring_info *txb = &tnapi->tx_buffers[entry]; | |
5773 | ||
5774 | pci_unmap_single(tnapi->tp->pdev, | |
5775 | dma_unmap_addr(txb, mapping), | |
5776 | skb_headlen(skb), | |
5777 | PCI_DMA_TODEVICE); | |
5778 | for (i = 0; i < last; i++) { | |
5779 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
5780 | ||
5781 | entry = NEXT_TX(entry); | |
5782 | txb = &tnapi->tx_buffers[entry]; | |
5783 | ||
5784 | pci_unmap_page(tnapi->tp->pdev, | |
5785 | dma_unmap_addr(txb, mapping), | |
5786 | frag->size, PCI_DMA_TODEVICE); | |
5787 | } | |
5788 | } | |
5789 | ||
5790 | /* Workaround 4GB and 40-bit hardware DMA bugs. */ | |
5791 | static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi, | |
5792 | struct sk_buff *skb, | |
5793 | u32 base_flags, u32 mss) | |
5794 | { | |
5795 | struct tg3 *tp = tnapi->tp; | |
5796 | struct sk_buff *new_skb; | |
5797 | dma_addr_t new_addr = 0; | |
5798 | u32 entry = tnapi->tx_prod; | |
5799 | int ret = 0; | |
5800 | ||
5801 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) | |
5802 | new_skb = skb_copy(skb, GFP_ATOMIC); | |
5803 | else { | |
5804 | int more_headroom = 4 - ((unsigned long)skb->data & 3); | |
5805 | ||
5806 | new_skb = skb_copy_expand(skb, | |
5807 | skb_headroom(skb) + more_headroom, | |
5808 | skb_tailroom(skb), GFP_ATOMIC); | |
5809 | } | |
5810 | ||
5811 | if (!new_skb) { | |
5812 | ret = -1; | |
5813 | } else { | |
5814 | /* New SKB is guaranteed to be linear. */ | |
5815 | new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len, | |
5816 | PCI_DMA_TODEVICE); | |
5817 | /* Make sure the mapping succeeded */ | |
5818 | if (pci_dma_mapping_error(tp->pdev, new_addr)) { | |
5819 | ret = -1; | |
5820 | dev_kfree_skb(new_skb); | |
5821 | ||
5822 | /* Make sure new skb does not cross any 4G boundaries. | |
5823 | * Drop the packet if it does. | |
5824 | */ | |
5825 | } else if (tg3_4g_overflow_test(new_addr, new_skb->len)) { | |
5826 | pci_unmap_single(tp->pdev, new_addr, new_skb->len, | |
5827 | PCI_DMA_TODEVICE); | |
5828 | ret = -1; | |
5829 | dev_kfree_skb(new_skb); | |
5830 | } else { | |
5831 | tnapi->tx_buffers[entry].skb = new_skb; | |
5832 | dma_unmap_addr_set(&tnapi->tx_buffers[entry], | |
5833 | mapping, new_addr); | |
5834 | ||
5835 | tg3_set_txd(tnapi, entry, new_addr, new_skb->len, | |
5836 | base_flags, 1 | (mss << 1)); | |
5837 | } | |
5838 | } | |
5839 | ||
5840 | dev_kfree_skb(skb); | |
5841 | ||
5842 | return ret; | |
5843 | } | |
5844 | ||
5845 | static netdev_tx_t tg3_start_xmit(struct sk_buff *, struct net_device *); | |
5846 | ||
5847 | /* Use GSO to workaround a rare TSO bug that may be triggered when the | |
5848 | * TSO header is greater than 80 bytes. | |
5849 | */ | |
5850 | static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb) | |
5851 | { | |
5852 | struct sk_buff *segs, *nskb; | |
5853 | u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3; | |
5854 | ||
5855 | /* Estimate the number of fragments in the worst case */ | |
5856 | if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) { | |
5857 | netif_stop_queue(tp->dev); | |
5858 | ||
5859 | /* netif_tx_stop_queue() must be done before checking | |
5860 | * checking tx index in tg3_tx_avail() below, because in | |
5861 | * tg3_tx(), we update tx index before checking for | |
5862 | * netif_tx_queue_stopped(). | |
5863 | */ | |
5864 | smp_mb(); | |
5865 | if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est) | |
5866 | return NETDEV_TX_BUSY; | |
5867 | ||
5868 | netif_wake_queue(tp->dev); | |
5869 | } | |
5870 | ||
5871 | segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO); | |
5872 | if (IS_ERR(segs)) | |
5873 | goto tg3_tso_bug_end; | |
5874 | ||
5875 | do { | |
5876 | nskb = segs; | |
5877 | segs = segs->next; | |
5878 | nskb->next = NULL; | |
5879 | tg3_start_xmit(nskb, tp->dev); | |
5880 | } while (segs); | |
5881 | ||
5882 | tg3_tso_bug_end: | |
5883 | dev_kfree_skb(skb); | |
5884 | ||
5885 | return NETDEV_TX_OK; | |
5886 | } | |
5887 | ||
5888 | /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and | |
5889 | * support TG3_FLAG_HW_TSO_1 or firmware TSO only. | |
5890 | */ | |
5891 | static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
5892 | { | |
5893 | struct tg3 *tp = netdev_priv(dev); | |
5894 | u32 len, entry, base_flags, mss; | |
5895 | int i = -1, would_hit_hwbug; | |
5896 | dma_addr_t mapping; | |
5897 | struct tg3_napi *tnapi; | |
5898 | struct netdev_queue *txq; | |
5899 | unsigned int last; | |
5900 | ||
5901 | txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb)); | |
5902 | tnapi = &tp->napi[skb_get_queue_mapping(skb)]; | |
5903 | if (tg3_flag(tp, ENABLE_TSS)) | |
5904 | tnapi++; | |
5905 | ||
5906 | /* We are running in BH disabled context with netif_tx_lock | |
5907 | * and TX reclaim runs via tp->napi.poll inside of a software | |
5908 | * interrupt. Furthermore, IRQ processing runs lockless so we have | |
5909 | * no IRQ context deadlocks to worry about either. Rejoice! | |
5910 | */ | |
5911 | if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) { | |
5912 | if (!netif_tx_queue_stopped(txq)) { | |
5913 | netif_tx_stop_queue(txq); | |
5914 | ||
5915 | /* This is a hard error, log it. */ | |
5916 | netdev_err(dev, | |
5917 | "BUG! Tx Ring full when queue awake!\n"); | |
5918 | } | |
5919 | return NETDEV_TX_BUSY; | |
5920 | } | |
5921 | ||
5922 | entry = tnapi->tx_prod; | |
5923 | base_flags = 0; | |
5924 | if (skb->ip_summed == CHECKSUM_PARTIAL) | |
5925 | base_flags |= TXD_FLAG_TCPUDP_CSUM; | |
5926 | ||
5927 | mss = skb_shinfo(skb)->gso_size; | |
5928 | if (mss) { | |
5929 | struct iphdr *iph; | |
5930 | u32 tcp_opt_len, hdr_len; | |
5931 | ||
5932 | if (skb_header_cloned(skb) && | |
5933 | pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) { | |
5934 | dev_kfree_skb(skb); | |
5935 | goto out_unlock; | |
5936 | } | |
5937 | ||
5938 | iph = ip_hdr(skb); | |
5939 | tcp_opt_len = tcp_optlen(skb); | |
5940 | ||
5941 | if (skb_is_gso_v6(skb)) { | |
5942 | hdr_len = skb_headlen(skb) - ETH_HLEN; | |
5943 | } else { | |
5944 | u32 ip_tcp_len; | |
5945 | ||
5946 | ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr); | |
5947 | hdr_len = ip_tcp_len + tcp_opt_len; | |
5948 | ||
5949 | iph->check = 0; | |
5950 | iph->tot_len = htons(mss + hdr_len); | |
5951 | } | |
5952 | ||
5953 | if (unlikely((ETH_HLEN + hdr_len) > 80) && | |
5954 | tg3_flag(tp, TSO_BUG)) | |
5955 | return tg3_tso_bug(tp, skb); | |
5956 | ||
5957 | base_flags |= (TXD_FLAG_CPU_PRE_DMA | | |
5958 | TXD_FLAG_CPU_POST_DMA); | |
5959 | ||
5960 | if (tg3_flag(tp, HW_TSO_1) || | |
5961 | tg3_flag(tp, HW_TSO_2) || | |
5962 | tg3_flag(tp, HW_TSO_3)) { | |
5963 | tcp_hdr(skb)->check = 0; | |
5964 | base_flags &= ~TXD_FLAG_TCPUDP_CSUM; | |
5965 | } else | |
5966 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, | |
5967 | iph->daddr, 0, | |
5968 | IPPROTO_TCP, | |
5969 | 0); | |
5970 | ||
5971 | if (tg3_flag(tp, HW_TSO_3)) { | |
5972 | mss |= (hdr_len & 0xc) << 12; | |
5973 | if (hdr_len & 0x10) | |
5974 | base_flags |= 0x00000010; | |
5975 | base_flags |= (hdr_len & 0x3e0) << 5; | |
5976 | } else if (tg3_flag(tp, HW_TSO_2)) | |
5977 | mss |= hdr_len << 9; | |
5978 | else if (tg3_flag(tp, HW_TSO_1) || | |
5979 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | |
5980 | if (tcp_opt_len || iph->ihl > 5) { | |
5981 | int tsflags; | |
5982 | ||
5983 | tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2); | |
5984 | mss |= (tsflags << 11); | |
5985 | } | |
5986 | } else { | |
5987 | if (tcp_opt_len || iph->ihl > 5) { | |
5988 | int tsflags; | |
5989 | ||
5990 | tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2); | |
5991 | base_flags |= tsflags << 12; | |
5992 | } | |
5993 | } | |
5994 | } | |
5995 | ||
5996 | if (vlan_tx_tag_present(skb)) | |
5997 | base_flags |= (TXD_FLAG_VLAN | | |
5998 | (vlan_tx_tag_get(skb) << 16)); | |
5999 | ||
6000 | if (tg3_flag(tp, USE_JUMBO_BDFLAG) && | |
6001 | !mss && skb->len > VLAN_ETH_FRAME_LEN) | |
6002 | base_flags |= TXD_FLAG_JMB_PKT; | |
6003 | ||
6004 | len = skb_headlen(skb); | |
6005 | ||
6006 | mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE); | |
6007 | if (pci_dma_mapping_error(tp->pdev, mapping)) { | |
6008 | dev_kfree_skb(skb); | |
6009 | goto out_unlock; | |
6010 | } | |
6011 | ||
6012 | tnapi->tx_buffers[entry].skb = skb; | |
6013 | dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping); | |
6014 | ||
6015 | would_hit_hwbug = 0; | |
6016 | ||
6017 | if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8) | |
6018 | would_hit_hwbug = 1; | |
6019 | ||
6020 | if (tg3_4g_overflow_test(mapping, len)) | |
6021 | would_hit_hwbug = 1; | |
6022 | ||
6023 | if (tg3_40bit_overflow_test(tp, mapping, len)) | |
6024 | would_hit_hwbug = 1; | |
6025 | ||
6026 | if (tg3_flag(tp, 5701_DMA_BUG)) | |
6027 | would_hit_hwbug = 1; | |
6028 | ||
6029 | tg3_set_txd(tnapi, entry, mapping, len, base_flags, | |
6030 | (skb_shinfo(skb)->nr_frags == 0) | (mss << 1)); | |
6031 | ||
6032 | entry = NEXT_TX(entry); | |
6033 | ||
6034 | /* Now loop through additional data fragments, and queue them. */ | |
6035 | if (skb_shinfo(skb)->nr_frags > 0) { | |
6036 | last = skb_shinfo(skb)->nr_frags - 1; | |
6037 | for (i = 0; i <= last; i++) { | |
6038 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
6039 | ||
6040 | len = frag->size; | |
6041 | mapping = pci_map_page(tp->pdev, | |
6042 | frag->page, | |
6043 | frag->page_offset, | |
6044 | len, PCI_DMA_TODEVICE); | |
6045 | ||
6046 | tnapi->tx_buffers[entry].skb = NULL; | |
6047 | dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, | |
6048 | mapping); | |
6049 | if (pci_dma_mapping_error(tp->pdev, mapping)) | |
6050 | goto dma_error; | |
6051 | ||
6052 | if (tg3_flag(tp, SHORT_DMA_BUG) && | |
6053 | len <= 8) | |
6054 | would_hit_hwbug = 1; | |
6055 | ||
6056 | if (tg3_4g_overflow_test(mapping, len)) | |
6057 | would_hit_hwbug = 1; | |
6058 | ||
6059 | if (tg3_40bit_overflow_test(tp, mapping, len)) | |
6060 | would_hit_hwbug = 1; | |
6061 | ||
6062 | if (tg3_flag(tp, HW_TSO_1) || | |
6063 | tg3_flag(tp, HW_TSO_2) || | |
6064 | tg3_flag(tp, HW_TSO_3)) | |
6065 | tg3_set_txd(tnapi, entry, mapping, len, | |
6066 | base_flags, (i == last)|(mss << 1)); | |
6067 | else | |
6068 | tg3_set_txd(tnapi, entry, mapping, len, | |
6069 | base_flags, (i == last)); | |
6070 | ||
6071 | entry = NEXT_TX(entry); | |
6072 | } | |
6073 | } | |
6074 | ||
6075 | if (would_hit_hwbug) { | |
6076 | tg3_skb_error_unmap(tnapi, skb, i); | |
6077 | ||
6078 | /* If the workaround fails due to memory/mapping | |
6079 | * failure, silently drop this packet. | |
6080 | */ | |
6081 | if (tigon3_dma_hwbug_workaround(tnapi, skb, base_flags, mss)) | |
6082 | goto out_unlock; | |
6083 | ||
6084 | entry = NEXT_TX(tnapi->tx_prod); | |
6085 | } | |
6086 | ||
6087 | /* Packets are ready, update Tx producer idx local and on card. */ | |
6088 | tw32_tx_mbox(tnapi->prodmbox, entry); | |
6089 | ||
6090 | skb_tx_timestamp(skb); | |
6091 | ||
6092 | tnapi->tx_prod = entry; | |
6093 | if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) { | |
6094 | netif_tx_stop_queue(txq); | |
6095 | ||
6096 | /* netif_tx_stop_queue() must be done before checking | |
6097 | * checking tx index in tg3_tx_avail() below, because in | |
6098 | * tg3_tx(), we update tx index before checking for | |
6099 | * netif_tx_queue_stopped(). | |
6100 | */ | |
6101 | smp_mb(); | |
6102 | if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)) | |
6103 | netif_tx_wake_queue(txq); | |
6104 | } | |
6105 | ||
6106 | out_unlock: | |
6107 | mmiowb(); | |
6108 | ||
6109 | return NETDEV_TX_OK; | |
6110 | ||
6111 | dma_error: | |
6112 | tg3_skb_error_unmap(tnapi, skb, i); | |
6113 | dev_kfree_skb(skb); | |
6114 | tnapi->tx_buffers[tnapi->tx_prod].skb = NULL; | |
6115 | return NETDEV_TX_OK; | |
6116 | } | |
6117 | ||
6118 | static void tg3_set_loopback(struct net_device *dev, u32 features) | |
6119 | { | |
6120 | struct tg3 *tp = netdev_priv(dev); | |
6121 | ||
6122 | if (features & NETIF_F_LOOPBACK) { | |
6123 | if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK) | |
6124 | return; | |
6125 | ||
6126 | /* | |
6127 | * Clear MAC_MODE_HALF_DUPLEX or you won't get packets back in | |
6128 | * loopback mode if Half-Duplex mode was negotiated earlier. | |
6129 | */ | |
6130 | tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; | |
6131 | ||
6132 | /* Enable internal MAC loopback mode */ | |
6133 | tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK; | |
6134 | spin_lock_bh(&tp->lock); | |
6135 | tw32(MAC_MODE, tp->mac_mode); | |
6136 | netif_carrier_on(tp->dev); | |
6137 | spin_unlock_bh(&tp->lock); | |
6138 | netdev_info(dev, "Internal MAC loopback mode enabled.\n"); | |
6139 | } else { | |
6140 | if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)) | |
6141 | return; | |
6142 | ||
6143 | /* Disable internal MAC loopback mode */ | |
6144 | tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK; | |
6145 | spin_lock_bh(&tp->lock); | |
6146 | tw32(MAC_MODE, tp->mac_mode); | |
6147 | /* Force link status check */ | |
6148 | tg3_setup_phy(tp, 1); | |
6149 | spin_unlock_bh(&tp->lock); | |
6150 | netdev_info(dev, "Internal MAC loopback mode disabled.\n"); | |
6151 | } | |
6152 | } | |
6153 | ||
6154 | static u32 tg3_fix_features(struct net_device *dev, u32 features) | |
6155 | { | |
6156 | struct tg3 *tp = netdev_priv(dev); | |
6157 | ||
6158 | if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS)) | |
6159 | features &= ~NETIF_F_ALL_TSO; | |
6160 | ||
6161 | return features; | |
6162 | } | |
6163 | ||
6164 | static int tg3_set_features(struct net_device *dev, u32 features) | |
6165 | { | |
6166 | u32 changed = dev->features ^ features; | |
6167 | ||
6168 | if ((changed & NETIF_F_LOOPBACK) && netif_running(dev)) | |
6169 | tg3_set_loopback(dev, features); | |
6170 | ||
6171 | return 0; | |
6172 | } | |
6173 | ||
6174 | static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp, | |
6175 | int new_mtu) | |
6176 | { | |
6177 | dev->mtu = new_mtu; | |
6178 | ||
6179 | if (new_mtu > ETH_DATA_LEN) { | |
6180 | if (tg3_flag(tp, 5780_CLASS)) { | |
6181 | netdev_update_features(dev); | |
6182 | tg3_flag_clear(tp, TSO_CAPABLE); | |
6183 | } else { | |
6184 | tg3_flag_set(tp, JUMBO_RING_ENABLE); | |
6185 | } | |
6186 | } else { | |
6187 | if (tg3_flag(tp, 5780_CLASS)) { | |
6188 | tg3_flag_set(tp, TSO_CAPABLE); | |
6189 | netdev_update_features(dev); | |
6190 | } | |
6191 | tg3_flag_clear(tp, JUMBO_RING_ENABLE); | |
6192 | } | |
6193 | } | |
6194 | ||
6195 | static int tg3_change_mtu(struct net_device *dev, int new_mtu) | |
6196 | { | |
6197 | struct tg3 *tp = netdev_priv(dev); | |
6198 | int err; | |
6199 | ||
6200 | if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp)) | |
6201 | return -EINVAL; | |
6202 | ||
6203 | if (!netif_running(dev)) { | |
6204 | /* We'll just catch it later when the | |
6205 | * device is up'd. | |
6206 | */ | |
6207 | tg3_set_mtu(dev, tp, new_mtu); | |
6208 | return 0; | |
6209 | } | |
6210 | ||
6211 | tg3_phy_stop(tp); | |
6212 | ||
6213 | tg3_netif_stop(tp); | |
6214 | ||
6215 | tg3_full_lock(tp, 1); | |
6216 | ||
6217 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | |
6218 | ||
6219 | tg3_set_mtu(dev, tp, new_mtu); | |
6220 | ||
6221 | err = tg3_restart_hw(tp, 0); | |
6222 | ||
6223 | if (!err) | |
6224 | tg3_netif_start(tp); | |
6225 | ||
6226 | tg3_full_unlock(tp); | |
6227 | ||
6228 | if (!err) | |
6229 | tg3_phy_start(tp); | |
6230 | ||
6231 | return err; | |
6232 | } | |
6233 | ||
6234 | static void tg3_rx_prodring_free(struct tg3 *tp, | |
6235 | struct tg3_rx_prodring_set *tpr) | |
6236 | { | |
6237 | int i; | |
6238 | ||
6239 | if (tpr != &tp->napi[0].prodring) { | |
6240 | for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx; | |
6241 | i = (i + 1) & tp->rx_std_ring_mask) | |
6242 | tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i], | |
6243 | tp->rx_pkt_map_sz); | |
6244 | ||
6245 | if (tg3_flag(tp, JUMBO_CAPABLE)) { | |
6246 | for (i = tpr->rx_jmb_cons_idx; | |
6247 | i != tpr->rx_jmb_prod_idx; | |
6248 | i = (i + 1) & tp->rx_jmb_ring_mask) { | |
6249 | tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i], | |
6250 | TG3_RX_JMB_MAP_SZ); | |
6251 | } | |
6252 | } | |
6253 | ||
6254 | return; | |
6255 | } | |
6256 | ||
6257 | for (i = 0; i <= tp->rx_std_ring_mask; i++) | |
6258 | tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i], | |
6259 | tp->rx_pkt_map_sz); | |
6260 | ||
6261 | if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) { | |
6262 | for (i = 0; i <= tp->rx_jmb_ring_mask; i++) | |
6263 | tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i], | |
6264 | TG3_RX_JMB_MAP_SZ); | |
6265 | } | |
6266 | } | |
6267 | ||
6268 | /* Initialize rx rings for packet processing. | |
6269 | * | |
6270 | * The chip has been shut down and the driver detached from | |
6271 | * the networking, so no interrupts or new tx packets will | |
6272 | * end up in the driver. tp->{tx,}lock are held and thus | |
6273 | * we may not sleep. | |
6274 | */ | |
6275 | static int tg3_rx_prodring_alloc(struct tg3 *tp, | |
6276 | struct tg3_rx_prodring_set *tpr) | |
6277 | { | |
6278 | u32 i, rx_pkt_dma_sz; | |
6279 | ||
6280 | tpr->rx_std_cons_idx = 0; | |
6281 | tpr->rx_std_prod_idx = 0; | |
6282 | tpr->rx_jmb_cons_idx = 0; | |
6283 | tpr->rx_jmb_prod_idx = 0; | |
6284 | ||
6285 | if (tpr != &tp->napi[0].prodring) { | |
6286 | memset(&tpr->rx_std_buffers[0], 0, | |
6287 | TG3_RX_STD_BUFF_RING_SIZE(tp)); | |
6288 | if (tpr->rx_jmb_buffers) | |
6289 | memset(&tpr->rx_jmb_buffers[0], 0, | |
6290 | TG3_RX_JMB_BUFF_RING_SIZE(tp)); | |
6291 | goto done; | |
6292 | } | |
6293 | ||
6294 | /* Zero out all descriptors. */ | |
6295 | memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp)); | |
6296 | ||
6297 | rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ; | |
6298 | if (tg3_flag(tp, 5780_CLASS) && | |
6299 | tp->dev->mtu > ETH_DATA_LEN) | |
6300 | rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ; | |
6301 | tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz); | |
6302 | ||
6303 | /* Initialize invariants of the rings, we only set this | |
6304 | * stuff once. This works because the card does not | |
6305 | * write into the rx buffer posting rings. | |
6306 | */ | |
6307 | for (i = 0; i <= tp->rx_std_ring_mask; i++) { | |
6308 | struct tg3_rx_buffer_desc *rxd; | |
6309 | ||
6310 | rxd = &tpr->rx_std[i]; | |
6311 | rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT; | |
6312 | rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT); | |
6313 | rxd->opaque = (RXD_OPAQUE_RING_STD | | |
6314 | (i << RXD_OPAQUE_INDEX_SHIFT)); | |
6315 | } | |
6316 | ||
6317 | /* Now allocate fresh SKBs for each rx ring. */ | |
6318 | for (i = 0; i < tp->rx_pending; i++) { | |
6319 | if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) { | |
6320 | netdev_warn(tp->dev, | |
6321 | "Using a smaller RX standard ring. Only " | |
6322 | "%d out of %d buffers were allocated " | |
6323 | "successfully\n", i, tp->rx_pending); | |
6324 | if (i == 0) | |
6325 | goto initfail; | |
6326 | tp->rx_pending = i; | |
6327 | break; | |
6328 | } | |
6329 | } | |
6330 | ||
6331 | if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS)) | |
6332 | goto done; | |
6333 | ||
6334 | memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp)); | |
6335 | ||
6336 | if (!tg3_flag(tp, JUMBO_RING_ENABLE)) | |
6337 | goto done; | |
6338 | ||
6339 | for (i = 0; i <= tp->rx_jmb_ring_mask; i++) { | |
6340 | struct tg3_rx_buffer_desc *rxd; | |
6341 | ||
6342 | rxd = &tpr->rx_jmb[i].std; | |
6343 | rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT; | |
6344 | rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) | | |
6345 | RXD_FLAG_JUMBO; | |
6346 | rxd->opaque = (RXD_OPAQUE_RING_JUMBO | | |
6347 | (i << RXD_OPAQUE_INDEX_SHIFT)); | |
6348 | } | |
6349 | ||
6350 | for (i = 0; i < tp->rx_jumbo_pending; i++) { | |
6351 | if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) { | |
6352 | netdev_warn(tp->dev, | |
6353 | "Using a smaller RX jumbo ring. Only %d " | |
6354 | "out of %d buffers were allocated " | |
6355 | "successfully\n", i, tp->rx_jumbo_pending); | |
6356 | if (i == 0) | |
6357 | goto initfail; | |
6358 | tp->rx_jumbo_pending = i; | |
6359 | break; | |
6360 | } | |
6361 | } | |
6362 | ||
6363 | done: | |
6364 | return 0; | |
6365 | ||
6366 | initfail: | |
6367 | tg3_rx_prodring_free(tp, tpr); | |
6368 | return -ENOMEM; | |
6369 | } | |
6370 | ||
6371 | static void tg3_rx_prodring_fini(struct tg3 *tp, | |
6372 | struct tg3_rx_prodring_set *tpr) | |
6373 | { | |
6374 | kfree(tpr->rx_std_buffers); | |
6375 | tpr->rx_std_buffers = NULL; | |
6376 | kfree(tpr->rx_jmb_buffers); | |
6377 | tpr->rx_jmb_buffers = NULL; | |
6378 | if (tpr->rx_std) { | |
6379 | dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp), | |
6380 | tpr->rx_std, tpr->rx_std_mapping); | |
6381 | tpr->rx_std = NULL; | |
6382 | } | |
6383 | if (tpr->rx_jmb) { | |
6384 | dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp), | |
6385 | tpr->rx_jmb, tpr->rx_jmb_mapping); | |
6386 | tpr->rx_jmb = NULL; | |
6387 | } | |
6388 | } | |
6389 | ||
6390 | static int tg3_rx_prodring_init(struct tg3 *tp, | |
6391 | struct tg3_rx_prodring_set *tpr) | |
6392 | { | |
6393 | tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp), | |
6394 | GFP_KERNEL); | |
6395 | if (!tpr->rx_std_buffers) | |
6396 | return -ENOMEM; | |
6397 | ||
6398 | tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev, | |
6399 | TG3_RX_STD_RING_BYTES(tp), | |
6400 | &tpr->rx_std_mapping, | |
6401 | GFP_KERNEL); | |
6402 | if (!tpr->rx_std) | |
6403 | goto err_out; | |
6404 | ||
6405 | if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) { | |
6406 | tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp), | |
6407 | GFP_KERNEL); | |
6408 | if (!tpr->rx_jmb_buffers) | |
6409 | goto err_out; | |
6410 | ||
6411 | tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev, | |
6412 | TG3_RX_JMB_RING_BYTES(tp), | |
6413 | &tpr->rx_jmb_mapping, | |
6414 | GFP_KERNEL); | |
6415 | if (!tpr->rx_jmb) | |
6416 | goto err_out; | |
6417 | } | |
6418 | ||
6419 | return 0; | |
6420 | ||
6421 | err_out: | |
6422 | tg3_rx_prodring_fini(tp, tpr); | |
6423 | return -ENOMEM; | |
6424 | } | |
6425 | ||
6426 | /* Free up pending packets in all rx/tx rings. | |
6427 | * | |
6428 | * The chip has been shut down and the driver detached from | |
6429 | * the networking, so no interrupts or new tx packets will | |
6430 | * end up in the driver. tp->{tx,}lock is not held and we are not | |
6431 | * in an interrupt context and thus may sleep. | |
6432 | */ | |
6433 | static void tg3_free_rings(struct tg3 *tp) | |
6434 | { | |
6435 | int i, j; | |
6436 | ||
6437 | for (j = 0; j < tp->irq_cnt; j++) { | |
6438 | struct tg3_napi *tnapi = &tp->napi[j]; | |
6439 | ||
6440 | tg3_rx_prodring_free(tp, &tnapi->prodring); | |
6441 | ||
6442 | if (!tnapi->tx_buffers) | |
6443 | continue; | |
6444 | ||
6445 | for (i = 0; i < TG3_TX_RING_SIZE; ) { | |
6446 | struct ring_info *txp; | |
6447 | struct sk_buff *skb; | |
6448 | unsigned int k; | |
6449 | ||
6450 | txp = &tnapi->tx_buffers[i]; | |
6451 | skb = txp->skb; | |
6452 | ||
6453 | if (skb == NULL) { | |
6454 | i++; | |
6455 | continue; | |
6456 | } | |
6457 | ||
6458 | pci_unmap_single(tp->pdev, | |
6459 | dma_unmap_addr(txp, mapping), | |
6460 | skb_headlen(skb), | |
6461 | PCI_DMA_TODEVICE); | |
6462 | txp->skb = NULL; | |
6463 | ||
6464 | i++; | |
6465 | ||
6466 | for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) { | |
6467 | txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)]; | |
6468 | pci_unmap_page(tp->pdev, | |
6469 | dma_unmap_addr(txp, mapping), | |
6470 | skb_shinfo(skb)->frags[k].size, | |
6471 | PCI_DMA_TODEVICE); | |
6472 | i++; | |
6473 | } | |
6474 | ||
6475 | dev_kfree_skb_any(skb); | |
6476 | } | |
6477 | } | |
6478 | } | |
6479 | ||
6480 | /* Initialize tx/rx rings for packet processing. | |
6481 | * | |
6482 | * The chip has been shut down and the driver detached from | |
6483 | * the networking, so no interrupts or new tx packets will | |
6484 | * end up in the driver. tp->{tx,}lock are held and thus | |
6485 | * we may not sleep. | |
6486 | */ | |
6487 | static int tg3_init_rings(struct tg3 *tp) | |
6488 | { | |
6489 | int i; | |
6490 | ||
6491 | /* Free up all the SKBs. */ | |
6492 | tg3_free_rings(tp); | |
6493 | ||
6494 | for (i = 0; i < tp->irq_cnt; i++) { | |
6495 | struct tg3_napi *tnapi = &tp->napi[i]; | |
6496 | ||
6497 | tnapi->last_tag = 0; | |
6498 | tnapi->last_irq_tag = 0; | |
6499 | tnapi->hw_status->status = 0; | |
6500 | tnapi->hw_status->status_tag = 0; | |
6501 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
6502 | ||
6503 | tnapi->tx_prod = 0; | |
6504 | tnapi->tx_cons = 0; | |
6505 | if (tnapi->tx_ring) | |
6506 | memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES); | |
6507 | ||
6508 | tnapi->rx_rcb_ptr = 0; | |
6509 | if (tnapi->rx_rcb) | |
6510 | memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp)); | |
6511 | ||
6512 | if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) { | |
6513 | tg3_free_rings(tp); | |
6514 | return -ENOMEM; | |
6515 | } | |
6516 | } | |
6517 | ||
6518 | return 0; | |
6519 | } | |
6520 | ||
6521 | /* | |
6522 | * Must not be invoked with interrupt sources disabled and | |
6523 | * the hardware shutdown down. | |
6524 | */ | |
6525 | static void tg3_free_consistent(struct tg3 *tp) | |
6526 | { | |
6527 | int i; | |
6528 | ||
6529 | for (i = 0; i < tp->irq_cnt; i++) { | |
6530 | struct tg3_napi *tnapi = &tp->napi[i]; | |
6531 | ||
6532 | if (tnapi->tx_ring) { | |
6533 | dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES, | |
6534 | tnapi->tx_ring, tnapi->tx_desc_mapping); | |
6535 | tnapi->tx_ring = NULL; | |
6536 | } | |
6537 | ||
6538 | kfree(tnapi->tx_buffers); | |
6539 | tnapi->tx_buffers = NULL; | |
6540 | ||
6541 | if (tnapi->rx_rcb) { | |
6542 | dma_free_coherent(&tp->pdev->dev, | |
6543 | TG3_RX_RCB_RING_BYTES(tp), | |
6544 | tnapi->rx_rcb, | |
6545 | tnapi->rx_rcb_mapping); | |
6546 | tnapi->rx_rcb = NULL; | |
6547 | } | |
6548 | ||
6549 | tg3_rx_prodring_fini(tp, &tnapi->prodring); | |
6550 | ||
6551 | if (tnapi->hw_status) { | |
6552 | dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE, | |
6553 | tnapi->hw_status, | |
6554 | tnapi->status_mapping); | |
6555 | tnapi->hw_status = NULL; | |
6556 | } | |
6557 | } | |
6558 | ||
6559 | if (tp->hw_stats) { | |
6560 | dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats), | |
6561 | tp->hw_stats, tp->stats_mapping); | |
6562 | tp->hw_stats = NULL; | |
6563 | } | |
6564 | } | |
6565 | ||
6566 | /* | |
6567 | * Must not be invoked with interrupt sources disabled and | |
6568 | * the hardware shutdown down. Can sleep. | |
6569 | */ | |
6570 | static int tg3_alloc_consistent(struct tg3 *tp) | |
6571 | { | |
6572 | int i; | |
6573 | ||
6574 | tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev, | |
6575 | sizeof(struct tg3_hw_stats), | |
6576 | &tp->stats_mapping, | |
6577 | GFP_KERNEL); | |
6578 | if (!tp->hw_stats) | |
6579 | goto err_out; | |
6580 | ||
6581 | memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats)); | |
6582 | ||
6583 | for (i = 0; i < tp->irq_cnt; i++) { | |
6584 | struct tg3_napi *tnapi = &tp->napi[i]; | |
6585 | struct tg3_hw_status *sblk; | |
6586 | ||
6587 | tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev, | |
6588 | TG3_HW_STATUS_SIZE, | |
6589 | &tnapi->status_mapping, | |
6590 | GFP_KERNEL); | |
6591 | if (!tnapi->hw_status) | |
6592 | goto err_out; | |
6593 | ||
6594 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
6595 | sblk = tnapi->hw_status; | |
6596 | ||
6597 | if (tg3_rx_prodring_init(tp, &tnapi->prodring)) | |
6598 | goto err_out; | |
6599 | ||
6600 | /* If multivector TSS is enabled, vector 0 does not handle | |
6601 | * tx interrupts. Don't allocate any resources for it. | |
6602 | */ | |
6603 | if ((!i && !tg3_flag(tp, ENABLE_TSS)) || | |
6604 | (i && tg3_flag(tp, ENABLE_TSS))) { | |
6605 | tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) * | |
6606 | TG3_TX_RING_SIZE, | |
6607 | GFP_KERNEL); | |
6608 | if (!tnapi->tx_buffers) | |
6609 | goto err_out; | |
6610 | ||
6611 | tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev, | |
6612 | TG3_TX_RING_BYTES, | |
6613 | &tnapi->tx_desc_mapping, | |
6614 | GFP_KERNEL); | |
6615 | if (!tnapi->tx_ring) | |
6616 | goto err_out; | |
6617 | } | |
6618 | ||
6619 | /* | |
6620 | * When RSS is enabled, the status block format changes | |
6621 | * slightly. The "rx_jumbo_consumer", "reserved", | |
6622 | * and "rx_mini_consumer" members get mapped to the | |
6623 | * other three rx return ring producer indexes. | |
6624 | */ | |
6625 | switch (i) { | |
6626 | default: | |
6627 | tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer; | |
6628 | break; | |
6629 | case 2: | |
6630 | tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer; | |
6631 | break; | |
6632 | case 3: | |
6633 | tnapi->rx_rcb_prod_idx = &sblk->reserved; | |
6634 | break; | |
6635 | case 4: | |
6636 | tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer; | |
6637 | break; | |
6638 | } | |
6639 | ||
6640 | /* | |
6641 | * If multivector RSS is enabled, vector 0 does not handle | |
6642 | * rx or tx interrupts. Don't allocate any resources for it. | |
6643 | */ | |
6644 | if (!i && tg3_flag(tp, ENABLE_RSS)) | |
6645 | continue; | |
6646 | ||
6647 | tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev, | |
6648 | TG3_RX_RCB_RING_BYTES(tp), | |
6649 | &tnapi->rx_rcb_mapping, | |
6650 | GFP_KERNEL); | |
6651 | if (!tnapi->rx_rcb) | |
6652 | goto err_out; | |
6653 | ||
6654 | memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp)); | |
6655 | } | |
6656 | ||
6657 | return 0; | |
6658 | ||
6659 | err_out: | |
6660 | tg3_free_consistent(tp); | |
6661 | return -ENOMEM; | |
6662 | } | |
6663 | ||
6664 | #define MAX_WAIT_CNT 1000 | |
6665 | ||
6666 | /* To stop a block, clear the enable bit and poll till it | |
6667 | * clears. tp->lock is held. | |
6668 | */ | |
6669 | static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent) | |
6670 | { | |
6671 | unsigned int i; | |
6672 | u32 val; | |
6673 | ||
6674 | if (tg3_flag(tp, 5705_PLUS)) { | |
6675 | switch (ofs) { | |
6676 | case RCVLSC_MODE: | |
6677 | case DMAC_MODE: | |
6678 | case MBFREE_MODE: | |
6679 | case BUFMGR_MODE: | |
6680 | case MEMARB_MODE: | |
6681 | /* We can't enable/disable these bits of the | |
6682 | * 5705/5750, just say success. | |
6683 | */ | |
6684 | return 0; | |
6685 | ||
6686 | default: | |
6687 | break; | |
6688 | } | |
6689 | } | |
6690 | ||
6691 | val = tr32(ofs); | |
6692 | val &= ~enable_bit; | |
6693 | tw32_f(ofs, val); | |
6694 | ||
6695 | for (i = 0; i < MAX_WAIT_CNT; i++) { | |
6696 | udelay(100); | |
6697 | val = tr32(ofs); | |
6698 | if ((val & enable_bit) == 0) | |
6699 | break; | |
6700 | } | |
6701 | ||
6702 | if (i == MAX_WAIT_CNT && !silent) { | |
6703 | dev_err(&tp->pdev->dev, | |
6704 | "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n", | |
6705 | ofs, enable_bit); | |
6706 | return -ENODEV; | |
6707 | } | |
6708 | ||
6709 | return 0; | |
6710 | } | |
6711 | ||
6712 | /* tp->lock is held. */ | |
6713 | static int tg3_abort_hw(struct tg3 *tp, int silent) | |
6714 | { | |
6715 | int i, err; | |
6716 | ||
6717 | tg3_disable_ints(tp); | |
6718 | ||
6719 | tp->rx_mode &= ~RX_MODE_ENABLE; | |
6720 | tw32_f(MAC_RX_MODE, tp->rx_mode); | |
6721 | udelay(10); | |
6722 | ||
6723 | err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent); | |
6724 | err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent); | |
6725 | err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent); | |
6726 | err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent); | |
6727 | err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent); | |
6728 | err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent); | |
6729 | ||
6730 | err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent); | |
6731 | err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent); | |
6732 | err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent); | |
6733 | err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent); | |
6734 | err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent); | |
6735 | err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent); | |
6736 | err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent); | |
6737 | ||
6738 | tp->mac_mode &= ~MAC_MODE_TDE_ENABLE; | |
6739 | tw32_f(MAC_MODE, tp->mac_mode); | |
6740 | udelay(40); | |
6741 | ||
6742 | tp->tx_mode &= ~TX_MODE_ENABLE; | |
6743 | tw32_f(MAC_TX_MODE, tp->tx_mode); | |
6744 | ||
6745 | for (i = 0; i < MAX_WAIT_CNT; i++) { | |
6746 | udelay(100); | |
6747 | if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE)) | |
6748 | break; | |
6749 | } | |
6750 | if (i >= MAX_WAIT_CNT) { | |
6751 | dev_err(&tp->pdev->dev, | |
6752 | "%s timed out, TX_MODE_ENABLE will not clear " | |
6753 | "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE)); | |
6754 | err |= -ENODEV; | |
6755 | } | |
6756 | ||
6757 | err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent); | |
6758 | err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent); | |
6759 | err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent); | |
6760 | ||
6761 | tw32(FTQ_RESET, 0xffffffff); | |
6762 | tw32(FTQ_RESET, 0x00000000); | |
6763 | ||
6764 | err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent); | |
6765 | err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent); | |
6766 | ||
6767 | for (i = 0; i < tp->irq_cnt; i++) { | |
6768 | struct tg3_napi *tnapi = &tp->napi[i]; | |
6769 | if (tnapi->hw_status) | |
6770 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
6771 | } | |
6772 | if (tp->hw_stats) | |
6773 | memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats)); | |
6774 | ||
6775 | return err; | |
6776 | } | |
6777 | ||
6778 | static void tg3_ape_send_event(struct tg3 *tp, u32 event) | |
6779 | { | |
6780 | int i; | |
6781 | u32 apedata; | |
6782 | ||
6783 | /* NCSI does not support APE events */ | |
6784 | if (tg3_flag(tp, APE_HAS_NCSI)) | |
6785 | return; | |
6786 | ||
6787 | apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG); | |
6788 | if (apedata != APE_SEG_SIG_MAGIC) | |
6789 | return; | |
6790 | ||
6791 | apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); | |
6792 | if (!(apedata & APE_FW_STATUS_READY)) | |
6793 | return; | |
6794 | ||
6795 | /* Wait for up to 1 millisecond for APE to service previous event. */ | |
6796 | for (i = 0; i < 10; i++) { | |
6797 | if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM)) | |
6798 | return; | |
6799 | ||
6800 | apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS); | |
6801 | ||
6802 | if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) | |
6803 | tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, | |
6804 | event | APE_EVENT_STATUS_EVENT_PENDING); | |
6805 | ||
6806 | tg3_ape_unlock(tp, TG3_APE_LOCK_MEM); | |
6807 | ||
6808 | if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) | |
6809 | break; | |
6810 | ||
6811 | udelay(100); | |
6812 | } | |
6813 | ||
6814 | if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) | |
6815 | tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1); | |
6816 | } | |
6817 | ||
6818 | static void tg3_ape_driver_state_change(struct tg3 *tp, int kind) | |
6819 | { | |
6820 | u32 event; | |
6821 | u32 apedata; | |
6822 | ||
6823 | if (!tg3_flag(tp, ENABLE_APE)) | |
6824 | return; | |
6825 | ||
6826 | switch (kind) { | |
6827 | case RESET_KIND_INIT: | |
6828 | tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, | |
6829 | APE_HOST_SEG_SIG_MAGIC); | |
6830 | tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN, | |
6831 | APE_HOST_SEG_LEN_MAGIC); | |
6832 | apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT); | |
6833 | tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata); | |
6834 | tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID, | |
6835 | APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM)); | |
6836 | tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR, | |
6837 | APE_HOST_BEHAV_NO_PHYLOCK); | |
6838 | tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, | |
6839 | TG3_APE_HOST_DRVR_STATE_START); | |
6840 | ||
6841 | event = APE_EVENT_STATUS_STATE_START; | |
6842 | break; | |
6843 | case RESET_KIND_SHUTDOWN: | |
6844 | /* With the interface we are currently using, | |
6845 | * APE does not track driver state. Wiping | |
6846 | * out the HOST SEGMENT SIGNATURE forces | |
6847 | * the APE to assume OS absent status. | |
6848 | */ | |
6849 | tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0); | |
6850 | ||
6851 | if (device_may_wakeup(&tp->pdev->dev) && | |
6852 | tg3_flag(tp, WOL_ENABLE)) { | |
6853 | tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED, | |
6854 | TG3_APE_HOST_WOL_SPEED_AUTO); | |
6855 | apedata = TG3_APE_HOST_DRVR_STATE_WOL; | |
6856 | } else | |
6857 | apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD; | |
6858 | ||
6859 | tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata); | |
6860 | ||
6861 | event = APE_EVENT_STATUS_STATE_UNLOAD; | |
6862 | break; | |
6863 | case RESET_KIND_SUSPEND: | |
6864 | event = APE_EVENT_STATUS_STATE_SUSPEND; | |
6865 | break; | |
6866 | default: | |
6867 | return; | |
6868 | } | |
6869 | ||
6870 | event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE; | |
6871 | ||
6872 | tg3_ape_send_event(tp, event); | |
6873 | } | |
6874 | ||
6875 | /* tp->lock is held. */ | |
6876 | static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind) | |
6877 | { | |
6878 | tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX, | |
6879 | NIC_SRAM_FIRMWARE_MBOX_MAGIC1); | |
6880 | ||
6881 | if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) { | |
6882 | switch (kind) { | |
6883 | case RESET_KIND_INIT: | |
6884 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
6885 | DRV_STATE_START); | |
6886 | break; | |
6887 | ||
6888 | case RESET_KIND_SHUTDOWN: | |
6889 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
6890 | DRV_STATE_UNLOAD); | |
6891 | break; | |
6892 | ||
6893 | case RESET_KIND_SUSPEND: | |
6894 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
6895 | DRV_STATE_SUSPEND); | |
6896 | break; | |
6897 | ||
6898 | default: | |
6899 | break; | |
6900 | } | |
6901 | } | |
6902 | ||
6903 | if (kind == RESET_KIND_INIT || | |
6904 | kind == RESET_KIND_SUSPEND) | |
6905 | tg3_ape_driver_state_change(tp, kind); | |
6906 | } | |
6907 | ||
6908 | /* tp->lock is held. */ | |
6909 | static void tg3_write_sig_post_reset(struct tg3 *tp, int kind) | |
6910 | { | |
6911 | if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) { | |
6912 | switch (kind) { | |
6913 | case RESET_KIND_INIT: | |
6914 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
6915 | DRV_STATE_START_DONE); | |
6916 | break; | |
6917 | ||
6918 | case RESET_KIND_SHUTDOWN: | |
6919 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
6920 | DRV_STATE_UNLOAD_DONE); | |
6921 | break; | |
6922 | ||
6923 | default: | |
6924 | break; | |
6925 | } | |
6926 | } | |
6927 | ||
6928 | if (kind == RESET_KIND_SHUTDOWN) | |
6929 | tg3_ape_driver_state_change(tp, kind); | |
6930 | } | |
6931 | ||
6932 | /* tp->lock is held. */ | |
6933 | static void tg3_write_sig_legacy(struct tg3 *tp, int kind) | |
6934 | { | |
6935 | if (tg3_flag(tp, ENABLE_ASF)) { | |
6936 | switch (kind) { | |
6937 | case RESET_KIND_INIT: | |
6938 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
6939 | DRV_STATE_START); | |
6940 | break; | |
6941 | ||
6942 | case RESET_KIND_SHUTDOWN: | |
6943 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
6944 | DRV_STATE_UNLOAD); | |
6945 | break; | |
6946 | ||
6947 | case RESET_KIND_SUSPEND: | |
6948 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
6949 | DRV_STATE_SUSPEND); | |
6950 | break; | |
6951 | ||
6952 | default: | |
6953 | break; | |
6954 | } | |
6955 | } | |
6956 | } | |
6957 | ||
6958 | static int tg3_poll_fw(struct tg3 *tp) | |
6959 | { | |
6960 | int i; | |
6961 | u32 val; | |
6962 | ||
6963 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | |
6964 | /* Wait up to 20ms for init done. */ | |
6965 | for (i = 0; i < 200; i++) { | |
6966 | if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE) | |
6967 | return 0; | |
6968 | udelay(100); | |
6969 | } | |
6970 | return -ENODEV; | |
6971 | } | |
6972 | ||
6973 | /* Wait for firmware initialization to complete. */ | |
6974 | for (i = 0; i < 100000; i++) { | |
6975 | tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val); | |
6976 | if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1) | |
6977 | break; | |
6978 | udelay(10); | |
6979 | } | |
6980 | ||
6981 | /* Chip might not be fitted with firmware. Some Sun onboard | |
6982 | * parts are configured like that. So don't signal the timeout | |
6983 | * of the above loop as an error, but do report the lack of | |
6984 | * running firmware once. | |
6985 | */ | |
6986 | if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) { | |
6987 | tg3_flag_set(tp, NO_FWARE_REPORTED); | |
6988 | ||
6989 | netdev_info(tp->dev, "No firmware running\n"); | |
6990 | } | |
6991 | ||
6992 | if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) { | |
6993 | /* The 57765 A0 needs a little more | |
6994 | * time to do some important work. | |
6995 | */ | |
6996 | mdelay(10); | |
6997 | } | |
6998 | ||
6999 | return 0; | |
7000 | } | |
7001 | ||
7002 | /* Save PCI command register before chip reset */ | |
7003 | static void tg3_save_pci_state(struct tg3 *tp) | |
7004 | { | |
7005 | pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd); | |
7006 | } | |
7007 | ||
7008 | /* Restore PCI state after chip reset */ | |
7009 | static void tg3_restore_pci_state(struct tg3 *tp) | |
7010 | { | |
7011 | u32 val; | |
7012 | ||
7013 | /* Re-enable indirect register accesses. */ | |
7014 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
7015 | tp->misc_host_ctrl); | |
7016 | ||
7017 | /* Set MAX PCI retry to zero. */ | |
7018 | val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE); | |
7019 | if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 && | |
7020 | tg3_flag(tp, PCIX_MODE)) | |
7021 | val |= PCISTATE_RETRY_SAME_DMA; | |
7022 | /* Allow reads and writes to the APE register and memory space. */ | |
7023 | if (tg3_flag(tp, ENABLE_APE)) | |
7024 | val |= PCISTATE_ALLOW_APE_CTLSPC_WR | | |
7025 | PCISTATE_ALLOW_APE_SHMEM_WR | | |
7026 | PCISTATE_ALLOW_APE_PSPACE_WR; | |
7027 | pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val); | |
7028 | ||
7029 | pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd); | |
7030 | ||
7031 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) { | |
7032 | if (tg3_flag(tp, PCI_EXPRESS)) | |
7033 | pcie_set_readrq(tp->pdev, tp->pcie_readrq); | |
7034 | else { | |
7035 | pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, | |
7036 | tp->pci_cacheline_sz); | |
7037 | pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, | |
7038 | tp->pci_lat_timer); | |
7039 | } | |
7040 | } | |
7041 | ||
7042 | /* Make sure PCI-X relaxed ordering bit is clear. */ | |
7043 | if (tg3_flag(tp, PCIX_MODE)) { | |
7044 | u16 pcix_cmd; | |
7045 | ||
7046 | pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, | |
7047 | &pcix_cmd); | |
7048 | pcix_cmd &= ~PCI_X_CMD_ERO; | |
7049 | pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, | |
7050 | pcix_cmd); | |
7051 | } | |
7052 | ||
7053 | if (tg3_flag(tp, 5780_CLASS)) { | |
7054 | ||
7055 | /* Chip reset on 5780 will reset MSI enable bit, | |
7056 | * so need to restore it. | |
7057 | */ | |
7058 | if (tg3_flag(tp, USING_MSI)) { | |
7059 | u16 ctrl; | |
7060 | ||
7061 | pci_read_config_word(tp->pdev, | |
7062 | tp->msi_cap + PCI_MSI_FLAGS, | |
7063 | &ctrl); | |
7064 | pci_write_config_word(tp->pdev, | |
7065 | tp->msi_cap + PCI_MSI_FLAGS, | |
7066 | ctrl | PCI_MSI_FLAGS_ENABLE); | |
7067 | val = tr32(MSGINT_MODE); | |
7068 | tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE); | |
7069 | } | |
7070 | } | |
7071 | } | |
7072 | ||
7073 | static void tg3_stop_fw(struct tg3 *); | |
7074 | ||
7075 | /* tp->lock is held. */ | |
7076 | static int tg3_chip_reset(struct tg3 *tp) | |
7077 | { | |
7078 | u32 val; | |
7079 | void (*write_op)(struct tg3 *, u32, u32); | |
7080 | int i, err; | |
7081 | ||
7082 | tg3_nvram_lock(tp); | |
7083 | ||
7084 | tg3_ape_lock(tp, TG3_APE_LOCK_GRC); | |
7085 | ||
7086 | /* No matching tg3_nvram_unlock() after this because | |
7087 | * chip reset below will undo the nvram lock. | |
7088 | */ | |
7089 | tp->nvram_lock_cnt = 0; | |
7090 | ||
7091 | /* GRC_MISC_CFG core clock reset will clear the memory | |
7092 | * enable bit in PCI register 4 and the MSI enable bit | |
7093 | * on some chips, so we save relevant registers here. | |
7094 | */ | |
7095 | tg3_save_pci_state(tp); | |
7096 | ||
7097 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || | |
7098 | tg3_flag(tp, 5755_PLUS)) | |
7099 | tw32(GRC_FASTBOOT_PC, 0); | |
7100 | ||
7101 | /* | |
7102 | * We must avoid the readl() that normally takes place. | |
7103 | * It locks machines, causes machine checks, and other | |
7104 | * fun things. So, temporarily disable the 5701 | |
7105 | * hardware workaround, while we do the reset. | |
7106 | */ | |
7107 | write_op = tp->write32; | |
7108 | if (write_op == tg3_write_flush_reg32) | |
7109 | tp->write32 = tg3_write32; | |
7110 | ||
7111 | /* Prevent the irq handler from reading or writing PCI registers | |
7112 | * during chip reset when the memory enable bit in the PCI command | |
7113 | * register may be cleared. The chip does not generate interrupt | |
7114 | * at this time, but the irq handler may still be called due to irq | |
7115 | * sharing or irqpoll. | |
7116 | */ | |
7117 | tg3_flag_set(tp, CHIP_RESETTING); | |
7118 | for (i = 0; i < tp->irq_cnt; i++) { | |
7119 | struct tg3_napi *tnapi = &tp->napi[i]; | |
7120 | if (tnapi->hw_status) { | |
7121 | tnapi->hw_status->status = 0; | |
7122 | tnapi->hw_status->status_tag = 0; | |
7123 | } | |
7124 | tnapi->last_tag = 0; | |
7125 | tnapi->last_irq_tag = 0; | |
7126 | } | |
7127 | smp_mb(); | |
7128 | ||
7129 | for (i = 0; i < tp->irq_cnt; i++) | |
7130 | synchronize_irq(tp->napi[i].irq_vec); | |
7131 | ||
7132 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { | |
7133 | val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN; | |
7134 | tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS); | |
7135 | } | |
7136 | ||
7137 | /* do the reset */ | |
7138 | val = GRC_MISC_CFG_CORECLK_RESET; | |
7139 | ||
7140 | if (tg3_flag(tp, PCI_EXPRESS)) { | |
7141 | /* Force PCIe 1.0a mode */ | |
7142 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && | |
7143 | !tg3_flag(tp, 57765_PLUS) && | |
7144 | tr32(TG3_PCIE_PHY_TSTCTL) == | |
7145 | (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM)) | |
7146 | tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM); | |
7147 | ||
7148 | if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) { | |
7149 | tw32(GRC_MISC_CFG, (1 << 29)); | |
7150 | val |= (1 << 29); | |
7151 | } | |
7152 | } | |
7153 | ||
7154 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | |
7155 | tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET); | |
7156 | tw32(GRC_VCPU_EXT_CTRL, | |
7157 | tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU); | |
7158 | } | |
7159 | ||
7160 | /* Manage gphy power for all CPMU absent PCIe devices. */ | |
7161 | if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT)) | |
7162 | val |= GRC_MISC_CFG_KEEP_GPHY_POWER; | |
7163 | ||
7164 | tw32(GRC_MISC_CFG, val); | |
7165 | ||
7166 | /* restore 5701 hardware bug workaround write method */ | |
7167 | tp->write32 = write_op; | |
7168 | ||
7169 | /* Unfortunately, we have to delay before the PCI read back. | |
7170 | * Some 575X chips even will not respond to a PCI cfg access | |
7171 | * when the reset command is given to the chip. | |
7172 | * | |
7173 | * How do these hardware designers expect things to work | |
7174 | * properly if the PCI write is posted for a long period | |
7175 | * of time? It is always necessary to have some method by | |
7176 | * which a register read back can occur to push the write | |
7177 | * out which does the reset. | |
7178 | * | |
7179 | * For most tg3 variants the trick below was working. | |
7180 | * Ho hum... | |
7181 | */ | |
7182 | udelay(120); | |
7183 | ||
7184 | /* Flush PCI posted writes. The normal MMIO registers | |
7185 | * are inaccessible at this time so this is the only | |
7186 | * way to make this reliably (actually, this is no longer | |
7187 | * the case, see above). I tried to use indirect | |
7188 | * register read/write but this upset some 5701 variants. | |
7189 | */ | |
7190 | pci_read_config_dword(tp->pdev, PCI_COMMAND, &val); | |
7191 | ||
7192 | udelay(120); | |
7193 | ||
7194 | if (tg3_flag(tp, PCI_EXPRESS) && tp->pcie_cap) { | |
7195 | u16 val16; | |
7196 | ||
7197 | if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) { | |
7198 | int i; | |
7199 | u32 cfg_val; | |
7200 | ||
7201 | /* Wait for link training to complete. */ | |
7202 | for (i = 0; i < 5000; i++) | |
7203 | udelay(100); | |
7204 | ||
7205 | pci_read_config_dword(tp->pdev, 0xc4, &cfg_val); | |
7206 | pci_write_config_dword(tp->pdev, 0xc4, | |
7207 | cfg_val | (1 << 15)); | |
7208 | } | |
7209 | ||
7210 | /* Clear the "no snoop" and "relaxed ordering" bits. */ | |
7211 | pci_read_config_word(tp->pdev, | |
7212 | tp->pcie_cap + PCI_EXP_DEVCTL, | |
7213 | &val16); | |
7214 | val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN | | |
7215 | PCI_EXP_DEVCTL_NOSNOOP_EN); | |
7216 | /* | |
7217 | * Older PCIe devices only support the 128 byte | |
7218 | * MPS setting. Enforce the restriction. | |
7219 | */ | |
7220 | if (!tg3_flag(tp, CPMU_PRESENT)) | |
7221 | val16 &= ~PCI_EXP_DEVCTL_PAYLOAD; | |
7222 | pci_write_config_word(tp->pdev, | |
7223 | tp->pcie_cap + PCI_EXP_DEVCTL, | |
7224 | val16); | |
7225 | ||
7226 | pcie_set_readrq(tp->pdev, tp->pcie_readrq); | |
7227 | ||
7228 | /* Clear error status */ | |
7229 | pci_write_config_word(tp->pdev, | |
7230 | tp->pcie_cap + PCI_EXP_DEVSTA, | |
7231 | PCI_EXP_DEVSTA_CED | | |
7232 | PCI_EXP_DEVSTA_NFED | | |
7233 | PCI_EXP_DEVSTA_FED | | |
7234 | PCI_EXP_DEVSTA_URD); | |
7235 | } | |
7236 | ||
7237 | tg3_restore_pci_state(tp); | |
7238 | ||
7239 | tg3_flag_clear(tp, CHIP_RESETTING); | |
7240 | tg3_flag_clear(tp, ERROR_PROCESSED); | |
7241 | ||
7242 | val = 0; | |
7243 | if (tg3_flag(tp, 5780_CLASS)) | |
7244 | val = tr32(MEMARB_MODE); | |
7245 | tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE); | |
7246 | ||
7247 | if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) { | |
7248 | tg3_stop_fw(tp); | |
7249 | tw32(0x5000, 0x400); | |
7250 | } | |
7251 | ||
7252 | tw32(GRC_MODE, tp->grc_mode); | |
7253 | ||
7254 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) { | |
7255 | val = tr32(0xc4); | |
7256 | ||
7257 | tw32(0xc4, val | (1 << 15)); | |
7258 | } | |
7259 | ||
7260 | if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 && | |
7261 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | |
7262 | tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE; | |
7263 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) | |
7264 | tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN; | |
7265 | tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); | |
7266 | } | |
7267 | ||
7268 | if (tg3_flag(tp, ENABLE_APE)) | |
7269 | tp->mac_mode = MAC_MODE_APE_TX_EN | | |
7270 | MAC_MODE_APE_RX_EN | | |
7271 | MAC_MODE_TDE_ENABLE; | |
7272 | ||
7273 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { | |
7274 | tp->mac_mode |= MAC_MODE_PORT_MODE_TBI; | |
7275 | val = tp->mac_mode; | |
7276 | } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { | |
7277 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
7278 | val = tp->mac_mode; | |
7279 | } else | |
7280 | val = 0; | |
7281 | ||
7282 | tw32_f(MAC_MODE, val); | |
7283 | udelay(40); | |
7284 | ||
7285 | tg3_ape_unlock(tp, TG3_APE_LOCK_GRC); | |
7286 | ||
7287 | err = tg3_poll_fw(tp); | |
7288 | if (err) | |
7289 | return err; | |
7290 | ||
7291 | tg3_mdio_start(tp); | |
7292 | ||
7293 | if (tg3_flag(tp, PCI_EXPRESS) && | |
7294 | tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 && | |
7295 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && | |
7296 | !tg3_flag(tp, 57765_PLUS)) { | |
7297 | val = tr32(0x7c00); | |
7298 | ||
7299 | tw32(0x7c00, val | (1 << 25)); | |
7300 | } | |
7301 | ||
7302 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
7303 | val = tr32(TG3_CPMU_CLCK_ORIDE); | |
7304 | tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN); | |
7305 | } | |
7306 | ||
7307 | /* Reprobe ASF enable state. */ | |
7308 | tg3_flag_clear(tp, ENABLE_ASF); | |
7309 | tg3_flag_clear(tp, ASF_NEW_HANDSHAKE); | |
7310 | tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); | |
7311 | if (val == NIC_SRAM_DATA_SIG_MAGIC) { | |
7312 | u32 nic_cfg; | |
7313 | ||
7314 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg); | |
7315 | if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) { | |
7316 | tg3_flag_set(tp, ENABLE_ASF); | |
7317 | tp->last_event_jiffies = jiffies; | |
7318 | if (tg3_flag(tp, 5750_PLUS)) | |
7319 | tg3_flag_set(tp, ASF_NEW_HANDSHAKE); | |
7320 | } | |
7321 | } | |
7322 | ||
7323 | return 0; | |
7324 | } | |
7325 | ||
7326 | /* tp->lock is held. */ | |
7327 | static void tg3_stop_fw(struct tg3 *tp) | |
7328 | { | |
7329 | if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) { | |
7330 | /* Wait for RX cpu to ACK the previous event. */ | |
7331 | tg3_wait_for_event_ack(tp); | |
7332 | ||
7333 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW); | |
7334 | ||
7335 | tg3_generate_fw_event(tp); | |
7336 | ||
7337 | /* Wait for RX cpu to ACK this event. */ | |
7338 | tg3_wait_for_event_ack(tp); | |
7339 | } | |
7340 | } | |
7341 | ||
7342 | /* tp->lock is held. */ | |
7343 | static int tg3_halt(struct tg3 *tp, int kind, int silent) | |
7344 | { | |
7345 | int err; | |
7346 | ||
7347 | tg3_stop_fw(tp); | |
7348 | ||
7349 | tg3_write_sig_pre_reset(tp, kind); | |
7350 | ||
7351 | tg3_abort_hw(tp, silent); | |
7352 | err = tg3_chip_reset(tp); | |
7353 | ||
7354 | __tg3_set_mac_addr(tp, 0); | |
7355 | ||
7356 | tg3_write_sig_legacy(tp, kind); | |
7357 | tg3_write_sig_post_reset(tp, kind); | |
7358 | ||
7359 | if (err) | |
7360 | return err; | |
7361 | ||
7362 | return 0; | |
7363 | } | |
7364 | ||
7365 | #define RX_CPU_SCRATCH_BASE 0x30000 | |
7366 | #define RX_CPU_SCRATCH_SIZE 0x04000 | |
7367 | #define TX_CPU_SCRATCH_BASE 0x34000 | |
7368 | #define TX_CPU_SCRATCH_SIZE 0x04000 | |
7369 | ||
7370 | /* tp->lock is held. */ | |
7371 | static int tg3_halt_cpu(struct tg3 *tp, u32 offset) | |
7372 | { | |
7373 | int i; | |
7374 | ||
7375 | BUG_ON(offset == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)); | |
7376 | ||
7377 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | |
7378 | u32 val = tr32(GRC_VCPU_EXT_CTRL); | |
7379 | ||
7380 | tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU); | |
7381 | return 0; | |
7382 | } | |
7383 | if (offset == RX_CPU_BASE) { | |
7384 | for (i = 0; i < 10000; i++) { | |
7385 | tw32(offset + CPU_STATE, 0xffffffff); | |
7386 | tw32(offset + CPU_MODE, CPU_MODE_HALT); | |
7387 | if (tr32(offset + CPU_MODE) & CPU_MODE_HALT) | |
7388 | break; | |
7389 | } | |
7390 | ||
7391 | tw32(offset + CPU_STATE, 0xffffffff); | |
7392 | tw32_f(offset + CPU_MODE, CPU_MODE_HALT); | |
7393 | udelay(10); | |
7394 | } else { | |
7395 | for (i = 0; i < 10000; i++) { | |
7396 | tw32(offset + CPU_STATE, 0xffffffff); | |
7397 | tw32(offset + CPU_MODE, CPU_MODE_HALT); | |
7398 | if (tr32(offset + CPU_MODE) & CPU_MODE_HALT) | |
7399 | break; | |
7400 | } | |
7401 | } | |
7402 | ||
7403 | if (i >= 10000) { | |
7404 | netdev_err(tp->dev, "%s timed out, %s CPU\n", | |
7405 | __func__, offset == RX_CPU_BASE ? "RX" : "TX"); | |
7406 | return -ENODEV; | |
7407 | } | |
7408 | ||
7409 | /* Clear firmware's nvram arbitration. */ | |
7410 | if (tg3_flag(tp, NVRAM)) | |
7411 | tw32(NVRAM_SWARB, SWARB_REQ_CLR0); | |
7412 | return 0; | |
7413 | } | |
7414 | ||
7415 | struct fw_info { | |
7416 | unsigned int fw_base; | |
7417 | unsigned int fw_len; | |
7418 | const __be32 *fw_data; | |
7419 | }; | |
7420 | ||
7421 | /* tp->lock is held. */ | |
7422 | static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base, | |
7423 | int cpu_scratch_size, struct fw_info *info) | |
7424 | { | |
7425 | int err, lock_err, i; | |
7426 | void (*write_op)(struct tg3 *, u32, u32); | |
7427 | ||
7428 | if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) { | |
7429 | netdev_err(tp->dev, | |
7430 | "%s: Trying to load TX cpu firmware which is 5705\n", | |
7431 | __func__); | |
7432 | return -EINVAL; | |
7433 | } | |
7434 | ||
7435 | if (tg3_flag(tp, 5705_PLUS)) | |
7436 | write_op = tg3_write_mem; | |
7437 | else | |
7438 | write_op = tg3_write_indirect_reg32; | |
7439 | ||
7440 | /* It is possible that bootcode is still loading at this point. | |
7441 | * Get the nvram lock first before halting the cpu. | |
7442 | */ | |
7443 | lock_err = tg3_nvram_lock(tp); | |
7444 | err = tg3_halt_cpu(tp, cpu_base); | |
7445 | if (!lock_err) | |
7446 | tg3_nvram_unlock(tp); | |
7447 | if (err) | |
7448 | goto out; | |
7449 | ||
7450 | for (i = 0; i < cpu_scratch_size; i += sizeof(u32)) | |
7451 | write_op(tp, cpu_scratch_base + i, 0); | |
7452 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
7453 | tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT); | |
7454 | for (i = 0; i < (info->fw_len / sizeof(u32)); i++) | |
7455 | write_op(tp, (cpu_scratch_base + | |
7456 | (info->fw_base & 0xffff) + | |
7457 | (i * sizeof(u32))), | |
7458 | be32_to_cpu(info->fw_data[i])); | |
7459 | ||
7460 | err = 0; | |
7461 | ||
7462 | out: | |
7463 | return err; | |
7464 | } | |
7465 | ||
7466 | /* tp->lock is held. */ | |
7467 | static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp) | |
7468 | { | |
7469 | struct fw_info info; | |
7470 | const __be32 *fw_data; | |
7471 | int err, i; | |
7472 | ||
7473 | fw_data = (void *)tp->fw->data; | |
7474 | ||
7475 | /* Firmware blob starts with version numbers, followed by | |
7476 | start address and length. We are setting complete length. | |
7477 | length = end_address_of_bss - start_address_of_text. | |
7478 | Remainder is the blob to be loaded contiguously | |
7479 | from start address. */ | |
7480 | ||
7481 | info.fw_base = be32_to_cpu(fw_data[1]); | |
7482 | info.fw_len = tp->fw->size - 12; | |
7483 | info.fw_data = &fw_data[3]; | |
7484 | ||
7485 | err = tg3_load_firmware_cpu(tp, RX_CPU_BASE, | |
7486 | RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE, | |
7487 | &info); | |
7488 | if (err) | |
7489 | return err; | |
7490 | ||
7491 | err = tg3_load_firmware_cpu(tp, TX_CPU_BASE, | |
7492 | TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE, | |
7493 | &info); | |
7494 | if (err) | |
7495 | return err; | |
7496 | ||
7497 | /* Now startup only the RX cpu. */ | |
7498 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); | |
7499 | tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base); | |
7500 | ||
7501 | for (i = 0; i < 5; i++) { | |
7502 | if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base) | |
7503 | break; | |
7504 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); | |
7505 | tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT); | |
7506 | tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base); | |
7507 | udelay(1000); | |
7508 | } | |
7509 | if (i >= 5) { | |
7510 | netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x " | |
7511 | "should be %08x\n", __func__, | |
7512 | tr32(RX_CPU_BASE + CPU_PC), info.fw_base); | |
7513 | return -ENODEV; | |
7514 | } | |
7515 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); | |
7516 | tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000); | |
7517 | ||
7518 | return 0; | |
7519 | } | |
7520 | ||
7521 | /* tp->lock is held. */ | |
7522 | static int tg3_load_tso_firmware(struct tg3 *tp) | |
7523 | { | |
7524 | struct fw_info info; | |
7525 | const __be32 *fw_data; | |
7526 | unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size; | |
7527 | int err, i; | |
7528 | ||
7529 | if (tg3_flag(tp, HW_TSO_1) || | |
7530 | tg3_flag(tp, HW_TSO_2) || | |
7531 | tg3_flag(tp, HW_TSO_3)) | |
7532 | return 0; | |
7533 | ||
7534 | fw_data = (void *)tp->fw->data; | |
7535 | ||
7536 | /* Firmware blob starts with version numbers, followed by | |
7537 | start address and length. We are setting complete length. | |
7538 | length = end_address_of_bss - start_address_of_text. | |
7539 | Remainder is the blob to be loaded contiguously | |
7540 | from start address. */ | |
7541 | ||
7542 | info.fw_base = be32_to_cpu(fw_data[1]); | |
7543 | cpu_scratch_size = tp->fw_len; | |
7544 | info.fw_len = tp->fw->size - 12; | |
7545 | info.fw_data = &fw_data[3]; | |
7546 | ||
7547 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | |
7548 | cpu_base = RX_CPU_BASE; | |
7549 | cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705; | |
7550 | } else { | |
7551 | cpu_base = TX_CPU_BASE; | |
7552 | cpu_scratch_base = TX_CPU_SCRATCH_BASE; | |
7553 | cpu_scratch_size = TX_CPU_SCRATCH_SIZE; | |
7554 | } | |
7555 | ||
7556 | err = tg3_load_firmware_cpu(tp, cpu_base, | |
7557 | cpu_scratch_base, cpu_scratch_size, | |
7558 | &info); | |
7559 | if (err) | |
7560 | return err; | |
7561 | ||
7562 | /* Now startup the cpu. */ | |
7563 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
7564 | tw32_f(cpu_base + CPU_PC, info.fw_base); | |
7565 | ||
7566 | for (i = 0; i < 5; i++) { | |
7567 | if (tr32(cpu_base + CPU_PC) == info.fw_base) | |
7568 | break; | |
7569 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
7570 | tw32(cpu_base + CPU_MODE, CPU_MODE_HALT); | |
7571 | tw32_f(cpu_base + CPU_PC, info.fw_base); | |
7572 | udelay(1000); | |
7573 | } | |
7574 | if (i >= 5) { | |
7575 | netdev_err(tp->dev, | |
7576 | "%s fails to set CPU PC, is %08x should be %08x\n", | |
7577 | __func__, tr32(cpu_base + CPU_PC), info.fw_base); | |
7578 | return -ENODEV; | |
7579 | } | |
7580 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
7581 | tw32_f(cpu_base + CPU_MODE, 0x00000000); | |
7582 | return 0; | |
7583 | } | |
7584 | ||
7585 | ||
7586 | static int tg3_set_mac_addr(struct net_device *dev, void *p) | |
7587 | { | |
7588 | struct tg3 *tp = netdev_priv(dev); | |
7589 | struct sockaddr *addr = p; | |
7590 | int err = 0, skip_mac_1 = 0; | |
7591 | ||
7592 | if (!is_valid_ether_addr(addr->sa_data)) | |
7593 | return -EINVAL; | |
7594 | ||
7595 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); | |
7596 | ||
7597 | if (!netif_running(dev)) | |
7598 | return 0; | |
7599 | ||
7600 | if (tg3_flag(tp, ENABLE_ASF)) { | |
7601 | u32 addr0_high, addr0_low, addr1_high, addr1_low; | |
7602 | ||
7603 | addr0_high = tr32(MAC_ADDR_0_HIGH); | |
7604 | addr0_low = tr32(MAC_ADDR_0_LOW); | |
7605 | addr1_high = tr32(MAC_ADDR_1_HIGH); | |
7606 | addr1_low = tr32(MAC_ADDR_1_LOW); | |
7607 | ||
7608 | /* Skip MAC addr 1 if ASF is using it. */ | |
7609 | if ((addr0_high != addr1_high || addr0_low != addr1_low) && | |
7610 | !(addr1_high == 0 && addr1_low == 0)) | |
7611 | skip_mac_1 = 1; | |
7612 | } | |
7613 | spin_lock_bh(&tp->lock); | |
7614 | __tg3_set_mac_addr(tp, skip_mac_1); | |
7615 | spin_unlock_bh(&tp->lock); | |
7616 | ||
7617 | return err; | |
7618 | } | |
7619 | ||
7620 | /* tp->lock is held. */ | |
7621 | static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr, | |
7622 | dma_addr_t mapping, u32 maxlen_flags, | |
7623 | u32 nic_addr) | |
7624 | { | |
7625 | tg3_write_mem(tp, | |
7626 | (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH), | |
7627 | ((u64) mapping >> 32)); | |
7628 | tg3_write_mem(tp, | |
7629 | (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW), | |
7630 | ((u64) mapping & 0xffffffff)); | |
7631 | tg3_write_mem(tp, | |
7632 | (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS), | |
7633 | maxlen_flags); | |
7634 | ||
7635 | if (!tg3_flag(tp, 5705_PLUS)) | |
7636 | tg3_write_mem(tp, | |
7637 | (bdinfo_addr + TG3_BDINFO_NIC_ADDR), | |
7638 | nic_addr); | |
7639 | } | |
7640 | ||
7641 | static void __tg3_set_rx_mode(struct net_device *); | |
7642 | static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec) | |
7643 | { | |
7644 | int i; | |
7645 | ||
7646 | if (!tg3_flag(tp, ENABLE_TSS)) { | |
7647 | tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs); | |
7648 | tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames); | |
7649 | tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq); | |
7650 | } else { | |
7651 | tw32(HOSTCC_TXCOL_TICKS, 0); | |
7652 | tw32(HOSTCC_TXMAX_FRAMES, 0); | |
7653 | tw32(HOSTCC_TXCOAL_MAXF_INT, 0); | |
7654 | } | |
7655 | ||
7656 | if (!tg3_flag(tp, ENABLE_RSS)) { | |
7657 | tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs); | |
7658 | tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames); | |
7659 | tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq); | |
7660 | } else { | |
7661 | tw32(HOSTCC_RXCOL_TICKS, 0); | |
7662 | tw32(HOSTCC_RXMAX_FRAMES, 0); | |
7663 | tw32(HOSTCC_RXCOAL_MAXF_INT, 0); | |
7664 | } | |
7665 | ||
7666 | if (!tg3_flag(tp, 5705_PLUS)) { | |
7667 | u32 val = ec->stats_block_coalesce_usecs; | |
7668 | ||
7669 | tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq); | |
7670 | tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq); | |
7671 | ||
7672 | if (!netif_carrier_ok(tp->dev)) | |
7673 | val = 0; | |
7674 | ||
7675 | tw32(HOSTCC_STAT_COAL_TICKS, val); | |
7676 | } | |
7677 | ||
7678 | for (i = 0; i < tp->irq_cnt - 1; i++) { | |
7679 | u32 reg; | |
7680 | ||
7681 | reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18; | |
7682 | tw32(reg, ec->rx_coalesce_usecs); | |
7683 | reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18; | |
7684 | tw32(reg, ec->rx_max_coalesced_frames); | |
7685 | reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18; | |
7686 | tw32(reg, ec->rx_max_coalesced_frames_irq); | |
7687 | ||
7688 | if (tg3_flag(tp, ENABLE_TSS)) { | |
7689 | reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18; | |
7690 | tw32(reg, ec->tx_coalesce_usecs); | |
7691 | reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18; | |
7692 | tw32(reg, ec->tx_max_coalesced_frames); | |
7693 | reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18; | |
7694 | tw32(reg, ec->tx_max_coalesced_frames_irq); | |
7695 | } | |
7696 | } | |
7697 | ||
7698 | for (; i < tp->irq_max - 1; i++) { | |
7699 | tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0); | |
7700 | tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0); | |
7701 | tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0); | |
7702 | ||
7703 | if (tg3_flag(tp, ENABLE_TSS)) { | |
7704 | tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0); | |
7705 | tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0); | |
7706 | tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0); | |
7707 | } | |
7708 | } | |
7709 | } | |
7710 | ||
7711 | /* tp->lock is held. */ | |
7712 | static void tg3_rings_reset(struct tg3 *tp) | |
7713 | { | |
7714 | int i; | |
7715 | u32 stblk, txrcb, rxrcb, limit; | |
7716 | struct tg3_napi *tnapi = &tp->napi[0]; | |
7717 | ||
7718 | /* Disable all transmit rings but the first. */ | |
7719 | if (!tg3_flag(tp, 5705_PLUS)) | |
7720 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16; | |
7721 | else if (tg3_flag(tp, 5717_PLUS)) | |
7722 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4; | |
7723 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
7724 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2; | |
7725 | else | |
7726 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; | |
7727 | ||
7728 | for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; | |
7729 | txrcb < limit; txrcb += TG3_BDINFO_SIZE) | |
7730 | tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS, | |
7731 | BDINFO_FLAGS_DISABLED); | |
7732 | ||
7733 | ||
7734 | /* Disable all receive return rings but the first. */ | |
7735 | if (tg3_flag(tp, 5717_PLUS)) | |
7736 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17; | |
7737 | else if (!tg3_flag(tp, 5705_PLUS)) | |
7738 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16; | |
7739 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || | |
7740 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
7741 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4; | |
7742 | else | |
7743 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE; | |
7744 | ||
7745 | for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE; | |
7746 | rxrcb < limit; rxrcb += TG3_BDINFO_SIZE) | |
7747 | tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS, | |
7748 | BDINFO_FLAGS_DISABLED); | |
7749 | ||
7750 | /* Disable interrupts */ | |
7751 | tw32_mailbox_f(tp->napi[0].int_mbox, 1); | |
7752 | tp->napi[0].chk_msi_cnt = 0; | |
7753 | tp->napi[0].last_rx_cons = 0; | |
7754 | tp->napi[0].last_tx_cons = 0; | |
7755 | ||
7756 | /* Zero mailbox registers. */ | |
7757 | if (tg3_flag(tp, SUPPORT_MSIX)) { | |
7758 | for (i = 1; i < tp->irq_max; i++) { | |
7759 | tp->napi[i].tx_prod = 0; | |
7760 | tp->napi[i].tx_cons = 0; | |
7761 | if (tg3_flag(tp, ENABLE_TSS)) | |
7762 | tw32_mailbox(tp->napi[i].prodmbox, 0); | |
7763 | tw32_rx_mbox(tp->napi[i].consmbox, 0); | |
7764 | tw32_mailbox_f(tp->napi[i].int_mbox, 1); | |
7765 | tp->napi[0].chk_msi_cnt = 0; | |
7766 | tp->napi[i].last_rx_cons = 0; | |
7767 | tp->napi[i].last_tx_cons = 0; | |
7768 | } | |
7769 | if (!tg3_flag(tp, ENABLE_TSS)) | |
7770 | tw32_mailbox(tp->napi[0].prodmbox, 0); | |
7771 | } else { | |
7772 | tp->napi[0].tx_prod = 0; | |
7773 | tp->napi[0].tx_cons = 0; | |
7774 | tw32_mailbox(tp->napi[0].prodmbox, 0); | |
7775 | tw32_rx_mbox(tp->napi[0].consmbox, 0); | |
7776 | } | |
7777 | ||
7778 | /* Make sure the NIC-based send BD rings are disabled. */ | |
7779 | if (!tg3_flag(tp, 5705_PLUS)) { | |
7780 | u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW; | |
7781 | for (i = 0; i < 16; i++) | |
7782 | tw32_tx_mbox(mbox + i * 8, 0); | |
7783 | } | |
7784 | ||
7785 | txrcb = NIC_SRAM_SEND_RCB; | |
7786 | rxrcb = NIC_SRAM_RCV_RET_RCB; | |
7787 | ||
7788 | /* Clear status block in ram. */ | |
7789 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
7790 | ||
7791 | /* Set status block DMA address */ | |
7792 | tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, | |
7793 | ((u64) tnapi->status_mapping >> 32)); | |
7794 | tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, | |
7795 | ((u64) tnapi->status_mapping & 0xffffffff)); | |
7796 | ||
7797 | if (tnapi->tx_ring) { | |
7798 | tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping, | |
7799 | (TG3_TX_RING_SIZE << | |
7800 | BDINFO_FLAGS_MAXLEN_SHIFT), | |
7801 | NIC_SRAM_TX_BUFFER_DESC); | |
7802 | txrcb += TG3_BDINFO_SIZE; | |
7803 | } | |
7804 | ||
7805 | if (tnapi->rx_rcb) { | |
7806 | tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping, | |
7807 | (tp->rx_ret_ring_mask + 1) << | |
7808 | BDINFO_FLAGS_MAXLEN_SHIFT, 0); | |
7809 | rxrcb += TG3_BDINFO_SIZE; | |
7810 | } | |
7811 | ||
7812 | stblk = HOSTCC_STATBLCK_RING1; | |
7813 | ||
7814 | for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) { | |
7815 | u64 mapping = (u64)tnapi->status_mapping; | |
7816 | tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32); | |
7817 | tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff); | |
7818 | ||
7819 | /* Clear status block in ram. */ | |
7820 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
7821 | ||
7822 | if (tnapi->tx_ring) { | |
7823 | tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping, | |
7824 | (TG3_TX_RING_SIZE << | |
7825 | BDINFO_FLAGS_MAXLEN_SHIFT), | |
7826 | NIC_SRAM_TX_BUFFER_DESC); | |
7827 | txrcb += TG3_BDINFO_SIZE; | |
7828 | } | |
7829 | ||
7830 | tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping, | |
7831 | ((tp->rx_ret_ring_mask + 1) << | |
7832 | BDINFO_FLAGS_MAXLEN_SHIFT), 0); | |
7833 | ||
7834 | stblk += 8; | |
7835 | rxrcb += TG3_BDINFO_SIZE; | |
7836 | } | |
7837 | } | |
7838 | ||
7839 | static void tg3_setup_rxbd_thresholds(struct tg3 *tp) | |
7840 | { | |
7841 | u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh; | |
7842 | ||
7843 | if (!tg3_flag(tp, 5750_PLUS) || | |
7844 | tg3_flag(tp, 5780_CLASS) || | |
7845 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || | |
7846 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) | |
7847 | bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700; | |
7848 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || | |
7849 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) | |
7850 | bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755; | |
7851 | else | |
7852 | bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906; | |
7853 | ||
7854 | nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post); | |
7855 | host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1); | |
7856 | ||
7857 | val = min(nic_rep_thresh, host_rep_thresh); | |
7858 | tw32(RCVBDI_STD_THRESH, val); | |
7859 | ||
7860 | if (tg3_flag(tp, 57765_PLUS)) | |
7861 | tw32(STD_REPLENISH_LWM, bdcache_maxcnt); | |
7862 | ||
7863 | if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS)) | |
7864 | return; | |
7865 | ||
7866 | if (!tg3_flag(tp, 5705_PLUS)) | |
7867 | bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700; | |
7868 | else | |
7869 | bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5717; | |
7870 | ||
7871 | host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1); | |
7872 | ||
7873 | val = min(bdcache_maxcnt / 2, host_rep_thresh); | |
7874 | tw32(RCVBDI_JUMBO_THRESH, val); | |
7875 | ||
7876 | if (tg3_flag(tp, 57765_PLUS)) | |
7877 | tw32(JMB_REPLENISH_LWM, bdcache_maxcnt); | |
7878 | } | |
7879 | ||
7880 | /* tp->lock is held. */ | |
7881 | static int tg3_reset_hw(struct tg3 *tp, int reset_phy) | |
7882 | { | |
7883 | u32 val, rdmac_mode; | |
7884 | int i, err, limit; | |
7885 | struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring; | |
7886 | ||
7887 | tg3_disable_ints(tp); | |
7888 | ||
7889 | tg3_stop_fw(tp); | |
7890 | ||
7891 | tg3_write_sig_pre_reset(tp, RESET_KIND_INIT); | |
7892 | ||
7893 | if (tg3_flag(tp, INIT_COMPLETE)) | |
7894 | tg3_abort_hw(tp, 1); | |
7895 | ||
7896 | /* Enable MAC control of LPI */ | |
7897 | if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) { | |
7898 | tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL, | |
7899 | TG3_CPMU_EEE_LNKIDL_PCIE_NL0 | | |
7900 | TG3_CPMU_EEE_LNKIDL_UART_IDL); | |
7901 | ||
7902 | tw32_f(TG3_CPMU_EEE_CTRL, | |
7903 | TG3_CPMU_EEE_CTRL_EXIT_20_1_US); | |
7904 | ||
7905 | val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET | | |
7906 | TG3_CPMU_EEEMD_LPI_IN_TX | | |
7907 | TG3_CPMU_EEEMD_LPI_IN_RX | | |
7908 | TG3_CPMU_EEEMD_EEE_ENABLE; | |
7909 | ||
7910 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) | |
7911 | val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN; | |
7912 | ||
7913 | if (tg3_flag(tp, ENABLE_APE)) | |
7914 | val |= TG3_CPMU_EEEMD_APE_TX_DET_EN; | |
7915 | ||
7916 | tw32_f(TG3_CPMU_EEE_MODE, val); | |
7917 | ||
7918 | tw32_f(TG3_CPMU_EEE_DBTMR1, | |
7919 | TG3_CPMU_DBTMR1_PCIEXIT_2047US | | |
7920 | TG3_CPMU_DBTMR1_LNKIDLE_2047US); | |
7921 | ||
7922 | tw32_f(TG3_CPMU_EEE_DBTMR2, | |
7923 | TG3_CPMU_DBTMR2_APE_TX_2047US | | |
7924 | TG3_CPMU_DBTMR2_TXIDXEQ_2047US); | |
7925 | } | |
7926 | ||
7927 | if (reset_phy) | |
7928 | tg3_phy_reset(tp); | |
7929 | ||
7930 | err = tg3_chip_reset(tp); | |
7931 | if (err) | |
7932 | return err; | |
7933 | ||
7934 | tg3_write_sig_legacy(tp, RESET_KIND_INIT); | |
7935 | ||
7936 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) { | |
7937 | val = tr32(TG3_CPMU_CTRL); | |
7938 | val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE); | |
7939 | tw32(TG3_CPMU_CTRL, val); | |
7940 | ||
7941 | val = tr32(TG3_CPMU_LSPD_10MB_CLK); | |
7942 | val &= ~CPMU_LSPD_10MB_MACCLK_MASK; | |
7943 | val |= CPMU_LSPD_10MB_MACCLK_6_25; | |
7944 | tw32(TG3_CPMU_LSPD_10MB_CLK, val); | |
7945 | ||
7946 | val = tr32(TG3_CPMU_LNK_AWARE_PWRMD); | |
7947 | val &= ~CPMU_LNK_AWARE_MACCLK_MASK; | |
7948 | val |= CPMU_LNK_AWARE_MACCLK_6_25; | |
7949 | tw32(TG3_CPMU_LNK_AWARE_PWRMD, val); | |
7950 | ||
7951 | val = tr32(TG3_CPMU_HST_ACC); | |
7952 | val &= ~CPMU_HST_ACC_MACCLK_MASK; | |
7953 | val |= CPMU_HST_ACC_MACCLK_6_25; | |
7954 | tw32(TG3_CPMU_HST_ACC, val); | |
7955 | } | |
7956 | ||
7957 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { | |
7958 | val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK; | |
7959 | val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN | | |
7960 | PCIE_PWR_MGMT_L1_THRESH_4MS; | |
7961 | tw32(PCIE_PWR_MGMT_THRESH, val); | |
7962 | ||
7963 | val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK; | |
7964 | tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS); | |
7965 | ||
7966 | tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR); | |
7967 | ||
7968 | val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN; | |
7969 | tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS); | |
7970 | } | |
7971 | ||
7972 | if (tg3_flag(tp, L1PLLPD_EN)) { | |
7973 | u32 grc_mode = tr32(GRC_MODE); | |
7974 | ||
7975 | /* Access the lower 1K of PL PCIE block registers. */ | |
7976 | val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK; | |
7977 | tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL); | |
7978 | ||
7979 | val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1); | |
7980 | tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1, | |
7981 | val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN); | |
7982 | ||
7983 | tw32(GRC_MODE, grc_mode); | |
7984 | } | |
7985 | ||
7986 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) { | |
7987 | if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) { | |
7988 | u32 grc_mode = tr32(GRC_MODE); | |
7989 | ||
7990 | /* Access the lower 1K of PL PCIE block registers. */ | |
7991 | val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK; | |
7992 | tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL); | |
7993 | ||
7994 | val = tr32(TG3_PCIE_TLDLPL_PORT + | |
7995 | TG3_PCIE_PL_LO_PHYCTL5); | |
7996 | tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5, | |
7997 | val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ); | |
7998 | ||
7999 | tw32(GRC_MODE, grc_mode); | |
8000 | } | |
8001 | ||
8002 | if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_57765_AX) { | |
8003 | u32 grc_mode = tr32(GRC_MODE); | |
8004 | ||
8005 | /* Access the lower 1K of DL PCIE block registers. */ | |
8006 | val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK; | |
8007 | tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL); | |
8008 | ||
8009 | val = tr32(TG3_PCIE_TLDLPL_PORT + | |
8010 | TG3_PCIE_DL_LO_FTSMAX); | |
8011 | val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK; | |
8012 | tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX, | |
8013 | val | TG3_PCIE_DL_LO_FTSMAX_VAL); | |
8014 | ||
8015 | tw32(GRC_MODE, grc_mode); | |
8016 | } | |
8017 | ||
8018 | val = tr32(TG3_CPMU_LSPD_10MB_CLK); | |
8019 | val &= ~CPMU_LSPD_10MB_MACCLK_MASK; | |
8020 | val |= CPMU_LSPD_10MB_MACCLK_6_25; | |
8021 | tw32(TG3_CPMU_LSPD_10MB_CLK, val); | |
8022 | } | |
8023 | ||
8024 | /* This works around an issue with Athlon chipsets on | |
8025 | * B3 tigon3 silicon. This bit has no effect on any | |
8026 | * other revision. But do not set this on PCI Express | |
8027 | * chips and don't even touch the clocks if the CPMU is present. | |
8028 | */ | |
8029 | if (!tg3_flag(tp, CPMU_PRESENT)) { | |
8030 | if (!tg3_flag(tp, PCI_EXPRESS)) | |
8031 | tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT; | |
8032 | tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); | |
8033 | } | |
8034 | ||
8035 | if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 && | |
8036 | tg3_flag(tp, PCIX_MODE)) { | |
8037 | val = tr32(TG3PCI_PCISTATE); | |
8038 | val |= PCISTATE_RETRY_SAME_DMA; | |
8039 | tw32(TG3PCI_PCISTATE, val); | |
8040 | } | |
8041 | ||
8042 | if (tg3_flag(tp, ENABLE_APE)) { | |
8043 | /* Allow reads and writes to the | |
8044 | * APE register and memory space. | |
8045 | */ | |
8046 | val = tr32(TG3PCI_PCISTATE); | |
8047 | val |= PCISTATE_ALLOW_APE_CTLSPC_WR | | |
8048 | PCISTATE_ALLOW_APE_SHMEM_WR | | |
8049 | PCISTATE_ALLOW_APE_PSPACE_WR; | |
8050 | tw32(TG3PCI_PCISTATE, val); | |
8051 | } | |
8052 | ||
8053 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) { | |
8054 | /* Enable some hw fixes. */ | |
8055 | val = tr32(TG3PCI_MSI_DATA); | |
8056 | val |= (1 << 26) | (1 << 28) | (1 << 29); | |
8057 | tw32(TG3PCI_MSI_DATA, val); | |
8058 | } | |
8059 | ||
8060 | /* Descriptor ring init may make accesses to the | |
8061 | * NIC SRAM area to setup the TX descriptors, so we | |
8062 | * can only do this after the hardware has been | |
8063 | * successfully reset. | |
8064 | */ | |
8065 | err = tg3_init_rings(tp); | |
8066 | if (err) | |
8067 | return err; | |
8068 | ||
8069 | if (tg3_flag(tp, 57765_PLUS)) { | |
8070 | val = tr32(TG3PCI_DMA_RW_CTRL) & | |
8071 | ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT; | |
8072 | if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) | |
8073 | val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK; | |
8074 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765 && | |
8075 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) | |
8076 | val |= DMA_RWCTRL_TAGGED_STAT_WA; | |
8077 | tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl); | |
8078 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 && | |
8079 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) { | |
8080 | /* This value is determined during the probe time DMA | |
8081 | * engine test, tg3_test_dma. | |
8082 | */ | |
8083 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
8084 | } | |
8085 | ||
8086 | tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS | | |
8087 | GRC_MODE_4X_NIC_SEND_RINGS | | |
8088 | GRC_MODE_NO_TX_PHDR_CSUM | | |
8089 | GRC_MODE_NO_RX_PHDR_CSUM); | |
8090 | tp->grc_mode |= GRC_MODE_HOST_SENDBDS; | |
8091 | ||
8092 | /* Pseudo-header checksum is done by hardware logic and not | |
8093 | * the offload processers, so make the chip do the pseudo- | |
8094 | * header checksums on receive. For transmit it is more | |
8095 | * convenient to do the pseudo-header checksum in software | |
8096 | * as Linux does that on transmit for us in all cases. | |
8097 | */ | |
8098 | tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM; | |
8099 | ||
8100 | tw32(GRC_MODE, | |
8101 | tp->grc_mode | | |
8102 | (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP)); | |
8103 | ||
8104 | /* Setup the timer prescalar register. Clock is always 66Mhz. */ | |
8105 | val = tr32(GRC_MISC_CFG); | |
8106 | val &= ~0xff; | |
8107 | val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT); | |
8108 | tw32(GRC_MISC_CFG, val); | |
8109 | ||
8110 | /* Initialize MBUF/DESC pool. */ | |
8111 | if (tg3_flag(tp, 5750_PLUS)) { | |
8112 | /* Do nothing. */ | |
8113 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) { | |
8114 | tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE); | |
8115 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) | |
8116 | tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64); | |
8117 | else | |
8118 | tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96); | |
8119 | tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE); | |
8120 | tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE); | |
8121 | } else if (tg3_flag(tp, TSO_CAPABLE)) { | |
8122 | int fw_len; | |
8123 | ||
8124 | fw_len = tp->fw_len; | |
8125 | fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1); | |
8126 | tw32(BUFMGR_MB_POOL_ADDR, | |
8127 | NIC_SRAM_MBUF_POOL_BASE5705 + fw_len); | |
8128 | tw32(BUFMGR_MB_POOL_SIZE, | |
8129 | NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00); | |
8130 | } | |
8131 | ||
8132 | if (tp->dev->mtu <= ETH_DATA_LEN) { | |
8133 | tw32(BUFMGR_MB_RDMA_LOW_WATER, | |
8134 | tp->bufmgr_config.mbuf_read_dma_low_water); | |
8135 | tw32(BUFMGR_MB_MACRX_LOW_WATER, | |
8136 | tp->bufmgr_config.mbuf_mac_rx_low_water); | |
8137 | tw32(BUFMGR_MB_HIGH_WATER, | |
8138 | tp->bufmgr_config.mbuf_high_water); | |
8139 | } else { | |
8140 | tw32(BUFMGR_MB_RDMA_LOW_WATER, | |
8141 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo); | |
8142 | tw32(BUFMGR_MB_MACRX_LOW_WATER, | |
8143 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo); | |
8144 | tw32(BUFMGR_MB_HIGH_WATER, | |
8145 | tp->bufmgr_config.mbuf_high_water_jumbo); | |
8146 | } | |
8147 | tw32(BUFMGR_DMA_LOW_WATER, | |
8148 | tp->bufmgr_config.dma_low_water); | |
8149 | tw32(BUFMGR_DMA_HIGH_WATER, | |
8150 | tp->bufmgr_config.dma_high_water); | |
8151 | ||
8152 | val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE; | |
8153 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) | |
8154 | val |= BUFMGR_MODE_NO_TX_UNDERRUN; | |
8155 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | |
8156 | tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 || | |
8157 | tp->pci_chip_rev_id == CHIPREV_ID_5720_A0) | |
8158 | val |= BUFMGR_MODE_MBLOW_ATTN_ENAB; | |
8159 | tw32(BUFMGR_MODE, val); | |
8160 | for (i = 0; i < 2000; i++) { | |
8161 | if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE) | |
8162 | break; | |
8163 | udelay(10); | |
8164 | } | |
8165 | if (i >= 2000) { | |
8166 | netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__); | |
8167 | return -ENODEV; | |
8168 | } | |
8169 | ||
8170 | if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1) | |
8171 | tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2); | |
8172 | ||
8173 | tg3_setup_rxbd_thresholds(tp); | |
8174 | ||
8175 | /* Initialize TG3_BDINFO's at: | |
8176 | * RCVDBDI_STD_BD: standard eth size rx ring | |
8177 | * RCVDBDI_JUMBO_BD: jumbo frame rx ring | |
8178 | * RCVDBDI_MINI_BD: small frame rx ring (??? does not work) | |
8179 | * | |
8180 | * like so: | |
8181 | * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring | |
8182 | * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) | | |
8183 | * ring attribute flags | |
8184 | * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM | |
8185 | * | |
8186 | * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries. | |
8187 | * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries. | |
8188 | * | |
8189 | * The size of each ring is fixed in the firmware, but the location is | |
8190 | * configurable. | |
8191 | */ | |
8192 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH, | |
8193 | ((u64) tpr->rx_std_mapping >> 32)); | |
8194 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, | |
8195 | ((u64) tpr->rx_std_mapping & 0xffffffff)); | |
8196 | if (!tg3_flag(tp, 5717_PLUS)) | |
8197 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR, | |
8198 | NIC_SRAM_RX_BUFFER_DESC); | |
8199 | ||
8200 | /* Disable the mini ring */ | |
8201 | if (!tg3_flag(tp, 5705_PLUS)) | |
8202 | tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS, | |
8203 | BDINFO_FLAGS_DISABLED); | |
8204 | ||
8205 | /* Program the jumbo buffer descriptor ring control | |
8206 | * blocks on those devices that have them. | |
8207 | */ | |
8208 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | |
8209 | (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) { | |
8210 | ||
8211 | if (tg3_flag(tp, JUMBO_RING_ENABLE)) { | |
8212 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH, | |
8213 | ((u64) tpr->rx_jmb_mapping >> 32)); | |
8214 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, | |
8215 | ((u64) tpr->rx_jmb_mapping & 0xffffffff)); | |
8216 | val = TG3_RX_JMB_RING_SIZE(tp) << | |
8217 | BDINFO_FLAGS_MAXLEN_SHIFT; | |
8218 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS, | |
8219 | val | BDINFO_FLAGS_USE_EXT_RECV); | |
8220 | if (!tg3_flag(tp, USE_JUMBO_BDFLAG) || | |
8221 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
8222 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR, | |
8223 | NIC_SRAM_RX_JUMBO_BUFFER_DESC); | |
8224 | } else { | |
8225 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS, | |
8226 | BDINFO_FLAGS_DISABLED); | |
8227 | } | |
8228 | ||
8229 | if (tg3_flag(tp, 57765_PLUS)) { | |
8230 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
8231 | val = TG3_RX_STD_MAX_SIZE_5700; | |
8232 | else | |
8233 | val = TG3_RX_STD_MAX_SIZE_5717; | |
8234 | val <<= BDINFO_FLAGS_MAXLEN_SHIFT; | |
8235 | val |= (TG3_RX_STD_DMA_SZ << 2); | |
8236 | } else | |
8237 | val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT; | |
8238 | } else | |
8239 | val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT; | |
8240 | ||
8241 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val); | |
8242 | ||
8243 | tpr->rx_std_prod_idx = tp->rx_pending; | |
8244 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx); | |
8245 | ||
8246 | tpr->rx_jmb_prod_idx = | |
8247 | tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0; | |
8248 | tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx); | |
8249 | ||
8250 | tg3_rings_reset(tp); | |
8251 | ||
8252 | /* Initialize MAC address and backoff seed. */ | |
8253 | __tg3_set_mac_addr(tp, 0); | |
8254 | ||
8255 | /* MTU + ethernet header + FCS + optional VLAN tag */ | |
8256 | tw32(MAC_RX_MTU_SIZE, | |
8257 | tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN); | |
8258 | ||
8259 | /* The slot time is changed by tg3_setup_phy if we | |
8260 | * run at gigabit with half duplex. | |
8261 | */ | |
8262 | val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) | | |
8263 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
8264 | (32 << TX_LENGTHS_SLOT_TIME_SHIFT); | |
8265 | ||
8266 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) | |
8267 | val |= tr32(MAC_TX_LENGTHS) & | |
8268 | (TX_LENGTHS_JMB_FRM_LEN_MSK | | |
8269 | TX_LENGTHS_CNT_DWN_VAL_MSK); | |
8270 | ||
8271 | tw32(MAC_TX_LENGTHS, val); | |
8272 | ||
8273 | /* Receive rules. */ | |
8274 | tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS); | |
8275 | tw32(RCVLPC_CONFIG, 0x0181); | |
8276 | ||
8277 | /* Calculate RDMAC_MODE setting early, we need it to determine | |
8278 | * the RCVLPC_STATE_ENABLE mask. | |
8279 | */ | |
8280 | rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB | | |
8281 | RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB | | |
8282 | RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB | | |
8283 | RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB | | |
8284 | RDMAC_MODE_LNGREAD_ENAB); | |
8285 | ||
8286 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) | |
8287 | rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS; | |
8288 | ||
8289 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || | |
8290 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || | |
8291 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) | |
8292 | rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB | | |
8293 | RDMAC_MODE_MBUF_RBD_CRPT_ENAB | | |
8294 | RDMAC_MODE_MBUF_SBD_CRPT_ENAB; | |
8295 | ||
8296 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && | |
8297 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) { | |
8298 | if (tg3_flag(tp, TSO_CAPABLE) && | |
8299 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | |
8300 | rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128; | |
8301 | } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) && | |
8302 | !tg3_flag(tp, IS_5788)) { | |
8303 | rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST; | |
8304 | } | |
8305 | } | |
8306 | ||
8307 | if (tg3_flag(tp, PCI_EXPRESS)) | |
8308 | rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST; | |
8309 | ||
8310 | if (tg3_flag(tp, HW_TSO_1) || | |
8311 | tg3_flag(tp, HW_TSO_2) || | |
8312 | tg3_flag(tp, HW_TSO_3)) | |
8313 | rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN; | |
8314 | ||
8315 | if (tg3_flag(tp, 57765_PLUS) || | |
8316 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || | |
8317 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) | |
8318 | rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN; | |
8319 | ||
8320 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) | |
8321 | rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET; | |
8322 | ||
8323 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || | |
8324 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || | |
8325 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || | |
8326 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || | |
8327 | tg3_flag(tp, 57765_PLUS)) { | |
8328 | val = tr32(TG3_RDMA_RSRVCTRL_REG); | |
8329 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | |
8330 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
8331 | val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK | | |
8332 | TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK | | |
8333 | TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK); | |
8334 | val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B | | |
8335 | TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K | | |
8336 | TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K; | |
8337 | } | |
8338 | tw32(TG3_RDMA_RSRVCTRL_REG, | |
8339 | val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX); | |
8340 | } | |
8341 | ||
8342 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | |
8343 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
8344 | val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL); | |
8345 | tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val | | |
8346 | TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K | | |
8347 | TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K); | |
8348 | } | |
8349 | ||
8350 | /* Receive/send statistics. */ | |
8351 | if (tg3_flag(tp, 5750_PLUS)) { | |
8352 | val = tr32(RCVLPC_STATS_ENABLE); | |
8353 | val &= ~RCVLPC_STATSENAB_DACK_FIX; | |
8354 | tw32(RCVLPC_STATS_ENABLE, val); | |
8355 | } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) && | |
8356 | tg3_flag(tp, TSO_CAPABLE)) { | |
8357 | val = tr32(RCVLPC_STATS_ENABLE); | |
8358 | val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX; | |
8359 | tw32(RCVLPC_STATS_ENABLE, val); | |
8360 | } else { | |
8361 | tw32(RCVLPC_STATS_ENABLE, 0xffffff); | |
8362 | } | |
8363 | tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE); | |
8364 | tw32(SNDDATAI_STATSENAB, 0xffffff); | |
8365 | tw32(SNDDATAI_STATSCTRL, | |
8366 | (SNDDATAI_SCTRL_ENABLE | | |
8367 | SNDDATAI_SCTRL_FASTUPD)); | |
8368 | ||
8369 | /* Setup host coalescing engine. */ | |
8370 | tw32(HOSTCC_MODE, 0); | |
8371 | for (i = 0; i < 2000; i++) { | |
8372 | if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE)) | |
8373 | break; | |
8374 | udelay(10); | |
8375 | } | |
8376 | ||
8377 | __tg3_set_coalesce(tp, &tp->coal); | |
8378 | ||
8379 | if (!tg3_flag(tp, 5705_PLUS)) { | |
8380 | /* Status/statistics block address. See tg3_timer, | |
8381 | * the tg3_periodic_fetch_stats call there, and | |
8382 | * tg3_get_stats to see how this works for 5705/5750 chips. | |
8383 | */ | |
8384 | tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, | |
8385 | ((u64) tp->stats_mapping >> 32)); | |
8386 | tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, | |
8387 | ((u64) tp->stats_mapping & 0xffffffff)); | |
8388 | tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK); | |
8389 | ||
8390 | tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK); | |
8391 | ||
8392 | /* Clear statistics and status block memory areas */ | |
8393 | for (i = NIC_SRAM_STATS_BLK; | |
8394 | i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE; | |
8395 | i += sizeof(u32)) { | |
8396 | tg3_write_mem(tp, i, 0); | |
8397 | udelay(40); | |
8398 | } | |
8399 | } | |
8400 | ||
8401 | tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode); | |
8402 | ||
8403 | tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE); | |
8404 | tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE); | |
8405 | if (!tg3_flag(tp, 5705_PLUS)) | |
8406 | tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE); | |
8407 | ||
8408 | if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { | |
8409 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; | |
8410 | /* reset to prevent losing 1st rx packet intermittently */ | |
8411 | tw32_f(MAC_RX_MODE, RX_MODE_RESET); | |
8412 | udelay(10); | |
8413 | } | |
8414 | ||
8415 | if (tg3_flag(tp, ENABLE_APE)) | |
8416 | tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; | |
8417 | else | |
8418 | tp->mac_mode = 0; | |
8419 | tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE | | |
8420 | MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE; | |
8421 | if (!tg3_flag(tp, 5705_PLUS) && | |
8422 | !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && | |
8423 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) | |
8424 | tp->mac_mode |= MAC_MODE_LINK_POLARITY; | |
8425 | tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR); | |
8426 | udelay(40); | |
8427 | ||
8428 | /* tp->grc_local_ctrl is partially set up during tg3_get_invariants(). | |
8429 | * If TG3_FLAG_IS_NIC is zero, we should read the | |
8430 | * register to preserve the GPIO settings for LOMs. The GPIOs, | |
8431 | * whether used as inputs or outputs, are set by boot code after | |
8432 | * reset. | |
8433 | */ | |
8434 | if (!tg3_flag(tp, IS_NIC)) { | |
8435 | u32 gpio_mask; | |
8436 | ||
8437 | gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 | | |
8438 | GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 | | |
8439 | GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2; | |
8440 | ||
8441 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) | |
8442 | gpio_mask |= GRC_LCLCTRL_GPIO_OE3 | | |
8443 | GRC_LCLCTRL_GPIO_OUTPUT3; | |
8444 | ||
8445 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) | |
8446 | gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL; | |
8447 | ||
8448 | tp->grc_local_ctrl &= ~gpio_mask; | |
8449 | tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask; | |
8450 | ||
8451 | /* GPIO1 must be driven high for eeprom write protect */ | |
8452 | if (tg3_flag(tp, EEPROM_WRITE_PROT)) | |
8453 | tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | | |
8454 | GRC_LCLCTRL_GPIO_OUTPUT1); | |
8455 | } | |
8456 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); | |
8457 | udelay(100); | |
8458 | ||
8459 | if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1) { | |
8460 | val = tr32(MSGINT_MODE); | |
8461 | val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE; | |
8462 | tw32(MSGINT_MODE, val); | |
8463 | } | |
8464 | ||
8465 | if (!tg3_flag(tp, 5705_PLUS)) { | |
8466 | tw32_f(DMAC_MODE, DMAC_MODE_ENABLE); | |
8467 | udelay(40); | |
8468 | } | |
8469 | ||
8470 | val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB | | |
8471 | WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB | | |
8472 | WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB | | |
8473 | WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB | | |
8474 | WDMAC_MODE_LNGREAD_ENAB); | |
8475 | ||
8476 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && | |
8477 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) { | |
8478 | if (tg3_flag(tp, TSO_CAPABLE) && | |
8479 | (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 || | |
8480 | tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) { | |
8481 | /* nothing */ | |
8482 | } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) && | |
8483 | !tg3_flag(tp, IS_5788)) { | |
8484 | val |= WDMAC_MODE_RX_ACCEL; | |
8485 | } | |
8486 | } | |
8487 | ||
8488 | /* Enable host coalescing bug fix */ | |
8489 | if (tg3_flag(tp, 5755_PLUS)) | |
8490 | val |= WDMAC_MODE_STATUS_TAG_FIX; | |
8491 | ||
8492 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | |
8493 | val |= WDMAC_MODE_BURST_ALL_DATA; | |
8494 | ||
8495 | tw32_f(WDMAC_MODE, val); | |
8496 | udelay(40); | |
8497 | ||
8498 | if (tg3_flag(tp, PCIX_MODE)) { | |
8499 | u16 pcix_cmd; | |
8500 | ||
8501 | pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, | |
8502 | &pcix_cmd); | |
8503 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) { | |
8504 | pcix_cmd &= ~PCI_X_CMD_MAX_READ; | |
8505 | pcix_cmd |= PCI_X_CMD_READ_2K; | |
8506 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { | |
8507 | pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ); | |
8508 | pcix_cmd |= PCI_X_CMD_READ_2K; | |
8509 | } | |
8510 | pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, | |
8511 | pcix_cmd); | |
8512 | } | |
8513 | ||
8514 | tw32_f(RDMAC_MODE, rdmac_mode); | |
8515 | udelay(40); | |
8516 | ||
8517 | tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE); | |
8518 | if (!tg3_flag(tp, 5705_PLUS)) | |
8519 | tw32(MBFREE_MODE, MBFREE_MODE_ENABLE); | |
8520 | ||
8521 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) | |
8522 | tw32(SNDDATAC_MODE, | |
8523 | SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY); | |
8524 | else | |
8525 | tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE); | |
8526 | ||
8527 | tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE); | |
8528 | tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB); | |
8529 | val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ; | |
8530 | if (tg3_flag(tp, LRG_PROD_RING_CAP)) | |
8531 | val |= RCVDBDI_MODE_LRG_RING_SZ; | |
8532 | tw32(RCVDBDI_MODE, val); | |
8533 | tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE); | |
8534 | if (tg3_flag(tp, HW_TSO_1) || | |
8535 | tg3_flag(tp, HW_TSO_2) || | |
8536 | tg3_flag(tp, HW_TSO_3)) | |
8537 | tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8); | |
8538 | val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE; | |
8539 | if (tg3_flag(tp, ENABLE_TSS)) | |
8540 | val |= SNDBDI_MODE_MULTI_TXQ_EN; | |
8541 | tw32(SNDBDI_MODE, val); | |
8542 | tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE); | |
8543 | ||
8544 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) { | |
8545 | err = tg3_load_5701_a0_firmware_fix(tp); | |
8546 | if (err) | |
8547 | return err; | |
8548 | } | |
8549 | ||
8550 | if (tg3_flag(tp, TSO_CAPABLE)) { | |
8551 | err = tg3_load_tso_firmware(tp); | |
8552 | if (err) | |
8553 | return err; | |
8554 | } | |
8555 | ||
8556 | tp->tx_mode = TX_MODE_ENABLE; | |
8557 | ||
8558 | if (tg3_flag(tp, 5755_PLUS) || | |
8559 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
8560 | tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX; | |
8561 | ||
8562 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
8563 | val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE; | |
8564 | tp->tx_mode &= ~val; | |
8565 | tp->tx_mode |= tr32(MAC_TX_MODE) & val; | |
8566 | } | |
8567 | ||
8568 | tw32_f(MAC_TX_MODE, tp->tx_mode); | |
8569 | udelay(100); | |
8570 | ||
8571 | if (tg3_flag(tp, ENABLE_RSS)) { | |
8572 | u32 reg = MAC_RSS_INDIR_TBL_0; | |
8573 | u8 *ent = (u8 *)&val; | |
8574 | ||
8575 | /* Setup the indirection table */ | |
8576 | for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) { | |
8577 | int idx = i % sizeof(val); | |
8578 | ||
8579 | ent[idx] = i % (tp->irq_cnt - 1); | |
8580 | if (idx == sizeof(val) - 1) { | |
8581 | tw32(reg, val); | |
8582 | reg += 4; | |
8583 | } | |
8584 | } | |
8585 | ||
8586 | /* Setup the "secret" hash key. */ | |
8587 | tw32(MAC_RSS_HASH_KEY_0, 0x5f865437); | |
8588 | tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc); | |
8589 | tw32(MAC_RSS_HASH_KEY_2, 0x50103a45); | |
8590 | tw32(MAC_RSS_HASH_KEY_3, 0x36621985); | |
8591 | tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8); | |
8592 | tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e); | |
8593 | tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556); | |
8594 | tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe); | |
8595 | tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7); | |
8596 | tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481); | |
8597 | } | |
8598 | ||
8599 | tp->rx_mode = RX_MODE_ENABLE; | |
8600 | if (tg3_flag(tp, 5755_PLUS)) | |
8601 | tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE; | |
8602 | ||
8603 | if (tg3_flag(tp, ENABLE_RSS)) | |
8604 | tp->rx_mode |= RX_MODE_RSS_ENABLE | | |
8605 | RX_MODE_RSS_ITBL_HASH_BITS_7 | | |
8606 | RX_MODE_RSS_IPV6_HASH_EN | | |
8607 | RX_MODE_RSS_TCP_IPV6_HASH_EN | | |
8608 | RX_MODE_RSS_IPV4_HASH_EN | | |
8609 | RX_MODE_RSS_TCP_IPV4_HASH_EN; | |
8610 | ||
8611 | tw32_f(MAC_RX_MODE, tp->rx_mode); | |
8612 | udelay(10); | |
8613 | ||
8614 | tw32(MAC_LED_CTRL, tp->led_ctrl); | |
8615 | ||
8616 | tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB); | |
8617 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { | |
8618 | tw32_f(MAC_RX_MODE, RX_MODE_RESET); | |
8619 | udelay(10); | |
8620 | } | |
8621 | tw32_f(MAC_RX_MODE, tp->rx_mode); | |
8622 | udelay(10); | |
8623 | ||
8624 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { | |
8625 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) && | |
8626 | !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) { | |
8627 | /* Set drive transmission level to 1.2V */ | |
8628 | /* only if the signal pre-emphasis bit is not set */ | |
8629 | val = tr32(MAC_SERDES_CFG); | |
8630 | val &= 0xfffff000; | |
8631 | val |= 0x880; | |
8632 | tw32(MAC_SERDES_CFG, val); | |
8633 | } | |
8634 | if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) | |
8635 | tw32(MAC_SERDES_CFG, 0x616000); | |
8636 | } | |
8637 | ||
8638 | /* Prevent chip from dropping frames when flow control | |
8639 | * is enabled. | |
8640 | */ | |
8641 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
8642 | val = 1; | |
8643 | else | |
8644 | val = 2; | |
8645 | tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val); | |
8646 | ||
8647 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 && | |
8648 | (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { | |
8649 | /* Use hardware link auto-negotiation */ | |
8650 | tg3_flag_set(tp, HW_AUTONEG); | |
8651 | } | |
8652 | ||
8653 | if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && | |
8654 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { | |
8655 | u32 tmp; | |
8656 | ||
8657 | tmp = tr32(SERDES_RX_CTRL); | |
8658 | tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT); | |
8659 | tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT; | |
8660 | tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT; | |
8661 | tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl); | |
8662 | } | |
8663 | ||
8664 | if (!tg3_flag(tp, USE_PHYLIB)) { | |
8665 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { | |
8666 | tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER; | |
8667 | tp->link_config.speed = tp->link_config.orig_speed; | |
8668 | tp->link_config.duplex = tp->link_config.orig_duplex; | |
8669 | tp->link_config.autoneg = tp->link_config.orig_autoneg; | |
8670 | } | |
8671 | ||
8672 | err = tg3_setup_phy(tp, 0); | |
8673 | if (err) | |
8674 | return err; | |
8675 | ||
8676 | if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && | |
8677 | !(tp->phy_flags & TG3_PHYFLG_IS_FET)) { | |
8678 | u32 tmp; | |
8679 | ||
8680 | /* Clear CRC stats. */ | |
8681 | if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) { | |
8682 | tg3_writephy(tp, MII_TG3_TEST1, | |
8683 | tmp | MII_TG3_TEST1_CRC_EN); | |
8684 | tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp); | |
8685 | } | |
8686 | } | |
8687 | } | |
8688 | ||
8689 | __tg3_set_rx_mode(tp->dev); | |
8690 | ||
8691 | /* Initialize receive rules. */ | |
8692 | tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK); | |
8693 | tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK); | |
8694 | tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK); | |
8695 | tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK); | |
8696 | ||
8697 | if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) | |
8698 | limit = 8; | |
8699 | else | |
8700 | limit = 16; | |
8701 | if (tg3_flag(tp, ENABLE_ASF)) | |
8702 | limit -= 4; | |
8703 | switch (limit) { | |
8704 | case 16: | |
8705 | tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0); | |
8706 | case 15: | |
8707 | tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0); | |
8708 | case 14: | |
8709 | tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0); | |
8710 | case 13: | |
8711 | tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0); | |
8712 | case 12: | |
8713 | tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0); | |
8714 | case 11: | |
8715 | tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0); | |
8716 | case 10: | |
8717 | tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0); | |
8718 | case 9: | |
8719 | tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0); | |
8720 | case 8: | |
8721 | tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0); | |
8722 | case 7: | |
8723 | tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0); | |
8724 | case 6: | |
8725 | tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0); | |
8726 | case 5: | |
8727 | tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0); | |
8728 | case 4: | |
8729 | /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */ | |
8730 | case 3: | |
8731 | /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */ | |
8732 | case 2: | |
8733 | case 1: | |
8734 | ||
8735 | default: | |
8736 | break; | |
8737 | } | |
8738 | ||
8739 | if (tg3_flag(tp, ENABLE_APE)) | |
8740 | /* Write our heartbeat update interval to APE. */ | |
8741 | tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS, | |
8742 | APE_HOST_HEARTBEAT_INT_DISABLE); | |
8743 | ||
8744 | tg3_write_sig_post_reset(tp, RESET_KIND_INIT); | |
8745 | ||
8746 | return 0; | |
8747 | } | |
8748 | ||
8749 | /* Called at device open time to get the chip ready for | |
8750 | * packet processing. Invoked with tp->lock held. | |
8751 | */ | |
8752 | static int tg3_init_hw(struct tg3 *tp, int reset_phy) | |
8753 | { | |
8754 | tg3_switch_clocks(tp); | |
8755 | ||
8756 | tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
8757 | ||
8758 | return tg3_reset_hw(tp, reset_phy); | |
8759 | } | |
8760 | ||
8761 | #define TG3_STAT_ADD32(PSTAT, REG) \ | |
8762 | do { u32 __val = tr32(REG); \ | |
8763 | (PSTAT)->low += __val; \ | |
8764 | if ((PSTAT)->low < __val) \ | |
8765 | (PSTAT)->high += 1; \ | |
8766 | } while (0) | |
8767 | ||
8768 | static void tg3_periodic_fetch_stats(struct tg3 *tp) | |
8769 | { | |
8770 | struct tg3_hw_stats *sp = tp->hw_stats; | |
8771 | ||
8772 | if (!netif_carrier_ok(tp->dev)) | |
8773 | return; | |
8774 | ||
8775 | TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS); | |
8776 | TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS); | |
8777 | TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT); | |
8778 | TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT); | |
8779 | TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS); | |
8780 | TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS); | |
8781 | TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS); | |
8782 | TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED); | |
8783 | TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL); | |
8784 | TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL); | |
8785 | TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST); | |
8786 | TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST); | |
8787 | TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST); | |
8788 | ||
8789 | TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS); | |
8790 | TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS); | |
8791 | TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST); | |
8792 | TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST); | |
8793 | TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST); | |
8794 | TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS); | |
8795 | TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS); | |
8796 | TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD); | |
8797 | TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD); | |
8798 | TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD); | |
8799 | TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED); | |
8800 | TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG); | |
8801 | TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS); | |
8802 | TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE); | |
8803 | ||
8804 | TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT); | |
8805 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 && | |
8806 | tp->pci_chip_rev_id != CHIPREV_ID_5719_A0 && | |
8807 | tp->pci_chip_rev_id != CHIPREV_ID_5720_A0) { | |
8808 | TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT); | |
8809 | } else { | |
8810 | u32 val = tr32(HOSTCC_FLOW_ATTN); | |
8811 | val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0; | |
8812 | if (val) { | |
8813 | tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM); | |
8814 | sp->rx_discards.low += val; | |
8815 | if (sp->rx_discards.low < val) | |
8816 | sp->rx_discards.high += 1; | |
8817 | } | |
8818 | sp->mbuf_lwm_thresh_hit = sp->rx_discards; | |
8819 | } | |
8820 | TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT); | |
8821 | } | |
8822 | ||
8823 | static void tg3_chk_missed_msi(struct tg3 *tp) | |
8824 | { | |
8825 | u32 i; | |
8826 | ||
8827 | for (i = 0; i < tp->irq_cnt; i++) { | |
8828 | struct tg3_napi *tnapi = &tp->napi[i]; | |
8829 | ||
8830 | if (tg3_has_work(tnapi)) { | |
8831 | if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr && | |
8832 | tnapi->last_tx_cons == tnapi->tx_cons) { | |
8833 | if (tnapi->chk_msi_cnt < 1) { | |
8834 | tnapi->chk_msi_cnt++; | |
8835 | return; | |
8836 | } | |
8837 | tw32_mailbox(tnapi->int_mbox, | |
8838 | tnapi->last_tag << 24); | |
8839 | } | |
8840 | } | |
8841 | tnapi->chk_msi_cnt = 0; | |
8842 | tnapi->last_rx_cons = tnapi->rx_rcb_ptr; | |
8843 | tnapi->last_tx_cons = tnapi->tx_cons; | |
8844 | } | |
8845 | } | |
8846 | ||
8847 | static void tg3_timer(unsigned long __opaque) | |
8848 | { | |
8849 | struct tg3 *tp = (struct tg3 *) __opaque; | |
8850 | ||
8851 | if (tp->irq_sync) | |
8852 | goto restart_timer; | |
8853 | ||
8854 | spin_lock(&tp->lock); | |
8855 | ||
8856 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | |
8857 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
8858 | tg3_chk_missed_msi(tp); | |
8859 | ||
8860 | if (!tg3_flag(tp, TAGGED_STATUS)) { | |
8861 | /* All of this garbage is because when using non-tagged | |
8862 | * IRQ status the mailbox/status_block protocol the chip | |
8863 | * uses with the cpu is race prone. | |
8864 | */ | |
8865 | if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) { | |
8866 | tw32(GRC_LOCAL_CTRL, | |
8867 | tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); | |
8868 | } else { | |
8869 | tw32(HOSTCC_MODE, tp->coalesce_mode | | |
8870 | HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW); | |
8871 | } | |
8872 | ||
8873 | if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) { | |
8874 | tg3_flag_set(tp, RESTART_TIMER); | |
8875 | spin_unlock(&tp->lock); | |
8876 | schedule_work(&tp->reset_task); | |
8877 | return; | |
8878 | } | |
8879 | } | |
8880 | ||
8881 | /* This part only runs once per second. */ | |
8882 | if (!--tp->timer_counter) { | |
8883 | if (tg3_flag(tp, 5705_PLUS)) | |
8884 | tg3_periodic_fetch_stats(tp); | |
8885 | ||
8886 | if (tp->setlpicnt && !--tp->setlpicnt) | |
8887 | tg3_phy_eee_enable(tp); | |
8888 | ||
8889 | if (tg3_flag(tp, USE_LINKCHG_REG)) { | |
8890 | u32 mac_stat; | |
8891 | int phy_event; | |
8892 | ||
8893 | mac_stat = tr32(MAC_STATUS); | |
8894 | ||
8895 | phy_event = 0; | |
8896 | if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) { | |
8897 | if (mac_stat & MAC_STATUS_MI_INTERRUPT) | |
8898 | phy_event = 1; | |
8899 | } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED) | |
8900 | phy_event = 1; | |
8901 | ||
8902 | if (phy_event) | |
8903 | tg3_setup_phy(tp, 0); | |
8904 | } else if (tg3_flag(tp, POLL_SERDES)) { | |
8905 | u32 mac_stat = tr32(MAC_STATUS); | |
8906 | int need_setup = 0; | |
8907 | ||
8908 | if (netif_carrier_ok(tp->dev) && | |
8909 | (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) { | |
8910 | need_setup = 1; | |
8911 | } | |
8912 | if (!netif_carrier_ok(tp->dev) && | |
8913 | (mac_stat & (MAC_STATUS_PCS_SYNCED | | |
8914 | MAC_STATUS_SIGNAL_DET))) { | |
8915 | need_setup = 1; | |
8916 | } | |
8917 | if (need_setup) { | |
8918 | if (!tp->serdes_counter) { | |
8919 | tw32_f(MAC_MODE, | |
8920 | (tp->mac_mode & | |
8921 | ~MAC_MODE_PORT_MODE_MASK)); | |
8922 | udelay(40); | |
8923 | tw32_f(MAC_MODE, tp->mac_mode); | |
8924 | udelay(40); | |
8925 | } | |
8926 | tg3_setup_phy(tp, 0); | |
8927 | } | |
8928 | } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && | |
8929 | tg3_flag(tp, 5780_CLASS)) { | |
8930 | tg3_serdes_parallel_detect(tp); | |
8931 | } | |
8932 | ||
8933 | tp->timer_counter = tp->timer_multiplier; | |
8934 | } | |
8935 | ||
8936 | /* Heartbeat is only sent once every 2 seconds. | |
8937 | * | |
8938 | * The heartbeat is to tell the ASF firmware that the host | |
8939 | * driver is still alive. In the event that the OS crashes, | |
8940 | * ASF needs to reset the hardware to free up the FIFO space | |
8941 | * that may be filled with rx packets destined for the host. | |
8942 | * If the FIFO is full, ASF will no longer function properly. | |
8943 | * | |
8944 | * Unintended resets have been reported on real time kernels | |
8945 | * where the timer doesn't run on time. Netpoll will also have | |
8946 | * same problem. | |
8947 | * | |
8948 | * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware | |
8949 | * to check the ring condition when the heartbeat is expiring | |
8950 | * before doing the reset. This will prevent most unintended | |
8951 | * resets. | |
8952 | */ | |
8953 | if (!--tp->asf_counter) { | |
8954 | if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) { | |
8955 | tg3_wait_for_event_ack(tp); | |
8956 | ||
8957 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, | |
8958 | FWCMD_NICDRV_ALIVE3); | |
8959 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4); | |
8960 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, | |
8961 | TG3_FW_UPDATE_TIMEOUT_SEC); | |
8962 | ||
8963 | tg3_generate_fw_event(tp); | |
8964 | } | |
8965 | tp->asf_counter = tp->asf_multiplier; | |
8966 | } | |
8967 | ||
8968 | spin_unlock(&tp->lock); | |
8969 | ||
8970 | restart_timer: | |
8971 | tp->timer.expires = jiffies + tp->timer_offset; | |
8972 | add_timer(&tp->timer); | |
8973 | } | |
8974 | ||
8975 | static int tg3_request_irq(struct tg3 *tp, int irq_num) | |
8976 | { | |
8977 | irq_handler_t fn; | |
8978 | unsigned long flags; | |
8979 | char *name; | |
8980 | struct tg3_napi *tnapi = &tp->napi[irq_num]; | |
8981 | ||
8982 | if (tp->irq_cnt == 1) | |
8983 | name = tp->dev->name; | |
8984 | else { | |
8985 | name = &tnapi->irq_lbl[0]; | |
8986 | snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num); | |
8987 | name[IFNAMSIZ-1] = 0; | |
8988 | } | |
8989 | ||
8990 | if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) { | |
8991 | fn = tg3_msi; | |
8992 | if (tg3_flag(tp, 1SHOT_MSI)) | |
8993 | fn = tg3_msi_1shot; | |
8994 | flags = 0; | |
8995 | } else { | |
8996 | fn = tg3_interrupt; | |
8997 | if (tg3_flag(tp, TAGGED_STATUS)) | |
8998 | fn = tg3_interrupt_tagged; | |
8999 | flags = IRQF_SHARED; | |
9000 | } | |
9001 | ||
9002 | return request_irq(tnapi->irq_vec, fn, flags, name, tnapi); | |
9003 | } | |
9004 | ||
9005 | static int tg3_test_interrupt(struct tg3 *tp) | |
9006 | { | |
9007 | struct tg3_napi *tnapi = &tp->napi[0]; | |
9008 | struct net_device *dev = tp->dev; | |
9009 | int err, i, intr_ok = 0; | |
9010 | u32 val; | |
9011 | ||
9012 | if (!netif_running(dev)) | |
9013 | return -ENODEV; | |
9014 | ||
9015 | tg3_disable_ints(tp); | |
9016 | ||
9017 | free_irq(tnapi->irq_vec, tnapi); | |
9018 | ||
9019 | /* | |
9020 | * Turn off MSI one shot mode. Otherwise this test has no | |
9021 | * observable way to know whether the interrupt was delivered. | |
9022 | */ | |
9023 | if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) { | |
9024 | val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE; | |
9025 | tw32(MSGINT_MODE, val); | |
9026 | } | |
9027 | ||
9028 | err = request_irq(tnapi->irq_vec, tg3_test_isr, | |
9029 | IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi); | |
9030 | if (err) | |
9031 | return err; | |
9032 | ||
9033 | tnapi->hw_status->status &= ~SD_STATUS_UPDATED; | |
9034 | tg3_enable_ints(tp); | |
9035 | ||
9036 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | | |
9037 | tnapi->coal_now); | |
9038 | ||
9039 | for (i = 0; i < 5; i++) { | |
9040 | u32 int_mbox, misc_host_ctrl; | |
9041 | ||
9042 | int_mbox = tr32_mailbox(tnapi->int_mbox); | |
9043 | misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL); | |
9044 | ||
9045 | if ((int_mbox != 0) || | |
9046 | (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) { | |
9047 | intr_ok = 1; | |
9048 | break; | |
9049 | } | |
9050 | ||
9051 | msleep(10); | |
9052 | } | |
9053 | ||
9054 | tg3_disable_ints(tp); | |
9055 | ||
9056 | free_irq(tnapi->irq_vec, tnapi); | |
9057 | ||
9058 | err = tg3_request_irq(tp, 0); | |
9059 | ||
9060 | if (err) | |
9061 | return err; | |
9062 | ||
9063 | if (intr_ok) { | |
9064 | /* Reenable MSI one shot mode. */ | |
9065 | if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) { | |
9066 | val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE; | |
9067 | tw32(MSGINT_MODE, val); | |
9068 | } | |
9069 | return 0; | |
9070 | } | |
9071 | ||
9072 | return -EIO; | |
9073 | } | |
9074 | ||
9075 | /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is | |
9076 | * successfully restored | |
9077 | */ | |
9078 | static int tg3_test_msi(struct tg3 *tp) | |
9079 | { | |
9080 | int err; | |
9081 | u16 pci_cmd; | |
9082 | ||
9083 | if (!tg3_flag(tp, USING_MSI)) | |
9084 | return 0; | |
9085 | ||
9086 | /* Turn off SERR reporting in case MSI terminates with Master | |
9087 | * Abort. | |
9088 | */ | |
9089 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
9090 | pci_write_config_word(tp->pdev, PCI_COMMAND, | |
9091 | pci_cmd & ~PCI_COMMAND_SERR); | |
9092 | ||
9093 | err = tg3_test_interrupt(tp); | |
9094 | ||
9095 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
9096 | ||
9097 | if (!err) | |
9098 | return 0; | |
9099 | ||
9100 | /* other failures */ | |
9101 | if (err != -EIO) | |
9102 | return err; | |
9103 | ||
9104 | /* MSI test failed, go back to INTx mode */ | |
9105 | netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching " | |
9106 | "to INTx mode. Please report this failure to the PCI " | |
9107 | "maintainer and include system chipset information\n"); | |
9108 | ||
9109 | free_irq(tp->napi[0].irq_vec, &tp->napi[0]); | |
9110 | ||
9111 | pci_disable_msi(tp->pdev); | |
9112 | ||
9113 | tg3_flag_clear(tp, USING_MSI); | |
9114 | tp->napi[0].irq_vec = tp->pdev->irq; | |
9115 | ||
9116 | err = tg3_request_irq(tp, 0); | |
9117 | if (err) | |
9118 | return err; | |
9119 | ||
9120 | /* Need to reset the chip because the MSI cycle may have terminated | |
9121 | * with Master Abort. | |
9122 | */ | |
9123 | tg3_full_lock(tp, 1); | |
9124 | ||
9125 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | |
9126 | err = tg3_init_hw(tp, 1); | |
9127 | ||
9128 | tg3_full_unlock(tp); | |
9129 | ||
9130 | if (err) | |
9131 | free_irq(tp->napi[0].irq_vec, &tp->napi[0]); | |
9132 | ||
9133 | return err; | |
9134 | } | |
9135 | ||
9136 | static int tg3_request_firmware(struct tg3 *tp) | |
9137 | { | |
9138 | const __be32 *fw_data; | |
9139 | ||
9140 | if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) { | |
9141 | netdev_err(tp->dev, "Failed to load firmware \"%s\"\n", | |
9142 | tp->fw_needed); | |
9143 | return -ENOENT; | |
9144 | } | |
9145 | ||
9146 | fw_data = (void *)tp->fw->data; | |
9147 | ||
9148 | /* Firmware blob starts with version numbers, followed by | |
9149 | * start address and _full_ length including BSS sections | |
9150 | * (which must be longer than the actual data, of course | |
9151 | */ | |
9152 | ||
9153 | tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */ | |
9154 | if (tp->fw_len < (tp->fw->size - 12)) { | |
9155 | netdev_err(tp->dev, "bogus length %d in \"%s\"\n", | |
9156 | tp->fw_len, tp->fw_needed); | |
9157 | release_firmware(tp->fw); | |
9158 | tp->fw = NULL; | |
9159 | return -EINVAL; | |
9160 | } | |
9161 | ||
9162 | /* We no longer need firmware; we have it. */ | |
9163 | tp->fw_needed = NULL; | |
9164 | return 0; | |
9165 | } | |
9166 | ||
9167 | static bool tg3_enable_msix(struct tg3 *tp) | |
9168 | { | |
9169 | int i, rc, cpus = num_online_cpus(); | |
9170 | struct msix_entry msix_ent[tp->irq_max]; | |
9171 | ||
9172 | if (cpus == 1) | |
9173 | /* Just fallback to the simpler MSI mode. */ | |
9174 | return false; | |
9175 | ||
9176 | /* | |
9177 | * We want as many rx rings enabled as there are cpus. | |
9178 | * The first MSIX vector only deals with link interrupts, etc, | |
9179 | * so we add one to the number of vectors we are requesting. | |
9180 | */ | |
9181 | tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max); | |
9182 | ||
9183 | for (i = 0; i < tp->irq_max; i++) { | |
9184 | msix_ent[i].entry = i; | |
9185 | msix_ent[i].vector = 0; | |
9186 | } | |
9187 | ||
9188 | rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt); | |
9189 | if (rc < 0) { | |
9190 | return false; | |
9191 | } else if (rc != 0) { | |
9192 | if (pci_enable_msix(tp->pdev, msix_ent, rc)) | |
9193 | return false; | |
9194 | netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n", | |
9195 | tp->irq_cnt, rc); | |
9196 | tp->irq_cnt = rc; | |
9197 | } | |
9198 | ||
9199 | for (i = 0; i < tp->irq_max; i++) | |
9200 | tp->napi[i].irq_vec = msix_ent[i].vector; | |
9201 | ||
9202 | netif_set_real_num_tx_queues(tp->dev, 1); | |
9203 | rc = tp->irq_cnt > 1 ? tp->irq_cnt - 1 : 1; | |
9204 | if (netif_set_real_num_rx_queues(tp->dev, rc)) { | |
9205 | pci_disable_msix(tp->pdev); | |
9206 | return false; | |
9207 | } | |
9208 | ||
9209 | if (tp->irq_cnt > 1) { | |
9210 | tg3_flag_set(tp, ENABLE_RSS); | |
9211 | ||
9212 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | |
9213 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
9214 | tg3_flag_set(tp, ENABLE_TSS); | |
9215 | netif_set_real_num_tx_queues(tp->dev, tp->irq_cnt - 1); | |
9216 | } | |
9217 | } | |
9218 | ||
9219 | return true; | |
9220 | } | |
9221 | ||
9222 | static void tg3_ints_init(struct tg3 *tp) | |
9223 | { | |
9224 | if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) && | |
9225 | !tg3_flag(tp, TAGGED_STATUS)) { | |
9226 | /* All MSI supporting chips should support tagged | |
9227 | * status. Assert that this is the case. | |
9228 | */ | |
9229 | netdev_warn(tp->dev, | |
9230 | "MSI without TAGGED_STATUS? Not using MSI\n"); | |
9231 | goto defcfg; | |
9232 | } | |
9233 | ||
9234 | if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp)) | |
9235 | tg3_flag_set(tp, USING_MSIX); | |
9236 | else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0) | |
9237 | tg3_flag_set(tp, USING_MSI); | |
9238 | ||
9239 | if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) { | |
9240 | u32 msi_mode = tr32(MSGINT_MODE); | |
9241 | if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1) | |
9242 | msi_mode |= MSGINT_MODE_MULTIVEC_EN; | |
9243 | tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE); | |
9244 | } | |
9245 | defcfg: | |
9246 | if (!tg3_flag(tp, USING_MSIX)) { | |
9247 | tp->irq_cnt = 1; | |
9248 | tp->napi[0].irq_vec = tp->pdev->irq; | |
9249 | netif_set_real_num_tx_queues(tp->dev, 1); | |
9250 | netif_set_real_num_rx_queues(tp->dev, 1); | |
9251 | } | |
9252 | } | |
9253 | ||
9254 | static void tg3_ints_fini(struct tg3 *tp) | |
9255 | { | |
9256 | if (tg3_flag(tp, USING_MSIX)) | |
9257 | pci_disable_msix(tp->pdev); | |
9258 | else if (tg3_flag(tp, USING_MSI)) | |
9259 | pci_disable_msi(tp->pdev); | |
9260 | tg3_flag_clear(tp, USING_MSI); | |
9261 | tg3_flag_clear(tp, USING_MSIX); | |
9262 | tg3_flag_clear(tp, ENABLE_RSS); | |
9263 | tg3_flag_clear(tp, ENABLE_TSS); | |
9264 | } | |
9265 | ||
9266 | static int tg3_open(struct net_device *dev) | |
9267 | { | |
9268 | struct tg3 *tp = netdev_priv(dev); | |
9269 | int i, err; | |
9270 | ||
9271 | if (tp->fw_needed) { | |
9272 | err = tg3_request_firmware(tp); | |
9273 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) { | |
9274 | if (err) | |
9275 | return err; | |
9276 | } else if (err) { | |
9277 | netdev_warn(tp->dev, "TSO capability disabled\n"); | |
9278 | tg3_flag_clear(tp, TSO_CAPABLE); | |
9279 | } else if (!tg3_flag(tp, TSO_CAPABLE)) { | |
9280 | netdev_notice(tp->dev, "TSO capability restored\n"); | |
9281 | tg3_flag_set(tp, TSO_CAPABLE); | |
9282 | } | |
9283 | } | |
9284 | ||
9285 | netif_carrier_off(tp->dev); | |
9286 | ||
9287 | err = tg3_power_up(tp); | |
9288 | if (err) | |
9289 | return err; | |
9290 | ||
9291 | tg3_full_lock(tp, 0); | |
9292 | ||
9293 | tg3_disable_ints(tp); | |
9294 | tg3_flag_clear(tp, INIT_COMPLETE); | |
9295 | ||
9296 | tg3_full_unlock(tp); | |
9297 | ||
9298 | /* | |
9299 | * Setup interrupts first so we know how | |
9300 | * many NAPI resources to allocate | |
9301 | */ | |
9302 | tg3_ints_init(tp); | |
9303 | ||
9304 | /* The placement of this call is tied | |
9305 | * to the setup and use of Host TX descriptors. | |
9306 | */ | |
9307 | err = tg3_alloc_consistent(tp); | |
9308 | if (err) | |
9309 | goto err_out1; | |
9310 | ||
9311 | tg3_napi_init(tp); | |
9312 | ||
9313 | tg3_napi_enable(tp); | |
9314 | ||
9315 | for (i = 0; i < tp->irq_cnt; i++) { | |
9316 | struct tg3_napi *tnapi = &tp->napi[i]; | |
9317 | err = tg3_request_irq(tp, i); | |
9318 | if (err) { | |
9319 | for (i--; i >= 0; i--) | |
9320 | free_irq(tnapi->irq_vec, tnapi); | |
9321 | break; | |
9322 | } | |
9323 | } | |
9324 | ||
9325 | if (err) | |
9326 | goto err_out2; | |
9327 | ||
9328 | tg3_full_lock(tp, 0); | |
9329 | ||
9330 | err = tg3_init_hw(tp, 1); | |
9331 | if (err) { | |
9332 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | |
9333 | tg3_free_rings(tp); | |
9334 | } else { | |
9335 | if (tg3_flag(tp, TAGGED_STATUS) && | |
9336 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 && | |
9337 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) | |
9338 | tp->timer_offset = HZ; | |
9339 | else | |
9340 | tp->timer_offset = HZ / 10; | |
9341 | ||
9342 | BUG_ON(tp->timer_offset > HZ); | |
9343 | tp->timer_counter = tp->timer_multiplier = | |
9344 | (HZ / tp->timer_offset); | |
9345 | tp->asf_counter = tp->asf_multiplier = | |
9346 | ((HZ / tp->timer_offset) * 2); | |
9347 | ||
9348 | init_timer(&tp->timer); | |
9349 | tp->timer.expires = jiffies + tp->timer_offset; | |
9350 | tp->timer.data = (unsigned long) tp; | |
9351 | tp->timer.function = tg3_timer; | |
9352 | } | |
9353 | ||
9354 | tg3_full_unlock(tp); | |
9355 | ||
9356 | if (err) | |
9357 | goto err_out3; | |
9358 | ||
9359 | if (tg3_flag(tp, USING_MSI)) { | |
9360 | err = tg3_test_msi(tp); | |
9361 | ||
9362 | if (err) { | |
9363 | tg3_full_lock(tp, 0); | |
9364 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | |
9365 | tg3_free_rings(tp); | |
9366 | tg3_full_unlock(tp); | |
9367 | ||
9368 | goto err_out2; | |
9369 | } | |
9370 | ||
9371 | if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) { | |
9372 | u32 val = tr32(PCIE_TRANSACTION_CFG); | |
9373 | ||
9374 | tw32(PCIE_TRANSACTION_CFG, | |
9375 | val | PCIE_TRANS_CFG_1SHOT_MSI); | |
9376 | } | |
9377 | } | |
9378 | ||
9379 | tg3_phy_start(tp); | |
9380 | ||
9381 | tg3_full_lock(tp, 0); | |
9382 | ||
9383 | add_timer(&tp->timer); | |
9384 | tg3_flag_set(tp, INIT_COMPLETE); | |
9385 | tg3_enable_ints(tp); | |
9386 | ||
9387 | tg3_full_unlock(tp); | |
9388 | ||
9389 | netif_tx_start_all_queues(dev); | |
9390 | ||
9391 | /* | |
9392 | * Reset loopback feature if it was turned on while the device was down | |
9393 | * make sure that it's installed properly now. | |
9394 | */ | |
9395 | if (dev->features & NETIF_F_LOOPBACK) | |
9396 | tg3_set_loopback(dev, dev->features); | |
9397 | ||
9398 | return 0; | |
9399 | ||
9400 | err_out3: | |
9401 | for (i = tp->irq_cnt - 1; i >= 0; i--) { | |
9402 | struct tg3_napi *tnapi = &tp->napi[i]; | |
9403 | free_irq(tnapi->irq_vec, tnapi); | |
9404 | } | |
9405 | ||
9406 | err_out2: | |
9407 | tg3_napi_disable(tp); | |
9408 | tg3_napi_fini(tp); | |
9409 | tg3_free_consistent(tp); | |
9410 | ||
9411 | err_out1: | |
9412 | tg3_ints_fini(tp); | |
9413 | return err; | |
9414 | } | |
9415 | ||
9416 | static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *, | |
9417 | struct rtnl_link_stats64 *); | |
9418 | static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *); | |
9419 | ||
9420 | static int tg3_close(struct net_device *dev) | |
9421 | { | |
9422 | int i; | |
9423 | struct tg3 *tp = netdev_priv(dev); | |
9424 | ||
9425 | tg3_napi_disable(tp); | |
9426 | cancel_work_sync(&tp->reset_task); | |
9427 | ||
9428 | netif_tx_stop_all_queues(dev); | |
9429 | ||
9430 | del_timer_sync(&tp->timer); | |
9431 | ||
9432 | tg3_phy_stop(tp); | |
9433 | ||
9434 | tg3_full_lock(tp, 1); | |
9435 | ||
9436 | tg3_disable_ints(tp); | |
9437 | ||
9438 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | |
9439 | tg3_free_rings(tp); | |
9440 | tg3_flag_clear(tp, INIT_COMPLETE); | |
9441 | ||
9442 | tg3_full_unlock(tp); | |
9443 | ||
9444 | for (i = tp->irq_cnt - 1; i >= 0; i--) { | |
9445 | struct tg3_napi *tnapi = &tp->napi[i]; | |
9446 | free_irq(tnapi->irq_vec, tnapi); | |
9447 | } | |
9448 | ||
9449 | tg3_ints_fini(tp); | |
9450 | ||
9451 | tg3_get_stats64(tp->dev, &tp->net_stats_prev); | |
9452 | ||
9453 | memcpy(&tp->estats_prev, tg3_get_estats(tp), | |
9454 | sizeof(tp->estats_prev)); | |
9455 | ||
9456 | tg3_napi_fini(tp); | |
9457 | ||
9458 | tg3_free_consistent(tp); | |
9459 | ||
9460 | tg3_power_down(tp); | |
9461 | ||
9462 | netif_carrier_off(tp->dev); | |
9463 | ||
9464 | return 0; | |
9465 | } | |
9466 | ||
9467 | static inline u64 get_stat64(tg3_stat64_t *val) | |
9468 | { | |
9469 | return ((u64)val->high << 32) | ((u64)val->low); | |
9470 | } | |
9471 | ||
9472 | static u64 calc_crc_errors(struct tg3 *tp) | |
9473 | { | |
9474 | struct tg3_hw_stats *hw_stats = tp->hw_stats; | |
9475 | ||
9476 | if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && | |
9477 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
9478 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) { | |
9479 | u32 val; | |
9480 | ||
9481 | spin_lock_bh(&tp->lock); | |
9482 | if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) { | |
9483 | tg3_writephy(tp, MII_TG3_TEST1, | |
9484 | val | MII_TG3_TEST1_CRC_EN); | |
9485 | tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val); | |
9486 | } else | |
9487 | val = 0; | |
9488 | spin_unlock_bh(&tp->lock); | |
9489 | ||
9490 | tp->phy_crc_errors += val; | |
9491 | ||
9492 | return tp->phy_crc_errors; | |
9493 | } | |
9494 | ||
9495 | return get_stat64(&hw_stats->rx_fcs_errors); | |
9496 | } | |
9497 | ||
9498 | #define ESTAT_ADD(member) \ | |
9499 | estats->member = old_estats->member + \ | |
9500 | get_stat64(&hw_stats->member) | |
9501 | ||
9502 | static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp) | |
9503 | { | |
9504 | struct tg3_ethtool_stats *estats = &tp->estats; | |
9505 | struct tg3_ethtool_stats *old_estats = &tp->estats_prev; | |
9506 | struct tg3_hw_stats *hw_stats = tp->hw_stats; | |
9507 | ||
9508 | if (!hw_stats) | |
9509 | return old_estats; | |
9510 | ||
9511 | ESTAT_ADD(rx_octets); | |
9512 | ESTAT_ADD(rx_fragments); | |
9513 | ESTAT_ADD(rx_ucast_packets); | |
9514 | ESTAT_ADD(rx_mcast_packets); | |
9515 | ESTAT_ADD(rx_bcast_packets); | |
9516 | ESTAT_ADD(rx_fcs_errors); | |
9517 | ESTAT_ADD(rx_align_errors); | |
9518 | ESTAT_ADD(rx_xon_pause_rcvd); | |
9519 | ESTAT_ADD(rx_xoff_pause_rcvd); | |
9520 | ESTAT_ADD(rx_mac_ctrl_rcvd); | |
9521 | ESTAT_ADD(rx_xoff_entered); | |
9522 | ESTAT_ADD(rx_frame_too_long_errors); | |
9523 | ESTAT_ADD(rx_jabbers); | |
9524 | ESTAT_ADD(rx_undersize_packets); | |
9525 | ESTAT_ADD(rx_in_length_errors); | |
9526 | ESTAT_ADD(rx_out_length_errors); | |
9527 | ESTAT_ADD(rx_64_or_less_octet_packets); | |
9528 | ESTAT_ADD(rx_65_to_127_octet_packets); | |
9529 | ESTAT_ADD(rx_128_to_255_octet_packets); | |
9530 | ESTAT_ADD(rx_256_to_511_octet_packets); | |
9531 | ESTAT_ADD(rx_512_to_1023_octet_packets); | |
9532 | ESTAT_ADD(rx_1024_to_1522_octet_packets); | |
9533 | ESTAT_ADD(rx_1523_to_2047_octet_packets); | |
9534 | ESTAT_ADD(rx_2048_to_4095_octet_packets); | |
9535 | ESTAT_ADD(rx_4096_to_8191_octet_packets); | |
9536 | ESTAT_ADD(rx_8192_to_9022_octet_packets); | |
9537 | ||
9538 | ESTAT_ADD(tx_octets); | |
9539 | ESTAT_ADD(tx_collisions); | |
9540 | ESTAT_ADD(tx_xon_sent); | |
9541 | ESTAT_ADD(tx_xoff_sent); | |
9542 | ESTAT_ADD(tx_flow_control); | |
9543 | ESTAT_ADD(tx_mac_errors); | |
9544 | ESTAT_ADD(tx_single_collisions); | |
9545 | ESTAT_ADD(tx_mult_collisions); | |
9546 | ESTAT_ADD(tx_deferred); | |
9547 | ESTAT_ADD(tx_excessive_collisions); | |
9548 | ESTAT_ADD(tx_late_collisions); | |
9549 | ESTAT_ADD(tx_collide_2times); | |
9550 | ESTAT_ADD(tx_collide_3times); | |
9551 | ESTAT_ADD(tx_collide_4times); | |
9552 | ESTAT_ADD(tx_collide_5times); | |
9553 | ESTAT_ADD(tx_collide_6times); | |
9554 | ESTAT_ADD(tx_collide_7times); | |
9555 | ESTAT_ADD(tx_collide_8times); | |
9556 | ESTAT_ADD(tx_collide_9times); | |
9557 | ESTAT_ADD(tx_collide_10times); | |
9558 | ESTAT_ADD(tx_collide_11times); | |
9559 | ESTAT_ADD(tx_collide_12times); | |
9560 | ESTAT_ADD(tx_collide_13times); | |
9561 | ESTAT_ADD(tx_collide_14times); | |
9562 | ESTAT_ADD(tx_collide_15times); | |
9563 | ESTAT_ADD(tx_ucast_packets); | |
9564 | ESTAT_ADD(tx_mcast_packets); | |
9565 | ESTAT_ADD(tx_bcast_packets); | |
9566 | ESTAT_ADD(tx_carrier_sense_errors); | |
9567 | ESTAT_ADD(tx_discards); | |
9568 | ESTAT_ADD(tx_errors); | |
9569 | ||
9570 | ESTAT_ADD(dma_writeq_full); | |
9571 | ESTAT_ADD(dma_write_prioq_full); | |
9572 | ESTAT_ADD(rxbds_empty); | |
9573 | ESTAT_ADD(rx_discards); | |
9574 | ESTAT_ADD(rx_errors); | |
9575 | ESTAT_ADD(rx_threshold_hit); | |
9576 | ||
9577 | ESTAT_ADD(dma_readq_full); | |
9578 | ESTAT_ADD(dma_read_prioq_full); | |
9579 | ESTAT_ADD(tx_comp_queue_full); | |
9580 | ||
9581 | ESTAT_ADD(ring_set_send_prod_index); | |
9582 | ESTAT_ADD(ring_status_update); | |
9583 | ESTAT_ADD(nic_irqs); | |
9584 | ESTAT_ADD(nic_avoided_irqs); | |
9585 | ESTAT_ADD(nic_tx_threshold_hit); | |
9586 | ||
9587 | ESTAT_ADD(mbuf_lwm_thresh_hit); | |
9588 | ||
9589 | return estats; | |
9590 | } | |
9591 | ||
9592 | static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev, | |
9593 | struct rtnl_link_stats64 *stats) | |
9594 | { | |
9595 | struct tg3 *tp = netdev_priv(dev); | |
9596 | struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev; | |
9597 | struct tg3_hw_stats *hw_stats = tp->hw_stats; | |
9598 | ||
9599 | if (!hw_stats) | |
9600 | return old_stats; | |
9601 | ||
9602 | stats->rx_packets = old_stats->rx_packets + | |
9603 | get_stat64(&hw_stats->rx_ucast_packets) + | |
9604 | get_stat64(&hw_stats->rx_mcast_packets) + | |
9605 | get_stat64(&hw_stats->rx_bcast_packets); | |
9606 | ||
9607 | stats->tx_packets = old_stats->tx_packets + | |
9608 | get_stat64(&hw_stats->tx_ucast_packets) + | |
9609 | get_stat64(&hw_stats->tx_mcast_packets) + | |
9610 | get_stat64(&hw_stats->tx_bcast_packets); | |
9611 | ||
9612 | stats->rx_bytes = old_stats->rx_bytes + | |
9613 | get_stat64(&hw_stats->rx_octets); | |
9614 | stats->tx_bytes = old_stats->tx_bytes + | |
9615 | get_stat64(&hw_stats->tx_octets); | |
9616 | ||
9617 | stats->rx_errors = old_stats->rx_errors + | |
9618 | get_stat64(&hw_stats->rx_errors); | |
9619 | stats->tx_errors = old_stats->tx_errors + | |
9620 | get_stat64(&hw_stats->tx_errors) + | |
9621 | get_stat64(&hw_stats->tx_mac_errors) + | |
9622 | get_stat64(&hw_stats->tx_carrier_sense_errors) + | |
9623 | get_stat64(&hw_stats->tx_discards); | |
9624 | ||
9625 | stats->multicast = old_stats->multicast + | |
9626 | get_stat64(&hw_stats->rx_mcast_packets); | |
9627 | stats->collisions = old_stats->collisions + | |
9628 | get_stat64(&hw_stats->tx_collisions); | |
9629 | ||
9630 | stats->rx_length_errors = old_stats->rx_length_errors + | |
9631 | get_stat64(&hw_stats->rx_frame_too_long_errors) + | |
9632 | get_stat64(&hw_stats->rx_undersize_packets); | |
9633 | ||
9634 | stats->rx_over_errors = old_stats->rx_over_errors + | |
9635 | get_stat64(&hw_stats->rxbds_empty); | |
9636 | stats->rx_frame_errors = old_stats->rx_frame_errors + | |
9637 | get_stat64(&hw_stats->rx_align_errors); | |
9638 | stats->tx_aborted_errors = old_stats->tx_aborted_errors + | |
9639 | get_stat64(&hw_stats->tx_discards); | |
9640 | stats->tx_carrier_errors = old_stats->tx_carrier_errors + | |
9641 | get_stat64(&hw_stats->tx_carrier_sense_errors); | |
9642 | ||
9643 | stats->rx_crc_errors = old_stats->rx_crc_errors + | |
9644 | calc_crc_errors(tp); | |
9645 | ||
9646 | stats->rx_missed_errors = old_stats->rx_missed_errors + | |
9647 | get_stat64(&hw_stats->rx_discards); | |
9648 | ||
9649 | stats->rx_dropped = tp->rx_dropped; | |
9650 | ||
9651 | return stats; | |
9652 | } | |
9653 | ||
9654 | static inline u32 calc_crc(unsigned char *buf, int len) | |
9655 | { | |
9656 | u32 reg; | |
9657 | u32 tmp; | |
9658 | int j, k; | |
9659 | ||
9660 | reg = 0xffffffff; | |
9661 | ||
9662 | for (j = 0; j < len; j++) { | |
9663 | reg ^= buf[j]; | |
9664 | ||
9665 | for (k = 0; k < 8; k++) { | |
9666 | tmp = reg & 0x01; | |
9667 | ||
9668 | reg >>= 1; | |
9669 | ||
9670 | if (tmp) | |
9671 | reg ^= 0xedb88320; | |
9672 | } | |
9673 | } | |
9674 | ||
9675 | return ~reg; | |
9676 | } | |
9677 | ||
9678 | static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all) | |
9679 | { | |
9680 | /* accept or reject all multicast frames */ | |
9681 | tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0); | |
9682 | tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0); | |
9683 | tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0); | |
9684 | tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0); | |
9685 | } | |
9686 | ||
9687 | static void __tg3_set_rx_mode(struct net_device *dev) | |
9688 | { | |
9689 | struct tg3 *tp = netdev_priv(dev); | |
9690 | u32 rx_mode; | |
9691 | ||
9692 | rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC | | |
9693 | RX_MODE_KEEP_VLAN_TAG); | |
9694 | ||
9695 | #if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE) | |
9696 | /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG | |
9697 | * flag clear. | |
9698 | */ | |
9699 | if (!tg3_flag(tp, ENABLE_ASF)) | |
9700 | rx_mode |= RX_MODE_KEEP_VLAN_TAG; | |
9701 | #endif | |
9702 | ||
9703 | if (dev->flags & IFF_PROMISC) { | |
9704 | /* Promiscuous mode. */ | |
9705 | rx_mode |= RX_MODE_PROMISC; | |
9706 | } else if (dev->flags & IFF_ALLMULTI) { | |
9707 | /* Accept all multicast. */ | |
9708 | tg3_set_multi(tp, 1); | |
9709 | } else if (netdev_mc_empty(dev)) { | |
9710 | /* Reject all multicast. */ | |
9711 | tg3_set_multi(tp, 0); | |
9712 | } else { | |
9713 | /* Accept one or more multicast(s). */ | |
9714 | struct netdev_hw_addr *ha; | |
9715 | u32 mc_filter[4] = { 0, }; | |
9716 | u32 regidx; | |
9717 | u32 bit; | |
9718 | u32 crc; | |
9719 | ||
9720 | netdev_for_each_mc_addr(ha, dev) { | |
9721 | crc = calc_crc(ha->addr, ETH_ALEN); | |
9722 | bit = ~crc & 0x7f; | |
9723 | regidx = (bit & 0x60) >> 5; | |
9724 | bit &= 0x1f; | |
9725 | mc_filter[regidx] |= (1 << bit); | |
9726 | } | |
9727 | ||
9728 | tw32(MAC_HASH_REG_0, mc_filter[0]); | |
9729 | tw32(MAC_HASH_REG_1, mc_filter[1]); | |
9730 | tw32(MAC_HASH_REG_2, mc_filter[2]); | |
9731 | tw32(MAC_HASH_REG_3, mc_filter[3]); | |
9732 | } | |
9733 | ||
9734 | if (rx_mode != tp->rx_mode) { | |
9735 | tp->rx_mode = rx_mode; | |
9736 | tw32_f(MAC_RX_MODE, rx_mode); | |
9737 | udelay(10); | |
9738 | } | |
9739 | } | |
9740 | ||
9741 | static void tg3_set_rx_mode(struct net_device *dev) | |
9742 | { | |
9743 | struct tg3 *tp = netdev_priv(dev); | |
9744 | ||
9745 | if (!netif_running(dev)) | |
9746 | return; | |
9747 | ||
9748 | tg3_full_lock(tp, 0); | |
9749 | __tg3_set_rx_mode(dev); | |
9750 | tg3_full_unlock(tp); | |
9751 | } | |
9752 | ||
9753 | static int tg3_get_regs_len(struct net_device *dev) | |
9754 | { | |
9755 | return TG3_REG_BLK_SIZE; | |
9756 | } | |
9757 | ||
9758 | static void tg3_get_regs(struct net_device *dev, | |
9759 | struct ethtool_regs *regs, void *_p) | |
9760 | { | |
9761 | struct tg3 *tp = netdev_priv(dev); | |
9762 | ||
9763 | regs->version = 0; | |
9764 | ||
9765 | memset(_p, 0, TG3_REG_BLK_SIZE); | |
9766 | ||
9767 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) | |
9768 | return; | |
9769 | ||
9770 | tg3_full_lock(tp, 0); | |
9771 | ||
9772 | tg3_dump_legacy_regs(tp, (u32 *)_p); | |
9773 | ||
9774 | tg3_full_unlock(tp); | |
9775 | } | |
9776 | ||
9777 | static int tg3_get_eeprom_len(struct net_device *dev) | |
9778 | { | |
9779 | struct tg3 *tp = netdev_priv(dev); | |
9780 | ||
9781 | return tp->nvram_size; | |
9782 | } | |
9783 | ||
9784 | static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data) | |
9785 | { | |
9786 | struct tg3 *tp = netdev_priv(dev); | |
9787 | int ret; | |
9788 | u8 *pd; | |
9789 | u32 i, offset, len, b_offset, b_count; | |
9790 | __be32 val; | |
9791 | ||
9792 | if (tg3_flag(tp, NO_NVRAM)) | |
9793 | return -EINVAL; | |
9794 | ||
9795 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) | |
9796 | return -EAGAIN; | |
9797 | ||
9798 | offset = eeprom->offset; | |
9799 | len = eeprom->len; | |
9800 | eeprom->len = 0; | |
9801 | ||
9802 | eeprom->magic = TG3_EEPROM_MAGIC; | |
9803 | ||
9804 | if (offset & 3) { | |
9805 | /* adjustments to start on required 4 byte boundary */ | |
9806 | b_offset = offset & 3; | |
9807 | b_count = 4 - b_offset; | |
9808 | if (b_count > len) { | |
9809 | /* i.e. offset=1 len=2 */ | |
9810 | b_count = len; | |
9811 | } | |
9812 | ret = tg3_nvram_read_be32(tp, offset-b_offset, &val); | |
9813 | if (ret) | |
9814 | return ret; | |
9815 | memcpy(data, ((char *)&val) + b_offset, b_count); | |
9816 | len -= b_count; | |
9817 | offset += b_count; | |
9818 | eeprom->len += b_count; | |
9819 | } | |
9820 | ||
9821 | /* read bytes up to the last 4 byte boundary */ | |
9822 | pd = &data[eeprom->len]; | |
9823 | for (i = 0; i < (len - (len & 3)); i += 4) { | |
9824 | ret = tg3_nvram_read_be32(tp, offset + i, &val); | |
9825 | if (ret) { | |
9826 | eeprom->len += i; | |
9827 | return ret; | |
9828 | } | |
9829 | memcpy(pd + i, &val, 4); | |
9830 | } | |
9831 | eeprom->len += i; | |
9832 | ||
9833 | if (len & 3) { | |
9834 | /* read last bytes not ending on 4 byte boundary */ | |
9835 | pd = &data[eeprom->len]; | |
9836 | b_count = len & 3; | |
9837 | b_offset = offset + len - b_count; | |
9838 | ret = tg3_nvram_read_be32(tp, b_offset, &val); | |
9839 | if (ret) | |
9840 | return ret; | |
9841 | memcpy(pd, &val, b_count); | |
9842 | eeprom->len += b_count; | |
9843 | } | |
9844 | return 0; | |
9845 | } | |
9846 | ||
9847 | static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf); | |
9848 | ||
9849 | static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data) | |
9850 | { | |
9851 | struct tg3 *tp = netdev_priv(dev); | |
9852 | int ret; | |
9853 | u32 offset, len, b_offset, odd_len; | |
9854 | u8 *buf; | |
9855 | __be32 start, end; | |
9856 | ||
9857 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) | |
9858 | return -EAGAIN; | |
9859 | ||
9860 | if (tg3_flag(tp, NO_NVRAM) || | |
9861 | eeprom->magic != TG3_EEPROM_MAGIC) | |
9862 | return -EINVAL; | |
9863 | ||
9864 | offset = eeprom->offset; | |
9865 | len = eeprom->len; | |
9866 | ||
9867 | if ((b_offset = (offset & 3))) { | |
9868 | /* adjustments to start on required 4 byte boundary */ | |
9869 | ret = tg3_nvram_read_be32(tp, offset-b_offset, &start); | |
9870 | if (ret) | |
9871 | return ret; | |
9872 | len += b_offset; | |
9873 | offset &= ~3; | |
9874 | if (len < 4) | |
9875 | len = 4; | |
9876 | } | |
9877 | ||
9878 | odd_len = 0; | |
9879 | if (len & 3) { | |
9880 | /* adjustments to end on required 4 byte boundary */ | |
9881 | odd_len = 1; | |
9882 | len = (len + 3) & ~3; | |
9883 | ret = tg3_nvram_read_be32(tp, offset+len-4, &end); | |
9884 | if (ret) | |
9885 | return ret; | |
9886 | } | |
9887 | ||
9888 | buf = data; | |
9889 | if (b_offset || odd_len) { | |
9890 | buf = kmalloc(len, GFP_KERNEL); | |
9891 | if (!buf) | |
9892 | return -ENOMEM; | |
9893 | if (b_offset) | |
9894 | memcpy(buf, &start, 4); | |
9895 | if (odd_len) | |
9896 | memcpy(buf+len-4, &end, 4); | |
9897 | memcpy(buf + b_offset, data, eeprom->len); | |
9898 | } | |
9899 | ||
9900 | ret = tg3_nvram_write_block(tp, offset, len, buf); | |
9901 | ||
9902 | if (buf != data) | |
9903 | kfree(buf); | |
9904 | ||
9905 | return ret; | |
9906 | } | |
9907 | ||
9908 | static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
9909 | { | |
9910 | struct tg3 *tp = netdev_priv(dev); | |
9911 | ||
9912 | if (tg3_flag(tp, USE_PHYLIB)) { | |
9913 | struct phy_device *phydev; | |
9914 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) | |
9915 | return -EAGAIN; | |
9916 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; | |
9917 | return phy_ethtool_gset(phydev, cmd); | |
9918 | } | |
9919 | ||
9920 | cmd->supported = (SUPPORTED_Autoneg); | |
9921 | ||
9922 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) | |
9923 | cmd->supported |= (SUPPORTED_1000baseT_Half | | |
9924 | SUPPORTED_1000baseT_Full); | |
9925 | ||
9926 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { | |
9927 | cmd->supported |= (SUPPORTED_100baseT_Half | | |
9928 | SUPPORTED_100baseT_Full | | |
9929 | SUPPORTED_10baseT_Half | | |
9930 | SUPPORTED_10baseT_Full | | |
9931 | SUPPORTED_TP); | |
9932 | cmd->port = PORT_TP; | |
9933 | } else { | |
9934 | cmd->supported |= SUPPORTED_FIBRE; | |
9935 | cmd->port = PORT_FIBRE; | |
9936 | } | |
9937 | ||
9938 | cmd->advertising = tp->link_config.advertising; | |
9939 | if (tg3_flag(tp, PAUSE_AUTONEG)) { | |
9940 | if (tp->link_config.flowctrl & FLOW_CTRL_RX) { | |
9941 | if (tp->link_config.flowctrl & FLOW_CTRL_TX) { | |
9942 | cmd->advertising |= ADVERTISED_Pause; | |
9943 | } else { | |
9944 | cmd->advertising |= ADVERTISED_Pause | | |
9945 | ADVERTISED_Asym_Pause; | |
9946 | } | |
9947 | } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) { | |
9948 | cmd->advertising |= ADVERTISED_Asym_Pause; | |
9949 | } | |
9950 | } | |
9951 | if (netif_running(dev)) { | |
9952 | ethtool_cmd_speed_set(cmd, tp->link_config.active_speed); | |
9953 | cmd->duplex = tp->link_config.active_duplex; | |
9954 | } else { | |
9955 | ethtool_cmd_speed_set(cmd, SPEED_INVALID); | |
9956 | cmd->duplex = DUPLEX_INVALID; | |
9957 | } | |
9958 | cmd->phy_address = tp->phy_addr; | |
9959 | cmd->transceiver = XCVR_INTERNAL; | |
9960 | cmd->autoneg = tp->link_config.autoneg; | |
9961 | cmd->maxtxpkt = 0; | |
9962 | cmd->maxrxpkt = 0; | |
9963 | return 0; | |
9964 | } | |
9965 | ||
9966 | static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
9967 | { | |
9968 | struct tg3 *tp = netdev_priv(dev); | |
9969 | u32 speed = ethtool_cmd_speed(cmd); | |
9970 | ||
9971 | if (tg3_flag(tp, USE_PHYLIB)) { | |
9972 | struct phy_device *phydev; | |
9973 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) | |
9974 | return -EAGAIN; | |
9975 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; | |
9976 | return phy_ethtool_sset(phydev, cmd); | |
9977 | } | |
9978 | ||
9979 | if (cmd->autoneg != AUTONEG_ENABLE && | |
9980 | cmd->autoneg != AUTONEG_DISABLE) | |
9981 | return -EINVAL; | |
9982 | ||
9983 | if (cmd->autoneg == AUTONEG_DISABLE && | |
9984 | cmd->duplex != DUPLEX_FULL && | |
9985 | cmd->duplex != DUPLEX_HALF) | |
9986 | return -EINVAL; | |
9987 | ||
9988 | if (cmd->autoneg == AUTONEG_ENABLE) { | |
9989 | u32 mask = ADVERTISED_Autoneg | | |
9990 | ADVERTISED_Pause | | |
9991 | ADVERTISED_Asym_Pause; | |
9992 | ||
9993 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) | |
9994 | mask |= ADVERTISED_1000baseT_Half | | |
9995 | ADVERTISED_1000baseT_Full; | |
9996 | ||
9997 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) | |
9998 | mask |= ADVERTISED_100baseT_Half | | |
9999 | ADVERTISED_100baseT_Full | | |
10000 | ADVERTISED_10baseT_Half | | |
10001 | ADVERTISED_10baseT_Full | | |
10002 | ADVERTISED_TP; | |
10003 | else | |
10004 | mask |= ADVERTISED_FIBRE; | |
10005 | ||
10006 | if (cmd->advertising & ~mask) | |
10007 | return -EINVAL; | |
10008 | ||
10009 | mask &= (ADVERTISED_1000baseT_Half | | |
10010 | ADVERTISED_1000baseT_Full | | |
10011 | ADVERTISED_100baseT_Half | | |
10012 | ADVERTISED_100baseT_Full | | |
10013 | ADVERTISED_10baseT_Half | | |
10014 | ADVERTISED_10baseT_Full); | |
10015 | ||
10016 | cmd->advertising &= mask; | |
10017 | } else { | |
10018 | if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) { | |
10019 | if (speed != SPEED_1000) | |
10020 | return -EINVAL; | |
10021 | ||
10022 | if (cmd->duplex != DUPLEX_FULL) | |
10023 | return -EINVAL; | |
10024 | } else { | |
10025 | if (speed != SPEED_100 && | |
10026 | speed != SPEED_10) | |
10027 | return -EINVAL; | |
10028 | } | |
10029 | } | |
10030 | ||
10031 | tg3_full_lock(tp, 0); | |
10032 | ||
10033 | tp->link_config.autoneg = cmd->autoneg; | |
10034 | if (cmd->autoneg == AUTONEG_ENABLE) { | |
10035 | tp->link_config.advertising = (cmd->advertising | | |
10036 | ADVERTISED_Autoneg); | |
10037 | tp->link_config.speed = SPEED_INVALID; | |
10038 | tp->link_config.duplex = DUPLEX_INVALID; | |
10039 | } else { | |
10040 | tp->link_config.advertising = 0; | |
10041 | tp->link_config.speed = speed; | |
10042 | tp->link_config.duplex = cmd->duplex; | |
10043 | } | |
10044 | ||
10045 | tp->link_config.orig_speed = tp->link_config.speed; | |
10046 | tp->link_config.orig_duplex = tp->link_config.duplex; | |
10047 | tp->link_config.orig_autoneg = tp->link_config.autoneg; | |
10048 | ||
10049 | if (netif_running(dev)) | |
10050 | tg3_setup_phy(tp, 1); | |
10051 | ||
10052 | tg3_full_unlock(tp); | |
10053 | ||
10054 | return 0; | |
10055 | } | |
10056 | ||
10057 | static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) | |
10058 | { | |
10059 | struct tg3 *tp = netdev_priv(dev); | |
10060 | ||
10061 | strcpy(info->driver, DRV_MODULE_NAME); | |
10062 | strcpy(info->version, DRV_MODULE_VERSION); | |
10063 | strcpy(info->fw_version, tp->fw_ver); | |
10064 | strcpy(info->bus_info, pci_name(tp->pdev)); | |
10065 | } | |
10066 | ||
10067 | static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
10068 | { | |
10069 | struct tg3 *tp = netdev_priv(dev); | |
10070 | ||
10071 | if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev)) | |
10072 | wol->supported = WAKE_MAGIC; | |
10073 | else | |
10074 | wol->supported = 0; | |
10075 | wol->wolopts = 0; | |
10076 | if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev)) | |
10077 | wol->wolopts = WAKE_MAGIC; | |
10078 | memset(&wol->sopass, 0, sizeof(wol->sopass)); | |
10079 | } | |
10080 | ||
10081 | static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
10082 | { | |
10083 | struct tg3 *tp = netdev_priv(dev); | |
10084 | struct device *dp = &tp->pdev->dev; | |
10085 | ||
10086 | if (wol->wolopts & ~WAKE_MAGIC) | |
10087 | return -EINVAL; | |
10088 | if ((wol->wolopts & WAKE_MAGIC) && | |
10089 | !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp))) | |
10090 | return -EINVAL; | |
10091 | ||
10092 | device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC); | |
10093 | ||
10094 | spin_lock_bh(&tp->lock); | |
10095 | if (device_may_wakeup(dp)) | |
10096 | tg3_flag_set(tp, WOL_ENABLE); | |
10097 | else | |
10098 | tg3_flag_clear(tp, WOL_ENABLE); | |
10099 | spin_unlock_bh(&tp->lock); | |
10100 | ||
10101 | return 0; | |
10102 | } | |
10103 | ||
10104 | static u32 tg3_get_msglevel(struct net_device *dev) | |
10105 | { | |
10106 | struct tg3 *tp = netdev_priv(dev); | |
10107 | return tp->msg_enable; | |
10108 | } | |
10109 | ||
10110 | static void tg3_set_msglevel(struct net_device *dev, u32 value) | |
10111 | { | |
10112 | struct tg3 *tp = netdev_priv(dev); | |
10113 | tp->msg_enable = value; | |
10114 | } | |
10115 | ||
10116 | static int tg3_nway_reset(struct net_device *dev) | |
10117 | { | |
10118 | struct tg3 *tp = netdev_priv(dev); | |
10119 | int r; | |
10120 | ||
10121 | if (!netif_running(dev)) | |
10122 | return -EAGAIN; | |
10123 | ||
10124 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) | |
10125 | return -EINVAL; | |
10126 | ||
10127 | if (tg3_flag(tp, USE_PHYLIB)) { | |
10128 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) | |
10129 | return -EAGAIN; | |
10130 | r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); | |
10131 | } else { | |
10132 | u32 bmcr; | |
10133 | ||
10134 | spin_lock_bh(&tp->lock); | |
10135 | r = -EINVAL; | |
10136 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
10137 | if (!tg3_readphy(tp, MII_BMCR, &bmcr) && | |
10138 | ((bmcr & BMCR_ANENABLE) || | |
10139 | (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) { | |
10140 | tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART | | |
10141 | BMCR_ANENABLE); | |
10142 | r = 0; | |
10143 | } | |
10144 | spin_unlock_bh(&tp->lock); | |
10145 | } | |
10146 | ||
10147 | return r; | |
10148 | } | |
10149 | ||
10150 | static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) | |
10151 | { | |
10152 | struct tg3 *tp = netdev_priv(dev); | |
10153 | ||
10154 | ering->rx_max_pending = tp->rx_std_ring_mask; | |
10155 | ering->rx_mini_max_pending = 0; | |
10156 | if (tg3_flag(tp, JUMBO_RING_ENABLE)) | |
10157 | ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask; | |
10158 | else | |
10159 | ering->rx_jumbo_max_pending = 0; | |
10160 | ||
10161 | ering->tx_max_pending = TG3_TX_RING_SIZE - 1; | |
10162 | ||
10163 | ering->rx_pending = tp->rx_pending; | |
10164 | ering->rx_mini_pending = 0; | |
10165 | if (tg3_flag(tp, JUMBO_RING_ENABLE)) | |
10166 | ering->rx_jumbo_pending = tp->rx_jumbo_pending; | |
10167 | else | |
10168 | ering->rx_jumbo_pending = 0; | |
10169 | ||
10170 | ering->tx_pending = tp->napi[0].tx_pending; | |
10171 | } | |
10172 | ||
10173 | static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) | |
10174 | { | |
10175 | struct tg3 *tp = netdev_priv(dev); | |
10176 | int i, irq_sync = 0, err = 0; | |
10177 | ||
10178 | if ((ering->rx_pending > tp->rx_std_ring_mask) || | |
10179 | (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) || | |
10180 | (ering->tx_pending > TG3_TX_RING_SIZE - 1) || | |
10181 | (ering->tx_pending <= MAX_SKB_FRAGS) || | |
10182 | (tg3_flag(tp, TSO_BUG) && | |
10183 | (ering->tx_pending <= (MAX_SKB_FRAGS * 3)))) | |
10184 | return -EINVAL; | |
10185 | ||
10186 | if (netif_running(dev)) { | |
10187 | tg3_phy_stop(tp); | |
10188 | tg3_netif_stop(tp); | |
10189 | irq_sync = 1; | |
10190 | } | |
10191 | ||
10192 | tg3_full_lock(tp, irq_sync); | |
10193 | ||
10194 | tp->rx_pending = ering->rx_pending; | |
10195 | ||
10196 | if (tg3_flag(tp, MAX_RXPEND_64) && | |
10197 | tp->rx_pending > 63) | |
10198 | tp->rx_pending = 63; | |
10199 | tp->rx_jumbo_pending = ering->rx_jumbo_pending; | |
10200 | ||
10201 | for (i = 0; i < tp->irq_max; i++) | |
10202 | tp->napi[i].tx_pending = ering->tx_pending; | |
10203 | ||
10204 | if (netif_running(dev)) { | |
10205 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | |
10206 | err = tg3_restart_hw(tp, 1); | |
10207 | if (!err) | |
10208 | tg3_netif_start(tp); | |
10209 | } | |
10210 | ||
10211 | tg3_full_unlock(tp); | |
10212 | ||
10213 | if (irq_sync && !err) | |
10214 | tg3_phy_start(tp); | |
10215 | ||
10216 | return err; | |
10217 | } | |
10218 | ||
10219 | static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) | |
10220 | { | |
10221 | struct tg3 *tp = netdev_priv(dev); | |
10222 | ||
10223 | epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG); | |
10224 | ||
10225 | if (tp->link_config.active_flowctrl & FLOW_CTRL_RX) | |
10226 | epause->rx_pause = 1; | |
10227 | else | |
10228 | epause->rx_pause = 0; | |
10229 | ||
10230 | if (tp->link_config.active_flowctrl & FLOW_CTRL_TX) | |
10231 | epause->tx_pause = 1; | |
10232 | else | |
10233 | epause->tx_pause = 0; | |
10234 | } | |
10235 | ||
10236 | static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) | |
10237 | { | |
10238 | struct tg3 *tp = netdev_priv(dev); | |
10239 | int err = 0; | |
10240 | ||
10241 | if (tg3_flag(tp, USE_PHYLIB)) { | |
10242 | u32 newadv; | |
10243 | struct phy_device *phydev; | |
10244 | ||
10245 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; | |
10246 | ||
10247 | if (!(phydev->supported & SUPPORTED_Pause) || | |
10248 | (!(phydev->supported & SUPPORTED_Asym_Pause) && | |
10249 | (epause->rx_pause != epause->tx_pause))) | |
10250 | return -EINVAL; | |
10251 | ||
10252 | tp->link_config.flowctrl = 0; | |
10253 | if (epause->rx_pause) { | |
10254 | tp->link_config.flowctrl |= FLOW_CTRL_RX; | |
10255 | ||
10256 | if (epause->tx_pause) { | |
10257 | tp->link_config.flowctrl |= FLOW_CTRL_TX; | |
10258 | newadv = ADVERTISED_Pause; | |
10259 | } else | |
10260 | newadv = ADVERTISED_Pause | | |
10261 | ADVERTISED_Asym_Pause; | |
10262 | } else if (epause->tx_pause) { | |
10263 | tp->link_config.flowctrl |= FLOW_CTRL_TX; | |
10264 | newadv = ADVERTISED_Asym_Pause; | |
10265 | } else | |
10266 | newadv = 0; | |
10267 | ||
10268 | if (epause->autoneg) | |
10269 | tg3_flag_set(tp, PAUSE_AUTONEG); | |
10270 | else | |
10271 | tg3_flag_clear(tp, PAUSE_AUTONEG); | |
10272 | ||
10273 | if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { | |
10274 | u32 oldadv = phydev->advertising & | |
10275 | (ADVERTISED_Pause | ADVERTISED_Asym_Pause); | |
10276 | if (oldadv != newadv) { | |
10277 | phydev->advertising &= | |
10278 | ~(ADVERTISED_Pause | | |
10279 | ADVERTISED_Asym_Pause); | |
10280 | phydev->advertising |= newadv; | |
10281 | if (phydev->autoneg) { | |
10282 | /* | |
10283 | * Always renegotiate the link to | |
10284 | * inform our link partner of our | |
10285 | * flow control settings, even if the | |
10286 | * flow control is forced. Let | |
10287 | * tg3_adjust_link() do the final | |
10288 | * flow control setup. | |
10289 | */ | |
10290 | return phy_start_aneg(phydev); | |
10291 | } | |
10292 | } | |
10293 | ||
10294 | if (!epause->autoneg) | |
10295 | tg3_setup_flow_control(tp, 0, 0); | |
10296 | } else { | |
10297 | tp->link_config.orig_advertising &= | |
10298 | ~(ADVERTISED_Pause | | |
10299 | ADVERTISED_Asym_Pause); | |
10300 | tp->link_config.orig_advertising |= newadv; | |
10301 | } | |
10302 | } else { | |
10303 | int irq_sync = 0; | |
10304 | ||
10305 | if (netif_running(dev)) { | |
10306 | tg3_netif_stop(tp); | |
10307 | irq_sync = 1; | |
10308 | } | |
10309 | ||
10310 | tg3_full_lock(tp, irq_sync); | |
10311 | ||
10312 | if (epause->autoneg) | |
10313 | tg3_flag_set(tp, PAUSE_AUTONEG); | |
10314 | else | |
10315 | tg3_flag_clear(tp, PAUSE_AUTONEG); | |
10316 | if (epause->rx_pause) | |
10317 | tp->link_config.flowctrl |= FLOW_CTRL_RX; | |
10318 | else | |
10319 | tp->link_config.flowctrl &= ~FLOW_CTRL_RX; | |
10320 | if (epause->tx_pause) | |
10321 | tp->link_config.flowctrl |= FLOW_CTRL_TX; | |
10322 | else | |
10323 | tp->link_config.flowctrl &= ~FLOW_CTRL_TX; | |
10324 | ||
10325 | if (netif_running(dev)) { | |
10326 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | |
10327 | err = tg3_restart_hw(tp, 1); | |
10328 | if (!err) | |
10329 | tg3_netif_start(tp); | |
10330 | } | |
10331 | ||
10332 | tg3_full_unlock(tp); | |
10333 | } | |
10334 | ||
10335 | return err; | |
10336 | } | |
10337 | ||
10338 | static int tg3_get_sset_count(struct net_device *dev, int sset) | |
10339 | { | |
10340 | switch (sset) { | |
10341 | case ETH_SS_TEST: | |
10342 | return TG3_NUM_TEST; | |
10343 | case ETH_SS_STATS: | |
10344 | return TG3_NUM_STATS; | |
10345 | default: | |
10346 | return -EOPNOTSUPP; | |
10347 | } | |
10348 | } | |
10349 | ||
10350 | static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf) | |
10351 | { | |
10352 | switch (stringset) { | |
10353 | case ETH_SS_STATS: | |
10354 | memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys)); | |
10355 | break; | |
10356 | case ETH_SS_TEST: | |
10357 | memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys)); | |
10358 | break; | |
10359 | default: | |
10360 | WARN_ON(1); /* we need a WARN() */ | |
10361 | break; | |
10362 | } | |
10363 | } | |
10364 | ||
10365 | static int tg3_set_phys_id(struct net_device *dev, | |
10366 | enum ethtool_phys_id_state state) | |
10367 | { | |
10368 | struct tg3 *tp = netdev_priv(dev); | |
10369 | ||
10370 | if (!netif_running(tp->dev)) | |
10371 | return -EAGAIN; | |
10372 | ||
10373 | switch (state) { | |
10374 | case ETHTOOL_ID_ACTIVE: | |
10375 | return 1; /* cycle on/off once per second */ | |
10376 | ||
10377 | case ETHTOOL_ID_ON: | |
10378 | tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE | | |
10379 | LED_CTRL_1000MBPS_ON | | |
10380 | LED_CTRL_100MBPS_ON | | |
10381 | LED_CTRL_10MBPS_ON | | |
10382 | LED_CTRL_TRAFFIC_OVERRIDE | | |
10383 | LED_CTRL_TRAFFIC_BLINK | | |
10384 | LED_CTRL_TRAFFIC_LED); | |
10385 | break; | |
10386 | ||
10387 | case ETHTOOL_ID_OFF: | |
10388 | tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE | | |
10389 | LED_CTRL_TRAFFIC_OVERRIDE); | |
10390 | break; | |
10391 | ||
10392 | case ETHTOOL_ID_INACTIVE: | |
10393 | tw32(MAC_LED_CTRL, tp->led_ctrl); | |
10394 | break; | |
10395 | } | |
10396 | ||
10397 | return 0; | |
10398 | } | |
10399 | ||
10400 | static void tg3_get_ethtool_stats(struct net_device *dev, | |
10401 | struct ethtool_stats *estats, u64 *tmp_stats) | |
10402 | { | |
10403 | struct tg3 *tp = netdev_priv(dev); | |
10404 | memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats)); | |
10405 | } | |
10406 | ||
10407 | static __be32 * tg3_vpd_readblock(struct tg3 *tp) | |
10408 | { | |
10409 | int i; | |
10410 | __be32 *buf; | |
10411 | u32 offset = 0, len = 0; | |
10412 | u32 magic, val; | |
10413 | ||
10414 | if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic)) | |
10415 | return NULL; | |
10416 | ||
10417 | if (magic == TG3_EEPROM_MAGIC) { | |
10418 | for (offset = TG3_NVM_DIR_START; | |
10419 | offset < TG3_NVM_DIR_END; | |
10420 | offset += TG3_NVM_DIRENT_SIZE) { | |
10421 | if (tg3_nvram_read(tp, offset, &val)) | |
10422 | return NULL; | |
10423 | ||
10424 | if ((val >> TG3_NVM_DIRTYPE_SHIFT) == | |
10425 | TG3_NVM_DIRTYPE_EXTVPD) | |
10426 | break; | |
10427 | } | |
10428 | ||
10429 | if (offset != TG3_NVM_DIR_END) { | |
10430 | len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4; | |
10431 | if (tg3_nvram_read(tp, offset + 4, &offset)) | |
10432 | return NULL; | |
10433 | ||
10434 | offset = tg3_nvram_logical_addr(tp, offset); | |
10435 | } | |
10436 | } | |
10437 | ||
10438 | if (!offset || !len) { | |
10439 | offset = TG3_NVM_VPD_OFF; | |
10440 | len = TG3_NVM_VPD_LEN; | |
10441 | } | |
10442 | ||
10443 | buf = kmalloc(len, GFP_KERNEL); | |
10444 | if (buf == NULL) | |
10445 | return NULL; | |
10446 | ||
10447 | if (magic == TG3_EEPROM_MAGIC) { | |
10448 | for (i = 0; i < len; i += 4) { | |
10449 | /* The data is in little-endian format in NVRAM. | |
10450 | * Use the big-endian read routines to preserve | |
10451 | * the byte order as it exists in NVRAM. | |
10452 | */ | |
10453 | if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4])) | |
10454 | goto error; | |
10455 | } | |
10456 | } else { | |
10457 | u8 *ptr; | |
10458 | ssize_t cnt; | |
10459 | unsigned int pos = 0; | |
10460 | ||
10461 | ptr = (u8 *)&buf[0]; | |
10462 | for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) { | |
10463 | cnt = pci_read_vpd(tp->pdev, pos, | |
10464 | len - pos, ptr); | |
10465 | if (cnt == -ETIMEDOUT || cnt == -EINTR) | |
10466 | cnt = 0; | |
10467 | else if (cnt < 0) | |
10468 | goto error; | |
10469 | } | |
10470 | if (pos != len) | |
10471 | goto error; | |
10472 | } | |
10473 | ||
10474 | return buf; | |
10475 | ||
10476 | error: | |
10477 | kfree(buf); | |
10478 | return NULL; | |
10479 | } | |
10480 | ||
10481 | #define NVRAM_TEST_SIZE 0x100 | |
10482 | #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14 | |
10483 | #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18 | |
10484 | #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c | |
10485 | #define NVRAM_SELFBOOT_FORMAT1_4_SIZE 0x20 | |
10486 | #define NVRAM_SELFBOOT_FORMAT1_5_SIZE 0x24 | |
10487 | #define NVRAM_SELFBOOT_FORMAT1_6_SIZE 0x4c | |
10488 | #define NVRAM_SELFBOOT_HW_SIZE 0x20 | |
10489 | #define NVRAM_SELFBOOT_DATA_SIZE 0x1c | |
10490 | ||
10491 | static int tg3_test_nvram(struct tg3 *tp) | |
10492 | { | |
10493 | u32 csum, magic; | |
10494 | __be32 *buf; | |
10495 | int i, j, k, err = 0, size; | |
10496 | ||
10497 | if (tg3_flag(tp, NO_NVRAM)) | |
10498 | return 0; | |
10499 | ||
10500 | if (tg3_nvram_read(tp, 0, &magic) != 0) | |
10501 | return -EIO; | |
10502 | ||
10503 | if (magic == TG3_EEPROM_MAGIC) | |
10504 | size = NVRAM_TEST_SIZE; | |
10505 | else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) { | |
10506 | if ((magic & TG3_EEPROM_SB_FORMAT_MASK) == | |
10507 | TG3_EEPROM_SB_FORMAT_1) { | |
10508 | switch (magic & TG3_EEPROM_SB_REVISION_MASK) { | |
10509 | case TG3_EEPROM_SB_REVISION_0: | |
10510 | size = NVRAM_SELFBOOT_FORMAT1_0_SIZE; | |
10511 | break; | |
10512 | case TG3_EEPROM_SB_REVISION_2: | |
10513 | size = NVRAM_SELFBOOT_FORMAT1_2_SIZE; | |
10514 | break; | |
10515 | case TG3_EEPROM_SB_REVISION_3: | |
10516 | size = NVRAM_SELFBOOT_FORMAT1_3_SIZE; | |
10517 | break; | |
10518 | case TG3_EEPROM_SB_REVISION_4: | |
10519 | size = NVRAM_SELFBOOT_FORMAT1_4_SIZE; | |
10520 | break; | |
10521 | case TG3_EEPROM_SB_REVISION_5: | |
10522 | size = NVRAM_SELFBOOT_FORMAT1_5_SIZE; | |
10523 | break; | |
10524 | case TG3_EEPROM_SB_REVISION_6: | |
10525 | size = NVRAM_SELFBOOT_FORMAT1_6_SIZE; | |
10526 | break; | |
10527 | default: | |
10528 | return -EIO; | |
10529 | } | |
10530 | } else | |
10531 | return 0; | |
10532 | } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW) | |
10533 | size = NVRAM_SELFBOOT_HW_SIZE; | |
10534 | else | |
10535 | return -EIO; | |
10536 | ||
10537 | buf = kmalloc(size, GFP_KERNEL); | |
10538 | if (buf == NULL) | |
10539 | return -ENOMEM; | |
10540 | ||
10541 | err = -EIO; | |
10542 | for (i = 0, j = 0; i < size; i += 4, j++) { | |
10543 | err = tg3_nvram_read_be32(tp, i, &buf[j]); | |
10544 | if (err) | |
10545 | break; | |
10546 | } | |
10547 | if (i < size) | |
10548 | goto out; | |
10549 | ||
10550 | /* Selfboot format */ | |
10551 | magic = be32_to_cpu(buf[0]); | |
10552 | if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == | |
10553 | TG3_EEPROM_MAGIC_FW) { | |
10554 | u8 *buf8 = (u8 *) buf, csum8 = 0; | |
10555 | ||
10556 | if ((magic & TG3_EEPROM_SB_REVISION_MASK) == | |
10557 | TG3_EEPROM_SB_REVISION_2) { | |
10558 | /* For rev 2, the csum doesn't include the MBA. */ | |
10559 | for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++) | |
10560 | csum8 += buf8[i]; | |
10561 | for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++) | |
10562 | csum8 += buf8[i]; | |
10563 | } else { | |
10564 | for (i = 0; i < size; i++) | |
10565 | csum8 += buf8[i]; | |
10566 | } | |
10567 | ||
10568 | if (csum8 == 0) { | |
10569 | err = 0; | |
10570 | goto out; | |
10571 | } | |
10572 | ||
10573 | err = -EIO; | |
10574 | goto out; | |
10575 | } | |
10576 | ||
10577 | if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == | |
10578 | TG3_EEPROM_MAGIC_HW) { | |
10579 | u8 data[NVRAM_SELFBOOT_DATA_SIZE]; | |
10580 | u8 parity[NVRAM_SELFBOOT_DATA_SIZE]; | |
10581 | u8 *buf8 = (u8 *) buf; | |
10582 | ||
10583 | /* Separate the parity bits and the data bytes. */ | |
10584 | for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) { | |
10585 | if ((i == 0) || (i == 8)) { | |
10586 | int l; | |
10587 | u8 msk; | |
10588 | ||
10589 | for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1) | |
10590 | parity[k++] = buf8[i] & msk; | |
10591 | i++; | |
10592 | } else if (i == 16) { | |
10593 | int l; | |
10594 | u8 msk; | |
10595 | ||
10596 | for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1) | |
10597 | parity[k++] = buf8[i] & msk; | |
10598 | i++; | |
10599 | ||
10600 | for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1) | |
10601 | parity[k++] = buf8[i] & msk; | |
10602 | i++; | |
10603 | } | |
10604 | data[j++] = buf8[i]; | |
10605 | } | |
10606 | ||
10607 | err = -EIO; | |
10608 | for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) { | |
10609 | u8 hw8 = hweight8(data[i]); | |
10610 | ||
10611 | if ((hw8 & 0x1) && parity[i]) | |
10612 | goto out; | |
10613 | else if (!(hw8 & 0x1) && !parity[i]) | |
10614 | goto out; | |
10615 | } | |
10616 | err = 0; | |
10617 | goto out; | |
10618 | } | |
10619 | ||
10620 | err = -EIO; | |
10621 | ||
10622 | /* Bootstrap checksum at offset 0x10 */ | |
10623 | csum = calc_crc((unsigned char *) buf, 0x10); | |
10624 | if (csum != le32_to_cpu(buf[0x10/4])) | |
10625 | goto out; | |
10626 | ||
10627 | /* Manufacturing block starts at offset 0x74, checksum at 0xfc */ | |
10628 | csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88); | |
10629 | if (csum != le32_to_cpu(buf[0xfc/4])) | |
10630 | goto out; | |
10631 | ||
10632 | kfree(buf); | |
10633 | ||
10634 | buf = tg3_vpd_readblock(tp); | |
10635 | if (!buf) | |
10636 | return -ENOMEM; | |
10637 | ||
10638 | i = pci_vpd_find_tag((u8 *)buf, 0, TG3_NVM_VPD_LEN, | |
10639 | PCI_VPD_LRDT_RO_DATA); | |
10640 | if (i > 0) { | |
10641 | j = pci_vpd_lrdt_size(&((u8 *)buf)[i]); | |
10642 | if (j < 0) | |
10643 | goto out; | |
10644 | ||
10645 | if (i + PCI_VPD_LRDT_TAG_SIZE + j > TG3_NVM_VPD_LEN) | |
10646 | goto out; | |
10647 | ||
10648 | i += PCI_VPD_LRDT_TAG_SIZE; | |
10649 | j = pci_vpd_find_info_keyword((u8 *)buf, i, j, | |
10650 | PCI_VPD_RO_KEYWORD_CHKSUM); | |
10651 | if (j > 0) { | |
10652 | u8 csum8 = 0; | |
10653 | ||
10654 | j += PCI_VPD_INFO_FLD_HDR_SIZE; | |
10655 | ||
10656 | for (i = 0; i <= j; i++) | |
10657 | csum8 += ((u8 *)buf)[i]; | |
10658 | ||
10659 | if (csum8) | |
10660 | goto out; | |
10661 | } | |
10662 | } | |
10663 | ||
10664 | err = 0; | |
10665 | ||
10666 | out: | |
10667 | kfree(buf); | |
10668 | return err; | |
10669 | } | |
10670 | ||
10671 | #define TG3_SERDES_TIMEOUT_SEC 2 | |
10672 | #define TG3_COPPER_TIMEOUT_SEC 6 | |
10673 | ||
10674 | static int tg3_test_link(struct tg3 *tp) | |
10675 | { | |
10676 | int i, max; | |
10677 | ||
10678 | if (!netif_running(tp->dev)) | |
10679 | return -ENODEV; | |
10680 | ||
10681 | if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) | |
10682 | max = TG3_SERDES_TIMEOUT_SEC; | |
10683 | else | |
10684 | max = TG3_COPPER_TIMEOUT_SEC; | |
10685 | ||
10686 | for (i = 0; i < max; i++) { | |
10687 | if (netif_carrier_ok(tp->dev)) | |
10688 | return 0; | |
10689 | ||
10690 | if (msleep_interruptible(1000)) | |
10691 | break; | |
10692 | } | |
10693 | ||
10694 | return -EIO; | |
10695 | } | |
10696 | ||
10697 | /* Only test the commonly used registers */ | |
10698 | static int tg3_test_registers(struct tg3 *tp) | |
10699 | { | |
10700 | int i, is_5705, is_5750; | |
10701 | u32 offset, read_mask, write_mask, val, save_val, read_val; | |
10702 | static struct { | |
10703 | u16 offset; | |
10704 | u16 flags; | |
10705 | #define TG3_FL_5705 0x1 | |
10706 | #define TG3_FL_NOT_5705 0x2 | |
10707 | #define TG3_FL_NOT_5788 0x4 | |
10708 | #define TG3_FL_NOT_5750 0x8 | |
10709 | u32 read_mask; | |
10710 | u32 write_mask; | |
10711 | } reg_tbl[] = { | |
10712 | /* MAC Control Registers */ | |
10713 | { MAC_MODE, TG3_FL_NOT_5705, | |
10714 | 0x00000000, 0x00ef6f8c }, | |
10715 | { MAC_MODE, TG3_FL_5705, | |
10716 | 0x00000000, 0x01ef6b8c }, | |
10717 | { MAC_STATUS, TG3_FL_NOT_5705, | |
10718 | 0x03800107, 0x00000000 }, | |
10719 | { MAC_STATUS, TG3_FL_5705, | |
10720 | 0x03800100, 0x00000000 }, | |
10721 | { MAC_ADDR_0_HIGH, 0x0000, | |
10722 | 0x00000000, 0x0000ffff }, | |
10723 | { MAC_ADDR_0_LOW, 0x0000, | |
10724 | 0x00000000, 0xffffffff }, | |
10725 | { MAC_RX_MTU_SIZE, 0x0000, | |
10726 | 0x00000000, 0x0000ffff }, | |
10727 | { MAC_TX_MODE, 0x0000, | |
10728 | 0x00000000, 0x00000070 }, | |
10729 | { MAC_TX_LENGTHS, 0x0000, | |
10730 | 0x00000000, 0x00003fff }, | |
10731 | { MAC_RX_MODE, TG3_FL_NOT_5705, | |
10732 | 0x00000000, 0x000007fc }, | |
10733 | { MAC_RX_MODE, TG3_FL_5705, | |
10734 | 0x00000000, 0x000007dc }, | |
10735 | { MAC_HASH_REG_0, 0x0000, | |
10736 | 0x00000000, 0xffffffff }, | |
10737 | { MAC_HASH_REG_1, 0x0000, | |
10738 | 0x00000000, 0xffffffff }, | |
10739 | { MAC_HASH_REG_2, 0x0000, | |
10740 | 0x00000000, 0xffffffff }, | |
10741 | { MAC_HASH_REG_3, 0x0000, | |
10742 | 0x00000000, 0xffffffff }, | |
10743 | ||
10744 | /* Receive Data and Receive BD Initiator Control Registers. */ | |
10745 | { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705, | |
10746 | 0x00000000, 0xffffffff }, | |
10747 | { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705, | |
10748 | 0x00000000, 0xffffffff }, | |
10749 | { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705, | |
10750 | 0x00000000, 0x00000003 }, | |
10751 | { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705, | |
10752 | 0x00000000, 0xffffffff }, | |
10753 | { RCVDBDI_STD_BD+0, 0x0000, | |
10754 | 0x00000000, 0xffffffff }, | |
10755 | { RCVDBDI_STD_BD+4, 0x0000, | |
10756 | 0x00000000, 0xffffffff }, | |
10757 | { RCVDBDI_STD_BD+8, 0x0000, | |
10758 | 0x00000000, 0xffff0002 }, | |
10759 | { RCVDBDI_STD_BD+0xc, 0x0000, | |
10760 | 0x00000000, 0xffffffff }, | |
10761 | ||
10762 | /* Receive BD Initiator Control Registers. */ | |
10763 | { RCVBDI_STD_THRESH, TG3_FL_NOT_5705, | |
10764 | 0x00000000, 0xffffffff }, | |
10765 | { RCVBDI_STD_THRESH, TG3_FL_5705, | |
10766 | 0x00000000, 0x000003ff }, | |
10767 | { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705, | |
10768 | 0x00000000, 0xffffffff }, | |
10769 | ||
10770 | /* Host Coalescing Control Registers. */ | |
10771 | { HOSTCC_MODE, TG3_FL_NOT_5705, | |
10772 | 0x00000000, 0x00000004 }, | |
10773 | { HOSTCC_MODE, TG3_FL_5705, | |
10774 | 0x00000000, 0x000000f6 }, | |
10775 | { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705, | |
10776 | 0x00000000, 0xffffffff }, | |
10777 | { HOSTCC_RXCOL_TICKS, TG3_FL_5705, | |
10778 | 0x00000000, 0x000003ff }, | |
10779 | { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705, | |
10780 | 0x00000000, 0xffffffff }, | |
10781 | { HOSTCC_TXCOL_TICKS, TG3_FL_5705, | |
10782 | 0x00000000, 0x000003ff }, | |
10783 | { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705, | |
10784 | 0x00000000, 0xffffffff }, | |
10785 | { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788, | |
10786 | 0x00000000, 0x000000ff }, | |
10787 | { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705, | |
10788 | 0x00000000, 0xffffffff }, | |
10789 | { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788, | |
10790 | 0x00000000, 0x000000ff }, | |
10791 | { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705, | |
10792 | 0x00000000, 0xffffffff }, | |
10793 | { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705, | |
10794 | 0x00000000, 0xffffffff }, | |
10795 | { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705, | |
10796 | 0x00000000, 0xffffffff }, | |
10797 | { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788, | |
10798 | 0x00000000, 0x000000ff }, | |
10799 | { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705, | |
10800 | 0x00000000, 0xffffffff }, | |
10801 | { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788, | |
10802 | 0x00000000, 0x000000ff }, | |
10803 | { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705, | |
10804 | 0x00000000, 0xffffffff }, | |
10805 | { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705, | |
10806 | 0x00000000, 0xffffffff }, | |
10807 | { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705, | |
10808 | 0x00000000, 0xffffffff }, | |
10809 | { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000, | |
10810 | 0x00000000, 0xffffffff }, | |
10811 | { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000, | |
10812 | 0x00000000, 0xffffffff }, | |
10813 | { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000, | |
10814 | 0xffffffff, 0x00000000 }, | |
10815 | { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000, | |
10816 | 0xffffffff, 0x00000000 }, | |
10817 | ||
10818 | /* Buffer Manager Control Registers. */ | |
10819 | { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750, | |
10820 | 0x00000000, 0x007fff80 }, | |
10821 | { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750, | |
10822 | 0x00000000, 0x007fffff }, | |
10823 | { BUFMGR_MB_RDMA_LOW_WATER, 0x0000, | |
10824 | 0x00000000, 0x0000003f }, | |
10825 | { BUFMGR_MB_MACRX_LOW_WATER, 0x0000, | |
10826 | 0x00000000, 0x000001ff }, | |
10827 | { BUFMGR_MB_HIGH_WATER, 0x0000, | |
10828 | 0x00000000, 0x000001ff }, | |
10829 | { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705, | |
10830 | 0xffffffff, 0x00000000 }, | |
10831 | { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705, | |
10832 | 0xffffffff, 0x00000000 }, | |
10833 | ||
10834 | /* Mailbox Registers */ | |
10835 | { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000, | |
10836 | 0x00000000, 0x000001ff }, | |
10837 | { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705, | |
10838 | 0x00000000, 0x000001ff }, | |
10839 | { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000, | |
10840 | 0x00000000, 0x000007ff }, | |
10841 | { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000, | |
10842 | 0x00000000, 0x000001ff }, | |
10843 | ||
10844 | { 0xffff, 0x0000, 0x00000000, 0x00000000 }, | |
10845 | }; | |
10846 | ||
10847 | is_5705 = is_5750 = 0; | |
10848 | if (tg3_flag(tp, 5705_PLUS)) { | |
10849 | is_5705 = 1; | |
10850 | if (tg3_flag(tp, 5750_PLUS)) | |
10851 | is_5750 = 1; | |
10852 | } | |
10853 | ||
10854 | for (i = 0; reg_tbl[i].offset != 0xffff; i++) { | |
10855 | if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705)) | |
10856 | continue; | |
10857 | ||
10858 | if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705)) | |
10859 | continue; | |
10860 | ||
10861 | if (tg3_flag(tp, IS_5788) && | |
10862 | (reg_tbl[i].flags & TG3_FL_NOT_5788)) | |
10863 | continue; | |
10864 | ||
10865 | if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750)) | |
10866 | continue; | |
10867 | ||
10868 | offset = (u32) reg_tbl[i].offset; | |
10869 | read_mask = reg_tbl[i].read_mask; | |
10870 | write_mask = reg_tbl[i].write_mask; | |
10871 | ||
10872 | /* Save the original register content */ | |
10873 | save_val = tr32(offset); | |
10874 | ||
10875 | /* Determine the read-only value. */ | |
10876 | read_val = save_val & read_mask; | |
10877 | ||
10878 | /* Write zero to the register, then make sure the read-only bits | |
10879 | * are not changed and the read/write bits are all zeros. | |
10880 | */ | |
10881 | tw32(offset, 0); | |
10882 | ||
10883 | val = tr32(offset); | |
10884 | ||
10885 | /* Test the read-only and read/write bits. */ | |
10886 | if (((val & read_mask) != read_val) || (val & write_mask)) | |
10887 | goto out; | |
10888 | ||
10889 | /* Write ones to all the bits defined by RdMask and WrMask, then | |
10890 | * make sure the read-only bits are not changed and the | |
10891 | * read/write bits are all ones. | |
10892 | */ | |
10893 | tw32(offset, read_mask | write_mask); | |
10894 | ||
10895 | val = tr32(offset); | |
10896 | ||
10897 | /* Test the read-only bits. */ | |
10898 | if ((val & read_mask) != read_val) | |
10899 | goto out; | |
10900 | ||
10901 | /* Test the read/write bits. */ | |
10902 | if ((val & write_mask) != write_mask) | |
10903 | goto out; | |
10904 | ||
10905 | tw32(offset, save_val); | |
10906 | } | |
10907 | ||
10908 | return 0; | |
10909 | ||
10910 | out: | |
10911 | if (netif_msg_hw(tp)) | |
10912 | netdev_err(tp->dev, | |
10913 | "Register test failed at offset %x\n", offset); | |
10914 | tw32(offset, save_val); | |
10915 | return -EIO; | |
10916 | } | |
10917 | ||
10918 | static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len) | |
10919 | { | |
10920 | static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a }; | |
10921 | int i; | |
10922 | u32 j; | |
10923 | ||
10924 | for (i = 0; i < ARRAY_SIZE(test_pattern); i++) { | |
10925 | for (j = 0; j < len; j += 4) { | |
10926 | u32 val; | |
10927 | ||
10928 | tg3_write_mem(tp, offset + j, test_pattern[i]); | |
10929 | tg3_read_mem(tp, offset + j, &val); | |
10930 | if (val != test_pattern[i]) | |
10931 | return -EIO; | |
10932 | } | |
10933 | } | |
10934 | return 0; | |
10935 | } | |
10936 | ||
10937 | static int tg3_test_memory(struct tg3 *tp) | |
10938 | { | |
10939 | static struct mem_entry { | |
10940 | u32 offset; | |
10941 | u32 len; | |
10942 | } mem_tbl_570x[] = { | |
10943 | { 0x00000000, 0x00b50}, | |
10944 | { 0x00002000, 0x1c000}, | |
10945 | { 0xffffffff, 0x00000} | |
10946 | }, mem_tbl_5705[] = { | |
10947 | { 0x00000100, 0x0000c}, | |
10948 | { 0x00000200, 0x00008}, | |
10949 | { 0x00004000, 0x00800}, | |
10950 | { 0x00006000, 0x01000}, | |
10951 | { 0x00008000, 0x02000}, | |
10952 | { 0x00010000, 0x0e000}, | |
10953 | { 0xffffffff, 0x00000} | |
10954 | }, mem_tbl_5755[] = { | |
10955 | { 0x00000200, 0x00008}, | |
10956 | { 0x00004000, 0x00800}, | |
10957 | { 0x00006000, 0x00800}, | |
10958 | { 0x00008000, 0x02000}, | |
10959 | { 0x00010000, 0x0c000}, | |
10960 | { 0xffffffff, 0x00000} | |
10961 | }, mem_tbl_5906[] = { | |
10962 | { 0x00000200, 0x00008}, | |
10963 | { 0x00004000, 0x00400}, | |
10964 | { 0x00006000, 0x00400}, | |
10965 | { 0x00008000, 0x01000}, | |
10966 | { 0x00010000, 0x01000}, | |
10967 | { 0xffffffff, 0x00000} | |
10968 | }, mem_tbl_5717[] = { | |
10969 | { 0x00000200, 0x00008}, | |
10970 | { 0x00010000, 0x0a000}, | |
10971 | { 0x00020000, 0x13c00}, | |
10972 | { 0xffffffff, 0x00000} | |
10973 | }, mem_tbl_57765[] = { | |
10974 | { 0x00000200, 0x00008}, | |
10975 | { 0x00004000, 0x00800}, | |
10976 | { 0x00006000, 0x09800}, | |
10977 | { 0x00010000, 0x0a000}, | |
10978 | { 0xffffffff, 0x00000} | |
10979 | }; | |
10980 | struct mem_entry *mem_tbl; | |
10981 | int err = 0; | |
10982 | int i; | |
10983 | ||
10984 | if (tg3_flag(tp, 5717_PLUS)) | |
10985 | mem_tbl = mem_tbl_5717; | |
10986 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
10987 | mem_tbl = mem_tbl_57765; | |
10988 | else if (tg3_flag(tp, 5755_PLUS)) | |
10989 | mem_tbl = mem_tbl_5755; | |
10990 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
10991 | mem_tbl = mem_tbl_5906; | |
10992 | else if (tg3_flag(tp, 5705_PLUS)) | |
10993 | mem_tbl = mem_tbl_5705; | |
10994 | else | |
10995 | mem_tbl = mem_tbl_570x; | |
10996 | ||
10997 | for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) { | |
10998 | err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len); | |
10999 | if (err) | |
11000 | break; | |
11001 | } | |
11002 | ||
11003 | return err; | |
11004 | } | |
11005 | ||
11006 | #define TG3_MAC_LOOPBACK 0 | |
11007 | #define TG3_PHY_LOOPBACK 1 | |
11008 | #define TG3_TSO_LOOPBACK 2 | |
11009 | ||
11010 | #define TG3_TSO_MSS 500 | |
11011 | ||
11012 | #define TG3_TSO_IP_HDR_LEN 20 | |
11013 | #define TG3_TSO_TCP_HDR_LEN 20 | |
11014 | #define TG3_TSO_TCP_OPT_LEN 12 | |
11015 | ||
11016 | static const u8 tg3_tso_header[] = { | |
11017 | 0x08, 0x00, | |
11018 | 0x45, 0x00, 0x00, 0x00, | |
11019 | 0x00, 0x00, 0x40, 0x00, | |
11020 | 0x40, 0x06, 0x00, 0x00, | |
11021 | 0x0a, 0x00, 0x00, 0x01, | |
11022 | 0x0a, 0x00, 0x00, 0x02, | |
11023 | 0x0d, 0x00, 0xe0, 0x00, | |
11024 | 0x00, 0x00, 0x01, 0x00, | |
11025 | 0x00, 0x00, 0x02, 0x00, | |
11026 | 0x80, 0x10, 0x10, 0x00, | |
11027 | 0x14, 0x09, 0x00, 0x00, | |
11028 | 0x01, 0x01, 0x08, 0x0a, | |
11029 | 0x11, 0x11, 0x11, 0x11, | |
11030 | 0x11, 0x11, 0x11, 0x11, | |
11031 | }; | |
11032 | ||
11033 | static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, int loopback_mode) | |
11034 | { | |
11035 | u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key; | |
11036 | u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val; | |
11037 | struct sk_buff *skb, *rx_skb; | |
11038 | u8 *tx_data; | |
11039 | dma_addr_t map; | |
11040 | int num_pkts, tx_len, rx_len, i, err; | |
11041 | struct tg3_rx_buffer_desc *desc; | |
11042 | struct tg3_napi *tnapi, *rnapi; | |
11043 | struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring; | |
11044 | ||
11045 | tnapi = &tp->napi[0]; | |
11046 | rnapi = &tp->napi[0]; | |
11047 | if (tp->irq_cnt > 1) { | |
11048 | if (tg3_flag(tp, ENABLE_RSS)) | |
11049 | rnapi = &tp->napi[1]; | |
11050 | if (tg3_flag(tp, ENABLE_TSS)) | |
11051 | tnapi = &tp->napi[1]; | |
11052 | } | |
11053 | coal_now = tnapi->coal_now | rnapi->coal_now; | |
11054 | ||
11055 | if (loopback_mode == TG3_MAC_LOOPBACK) { | |
11056 | /* HW errata - mac loopback fails in some cases on 5780. | |
11057 | * Normal traffic and PHY loopback are not affected by | |
11058 | * errata. Also, the MAC loopback test is deprecated for | |
11059 | * all newer ASIC revisions. | |
11060 | */ | |
11061 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 || | |
11062 | tg3_flag(tp, CPMU_PRESENT)) | |
11063 | return 0; | |
11064 | ||
11065 | mac_mode = tp->mac_mode & | |
11066 | ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX); | |
11067 | mac_mode |= MAC_MODE_PORT_INT_LPBACK; | |
11068 | if (!tg3_flag(tp, 5705_PLUS)) | |
11069 | mac_mode |= MAC_MODE_LINK_POLARITY; | |
11070 | if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) | |
11071 | mac_mode |= MAC_MODE_PORT_MODE_MII; | |
11072 | else | |
11073 | mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
11074 | tw32(MAC_MODE, mac_mode); | |
11075 | } else { | |
11076 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { | |
11077 | tg3_phy_fet_toggle_apd(tp, false); | |
11078 | val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100; | |
11079 | } else | |
11080 | val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000; | |
11081 | ||
11082 | tg3_phy_toggle_automdix(tp, 0); | |
11083 | ||
11084 | tg3_writephy(tp, MII_BMCR, val); | |
11085 | udelay(40); | |
11086 | ||
11087 | mac_mode = tp->mac_mode & | |
11088 | ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX); | |
11089 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { | |
11090 | tg3_writephy(tp, MII_TG3_FET_PTEST, | |
11091 | MII_TG3_FET_PTEST_FRC_TX_LINK | | |
11092 | MII_TG3_FET_PTEST_FRC_TX_LOCK); | |
11093 | /* The write needs to be flushed for the AC131 */ | |
11094 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | |
11095 | tg3_readphy(tp, MII_TG3_FET_PTEST, &val); | |
11096 | mac_mode |= MAC_MODE_PORT_MODE_MII; | |
11097 | } else | |
11098 | mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
11099 | ||
11100 | /* reset to prevent losing 1st rx packet intermittently */ | |
11101 | if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { | |
11102 | tw32_f(MAC_RX_MODE, RX_MODE_RESET); | |
11103 | udelay(10); | |
11104 | tw32_f(MAC_RX_MODE, tp->rx_mode); | |
11105 | } | |
11106 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) { | |
11107 | u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK; | |
11108 | if (masked_phy_id == TG3_PHY_ID_BCM5401) | |
11109 | mac_mode &= ~MAC_MODE_LINK_POLARITY; | |
11110 | else if (masked_phy_id == TG3_PHY_ID_BCM5411) | |
11111 | mac_mode |= MAC_MODE_LINK_POLARITY; | |
11112 | tg3_writephy(tp, MII_TG3_EXT_CTRL, | |
11113 | MII_TG3_EXT_CTRL_LNK3_LED_MODE); | |
11114 | } | |
11115 | tw32(MAC_MODE, mac_mode); | |
11116 | ||
11117 | /* Wait for link */ | |
11118 | for (i = 0; i < 100; i++) { | |
11119 | if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) | |
11120 | break; | |
11121 | mdelay(1); | |
11122 | } | |
11123 | } | |
11124 | ||
11125 | err = -EIO; | |
11126 | ||
11127 | tx_len = pktsz; | |
11128 | skb = netdev_alloc_skb(tp->dev, tx_len); | |
11129 | if (!skb) | |
11130 | return -ENOMEM; | |
11131 | ||
11132 | tx_data = skb_put(skb, tx_len); | |
11133 | memcpy(tx_data, tp->dev->dev_addr, 6); | |
11134 | memset(tx_data + 6, 0x0, 8); | |
11135 | ||
11136 | tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN); | |
11137 | ||
11138 | if (loopback_mode == TG3_TSO_LOOPBACK) { | |
11139 | struct iphdr *iph = (struct iphdr *)&tx_data[ETH_HLEN]; | |
11140 | ||
11141 | u32 hdr_len = TG3_TSO_IP_HDR_LEN + TG3_TSO_TCP_HDR_LEN + | |
11142 | TG3_TSO_TCP_OPT_LEN; | |
11143 | ||
11144 | memcpy(tx_data + ETH_ALEN * 2, tg3_tso_header, | |
11145 | sizeof(tg3_tso_header)); | |
11146 | mss = TG3_TSO_MSS; | |
11147 | ||
11148 | val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header); | |
11149 | num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS); | |
11150 | ||
11151 | /* Set the total length field in the IP header */ | |
11152 | iph->tot_len = htons((u16)(mss + hdr_len)); | |
11153 | ||
11154 | base_flags = (TXD_FLAG_CPU_PRE_DMA | | |
11155 | TXD_FLAG_CPU_POST_DMA); | |
11156 | ||
11157 | if (tg3_flag(tp, HW_TSO_1) || | |
11158 | tg3_flag(tp, HW_TSO_2) || | |
11159 | tg3_flag(tp, HW_TSO_3)) { | |
11160 | struct tcphdr *th; | |
11161 | val = ETH_HLEN + TG3_TSO_IP_HDR_LEN; | |
11162 | th = (struct tcphdr *)&tx_data[val]; | |
11163 | th->check = 0; | |
11164 | } else | |
11165 | base_flags |= TXD_FLAG_TCPUDP_CSUM; | |
11166 | ||
11167 | if (tg3_flag(tp, HW_TSO_3)) { | |
11168 | mss |= (hdr_len & 0xc) << 12; | |
11169 | if (hdr_len & 0x10) | |
11170 | base_flags |= 0x00000010; | |
11171 | base_flags |= (hdr_len & 0x3e0) << 5; | |
11172 | } else if (tg3_flag(tp, HW_TSO_2)) | |
11173 | mss |= hdr_len << 9; | |
11174 | else if (tg3_flag(tp, HW_TSO_1) || | |
11175 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | |
11176 | mss |= (TG3_TSO_TCP_OPT_LEN << 9); | |
11177 | } else { | |
11178 | base_flags |= (TG3_TSO_TCP_OPT_LEN << 10); | |
11179 | } | |
11180 | ||
11181 | data_off = ETH_ALEN * 2 + sizeof(tg3_tso_header); | |
11182 | } else { | |
11183 | num_pkts = 1; | |
11184 | data_off = ETH_HLEN; | |
11185 | } | |
11186 | ||
11187 | for (i = data_off; i < tx_len; i++) | |
11188 | tx_data[i] = (u8) (i & 0xff); | |
11189 | ||
11190 | map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE); | |
11191 | if (pci_dma_mapping_error(tp->pdev, map)) { | |
11192 | dev_kfree_skb(skb); | |
11193 | return -EIO; | |
11194 | } | |
11195 | ||
11196 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | | |
11197 | rnapi->coal_now); | |
11198 | ||
11199 | udelay(10); | |
11200 | ||
11201 | rx_start_idx = rnapi->hw_status->idx[0].rx_producer; | |
11202 | ||
11203 | tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, | |
11204 | base_flags, (mss << 1) | 1); | |
11205 | ||
11206 | tnapi->tx_prod++; | |
11207 | ||
11208 | tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod); | |
11209 | tr32_mailbox(tnapi->prodmbox); | |
11210 | ||
11211 | udelay(10); | |
11212 | ||
11213 | /* 350 usec to allow enough time on some 10/100 Mbps devices. */ | |
11214 | for (i = 0; i < 35; i++) { | |
11215 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | | |
11216 | coal_now); | |
11217 | ||
11218 | udelay(10); | |
11219 | ||
11220 | tx_idx = tnapi->hw_status->idx[0].tx_consumer; | |
11221 | rx_idx = rnapi->hw_status->idx[0].rx_producer; | |
11222 | if ((tx_idx == tnapi->tx_prod) && | |
11223 | (rx_idx == (rx_start_idx + num_pkts))) | |
11224 | break; | |
11225 | } | |
11226 | ||
11227 | pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE); | |
11228 | dev_kfree_skb(skb); | |
11229 | ||
11230 | if (tx_idx != tnapi->tx_prod) | |
11231 | goto out; | |
11232 | ||
11233 | if (rx_idx != rx_start_idx + num_pkts) | |
11234 | goto out; | |
11235 | ||
11236 | val = data_off; | |
11237 | while (rx_idx != rx_start_idx) { | |
11238 | desc = &rnapi->rx_rcb[rx_start_idx++]; | |
11239 | desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK; | |
11240 | opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK; | |
11241 | ||
11242 | if ((desc->err_vlan & RXD_ERR_MASK) != 0 && | |
11243 | (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) | |
11244 | goto out; | |
11245 | ||
11246 | rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) | |
11247 | - ETH_FCS_LEN; | |
11248 | ||
11249 | if (loopback_mode != TG3_TSO_LOOPBACK) { | |
11250 | if (rx_len != tx_len) | |
11251 | goto out; | |
11252 | ||
11253 | if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) { | |
11254 | if (opaque_key != RXD_OPAQUE_RING_STD) | |
11255 | goto out; | |
11256 | } else { | |
11257 | if (opaque_key != RXD_OPAQUE_RING_JUMBO) | |
11258 | goto out; | |
11259 | } | |
11260 | } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) && | |
11261 | (desc->ip_tcp_csum & RXD_TCPCSUM_MASK) | |
11262 | >> RXD_TCPCSUM_SHIFT != 0xffff) { | |
11263 | goto out; | |
11264 | } | |
11265 | ||
11266 | if (opaque_key == RXD_OPAQUE_RING_STD) { | |
11267 | rx_skb = tpr->rx_std_buffers[desc_idx].skb; | |
11268 | map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], | |
11269 | mapping); | |
11270 | } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) { | |
11271 | rx_skb = tpr->rx_jmb_buffers[desc_idx].skb; | |
11272 | map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx], | |
11273 | mapping); | |
11274 | } else | |
11275 | goto out; | |
11276 | ||
11277 | pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, | |
11278 | PCI_DMA_FROMDEVICE); | |
11279 | ||
11280 | for (i = data_off; i < rx_len; i++, val++) { | |
11281 | if (*(rx_skb->data + i) != (u8) (val & 0xff)) | |
11282 | goto out; | |
11283 | } | |
11284 | } | |
11285 | ||
11286 | err = 0; | |
11287 | ||
11288 | /* tg3_free_rings will unmap and free the rx_skb */ | |
11289 | out: | |
11290 | return err; | |
11291 | } | |
11292 | ||
11293 | #define TG3_STD_LOOPBACK_FAILED 1 | |
11294 | #define TG3_JMB_LOOPBACK_FAILED 2 | |
11295 | #define TG3_TSO_LOOPBACK_FAILED 4 | |
11296 | ||
11297 | #define TG3_MAC_LOOPBACK_SHIFT 0 | |
11298 | #define TG3_PHY_LOOPBACK_SHIFT 4 | |
11299 | #define TG3_LOOPBACK_FAILED 0x00000077 | |
11300 | ||
11301 | static int tg3_test_loopback(struct tg3 *tp) | |
11302 | { | |
11303 | int err = 0; | |
11304 | u32 eee_cap, cpmuctrl = 0; | |
11305 | ||
11306 | if (!netif_running(tp->dev)) | |
11307 | return TG3_LOOPBACK_FAILED; | |
11308 | ||
11309 | eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP; | |
11310 | tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP; | |
11311 | ||
11312 | err = tg3_reset_hw(tp, 1); | |
11313 | if (err) { | |
11314 | err = TG3_LOOPBACK_FAILED; | |
11315 | goto done; | |
11316 | } | |
11317 | ||
11318 | if (tg3_flag(tp, ENABLE_RSS)) { | |
11319 | int i; | |
11320 | ||
11321 | /* Reroute all rx packets to the 1st queue */ | |
11322 | for (i = MAC_RSS_INDIR_TBL_0; | |
11323 | i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4) | |
11324 | tw32(i, 0x0); | |
11325 | } | |
11326 | ||
11327 | /* Turn off gphy autopowerdown. */ | |
11328 | if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) | |
11329 | tg3_phy_toggle_apd(tp, false); | |
11330 | ||
11331 | if (tg3_flag(tp, CPMU_PRESENT)) { | |
11332 | int i; | |
11333 | u32 status; | |
11334 | ||
11335 | tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER); | |
11336 | ||
11337 | /* Wait for up to 40 microseconds to acquire lock. */ | |
11338 | for (i = 0; i < 4; i++) { | |
11339 | status = tr32(TG3_CPMU_MUTEX_GNT); | |
11340 | if (status == CPMU_MUTEX_GNT_DRIVER) | |
11341 | break; | |
11342 | udelay(10); | |
11343 | } | |
11344 | ||
11345 | if (status != CPMU_MUTEX_GNT_DRIVER) { | |
11346 | err = TG3_LOOPBACK_FAILED; | |
11347 | goto done; | |
11348 | } | |
11349 | ||
11350 | /* Turn off link-based power management. */ | |
11351 | cpmuctrl = tr32(TG3_CPMU_CTRL); | |
11352 | tw32(TG3_CPMU_CTRL, | |
11353 | cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE | | |
11354 | CPMU_CTRL_LINK_AWARE_MODE)); | |
11355 | } | |
11356 | ||
11357 | if (tg3_run_loopback(tp, ETH_FRAME_LEN, TG3_MAC_LOOPBACK)) | |
11358 | err |= TG3_STD_LOOPBACK_FAILED << TG3_MAC_LOOPBACK_SHIFT; | |
11359 | ||
11360 | if (tg3_flag(tp, JUMBO_RING_ENABLE) && | |
11361 | tg3_run_loopback(tp, 9000 + ETH_HLEN, TG3_MAC_LOOPBACK)) | |
11362 | err |= TG3_JMB_LOOPBACK_FAILED << TG3_MAC_LOOPBACK_SHIFT; | |
11363 | ||
11364 | if (tg3_flag(tp, CPMU_PRESENT)) { | |
11365 | tw32(TG3_CPMU_CTRL, cpmuctrl); | |
11366 | ||
11367 | /* Release the mutex */ | |
11368 | tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER); | |
11369 | } | |
11370 | ||
11371 | if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && | |
11372 | !tg3_flag(tp, USE_PHYLIB)) { | |
11373 | if (tg3_run_loopback(tp, ETH_FRAME_LEN, TG3_PHY_LOOPBACK)) | |
11374 | err |= TG3_STD_LOOPBACK_FAILED << | |
11375 | TG3_PHY_LOOPBACK_SHIFT; | |
11376 | if (tg3_flag(tp, TSO_CAPABLE) && | |
11377 | tg3_run_loopback(tp, ETH_FRAME_LEN, TG3_TSO_LOOPBACK)) | |
11378 | err |= TG3_TSO_LOOPBACK_FAILED << | |
11379 | TG3_PHY_LOOPBACK_SHIFT; | |
11380 | if (tg3_flag(tp, JUMBO_RING_ENABLE) && | |
11381 | tg3_run_loopback(tp, 9000 + ETH_HLEN, TG3_PHY_LOOPBACK)) | |
11382 | err |= TG3_JMB_LOOPBACK_FAILED << | |
11383 | TG3_PHY_LOOPBACK_SHIFT; | |
11384 | } | |
11385 | ||
11386 | /* Re-enable gphy autopowerdown. */ | |
11387 | if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) | |
11388 | tg3_phy_toggle_apd(tp, true); | |
11389 | ||
11390 | done: | |
11391 | tp->phy_flags |= eee_cap; | |
11392 | ||
11393 | return err; | |
11394 | } | |
11395 | ||
11396 | static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest, | |
11397 | u64 *data) | |
11398 | { | |
11399 | struct tg3 *tp = netdev_priv(dev); | |
11400 | ||
11401 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) | |
11402 | tg3_power_up(tp); | |
11403 | ||
11404 | memset(data, 0, sizeof(u64) * TG3_NUM_TEST); | |
11405 | ||
11406 | if (tg3_test_nvram(tp) != 0) { | |
11407 | etest->flags |= ETH_TEST_FL_FAILED; | |
11408 | data[0] = 1; | |
11409 | } | |
11410 | if (tg3_test_link(tp) != 0) { | |
11411 | etest->flags |= ETH_TEST_FL_FAILED; | |
11412 | data[1] = 1; | |
11413 | } | |
11414 | if (etest->flags & ETH_TEST_FL_OFFLINE) { | |
11415 | int err, err2 = 0, irq_sync = 0; | |
11416 | ||
11417 | if (netif_running(dev)) { | |
11418 | tg3_phy_stop(tp); | |
11419 | tg3_netif_stop(tp); | |
11420 | irq_sync = 1; | |
11421 | } | |
11422 | ||
11423 | tg3_full_lock(tp, irq_sync); | |
11424 | ||
11425 | tg3_halt(tp, RESET_KIND_SUSPEND, 1); | |
11426 | err = tg3_nvram_lock(tp); | |
11427 | tg3_halt_cpu(tp, RX_CPU_BASE); | |
11428 | if (!tg3_flag(tp, 5705_PLUS)) | |
11429 | tg3_halt_cpu(tp, TX_CPU_BASE); | |
11430 | if (!err) | |
11431 | tg3_nvram_unlock(tp); | |
11432 | ||
11433 | if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) | |
11434 | tg3_phy_reset(tp); | |
11435 | ||
11436 | if (tg3_test_registers(tp) != 0) { | |
11437 | etest->flags |= ETH_TEST_FL_FAILED; | |
11438 | data[2] = 1; | |
11439 | } | |
11440 | if (tg3_test_memory(tp) != 0) { | |
11441 | etest->flags |= ETH_TEST_FL_FAILED; | |
11442 | data[3] = 1; | |
11443 | } | |
11444 | if ((data[4] = tg3_test_loopback(tp)) != 0) | |
11445 | etest->flags |= ETH_TEST_FL_FAILED; | |
11446 | ||
11447 | tg3_full_unlock(tp); | |
11448 | ||
11449 | if (tg3_test_interrupt(tp) != 0) { | |
11450 | etest->flags |= ETH_TEST_FL_FAILED; | |
11451 | data[5] = 1; | |
11452 | } | |
11453 | ||
11454 | tg3_full_lock(tp, 0); | |
11455 | ||
11456 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | |
11457 | if (netif_running(dev)) { | |
11458 | tg3_flag_set(tp, INIT_COMPLETE); | |
11459 | err2 = tg3_restart_hw(tp, 1); | |
11460 | if (!err2) | |
11461 | tg3_netif_start(tp); | |
11462 | } | |
11463 | ||
11464 | tg3_full_unlock(tp); | |
11465 | ||
11466 | if (irq_sync && !err2) | |
11467 | tg3_phy_start(tp); | |
11468 | } | |
11469 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) | |
11470 | tg3_power_down(tp); | |
11471 | ||
11472 | } | |
11473 | ||
11474 | static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
11475 | { | |
11476 | struct mii_ioctl_data *data = if_mii(ifr); | |
11477 | struct tg3 *tp = netdev_priv(dev); | |
11478 | int err; | |
11479 | ||
11480 | if (tg3_flag(tp, USE_PHYLIB)) { | |
11481 | struct phy_device *phydev; | |
11482 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) | |
11483 | return -EAGAIN; | |
11484 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; | |
11485 | return phy_mii_ioctl(phydev, ifr, cmd); | |
11486 | } | |
11487 | ||
11488 | switch (cmd) { | |
11489 | case SIOCGMIIPHY: | |
11490 | data->phy_id = tp->phy_addr; | |
11491 | ||
11492 | /* fallthru */ | |
11493 | case SIOCGMIIREG: { | |
11494 | u32 mii_regval; | |
11495 | ||
11496 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) | |
11497 | break; /* We have no PHY */ | |
11498 | ||
11499 | if (!netif_running(dev)) | |
11500 | return -EAGAIN; | |
11501 | ||
11502 | spin_lock_bh(&tp->lock); | |
11503 | err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval); | |
11504 | spin_unlock_bh(&tp->lock); | |
11505 | ||
11506 | data->val_out = mii_regval; | |
11507 | ||
11508 | return err; | |
11509 | } | |
11510 | ||
11511 | case SIOCSMIIREG: | |
11512 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) | |
11513 | break; /* We have no PHY */ | |
11514 | ||
11515 | if (!netif_running(dev)) | |
11516 | return -EAGAIN; | |
11517 | ||
11518 | spin_lock_bh(&tp->lock); | |
11519 | err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in); | |
11520 | spin_unlock_bh(&tp->lock); | |
11521 | ||
11522 | return err; | |
11523 | ||
11524 | default: | |
11525 | /* do nothing */ | |
11526 | break; | |
11527 | } | |
11528 | return -EOPNOTSUPP; | |
11529 | } | |
11530 | ||
11531 | static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) | |
11532 | { | |
11533 | struct tg3 *tp = netdev_priv(dev); | |
11534 | ||
11535 | memcpy(ec, &tp->coal, sizeof(*ec)); | |
11536 | return 0; | |
11537 | } | |
11538 | ||
11539 | static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) | |
11540 | { | |
11541 | struct tg3 *tp = netdev_priv(dev); | |
11542 | u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0; | |
11543 | u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0; | |
11544 | ||
11545 | if (!tg3_flag(tp, 5705_PLUS)) { | |
11546 | max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT; | |
11547 | max_txcoal_tick_int = MAX_TXCOAL_TICK_INT; | |
11548 | max_stat_coal_ticks = MAX_STAT_COAL_TICKS; | |
11549 | min_stat_coal_ticks = MIN_STAT_COAL_TICKS; | |
11550 | } | |
11551 | ||
11552 | if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) || | |
11553 | (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) || | |
11554 | (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) || | |
11555 | (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) || | |
11556 | (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) || | |
11557 | (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) || | |
11558 | (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) || | |
11559 | (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) || | |
11560 | (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) || | |
11561 | (ec->stats_block_coalesce_usecs < min_stat_coal_ticks)) | |
11562 | return -EINVAL; | |
11563 | ||
11564 | /* No rx interrupts will be generated if both are zero */ | |
11565 | if ((ec->rx_coalesce_usecs == 0) && | |
11566 | (ec->rx_max_coalesced_frames == 0)) | |
11567 | return -EINVAL; | |
11568 | ||
11569 | /* No tx interrupts will be generated if both are zero */ | |
11570 | if ((ec->tx_coalesce_usecs == 0) && | |
11571 | (ec->tx_max_coalesced_frames == 0)) | |
11572 | return -EINVAL; | |
11573 | ||
11574 | /* Only copy relevant parameters, ignore all others. */ | |
11575 | tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs; | |
11576 | tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs; | |
11577 | tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames; | |
11578 | tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames; | |
11579 | tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq; | |
11580 | tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq; | |
11581 | tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq; | |
11582 | tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq; | |
11583 | tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs; | |
11584 | ||
11585 | if (netif_running(dev)) { | |
11586 | tg3_full_lock(tp, 0); | |
11587 | __tg3_set_coalesce(tp, &tp->coal); | |
11588 | tg3_full_unlock(tp); | |
11589 | } | |
11590 | return 0; | |
11591 | } | |
11592 | ||
11593 | static const struct ethtool_ops tg3_ethtool_ops = { | |
11594 | .get_settings = tg3_get_settings, | |
11595 | .set_settings = tg3_set_settings, | |
11596 | .get_drvinfo = tg3_get_drvinfo, | |
11597 | .get_regs_len = tg3_get_regs_len, | |
11598 | .get_regs = tg3_get_regs, | |
11599 | .get_wol = tg3_get_wol, | |
11600 | .set_wol = tg3_set_wol, | |
11601 | .get_msglevel = tg3_get_msglevel, | |
11602 | .set_msglevel = tg3_set_msglevel, | |
11603 | .nway_reset = tg3_nway_reset, | |
11604 | .get_link = ethtool_op_get_link, | |
11605 | .get_eeprom_len = tg3_get_eeprom_len, | |
11606 | .get_eeprom = tg3_get_eeprom, | |
11607 | .set_eeprom = tg3_set_eeprom, | |
11608 | .get_ringparam = tg3_get_ringparam, | |
11609 | .set_ringparam = tg3_set_ringparam, | |
11610 | .get_pauseparam = tg3_get_pauseparam, | |
11611 | .set_pauseparam = tg3_set_pauseparam, | |
11612 | .self_test = tg3_self_test, | |
11613 | .get_strings = tg3_get_strings, | |
11614 | .set_phys_id = tg3_set_phys_id, | |
11615 | .get_ethtool_stats = tg3_get_ethtool_stats, | |
11616 | .get_coalesce = tg3_get_coalesce, | |
11617 | .set_coalesce = tg3_set_coalesce, | |
11618 | .get_sset_count = tg3_get_sset_count, | |
11619 | }; | |
11620 | ||
11621 | static void __devinit tg3_get_eeprom_size(struct tg3 *tp) | |
11622 | { | |
11623 | u32 cursize, val, magic; | |
11624 | ||
11625 | tp->nvram_size = EEPROM_CHIP_SIZE; | |
11626 | ||
11627 | if (tg3_nvram_read(tp, 0, &magic) != 0) | |
11628 | return; | |
11629 | ||
11630 | if ((magic != TG3_EEPROM_MAGIC) && | |
11631 | ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) && | |
11632 | ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW)) | |
11633 | return; | |
11634 | ||
11635 | /* | |
11636 | * Size the chip by reading offsets at increasing powers of two. | |
11637 | * When we encounter our validation signature, we know the addressing | |
11638 | * has wrapped around, and thus have our chip size. | |
11639 | */ | |
11640 | cursize = 0x10; | |
11641 | ||
11642 | while (cursize < tp->nvram_size) { | |
11643 | if (tg3_nvram_read(tp, cursize, &val) != 0) | |
11644 | return; | |
11645 | ||
11646 | if (val == magic) | |
11647 | break; | |
11648 | ||
11649 | cursize <<= 1; | |
11650 | } | |
11651 | ||
11652 | tp->nvram_size = cursize; | |
11653 | } | |
11654 | ||
11655 | static void __devinit tg3_get_nvram_size(struct tg3 *tp) | |
11656 | { | |
11657 | u32 val; | |
11658 | ||
11659 | if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0) | |
11660 | return; | |
11661 | ||
11662 | /* Selfboot format */ | |
11663 | if (val != TG3_EEPROM_MAGIC) { | |
11664 | tg3_get_eeprom_size(tp); | |
11665 | return; | |
11666 | } | |
11667 | ||
11668 | if (tg3_nvram_read(tp, 0xf0, &val) == 0) { | |
11669 | if (val != 0) { | |
11670 | /* This is confusing. We want to operate on the | |
11671 | * 16-bit value at offset 0xf2. The tg3_nvram_read() | |
11672 | * call will read from NVRAM and byteswap the data | |
11673 | * according to the byteswapping settings for all | |
11674 | * other register accesses. This ensures the data we | |
11675 | * want will always reside in the lower 16-bits. | |
11676 | * However, the data in NVRAM is in LE format, which | |
11677 | * means the data from the NVRAM read will always be | |
11678 | * opposite the endianness of the CPU. The 16-bit | |
11679 | * byteswap then brings the data to CPU endianness. | |
11680 | */ | |
11681 | tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024; | |
11682 | return; | |
11683 | } | |
11684 | } | |
11685 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
11686 | } | |
11687 | ||
11688 | static void __devinit tg3_get_nvram_info(struct tg3 *tp) | |
11689 | { | |
11690 | u32 nvcfg1; | |
11691 | ||
11692 | nvcfg1 = tr32(NVRAM_CFG1); | |
11693 | if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) { | |
11694 | tg3_flag_set(tp, FLASH); | |
11695 | } else { | |
11696 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
11697 | tw32(NVRAM_CFG1, nvcfg1); | |
11698 | } | |
11699 | ||
11700 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || | |
11701 | tg3_flag(tp, 5780_CLASS)) { | |
11702 | switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) { | |
11703 | case FLASH_VENDOR_ATMEL_FLASH_BUFFERED: | |
11704 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11705 | tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; | |
11706 | tg3_flag_set(tp, NVRAM_BUFFERED); | |
11707 | break; | |
11708 | case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED: | |
11709 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11710 | tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE; | |
11711 | break; | |
11712 | case FLASH_VENDOR_ATMEL_EEPROM: | |
11713 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11714 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
11715 | tg3_flag_set(tp, NVRAM_BUFFERED); | |
11716 | break; | |
11717 | case FLASH_VENDOR_ST: | |
11718 | tp->nvram_jedecnum = JEDEC_ST; | |
11719 | tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE; | |
11720 | tg3_flag_set(tp, NVRAM_BUFFERED); | |
11721 | break; | |
11722 | case FLASH_VENDOR_SAIFUN: | |
11723 | tp->nvram_jedecnum = JEDEC_SAIFUN; | |
11724 | tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE; | |
11725 | break; | |
11726 | case FLASH_VENDOR_SST_SMALL: | |
11727 | case FLASH_VENDOR_SST_LARGE: | |
11728 | tp->nvram_jedecnum = JEDEC_SST; | |
11729 | tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE; | |
11730 | break; | |
11731 | } | |
11732 | } else { | |
11733 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11734 | tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; | |
11735 | tg3_flag_set(tp, NVRAM_BUFFERED); | |
11736 | } | |
11737 | } | |
11738 | ||
11739 | static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1) | |
11740 | { | |
11741 | switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) { | |
11742 | case FLASH_5752PAGE_SIZE_256: | |
11743 | tp->nvram_pagesize = 256; | |
11744 | break; | |
11745 | case FLASH_5752PAGE_SIZE_512: | |
11746 | tp->nvram_pagesize = 512; | |
11747 | break; | |
11748 | case FLASH_5752PAGE_SIZE_1K: | |
11749 | tp->nvram_pagesize = 1024; | |
11750 | break; | |
11751 | case FLASH_5752PAGE_SIZE_2K: | |
11752 | tp->nvram_pagesize = 2048; | |
11753 | break; | |
11754 | case FLASH_5752PAGE_SIZE_4K: | |
11755 | tp->nvram_pagesize = 4096; | |
11756 | break; | |
11757 | case FLASH_5752PAGE_SIZE_264: | |
11758 | tp->nvram_pagesize = 264; | |
11759 | break; | |
11760 | case FLASH_5752PAGE_SIZE_528: | |
11761 | tp->nvram_pagesize = 528; | |
11762 | break; | |
11763 | } | |
11764 | } | |
11765 | ||
11766 | static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp) | |
11767 | { | |
11768 | u32 nvcfg1; | |
11769 | ||
11770 | nvcfg1 = tr32(NVRAM_CFG1); | |
11771 | ||
11772 | /* NVRAM protection for TPM */ | |
11773 | if (nvcfg1 & (1 << 27)) | |
11774 | tg3_flag_set(tp, PROTECTED_NVRAM); | |
11775 | ||
11776 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
11777 | case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ: | |
11778 | case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ: | |
11779 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11780 | tg3_flag_set(tp, NVRAM_BUFFERED); | |
11781 | break; | |
11782 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
11783 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11784 | tg3_flag_set(tp, NVRAM_BUFFERED); | |
11785 | tg3_flag_set(tp, FLASH); | |
11786 | break; | |
11787 | case FLASH_5752VENDOR_ST_M45PE10: | |
11788 | case FLASH_5752VENDOR_ST_M45PE20: | |
11789 | case FLASH_5752VENDOR_ST_M45PE40: | |
11790 | tp->nvram_jedecnum = JEDEC_ST; | |
11791 | tg3_flag_set(tp, NVRAM_BUFFERED); | |
11792 | tg3_flag_set(tp, FLASH); | |
11793 | break; | |
11794 | } | |
11795 | ||
11796 | if (tg3_flag(tp, FLASH)) { | |
11797 | tg3_nvram_get_pagesize(tp, nvcfg1); | |
11798 | } else { | |
11799 | /* For eeprom, set pagesize to maximum eeprom size */ | |
11800 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
11801 | ||
11802 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
11803 | tw32(NVRAM_CFG1, nvcfg1); | |
11804 | } | |
11805 | } | |
11806 | ||
11807 | static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp) | |
11808 | { | |
11809 | u32 nvcfg1, protect = 0; | |
11810 | ||
11811 | nvcfg1 = tr32(NVRAM_CFG1); | |
11812 | ||
11813 | /* NVRAM protection for TPM */ | |
11814 | if (nvcfg1 & (1 << 27)) { | |
11815 | tg3_flag_set(tp, PROTECTED_NVRAM); | |
11816 | protect = 1; | |
11817 | } | |
11818 | ||
11819 | nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK; | |
11820 | switch (nvcfg1) { | |
11821 | case FLASH_5755VENDOR_ATMEL_FLASH_1: | |
11822 | case FLASH_5755VENDOR_ATMEL_FLASH_2: | |
11823 | case FLASH_5755VENDOR_ATMEL_FLASH_3: | |
11824 | case FLASH_5755VENDOR_ATMEL_FLASH_5: | |
11825 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11826 | tg3_flag_set(tp, NVRAM_BUFFERED); | |
11827 | tg3_flag_set(tp, FLASH); | |
11828 | tp->nvram_pagesize = 264; | |
11829 | if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 || | |
11830 | nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5) | |
11831 | tp->nvram_size = (protect ? 0x3e200 : | |
11832 | TG3_NVRAM_SIZE_512KB); | |
11833 | else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2) | |
11834 | tp->nvram_size = (protect ? 0x1f200 : | |
11835 | TG3_NVRAM_SIZE_256KB); | |
11836 | else | |
11837 | tp->nvram_size = (protect ? 0x1f200 : | |
11838 | TG3_NVRAM_SIZE_128KB); | |
11839 | break; | |
11840 | case FLASH_5752VENDOR_ST_M45PE10: | |
11841 | case FLASH_5752VENDOR_ST_M45PE20: | |
11842 | case FLASH_5752VENDOR_ST_M45PE40: | |
11843 | tp->nvram_jedecnum = JEDEC_ST; | |
11844 | tg3_flag_set(tp, NVRAM_BUFFERED); | |
11845 | tg3_flag_set(tp, FLASH); | |
11846 | tp->nvram_pagesize = 256; | |
11847 | if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10) | |
11848 | tp->nvram_size = (protect ? | |
11849 | TG3_NVRAM_SIZE_64KB : | |
11850 | TG3_NVRAM_SIZE_128KB); | |
11851 | else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20) | |
11852 | tp->nvram_size = (protect ? | |
11853 | TG3_NVRAM_SIZE_64KB : | |
11854 | TG3_NVRAM_SIZE_256KB); | |
11855 | else | |
11856 | tp->nvram_size = (protect ? | |
11857 | TG3_NVRAM_SIZE_128KB : | |
11858 | TG3_NVRAM_SIZE_512KB); | |
11859 | break; | |
11860 | } | |
11861 | } | |
11862 | ||
11863 | static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp) | |
11864 | { | |
11865 | u32 nvcfg1; | |
11866 | ||
11867 | nvcfg1 = tr32(NVRAM_CFG1); | |
11868 | ||
11869 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
11870 | case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ: | |
11871 | case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ: | |
11872 | case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ: | |
11873 | case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ: | |
11874 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11875 | tg3_flag_set(tp, NVRAM_BUFFERED); | |
11876 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
11877 | ||
11878 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
11879 | tw32(NVRAM_CFG1, nvcfg1); | |
11880 | break; | |
11881 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
11882 | case FLASH_5755VENDOR_ATMEL_FLASH_1: | |
11883 | case FLASH_5755VENDOR_ATMEL_FLASH_2: | |
11884 | case FLASH_5755VENDOR_ATMEL_FLASH_3: | |
11885 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11886 | tg3_flag_set(tp, NVRAM_BUFFERED); | |
11887 | tg3_flag_set(tp, FLASH); | |
11888 | tp->nvram_pagesize = 264; | |
11889 | break; | |
11890 | case FLASH_5752VENDOR_ST_M45PE10: | |
11891 | case FLASH_5752VENDOR_ST_M45PE20: | |
11892 | case FLASH_5752VENDOR_ST_M45PE40: | |
11893 | tp->nvram_jedecnum = JEDEC_ST; | |
11894 | tg3_flag_set(tp, NVRAM_BUFFERED); | |
11895 | tg3_flag_set(tp, FLASH); | |
11896 | tp->nvram_pagesize = 256; | |
11897 | break; | |
11898 | } | |
11899 | } | |
11900 | ||
11901 | static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp) | |
11902 | { | |
11903 | u32 nvcfg1, protect = 0; | |
11904 | ||
11905 | nvcfg1 = tr32(NVRAM_CFG1); | |
11906 | ||
11907 | /* NVRAM protection for TPM */ | |
11908 | if (nvcfg1 & (1 << 27)) { | |
11909 | tg3_flag_set(tp, PROTECTED_NVRAM); | |
11910 | protect = 1; | |
11911 | } | |
11912 | ||
11913 | nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK; | |
11914 | switch (nvcfg1) { | |
11915 | case FLASH_5761VENDOR_ATMEL_ADB021D: | |
11916 | case FLASH_5761VENDOR_ATMEL_ADB041D: | |
11917 | case FLASH_5761VENDOR_ATMEL_ADB081D: | |
11918 | case FLASH_5761VENDOR_ATMEL_ADB161D: | |
11919 | case FLASH_5761VENDOR_ATMEL_MDB021D: | |
11920 | case FLASH_5761VENDOR_ATMEL_MDB041D: | |
11921 | case FLASH_5761VENDOR_ATMEL_MDB081D: | |
11922 | case FLASH_5761VENDOR_ATMEL_MDB161D: | |
11923 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11924 | tg3_flag_set(tp, NVRAM_BUFFERED); | |
11925 | tg3_flag_set(tp, FLASH); | |
11926 | tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); | |
11927 | tp->nvram_pagesize = 256; | |
11928 | break; | |
11929 | case FLASH_5761VENDOR_ST_A_M45PE20: | |
11930 | case FLASH_5761VENDOR_ST_A_M45PE40: | |
11931 | case FLASH_5761VENDOR_ST_A_M45PE80: | |
11932 | case FLASH_5761VENDOR_ST_A_M45PE16: | |
11933 | case FLASH_5761VENDOR_ST_M_M45PE20: | |
11934 | case FLASH_5761VENDOR_ST_M_M45PE40: | |
11935 | case FLASH_5761VENDOR_ST_M_M45PE80: | |
11936 | case FLASH_5761VENDOR_ST_M_M45PE16: | |
11937 | tp->nvram_jedecnum = JEDEC_ST; | |
11938 | tg3_flag_set(tp, NVRAM_BUFFERED); | |
11939 | tg3_flag_set(tp, FLASH); | |
11940 | tp->nvram_pagesize = 256; | |
11941 | break; | |
11942 | } | |
11943 | ||
11944 | if (protect) { | |
11945 | tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT); | |
11946 | } else { | |
11947 | switch (nvcfg1) { | |
11948 | case FLASH_5761VENDOR_ATMEL_ADB161D: | |
11949 | case FLASH_5761VENDOR_ATMEL_MDB161D: | |
11950 | case FLASH_5761VENDOR_ST_A_M45PE16: | |
11951 | case FLASH_5761VENDOR_ST_M_M45PE16: | |
11952 | tp->nvram_size = TG3_NVRAM_SIZE_2MB; | |
11953 | break; | |
11954 | case FLASH_5761VENDOR_ATMEL_ADB081D: | |
11955 | case FLASH_5761VENDOR_ATMEL_MDB081D: | |
11956 | case FLASH_5761VENDOR_ST_A_M45PE80: | |
11957 | case FLASH_5761VENDOR_ST_M_M45PE80: | |
11958 | tp->nvram_size = TG3_NVRAM_SIZE_1MB; | |
11959 | break; | |
11960 | case FLASH_5761VENDOR_ATMEL_ADB041D: | |
11961 | case FLASH_5761VENDOR_ATMEL_MDB041D: | |
11962 | case FLASH_5761VENDOR_ST_A_M45PE40: | |
11963 | case FLASH_5761VENDOR_ST_M_M45PE40: | |
11964 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
11965 | break; | |
11966 | case FLASH_5761VENDOR_ATMEL_ADB021D: | |
11967 | case FLASH_5761VENDOR_ATMEL_MDB021D: | |
11968 | case FLASH_5761VENDOR_ST_A_M45PE20: | |
11969 | case FLASH_5761VENDOR_ST_M_M45PE20: | |
11970 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
11971 | break; | |
11972 | } | |
11973 | } | |
11974 | } | |
11975 | ||
11976 | static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp) | |
11977 | { | |
11978 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11979 | tg3_flag_set(tp, NVRAM_BUFFERED); | |
11980 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
11981 | } | |
11982 | ||
11983 | static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp) | |
11984 | { | |
11985 | u32 nvcfg1; | |
11986 | ||
11987 | nvcfg1 = tr32(NVRAM_CFG1); | |
11988 | ||
11989 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
11990 | case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ: | |
11991 | case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ: | |
11992 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11993 | tg3_flag_set(tp, NVRAM_BUFFERED); | |
11994 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
11995 | ||
11996 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
11997 | tw32(NVRAM_CFG1, nvcfg1); | |
11998 | return; | |
11999 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
12000 | case FLASH_57780VENDOR_ATMEL_AT45DB011D: | |
12001 | case FLASH_57780VENDOR_ATMEL_AT45DB011B: | |
12002 | case FLASH_57780VENDOR_ATMEL_AT45DB021D: | |
12003 | case FLASH_57780VENDOR_ATMEL_AT45DB021B: | |
12004 | case FLASH_57780VENDOR_ATMEL_AT45DB041D: | |
12005 | case FLASH_57780VENDOR_ATMEL_AT45DB041B: | |
12006 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
12007 | tg3_flag_set(tp, NVRAM_BUFFERED); | |
12008 | tg3_flag_set(tp, FLASH); | |
12009 | ||
12010 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
12011 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
12012 | case FLASH_57780VENDOR_ATMEL_AT45DB011D: | |
12013 | case FLASH_57780VENDOR_ATMEL_AT45DB011B: | |
12014 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
12015 | break; | |
12016 | case FLASH_57780VENDOR_ATMEL_AT45DB021D: | |
12017 | case FLASH_57780VENDOR_ATMEL_AT45DB021B: | |
12018 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
12019 | break; | |
12020 | case FLASH_57780VENDOR_ATMEL_AT45DB041D: | |
12021 | case FLASH_57780VENDOR_ATMEL_AT45DB041B: | |
12022 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
12023 | break; | |
12024 | } | |
12025 | break; | |
12026 | case FLASH_5752VENDOR_ST_M45PE10: | |
12027 | case FLASH_5752VENDOR_ST_M45PE20: | |
12028 | case FLASH_5752VENDOR_ST_M45PE40: | |
12029 | tp->nvram_jedecnum = JEDEC_ST; | |
12030 | tg3_flag_set(tp, NVRAM_BUFFERED); | |
12031 | tg3_flag_set(tp, FLASH); | |
12032 | ||
12033 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
12034 | case FLASH_5752VENDOR_ST_M45PE10: | |
12035 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
12036 | break; | |
12037 | case FLASH_5752VENDOR_ST_M45PE20: | |
12038 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
12039 | break; | |
12040 | case FLASH_5752VENDOR_ST_M45PE40: | |
12041 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
12042 | break; | |
12043 | } | |
12044 | break; | |
12045 | default: | |
12046 | tg3_flag_set(tp, NO_NVRAM); | |
12047 | return; | |
12048 | } | |
12049 | ||
12050 | tg3_nvram_get_pagesize(tp, nvcfg1); | |
12051 | if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) | |
12052 | tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); | |
12053 | } | |
12054 | ||
12055 | ||
12056 | static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp) | |
12057 | { | |
12058 | u32 nvcfg1; | |
12059 | ||
12060 | nvcfg1 = tr32(NVRAM_CFG1); | |
12061 | ||
12062 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
12063 | case FLASH_5717VENDOR_ATMEL_EEPROM: | |
12064 | case FLASH_5717VENDOR_MICRO_EEPROM: | |
12065 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
12066 | tg3_flag_set(tp, NVRAM_BUFFERED); | |
12067 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
12068 | ||
12069 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
12070 | tw32(NVRAM_CFG1, nvcfg1); | |
12071 | return; | |
12072 | case FLASH_5717VENDOR_ATMEL_MDB011D: | |
12073 | case FLASH_5717VENDOR_ATMEL_ADB011B: | |
12074 | case FLASH_5717VENDOR_ATMEL_ADB011D: | |
12075 | case FLASH_5717VENDOR_ATMEL_MDB021D: | |
12076 | case FLASH_5717VENDOR_ATMEL_ADB021B: | |
12077 | case FLASH_5717VENDOR_ATMEL_ADB021D: | |
12078 | case FLASH_5717VENDOR_ATMEL_45USPT: | |
12079 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
12080 | tg3_flag_set(tp, NVRAM_BUFFERED); | |
12081 | tg3_flag_set(tp, FLASH); | |
12082 | ||
12083 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
12084 | case FLASH_5717VENDOR_ATMEL_MDB021D: | |
12085 | /* Detect size with tg3_nvram_get_size() */ | |
12086 | break; | |
12087 | case FLASH_5717VENDOR_ATMEL_ADB021B: | |
12088 | case FLASH_5717VENDOR_ATMEL_ADB021D: | |
12089 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
12090 | break; | |
12091 | default: | |
12092 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
12093 | break; | |
12094 | } | |
12095 | break; | |
12096 | case FLASH_5717VENDOR_ST_M_M25PE10: | |
12097 | case FLASH_5717VENDOR_ST_A_M25PE10: | |
12098 | case FLASH_5717VENDOR_ST_M_M45PE10: | |
12099 | case FLASH_5717VENDOR_ST_A_M45PE10: | |
12100 | case FLASH_5717VENDOR_ST_M_M25PE20: | |
12101 | case FLASH_5717VENDOR_ST_A_M25PE20: | |
12102 | case FLASH_5717VENDOR_ST_M_M45PE20: | |
12103 | case FLASH_5717VENDOR_ST_A_M45PE20: | |
12104 | case FLASH_5717VENDOR_ST_25USPT: | |
12105 | case FLASH_5717VENDOR_ST_45USPT: | |
12106 | tp->nvram_jedecnum = JEDEC_ST; | |
12107 | tg3_flag_set(tp, NVRAM_BUFFERED); | |
12108 | tg3_flag_set(tp, FLASH); | |
12109 | ||
12110 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
12111 | case FLASH_5717VENDOR_ST_M_M25PE20: | |
12112 | case FLASH_5717VENDOR_ST_M_M45PE20: | |
12113 | /* Detect size with tg3_nvram_get_size() */ | |
12114 | break; | |
12115 | case FLASH_5717VENDOR_ST_A_M25PE20: | |
12116 | case FLASH_5717VENDOR_ST_A_M45PE20: | |
12117 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
12118 | break; | |
12119 | default: | |
12120 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
12121 | break; | |
12122 | } | |
12123 | break; | |
12124 | default: | |
12125 | tg3_flag_set(tp, NO_NVRAM); | |
12126 | return; | |
12127 | } | |
12128 | ||
12129 | tg3_nvram_get_pagesize(tp, nvcfg1); | |
12130 | if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) | |
12131 | tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); | |
12132 | } | |
12133 | ||
12134 | static void __devinit tg3_get_5720_nvram_info(struct tg3 *tp) | |
12135 | { | |
12136 | u32 nvcfg1, nvmpinstrp; | |
12137 | ||
12138 | nvcfg1 = tr32(NVRAM_CFG1); | |
12139 | nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK; | |
12140 | ||
12141 | switch (nvmpinstrp) { | |
12142 | case FLASH_5720_EEPROM_HD: | |
12143 | case FLASH_5720_EEPROM_LD: | |
12144 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
12145 | tg3_flag_set(tp, NVRAM_BUFFERED); | |
12146 | ||
12147 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
12148 | tw32(NVRAM_CFG1, nvcfg1); | |
12149 | if (nvmpinstrp == FLASH_5720_EEPROM_HD) | |
12150 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
12151 | else | |
12152 | tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE; | |
12153 | return; | |
12154 | case FLASH_5720VENDOR_M_ATMEL_DB011D: | |
12155 | case FLASH_5720VENDOR_A_ATMEL_DB011B: | |
12156 | case FLASH_5720VENDOR_A_ATMEL_DB011D: | |
12157 | case FLASH_5720VENDOR_M_ATMEL_DB021D: | |
12158 | case FLASH_5720VENDOR_A_ATMEL_DB021B: | |
12159 | case FLASH_5720VENDOR_A_ATMEL_DB021D: | |
12160 | case FLASH_5720VENDOR_M_ATMEL_DB041D: | |
12161 | case FLASH_5720VENDOR_A_ATMEL_DB041B: | |
12162 | case FLASH_5720VENDOR_A_ATMEL_DB041D: | |
12163 | case FLASH_5720VENDOR_M_ATMEL_DB081D: | |
12164 | case FLASH_5720VENDOR_A_ATMEL_DB081D: | |
12165 | case FLASH_5720VENDOR_ATMEL_45USPT: | |
12166 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
12167 | tg3_flag_set(tp, NVRAM_BUFFERED); | |
12168 | tg3_flag_set(tp, FLASH); | |
12169 | ||
12170 | switch (nvmpinstrp) { | |
12171 | case FLASH_5720VENDOR_M_ATMEL_DB021D: | |
12172 | case FLASH_5720VENDOR_A_ATMEL_DB021B: | |
12173 | case FLASH_5720VENDOR_A_ATMEL_DB021D: | |
12174 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
12175 | break; | |
12176 | case FLASH_5720VENDOR_M_ATMEL_DB041D: | |
12177 | case FLASH_5720VENDOR_A_ATMEL_DB041B: | |
12178 | case FLASH_5720VENDOR_A_ATMEL_DB041D: | |
12179 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
12180 | break; | |
12181 | case FLASH_5720VENDOR_M_ATMEL_DB081D: | |
12182 | case FLASH_5720VENDOR_A_ATMEL_DB081D: | |
12183 | tp->nvram_size = TG3_NVRAM_SIZE_1MB; | |
12184 | break; | |
12185 | default: | |
12186 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
12187 | break; | |
12188 | } | |
12189 | break; | |
12190 | case FLASH_5720VENDOR_M_ST_M25PE10: | |
12191 | case FLASH_5720VENDOR_M_ST_M45PE10: | |
12192 | case FLASH_5720VENDOR_A_ST_M25PE10: | |
12193 | case FLASH_5720VENDOR_A_ST_M45PE10: | |
12194 | case FLASH_5720VENDOR_M_ST_M25PE20: | |
12195 | case FLASH_5720VENDOR_M_ST_M45PE20: | |
12196 | case FLASH_5720VENDOR_A_ST_M25PE20: | |
12197 | case FLASH_5720VENDOR_A_ST_M45PE20: | |
12198 | case FLASH_5720VENDOR_M_ST_M25PE40: | |
12199 | case FLASH_5720VENDOR_M_ST_M45PE40: | |
12200 | case FLASH_5720VENDOR_A_ST_M25PE40: | |
12201 | case FLASH_5720VENDOR_A_ST_M45PE40: | |
12202 | case FLASH_5720VENDOR_M_ST_M25PE80: | |
12203 | case FLASH_5720VENDOR_M_ST_M45PE80: | |
12204 | case FLASH_5720VENDOR_A_ST_M25PE80: | |
12205 | case FLASH_5720VENDOR_A_ST_M45PE80: | |
12206 | case FLASH_5720VENDOR_ST_25USPT: | |
12207 | case FLASH_5720VENDOR_ST_45USPT: | |
12208 | tp->nvram_jedecnum = JEDEC_ST; | |
12209 | tg3_flag_set(tp, NVRAM_BUFFERED); | |
12210 | tg3_flag_set(tp, FLASH); | |
12211 | ||
12212 | switch (nvmpinstrp) { | |
12213 | case FLASH_5720VENDOR_M_ST_M25PE20: | |
12214 | case FLASH_5720VENDOR_M_ST_M45PE20: | |
12215 | case FLASH_5720VENDOR_A_ST_M25PE20: | |
12216 | case FLASH_5720VENDOR_A_ST_M45PE20: | |
12217 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
12218 | break; | |
12219 | case FLASH_5720VENDOR_M_ST_M25PE40: | |
12220 | case FLASH_5720VENDOR_M_ST_M45PE40: | |
12221 | case FLASH_5720VENDOR_A_ST_M25PE40: | |
12222 | case FLASH_5720VENDOR_A_ST_M45PE40: | |
12223 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
12224 | break; | |
12225 | case FLASH_5720VENDOR_M_ST_M25PE80: | |
12226 | case FLASH_5720VENDOR_M_ST_M45PE80: | |
12227 | case FLASH_5720VENDOR_A_ST_M25PE80: | |
12228 | case FLASH_5720VENDOR_A_ST_M45PE80: | |
12229 | tp->nvram_size = TG3_NVRAM_SIZE_1MB; | |
12230 | break; | |
12231 | default: | |
12232 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
12233 | break; | |
12234 | } | |
12235 | break; | |
12236 | default: | |
12237 | tg3_flag_set(tp, NO_NVRAM); | |
12238 | return; | |
12239 | } | |
12240 | ||
12241 | tg3_nvram_get_pagesize(tp, nvcfg1); | |
12242 | if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) | |
12243 | tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); | |
12244 | } | |
12245 | ||
12246 | /* Chips other than 5700/5701 use the NVRAM for fetching info. */ | |
12247 | static void __devinit tg3_nvram_init(struct tg3 *tp) | |
12248 | { | |
12249 | tw32_f(GRC_EEPROM_ADDR, | |
12250 | (EEPROM_ADDR_FSM_RESET | | |
12251 | (EEPROM_DEFAULT_CLOCK_PERIOD << | |
12252 | EEPROM_ADDR_CLKPERD_SHIFT))); | |
12253 | ||
12254 | msleep(1); | |
12255 | ||
12256 | /* Enable seeprom accesses. */ | |
12257 | tw32_f(GRC_LOCAL_CTRL, | |
12258 | tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM); | |
12259 | udelay(100); | |
12260 | ||
12261 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | |
12262 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) { | |
12263 | tg3_flag_set(tp, NVRAM); | |
12264 | ||
12265 | if (tg3_nvram_lock(tp)) { | |
12266 | netdev_warn(tp->dev, | |
12267 | "Cannot get nvram lock, %s failed\n", | |
12268 | __func__); | |
12269 | return; | |
12270 | } | |
12271 | tg3_enable_nvram_access(tp); | |
12272 | ||
12273 | tp->nvram_size = 0; | |
12274 | ||
12275 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) | |
12276 | tg3_get_5752_nvram_info(tp); | |
12277 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) | |
12278 | tg3_get_5755_nvram_info(tp); | |
12279 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || | |
12280 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || | |
12281 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | |
12282 | tg3_get_5787_nvram_info(tp); | |
12283 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) | |
12284 | tg3_get_5761_nvram_info(tp); | |
12285 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
12286 | tg3_get_5906_nvram_info(tp); | |
12287 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || | |
12288 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
12289 | tg3_get_57780_nvram_info(tp); | |
12290 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | |
12291 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) | |
12292 | tg3_get_5717_nvram_info(tp); | |
12293 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) | |
12294 | tg3_get_5720_nvram_info(tp); | |
12295 | else | |
12296 | tg3_get_nvram_info(tp); | |
12297 | ||
12298 | if (tp->nvram_size == 0) | |
12299 | tg3_get_nvram_size(tp); | |
12300 | ||
12301 | tg3_disable_nvram_access(tp); | |
12302 | tg3_nvram_unlock(tp); | |
12303 | ||
12304 | } else { | |
12305 | tg3_flag_clear(tp, NVRAM); | |
12306 | tg3_flag_clear(tp, NVRAM_BUFFERED); | |
12307 | ||
12308 | tg3_get_eeprom_size(tp); | |
12309 | } | |
12310 | } | |
12311 | ||
12312 | static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp, | |
12313 | u32 offset, u32 len, u8 *buf) | |
12314 | { | |
12315 | int i, j, rc = 0; | |
12316 | u32 val; | |
12317 | ||
12318 | for (i = 0; i < len; i += 4) { | |
12319 | u32 addr; | |
12320 | __be32 data; | |
12321 | ||
12322 | addr = offset + i; | |
12323 | ||
12324 | memcpy(&data, buf + i, 4); | |
12325 | ||
12326 | /* | |
12327 | * The SEEPROM interface expects the data to always be opposite | |
12328 | * the native endian format. We accomplish this by reversing | |
12329 | * all the operations that would have been performed on the | |
12330 | * data from a call to tg3_nvram_read_be32(). | |
12331 | */ | |
12332 | tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data))); | |
12333 | ||
12334 | val = tr32(GRC_EEPROM_ADDR); | |
12335 | tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE); | |
12336 | ||
12337 | val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK | | |
12338 | EEPROM_ADDR_READ); | |
12339 | tw32(GRC_EEPROM_ADDR, val | | |
12340 | (0 << EEPROM_ADDR_DEVID_SHIFT) | | |
12341 | (addr & EEPROM_ADDR_ADDR_MASK) | | |
12342 | EEPROM_ADDR_START | | |
12343 | EEPROM_ADDR_WRITE); | |
12344 | ||
12345 | for (j = 0; j < 1000; j++) { | |
12346 | val = tr32(GRC_EEPROM_ADDR); | |
12347 | ||
12348 | if (val & EEPROM_ADDR_COMPLETE) | |
12349 | break; | |
12350 | msleep(1); | |
12351 | } | |
12352 | if (!(val & EEPROM_ADDR_COMPLETE)) { | |
12353 | rc = -EBUSY; | |
12354 | break; | |
12355 | } | |
12356 | } | |
12357 | ||
12358 | return rc; | |
12359 | } | |
12360 | ||
12361 | /* offset and length are dword aligned */ | |
12362 | static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len, | |
12363 | u8 *buf) | |
12364 | { | |
12365 | int ret = 0; | |
12366 | u32 pagesize = tp->nvram_pagesize; | |
12367 | u32 pagemask = pagesize - 1; | |
12368 | u32 nvram_cmd; | |
12369 | u8 *tmp; | |
12370 | ||
12371 | tmp = kmalloc(pagesize, GFP_KERNEL); | |
12372 | if (tmp == NULL) | |
12373 | return -ENOMEM; | |
12374 | ||
12375 | while (len) { | |
12376 | int j; | |
12377 | u32 phy_addr, page_off, size; | |
12378 | ||
12379 | phy_addr = offset & ~pagemask; | |
12380 | ||
12381 | for (j = 0; j < pagesize; j += 4) { | |
12382 | ret = tg3_nvram_read_be32(tp, phy_addr + j, | |
12383 | (__be32 *) (tmp + j)); | |
12384 | if (ret) | |
12385 | break; | |
12386 | } | |
12387 | if (ret) | |
12388 | break; | |
12389 | ||
12390 | page_off = offset & pagemask; | |
12391 | size = pagesize; | |
12392 | if (len < size) | |
12393 | size = len; | |
12394 | ||
12395 | len -= size; | |
12396 | ||
12397 | memcpy(tmp + page_off, buf, size); | |
12398 | ||
12399 | offset = offset + (pagesize - page_off); | |
12400 | ||
12401 | tg3_enable_nvram_access(tp); | |
12402 | ||
12403 | /* | |
12404 | * Before we can erase the flash page, we need | |
12405 | * to issue a special "write enable" command. | |
12406 | */ | |
12407 | nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE; | |
12408 | ||
12409 | if (tg3_nvram_exec_cmd(tp, nvram_cmd)) | |
12410 | break; | |
12411 | ||
12412 | /* Erase the target page */ | |
12413 | tw32(NVRAM_ADDR, phy_addr); | |
12414 | ||
12415 | nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR | | |
12416 | NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE; | |
12417 | ||
12418 | if (tg3_nvram_exec_cmd(tp, nvram_cmd)) | |
12419 | break; | |
12420 | ||
12421 | /* Issue another write enable to start the write. */ | |
12422 | nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE; | |
12423 | ||
12424 | if (tg3_nvram_exec_cmd(tp, nvram_cmd)) | |
12425 | break; | |
12426 | ||
12427 | for (j = 0; j < pagesize; j += 4) { | |
12428 | __be32 data; | |
12429 | ||
12430 | data = *((__be32 *) (tmp + j)); | |
12431 | ||
12432 | tw32(NVRAM_WRDATA, be32_to_cpu(data)); | |
12433 | ||
12434 | tw32(NVRAM_ADDR, phy_addr + j); | |
12435 | ||
12436 | nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | | |
12437 | NVRAM_CMD_WR; | |
12438 | ||
12439 | if (j == 0) | |
12440 | nvram_cmd |= NVRAM_CMD_FIRST; | |
12441 | else if (j == (pagesize - 4)) | |
12442 | nvram_cmd |= NVRAM_CMD_LAST; | |
12443 | ||
12444 | if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd))) | |
12445 | break; | |
12446 | } | |
12447 | if (ret) | |
12448 | break; | |
12449 | } | |
12450 | ||
12451 | nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE; | |
12452 | tg3_nvram_exec_cmd(tp, nvram_cmd); | |
12453 | ||
12454 | kfree(tmp); | |
12455 | ||
12456 | return ret; | |
12457 | } | |
12458 | ||
12459 | /* offset and length are dword aligned */ | |
12460 | static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len, | |
12461 | u8 *buf) | |
12462 | { | |
12463 | int i, ret = 0; | |
12464 | ||
12465 | for (i = 0; i < len; i += 4, offset += 4) { | |
12466 | u32 page_off, phy_addr, nvram_cmd; | |
12467 | __be32 data; | |
12468 | ||
12469 | memcpy(&data, buf + i, 4); | |
12470 | tw32(NVRAM_WRDATA, be32_to_cpu(data)); | |
12471 | ||
12472 | page_off = offset % tp->nvram_pagesize; | |
12473 | ||
12474 | phy_addr = tg3_nvram_phys_addr(tp, offset); | |
12475 | ||
12476 | tw32(NVRAM_ADDR, phy_addr); | |
12477 | ||
12478 | nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR; | |
12479 | ||
12480 | if (page_off == 0 || i == 0) | |
12481 | nvram_cmd |= NVRAM_CMD_FIRST; | |
12482 | if (page_off == (tp->nvram_pagesize - 4)) | |
12483 | nvram_cmd |= NVRAM_CMD_LAST; | |
12484 | ||
12485 | if (i == (len - 4)) | |
12486 | nvram_cmd |= NVRAM_CMD_LAST; | |
12487 | ||
12488 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 && | |
12489 | !tg3_flag(tp, 5755_PLUS) && | |
12490 | (tp->nvram_jedecnum == JEDEC_ST) && | |
12491 | (nvram_cmd & NVRAM_CMD_FIRST)) { | |
12492 | ||
12493 | if ((ret = tg3_nvram_exec_cmd(tp, | |
12494 | NVRAM_CMD_WREN | NVRAM_CMD_GO | | |
12495 | NVRAM_CMD_DONE))) | |
12496 | ||
12497 | break; | |
12498 | } | |
12499 | if (!tg3_flag(tp, FLASH)) { | |
12500 | /* We always do complete word writes to eeprom. */ | |
12501 | nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST); | |
12502 | } | |
12503 | ||
12504 | if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd))) | |
12505 | break; | |
12506 | } | |
12507 | return ret; | |
12508 | } | |
12509 | ||
12510 | /* offset and length are dword aligned */ | |
12511 | static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf) | |
12512 | { | |
12513 | int ret; | |
12514 | ||
12515 | if (tg3_flag(tp, EEPROM_WRITE_PROT)) { | |
12516 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl & | |
12517 | ~GRC_LCLCTRL_GPIO_OUTPUT1); | |
12518 | udelay(40); | |
12519 | } | |
12520 | ||
12521 | if (!tg3_flag(tp, NVRAM)) { | |
12522 | ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf); | |
12523 | } else { | |
12524 | u32 grc_mode; | |
12525 | ||
12526 | ret = tg3_nvram_lock(tp); | |
12527 | if (ret) | |
12528 | return ret; | |
12529 | ||
12530 | tg3_enable_nvram_access(tp); | |
12531 | if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) | |
12532 | tw32(NVRAM_WRITE1, 0x406); | |
12533 | ||
12534 | grc_mode = tr32(GRC_MODE); | |
12535 | tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE); | |
12536 | ||
12537 | if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) { | |
12538 | ret = tg3_nvram_write_block_buffered(tp, offset, len, | |
12539 | buf); | |
12540 | } else { | |
12541 | ret = tg3_nvram_write_block_unbuffered(tp, offset, len, | |
12542 | buf); | |
12543 | } | |
12544 | ||
12545 | grc_mode = tr32(GRC_MODE); | |
12546 | tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE); | |
12547 | ||
12548 | tg3_disable_nvram_access(tp); | |
12549 | tg3_nvram_unlock(tp); | |
12550 | } | |
12551 | ||
12552 | if (tg3_flag(tp, EEPROM_WRITE_PROT)) { | |
12553 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); | |
12554 | udelay(40); | |
12555 | } | |
12556 | ||
12557 | return ret; | |
12558 | } | |
12559 | ||
12560 | struct subsys_tbl_ent { | |
12561 | u16 subsys_vendor, subsys_devid; | |
12562 | u32 phy_id; | |
12563 | }; | |
12564 | ||
12565 | static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = { | |
12566 | /* Broadcom boards. */ | |
12567 | { TG3PCI_SUBVENDOR_ID_BROADCOM, | |
12568 | TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 }, | |
12569 | { TG3PCI_SUBVENDOR_ID_BROADCOM, | |
12570 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 }, | |
12571 | { TG3PCI_SUBVENDOR_ID_BROADCOM, | |
12572 | TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 }, | |
12573 | { TG3PCI_SUBVENDOR_ID_BROADCOM, | |
12574 | TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 }, | |
12575 | { TG3PCI_SUBVENDOR_ID_BROADCOM, | |
12576 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 }, | |
12577 | { TG3PCI_SUBVENDOR_ID_BROADCOM, | |
12578 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 }, | |
12579 | { TG3PCI_SUBVENDOR_ID_BROADCOM, | |
12580 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 }, | |
12581 | { TG3PCI_SUBVENDOR_ID_BROADCOM, | |
12582 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 }, | |
12583 | { TG3PCI_SUBVENDOR_ID_BROADCOM, | |
12584 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 }, | |
12585 | { TG3PCI_SUBVENDOR_ID_BROADCOM, | |
12586 | TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 }, | |
12587 | { TG3PCI_SUBVENDOR_ID_BROADCOM, | |
12588 | TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 }, | |
12589 | ||
12590 | /* 3com boards. */ | |
12591 | { TG3PCI_SUBVENDOR_ID_3COM, | |
12592 | TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 }, | |
12593 | { TG3PCI_SUBVENDOR_ID_3COM, | |
12594 | TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 }, | |
12595 | { TG3PCI_SUBVENDOR_ID_3COM, | |
12596 | TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 }, | |
12597 | { TG3PCI_SUBVENDOR_ID_3COM, | |
12598 | TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 }, | |
12599 | { TG3PCI_SUBVENDOR_ID_3COM, | |
12600 | TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 }, | |
12601 | ||
12602 | /* DELL boards. */ | |
12603 | { TG3PCI_SUBVENDOR_ID_DELL, | |
12604 | TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 }, | |
12605 | { TG3PCI_SUBVENDOR_ID_DELL, | |
12606 | TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 }, | |
12607 | { TG3PCI_SUBVENDOR_ID_DELL, | |
12608 | TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 }, | |
12609 | { TG3PCI_SUBVENDOR_ID_DELL, | |
12610 | TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 }, | |
12611 | ||
12612 | /* Compaq boards. */ | |
12613 | { TG3PCI_SUBVENDOR_ID_COMPAQ, | |
12614 | TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 }, | |
12615 | { TG3PCI_SUBVENDOR_ID_COMPAQ, | |
12616 | TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 }, | |
12617 | { TG3PCI_SUBVENDOR_ID_COMPAQ, | |
12618 | TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 }, | |
12619 | { TG3PCI_SUBVENDOR_ID_COMPAQ, | |
12620 | TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 }, | |
12621 | { TG3PCI_SUBVENDOR_ID_COMPAQ, | |
12622 | TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 }, | |
12623 | ||
12624 | /* IBM boards. */ | |
12625 | { TG3PCI_SUBVENDOR_ID_IBM, | |
12626 | TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 } | |
12627 | }; | |
12628 | ||
12629 | static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp) | |
12630 | { | |
12631 | int i; | |
12632 | ||
12633 | for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) { | |
12634 | if ((subsys_id_to_phy_id[i].subsys_vendor == | |
12635 | tp->pdev->subsystem_vendor) && | |
12636 | (subsys_id_to_phy_id[i].subsys_devid == | |
12637 | tp->pdev->subsystem_device)) | |
12638 | return &subsys_id_to_phy_id[i]; | |
12639 | } | |
12640 | return NULL; | |
12641 | } | |
12642 | ||
12643 | static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp) | |
12644 | { | |
12645 | u32 val; | |
12646 | u16 pmcsr; | |
12647 | ||
12648 | /* On some early chips the SRAM cannot be accessed in D3hot state, | |
12649 | * so need make sure we're in D0. | |
12650 | */ | |
12651 | pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr); | |
12652 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; | |
12653 | pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr); | |
12654 | msleep(1); | |
12655 | ||
12656 | /* Make sure register accesses (indirect or otherwise) | |
12657 | * will function correctly. | |
12658 | */ | |
12659 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
12660 | tp->misc_host_ctrl); | |
12661 | ||
12662 | /* The memory arbiter has to be enabled in order for SRAM accesses | |
12663 | * to succeed. Normally on powerup the tg3 chip firmware will make | |
12664 | * sure it is enabled, but other entities such as system netboot | |
12665 | * code might disable it. | |
12666 | */ | |
12667 | val = tr32(MEMARB_MODE); | |
12668 | tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE); | |
12669 | ||
12670 | tp->phy_id = TG3_PHY_ID_INVALID; | |
12671 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; | |
12672 | ||
12673 | /* Assume an onboard device and WOL capable by default. */ | |
12674 | tg3_flag_set(tp, EEPROM_WRITE_PROT); | |
12675 | tg3_flag_set(tp, WOL_CAP); | |
12676 | ||
12677 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | |
12678 | if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) { | |
12679 | tg3_flag_clear(tp, EEPROM_WRITE_PROT); | |
12680 | tg3_flag_set(tp, IS_NIC); | |
12681 | } | |
12682 | val = tr32(VCPU_CFGSHDW); | |
12683 | if (val & VCPU_CFGSHDW_ASPM_DBNC) | |
12684 | tg3_flag_set(tp, ASPM_WORKAROUND); | |
12685 | if ((val & VCPU_CFGSHDW_WOL_ENABLE) && | |
12686 | (val & VCPU_CFGSHDW_WOL_MAGPKT)) { | |
12687 | tg3_flag_set(tp, WOL_ENABLE); | |
12688 | device_set_wakeup_enable(&tp->pdev->dev, true); | |
12689 | } | |
12690 | goto done; | |
12691 | } | |
12692 | ||
12693 | tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); | |
12694 | if (val == NIC_SRAM_DATA_SIG_MAGIC) { | |
12695 | u32 nic_cfg, led_cfg; | |
12696 | u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id; | |
12697 | int eeprom_phy_serdes = 0; | |
12698 | ||
12699 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg); | |
12700 | tp->nic_sram_data_cfg = nic_cfg; | |
12701 | ||
12702 | tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver); | |
12703 | ver >>= NIC_SRAM_DATA_VER_SHIFT; | |
12704 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | |
12705 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 && | |
12706 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703 && | |
12707 | (ver > 0) && (ver < 0x100)) | |
12708 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2); | |
12709 | ||
12710 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | |
12711 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4); | |
12712 | ||
12713 | if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) == | |
12714 | NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER) | |
12715 | eeprom_phy_serdes = 1; | |
12716 | ||
12717 | tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id); | |
12718 | if (nic_phy_id != 0) { | |
12719 | u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK; | |
12720 | u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK; | |
12721 | ||
12722 | eeprom_phy_id = (id1 >> 16) << 10; | |
12723 | eeprom_phy_id |= (id2 & 0xfc00) << 16; | |
12724 | eeprom_phy_id |= (id2 & 0x03ff) << 0; | |
12725 | } else | |
12726 | eeprom_phy_id = 0; | |
12727 | ||
12728 | tp->phy_id = eeprom_phy_id; | |
12729 | if (eeprom_phy_serdes) { | |
12730 | if (!tg3_flag(tp, 5705_PLUS)) | |
12731 | tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; | |
12732 | else | |
12733 | tp->phy_flags |= TG3_PHYFLG_MII_SERDES; | |
12734 | } | |
12735 | ||
12736 | if (tg3_flag(tp, 5750_PLUS)) | |
12737 | led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK | | |
12738 | SHASTA_EXT_LED_MODE_MASK); | |
12739 | else | |
12740 | led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK; | |
12741 | ||
12742 | switch (led_cfg) { | |
12743 | default: | |
12744 | case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1: | |
12745 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; | |
12746 | break; | |
12747 | ||
12748 | case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2: | |
12749 | tp->led_ctrl = LED_CTRL_MODE_PHY_2; | |
12750 | break; | |
12751 | ||
12752 | case NIC_SRAM_DATA_CFG_LED_MODE_MAC: | |
12753 | tp->led_ctrl = LED_CTRL_MODE_MAC; | |
12754 | ||
12755 | /* Default to PHY_1_MODE if 0 (MAC_MODE) is | |
12756 | * read on some older 5700/5701 bootcode. | |
12757 | */ | |
12758 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == | |
12759 | ASIC_REV_5700 || | |
12760 | GET_ASIC_REV(tp->pci_chip_rev_id) == | |
12761 | ASIC_REV_5701) | |
12762 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; | |
12763 | ||
12764 | break; | |
12765 | ||
12766 | case SHASTA_EXT_LED_SHARED: | |
12767 | tp->led_ctrl = LED_CTRL_MODE_SHARED; | |
12768 | if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 && | |
12769 | tp->pci_chip_rev_id != CHIPREV_ID_5750_A1) | |
12770 | tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | | |
12771 | LED_CTRL_MODE_PHY_2); | |
12772 | break; | |
12773 | ||
12774 | case SHASTA_EXT_LED_MAC: | |
12775 | tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC; | |
12776 | break; | |
12777 | ||
12778 | case SHASTA_EXT_LED_COMBO: | |
12779 | tp->led_ctrl = LED_CTRL_MODE_COMBO; | |
12780 | if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) | |
12781 | tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | | |
12782 | LED_CTRL_MODE_PHY_2); | |
12783 | break; | |
12784 | ||
12785 | } | |
12786 | ||
12787 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
12788 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) && | |
12789 | tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL) | |
12790 | tp->led_ctrl = LED_CTRL_MODE_PHY_2; | |
12791 | ||
12792 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) | |
12793 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; | |
12794 | ||
12795 | if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) { | |
12796 | tg3_flag_set(tp, EEPROM_WRITE_PROT); | |
12797 | if ((tp->pdev->subsystem_vendor == | |
12798 | PCI_VENDOR_ID_ARIMA) && | |
12799 | (tp->pdev->subsystem_device == 0x205a || | |
12800 | tp->pdev->subsystem_device == 0x2063)) | |
12801 | tg3_flag_clear(tp, EEPROM_WRITE_PROT); | |
12802 | } else { | |
12803 | tg3_flag_clear(tp, EEPROM_WRITE_PROT); | |
12804 | tg3_flag_set(tp, IS_NIC); | |
12805 | } | |
12806 | ||
12807 | if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) { | |
12808 | tg3_flag_set(tp, ENABLE_ASF); | |
12809 | if (tg3_flag(tp, 5750_PLUS)) | |
12810 | tg3_flag_set(tp, ASF_NEW_HANDSHAKE); | |
12811 | } | |
12812 | ||
12813 | if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) && | |
12814 | tg3_flag(tp, 5750_PLUS)) | |
12815 | tg3_flag_set(tp, ENABLE_APE); | |
12816 | ||
12817 | if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES && | |
12818 | !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)) | |
12819 | tg3_flag_clear(tp, WOL_CAP); | |
12820 | ||
12821 | if (tg3_flag(tp, WOL_CAP) && | |
12822 | (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) { | |
12823 | tg3_flag_set(tp, WOL_ENABLE); | |
12824 | device_set_wakeup_enable(&tp->pdev->dev, true); | |
12825 | } | |
12826 | ||
12827 | if (cfg2 & (1 << 17)) | |
12828 | tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING; | |
12829 | ||
12830 | /* serdes signal pre-emphasis in register 0x590 set by */ | |
12831 | /* bootcode if bit 18 is set */ | |
12832 | if (cfg2 & (1 << 18)) | |
12833 | tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS; | |
12834 | ||
12835 | if ((tg3_flag(tp, 57765_PLUS) || | |
12836 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && | |
12837 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) && | |
12838 | (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN)) | |
12839 | tp->phy_flags |= TG3_PHYFLG_ENABLE_APD; | |
12840 | ||
12841 | if (tg3_flag(tp, PCI_EXPRESS) && | |
12842 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && | |
12843 | !tg3_flag(tp, 57765_PLUS)) { | |
12844 | u32 cfg3; | |
12845 | ||
12846 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3); | |
12847 | if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE) | |
12848 | tg3_flag_set(tp, ASPM_WORKAROUND); | |
12849 | } | |
12850 | ||
12851 | if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE) | |
12852 | tg3_flag_set(tp, RGMII_INBAND_DISABLE); | |
12853 | if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN) | |
12854 | tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN); | |
12855 | if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN) | |
12856 | tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN); | |
12857 | } | |
12858 | done: | |
12859 | if (tg3_flag(tp, WOL_CAP)) | |
12860 | device_set_wakeup_enable(&tp->pdev->dev, | |
12861 | tg3_flag(tp, WOL_ENABLE)); | |
12862 | else | |
12863 | device_set_wakeup_capable(&tp->pdev->dev, false); | |
12864 | } | |
12865 | ||
12866 | static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd) | |
12867 | { | |
12868 | int i; | |
12869 | u32 val; | |
12870 | ||
12871 | tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START); | |
12872 | tw32(OTP_CTRL, cmd); | |
12873 | ||
12874 | /* Wait for up to 1 ms for command to execute. */ | |
12875 | for (i = 0; i < 100; i++) { | |
12876 | val = tr32(OTP_STATUS); | |
12877 | if (val & OTP_STATUS_CMD_DONE) | |
12878 | break; | |
12879 | udelay(10); | |
12880 | } | |
12881 | ||
12882 | return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY; | |
12883 | } | |
12884 | ||
12885 | /* Read the gphy configuration from the OTP region of the chip. The gphy | |
12886 | * configuration is a 32-bit value that straddles the alignment boundary. | |
12887 | * We do two 32-bit reads and then shift and merge the results. | |
12888 | */ | |
12889 | static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp) | |
12890 | { | |
12891 | u32 bhalf_otp, thalf_otp; | |
12892 | ||
12893 | tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC); | |
12894 | ||
12895 | if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT)) | |
12896 | return 0; | |
12897 | ||
12898 | tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1); | |
12899 | ||
12900 | if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ)) | |
12901 | return 0; | |
12902 | ||
12903 | thalf_otp = tr32(OTP_READ_DATA); | |
12904 | ||
12905 | tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2); | |
12906 | ||
12907 | if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ)) | |
12908 | return 0; | |
12909 | ||
12910 | bhalf_otp = tr32(OTP_READ_DATA); | |
12911 | ||
12912 | return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16); | |
12913 | } | |
12914 | ||
12915 | static void __devinit tg3_phy_init_link_config(struct tg3 *tp) | |
12916 | { | |
12917 | u32 adv = ADVERTISED_Autoneg | | |
12918 | ADVERTISED_Pause; | |
12919 | ||
12920 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) | |
12921 | adv |= ADVERTISED_1000baseT_Half | | |
12922 | ADVERTISED_1000baseT_Full; | |
12923 | ||
12924 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) | |
12925 | adv |= ADVERTISED_100baseT_Half | | |
12926 | ADVERTISED_100baseT_Full | | |
12927 | ADVERTISED_10baseT_Half | | |
12928 | ADVERTISED_10baseT_Full | | |
12929 | ADVERTISED_TP; | |
12930 | else | |
12931 | adv |= ADVERTISED_FIBRE; | |
12932 | ||
12933 | tp->link_config.advertising = adv; | |
12934 | tp->link_config.speed = SPEED_INVALID; | |
12935 | tp->link_config.duplex = DUPLEX_INVALID; | |
12936 | tp->link_config.autoneg = AUTONEG_ENABLE; | |
12937 | tp->link_config.active_speed = SPEED_INVALID; | |
12938 | tp->link_config.active_duplex = DUPLEX_INVALID; | |
12939 | tp->link_config.orig_speed = SPEED_INVALID; | |
12940 | tp->link_config.orig_duplex = DUPLEX_INVALID; | |
12941 | tp->link_config.orig_autoneg = AUTONEG_INVALID; | |
12942 | } | |
12943 | ||
12944 | static int __devinit tg3_phy_probe(struct tg3 *tp) | |
12945 | { | |
12946 | u32 hw_phy_id_1, hw_phy_id_2; | |
12947 | u32 hw_phy_id, hw_phy_id_masked; | |
12948 | int err; | |
12949 | ||
12950 | /* flow control autonegotiation is default behavior */ | |
12951 | tg3_flag_set(tp, PAUSE_AUTONEG); | |
12952 | tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; | |
12953 | ||
12954 | if (tg3_flag(tp, USE_PHYLIB)) | |
12955 | return tg3_phy_init(tp); | |
12956 | ||
12957 | /* Reading the PHY ID register can conflict with ASF | |
12958 | * firmware access to the PHY hardware. | |
12959 | */ | |
12960 | err = 0; | |
12961 | if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) { | |
12962 | hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID; | |
12963 | } else { | |
12964 | /* Now read the physical PHY_ID from the chip and verify | |
12965 | * that it is sane. If it doesn't look good, we fall back | |
12966 | * to either the hard-coded table based PHY_ID and failing | |
12967 | * that the value found in the eeprom area. | |
12968 | */ | |
12969 | err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1); | |
12970 | err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2); | |
12971 | ||
12972 | hw_phy_id = (hw_phy_id_1 & 0xffff) << 10; | |
12973 | hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16; | |
12974 | hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0; | |
12975 | ||
12976 | hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK; | |
12977 | } | |
12978 | ||
12979 | if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) { | |
12980 | tp->phy_id = hw_phy_id; | |
12981 | if (hw_phy_id_masked == TG3_PHY_ID_BCM8002) | |
12982 | tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; | |
12983 | else | |
12984 | tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES; | |
12985 | } else { | |
12986 | if (tp->phy_id != TG3_PHY_ID_INVALID) { | |
12987 | /* Do nothing, phy ID already set up in | |
12988 | * tg3_get_eeprom_hw_cfg(). | |
12989 | */ | |
12990 | } else { | |
12991 | struct subsys_tbl_ent *p; | |
12992 | ||
12993 | /* No eeprom signature? Try the hardcoded | |
12994 | * subsys device table. | |
12995 | */ | |
12996 | p = tg3_lookup_by_subsys(tp); | |
12997 | if (!p) | |
12998 | return -ENODEV; | |
12999 | ||
13000 | tp->phy_id = p->phy_id; | |
13001 | if (!tp->phy_id || | |
13002 | tp->phy_id == TG3_PHY_ID_BCM8002) | |
13003 | tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; | |
13004 | } | |
13005 | } | |
13006 | ||
13007 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && | |
13008 | ((tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 && | |
13009 | tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) || | |
13010 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 && | |
13011 | tp->pci_chip_rev_id != CHIPREV_ID_57765_A0))) | |
13012 | tp->phy_flags |= TG3_PHYFLG_EEE_CAP; | |
13013 | ||
13014 | tg3_phy_init_link_config(tp); | |
13015 | ||
13016 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && | |
13017 | !tg3_flag(tp, ENABLE_APE) && | |
13018 | !tg3_flag(tp, ENABLE_ASF)) { | |
13019 | u32 bmsr, mask; | |
13020 | ||
13021 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
13022 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
13023 | (bmsr & BMSR_LSTATUS)) | |
13024 | goto skip_phy_reset; | |
13025 | ||
13026 | err = tg3_phy_reset(tp); | |
13027 | if (err) | |
13028 | return err; | |
13029 | ||
13030 | tg3_phy_set_wirespeed(tp); | |
13031 | ||
13032 | mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | | |
13033 | ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | | |
13034 | ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full); | |
13035 | if (!tg3_copper_is_advertising_all(tp, mask)) { | |
13036 | tg3_phy_autoneg_cfg(tp, tp->link_config.advertising, | |
13037 | tp->link_config.flowctrl); | |
13038 | ||
13039 | tg3_writephy(tp, MII_BMCR, | |
13040 | BMCR_ANENABLE | BMCR_ANRESTART); | |
13041 | } | |
13042 | } | |
13043 | ||
13044 | skip_phy_reset: | |
13045 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { | |
13046 | err = tg3_init_5401phy_dsp(tp); | |
13047 | if (err) | |
13048 | return err; | |
13049 | ||
13050 | err = tg3_init_5401phy_dsp(tp); | |
13051 | } | |
13052 | ||
13053 | return err; | |
13054 | } | |
13055 | ||
13056 | static void __devinit tg3_read_vpd(struct tg3 *tp) | |
13057 | { | |
13058 | u8 *vpd_data; | |
13059 | unsigned int block_end, rosize, len; | |
13060 | int j, i = 0; | |
13061 | ||
13062 | vpd_data = (u8 *)tg3_vpd_readblock(tp); | |
13063 | if (!vpd_data) | |
13064 | goto out_no_vpd; | |
13065 | ||
13066 | i = pci_vpd_find_tag(vpd_data, 0, TG3_NVM_VPD_LEN, | |
13067 | PCI_VPD_LRDT_RO_DATA); | |
13068 | if (i < 0) | |
13069 | goto out_not_found; | |
13070 | ||
13071 | rosize = pci_vpd_lrdt_size(&vpd_data[i]); | |
13072 | block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize; | |
13073 | i += PCI_VPD_LRDT_TAG_SIZE; | |
13074 | ||
13075 | if (block_end > TG3_NVM_VPD_LEN) | |
13076 | goto out_not_found; | |
13077 | ||
13078 | j = pci_vpd_find_info_keyword(vpd_data, i, rosize, | |
13079 | PCI_VPD_RO_KEYWORD_MFR_ID); | |
13080 | if (j > 0) { | |
13081 | len = pci_vpd_info_field_size(&vpd_data[j]); | |
13082 | ||
13083 | j += PCI_VPD_INFO_FLD_HDR_SIZE; | |
13084 | if (j + len > block_end || len != 4 || | |
13085 | memcmp(&vpd_data[j], "1028", 4)) | |
13086 | goto partno; | |
13087 | ||
13088 | j = pci_vpd_find_info_keyword(vpd_data, i, rosize, | |
13089 | PCI_VPD_RO_KEYWORD_VENDOR0); | |
13090 | if (j < 0) | |
13091 | goto partno; | |
13092 | ||
13093 | len = pci_vpd_info_field_size(&vpd_data[j]); | |
13094 | ||
13095 | j += PCI_VPD_INFO_FLD_HDR_SIZE; | |
13096 | if (j + len > block_end) | |
13097 | goto partno; | |
13098 | ||
13099 | memcpy(tp->fw_ver, &vpd_data[j], len); | |
13100 | strncat(tp->fw_ver, " bc ", TG3_NVM_VPD_LEN - len - 1); | |
13101 | } | |
13102 | ||
13103 | partno: | |
13104 | i = pci_vpd_find_info_keyword(vpd_data, i, rosize, | |
13105 | PCI_VPD_RO_KEYWORD_PARTNO); | |
13106 | if (i < 0) | |
13107 | goto out_not_found; | |
13108 | ||
13109 | len = pci_vpd_info_field_size(&vpd_data[i]); | |
13110 | ||
13111 | i += PCI_VPD_INFO_FLD_HDR_SIZE; | |
13112 | if (len > TG3_BPN_SIZE || | |
13113 | (len + i) > TG3_NVM_VPD_LEN) | |
13114 | goto out_not_found; | |
13115 | ||
13116 | memcpy(tp->board_part_number, &vpd_data[i], len); | |
13117 | ||
13118 | out_not_found: | |
13119 | kfree(vpd_data); | |
13120 | if (tp->board_part_number[0]) | |
13121 | return; | |
13122 | ||
13123 | out_no_vpd: | |
13124 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) { | |
13125 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717) | |
13126 | strcpy(tp->board_part_number, "BCM5717"); | |
13127 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718) | |
13128 | strcpy(tp->board_part_number, "BCM5718"); | |
13129 | else | |
13130 | goto nomatch; | |
13131 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { | |
13132 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780) | |
13133 | strcpy(tp->board_part_number, "BCM57780"); | |
13134 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760) | |
13135 | strcpy(tp->board_part_number, "BCM57760"); | |
13136 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790) | |
13137 | strcpy(tp->board_part_number, "BCM57790"); | |
13138 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788) | |
13139 | strcpy(tp->board_part_number, "BCM57788"); | |
13140 | else | |
13141 | goto nomatch; | |
13142 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) { | |
13143 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761) | |
13144 | strcpy(tp->board_part_number, "BCM57761"); | |
13145 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765) | |
13146 | strcpy(tp->board_part_number, "BCM57765"); | |
13147 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781) | |
13148 | strcpy(tp->board_part_number, "BCM57781"); | |
13149 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785) | |
13150 | strcpy(tp->board_part_number, "BCM57785"); | |
13151 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791) | |
13152 | strcpy(tp->board_part_number, "BCM57791"); | |
13153 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795) | |
13154 | strcpy(tp->board_part_number, "BCM57795"); | |
13155 | else | |
13156 | goto nomatch; | |
13157 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | |
13158 | strcpy(tp->board_part_number, "BCM95906"); | |
13159 | } else { | |
13160 | nomatch: | |
13161 | strcpy(tp->board_part_number, "none"); | |
13162 | } | |
13163 | } | |
13164 | ||
13165 | static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset) | |
13166 | { | |
13167 | u32 val; | |
13168 | ||
13169 | if (tg3_nvram_read(tp, offset, &val) || | |
13170 | (val & 0xfc000000) != 0x0c000000 || | |
13171 | tg3_nvram_read(tp, offset + 4, &val) || | |
13172 | val != 0) | |
13173 | return 0; | |
13174 | ||
13175 | return 1; | |
13176 | } | |
13177 | ||
13178 | static void __devinit tg3_read_bc_ver(struct tg3 *tp) | |
13179 | { | |
13180 | u32 val, offset, start, ver_offset; | |
13181 | int i, dst_off; | |
13182 | bool newver = false; | |
13183 | ||
13184 | if (tg3_nvram_read(tp, 0xc, &offset) || | |
13185 | tg3_nvram_read(tp, 0x4, &start)) | |
13186 | return; | |
13187 | ||
13188 | offset = tg3_nvram_logical_addr(tp, offset); | |
13189 | ||
13190 | if (tg3_nvram_read(tp, offset, &val)) | |
13191 | return; | |
13192 | ||
13193 | if ((val & 0xfc000000) == 0x0c000000) { | |
13194 | if (tg3_nvram_read(tp, offset + 4, &val)) | |
13195 | return; | |
13196 | ||
13197 | if (val == 0) | |
13198 | newver = true; | |
13199 | } | |
13200 | ||
13201 | dst_off = strlen(tp->fw_ver); | |
13202 | ||
13203 | if (newver) { | |
13204 | if (TG3_VER_SIZE - dst_off < 16 || | |
13205 | tg3_nvram_read(tp, offset + 8, &ver_offset)) | |
13206 | return; | |
13207 | ||
13208 | offset = offset + ver_offset - start; | |
13209 | for (i = 0; i < 16; i += 4) { | |
13210 | __be32 v; | |
13211 | if (tg3_nvram_read_be32(tp, offset + i, &v)) | |
13212 | return; | |
13213 | ||
13214 | memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v)); | |
13215 | } | |
13216 | } else { | |
13217 | u32 major, minor; | |
13218 | ||
13219 | if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset)) | |
13220 | return; | |
13221 | ||
13222 | major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >> | |
13223 | TG3_NVM_BCVER_MAJSFT; | |
13224 | minor = ver_offset & TG3_NVM_BCVER_MINMSK; | |
13225 | snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off, | |
13226 | "v%d.%02d", major, minor); | |
13227 | } | |
13228 | } | |
13229 | ||
13230 | static void __devinit tg3_read_hwsb_ver(struct tg3 *tp) | |
13231 | { | |
13232 | u32 val, major, minor; | |
13233 | ||
13234 | /* Use native endian representation */ | |
13235 | if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val)) | |
13236 | return; | |
13237 | ||
13238 | major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >> | |
13239 | TG3_NVM_HWSB_CFG1_MAJSFT; | |
13240 | minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >> | |
13241 | TG3_NVM_HWSB_CFG1_MINSFT; | |
13242 | ||
13243 | snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor); | |
13244 | } | |
13245 | ||
13246 | static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val) | |
13247 | { | |
13248 | u32 offset, major, minor, build; | |
13249 | ||
13250 | strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1); | |
13251 | ||
13252 | if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1) | |
13253 | return; | |
13254 | ||
13255 | switch (val & TG3_EEPROM_SB_REVISION_MASK) { | |
13256 | case TG3_EEPROM_SB_REVISION_0: | |
13257 | offset = TG3_EEPROM_SB_F1R0_EDH_OFF; | |
13258 | break; | |
13259 | case TG3_EEPROM_SB_REVISION_2: | |
13260 | offset = TG3_EEPROM_SB_F1R2_EDH_OFF; | |
13261 | break; | |
13262 | case TG3_EEPROM_SB_REVISION_3: | |
13263 | offset = TG3_EEPROM_SB_F1R3_EDH_OFF; | |
13264 | break; | |
13265 | case TG3_EEPROM_SB_REVISION_4: | |
13266 | offset = TG3_EEPROM_SB_F1R4_EDH_OFF; | |
13267 | break; | |
13268 | case TG3_EEPROM_SB_REVISION_5: | |
13269 | offset = TG3_EEPROM_SB_F1R5_EDH_OFF; | |
13270 | break; | |
13271 | case TG3_EEPROM_SB_REVISION_6: | |
13272 | offset = TG3_EEPROM_SB_F1R6_EDH_OFF; | |
13273 | break; | |
13274 | default: | |
13275 | return; | |
13276 | } | |
13277 | ||
13278 | if (tg3_nvram_read(tp, offset, &val)) | |
13279 | return; | |
13280 | ||
13281 | build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >> | |
13282 | TG3_EEPROM_SB_EDH_BLD_SHFT; | |
13283 | major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >> | |
13284 | TG3_EEPROM_SB_EDH_MAJ_SHFT; | |
13285 | minor = val & TG3_EEPROM_SB_EDH_MIN_MASK; | |
13286 | ||
13287 | if (minor > 99 || build > 26) | |
13288 | return; | |
13289 | ||
13290 | offset = strlen(tp->fw_ver); | |
13291 | snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset, | |
13292 | " v%d.%02d", major, minor); | |
13293 | ||
13294 | if (build > 0) { | |
13295 | offset = strlen(tp->fw_ver); | |
13296 | if (offset < TG3_VER_SIZE - 1) | |
13297 | tp->fw_ver[offset] = 'a' + build - 1; | |
13298 | } | |
13299 | } | |
13300 | ||
13301 | static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp) | |
13302 | { | |
13303 | u32 val, offset, start; | |
13304 | int i, vlen; | |
13305 | ||
13306 | for (offset = TG3_NVM_DIR_START; | |
13307 | offset < TG3_NVM_DIR_END; | |
13308 | offset += TG3_NVM_DIRENT_SIZE) { | |
13309 | if (tg3_nvram_read(tp, offset, &val)) | |
13310 | return; | |
13311 | ||
13312 | if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI) | |
13313 | break; | |
13314 | } | |
13315 | ||
13316 | if (offset == TG3_NVM_DIR_END) | |
13317 | return; | |
13318 | ||
13319 | if (!tg3_flag(tp, 5705_PLUS)) | |
13320 | start = 0x08000000; | |
13321 | else if (tg3_nvram_read(tp, offset - 4, &start)) | |
13322 | return; | |
13323 | ||
13324 | if (tg3_nvram_read(tp, offset + 4, &offset) || | |
13325 | !tg3_fw_img_is_valid(tp, offset) || | |
13326 | tg3_nvram_read(tp, offset + 8, &val)) | |
13327 | return; | |
13328 | ||
13329 | offset += val - start; | |
13330 | ||
13331 | vlen = strlen(tp->fw_ver); | |
13332 | ||
13333 | tp->fw_ver[vlen++] = ','; | |
13334 | tp->fw_ver[vlen++] = ' '; | |
13335 | ||
13336 | for (i = 0; i < 4; i++) { | |
13337 | __be32 v; | |
13338 | if (tg3_nvram_read_be32(tp, offset, &v)) | |
13339 | return; | |
13340 | ||
13341 | offset += sizeof(v); | |
13342 | ||
13343 | if (vlen > TG3_VER_SIZE - sizeof(v)) { | |
13344 | memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen); | |
13345 | break; | |
13346 | } | |
13347 | ||
13348 | memcpy(&tp->fw_ver[vlen], &v, sizeof(v)); | |
13349 | vlen += sizeof(v); | |
13350 | } | |
13351 | } | |
13352 | ||
13353 | static void __devinit tg3_read_dash_ver(struct tg3 *tp) | |
13354 | { | |
13355 | int vlen; | |
13356 | u32 apedata; | |
13357 | char *fwtype; | |
13358 | ||
13359 | if (!tg3_flag(tp, ENABLE_APE) || !tg3_flag(tp, ENABLE_ASF)) | |
13360 | return; | |
13361 | ||
13362 | apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG); | |
13363 | if (apedata != APE_SEG_SIG_MAGIC) | |
13364 | return; | |
13365 | ||
13366 | apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); | |
13367 | if (!(apedata & APE_FW_STATUS_READY)) | |
13368 | return; | |
13369 | ||
13370 | apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION); | |
13371 | ||
13372 | if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) { | |
13373 | tg3_flag_set(tp, APE_HAS_NCSI); | |
13374 | fwtype = "NCSI"; | |
13375 | } else { | |
13376 | fwtype = "DASH"; | |
13377 | } | |
13378 | ||
13379 | vlen = strlen(tp->fw_ver); | |
13380 | ||
13381 | snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d", | |
13382 | fwtype, | |
13383 | (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT, | |
13384 | (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT, | |
13385 | (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT, | |
13386 | (apedata & APE_FW_VERSION_BLDMSK)); | |
13387 | } | |
13388 | ||
13389 | static void __devinit tg3_read_fw_ver(struct tg3 *tp) | |
13390 | { | |
13391 | u32 val; | |
13392 | bool vpd_vers = false; | |
13393 | ||
13394 | if (tp->fw_ver[0] != 0) | |
13395 | vpd_vers = true; | |
13396 | ||
13397 | if (tg3_flag(tp, NO_NVRAM)) { | |
13398 | strcat(tp->fw_ver, "sb"); | |
13399 | return; | |
13400 | } | |
13401 | ||
13402 | if (tg3_nvram_read(tp, 0, &val)) | |
13403 | return; | |
13404 | ||
13405 | if (val == TG3_EEPROM_MAGIC) | |
13406 | tg3_read_bc_ver(tp); | |
13407 | else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) | |
13408 | tg3_read_sb_ver(tp, val); | |
13409 | else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW) | |
13410 | tg3_read_hwsb_ver(tp); | |
13411 | else | |
13412 | return; | |
13413 | ||
13414 | if (!tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || vpd_vers) | |
13415 | goto done; | |
13416 | ||
13417 | tg3_read_mgmtfw_ver(tp); | |
13418 | ||
13419 | done: | |
13420 | tp->fw_ver[TG3_VER_SIZE - 1] = 0; | |
13421 | } | |
13422 | ||
13423 | static struct pci_dev * __devinit tg3_find_peer(struct tg3 *); | |
13424 | ||
13425 | static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp) | |
13426 | { | |
13427 | if (tg3_flag(tp, LRG_PROD_RING_CAP)) | |
13428 | return TG3_RX_RET_MAX_SIZE_5717; | |
13429 | else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) | |
13430 | return TG3_RX_RET_MAX_SIZE_5700; | |
13431 | else | |
13432 | return TG3_RX_RET_MAX_SIZE_5705; | |
13433 | } | |
13434 | ||
13435 | static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = { | |
13436 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) }, | |
13437 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) }, | |
13438 | { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) }, | |
13439 | { }, | |
13440 | }; | |
13441 | ||
13442 | static int __devinit tg3_get_invariants(struct tg3 *tp) | |
13443 | { | |
13444 | u32 misc_ctrl_reg; | |
13445 | u32 pci_state_reg, grc_misc_cfg; | |
13446 | u32 val; | |
13447 | u16 pci_cmd; | |
13448 | int err; | |
13449 | ||
13450 | /* Force memory write invalidate off. If we leave it on, | |
13451 | * then on 5700_BX chips we have to enable a workaround. | |
13452 | * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary | |
13453 | * to match the cacheline size. The Broadcom driver have this | |
13454 | * workaround but turns MWI off all the times so never uses | |
13455 | * it. This seems to suggest that the workaround is insufficient. | |
13456 | */ | |
13457 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
13458 | pci_cmd &= ~PCI_COMMAND_INVALIDATE; | |
13459 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
13460 | ||
13461 | /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL | |
13462 | * has the register indirect write enable bit set before | |
13463 | * we try to access any of the MMIO registers. It is also | |
13464 | * critical that the PCI-X hw workaround situation is decided | |
13465 | * before that as well. | |
13466 | */ | |
13467 | pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
13468 | &misc_ctrl_reg); | |
13469 | ||
13470 | tp->pci_chip_rev_id = (misc_ctrl_reg >> | |
13471 | MISC_HOST_CTRL_CHIPREV_SHIFT); | |
13472 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) { | |
13473 | u32 prod_id_asic_rev; | |
13474 | ||
13475 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || | |
13476 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 || | |
13477 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 || | |
13478 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720) | |
13479 | pci_read_config_dword(tp->pdev, | |
13480 | TG3PCI_GEN2_PRODID_ASICREV, | |
13481 | &prod_id_asic_rev); | |
13482 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 || | |
13483 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 || | |
13484 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 || | |
13485 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 || | |
13486 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 || | |
13487 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795) | |
13488 | pci_read_config_dword(tp->pdev, | |
13489 | TG3PCI_GEN15_PRODID_ASICREV, | |
13490 | &prod_id_asic_rev); | |
13491 | else | |
13492 | pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV, | |
13493 | &prod_id_asic_rev); | |
13494 | ||
13495 | tp->pci_chip_rev_id = prod_id_asic_rev; | |
13496 | } | |
13497 | ||
13498 | /* Wrong chip ID in 5752 A0. This code can be removed later | |
13499 | * as A0 is not in production. | |
13500 | */ | |
13501 | if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW) | |
13502 | tp->pci_chip_rev_id = CHIPREV_ID_5752_A0; | |
13503 | ||
13504 | /* If we have 5702/03 A1 or A2 on certain ICH chipsets, | |
13505 | * we need to disable memory and use config. cycles | |
13506 | * only to access all registers. The 5702/03 chips | |
13507 | * can mistakenly decode the special cycles from the | |
13508 | * ICH chipsets as memory write cycles, causing corruption | |
13509 | * of register and memory space. Only certain ICH bridges | |
13510 | * will drive special cycles with non-zero data during the | |
13511 | * address phase which can fall within the 5703's address | |
13512 | * range. This is not an ICH bug as the PCI spec allows | |
13513 | * non-zero address during special cycles. However, only | |
13514 | * these ICH bridges are known to drive non-zero addresses | |
13515 | * during special cycles. | |
13516 | * | |
13517 | * Since special cycles do not cross PCI bridges, we only | |
13518 | * enable this workaround if the 5703 is on the secondary | |
13519 | * bus of these ICH bridges. | |
13520 | */ | |
13521 | if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) || | |
13522 | (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) { | |
13523 | static struct tg3_dev_id { | |
13524 | u32 vendor; | |
13525 | u32 device; | |
13526 | u32 rev; | |
13527 | } ich_chipsets[] = { | |
13528 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8, | |
13529 | PCI_ANY_ID }, | |
13530 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8, | |
13531 | PCI_ANY_ID }, | |
13532 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11, | |
13533 | 0xa }, | |
13534 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6, | |
13535 | PCI_ANY_ID }, | |
13536 | { }, | |
13537 | }; | |
13538 | struct tg3_dev_id *pci_id = &ich_chipsets[0]; | |
13539 | struct pci_dev *bridge = NULL; | |
13540 | ||
13541 | while (pci_id->vendor != 0) { | |
13542 | bridge = pci_get_device(pci_id->vendor, pci_id->device, | |
13543 | bridge); | |
13544 | if (!bridge) { | |
13545 | pci_id++; | |
13546 | continue; | |
13547 | } | |
13548 | if (pci_id->rev != PCI_ANY_ID) { | |
13549 | if (bridge->revision > pci_id->rev) | |
13550 | continue; | |
13551 | } | |
13552 | if (bridge->subordinate && | |
13553 | (bridge->subordinate->number == | |
13554 | tp->pdev->bus->number)) { | |
13555 | tg3_flag_set(tp, ICH_WORKAROUND); | |
13556 | pci_dev_put(bridge); | |
13557 | break; | |
13558 | } | |
13559 | } | |
13560 | } | |
13561 | ||
13562 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
13563 | static struct tg3_dev_id { | |
13564 | u32 vendor; | |
13565 | u32 device; | |
13566 | } bridge_chipsets[] = { | |
13567 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 }, | |
13568 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 }, | |
13569 | { }, | |
13570 | }; | |
13571 | struct tg3_dev_id *pci_id = &bridge_chipsets[0]; | |
13572 | struct pci_dev *bridge = NULL; | |
13573 | ||
13574 | while (pci_id->vendor != 0) { | |
13575 | bridge = pci_get_device(pci_id->vendor, | |
13576 | pci_id->device, | |
13577 | bridge); | |
13578 | if (!bridge) { | |
13579 | pci_id++; | |
13580 | continue; | |
13581 | } | |
13582 | if (bridge->subordinate && | |
13583 | (bridge->subordinate->number <= | |
13584 | tp->pdev->bus->number) && | |
13585 | (bridge->subordinate->subordinate >= | |
13586 | tp->pdev->bus->number)) { | |
13587 | tg3_flag_set(tp, 5701_DMA_BUG); | |
13588 | pci_dev_put(bridge); | |
13589 | break; | |
13590 | } | |
13591 | } | |
13592 | } | |
13593 | ||
13594 | /* The EPB bridge inside 5714, 5715, and 5780 cannot support | |
13595 | * DMA addresses > 40-bit. This bridge may have other additional | |
13596 | * 57xx devices behind it in some 4-port NIC designs for example. | |
13597 | * Any tg3 device found behind the bridge will also need the 40-bit | |
13598 | * DMA workaround. | |
13599 | */ | |
13600 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 || | |
13601 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { | |
13602 | tg3_flag_set(tp, 5780_CLASS); | |
13603 | tg3_flag_set(tp, 40BIT_DMA_BUG); | |
13604 | tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI); | |
13605 | } else { | |
13606 | struct pci_dev *bridge = NULL; | |
13607 | ||
13608 | do { | |
13609 | bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS, | |
13610 | PCI_DEVICE_ID_SERVERWORKS_EPB, | |
13611 | bridge); | |
13612 | if (bridge && bridge->subordinate && | |
13613 | (bridge->subordinate->number <= | |
13614 | tp->pdev->bus->number) && | |
13615 | (bridge->subordinate->subordinate >= | |
13616 | tp->pdev->bus->number)) { | |
13617 | tg3_flag_set(tp, 40BIT_DMA_BUG); | |
13618 | pci_dev_put(bridge); | |
13619 | break; | |
13620 | } | |
13621 | } while (bridge); | |
13622 | } | |
13623 | ||
13624 | /* Initialize misc host control in PCI block. */ | |
13625 | tp->misc_host_ctrl |= (misc_ctrl_reg & | |
13626 | MISC_HOST_CTRL_CHIPREV); | |
13627 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
13628 | tp->misc_host_ctrl); | |
13629 | ||
13630 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
13631 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 || | |
13632 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | |
13633 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) | |
13634 | tp->pdev_peer = tg3_find_peer(tp); | |
13635 | ||
13636 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | |
13637 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | |
13638 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) | |
13639 | tg3_flag_set(tp, 5717_PLUS); | |
13640 | ||
13641 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 || | |
13642 | tg3_flag(tp, 5717_PLUS)) | |
13643 | tg3_flag_set(tp, 57765_PLUS); | |
13644 | ||
13645 | /* Intentionally exclude ASIC_REV_5906 */ | |
13646 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || | |
13647 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || | |
13648 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || | |
13649 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || | |
13650 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || | |
13651 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || | |
13652 | tg3_flag(tp, 57765_PLUS)) | |
13653 | tg3_flag_set(tp, 5755_PLUS); | |
13654 | ||
13655 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || | |
13656 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || | |
13657 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 || | |
13658 | tg3_flag(tp, 5755_PLUS) || | |
13659 | tg3_flag(tp, 5780_CLASS)) | |
13660 | tg3_flag_set(tp, 5750_PLUS); | |
13661 | ||
13662 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 || | |
13663 | tg3_flag(tp, 5750_PLUS)) | |
13664 | tg3_flag_set(tp, 5705_PLUS); | |
13665 | ||
13666 | /* Determine TSO capabilities */ | |
13667 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) | |
13668 | ; /* Do nothing. HW bug. */ | |
13669 | else if (tg3_flag(tp, 57765_PLUS)) | |
13670 | tg3_flag_set(tp, HW_TSO_3); | |
13671 | else if (tg3_flag(tp, 5755_PLUS) || | |
13672 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
13673 | tg3_flag_set(tp, HW_TSO_2); | |
13674 | else if (tg3_flag(tp, 5750_PLUS)) { | |
13675 | tg3_flag_set(tp, HW_TSO_1); | |
13676 | tg3_flag_set(tp, TSO_BUG); | |
13677 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 && | |
13678 | tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2) | |
13679 | tg3_flag_clear(tp, TSO_BUG); | |
13680 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | |
13681 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 && | |
13682 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) { | |
13683 | tg3_flag_set(tp, TSO_BUG); | |
13684 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) | |
13685 | tp->fw_needed = FIRMWARE_TG3TSO5; | |
13686 | else | |
13687 | tp->fw_needed = FIRMWARE_TG3TSO; | |
13688 | } | |
13689 | ||
13690 | /* Selectively allow TSO based on operating conditions */ | |
13691 | if (tg3_flag(tp, HW_TSO_1) || | |
13692 | tg3_flag(tp, HW_TSO_2) || | |
13693 | tg3_flag(tp, HW_TSO_3) || | |
13694 | (tp->fw_needed && !tg3_flag(tp, ENABLE_ASF))) | |
13695 | tg3_flag_set(tp, TSO_CAPABLE); | |
13696 | else { | |
13697 | tg3_flag_clear(tp, TSO_CAPABLE); | |
13698 | tg3_flag_clear(tp, TSO_BUG); | |
13699 | tp->fw_needed = NULL; | |
13700 | } | |
13701 | ||
13702 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) | |
13703 | tp->fw_needed = FIRMWARE_TG3; | |
13704 | ||
13705 | tp->irq_max = 1; | |
13706 | ||
13707 | if (tg3_flag(tp, 5750_PLUS)) { | |
13708 | tg3_flag_set(tp, SUPPORT_MSI); | |
13709 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX || | |
13710 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX || | |
13711 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 && | |
13712 | tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 && | |
13713 | tp->pdev_peer == tp->pdev)) | |
13714 | tg3_flag_clear(tp, SUPPORT_MSI); | |
13715 | ||
13716 | if (tg3_flag(tp, 5755_PLUS) || | |
13717 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | |
13718 | tg3_flag_set(tp, 1SHOT_MSI); | |
13719 | } | |
13720 | ||
13721 | if (tg3_flag(tp, 57765_PLUS)) { | |
13722 | tg3_flag_set(tp, SUPPORT_MSIX); | |
13723 | tp->irq_max = TG3_IRQ_MAX_VECS; | |
13724 | } | |
13725 | } | |
13726 | ||
13727 | if (tg3_flag(tp, 5755_PLUS)) | |
13728 | tg3_flag_set(tp, SHORT_DMA_BUG); | |
13729 | ||
13730 | if (tg3_flag(tp, 5717_PLUS)) | |
13731 | tg3_flag_set(tp, LRG_PROD_RING_CAP); | |
13732 | ||
13733 | if (tg3_flag(tp, 57765_PLUS) && | |
13734 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719) | |
13735 | tg3_flag_set(tp, USE_JUMBO_BDFLAG); | |
13736 | ||
13737 | if (!tg3_flag(tp, 5705_PLUS) || | |
13738 | tg3_flag(tp, 5780_CLASS) || | |
13739 | tg3_flag(tp, USE_JUMBO_BDFLAG)) | |
13740 | tg3_flag_set(tp, JUMBO_CAPABLE); | |
13741 | ||
13742 | pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, | |
13743 | &pci_state_reg); | |
13744 | ||
13745 | tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP); | |
13746 | if (tp->pcie_cap != 0) { | |
13747 | u16 lnkctl; | |
13748 | ||
13749 | tg3_flag_set(tp, PCI_EXPRESS); | |
13750 | ||
13751 | tp->pcie_readrq = 4096; | |
13752 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | |
13753 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) | |
13754 | tp->pcie_readrq = 2048; | |
13755 | ||
13756 | pcie_set_readrq(tp->pdev, tp->pcie_readrq); | |
13757 | ||
13758 | pci_read_config_word(tp->pdev, | |
13759 | tp->pcie_cap + PCI_EXP_LNKCTL, | |
13760 | &lnkctl); | |
13761 | if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) { | |
13762 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == | |
13763 | ASIC_REV_5906) { | |
13764 | tg3_flag_clear(tp, HW_TSO_2); | |
13765 | tg3_flag_clear(tp, TSO_CAPABLE); | |
13766 | } | |
13767 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || | |
13768 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || | |
13769 | tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 || | |
13770 | tp->pci_chip_rev_id == CHIPREV_ID_57780_A1) | |
13771 | tg3_flag_set(tp, CLKREQ_BUG); | |
13772 | } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) { | |
13773 | tg3_flag_set(tp, L1PLLPD_EN); | |
13774 | } | |
13775 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) { | |
13776 | tg3_flag_set(tp, PCI_EXPRESS); | |
13777 | } else if (!tg3_flag(tp, 5705_PLUS) || | |
13778 | tg3_flag(tp, 5780_CLASS)) { | |
13779 | tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX); | |
13780 | if (!tp->pcix_cap) { | |
13781 | dev_err(&tp->pdev->dev, | |
13782 | "Cannot find PCI-X capability, aborting\n"); | |
13783 | return -EIO; | |
13784 | } | |
13785 | ||
13786 | if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE)) | |
13787 | tg3_flag_set(tp, PCIX_MODE); | |
13788 | } | |
13789 | ||
13790 | /* If we have an AMD 762 or VIA K8T800 chipset, write | |
13791 | * reordering to the mailbox registers done by the host | |
13792 | * controller can cause major troubles. We read back from | |
13793 | * every mailbox register write to force the writes to be | |
13794 | * posted to the chip in order. | |
13795 | */ | |
13796 | if (pci_dev_present(tg3_write_reorder_chipsets) && | |
13797 | !tg3_flag(tp, PCI_EXPRESS)) | |
13798 | tg3_flag_set(tp, MBOX_WRITE_REORDER); | |
13799 | ||
13800 | pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, | |
13801 | &tp->pci_cacheline_sz); | |
13802 | pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER, | |
13803 | &tp->pci_lat_timer); | |
13804 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 && | |
13805 | tp->pci_lat_timer < 64) { | |
13806 | tp->pci_lat_timer = 64; | |
13807 | pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, | |
13808 | tp->pci_lat_timer); | |
13809 | } | |
13810 | ||
13811 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) { | |
13812 | /* 5700 BX chips need to have their TX producer index | |
13813 | * mailboxes written twice to workaround a bug. | |
13814 | */ | |
13815 | tg3_flag_set(tp, TXD_MBOX_HWBUG); | |
13816 | ||
13817 | /* If we are in PCI-X mode, enable register write workaround. | |
13818 | * | |
13819 | * The workaround is to use indirect register accesses | |
13820 | * for all chip writes not to mailbox registers. | |
13821 | */ | |
13822 | if (tg3_flag(tp, PCIX_MODE)) { | |
13823 | u32 pm_reg; | |
13824 | ||
13825 | tg3_flag_set(tp, PCIX_TARGET_HWBUG); | |
13826 | ||
13827 | /* The chip can have it's power management PCI config | |
13828 | * space registers clobbered due to this bug. | |
13829 | * So explicitly force the chip into D0 here. | |
13830 | */ | |
13831 | pci_read_config_dword(tp->pdev, | |
13832 | tp->pm_cap + PCI_PM_CTRL, | |
13833 | &pm_reg); | |
13834 | pm_reg &= ~PCI_PM_CTRL_STATE_MASK; | |
13835 | pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */; | |
13836 | pci_write_config_dword(tp->pdev, | |
13837 | tp->pm_cap + PCI_PM_CTRL, | |
13838 | pm_reg); | |
13839 | ||
13840 | /* Also, force SERR#/PERR# in PCI command. */ | |
13841 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
13842 | pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR; | |
13843 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
13844 | } | |
13845 | } | |
13846 | ||
13847 | if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0) | |
13848 | tg3_flag_set(tp, PCI_HIGH_SPEED); | |
13849 | if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0) | |
13850 | tg3_flag_set(tp, PCI_32BIT); | |
13851 | ||
13852 | /* Chip-specific fixup from Broadcom driver */ | |
13853 | if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) && | |
13854 | (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) { | |
13855 | pci_state_reg |= PCISTATE_RETRY_SAME_DMA; | |
13856 | pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg); | |
13857 | } | |
13858 | ||
13859 | /* Default fast path register access methods */ | |
13860 | tp->read32 = tg3_read32; | |
13861 | tp->write32 = tg3_write32; | |
13862 | tp->read32_mbox = tg3_read32; | |
13863 | tp->write32_mbox = tg3_write32; | |
13864 | tp->write32_tx_mbox = tg3_write32; | |
13865 | tp->write32_rx_mbox = tg3_write32; | |
13866 | ||
13867 | /* Various workaround register access methods */ | |
13868 | if (tg3_flag(tp, PCIX_TARGET_HWBUG)) | |
13869 | tp->write32 = tg3_write_indirect_reg32; | |
13870 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 || | |
13871 | (tg3_flag(tp, PCI_EXPRESS) && | |
13872 | tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) { | |
13873 | /* | |
13874 | * Back to back register writes can cause problems on these | |
13875 | * chips, the workaround is to read back all reg writes | |
13876 | * except those to mailbox regs. | |
13877 | * | |
13878 | * See tg3_write_indirect_reg32(). | |
13879 | */ | |
13880 | tp->write32 = tg3_write_flush_reg32; | |
13881 | } | |
13882 | ||
13883 | if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) { | |
13884 | tp->write32_tx_mbox = tg3_write32_tx_mbox; | |
13885 | if (tg3_flag(tp, MBOX_WRITE_REORDER)) | |
13886 | tp->write32_rx_mbox = tg3_write_flush_reg32; | |
13887 | } | |
13888 | ||
13889 | if (tg3_flag(tp, ICH_WORKAROUND)) { | |
13890 | tp->read32 = tg3_read_indirect_reg32; | |
13891 | tp->write32 = tg3_write_indirect_reg32; | |
13892 | tp->read32_mbox = tg3_read_indirect_mbox; | |
13893 | tp->write32_mbox = tg3_write_indirect_mbox; | |
13894 | tp->write32_tx_mbox = tg3_write_indirect_mbox; | |
13895 | tp->write32_rx_mbox = tg3_write_indirect_mbox; | |
13896 | ||
13897 | iounmap(tp->regs); | |
13898 | tp->regs = NULL; | |
13899 | ||
13900 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
13901 | pci_cmd &= ~PCI_COMMAND_MEMORY; | |
13902 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
13903 | } | |
13904 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | |
13905 | tp->read32_mbox = tg3_read32_mbox_5906; | |
13906 | tp->write32_mbox = tg3_write32_mbox_5906; | |
13907 | tp->write32_tx_mbox = tg3_write32_mbox_5906; | |
13908 | tp->write32_rx_mbox = tg3_write32_mbox_5906; | |
13909 | } | |
13910 | ||
13911 | if (tp->write32 == tg3_write_indirect_reg32 || | |
13912 | (tg3_flag(tp, PCIX_MODE) && | |
13913 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
13914 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701))) | |
13915 | tg3_flag_set(tp, SRAM_USE_CONFIG); | |
13916 | ||
13917 | /* Get eeprom hw config before calling tg3_set_power_state(). | |
13918 | * In particular, the TG3_FLAG_IS_NIC flag must be | |
13919 | * determined before calling tg3_set_power_state() so that | |
13920 | * we know whether or not to switch out of Vaux power. | |
13921 | * When the flag is set, it means that GPIO1 is used for eeprom | |
13922 | * write protect and also implies that it is a LOM where GPIOs | |
13923 | * are not used to switch power. | |
13924 | */ | |
13925 | tg3_get_eeprom_hw_cfg(tp); | |
13926 | ||
13927 | if (tg3_flag(tp, ENABLE_APE)) { | |
13928 | /* Allow reads and writes to the | |
13929 | * APE register and memory space. | |
13930 | */ | |
13931 | pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR | | |
13932 | PCISTATE_ALLOW_APE_SHMEM_WR | | |
13933 | PCISTATE_ALLOW_APE_PSPACE_WR; | |
13934 | pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, | |
13935 | pci_state_reg); | |
13936 | } | |
13937 | ||
13938 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || | |
13939 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || | |
13940 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || | |
13941 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || | |
13942 | tg3_flag(tp, 57765_PLUS)) | |
13943 | tg3_flag_set(tp, CPMU_PRESENT); | |
13944 | ||
13945 | /* Set up tp->grc_local_ctrl before calling tg3_power_up(). | |
13946 | * GPIO1 driven high will bring 5700's external PHY out of reset. | |
13947 | * It is also used as eeprom write protect on LOMs. | |
13948 | */ | |
13949 | tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM; | |
13950 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
13951 | tg3_flag(tp, EEPROM_WRITE_PROT)) | |
13952 | tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | | |
13953 | GRC_LCLCTRL_GPIO_OUTPUT1); | |
13954 | /* Unused GPIO3 must be driven as output on 5752 because there | |
13955 | * are no pull-up resistors on unused GPIO pins. | |
13956 | */ | |
13957 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) | |
13958 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3; | |
13959 | ||
13960 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || | |
13961 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || | |
13962 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
13963 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; | |
13964 | ||
13965 | if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || | |
13966 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { | |
13967 | /* Turn off the debug UART. */ | |
13968 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; | |
13969 | if (tg3_flag(tp, IS_NIC)) | |
13970 | /* Keep VMain power. */ | |
13971 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 | | |
13972 | GRC_LCLCTRL_GPIO_OUTPUT0; | |
13973 | } | |
13974 | ||
13975 | /* Force the chip into D0. */ | |
13976 | err = tg3_power_up(tp); | |
13977 | if (err) { | |
13978 | dev_err(&tp->pdev->dev, "Transition to D0 failed\n"); | |
13979 | return err; | |
13980 | } | |
13981 | ||
13982 | /* Derive initial jumbo mode from MTU assigned in | |
13983 | * ether_setup() via the alloc_etherdev() call | |
13984 | */ | |
13985 | if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS)) | |
13986 | tg3_flag_set(tp, JUMBO_RING_ENABLE); | |
13987 | ||
13988 | /* Determine WakeOnLan speed to use. */ | |
13989 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
13990 | tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
13991 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 || | |
13992 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) { | |
13993 | tg3_flag_clear(tp, WOL_SPEED_100MB); | |
13994 | } else { | |
13995 | tg3_flag_set(tp, WOL_SPEED_100MB); | |
13996 | } | |
13997 | ||
13998 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
13999 | tp->phy_flags |= TG3_PHYFLG_IS_FET; | |
14000 | ||
14001 | /* A few boards don't want Ethernet@WireSpeed phy feature */ | |
14002 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
14003 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && | |
14004 | (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) && | |
14005 | (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) || | |
14006 | (tp->phy_flags & TG3_PHYFLG_IS_FET) || | |
14007 | (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) | |
14008 | tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED; | |
14009 | ||
14010 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX || | |
14011 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX) | |
14012 | tp->phy_flags |= TG3_PHYFLG_ADC_BUG; | |
14013 | if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) | |
14014 | tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG; | |
14015 | ||
14016 | if (tg3_flag(tp, 5705_PLUS) && | |
14017 | !(tp->phy_flags & TG3_PHYFLG_IS_FET) && | |
14018 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && | |
14019 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 && | |
14020 | !tg3_flag(tp, 57765_PLUS)) { | |
14021 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || | |
14022 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || | |
14023 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || | |
14024 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) { | |
14025 | if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 && | |
14026 | tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722) | |
14027 | tp->phy_flags |= TG3_PHYFLG_JITTER_BUG; | |
14028 | if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M) | |
14029 | tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM; | |
14030 | } else | |
14031 | tp->phy_flags |= TG3_PHYFLG_BER_BUG; | |
14032 | } | |
14033 | ||
14034 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && | |
14035 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) { | |
14036 | tp->phy_otp = tg3_read_otp_phycfg(tp); | |
14037 | if (tp->phy_otp == 0) | |
14038 | tp->phy_otp = TG3_OTP_DEFAULT; | |
14039 | } | |
14040 | ||
14041 | if (tg3_flag(tp, CPMU_PRESENT)) | |
14042 | tp->mi_mode = MAC_MI_MODE_500KHZ_CONST; | |
14043 | else | |
14044 | tp->mi_mode = MAC_MI_MODE_BASE; | |
14045 | ||
14046 | tp->coalesce_mode = 0; | |
14047 | if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX && | |
14048 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX) | |
14049 | tp->coalesce_mode |= HOSTCC_MODE_32BYTE; | |
14050 | ||
14051 | /* Set these bits to enable statistics workaround. */ | |
14052 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | |
14053 | tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 || | |
14054 | tp->pci_chip_rev_id == CHIPREV_ID_5720_A0) { | |
14055 | tp->coalesce_mode |= HOSTCC_MODE_ATTN; | |
14056 | tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN; | |
14057 | } | |
14058 | ||
14059 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || | |
14060 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) | |
14061 | tg3_flag_set(tp, USE_PHYLIB); | |
14062 | ||
14063 | err = tg3_mdio_init(tp); | |
14064 | if (err) | |
14065 | return err; | |
14066 | ||
14067 | /* Initialize data/descriptor byte/word swapping. */ | |
14068 | val = tr32(GRC_MODE); | |
14069 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) | |
14070 | val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA | | |
14071 | GRC_MODE_WORD_SWAP_B2HRX_DATA | | |
14072 | GRC_MODE_B2HRX_ENABLE | | |
14073 | GRC_MODE_HTX2B_ENABLE | | |
14074 | GRC_MODE_HOST_STACKUP); | |
14075 | else | |
14076 | val &= GRC_MODE_HOST_STACKUP; | |
14077 | ||
14078 | tw32(GRC_MODE, val | tp->grc_mode); | |
14079 | ||
14080 | tg3_switch_clocks(tp); | |
14081 | ||
14082 | /* Clear this out for sanity. */ | |
14083 | tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
14084 | ||
14085 | pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, | |
14086 | &pci_state_reg); | |
14087 | if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 && | |
14088 | !tg3_flag(tp, PCIX_TARGET_HWBUG)) { | |
14089 | u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl); | |
14090 | ||
14091 | if (chiprevid == CHIPREV_ID_5701_A0 || | |
14092 | chiprevid == CHIPREV_ID_5701_B0 || | |
14093 | chiprevid == CHIPREV_ID_5701_B2 || | |
14094 | chiprevid == CHIPREV_ID_5701_B5) { | |
14095 | void __iomem *sram_base; | |
14096 | ||
14097 | /* Write some dummy words into the SRAM status block | |
14098 | * area, see if it reads back correctly. If the return | |
14099 | * value is bad, force enable the PCIX workaround. | |
14100 | */ | |
14101 | sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK; | |
14102 | ||
14103 | writel(0x00000000, sram_base); | |
14104 | writel(0x00000000, sram_base + 4); | |
14105 | writel(0xffffffff, sram_base + 4); | |
14106 | if (readl(sram_base) != 0x00000000) | |
14107 | tg3_flag_set(tp, PCIX_TARGET_HWBUG); | |
14108 | } | |
14109 | } | |
14110 | ||
14111 | udelay(50); | |
14112 | tg3_nvram_init(tp); | |
14113 | ||
14114 | grc_misc_cfg = tr32(GRC_MISC_CFG); | |
14115 | grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK; | |
14116 | ||
14117 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && | |
14118 | (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 || | |
14119 | grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M)) | |
14120 | tg3_flag_set(tp, IS_5788); | |
14121 | ||
14122 | if (!tg3_flag(tp, IS_5788) && | |
14123 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) | |
14124 | tg3_flag_set(tp, TAGGED_STATUS); | |
14125 | if (tg3_flag(tp, TAGGED_STATUS)) { | |
14126 | tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD | | |
14127 | HOSTCC_MODE_CLRTICK_TXBD); | |
14128 | ||
14129 | tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS; | |
14130 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
14131 | tp->misc_host_ctrl); | |
14132 | } | |
14133 | ||
14134 | /* Preserve the APE MAC_MODE bits */ | |
14135 | if (tg3_flag(tp, ENABLE_APE)) | |
14136 | tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; | |
14137 | else | |
14138 | tp->mac_mode = TG3_DEF_MAC_MODE; | |
14139 | ||
14140 | /* these are limited to 10/100 only */ | |
14141 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 && | |
14142 | (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) || | |
14143 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && | |
14144 | tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM && | |
14145 | (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 || | |
14146 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 || | |
14147 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) || | |
14148 | (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM && | |
14149 | (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F || | |
14150 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F || | |
14151 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) || | |
14152 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 || | |
14153 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 || | |
14154 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 || | |
14155 | (tp->phy_flags & TG3_PHYFLG_IS_FET)) | |
14156 | tp->phy_flags |= TG3_PHYFLG_10_100_ONLY; | |
14157 | ||
14158 | err = tg3_phy_probe(tp); | |
14159 | if (err) { | |
14160 | dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err); | |
14161 | /* ... but do not return immediately ... */ | |
14162 | tg3_mdio_fini(tp); | |
14163 | } | |
14164 | ||
14165 | tg3_read_vpd(tp); | |
14166 | tg3_read_fw_ver(tp); | |
14167 | ||
14168 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { | |
14169 | tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT; | |
14170 | } else { | |
14171 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) | |
14172 | tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT; | |
14173 | else | |
14174 | tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT; | |
14175 | } | |
14176 | ||
14177 | /* 5700 {AX,BX} chips have a broken status block link | |
14178 | * change bit implementation, so we must use the | |
14179 | * status register in those cases. | |
14180 | */ | |
14181 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) | |
14182 | tg3_flag_set(tp, USE_LINKCHG_REG); | |
14183 | else | |
14184 | tg3_flag_clear(tp, USE_LINKCHG_REG); | |
14185 | ||
14186 | /* The led_ctrl is set during tg3_phy_probe, here we might | |
14187 | * have to force the link status polling mechanism based | |
14188 | * upon subsystem IDs. | |
14189 | */ | |
14190 | if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL && | |
14191 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 && | |
14192 | !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { | |
14193 | tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT; | |
14194 | tg3_flag_set(tp, USE_LINKCHG_REG); | |
14195 | } | |
14196 | ||
14197 | /* For all SERDES we poll the MAC status register. */ | |
14198 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) | |
14199 | tg3_flag_set(tp, POLL_SERDES); | |
14200 | else | |
14201 | tg3_flag_clear(tp, POLL_SERDES); | |
14202 | ||
14203 | tp->rx_offset = NET_IP_ALIGN; | |
14204 | tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD; | |
14205 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 && | |
14206 | tg3_flag(tp, PCIX_MODE)) { | |
14207 | tp->rx_offset = 0; | |
14208 | #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS | |
14209 | tp->rx_copy_thresh = ~(u16)0; | |
14210 | #endif | |
14211 | } | |
14212 | ||
14213 | tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1; | |
14214 | tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1; | |
14215 | tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1; | |
14216 | ||
14217 | tp->rx_std_max_post = tp->rx_std_ring_mask + 1; | |
14218 | ||
14219 | /* Increment the rx prod index on the rx std ring by at most | |
14220 | * 8 for these chips to workaround hw errata. | |
14221 | */ | |
14222 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || | |
14223 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || | |
14224 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) | |
14225 | tp->rx_std_max_post = 8; | |
14226 | ||
14227 | if (tg3_flag(tp, ASPM_WORKAROUND)) | |
14228 | tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) & | |
14229 | PCIE_PWR_MGMT_L1_THRESH_MSK; | |
14230 | ||
14231 | return err; | |
14232 | } | |
14233 | ||
14234 | #ifdef CONFIG_SPARC | |
14235 | static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp) | |
14236 | { | |
14237 | struct net_device *dev = tp->dev; | |
14238 | struct pci_dev *pdev = tp->pdev; | |
14239 | struct device_node *dp = pci_device_to_OF_node(pdev); | |
14240 | const unsigned char *addr; | |
14241 | int len; | |
14242 | ||
14243 | addr = of_get_property(dp, "local-mac-address", &len); | |
14244 | if (addr && len == 6) { | |
14245 | memcpy(dev->dev_addr, addr, 6); | |
14246 | memcpy(dev->perm_addr, dev->dev_addr, 6); | |
14247 | return 0; | |
14248 | } | |
14249 | return -ENODEV; | |
14250 | } | |
14251 | ||
14252 | static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp) | |
14253 | { | |
14254 | struct net_device *dev = tp->dev; | |
14255 | ||
14256 | memcpy(dev->dev_addr, idprom->id_ethaddr, 6); | |
14257 | memcpy(dev->perm_addr, idprom->id_ethaddr, 6); | |
14258 | return 0; | |
14259 | } | |
14260 | #endif | |
14261 | ||
14262 | static int __devinit tg3_get_device_address(struct tg3 *tp) | |
14263 | { | |
14264 | struct net_device *dev = tp->dev; | |
14265 | u32 hi, lo, mac_offset; | |
14266 | int addr_ok = 0; | |
14267 | ||
14268 | #ifdef CONFIG_SPARC | |
14269 | if (!tg3_get_macaddr_sparc(tp)) | |
14270 | return 0; | |
14271 | #endif | |
14272 | ||
14273 | mac_offset = 0x7c; | |
14274 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
14275 | tg3_flag(tp, 5780_CLASS)) { | |
14276 | if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID) | |
14277 | mac_offset = 0xcc; | |
14278 | if (tg3_nvram_lock(tp)) | |
14279 | tw32_f(NVRAM_CMD, NVRAM_CMD_RESET); | |
14280 | else | |
14281 | tg3_nvram_unlock(tp); | |
14282 | } else if (tg3_flag(tp, 5717_PLUS)) { | |
14283 | if (PCI_FUNC(tp->pdev->devfn) & 1) | |
14284 | mac_offset = 0xcc; | |
14285 | if (PCI_FUNC(tp->pdev->devfn) > 1) | |
14286 | mac_offset += 0x18c; | |
14287 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
14288 | mac_offset = 0x10; | |
14289 | ||
14290 | /* First try to get it from MAC address mailbox. */ | |
14291 | tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi); | |
14292 | if ((hi >> 16) == 0x484b) { | |
14293 | dev->dev_addr[0] = (hi >> 8) & 0xff; | |
14294 | dev->dev_addr[1] = (hi >> 0) & 0xff; | |
14295 | ||
14296 | tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo); | |
14297 | dev->dev_addr[2] = (lo >> 24) & 0xff; | |
14298 | dev->dev_addr[3] = (lo >> 16) & 0xff; | |
14299 | dev->dev_addr[4] = (lo >> 8) & 0xff; | |
14300 | dev->dev_addr[5] = (lo >> 0) & 0xff; | |
14301 | ||
14302 | /* Some old bootcode may report a 0 MAC address in SRAM */ | |
14303 | addr_ok = is_valid_ether_addr(&dev->dev_addr[0]); | |
14304 | } | |
14305 | if (!addr_ok) { | |
14306 | /* Next, try NVRAM. */ | |
14307 | if (!tg3_flag(tp, NO_NVRAM) && | |
14308 | !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) && | |
14309 | !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) { | |
14310 | memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2); | |
14311 | memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo)); | |
14312 | } | |
14313 | /* Finally just fetch it out of the MAC control regs. */ | |
14314 | else { | |
14315 | hi = tr32(MAC_ADDR_0_HIGH); | |
14316 | lo = tr32(MAC_ADDR_0_LOW); | |
14317 | ||
14318 | dev->dev_addr[5] = lo & 0xff; | |
14319 | dev->dev_addr[4] = (lo >> 8) & 0xff; | |
14320 | dev->dev_addr[3] = (lo >> 16) & 0xff; | |
14321 | dev->dev_addr[2] = (lo >> 24) & 0xff; | |
14322 | dev->dev_addr[1] = hi & 0xff; | |
14323 | dev->dev_addr[0] = (hi >> 8) & 0xff; | |
14324 | } | |
14325 | } | |
14326 | ||
14327 | if (!is_valid_ether_addr(&dev->dev_addr[0])) { | |
14328 | #ifdef CONFIG_SPARC | |
14329 | if (!tg3_get_default_macaddr_sparc(tp)) | |
14330 | return 0; | |
14331 | #endif | |
14332 | return -EINVAL; | |
14333 | } | |
14334 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); | |
14335 | return 0; | |
14336 | } | |
14337 | ||
14338 | #define BOUNDARY_SINGLE_CACHELINE 1 | |
14339 | #define BOUNDARY_MULTI_CACHELINE 2 | |
14340 | ||
14341 | static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val) | |
14342 | { | |
14343 | int cacheline_size; | |
14344 | u8 byte; | |
14345 | int goal; | |
14346 | ||
14347 | pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte); | |
14348 | if (byte == 0) | |
14349 | cacheline_size = 1024; | |
14350 | else | |
14351 | cacheline_size = (int) byte * 4; | |
14352 | ||
14353 | /* On 5703 and later chips, the boundary bits have no | |
14354 | * effect. | |
14355 | */ | |
14356 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | |
14357 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 && | |
14358 | !tg3_flag(tp, PCI_EXPRESS)) | |
14359 | goto out; | |
14360 | ||
14361 | #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC) | |
14362 | goal = BOUNDARY_MULTI_CACHELINE; | |
14363 | #else | |
14364 | #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA) | |
14365 | goal = BOUNDARY_SINGLE_CACHELINE; | |
14366 | #else | |
14367 | goal = 0; | |
14368 | #endif | |
14369 | #endif | |
14370 | ||
14371 | if (tg3_flag(tp, 57765_PLUS)) { | |
14372 | val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT; | |
14373 | goto out; | |
14374 | } | |
14375 | ||
14376 | if (!goal) | |
14377 | goto out; | |
14378 | ||
14379 | /* PCI controllers on most RISC systems tend to disconnect | |
14380 | * when a device tries to burst across a cache-line boundary. | |
14381 | * Therefore, letting tg3 do so just wastes PCI bandwidth. | |
14382 | * | |
14383 | * Unfortunately, for PCI-E there are only limited | |
14384 | * write-side controls for this, and thus for reads | |
14385 | * we will still get the disconnects. We'll also waste | |
14386 | * these PCI cycles for both read and write for chips | |
14387 | * other than 5700 and 5701 which do not implement the | |
14388 | * boundary bits. | |
14389 | */ | |
14390 | if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) { | |
14391 | switch (cacheline_size) { | |
14392 | case 16: | |
14393 | case 32: | |
14394 | case 64: | |
14395 | case 128: | |
14396 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
14397 | val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX | | |
14398 | DMA_RWCTRL_WRITE_BNDRY_128_PCIX); | |
14399 | } else { | |
14400 | val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX | | |
14401 | DMA_RWCTRL_WRITE_BNDRY_384_PCIX); | |
14402 | } | |
14403 | break; | |
14404 | ||
14405 | case 256: | |
14406 | val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX | | |
14407 | DMA_RWCTRL_WRITE_BNDRY_256_PCIX); | |
14408 | break; | |
14409 | ||
14410 | default: | |
14411 | val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX | | |
14412 | DMA_RWCTRL_WRITE_BNDRY_384_PCIX); | |
14413 | break; | |
14414 | } | |
14415 | } else if (tg3_flag(tp, PCI_EXPRESS)) { | |
14416 | switch (cacheline_size) { | |
14417 | case 16: | |
14418 | case 32: | |
14419 | case 64: | |
14420 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
14421 | val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE; | |
14422 | val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE; | |
14423 | break; | |
14424 | } | |
14425 | /* fallthrough */ | |
14426 | case 128: | |
14427 | default: | |
14428 | val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE; | |
14429 | val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE; | |
14430 | break; | |
14431 | } | |
14432 | } else { | |
14433 | switch (cacheline_size) { | |
14434 | case 16: | |
14435 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
14436 | val |= (DMA_RWCTRL_READ_BNDRY_16 | | |
14437 | DMA_RWCTRL_WRITE_BNDRY_16); | |
14438 | break; | |
14439 | } | |
14440 | /* fallthrough */ | |
14441 | case 32: | |
14442 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
14443 | val |= (DMA_RWCTRL_READ_BNDRY_32 | | |
14444 | DMA_RWCTRL_WRITE_BNDRY_32); | |
14445 | break; | |
14446 | } | |
14447 | /* fallthrough */ | |
14448 | case 64: | |
14449 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
14450 | val |= (DMA_RWCTRL_READ_BNDRY_64 | | |
14451 | DMA_RWCTRL_WRITE_BNDRY_64); | |
14452 | break; | |
14453 | } | |
14454 | /* fallthrough */ | |
14455 | case 128: | |
14456 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
14457 | val |= (DMA_RWCTRL_READ_BNDRY_128 | | |
14458 | DMA_RWCTRL_WRITE_BNDRY_128); | |
14459 | break; | |
14460 | } | |
14461 | /* fallthrough */ | |
14462 | case 256: | |
14463 | val |= (DMA_RWCTRL_READ_BNDRY_256 | | |
14464 | DMA_RWCTRL_WRITE_BNDRY_256); | |
14465 | break; | |
14466 | case 512: | |
14467 | val |= (DMA_RWCTRL_READ_BNDRY_512 | | |
14468 | DMA_RWCTRL_WRITE_BNDRY_512); | |
14469 | break; | |
14470 | case 1024: | |
14471 | default: | |
14472 | val |= (DMA_RWCTRL_READ_BNDRY_1024 | | |
14473 | DMA_RWCTRL_WRITE_BNDRY_1024); | |
14474 | break; | |
14475 | } | |
14476 | } | |
14477 | ||
14478 | out: | |
14479 | return val; | |
14480 | } | |
14481 | ||
14482 | static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device) | |
14483 | { | |
14484 | struct tg3_internal_buffer_desc test_desc; | |
14485 | u32 sram_dma_descs; | |
14486 | int i, ret; | |
14487 | ||
14488 | sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE; | |
14489 | ||
14490 | tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0); | |
14491 | tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0); | |
14492 | tw32(RDMAC_STATUS, 0); | |
14493 | tw32(WDMAC_STATUS, 0); | |
14494 | ||
14495 | tw32(BUFMGR_MODE, 0); | |
14496 | tw32(FTQ_RESET, 0); | |
14497 | ||
14498 | test_desc.addr_hi = ((u64) buf_dma) >> 32; | |
14499 | test_desc.addr_lo = buf_dma & 0xffffffff; | |
14500 | test_desc.nic_mbuf = 0x00002100; | |
14501 | test_desc.len = size; | |
14502 | ||
14503 | /* | |
14504 | * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz | |
14505 | * the *second* time the tg3 driver was getting loaded after an | |
14506 | * initial scan. | |
14507 | * | |
14508 | * Broadcom tells me: | |
14509 | * ...the DMA engine is connected to the GRC block and a DMA | |
14510 | * reset may affect the GRC block in some unpredictable way... | |
14511 | * The behavior of resets to individual blocks has not been tested. | |
14512 | * | |
14513 | * Broadcom noted the GRC reset will also reset all sub-components. | |
14514 | */ | |
14515 | if (to_device) { | |
14516 | test_desc.cqid_sqid = (13 << 8) | 2; | |
14517 | ||
14518 | tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE); | |
14519 | udelay(40); | |
14520 | } else { | |
14521 | test_desc.cqid_sqid = (16 << 8) | 7; | |
14522 | ||
14523 | tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE); | |
14524 | udelay(40); | |
14525 | } | |
14526 | test_desc.flags = 0x00000005; | |
14527 | ||
14528 | for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) { | |
14529 | u32 val; | |
14530 | ||
14531 | val = *(((u32 *)&test_desc) + i); | |
14532 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, | |
14533 | sram_dma_descs + (i * sizeof(u32))); | |
14534 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); | |
14535 | } | |
14536 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
14537 | ||
14538 | if (to_device) | |
14539 | tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs); | |
14540 | else | |
14541 | tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs); | |
14542 | ||
14543 | ret = -ENODEV; | |
14544 | for (i = 0; i < 40; i++) { | |
14545 | u32 val; | |
14546 | ||
14547 | if (to_device) | |
14548 | val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ); | |
14549 | else | |
14550 | val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ); | |
14551 | if ((val & 0xffff) == sram_dma_descs) { | |
14552 | ret = 0; | |
14553 | break; | |
14554 | } | |
14555 | ||
14556 | udelay(100); | |
14557 | } | |
14558 | ||
14559 | return ret; | |
14560 | } | |
14561 | ||
14562 | #define TEST_BUFFER_SIZE 0x2000 | |
14563 | ||
14564 | static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets) = { | |
14565 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) }, | |
14566 | { }, | |
14567 | }; | |
14568 | ||
14569 | static int __devinit tg3_test_dma(struct tg3 *tp) | |
14570 | { | |
14571 | dma_addr_t buf_dma; | |
14572 | u32 *buf, saved_dma_rwctrl; | |
14573 | int ret = 0; | |
14574 | ||
14575 | buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, | |
14576 | &buf_dma, GFP_KERNEL); | |
14577 | if (!buf) { | |
14578 | ret = -ENOMEM; | |
14579 | goto out_nofree; | |
14580 | } | |
14581 | ||
14582 | tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) | | |
14583 | (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT)); | |
14584 | ||
14585 | tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl); | |
14586 | ||
14587 | if (tg3_flag(tp, 57765_PLUS)) | |
14588 | goto out; | |
14589 | ||
14590 | if (tg3_flag(tp, PCI_EXPRESS)) { | |
14591 | /* DMA read watermark not used on PCIE */ | |
14592 | tp->dma_rwctrl |= 0x00180000; | |
14593 | } else if (!tg3_flag(tp, PCIX_MODE)) { | |
14594 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 || | |
14595 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) | |
14596 | tp->dma_rwctrl |= 0x003f0000; | |
14597 | else | |
14598 | tp->dma_rwctrl |= 0x003f000f; | |
14599 | } else { | |
14600 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
14601 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { | |
14602 | u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f); | |
14603 | u32 read_water = 0x7; | |
14604 | ||
14605 | /* If the 5704 is behind the EPB bridge, we can | |
14606 | * do the less restrictive ONE_DMA workaround for | |
14607 | * better performance. | |
14608 | */ | |
14609 | if (tg3_flag(tp, 40BIT_DMA_BUG) && | |
14610 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) | |
14611 | tp->dma_rwctrl |= 0x8000; | |
14612 | else if (ccval == 0x6 || ccval == 0x7) | |
14613 | tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA; | |
14614 | ||
14615 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) | |
14616 | read_water = 4; | |
14617 | /* Set bit 23 to enable PCIX hw bug fix */ | |
14618 | tp->dma_rwctrl |= | |
14619 | (read_water << DMA_RWCTRL_READ_WATER_SHIFT) | | |
14620 | (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) | | |
14621 | (1 << 23); | |
14622 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) { | |
14623 | /* 5780 always in PCIX mode */ | |
14624 | tp->dma_rwctrl |= 0x00144000; | |
14625 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { | |
14626 | /* 5714 always in PCIX mode */ | |
14627 | tp->dma_rwctrl |= 0x00148000; | |
14628 | } else { | |
14629 | tp->dma_rwctrl |= 0x001b000f; | |
14630 | } | |
14631 | } | |
14632 | ||
14633 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
14634 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) | |
14635 | tp->dma_rwctrl &= 0xfffffff0; | |
14636 | ||
14637 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
14638 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
14639 | /* Remove this if it causes problems for some boards. */ | |
14640 | tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT; | |
14641 | ||
14642 | /* On 5700/5701 chips, we need to set this bit. | |
14643 | * Otherwise the chip will issue cacheline transactions | |
14644 | * to streamable DMA memory with not all the byte | |
14645 | * enables turned on. This is an error on several | |
14646 | * RISC PCI controllers, in particular sparc64. | |
14647 | * | |
14648 | * On 5703/5704 chips, this bit has been reassigned | |
14649 | * a different meaning. In particular, it is used | |
14650 | * on those chips to enable a PCI-X workaround. | |
14651 | */ | |
14652 | tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE; | |
14653 | } | |
14654 | ||
14655 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
14656 | ||
14657 | #if 0 | |
14658 | /* Unneeded, already done by tg3_get_invariants. */ | |
14659 | tg3_switch_clocks(tp); | |
14660 | #endif | |
14661 | ||
14662 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | |
14663 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) | |
14664 | goto out; | |
14665 | ||
14666 | /* It is best to perform DMA test with maximum write burst size | |
14667 | * to expose the 5700/5701 write DMA bug. | |
14668 | */ | |
14669 | saved_dma_rwctrl = tp->dma_rwctrl; | |
14670 | tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; | |
14671 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
14672 | ||
14673 | while (1) { | |
14674 | u32 *p = buf, i; | |
14675 | ||
14676 | for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) | |
14677 | p[i] = i; | |
14678 | ||
14679 | /* Send the buffer to the chip. */ | |
14680 | ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1); | |
14681 | if (ret) { | |
14682 | dev_err(&tp->pdev->dev, | |
14683 | "%s: Buffer write failed. err = %d\n", | |
14684 | __func__, ret); | |
14685 | break; | |
14686 | } | |
14687 | ||
14688 | #if 0 | |
14689 | /* validate data reached card RAM correctly. */ | |
14690 | for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) { | |
14691 | u32 val; | |
14692 | tg3_read_mem(tp, 0x2100 + (i*4), &val); | |
14693 | if (le32_to_cpu(val) != p[i]) { | |
14694 | dev_err(&tp->pdev->dev, | |
14695 | "%s: Buffer corrupted on device! " | |
14696 | "(%d != %d)\n", __func__, val, i); | |
14697 | /* ret = -ENODEV here? */ | |
14698 | } | |
14699 | p[i] = 0; | |
14700 | } | |
14701 | #endif | |
14702 | /* Now read it back. */ | |
14703 | ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0); | |
14704 | if (ret) { | |
14705 | dev_err(&tp->pdev->dev, "%s: Buffer read failed. " | |
14706 | "err = %d\n", __func__, ret); | |
14707 | break; | |
14708 | } | |
14709 | ||
14710 | /* Verify it. */ | |
14711 | for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) { | |
14712 | if (p[i] == i) | |
14713 | continue; | |
14714 | ||
14715 | if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != | |
14716 | DMA_RWCTRL_WRITE_BNDRY_16) { | |
14717 | tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; | |
14718 | tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; | |
14719 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
14720 | break; | |
14721 | } else { | |
14722 | dev_err(&tp->pdev->dev, | |
14723 | "%s: Buffer corrupted on read back! " | |
14724 | "(%d != %d)\n", __func__, p[i], i); | |
14725 | ret = -ENODEV; | |
14726 | goto out; | |
14727 | } | |
14728 | } | |
14729 | ||
14730 | if (i == (TEST_BUFFER_SIZE / sizeof(u32))) { | |
14731 | /* Success. */ | |
14732 | ret = 0; | |
14733 | break; | |
14734 | } | |
14735 | } | |
14736 | if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != | |
14737 | DMA_RWCTRL_WRITE_BNDRY_16) { | |
14738 | /* DMA test passed without adjusting DMA boundary, | |
14739 | * now look for chipsets that are known to expose the | |
14740 | * DMA bug without failing the test. | |
14741 | */ | |
14742 | if (pci_dev_present(tg3_dma_wait_state_chipsets)) { | |
14743 | tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; | |
14744 | tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; | |
14745 | } else { | |
14746 | /* Safe to use the calculated DMA boundary. */ | |
14747 | tp->dma_rwctrl = saved_dma_rwctrl; | |
14748 | } | |
14749 | ||
14750 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
14751 | } | |
14752 | ||
14753 | out: | |
14754 | dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma); | |
14755 | out_nofree: | |
14756 | return ret; | |
14757 | } | |
14758 | ||
14759 | static void __devinit tg3_init_bufmgr_config(struct tg3 *tp) | |
14760 | { | |
14761 | if (tg3_flag(tp, 57765_PLUS)) { | |
14762 | tp->bufmgr_config.mbuf_read_dma_low_water = | |
14763 | DEFAULT_MB_RDMA_LOW_WATER_5705; | |
14764 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
14765 | DEFAULT_MB_MACRX_LOW_WATER_57765; | |
14766 | tp->bufmgr_config.mbuf_high_water = | |
14767 | DEFAULT_MB_HIGH_WATER_57765; | |
14768 | ||
14769 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = | |
14770 | DEFAULT_MB_RDMA_LOW_WATER_5705; | |
14771 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = | |
14772 | DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765; | |
14773 | tp->bufmgr_config.mbuf_high_water_jumbo = | |
14774 | DEFAULT_MB_HIGH_WATER_JUMBO_57765; | |
14775 | } else if (tg3_flag(tp, 5705_PLUS)) { | |
14776 | tp->bufmgr_config.mbuf_read_dma_low_water = | |
14777 | DEFAULT_MB_RDMA_LOW_WATER_5705; | |
14778 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
14779 | DEFAULT_MB_MACRX_LOW_WATER_5705; | |
14780 | tp->bufmgr_config.mbuf_high_water = | |
14781 | DEFAULT_MB_HIGH_WATER_5705; | |
14782 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | |
14783 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
14784 | DEFAULT_MB_MACRX_LOW_WATER_5906; | |
14785 | tp->bufmgr_config.mbuf_high_water = | |
14786 | DEFAULT_MB_HIGH_WATER_5906; | |
14787 | } | |
14788 | ||
14789 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = | |
14790 | DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780; | |
14791 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = | |
14792 | DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780; | |
14793 | tp->bufmgr_config.mbuf_high_water_jumbo = | |
14794 | DEFAULT_MB_HIGH_WATER_JUMBO_5780; | |
14795 | } else { | |
14796 | tp->bufmgr_config.mbuf_read_dma_low_water = | |
14797 | DEFAULT_MB_RDMA_LOW_WATER; | |
14798 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
14799 | DEFAULT_MB_MACRX_LOW_WATER; | |
14800 | tp->bufmgr_config.mbuf_high_water = | |
14801 | DEFAULT_MB_HIGH_WATER; | |
14802 | ||
14803 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = | |
14804 | DEFAULT_MB_RDMA_LOW_WATER_JUMBO; | |
14805 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = | |
14806 | DEFAULT_MB_MACRX_LOW_WATER_JUMBO; | |
14807 | tp->bufmgr_config.mbuf_high_water_jumbo = | |
14808 | DEFAULT_MB_HIGH_WATER_JUMBO; | |
14809 | } | |
14810 | ||
14811 | tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER; | |
14812 | tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER; | |
14813 | } | |
14814 | ||
14815 | static char * __devinit tg3_phy_string(struct tg3 *tp) | |
14816 | { | |
14817 | switch (tp->phy_id & TG3_PHY_ID_MASK) { | |
14818 | case TG3_PHY_ID_BCM5400: return "5400"; | |
14819 | case TG3_PHY_ID_BCM5401: return "5401"; | |
14820 | case TG3_PHY_ID_BCM5411: return "5411"; | |
14821 | case TG3_PHY_ID_BCM5701: return "5701"; | |
14822 | case TG3_PHY_ID_BCM5703: return "5703"; | |
14823 | case TG3_PHY_ID_BCM5704: return "5704"; | |
14824 | case TG3_PHY_ID_BCM5705: return "5705"; | |
14825 | case TG3_PHY_ID_BCM5750: return "5750"; | |
14826 | case TG3_PHY_ID_BCM5752: return "5752"; | |
14827 | case TG3_PHY_ID_BCM5714: return "5714"; | |
14828 | case TG3_PHY_ID_BCM5780: return "5780"; | |
14829 | case TG3_PHY_ID_BCM5755: return "5755"; | |
14830 | case TG3_PHY_ID_BCM5787: return "5787"; | |
14831 | case TG3_PHY_ID_BCM5784: return "5784"; | |
14832 | case TG3_PHY_ID_BCM5756: return "5722/5756"; | |
14833 | case TG3_PHY_ID_BCM5906: return "5906"; | |
14834 | case TG3_PHY_ID_BCM5761: return "5761"; | |
14835 | case TG3_PHY_ID_BCM5718C: return "5718C"; | |
14836 | case TG3_PHY_ID_BCM5718S: return "5718S"; | |
14837 | case TG3_PHY_ID_BCM57765: return "57765"; | |
14838 | case TG3_PHY_ID_BCM5719C: return "5719C"; | |
14839 | case TG3_PHY_ID_BCM5720C: return "5720C"; | |
14840 | case TG3_PHY_ID_BCM8002: return "8002/serdes"; | |
14841 | case 0: return "serdes"; | |
14842 | default: return "unknown"; | |
14843 | } | |
14844 | } | |
14845 | ||
14846 | static char * __devinit tg3_bus_string(struct tg3 *tp, char *str) | |
14847 | { | |
14848 | if (tg3_flag(tp, PCI_EXPRESS)) { | |
14849 | strcpy(str, "PCI Express"); | |
14850 | return str; | |
14851 | } else if (tg3_flag(tp, PCIX_MODE)) { | |
14852 | u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f; | |
14853 | ||
14854 | strcpy(str, "PCIX:"); | |
14855 | ||
14856 | if ((clock_ctrl == 7) || | |
14857 | ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) == | |
14858 | GRC_MISC_CFG_BOARD_ID_5704CIOBE)) | |
14859 | strcat(str, "133MHz"); | |
14860 | else if (clock_ctrl == 0) | |
14861 | strcat(str, "33MHz"); | |
14862 | else if (clock_ctrl == 2) | |
14863 | strcat(str, "50MHz"); | |
14864 | else if (clock_ctrl == 4) | |
14865 | strcat(str, "66MHz"); | |
14866 | else if (clock_ctrl == 6) | |
14867 | strcat(str, "100MHz"); | |
14868 | } else { | |
14869 | strcpy(str, "PCI:"); | |
14870 | if (tg3_flag(tp, PCI_HIGH_SPEED)) | |
14871 | strcat(str, "66MHz"); | |
14872 | else | |
14873 | strcat(str, "33MHz"); | |
14874 | } | |
14875 | if (tg3_flag(tp, PCI_32BIT)) | |
14876 | strcat(str, ":32-bit"); | |
14877 | else | |
14878 | strcat(str, ":64-bit"); | |
14879 | return str; | |
14880 | } | |
14881 | ||
14882 | static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp) | |
14883 | { | |
14884 | struct pci_dev *peer; | |
14885 | unsigned int func, devnr = tp->pdev->devfn & ~7; | |
14886 | ||
14887 | for (func = 0; func < 8; func++) { | |
14888 | peer = pci_get_slot(tp->pdev->bus, devnr | func); | |
14889 | if (peer && peer != tp->pdev) | |
14890 | break; | |
14891 | pci_dev_put(peer); | |
14892 | } | |
14893 | /* 5704 can be configured in single-port mode, set peer to | |
14894 | * tp->pdev in that case. | |
14895 | */ | |
14896 | if (!peer) { | |
14897 | peer = tp->pdev; | |
14898 | return peer; | |
14899 | } | |
14900 | ||
14901 | /* | |
14902 | * We don't need to keep the refcount elevated; there's no way | |
14903 | * to remove one half of this device without removing the other | |
14904 | */ | |
14905 | pci_dev_put(peer); | |
14906 | ||
14907 | return peer; | |
14908 | } | |
14909 | ||
14910 | static void __devinit tg3_init_coal(struct tg3 *tp) | |
14911 | { | |
14912 | struct ethtool_coalesce *ec = &tp->coal; | |
14913 | ||
14914 | memset(ec, 0, sizeof(*ec)); | |
14915 | ec->cmd = ETHTOOL_GCOALESCE; | |
14916 | ec->rx_coalesce_usecs = LOW_RXCOL_TICKS; | |
14917 | ec->tx_coalesce_usecs = LOW_TXCOL_TICKS; | |
14918 | ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES; | |
14919 | ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES; | |
14920 | ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT; | |
14921 | ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT; | |
14922 | ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT; | |
14923 | ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT; | |
14924 | ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS; | |
14925 | ||
14926 | if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD | | |
14927 | HOSTCC_MODE_CLRTICK_TXBD)) { | |
14928 | ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS; | |
14929 | ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS; | |
14930 | ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS; | |
14931 | ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS; | |
14932 | } | |
14933 | ||
14934 | if (tg3_flag(tp, 5705_PLUS)) { | |
14935 | ec->rx_coalesce_usecs_irq = 0; | |
14936 | ec->tx_coalesce_usecs_irq = 0; | |
14937 | ec->stats_block_coalesce_usecs = 0; | |
14938 | } | |
14939 | } | |
14940 | ||
14941 | static const struct net_device_ops tg3_netdev_ops = { | |
14942 | .ndo_open = tg3_open, | |
14943 | .ndo_stop = tg3_close, | |
14944 | .ndo_start_xmit = tg3_start_xmit, | |
14945 | .ndo_get_stats64 = tg3_get_stats64, | |
14946 | .ndo_validate_addr = eth_validate_addr, | |
14947 | .ndo_set_multicast_list = tg3_set_rx_mode, | |
14948 | .ndo_set_mac_address = tg3_set_mac_addr, | |
14949 | .ndo_do_ioctl = tg3_ioctl, | |
14950 | .ndo_tx_timeout = tg3_tx_timeout, | |
14951 | .ndo_change_mtu = tg3_change_mtu, | |
14952 | .ndo_fix_features = tg3_fix_features, | |
14953 | .ndo_set_features = tg3_set_features, | |
14954 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
14955 | .ndo_poll_controller = tg3_poll_controller, | |
14956 | #endif | |
14957 | }; | |
14958 | ||
14959 | static int __devinit tg3_init_one(struct pci_dev *pdev, | |
14960 | const struct pci_device_id *ent) | |
14961 | { | |
14962 | struct net_device *dev; | |
14963 | struct tg3 *tp; | |
14964 | int i, err, pm_cap; | |
14965 | u32 sndmbx, rcvmbx, intmbx; | |
14966 | char str[40]; | |
14967 | u64 dma_mask, persist_dma_mask; | |
14968 | u32 features = 0; | |
14969 | ||
14970 | printk_once(KERN_INFO "%s\n", version); | |
14971 | ||
14972 | err = pci_enable_device(pdev); | |
14973 | if (err) { | |
14974 | dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); | |
14975 | return err; | |
14976 | } | |
14977 | ||
14978 | err = pci_request_regions(pdev, DRV_MODULE_NAME); | |
14979 | if (err) { | |
14980 | dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n"); | |
14981 | goto err_out_disable_pdev; | |
14982 | } | |
14983 | ||
14984 | pci_set_master(pdev); | |
14985 | ||
14986 | /* Find power-management capability. */ | |
14987 | pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); | |
14988 | if (pm_cap == 0) { | |
14989 | dev_err(&pdev->dev, | |
14990 | "Cannot find Power Management capability, aborting\n"); | |
14991 | err = -EIO; | |
14992 | goto err_out_free_res; | |
14993 | } | |
14994 | ||
14995 | dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS); | |
14996 | if (!dev) { | |
14997 | dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n"); | |
14998 | err = -ENOMEM; | |
14999 | goto err_out_free_res; | |
15000 | } | |
15001 | ||
15002 | SET_NETDEV_DEV(dev, &pdev->dev); | |
15003 | ||
15004 | tp = netdev_priv(dev); | |
15005 | tp->pdev = pdev; | |
15006 | tp->dev = dev; | |
15007 | tp->pm_cap = pm_cap; | |
15008 | tp->rx_mode = TG3_DEF_RX_MODE; | |
15009 | tp->tx_mode = TG3_DEF_TX_MODE; | |
15010 | ||
15011 | if (tg3_debug > 0) | |
15012 | tp->msg_enable = tg3_debug; | |
15013 | else | |
15014 | tp->msg_enable = TG3_DEF_MSG_ENABLE; | |
15015 | ||
15016 | /* The word/byte swap controls here control register access byte | |
15017 | * swapping. DMA data byte swapping is controlled in the GRC_MODE | |
15018 | * setting below. | |
15019 | */ | |
15020 | tp->misc_host_ctrl = | |
15021 | MISC_HOST_CTRL_MASK_PCI_INT | | |
15022 | MISC_HOST_CTRL_WORD_SWAP | | |
15023 | MISC_HOST_CTRL_INDIR_ACCESS | | |
15024 | MISC_HOST_CTRL_PCISTATE_RW; | |
15025 | ||
15026 | /* The NONFRM (non-frame) byte/word swap controls take effect | |
15027 | * on descriptor entries, anything which isn't packet data. | |
15028 | * | |
15029 | * The StrongARM chips on the board (one for tx, one for rx) | |
15030 | * are running in big-endian mode. | |
15031 | */ | |
15032 | tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA | | |
15033 | GRC_MODE_WSWAP_NONFRM_DATA); | |
15034 | #ifdef __BIG_ENDIAN | |
15035 | tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA; | |
15036 | #endif | |
15037 | spin_lock_init(&tp->lock); | |
15038 | spin_lock_init(&tp->indirect_lock); | |
15039 | INIT_WORK(&tp->reset_task, tg3_reset_task); | |
15040 | ||
15041 | tp->regs = pci_ioremap_bar(pdev, BAR_0); | |
15042 | if (!tp->regs) { | |
15043 | dev_err(&pdev->dev, "Cannot map device registers, aborting\n"); | |
15044 | err = -ENOMEM; | |
15045 | goto err_out_free_dev; | |
15046 | } | |
15047 | ||
15048 | tp->rx_pending = TG3_DEF_RX_RING_PENDING; | |
15049 | tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING; | |
15050 | ||
15051 | dev->ethtool_ops = &tg3_ethtool_ops; | |
15052 | dev->watchdog_timeo = TG3_TX_TIMEOUT; | |
15053 | dev->netdev_ops = &tg3_netdev_ops; | |
15054 | dev->irq = pdev->irq; | |
15055 | ||
15056 | err = tg3_get_invariants(tp); | |
15057 | if (err) { | |
15058 | dev_err(&pdev->dev, | |
15059 | "Problem fetching invariants of chip, aborting\n"); | |
15060 | goto err_out_iounmap; | |
15061 | } | |
15062 | ||
15063 | /* The EPB bridge inside 5714, 5715, and 5780 and any | |
15064 | * device behind the EPB cannot support DMA addresses > 40-bit. | |
15065 | * On 64-bit systems with IOMMU, use 40-bit dma_mask. | |
15066 | * On 64-bit systems without IOMMU, use 64-bit dma_mask and | |
15067 | * do DMA address check in tg3_start_xmit(). | |
15068 | */ | |
15069 | if (tg3_flag(tp, IS_5788)) | |
15070 | persist_dma_mask = dma_mask = DMA_BIT_MASK(32); | |
15071 | else if (tg3_flag(tp, 40BIT_DMA_BUG)) { | |
15072 | persist_dma_mask = dma_mask = DMA_BIT_MASK(40); | |
15073 | #ifdef CONFIG_HIGHMEM | |
15074 | dma_mask = DMA_BIT_MASK(64); | |
15075 | #endif | |
15076 | } else | |
15077 | persist_dma_mask = dma_mask = DMA_BIT_MASK(64); | |
15078 | ||
15079 | /* Configure DMA attributes. */ | |
15080 | if (dma_mask > DMA_BIT_MASK(32)) { | |
15081 | err = pci_set_dma_mask(pdev, dma_mask); | |
15082 | if (!err) { | |
15083 | features |= NETIF_F_HIGHDMA; | |
15084 | err = pci_set_consistent_dma_mask(pdev, | |
15085 | persist_dma_mask); | |
15086 | if (err < 0) { | |
15087 | dev_err(&pdev->dev, "Unable to obtain 64 bit " | |
15088 | "DMA for consistent allocations\n"); | |
15089 | goto err_out_iounmap; | |
15090 | } | |
15091 | } | |
15092 | } | |
15093 | if (err || dma_mask == DMA_BIT_MASK(32)) { | |
15094 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
15095 | if (err) { | |
15096 | dev_err(&pdev->dev, | |
15097 | "No usable DMA configuration, aborting\n"); | |
15098 | goto err_out_iounmap; | |
15099 | } | |
15100 | } | |
15101 | ||
15102 | tg3_init_bufmgr_config(tp); | |
15103 | ||
15104 | features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; | |
15105 | ||
15106 | /* 5700 B0 chips do not support checksumming correctly due | |
15107 | * to hardware bugs. | |
15108 | */ | |
15109 | if (tp->pci_chip_rev_id != CHIPREV_ID_5700_B0) { | |
15110 | features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM; | |
15111 | ||
15112 | if (tg3_flag(tp, 5755_PLUS)) | |
15113 | features |= NETIF_F_IPV6_CSUM; | |
15114 | } | |
15115 | ||
15116 | /* TSO is on by default on chips that support hardware TSO. | |
15117 | * Firmware TSO on older chips gives lower performance, so it | |
15118 | * is off by default, but can be enabled using ethtool. | |
15119 | */ | |
15120 | if ((tg3_flag(tp, HW_TSO_1) || | |
15121 | tg3_flag(tp, HW_TSO_2) || | |
15122 | tg3_flag(tp, HW_TSO_3)) && | |
15123 | (features & NETIF_F_IP_CSUM)) | |
15124 | features |= NETIF_F_TSO; | |
15125 | if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) { | |
15126 | if (features & NETIF_F_IPV6_CSUM) | |
15127 | features |= NETIF_F_TSO6; | |
15128 | if (tg3_flag(tp, HW_TSO_3) || | |
15129 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || | |
15130 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && | |
15131 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) || | |
15132 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || | |
15133 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) | |
15134 | features |= NETIF_F_TSO_ECN; | |
15135 | } | |
15136 | ||
15137 | dev->features |= features; | |
15138 | dev->vlan_features |= features; | |
15139 | ||
15140 | /* | |
15141 | * Add loopback capability only for a subset of devices that support | |
15142 | * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY | |
15143 | * loopback for the remaining devices. | |
15144 | */ | |
15145 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780 && | |
15146 | !tg3_flag(tp, CPMU_PRESENT)) | |
15147 | /* Add the loopback capability */ | |
15148 | features |= NETIF_F_LOOPBACK; | |
15149 | ||
15150 | dev->hw_features |= features; | |
15151 | ||
15152 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 && | |
15153 | !tg3_flag(tp, TSO_CAPABLE) && | |
15154 | !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) { | |
15155 | tg3_flag_set(tp, MAX_RXPEND_64); | |
15156 | tp->rx_pending = 63; | |
15157 | } | |
15158 | ||
15159 | err = tg3_get_device_address(tp); | |
15160 | if (err) { | |
15161 | dev_err(&pdev->dev, | |
15162 | "Could not obtain valid ethernet address, aborting\n"); | |
15163 | goto err_out_iounmap; | |
15164 | } | |
15165 | ||
15166 | if (tg3_flag(tp, ENABLE_APE)) { | |
15167 | tp->aperegs = pci_ioremap_bar(pdev, BAR_2); | |
15168 | if (!tp->aperegs) { | |
15169 | dev_err(&pdev->dev, | |
15170 | "Cannot map APE registers, aborting\n"); | |
15171 | err = -ENOMEM; | |
15172 | goto err_out_iounmap; | |
15173 | } | |
15174 | ||
15175 | tg3_ape_lock_init(tp); | |
15176 | ||
15177 | if (tg3_flag(tp, ENABLE_ASF)) | |
15178 | tg3_read_dash_ver(tp); | |
15179 | } | |
15180 | ||
15181 | /* | |
15182 | * Reset chip in case UNDI or EFI driver did not shutdown | |
15183 | * DMA self test will enable WDMAC and we'll see (spurious) | |
15184 | * pending DMA on the PCI bus at that point. | |
15185 | */ | |
15186 | if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) || | |
15187 | (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) { | |
15188 | tw32(MEMARB_MODE, MEMARB_MODE_ENABLE); | |
15189 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | |
15190 | } | |
15191 | ||
15192 | err = tg3_test_dma(tp); | |
15193 | if (err) { | |
15194 | dev_err(&pdev->dev, "DMA engine test failed, aborting\n"); | |
15195 | goto err_out_apeunmap; | |
15196 | } | |
15197 | ||
15198 | intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW; | |
15199 | rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW; | |
15200 | sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW; | |
15201 | for (i = 0; i < tp->irq_max; i++) { | |
15202 | struct tg3_napi *tnapi = &tp->napi[i]; | |
15203 | ||
15204 | tnapi->tp = tp; | |
15205 | tnapi->tx_pending = TG3_DEF_TX_RING_PENDING; | |
15206 | ||
15207 | tnapi->int_mbox = intmbx; | |
15208 | if (i < 4) | |
15209 | intmbx += 0x8; | |
15210 | else | |
15211 | intmbx += 0x4; | |
15212 | ||
15213 | tnapi->consmbox = rcvmbx; | |
15214 | tnapi->prodmbox = sndmbx; | |
15215 | ||
15216 | if (i) | |
15217 | tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1); | |
15218 | else | |
15219 | tnapi->coal_now = HOSTCC_MODE_NOW; | |
15220 | ||
15221 | if (!tg3_flag(tp, SUPPORT_MSIX)) | |
15222 | break; | |
15223 | ||
15224 | /* | |
15225 | * If we support MSIX, we'll be using RSS. If we're using | |
15226 | * RSS, the first vector only handles link interrupts and the | |
15227 | * remaining vectors handle rx and tx interrupts. Reuse the | |
15228 | * mailbox values for the next iteration. The values we setup | |
15229 | * above are still useful for the single vectored mode. | |
15230 | */ | |
15231 | if (!i) | |
15232 | continue; | |
15233 | ||
15234 | rcvmbx += 0x8; | |
15235 | ||
15236 | if (sndmbx & 0x4) | |
15237 | sndmbx -= 0x4; | |
15238 | else | |
15239 | sndmbx += 0xc; | |
15240 | } | |
15241 | ||
15242 | tg3_init_coal(tp); | |
15243 | ||
15244 | pci_set_drvdata(pdev, dev); | |
15245 | ||
15246 | err = register_netdev(dev); | |
15247 | if (err) { | |
15248 | dev_err(&pdev->dev, "Cannot register net device, aborting\n"); | |
15249 | goto err_out_apeunmap; | |
15250 | } | |
15251 | ||
15252 | netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n", | |
15253 | tp->board_part_number, | |
15254 | tp->pci_chip_rev_id, | |
15255 | tg3_bus_string(tp, str), | |
15256 | dev->dev_addr); | |
15257 | ||
15258 | if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { | |
15259 | struct phy_device *phydev; | |
15260 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; | |
15261 | netdev_info(dev, | |
15262 | "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n", | |
15263 | phydev->drv->name, dev_name(&phydev->dev)); | |
15264 | } else { | |
15265 | char *ethtype; | |
15266 | ||
15267 | if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) | |
15268 | ethtype = "10/100Base-TX"; | |
15269 | else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) | |
15270 | ethtype = "1000Base-SX"; | |
15271 | else | |
15272 | ethtype = "10/100/1000Base-T"; | |
15273 | ||
15274 | netdev_info(dev, "attached PHY is %s (%s Ethernet) " | |
15275 | "(WireSpeed[%d], EEE[%d])\n", | |
15276 | tg3_phy_string(tp), ethtype, | |
15277 | (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0, | |
15278 | (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0); | |
15279 | } | |
15280 | ||
15281 | netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n", | |
15282 | (dev->features & NETIF_F_RXCSUM) != 0, | |
15283 | tg3_flag(tp, USE_LINKCHG_REG) != 0, | |
15284 | (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0, | |
15285 | tg3_flag(tp, ENABLE_ASF) != 0, | |
15286 | tg3_flag(tp, TSO_CAPABLE) != 0); | |
15287 | netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n", | |
15288 | tp->dma_rwctrl, | |
15289 | pdev->dma_mask == DMA_BIT_MASK(32) ? 32 : | |
15290 | ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64); | |
15291 | ||
15292 | pci_save_state(pdev); | |
15293 | ||
15294 | return 0; | |
15295 | ||
15296 | err_out_apeunmap: | |
15297 | if (tp->aperegs) { | |
15298 | iounmap(tp->aperegs); | |
15299 | tp->aperegs = NULL; | |
15300 | } | |
15301 | ||
15302 | err_out_iounmap: | |
15303 | if (tp->regs) { | |
15304 | iounmap(tp->regs); | |
15305 | tp->regs = NULL; | |
15306 | } | |
15307 | ||
15308 | err_out_free_dev: | |
15309 | free_netdev(dev); | |
15310 | ||
15311 | err_out_free_res: | |
15312 | pci_release_regions(pdev); | |
15313 | ||
15314 | err_out_disable_pdev: | |
15315 | pci_disable_device(pdev); | |
15316 | pci_set_drvdata(pdev, NULL); | |
15317 | return err; | |
15318 | } | |
15319 | ||
15320 | static void __devexit tg3_remove_one(struct pci_dev *pdev) | |
15321 | { | |
15322 | struct net_device *dev = pci_get_drvdata(pdev); | |
15323 | ||
15324 | if (dev) { | |
15325 | struct tg3 *tp = netdev_priv(dev); | |
15326 | ||
15327 | if (tp->fw) | |
15328 | release_firmware(tp->fw); | |
15329 | ||
15330 | cancel_work_sync(&tp->reset_task); | |
15331 | ||
15332 | if (!tg3_flag(tp, USE_PHYLIB)) { | |
15333 | tg3_phy_fini(tp); | |
15334 | tg3_mdio_fini(tp); | |
15335 | } | |
15336 | ||
15337 | unregister_netdev(dev); | |
15338 | if (tp->aperegs) { | |
15339 | iounmap(tp->aperegs); | |
15340 | tp->aperegs = NULL; | |
15341 | } | |
15342 | if (tp->regs) { | |
15343 | iounmap(tp->regs); | |
15344 | tp->regs = NULL; | |
15345 | } | |
15346 | free_netdev(dev); | |
15347 | pci_release_regions(pdev); | |
15348 | pci_disable_device(pdev); | |
15349 | pci_set_drvdata(pdev, NULL); | |
15350 | } | |
15351 | } | |
15352 | ||
15353 | #ifdef CONFIG_PM_SLEEP | |
15354 | static int tg3_suspend(struct device *device) | |
15355 | { | |
15356 | struct pci_dev *pdev = to_pci_dev(device); | |
15357 | struct net_device *dev = pci_get_drvdata(pdev); | |
15358 | struct tg3 *tp = netdev_priv(dev); | |
15359 | int err; | |
15360 | ||
15361 | if (!netif_running(dev)) | |
15362 | return 0; | |
15363 | ||
15364 | flush_work_sync(&tp->reset_task); | |
15365 | tg3_phy_stop(tp); | |
15366 | tg3_netif_stop(tp); | |
15367 | ||
15368 | del_timer_sync(&tp->timer); | |
15369 | ||
15370 | tg3_full_lock(tp, 1); | |
15371 | tg3_disable_ints(tp); | |
15372 | tg3_full_unlock(tp); | |
15373 | ||
15374 | netif_device_detach(dev); | |
15375 | ||
15376 | tg3_full_lock(tp, 0); | |
15377 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | |
15378 | tg3_flag_clear(tp, INIT_COMPLETE); | |
15379 | tg3_full_unlock(tp); | |
15380 | ||
15381 | err = tg3_power_down_prepare(tp); | |
15382 | if (err) { | |
15383 | int err2; | |
15384 | ||
15385 | tg3_full_lock(tp, 0); | |
15386 | ||
15387 | tg3_flag_set(tp, INIT_COMPLETE); | |
15388 | err2 = tg3_restart_hw(tp, 1); | |
15389 | if (err2) | |
15390 | goto out; | |
15391 | ||
15392 | tp->timer.expires = jiffies + tp->timer_offset; | |
15393 | add_timer(&tp->timer); | |
15394 | ||
15395 | netif_device_attach(dev); | |
15396 | tg3_netif_start(tp); | |
15397 | ||
15398 | out: | |
15399 | tg3_full_unlock(tp); | |
15400 | ||
15401 | if (!err2) | |
15402 | tg3_phy_start(tp); | |
15403 | } | |
15404 | ||
15405 | return err; | |
15406 | } | |
15407 | ||
15408 | static int tg3_resume(struct device *device) | |
15409 | { | |
15410 | struct pci_dev *pdev = to_pci_dev(device); | |
15411 | struct net_device *dev = pci_get_drvdata(pdev); | |
15412 | struct tg3 *tp = netdev_priv(dev); | |
15413 | int err; | |
15414 | ||
15415 | if (!netif_running(dev)) | |
15416 | return 0; | |
15417 | ||
15418 | netif_device_attach(dev); | |
15419 | ||
15420 | tg3_full_lock(tp, 0); | |
15421 | ||
15422 | tg3_flag_set(tp, INIT_COMPLETE); | |
15423 | err = tg3_restart_hw(tp, 1); | |
15424 | if (err) | |
15425 | goto out; | |
15426 | ||
15427 | tp->timer.expires = jiffies + tp->timer_offset; | |
15428 | add_timer(&tp->timer); | |
15429 | ||
15430 | tg3_netif_start(tp); | |
15431 | ||
15432 | out: | |
15433 | tg3_full_unlock(tp); | |
15434 | ||
15435 | if (!err) | |
15436 | tg3_phy_start(tp); | |
15437 | ||
15438 | return err; | |
15439 | } | |
15440 | ||
15441 | static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume); | |
15442 | #define TG3_PM_OPS (&tg3_pm_ops) | |
15443 | ||
15444 | #else | |
15445 | ||
15446 | #define TG3_PM_OPS NULL | |
15447 | ||
15448 | #endif /* CONFIG_PM_SLEEP */ | |
15449 | ||
15450 | /** | |
15451 | * tg3_io_error_detected - called when PCI error is detected | |
15452 | * @pdev: Pointer to PCI device | |
15453 | * @state: The current pci connection state | |
15454 | * | |
15455 | * This function is called after a PCI bus error affecting | |
15456 | * this device has been detected. | |
15457 | */ | |
15458 | static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev, | |
15459 | pci_channel_state_t state) | |
15460 | { | |
15461 | struct net_device *netdev = pci_get_drvdata(pdev); | |
15462 | struct tg3 *tp = netdev_priv(netdev); | |
15463 | pci_ers_result_t err = PCI_ERS_RESULT_NEED_RESET; | |
15464 | ||
15465 | netdev_info(netdev, "PCI I/O error detected\n"); | |
15466 | ||
15467 | rtnl_lock(); | |
15468 | ||
15469 | if (!netif_running(netdev)) | |
15470 | goto done; | |
15471 | ||
15472 | tg3_phy_stop(tp); | |
15473 | ||
15474 | tg3_netif_stop(tp); | |
15475 | ||
15476 | del_timer_sync(&tp->timer); | |
15477 | tg3_flag_clear(tp, RESTART_TIMER); | |
15478 | ||
15479 | /* Want to make sure that the reset task doesn't run */ | |
15480 | cancel_work_sync(&tp->reset_task); | |
15481 | tg3_flag_clear(tp, TX_RECOVERY_PENDING); | |
15482 | tg3_flag_clear(tp, RESTART_TIMER); | |
15483 | ||
15484 | netif_device_detach(netdev); | |
15485 | ||
15486 | /* Clean up software state, even if MMIO is blocked */ | |
15487 | tg3_full_lock(tp, 0); | |
15488 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 0); | |
15489 | tg3_full_unlock(tp); | |
15490 | ||
15491 | done: | |
15492 | if (state == pci_channel_io_perm_failure) | |
15493 | err = PCI_ERS_RESULT_DISCONNECT; | |
15494 | else | |
15495 | pci_disable_device(pdev); | |
15496 | ||
15497 | rtnl_unlock(); | |
15498 | ||
15499 | return err; | |
15500 | } | |
15501 | ||
15502 | /** | |
15503 | * tg3_io_slot_reset - called after the pci bus has been reset. | |
15504 | * @pdev: Pointer to PCI device | |
15505 | * | |
15506 | * Restart the card from scratch, as if from a cold-boot. | |
15507 | * At this point, the card has exprienced a hard reset, | |
15508 | * followed by fixups by BIOS, and has its config space | |
15509 | * set up identically to what it was at cold boot. | |
15510 | */ | |
15511 | static pci_ers_result_t tg3_io_slot_reset(struct pci_dev *pdev) | |
15512 | { | |
15513 | struct net_device *netdev = pci_get_drvdata(pdev); | |
15514 | struct tg3 *tp = netdev_priv(netdev); | |
15515 | pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT; | |
15516 | int err; | |
15517 | ||
15518 | rtnl_lock(); | |
15519 | ||
15520 | if (pci_enable_device(pdev)) { | |
15521 | netdev_err(netdev, "Cannot re-enable PCI device after reset.\n"); | |
15522 | goto done; | |
15523 | } | |
15524 | ||
15525 | pci_set_master(pdev); | |
15526 | pci_restore_state(pdev); | |
15527 | pci_save_state(pdev); | |
15528 | ||
15529 | if (!netif_running(netdev)) { | |
15530 | rc = PCI_ERS_RESULT_RECOVERED; | |
15531 | goto done; | |
15532 | } | |
15533 | ||
15534 | err = tg3_power_up(tp); | |
15535 | if (err) { | |
15536 | netdev_err(netdev, "Failed to restore register access.\n"); | |
15537 | goto done; | |
15538 | } | |
15539 | ||
15540 | rc = PCI_ERS_RESULT_RECOVERED; | |
15541 | ||
15542 | done: | |
15543 | rtnl_unlock(); | |
15544 | ||
15545 | return rc; | |
15546 | } | |
15547 | ||
15548 | /** | |
15549 | * tg3_io_resume - called when traffic can start flowing again. | |
15550 | * @pdev: Pointer to PCI device | |
15551 | * | |
15552 | * This callback is called when the error recovery driver tells | |
15553 | * us that its OK to resume normal operation. | |
15554 | */ | |
15555 | static void tg3_io_resume(struct pci_dev *pdev) | |
15556 | { | |
15557 | struct net_device *netdev = pci_get_drvdata(pdev); | |
15558 | struct tg3 *tp = netdev_priv(netdev); | |
15559 | int err; | |
15560 | ||
15561 | rtnl_lock(); | |
15562 | ||
15563 | if (!netif_running(netdev)) | |
15564 | goto done; | |
15565 | ||
15566 | tg3_full_lock(tp, 0); | |
15567 | tg3_flag_set(tp, INIT_COMPLETE); | |
15568 | err = tg3_restart_hw(tp, 1); | |
15569 | tg3_full_unlock(tp); | |
15570 | if (err) { | |
15571 | netdev_err(netdev, "Cannot restart hardware after reset.\n"); | |
15572 | goto done; | |
15573 | } | |
15574 | ||
15575 | netif_device_attach(netdev); | |
15576 | ||
15577 | tp->timer.expires = jiffies + tp->timer_offset; | |
15578 | add_timer(&tp->timer); | |
15579 | ||
15580 | tg3_netif_start(tp); | |
15581 | ||
15582 | tg3_phy_start(tp); | |
15583 | ||
15584 | done: | |
15585 | rtnl_unlock(); | |
15586 | } | |
15587 | ||
15588 | static struct pci_error_handlers tg3_err_handler = { | |
15589 | .error_detected = tg3_io_error_detected, | |
15590 | .slot_reset = tg3_io_slot_reset, | |
15591 | .resume = tg3_io_resume | |
15592 | }; | |
15593 | ||
15594 | static struct pci_driver tg3_driver = { | |
15595 | .name = DRV_MODULE_NAME, | |
15596 | .id_table = tg3_pci_tbl, | |
15597 | .probe = tg3_init_one, | |
15598 | .remove = __devexit_p(tg3_remove_one), | |
15599 | .err_handler = &tg3_err_handler, | |
15600 | .driver.pm = TG3_PM_OPS, | |
15601 | }; | |
15602 | ||
15603 | static int __init tg3_init(void) | |
15604 | { | |
15605 | return pci_register_driver(&tg3_driver); | |
15606 | } | |
15607 | ||
15608 | static void __exit tg3_cleanup(void) | |
15609 | { | |
15610 | pci_unregister_driver(&tg3_driver); | |
15611 | } | |
15612 | ||
15613 | module_init(tg3_init); | |
15614 | module_exit(tg3_cleanup); |