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1 | /****************************************************************************** | |
2 | * | |
3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | * redistributing this file, you may do so under either license. | |
5 | * | |
6 | * GPL LICENSE SUMMARY | |
7 | * | |
8 | * Copyright(c) 2007 - 2013 Intel Corporation. All rights reserved. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of version 2 of the GNU General Public License as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but | |
15 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
22 | * USA | |
23 | * | |
24 | * The full GNU General Public License is included in this distribution | |
25 | * in the file called COPYING. | |
26 | * | |
27 | * Contact Information: | |
28 | * Intel Linux Wireless <ilw@linux.intel.com> | |
29 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
30 | * | |
31 | * BSD LICENSE | |
32 | * | |
33 | * Copyright(c) 2005 - 2013 Intel Corporation. All rights reserved. | |
34 | * All rights reserved. | |
35 | * | |
36 | * Redistribution and use in source and binary forms, with or without | |
37 | * modification, are permitted provided that the following conditions | |
38 | * are met: | |
39 | * | |
40 | * * Redistributions of source code must retain the above copyright | |
41 | * notice, this list of conditions and the following disclaimer. | |
42 | * * Redistributions in binary form must reproduce the above copyright | |
43 | * notice, this list of conditions and the following disclaimer in | |
44 | * the documentation and/or other materials provided with the | |
45 | * distribution. | |
46 | * * Neither the name Intel Corporation nor the names of its | |
47 | * contributors may be used to endorse or promote products derived | |
48 | * from this software without specific prior written permission. | |
49 | * | |
50 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
51 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
52 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
53 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
54 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
55 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
56 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
57 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
58 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
59 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
60 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
61 | * | |
62 | *****************************************************************************/ | |
63 | #include <linux/pci.h> | |
64 | #include <linux/pci-aspm.h> | |
65 | #include <linux/interrupt.h> | |
66 | #include <linux/debugfs.h> | |
67 | #include <linux/sched.h> | |
68 | #include <linux/bitops.h> | |
69 | #include <linux/gfp.h> | |
70 | ||
71 | #include "iwl-drv.h" | |
72 | #include "iwl-trans.h" | |
73 | #include "iwl-csr.h" | |
74 | #include "iwl-prph.h" | |
75 | #include "iwl-agn-hw.h" | |
76 | #include "internal.h" | |
77 | ||
78 | static void __iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, | |
79 | u32 reg, u32 mask, u32 value) | |
80 | { | |
81 | u32 v; | |
82 | ||
83 | #ifdef CONFIG_IWLWIFI_DEBUG | |
84 | WARN_ON_ONCE(value & ~mask); | |
85 | #endif | |
86 | ||
87 | v = iwl_read32(trans, reg); | |
88 | v &= ~mask; | |
89 | v |= value; | |
90 | iwl_write32(trans, reg, v); | |
91 | } | |
92 | ||
93 | static inline void __iwl_trans_pcie_clear_bit(struct iwl_trans *trans, | |
94 | u32 reg, u32 mask) | |
95 | { | |
96 | __iwl_trans_pcie_set_bits_mask(trans, reg, mask, 0); | |
97 | } | |
98 | ||
99 | static inline void __iwl_trans_pcie_set_bit(struct iwl_trans *trans, | |
100 | u32 reg, u32 mask) | |
101 | { | |
102 | __iwl_trans_pcie_set_bits_mask(trans, reg, mask, mask); | |
103 | } | |
104 | ||
105 | static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux) | |
106 | { | |
107 | if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) | |
108 | iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, | |
109 | APMG_PS_CTRL_VAL_PWR_SRC_VAUX, | |
110 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
111 | else | |
112 | iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, | |
113 | APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, | |
114 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
115 | } | |
116 | ||
117 | /* PCI registers */ | |
118 | #define PCI_CFG_RETRY_TIMEOUT 0x041 | |
119 | ||
120 | static void iwl_pcie_apm_config(struct iwl_trans *trans) | |
121 | { | |
122 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
123 | u16 lctl; | |
124 | ||
125 | /* | |
126 | * HW bug W/A for instability in PCIe bus L0S->L1 transition. | |
127 | * Check if BIOS (or OS) enabled L1-ASPM on this device. | |
128 | * If so (likely), disable L0S, so device moves directly L0->L1; | |
129 | * costs negligible amount of power savings. | |
130 | * If not (unlikely), enable L0S, so there is at least some | |
131 | * power savings, even without L1. | |
132 | */ | |
133 | pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); | |
134 | if (lctl & PCI_EXP_LNKCTL_ASPM_L1) { | |
135 | /* L1-ASPM enabled; disable(!) L0S */ | |
136 | iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); | |
137 | dev_info(trans->dev, "L1 Enabled; Disabling L0S\n"); | |
138 | } else { | |
139 | /* L1-ASPM disabled; enable(!) L0S */ | |
140 | iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); | |
141 | dev_info(trans->dev, "L1 Disabled; Enabling L0S\n"); | |
142 | } | |
143 | trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); | |
144 | } | |
145 | ||
146 | /* | |
147 | * Start up NIC's basic functionality after it has been reset | |
148 | * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) | |
149 | * NOTE: This does not load uCode nor start the embedded processor | |
150 | */ | |
151 | static int iwl_pcie_apm_init(struct iwl_trans *trans) | |
152 | { | |
153 | int ret = 0; | |
154 | IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); | |
155 | ||
156 | /* | |
157 | * Use "set_bit" below rather than "write", to preserve any hardware | |
158 | * bits already set by default after reset. | |
159 | */ | |
160 | ||
161 | /* Disable L0S exit timer (platform NMI Work/Around) */ | |
162 | iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, | |
163 | CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); | |
164 | ||
165 | /* | |
166 | * Disable L0s without affecting L1; | |
167 | * don't wait for ICH L0s (ICH bug W/A) | |
168 | */ | |
169 | iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, | |
170 | CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); | |
171 | ||
172 | /* Set FH wait threshold to maximum (HW error during stress W/A) */ | |
173 | iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); | |
174 | ||
175 | /* | |
176 | * Enable HAP INTA (interrupt from management bus) to | |
177 | * wake device's PCI Express link L1a -> L0s | |
178 | */ | |
179 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, | |
180 | CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); | |
181 | ||
182 | iwl_pcie_apm_config(trans); | |
183 | ||
184 | /* Configure analog phase-lock-loop before activating to D0A */ | |
185 | if (trans->cfg->base_params->pll_cfg_val) | |
186 | iwl_set_bit(trans, CSR_ANA_PLL_CFG, | |
187 | trans->cfg->base_params->pll_cfg_val); | |
188 | ||
189 | /* | |
190 | * Set "initialization complete" bit to move adapter from | |
191 | * D0U* --> D0A* (powered-up active) state. | |
192 | */ | |
193 | iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
194 | ||
195 | /* | |
196 | * Wait for clock stabilization; once stabilized, access to | |
197 | * device-internal resources is supported, e.g. iwl_write_prph() | |
198 | * and accesses to uCode SRAM. | |
199 | */ | |
200 | ret = iwl_poll_bit(trans, CSR_GP_CNTRL, | |
201 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, | |
202 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); | |
203 | if (ret < 0) { | |
204 | IWL_DEBUG_INFO(trans, "Failed to init the card\n"); | |
205 | goto out; | |
206 | } | |
207 | ||
208 | /* | |
209 | * Enable DMA clock and wait for it to stabilize. | |
210 | * | |
211 | * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits | |
212 | * do not disable clocks. This preserves any hardware bits already | |
213 | * set by default in "CLK_CTRL_REG" after reset. | |
214 | */ | |
215 | iwl_write_prph(trans, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT); | |
216 | udelay(20); | |
217 | ||
218 | /* Disable L1-Active */ | |
219 | iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, | |
220 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); | |
221 | ||
222 | /* Clear the interrupt in APMG if the NIC is in RFKILL */ | |
223 | iwl_write_prph(trans, APMG_RTC_INT_STT_REG, APMG_RTC_INT_STT_RFKILL); | |
224 | ||
225 | set_bit(STATUS_DEVICE_ENABLED, &trans->status); | |
226 | ||
227 | out: | |
228 | return ret; | |
229 | } | |
230 | ||
231 | static int iwl_pcie_apm_stop_master(struct iwl_trans *trans) | |
232 | { | |
233 | int ret = 0; | |
234 | ||
235 | /* stop device's busmaster DMA activity */ | |
236 | iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); | |
237 | ||
238 | ret = iwl_poll_bit(trans, CSR_RESET, | |
239 | CSR_RESET_REG_FLAG_MASTER_DISABLED, | |
240 | CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); | |
241 | if (ret) | |
242 | IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); | |
243 | ||
244 | IWL_DEBUG_INFO(trans, "stop master\n"); | |
245 | ||
246 | return ret; | |
247 | } | |
248 | ||
249 | static void iwl_pcie_apm_stop(struct iwl_trans *trans) | |
250 | { | |
251 | IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); | |
252 | ||
253 | clear_bit(STATUS_DEVICE_ENABLED, &trans->status); | |
254 | ||
255 | /* Stop device's DMA activity */ | |
256 | iwl_pcie_apm_stop_master(trans); | |
257 | ||
258 | /* Reset the entire device */ | |
259 | iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); | |
260 | ||
261 | udelay(10); | |
262 | ||
263 | /* | |
264 | * Clear "initialization complete" bit to move adapter from | |
265 | * D0A* (powered-up Active) --> D0U* (Uninitialized) state. | |
266 | */ | |
267 | iwl_clear_bit(trans, CSR_GP_CNTRL, | |
268 | CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
269 | } | |
270 | ||
271 | static int iwl_pcie_nic_init(struct iwl_trans *trans) | |
272 | { | |
273 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
274 | unsigned long flags; | |
275 | ||
276 | /* nic_init */ | |
277 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); | |
278 | iwl_pcie_apm_init(trans); | |
279 | ||
280 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); | |
281 | ||
282 | iwl_pcie_set_pwr(trans, false); | |
283 | ||
284 | iwl_op_mode_nic_config(trans->op_mode); | |
285 | ||
286 | /* Allocate the RX queue, or reset if it is already allocated */ | |
287 | iwl_pcie_rx_init(trans); | |
288 | ||
289 | /* Allocate or reset and init all Tx and Command queues */ | |
290 | if (iwl_pcie_tx_init(trans)) | |
291 | return -ENOMEM; | |
292 | ||
293 | if (trans->cfg->base_params->shadow_reg_enable) { | |
294 | /* enable shadow regs in HW */ | |
295 | iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); | |
296 | IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); | |
297 | } | |
298 | ||
299 | return 0; | |
300 | } | |
301 | ||
302 | #define HW_READY_TIMEOUT (50) | |
303 | ||
304 | /* Note: returns poll_bit return value, which is >= 0 if success */ | |
305 | static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) | |
306 | { | |
307 | int ret; | |
308 | ||
309 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, | |
310 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); | |
311 | ||
312 | /* See if we got it */ | |
313 | ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, | |
314 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, | |
315 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, | |
316 | HW_READY_TIMEOUT); | |
317 | ||
318 | IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); | |
319 | return ret; | |
320 | } | |
321 | ||
322 | /* Note: returns standard 0/-ERROR code */ | |
323 | static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) | |
324 | { | |
325 | int ret; | |
326 | int t = 0; | |
327 | ||
328 | IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); | |
329 | ||
330 | ret = iwl_pcie_set_hw_ready(trans); | |
331 | /* If the card is ready, exit 0 */ | |
332 | if (ret >= 0) | |
333 | return 0; | |
334 | ||
335 | /* If HW is not ready, prepare the conditions to check again */ | |
336 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, | |
337 | CSR_HW_IF_CONFIG_REG_PREPARE); | |
338 | ||
339 | do { | |
340 | ret = iwl_pcie_set_hw_ready(trans); | |
341 | if (ret >= 0) | |
342 | return 0; | |
343 | ||
344 | usleep_range(200, 1000); | |
345 | t += 200; | |
346 | } while (t < 150000); | |
347 | ||
348 | return ret; | |
349 | } | |
350 | ||
351 | /* | |
352 | * ucode | |
353 | */ | |
354 | static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr, | |
355 | dma_addr_t phy_addr, u32 byte_cnt) | |
356 | { | |
357 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
358 | int ret; | |
359 | ||
360 | trans_pcie->ucode_write_complete = false; | |
361 | ||
362 | iwl_write_direct32(trans, | |
363 | FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), | |
364 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); | |
365 | ||
366 | iwl_write_direct32(trans, | |
367 | FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), | |
368 | dst_addr); | |
369 | ||
370 | iwl_write_direct32(trans, | |
371 | FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), | |
372 | phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); | |
373 | ||
374 | iwl_write_direct32(trans, | |
375 | FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), | |
376 | (iwl_get_dma_hi_addr(phy_addr) | |
377 | << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); | |
378 | ||
379 | iwl_write_direct32(trans, | |
380 | FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), | |
381 | 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM | | |
382 | 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX | | |
383 | FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); | |
384 | ||
385 | iwl_write_direct32(trans, | |
386 | FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), | |
387 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | | |
388 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | | |
389 | FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); | |
390 | ||
391 | ret = wait_event_timeout(trans_pcie->ucode_write_waitq, | |
392 | trans_pcie->ucode_write_complete, 5 * HZ); | |
393 | if (!ret) { | |
394 | IWL_ERR(trans, "Failed to load firmware chunk!\n"); | |
395 | return -ETIMEDOUT; | |
396 | } | |
397 | ||
398 | return 0; | |
399 | } | |
400 | ||
401 | static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num, | |
402 | const struct fw_desc *section) | |
403 | { | |
404 | u8 *v_addr; | |
405 | dma_addr_t p_addr; | |
406 | u32 offset, chunk_sz = section->len; | |
407 | int ret = 0; | |
408 | ||
409 | IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", | |
410 | section_num); | |
411 | ||
412 | v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr, | |
413 | GFP_KERNEL | __GFP_NOWARN); | |
414 | if (!v_addr) { | |
415 | IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n"); | |
416 | chunk_sz = PAGE_SIZE; | |
417 | v_addr = dma_alloc_coherent(trans->dev, chunk_sz, | |
418 | &p_addr, GFP_KERNEL); | |
419 | if (!v_addr) | |
420 | return -ENOMEM; | |
421 | } | |
422 | ||
423 | for (offset = 0; offset < section->len; offset += chunk_sz) { | |
424 | u32 copy_size; | |
425 | ||
426 | copy_size = min_t(u32, chunk_sz, section->len - offset); | |
427 | ||
428 | memcpy(v_addr, (u8 *)section->data + offset, copy_size); | |
429 | ret = iwl_pcie_load_firmware_chunk(trans, | |
430 | section->offset + offset, | |
431 | p_addr, copy_size); | |
432 | if (ret) { | |
433 | IWL_ERR(trans, | |
434 | "Could not load the [%d] uCode section\n", | |
435 | section_num); | |
436 | break; | |
437 | } | |
438 | } | |
439 | ||
440 | dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr); | |
441 | return ret; | |
442 | } | |
443 | ||
444 | static int iwl_pcie_secure_set(struct iwl_trans *trans, int cpu) | |
445 | { | |
446 | int shift_param; | |
447 | u32 address; | |
448 | int ret = 0; | |
449 | ||
450 | if (cpu == 1) { | |
451 | shift_param = 0; | |
452 | address = CSR_SECURE_BOOT_CPU1_STATUS_ADDR; | |
453 | } else { | |
454 | shift_param = 16; | |
455 | address = CSR_SECURE_BOOT_CPU2_STATUS_ADDR; | |
456 | } | |
457 | ||
458 | /* set CPU to started */ | |
459 | iwl_trans_set_bits_mask(trans, | |
460 | CSR_UCODE_LOAD_STATUS_ADDR, | |
461 | CSR_CPU_STATUS_LOADING_STARTED << shift_param, | |
462 | 1); | |
463 | ||
464 | /* set last complete descriptor number */ | |
465 | iwl_trans_set_bits_mask(trans, | |
466 | CSR_UCODE_LOAD_STATUS_ADDR, | |
467 | CSR_CPU_STATUS_NUM_OF_LAST_COMPLETED | |
468 | << shift_param, | |
469 | 1); | |
470 | ||
471 | /* set last loaded block */ | |
472 | iwl_trans_set_bits_mask(trans, | |
473 | CSR_UCODE_LOAD_STATUS_ADDR, | |
474 | CSR_CPU_STATUS_NUM_OF_LAST_LOADED_BLOCK | |
475 | << shift_param, | |
476 | 1); | |
477 | ||
478 | /* image loading complete */ | |
479 | iwl_trans_set_bits_mask(trans, | |
480 | CSR_UCODE_LOAD_STATUS_ADDR, | |
481 | CSR_CPU_STATUS_LOADING_COMPLETED | |
482 | << shift_param, | |
483 | 1); | |
484 | ||
485 | /* set FH_TCSR_0_REG */ | |
486 | iwl_trans_set_bits_mask(trans, FH_TCSR_0_REG0, 0x00400000, 1); | |
487 | ||
488 | /* verify image verification started */ | |
489 | ret = iwl_poll_bit(trans, address, | |
490 | CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS, | |
491 | CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS, | |
492 | CSR_SECURE_TIME_OUT); | |
493 | if (ret < 0) { | |
494 | IWL_ERR(trans, "secure boot process didn't start\n"); | |
495 | return ret; | |
496 | } | |
497 | ||
498 | /* wait for image verification to complete */ | |
499 | ret = iwl_poll_bit(trans, address, | |
500 | CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED, | |
501 | CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED, | |
502 | CSR_SECURE_TIME_OUT); | |
503 | ||
504 | if (ret < 0) { | |
505 | IWL_ERR(trans, "Time out on secure boot process\n"); | |
506 | return ret; | |
507 | } | |
508 | ||
509 | return 0; | |
510 | } | |
511 | ||
512 | static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, | |
513 | const struct fw_img *image) | |
514 | { | |
515 | int i, ret = 0; | |
516 | ||
517 | IWL_DEBUG_FW(trans, | |
518 | "working with %s image\n", | |
519 | image->is_secure ? "Secured" : "Non Secured"); | |
520 | IWL_DEBUG_FW(trans, | |
521 | "working with %s CPU\n", | |
522 | image->is_dual_cpus ? "Dual" : "Single"); | |
523 | ||
524 | /* configure the ucode to be ready to get the secured image */ | |
525 | if (image->is_secure) { | |
526 | /* set secure boot inspector addresses */ | |
527 | iwl_write32(trans, CSR_SECURE_INSPECTOR_CODE_ADDR, 0); | |
528 | iwl_write32(trans, CSR_SECURE_INSPECTOR_DATA_ADDR, 0); | |
529 | ||
530 | /* release CPU1 reset if secure inspector image burned in OTP */ | |
531 | iwl_write32(trans, CSR_RESET, 0); | |
532 | } | |
533 | ||
534 | /* load to FW the binary sections of CPU1 */ | |
535 | IWL_DEBUG_INFO(trans, "Loading CPU1\n"); | |
536 | for (i = 0; | |
537 | i < IWL_UCODE_FIRST_SECTION_OF_SECOND_CPU; | |
538 | i++) { | |
539 | if (!image->sec[i].data) | |
540 | break; | |
541 | ret = iwl_pcie_load_section(trans, i, &image->sec[i]); | |
542 | if (ret) | |
543 | return ret; | |
544 | } | |
545 | ||
546 | /* configure the ucode to start secure process on CPU1 */ | |
547 | if (image->is_secure) { | |
548 | /* config CPU1 to start secure protocol */ | |
549 | ret = iwl_pcie_secure_set(trans, 1); | |
550 | if (ret) | |
551 | return ret; | |
552 | } else { | |
553 | /* Remove all resets to allow NIC to operate */ | |
554 | iwl_write32(trans, CSR_RESET, 0); | |
555 | } | |
556 | ||
557 | if (image->is_dual_cpus) { | |
558 | /* load to FW the binary sections of CPU2 */ | |
559 | IWL_DEBUG_INFO(trans, "working w/ DUAL CPUs - Loading CPU2\n"); | |
560 | for (i = IWL_UCODE_FIRST_SECTION_OF_SECOND_CPU; | |
561 | i < IWL_UCODE_SECTION_MAX; i++) { | |
562 | if (!image->sec[i].data) | |
563 | break; | |
564 | ret = iwl_pcie_load_section(trans, i, &image->sec[i]); | |
565 | if (ret) | |
566 | return ret; | |
567 | } | |
568 | ||
569 | if (image->is_secure) { | |
570 | /* set CPU2 for secure protocol */ | |
571 | ret = iwl_pcie_secure_set(trans, 2); | |
572 | if (ret) | |
573 | return ret; | |
574 | } | |
575 | } | |
576 | ||
577 | return 0; | |
578 | } | |
579 | ||
580 | static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, | |
581 | const struct fw_img *fw, bool run_in_rfkill) | |
582 | { | |
583 | int ret; | |
584 | bool hw_rfkill; | |
585 | ||
586 | /* This may fail if AMT took ownership of the device */ | |
587 | if (iwl_pcie_prepare_card_hw(trans)) { | |
588 | IWL_WARN(trans, "Exit HW not ready\n"); | |
589 | return -EIO; | |
590 | } | |
591 | ||
592 | iwl_enable_rfkill_int(trans); | |
593 | ||
594 | /* If platform's RF_KILL switch is NOT set to KILL */ | |
595 | hw_rfkill = iwl_is_rfkill_set(trans); | |
596 | if (hw_rfkill) | |
597 | set_bit(STATUS_RFKILL, &trans->status); | |
598 | else | |
599 | clear_bit(STATUS_RFKILL, &trans->status); | |
600 | iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill); | |
601 | if (hw_rfkill && !run_in_rfkill) | |
602 | return -ERFKILL; | |
603 | ||
604 | iwl_write32(trans, CSR_INT, 0xFFFFFFFF); | |
605 | ||
606 | ret = iwl_pcie_nic_init(trans); | |
607 | if (ret) { | |
608 | IWL_ERR(trans, "Unable to init nic\n"); | |
609 | return ret; | |
610 | } | |
611 | ||
612 | /* make sure rfkill handshake bits are cleared */ | |
613 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
614 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, | |
615 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); | |
616 | ||
617 | /* clear (again), then enable host interrupts */ | |
618 | iwl_write32(trans, CSR_INT, 0xFFFFFFFF); | |
619 | iwl_enable_interrupts(trans); | |
620 | ||
621 | /* really make sure rfkill handshake bits are cleared */ | |
622 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
623 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
624 | ||
625 | /* Load the given image to the HW */ | |
626 | return iwl_pcie_load_given_ucode(trans, fw); | |
627 | } | |
628 | ||
629 | static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr) | |
630 | { | |
631 | iwl_pcie_reset_ict(trans); | |
632 | iwl_pcie_tx_start(trans, scd_addr); | |
633 | } | |
634 | ||
635 | static void iwl_trans_pcie_stop_device(struct iwl_trans *trans) | |
636 | { | |
637 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
638 | unsigned long flags; | |
639 | bool hw_rfkill; | |
640 | ||
641 | /* tell the device to stop sending interrupts */ | |
642 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); | |
643 | iwl_disable_interrupts(trans); | |
644 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); | |
645 | ||
646 | /* device going down, Stop using ICT table */ | |
647 | iwl_pcie_disable_ict(trans); | |
648 | ||
649 | /* | |
650 | * If a HW restart happens during firmware loading, | |
651 | * then the firmware loading might call this function | |
652 | * and later it might be called again due to the | |
653 | * restart. So don't process again if the device is | |
654 | * already dead. | |
655 | */ | |
656 | if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) { | |
657 | iwl_pcie_tx_stop(trans); | |
658 | iwl_pcie_rx_stop(trans); | |
659 | ||
660 | /* Power-down device's busmaster DMA clocks */ | |
661 | iwl_write_prph(trans, APMG_CLK_DIS_REG, | |
662 | APMG_CLK_VAL_DMA_CLK_RQT); | |
663 | udelay(5); | |
664 | } | |
665 | ||
666 | /* Make sure (redundant) we've released our request to stay awake */ | |
667 | iwl_clear_bit(trans, CSR_GP_CNTRL, | |
668 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
669 | ||
670 | /* Stop the device, and put it in low power state */ | |
671 | iwl_pcie_apm_stop(trans); | |
672 | ||
673 | /* Upon stop, the APM issues an interrupt if HW RF kill is set. | |
674 | * Clean again the interrupt here | |
675 | */ | |
676 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); | |
677 | iwl_disable_interrupts(trans); | |
678 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); | |
679 | ||
680 | /* stop and reset the on-board processor */ | |
681 | iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); | |
682 | ||
683 | /* clear all status bits */ | |
684 | clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); | |
685 | clear_bit(STATUS_INT_ENABLED, &trans->status); | |
686 | clear_bit(STATUS_DEVICE_ENABLED, &trans->status); | |
687 | clear_bit(STATUS_TPOWER_PMI, &trans->status); | |
688 | clear_bit(STATUS_RFKILL, &trans->status); | |
689 | ||
690 | /* | |
691 | * Even if we stop the HW, we still want the RF kill | |
692 | * interrupt | |
693 | */ | |
694 | iwl_enable_rfkill_int(trans); | |
695 | ||
696 | /* | |
697 | * Check again since the RF kill state may have changed while | |
698 | * all the interrupts were disabled, in this case we couldn't | |
699 | * receive the RF kill interrupt and update the state in the | |
700 | * op_mode. | |
701 | */ | |
702 | hw_rfkill = iwl_is_rfkill_set(trans); | |
703 | if (hw_rfkill) | |
704 | set_bit(STATUS_RFKILL, &trans->status); | |
705 | else | |
706 | clear_bit(STATUS_RFKILL, &trans->status); | |
707 | iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill); | |
708 | } | |
709 | ||
710 | static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test) | |
711 | { | |
712 | iwl_disable_interrupts(trans); | |
713 | ||
714 | /* | |
715 | * in testing mode, the host stays awake and the | |
716 | * hardware won't be reset (not even partially) | |
717 | */ | |
718 | if (test) | |
719 | return; | |
720 | ||
721 | iwl_pcie_disable_ict(trans); | |
722 | ||
723 | iwl_clear_bit(trans, CSR_GP_CNTRL, | |
724 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
725 | iwl_clear_bit(trans, CSR_GP_CNTRL, | |
726 | CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
727 | ||
728 | /* | |
729 | * reset TX queues -- some of their registers reset during S3 | |
730 | * so if we don't reset everything here the D3 image would try | |
731 | * to execute some invalid memory upon resume | |
732 | */ | |
733 | iwl_trans_pcie_tx_reset(trans); | |
734 | ||
735 | iwl_pcie_set_pwr(trans, true); | |
736 | } | |
737 | ||
738 | static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans, | |
739 | enum iwl_d3_status *status, | |
740 | bool test) | |
741 | { | |
742 | u32 val; | |
743 | int ret; | |
744 | ||
745 | if (test) { | |
746 | iwl_enable_interrupts(trans); | |
747 | *status = IWL_D3_STATUS_ALIVE; | |
748 | return 0; | |
749 | } | |
750 | ||
751 | iwl_pcie_set_pwr(trans, false); | |
752 | ||
753 | val = iwl_read32(trans, CSR_RESET); | |
754 | if (val & CSR_RESET_REG_FLAG_NEVO_RESET) { | |
755 | *status = IWL_D3_STATUS_RESET; | |
756 | return 0; | |
757 | } | |
758 | ||
759 | /* | |
760 | * Also enables interrupts - none will happen as the device doesn't | |
761 | * know we're waking it up, only when the opmode actually tells it | |
762 | * after this call. | |
763 | */ | |
764 | iwl_pcie_reset_ict(trans); | |
765 | ||
766 | iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
767 | iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
768 | ||
769 | ret = iwl_poll_bit(trans, CSR_GP_CNTRL, | |
770 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, | |
771 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, | |
772 | 25000); | |
773 | if (ret) { | |
774 | IWL_ERR(trans, "Failed to resume the device (mac ready)\n"); | |
775 | return ret; | |
776 | } | |
777 | ||
778 | iwl_trans_pcie_tx_reset(trans); | |
779 | ||
780 | ret = iwl_pcie_rx_init(trans); | |
781 | if (ret) { | |
782 | IWL_ERR(trans, "Failed to resume the device (RX reset)\n"); | |
783 | return ret; | |
784 | } | |
785 | ||
786 | *status = IWL_D3_STATUS_ALIVE; | |
787 | return 0; | |
788 | } | |
789 | ||
790 | static int iwl_trans_pcie_start_hw(struct iwl_trans *trans) | |
791 | { | |
792 | bool hw_rfkill; | |
793 | int err; | |
794 | ||
795 | err = iwl_pcie_prepare_card_hw(trans); | |
796 | if (err) { | |
797 | IWL_ERR(trans, "Error while preparing HW: %d\n", err); | |
798 | return err; | |
799 | } | |
800 | ||
801 | /* Reset the entire device */ | |
802 | iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); | |
803 | ||
804 | usleep_range(10, 15); | |
805 | ||
806 | iwl_pcie_apm_init(trans); | |
807 | ||
808 | /* From now on, the op_mode will be kept updated about RF kill state */ | |
809 | iwl_enable_rfkill_int(trans); | |
810 | ||
811 | hw_rfkill = iwl_is_rfkill_set(trans); | |
812 | if (hw_rfkill) | |
813 | set_bit(STATUS_RFKILL, &trans->status); | |
814 | else | |
815 | clear_bit(STATUS_RFKILL, &trans->status); | |
816 | iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill); | |
817 | ||
818 | return 0; | |
819 | } | |
820 | ||
821 | static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans) | |
822 | { | |
823 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
824 | unsigned long flags; | |
825 | ||
826 | /* disable interrupts - don't enable HW RF kill interrupt */ | |
827 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); | |
828 | iwl_disable_interrupts(trans); | |
829 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); | |
830 | ||
831 | iwl_pcie_apm_stop(trans); | |
832 | ||
833 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); | |
834 | iwl_disable_interrupts(trans); | |
835 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); | |
836 | ||
837 | iwl_pcie_disable_ict(trans); | |
838 | } | |
839 | ||
840 | static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) | |
841 | { | |
842 | writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); | |
843 | } | |
844 | ||
845 | static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) | |
846 | { | |
847 | writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); | |
848 | } | |
849 | ||
850 | static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) | |
851 | { | |
852 | return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); | |
853 | } | |
854 | ||
855 | static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) | |
856 | { | |
857 | iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, | |
858 | ((reg & 0x000FFFFF) | (3 << 24))); | |
859 | return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); | |
860 | } | |
861 | ||
862 | static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, | |
863 | u32 val) | |
864 | { | |
865 | iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, | |
866 | ((addr & 0x000FFFFF) | (3 << 24))); | |
867 | iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); | |
868 | } | |
869 | ||
870 | static void iwl_trans_pcie_configure(struct iwl_trans *trans, | |
871 | const struct iwl_trans_config *trans_cfg) | |
872 | { | |
873 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
874 | ||
875 | trans_pcie->cmd_queue = trans_cfg->cmd_queue; | |
876 | trans_pcie->cmd_fifo = trans_cfg->cmd_fifo; | |
877 | if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS)) | |
878 | trans_pcie->n_no_reclaim_cmds = 0; | |
879 | else | |
880 | trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds; | |
881 | if (trans_pcie->n_no_reclaim_cmds) | |
882 | memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds, | |
883 | trans_pcie->n_no_reclaim_cmds * sizeof(u8)); | |
884 | ||
885 | trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k; | |
886 | if (trans_pcie->rx_buf_size_8k) | |
887 | trans_pcie->rx_page_order = get_order(8 * 1024); | |
888 | else | |
889 | trans_pcie->rx_page_order = get_order(4 * 1024); | |
890 | ||
891 | trans_pcie->wd_timeout = | |
892 | msecs_to_jiffies(trans_cfg->queue_watchdog_timeout); | |
893 | ||
894 | trans_pcie->command_names = trans_cfg->command_names; | |
895 | trans_pcie->bc_table_dword = trans_cfg->bc_table_dword; | |
896 | } | |
897 | ||
898 | void iwl_trans_pcie_free(struct iwl_trans *trans) | |
899 | { | |
900 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
901 | ||
902 | synchronize_irq(trans_pcie->pci_dev->irq); | |
903 | ||
904 | iwl_pcie_tx_free(trans); | |
905 | iwl_pcie_rx_free(trans); | |
906 | ||
907 | free_irq(trans_pcie->pci_dev->irq, trans); | |
908 | iwl_pcie_free_ict(trans); | |
909 | ||
910 | pci_disable_msi(trans_pcie->pci_dev); | |
911 | iounmap(trans_pcie->hw_base); | |
912 | pci_release_regions(trans_pcie->pci_dev); | |
913 | pci_disable_device(trans_pcie->pci_dev); | |
914 | kmem_cache_destroy(trans->dev_cmd_pool); | |
915 | ||
916 | kfree(trans); | |
917 | } | |
918 | ||
919 | static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state) | |
920 | { | |
921 | if (state) | |
922 | set_bit(STATUS_TPOWER_PMI, &trans->status); | |
923 | else | |
924 | clear_bit(STATUS_TPOWER_PMI, &trans->status); | |
925 | } | |
926 | ||
927 | static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent, | |
928 | unsigned long *flags) | |
929 | { | |
930 | int ret; | |
931 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
932 | ||
933 | spin_lock_irqsave(&trans_pcie->reg_lock, *flags); | |
934 | ||
935 | /* this bit wakes up the NIC */ | |
936 | __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, | |
937 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
938 | ||
939 | /* | |
940 | * These bits say the device is running, and should keep running for | |
941 | * at least a short while (at least as long as MAC_ACCESS_REQ stays 1), | |
942 | * but they do not indicate that embedded SRAM is restored yet; | |
943 | * 3945 and 4965 have volatile SRAM, and must save/restore contents | |
944 | * to/from host DRAM when sleeping/waking for power-saving. | |
945 | * Each direction takes approximately 1/4 millisecond; with this | |
946 | * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a | |
947 | * series of register accesses are expected (e.g. reading Event Log), | |
948 | * to keep device from sleeping. | |
949 | * | |
950 | * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that | |
951 | * SRAM is okay/restored. We don't check that here because this call | |
952 | * is just for hardware register access; but GP1 MAC_SLEEP check is a | |
953 | * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log). | |
954 | * | |
955 | * 5000 series and later (including 1000 series) have non-volatile SRAM, | |
956 | * and do not save/restore SRAM when power cycling. | |
957 | */ | |
958 | ret = iwl_poll_bit(trans, CSR_GP_CNTRL, | |
959 | CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, | |
960 | (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | | |
961 | CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000); | |
962 | if (unlikely(ret < 0)) { | |
963 | iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI); | |
964 | if (!silent) { | |
965 | u32 val = iwl_read32(trans, CSR_GP_CNTRL); | |
966 | WARN_ONCE(1, | |
967 | "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n", | |
968 | val); | |
969 | spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); | |
970 | return false; | |
971 | } | |
972 | } | |
973 | ||
974 | /* | |
975 | * Fool sparse by faking we release the lock - sparse will | |
976 | * track nic_access anyway. | |
977 | */ | |
978 | __release(&trans_pcie->reg_lock); | |
979 | return true; | |
980 | } | |
981 | ||
982 | static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans, | |
983 | unsigned long *flags) | |
984 | { | |
985 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
986 | ||
987 | lockdep_assert_held(&trans_pcie->reg_lock); | |
988 | ||
989 | /* | |
990 | * Fool sparse by faking we acquiring the lock - sparse will | |
991 | * track nic_access anyway. | |
992 | */ | |
993 | __acquire(&trans_pcie->reg_lock); | |
994 | ||
995 | __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, | |
996 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
997 | /* | |
998 | * Above we read the CSR_GP_CNTRL register, which will flush | |
999 | * any previous writes, but we need the write that clears the | |
1000 | * MAC_ACCESS_REQ bit to be performed before any other writes | |
1001 | * scheduled on different CPUs (after we drop reg_lock). | |
1002 | */ | |
1003 | mmiowb(); | |
1004 | spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); | |
1005 | } | |
1006 | ||
1007 | static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, | |
1008 | void *buf, int dwords) | |
1009 | { | |
1010 | unsigned long flags; | |
1011 | int offs, ret = 0; | |
1012 | u32 *vals = buf; | |
1013 | ||
1014 | if (iwl_trans_grab_nic_access(trans, false, &flags)) { | |
1015 | iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr); | |
1016 | for (offs = 0; offs < dwords; offs++) | |
1017 | vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT); | |
1018 | iwl_trans_release_nic_access(trans, &flags); | |
1019 | } else { | |
1020 | ret = -EBUSY; | |
1021 | } | |
1022 | return ret; | |
1023 | } | |
1024 | ||
1025 | static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr, | |
1026 | const void *buf, int dwords) | |
1027 | { | |
1028 | unsigned long flags; | |
1029 | int offs, ret = 0; | |
1030 | const u32 *vals = buf; | |
1031 | ||
1032 | if (iwl_trans_grab_nic_access(trans, false, &flags)) { | |
1033 | iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr); | |
1034 | for (offs = 0; offs < dwords; offs++) | |
1035 | iwl_write32(trans, HBUS_TARG_MEM_WDAT, | |
1036 | vals ? vals[offs] : 0); | |
1037 | iwl_trans_release_nic_access(trans, &flags); | |
1038 | } else { | |
1039 | ret = -EBUSY; | |
1040 | } | |
1041 | return ret; | |
1042 | } | |
1043 | ||
1044 | #define IWL_FLUSH_WAIT_MS 2000 | |
1045 | ||
1046 | static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans) | |
1047 | { | |
1048 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1049 | struct iwl_txq *txq; | |
1050 | struct iwl_queue *q; | |
1051 | int cnt; | |
1052 | unsigned long now = jiffies; | |
1053 | u32 scd_sram_addr; | |
1054 | u8 buf[16]; | |
1055 | int ret = 0; | |
1056 | ||
1057 | /* waiting for all the tx frames complete might take a while */ | |
1058 | for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { | |
1059 | if (cnt == trans_pcie->cmd_queue) | |
1060 | continue; | |
1061 | txq = &trans_pcie->txq[cnt]; | |
1062 | q = &txq->q; | |
1063 | while (q->read_ptr != q->write_ptr && !time_after(jiffies, | |
1064 | now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) | |
1065 | msleep(1); | |
1066 | ||
1067 | if (q->read_ptr != q->write_ptr) { | |
1068 | IWL_ERR(trans, | |
1069 | "fail to flush all tx fifo queues Q %d\n", cnt); | |
1070 | ret = -ETIMEDOUT; | |
1071 | break; | |
1072 | } | |
1073 | } | |
1074 | ||
1075 | if (!ret) | |
1076 | return 0; | |
1077 | ||
1078 | IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n", | |
1079 | txq->q.read_ptr, txq->q.write_ptr); | |
1080 | ||
1081 | scd_sram_addr = trans_pcie->scd_base_addr + | |
1082 | SCD_TX_STTS_QUEUE_OFFSET(txq->q.id); | |
1083 | iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf)); | |
1084 | ||
1085 | iwl_print_hex_error(trans, buf, sizeof(buf)); | |
1086 | ||
1087 | for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++) | |
1088 | IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt, | |
1089 | iwl_read_direct32(trans, FH_TX_TRB_REG(cnt))); | |
1090 | ||
1091 | for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { | |
1092 | u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt)); | |
1093 | u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7; | |
1094 | bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE)); | |
1095 | u32 tbl_dw = | |
1096 | iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr + | |
1097 | SCD_TRANS_TBL_OFFSET_QUEUE(cnt)); | |
1098 | ||
1099 | if (cnt & 0x1) | |
1100 | tbl_dw = (tbl_dw & 0xFFFF0000) >> 16; | |
1101 | else | |
1102 | tbl_dw = tbl_dw & 0x0000FFFF; | |
1103 | ||
1104 | IWL_ERR(trans, | |
1105 | "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n", | |
1106 | cnt, active ? "" : "in", fifo, tbl_dw, | |
1107 | iwl_read_prph(trans, | |
1108 | SCD_QUEUE_RDPTR(cnt)) & (txq->q.n_bd - 1), | |
1109 | iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt))); | |
1110 | } | |
1111 | ||
1112 | return ret; | |
1113 | } | |
1114 | ||
1115 | static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg, | |
1116 | u32 mask, u32 value) | |
1117 | { | |
1118 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1119 | unsigned long flags; | |
1120 | ||
1121 | spin_lock_irqsave(&trans_pcie->reg_lock, flags); | |
1122 | __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value); | |
1123 | spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); | |
1124 | } | |
1125 | ||
1126 | static const char *get_csr_string(int cmd) | |
1127 | { | |
1128 | #define IWL_CMD(x) case x: return #x | |
1129 | switch (cmd) { | |
1130 | IWL_CMD(CSR_HW_IF_CONFIG_REG); | |
1131 | IWL_CMD(CSR_INT_COALESCING); | |
1132 | IWL_CMD(CSR_INT); | |
1133 | IWL_CMD(CSR_INT_MASK); | |
1134 | IWL_CMD(CSR_FH_INT_STATUS); | |
1135 | IWL_CMD(CSR_GPIO_IN); | |
1136 | IWL_CMD(CSR_RESET); | |
1137 | IWL_CMD(CSR_GP_CNTRL); | |
1138 | IWL_CMD(CSR_HW_REV); | |
1139 | IWL_CMD(CSR_EEPROM_REG); | |
1140 | IWL_CMD(CSR_EEPROM_GP); | |
1141 | IWL_CMD(CSR_OTP_GP_REG); | |
1142 | IWL_CMD(CSR_GIO_REG); | |
1143 | IWL_CMD(CSR_GP_UCODE_REG); | |
1144 | IWL_CMD(CSR_GP_DRIVER_REG); | |
1145 | IWL_CMD(CSR_UCODE_DRV_GP1); | |
1146 | IWL_CMD(CSR_UCODE_DRV_GP2); | |
1147 | IWL_CMD(CSR_LED_REG); | |
1148 | IWL_CMD(CSR_DRAM_INT_TBL_REG); | |
1149 | IWL_CMD(CSR_GIO_CHICKEN_BITS); | |
1150 | IWL_CMD(CSR_ANA_PLL_CFG); | |
1151 | IWL_CMD(CSR_HW_REV_WA_REG); | |
1152 | IWL_CMD(CSR_DBG_HPET_MEM_REG); | |
1153 | default: | |
1154 | return "UNKNOWN"; | |
1155 | } | |
1156 | #undef IWL_CMD | |
1157 | } | |
1158 | ||
1159 | void iwl_pcie_dump_csr(struct iwl_trans *trans) | |
1160 | { | |
1161 | int i; | |
1162 | static const u32 csr_tbl[] = { | |
1163 | CSR_HW_IF_CONFIG_REG, | |
1164 | CSR_INT_COALESCING, | |
1165 | CSR_INT, | |
1166 | CSR_INT_MASK, | |
1167 | CSR_FH_INT_STATUS, | |
1168 | CSR_GPIO_IN, | |
1169 | CSR_RESET, | |
1170 | CSR_GP_CNTRL, | |
1171 | CSR_HW_REV, | |
1172 | CSR_EEPROM_REG, | |
1173 | CSR_EEPROM_GP, | |
1174 | CSR_OTP_GP_REG, | |
1175 | CSR_GIO_REG, | |
1176 | CSR_GP_UCODE_REG, | |
1177 | CSR_GP_DRIVER_REG, | |
1178 | CSR_UCODE_DRV_GP1, | |
1179 | CSR_UCODE_DRV_GP2, | |
1180 | CSR_LED_REG, | |
1181 | CSR_DRAM_INT_TBL_REG, | |
1182 | CSR_GIO_CHICKEN_BITS, | |
1183 | CSR_ANA_PLL_CFG, | |
1184 | CSR_HW_REV_WA_REG, | |
1185 | CSR_DBG_HPET_MEM_REG | |
1186 | }; | |
1187 | IWL_ERR(trans, "CSR values:\n"); | |
1188 | IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " | |
1189 | "CSR_INT_PERIODIC_REG)\n"); | |
1190 | for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { | |
1191 | IWL_ERR(trans, " %25s: 0X%08x\n", | |
1192 | get_csr_string(csr_tbl[i]), | |
1193 | iwl_read32(trans, csr_tbl[i])); | |
1194 | } | |
1195 | } | |
1196 | ||
1197 | #ifdef CONFIG_IWLWIFI_DEBUGFS | |
1198 | /* create and remove of files */ | |
1199 | #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ | |
1200 | if (!debugfs_create_file(#name, mode, parent, trans, \ | |
1201 | &iwl_dbgfs_##name##_ops)) \ | |
1202 | goto err; \ | |
1203 | } while (0) | |
1204 | ||
1205 | /* file operation */ | |
1206 | #define DEBUGFS_READ_FILE_OPS(name) \ | |
1207 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ | |
1208 | .read = iwl_dbgfs_##name##_read, \ | |
1209 | .open = simple_open, \ | |
1210 | .llseek = generic_file_llseek, \ | |
1211 | }; | |
1212 | ||
1213 | #define DEBUGFS_WRITE_FILE_OPS(name) \ | |
1214 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ | |
1215 | .write = iwl_dbgfs_##name##_write, \ | |
1216 | .open = simple_open, \ | |
1217 | .llseek = generic_file_llseek, \ | |
1218 | }; | |
1219 | ||
1220 | #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ | |
1221 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ | |
1222 | .write = iwl_dbgfs_##name##_write, \ | |
1223 | .read = iwl_dbgfs_##name##_read, \ | |
1224 | .open = simple_open, \ | |
1225 | .llseek = generic_file_llseek, \ | |
1226 | }; | |
1227 | ||
1228 | static ssize_t iwl_dbgfs_tx_queue_read(struct file *file, | |
1229 | char __user *user_buf, | |
1230 | size_t count, loff_t *ppos) | |
1231 | { | |
1232 | struct iwl_trans *trans = file->private_data; | |
1233 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1234 | struct iwl_txq *txq; | |
1235 | struct iwl_queue *q; | |
1236 | char *buf; | |
1237 | int pos = 0; | |
1238 | int cnt; | |
1239 | int ret; | |
1240 | size_t bufsz; | |
1241 | ||
1242 | bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues; | |
1243 | ||
1244 | if (!trans_pcie->txq) | |
1245 | return -EAGAIN; | |
1246 | ||
1247 | buf = kzalloc(bufsz, GFP_KERNEL); | |
1248 | if (!buf) | |
1249 | return -ENOMEM; | |
1250 | ||
1251 | for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { | |
1252 | txq = &trans_pcie->txq[cnt]; | |
1253 | q = &txq->q; | |
1254 | pos += scnprintf(buf + pos, bufsz - pos, | |
1255 | "hwq %.2d: read=%u write=%u use=%d stop=%d\n", | |
1256 | cnt, q->read_ptr, q->write_ptr, | |
1257 | !!test_bit(cnt, trans_pcie->queue_used), | |
1258 | !!test_bit(cnt, trans_pcie->queue_stopped)); | |
1259 | } | |
1260 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
1261 | kfree(buf); | |
1262 | return ret; | |
1263 | } | |
1264 | ||
1265 | static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, | |
1266 | char __user *user_buf, | |
1267 | size_t count, loff_t *ppos) | |
1268 | { | |
1269 | struct iwl_trans *trans = file->private_data; | |
1270 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1271 | struct iwl_rxq *rxq = &trans_pcie->rxq; | |
1272 | char buf[256]; | |
1273 | int pos = 0; | |
1274 | const size_t bufsz = sizeof(buf); | |
1275 | ||
1276 | pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n", | |
1277 | rxq->read); | |
1278 | pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n", | |
1279 | rxq->write); | |
1280 | pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n", | |
1281 | rxq->free_count); | |
1282 | if (rxq->rb_stts) { | |
1283 | pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n", | |
1284 | le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF); | |
1285 | } else { | |
1286 | pos += scnprintf(buf + pos, bufsz - pos, | |
1287 | "closed_rb_num: Not Allocated\n"); | |
1288 | } | |
1289 | return simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
1290 | } | |
1291 | ||
1292 | static ssize_t iwl_dbgfs_interrupt_read(struct file *file, | |
1293 | char __user *user_buf, | |
1294 | size_t count, loff_t *ppos) | |
1295 | { | |
1296 | struct iwl_trans *trans = file->private_data; | |
1297 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1298 | struct isr_statistics *isr_stats = &trans_pcie->isr_stats; | |
1299 | ||
1300 | int pos = 0; | |
1301 | char *buf; | |
1302 | int bufsz = 24 * 64; /* 24 items * 64 char per item */ | |
1303 | ssize_t ret; | |
1304 | ||
1305 | buf = kzalloc(bufsz, GFP_KERNEL); | |
1306 | if (!buf) | |
1307 | return -ENOMEM; | |
1308 | ||
1309 | pos += scnprintf(buf + pos, bufsz - pos, | |
1310 | "Interrupt Statistics Report:\n"); | |
1311 | ||
1312 | pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", | |
1313 | isr_stats->hw); | |
1314 | pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", | |
1315 | isr_stats->sw); | |
1316 | if (isr_stats->sw || isr_stats->hw) { | |
1317 | pos += scnprintf(buf + pos, bufsz - pos, | |
1318 | "\tLast Restarting Code: 0x%X\n", | |
1319 | isr_stats->err_code); | |
1320 | } | |
1321 | #ifdef CONFIG_IWLWIFI_DEBUG | |
1322 | pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", | |
1323 | isr_stats->sch); | |
1324 | pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", | |
1325 | isr_stats->alive); | |
1326 | #endif | |
1327 | pos += scnprintf(buf + pos, bufsz - pos, | |
1328 | "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); | |
1329 | ||
1330 | pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", | |
1331 | isr_stats->ctkill); | |
1332 | ||
1333 | pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", | |
1334 | isr_stats->wakeup); | |
1335 | ||
1336 | pos += scnprintf(buf + pos, bufsz - pos, | |
1337 | "Rx command responses:\t\t %u\n", isr_stats->rx); | |
1338 | ||
1339 | pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", | |
1340 | isr_stats->tx); | |
1341 | ||
1342 | pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", | |
1343 | isr_stats->unhandled); | |
1344 | ||
1345 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
1346 | kfree(buf); | |
1347 | return ret; | |
1348 | } | |
1349 | ||
1350 | static ssize_t iwl_dbgfs_interrupt_write(struct file *file, | |
1351 | const char __user *user_buf, | |
1352 | size_t count, loff_t *ppos) | |
1353 | { | |
1354 | struct iwl_trans *trans = file->private_data; | |
1355 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1356 | struct isr_statistics *isr_stats = &trans_pcie->isr_stats; | |
1357 | ||
1358 | char buf[8]; | |
1359 | int buf_size; | |
1360 | u32 reset_flag; | |
1361 | ||
1362 | memset(buf, 0, sizeof(buf)); | |
1363 | buf_size = min(count, sizeof(buf) - 1); | |
1364 | if (copy_from_user(buf, user_buf, buf_size)) | |
1365 | return -EFAULT; | |
1366 | if (sscanf(buf, "%x", &reset_flag) != 1) | |
1367 | return -EFAULT; | |
1368 | if (reset_flag == 0) | |
1369 | memset(isr_stats, 0, sizeof(*isr_stats)); | |
1370 | ||
1371 | return count; | |
1372 | } | |
1373 | ||
1374 | static ssize_t iwl_dbgfs_csr_write(struct file *file, | |
1375 | const char __user *user_buf, | |
1376 | size_t count, loff_t *ppos) | |
1377 | { | |
1378 | struct iwl_trans *trans = file->private_data; | |
1379 | char buf[8]; | |
1380 | int buf_size; | |
1381 | int csr; | |
1382 | ||
1383 | memset(buf, 0, sizeof(buf)); | |
1384 | buf_size = min(count, sizeof(buf) - 1); | |
1385 | if (copy_from_user(buf, user_buf, buf_size)) | |
1386 | return -EFAULT; | |
1387 | if (sscanf(buf, "%d", &csr) != 1) | |
1388 | return -EFAULT; | |
1389 | ||
1390 | iwl_pcie_dump_csr(trans); | |
1391 | ||
1392 | return count; | |
1393 | } | |
1394 | ||
1395 | static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, | |
1396 | char __user *user_buf, | |
1397 | size_t count, loff_t *ppos) | |
1398 | { | |
1399 | struct iwl_trans *trans = file->private_data; | |
1400 | char *buf = NULL; | |
1401 | int pos = 0; | |
1402 | ssize_t ret = -EFAULT; | |
1403 | ||
1404 | ret = pos = iwl_dump_fh(trans, &buf); | |
1405 | if (buf) { | |
1406 | ret = simple_read_from_buffer(user_buf, | |
1407 | count, ppos, buf, pos); | |
1408 | kfree(buf); | |
1409 | } | |
1410 | ||
1411 | return ret; | |
1412 | } | |
1413 | ||
1414 | DEBUGFS_READ_WRITE_FILE_OPS(interrupt); | |
1415 | DEBUGFS_READ_FILE_OPS(fh_reg); | |
1416 | DEBUGFS_READ_FILE_OPS(rx_queue); | |
1417 | DEBUGFS_READ_FILE_OPS(tx_queue); | |
1418 | DEBUGFS_WRITE_FILE_OPS(csr); | |
1419 | ||
1420 | /* | |
1421 | * Create the debugfs files and directories | |
1422 | * | |
1423 | */ | |
1424 | static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans, | |
1425 | struct dentry *dir) | |
1426 | { | |
1427 | DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR); | |
1428 | DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR); | |
1429 | DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR); | |
1430 | DEBUGFS_ADD_FILE(csr, dir, S_IWUSR); | |
1431 | DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR); | |
1432 | return 0; | |
1433 | ||
1434 | err: | |
1435 | IWL_ERR(trans, "failed to create the trans debugfs entry\n"); | |
1436 | return -ENOMEM; | |
1437 | } | |
1438 | #else | |
1439 | static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans, | |
1440 | struct dentry *dir) | |
1441 | { | |
1442 | return 0; | |
1443 | } | |
1444 | #endif /*CONFIG_IWLWIFI_DEBUGFS */ | |
1445 | ||
1446 | static const struct iwl_trans_ops trans_ops_pcie = { | |
1447 | .start_hw = iwl_trans_pcie_start_hw, | |
1448 | .op_mode_leave = iwl_trans_pcie_op_mode_leave, | |
1449 | .fw_alive = iwl_trans_pcie_fw_alive, | |
1450 | .start_fw = iwl_trans_pcie_start_fw, | |
1451 | .stop_device = iwl_trans_pcie_stop_device, | |
1452 | ||
1453 | .d3_suspend = iwl_trans_pcie_d3_suspend, | |
1454 | .d3_resume = iwl_trans_pcie_d3_resume, | |
1455 | ||
1456 | .send_cmd = iwl_trans_pcie_send_hcmd, | |
1457 | ||
1458 | .tx = iwl_trans_pcie_tx, | |
1459 | .reclaim = iwl_trans_pcie_reclaim, | |
1460 | ||
1461 | .txq_disable = iwl_trans_pcie_txq_disable, | |
1462 | .txq_enable = iwl_trans_pcie_txq_enable, | |
1463 | ||
1464 | .dbgfs_register = iwl_trans_pcie_dbgfs_register, | |
1465 | ||
1466 | .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty, | |
1467 | ||
1468 | .write8 = iwl_trans_pcie_write8, | |
1469 | .write32 = iwl_trans_pcie_write32, | |
1470 | .read32 = iwl_trans_pcie_read32, | |
1471 | .read_prph = iwl_trans_pcie_read_prph, | |
1472 | .write_prph = iwl_trans_pcie_write_prph, | |
1473 | .read_mem = iwl_trans_pcie_read_mem, | |
1474 | .write_mem = iwl_trans_pcie_write_mem, | |
1475 | .configure = iwl_trans_pcie_configure, | |
1476 | .set_pmi = iwl_trans_pcie_set_pmi, | |
1477 | .grab_nic_access = iwl_trans_pcie_grab_nic_access, | |
1478 | .release_nic_access = iwl_trans_pcie_release_nic_access, | |
1479 | .set_bits_mask = iwl_trans_pcie_set_bits_mask, | |
1480 | }; | |
1481 | ||
1482 | struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, | |
1483 | const struct pci_device_id *ent, | |
1484 | const struct iwl_cfg *cfg) | |
1485 | { | |
1486 | struct iwl_trans_pcie *trans_pcie; | |
1487 | struct iwl_trans *trans; | |
1488 | u16 pci_cmd; | |
1489 | int err; | |
1490 | ||
1491 | trans = kzalloc(sizeof(struct iwl_trans) + | |
1492 | sizeof(struct iwl_trans_pcie), GFP_KERNEL); | |
1493 | if (!trans) { | |
1494 | err = -ENOMEM; | |
1495 | goto out; | |
1496 | } | |
1497 | ||
1498 | trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1499 | ||
1500 | trans->ops = &trans_ops_pcie; | |
1501 | trans->cfg = cfg; | |
1502 | trans_lockdep_init(trans); | |
1503 | trans_pcie->trans = trans; | |
1504 | spin_lock_init(&trans_pcie->irq_lock); | |
1505 | spin_lock_init(&trans_pcie->reg_lock); | |
1506 | init_waitqueue_head(&trans_pcie->ucode_write_waitq); | |
1507 | ||
1508 | err = pci_enable_device(pdev); | |
1509 | if (err) | |
1510 | goto out_no_pci; | |
1511 | ||
1512 | if (!cfg->base_params->pcie_l1_allowed) { | |
1513 | /* | |
1514 | * W/A - seems to solve weird behavior. We need to remove this | |
1515 | * if we don't want to stay in L1 all the time. This wastes a | |
1516 | * lot of power. | |
1517 | */ | |
1518 | pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | | |
1519 | PCIE_LINK_STATE_L1 | | |
1520 | PCIE_LINK_STATE_CLKPM); | |
1521 | } | |
1522 | ||
1523 | pci_set_master(pdev); | |
1524 | ||
1525 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36)); | |
1526 | if (!err) | |
1527 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36)); | |
1528 | if (err) { | |
1529 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
1530 | if (!err) | |
1531 | err = pci_set_consistent_dma_mask(pdev, | |
1532 | DMA_BIT_MASK(32)); | |
1533 | /* both attempts failed: */ | |
1534 | if (err) { | |
1535 | dev_err(&pdev->dev, "No suitable DMA available\n"); | |
1536 | goto out_pci_disable_device; | |
1537 | } | |
1538 | } | |
1539 | ||
1540 | err = pci_request_regions(pdev, DRV_NAME); | |
1541 | if (err) { | |
1542 | dev_err(&pdev->dev, "pci_request_regions failed\n"); | |
1543 | goto out_pci_disable_device; | |
1544 | } | |
1545 | ||
1546 | trans_pcie->hw_base = pci_ioremap_bar(pdev, 0); | |
1547 | if (!trans_pcie->hw_base) { | |
1548 | dev_err(&pdev->dev, "pci_ioremap_bar failed\n"); | |
1549 | err = -ENODEV; | |
1550 | goto out_pci_release_regions; | |
1551 | } | |
1552 | ||
1553 | /* We disable the RETRY_TIMEOUT register (0x41) to keep | |
1554 | * PCI Tx retries from interfering with C3 CPU state */ | |
1555 | pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); | |
1556 | ||
1557 | err = pci_enable_msi(pdev); | |
1558 | if (err) { | |
1559 | dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", err); | |
1560 | /* enable rfkill interrupt: hw bug w/a */ | |
1561 | pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); | |
1562 | if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { | |
1563 | pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; | |
1564 | pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); | |
1565 | } | |
1566 | } | |
1567 | ||
1568 | trans->dev = &pdev->dev; | |
1569 | trans_pcie->pci_dev = pdev; | |
1570 | trans->hw_rev = iwl_read32(trans, CSR_HW_REV); | |
1571 | trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; | |
1572 | snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), | |
1573 | "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); | |
1574 | ||
1575 | /* Initialize the wait queue for commands */ | |
1576 | init_waitqueue_head(&trans_pcie->wait_command_queue); | |
1577 | ||
1578 | snprintf(trans->dev_cmd_pool_name, sizeof(trans->dev_cmd_pool_name), | |
1579 | "iwl_cmd_pool:%s", dev_name(trans->dev)); | |
1580 | ||
1581 | trans->dev_cmd_headroom = 0; | |
1582 | trans->dev_cmd_pool = | |
1583 | kmem_cache_create(trans->dev_cmd_pool_name, | |
1584 | sizeof(struct iwl_device_cmd) | |
1585 | + trans->dev_cmd_headroom, | |
1586 | sizeof(void *), | |
1587 | SLAB_HWCACHE_ALIGN, | |
1588 | NULL); | |
1589 | ||
1590 | if (!trans->dev_cmd_pool) { | |
1591 | err = -ENOMEM; | |
1592 | goto out_pci_disable_msi; | |
1593 | } | |
1594 | ||
1595 | trans_pcie->inta_mask = CSR_INI_SET_MASK; | |
1596 | ||
1597 | if (iwl_pcie_alloc_ict(trans)) | |
1598 | goto out_free_cmd_pool; | |
1599 | ||
1600 | err = request_threaded_irq(pdev->irq, iwl_pcie_isr_ict, | |
1601 | iwl_pcie_irq_handler, | |
1602 | IRQF_SHARED, DRV_NAME, trans); | |
1603 | if (err) { | |
1604 | IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); | |
1605 | goto out_free_ict; | |
1606 | } | |
1607 | ||
1608 | return trans; | |
1609 | ||
1610 | out_free_ict: | |
1611 | iwl_pcie_free_ict(trans); | |
1612 | out_free_cmd_pool: | |
1613 | kmem_cache_destroy(trans->dev_cmd_pool); | |
1614 | out_pci_disable_msi: | |
1615 | pci_disable_msi(pdev); | |
1616 | out_pci_release_regions: | |
1617 | pci_release_regions(pdev); | |
1618 | out_pci_disable_device: | |
1619 | pci_disable_device(pdev); | |
1620 | out_no_pci: | |
1621 | kfree(trans); | |
1622 | out: | |
1623 | return ERR_PTR(err); | |
1624 | } |