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blk-mq: add a flags parameter to blk_mq_alloc_request
[mirror_ubuntu-bionic-kernel.git] / drivers / nvme / host / pci.c
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CommitLineData
1/*
2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 */
14
15#include <linux/bitops.h>
16#include <linux/blkdev.h>
17#include <linux/blk-mq.h>
18#include <linux/cpu.h>
19#include <linux/delay.h>
20#include <linux/errno.h>
21#include <linux/fs.h>
22#include <linux/genhd.h>
23#include <linux/hdreg.h>
24#include <linux/idr.h>
25#include <linux/init.h>
26#include <linux/interrupt.h>
27#include <linux/io.h>
28#include <linux/kdev_t.h>
29#include <linux/kthread.h>
30#include <linux/kernel.h>
31#include <linux/list_sort.h>
32#include <linux/mm.h>
33#include <linux/module.h>
34#include <linux/moduleparam.h>
35#include <linux/pci.h>
36#include <linux/poison.h>
37#include <linux/ptrace.h>
38#include <linux/sched.h>
39#include <linux/slab.h>
40#include <linux/t10-pi.h>
41#include <linux/types.h>
42#include <linux/pr.h>
43#include <scsi/sg.h>
44#include <linux/io-64-nonatomic-lo-hi.h>
45#include <asm/unaligned.h>
46
47#include <uapi/linux/nvme_ioctl.h>
48#include "nvme.h"
49
50#define NVME_MINORS (1U << MINORBITS)
51#define NVME_Q_DEPTH 1024
52#define NVME_AQ_DEPTH 256
53#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
54#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
55#define ADMIN_TIMEOUT (admin_timeout * HZ)
56#define SHUTDOWN_TIMEOUT (shutdown_timeout * HZ)
57
58static unsigned char admin_timeout = 60;
59module_param(admin_timeout, byte, 0644);
60MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
61
62unsigned char nvme_io_timeout = 30;
63module_param_named(io_timeout, nvme_io_timeout, byte, 0644);
64MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
65
66static unsigned char shutdown_timeout = 5;
67module_param(shutdown_timeout, byte, 0644);
68MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
69
70static int nvme_major;
71module_param(nvme_major, int, 0);
72
73static int nvme_char_major;
74module_param(nvme_char_major, int, 0);
75
76static int use_threaded_interrupts;
77module_param(use_threaded_interrupts, int, 0);
78
79static bool use_cmb_sqes = true;
80module_param(use_cmb_sqes, bool, 0644);
81MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
82
83static DEFINE_SPINLOCK(dev_list_lock);
84static LIST_HEAD(dev_list);
85static struct task_struct *nvme_thread;
86static struct workqueue_struct *nvme_workq;
87static wait_queue_head_t nvme_kthread_wait;
88
89static struct class *nvme_class;
90
91static int __nvme_reset(struct nvme_dev *dev);
92static int nvme_reset(struct nvme_dev *dev);
93static void nvme_process_cq(struct nvme_queue *nvmeq);
94static void nvme_dead_ctrl(struct nvme_dev *dev);
95
96struct async_cmd_info {
97 struct kthread_work work;
98 struct kthread_worker *worker;
99 struct request *req;
100 u32 result;
101 int status;
102 void *ctx;
103};
104
105/*
106 * An NVM Express queue. Each device has at least two (one for admin
107 * commands and one for I/O commands).
108 */
109struct nvme_queue {
110 struct device *q_dmadev;
111 struct nvme_dev *dev;
112 char irqname[24]; /* nvme4294967295-65535\0 */
113 spinlock_t q_lock;
114 struct nvme_command *sq_cmds;
115 struct nvme_command __iomem *sq_cmds_io;
116 volatile struct nvme_completion *cqes;
117 struct blk_mq_tags **tags;
118 dma_addr_t sq_dma_addr;
119 dma_addr_t cq_dma_addr;
120 u32 __iomem *q_db;
121 u16 q_depth;
122 s16 cq_vector;
123 u16 sq_head;
124 u16 sq_tail;
125 u16 cq_head;
126 u16 qid;
127 u8 cq_phase;
128 u8 cqe_seen;
129 struct async_cmd_info cmdinfo;
130};
131
132/*
133 * Check we didin't inadvertently grow the command struct
134 */
135static inline void _nvme_check_size(void)
136{
137 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
138 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
139 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
140 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
141 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
142 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
143 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
144 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
145 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
146 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
147 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
148 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
149}
150
151typedef void (*nvme_completion_fn)(struct nvme_queue *, void *,
152 struct nvme_completion *);
153
154struct nvme_cmd_info {
155 nvme_completion_fn fn;
156 void *ctx;
157 int aborted;
158 struct nvme_queue *nvmeq;
159 struct nvme_iod iod[0];
160};
161
162/*
163 * Max size of iod being embedded in the request payload
164 */
165#define NVME_INT_PAGES 2
166#define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->page_size)
167#define NVME_INT_MASK 0x01
168
169/*
170 * Will slightly overestimate the number of pages needed. This is OK
171 * as it only leads to a small amount of wasted memory for the lifetime of
172 * the I/O.
173 */
174static int nvme_npages(unsigned size, struct nvme_dev *dev)
175{
176 unsigned nprps = DIV_ROUND_UP(size + dev->page_size, dev->page_size);
177 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
178}
179
180static unsigned int nvme_cmd_size(struct nvme_dev *dev)
181{
182 unsigned int ret = sizeof(struct nvme_cmd_info);
183
184 ret += sizeof(struct nvme_iod);
185 ret += sizeof(__le64 *) * nvme_npages(NVME_INT_BYTES(dev), dev);
186 ret += sizeof(struct scatterlist) * NVME_INT_PAGES;
187
188 return ret;
189}
190
191static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
192 unsigned int hctx_idx)
193{
194 struct nvme_dev *dev = data;
195 struct nvme_queue *nvmeq = dev->queues[0];
196
197 WARN_ON(hctx_idx != 0);
198 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
199 WARN_ON(nvmeq->tags);
200
201 hctx->driver_data = nvmeq;
202 nvmeq->tags = &dev->admin_tagset.tags[0];
203 return 0;
204}
205
206static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
207{
208 struct nvme_queue *nvmeq = hctx->driver_data;
209
210 nvmeq->tags = NULL;
211}
212
213static int nvme_admin_init_request(void *data, struct request *req,
214 unsigned int hctx_idx, unsigned int rq_idx,
215 unsigned int numa_node)
216{
217 struct nvme_dev *dev = data;
218 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
219 struct nvme_queue *nvmeq = dev->queues[0];
220
221 BUG_ON(!nvmeq);
222 cmd->nvmeq = nvmeq;
223 return 0;
224}
225
226static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
227 unsigned int hctx_idx)
228{
229 struct nvme_dev *dev = data;
230 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
231
232 if (!nvmeq->tags)
233 nvmeq->tags = &dev->tagset.tags[hctx_idx];
234
235 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
236 hctx->driver_data = nvmeq;
237 return 0;
238}
239
240static int nvme_init_request(void *data, struct request *req,
241 unsigned int hctx_idx, unsigned int rq_idx,
242 unsigned int numa_node)
243{
244 struct nvme_dev *dev = data;
245 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
246 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
247
248 BUG_ON(!nvmeq);
249 cmd->nvmeq = nvmeq;
250 return 0;
251}
252
253static void nvme_set_info(struct nvme_cmd_info *cmd, void *ctx,
254 nvme_completion_fn handler)
255{
256 cmd->fn = handler;
257 cmd->ctx = ctx;
258 cmd->aborted = 0;
259 blk_mq_start_request(blk_mq_rq_from_pdu(cmd));
260}
261
262static void *iod_get_private(struct nvme_iod *iod)
263{
264 return (void *) (iod->private & ~0x1UL);
265}
266
267/*
268 * If bit 0 is set, the iod is embedded in the request payload.
269 */
270static bool iod_should_kfree(struct nvme_iod *iod)
271{
272 return (iod->private & NVME_INT_MASK) == 0;
273}
274
275/* Special values must be less than 0x1000 */
276#define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
277#define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
278#define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
279#define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
280
281static void special_completion(struct nvme_queue *nvmeq, void *ctx,
282 struct nvme_completion *cqe)
283{
284 if (ctx == CMD_CTX_CANCELLED)
285 return;
286 if (ctx == CMD_CTX_COMPLETED) {
287 dev_warn(nvmeq->q_dmadev,
288 "completed id %d twice on queue %d\n",
289 cqe->command_id, le16_to_cpup(&cqe->sq_id));
290 return;
291 }
292 if (ctx == CMD_CTX_INVALID) {
293 dev_warn(nvmeq->q_dmadev,
294 "invalid id %d completed on queue %d\n",
295 cqe->command_id, le16_to_cpup(&cqe->sq_id));
296 return;
297 }
298 dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx);
299}
300
301static void *cancel_cmd_info(struct nvme_cmd_info *cmd, nvme_completion_fn *fn)
302{
303 void *ctx;
304
305 if (fn)
306 *fn = cmd->fn;
307 ctx = cmd->ctx;
308 cmd->fn = special_completion;
309 cmd->ctx = CMD_CTX_CANCELLED;
310 return ctx;
311}
312
313static void async_req_completion(struct nvme_queue *nvmeq, void *ctx,
314 struct nvme_completion *cqe)
315{
316 u32 result = le32_to_cpup(&cqe->result);
317 u16 status = le16_to_cpup(&cqe->status) >> 1;
318
319 if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ)
320 ++nvmeq->dev->event_limit;
321 if (status != NVME_SC_SUCCESS)
322 return;
323
324 switch (result & 0xff07) {
325 case NVME_AER_NOTICE_NS_CHANGED:
326 dev_info(nvmeq->q_dmadev, "rescanning\n");
327 schedule_work(&nvmeq->dev->scan_work);
328 default:
329 dev_warn(nvmeq->q_dmadev, "async event result %08x\n", result);
330 }
331}
332
333static void abort_completion(struct nvme_queue *nvmeq, void *ctx,
334 struct nvme_completion *cqe)
335{
336 struct request *req = ctx;
337
338 u16 status = le16_to_cpup(&cqe->status) >> 1;
339 u32 result = le32_to_cpup(&cqe->result);
340
341 blk_mq_free_request(req);
342
343 dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result);
344 ++nvmeq->dev->abort_limit;
345}
346
347static void async_completion(struct nvme_queue *nvmeq, void *ctx,
348 struct nvme_completion *cqe)
349{
350 struct async_cmd_info *cmdinfo = ctx;
351 cmdinfo->result = le32_to_cpup(&cqe->result);
352 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
353 queue_kthread_work(cmdinfo->worker, &cmdinfo->work);
354 blk_mq_free_request(cmdinfo->req);
355}
356
357static inline struct nvme_cmd_info *get_cmd_from_tag(struct nvme_queue *nvmeq,
358 unsigned int tag)
359{
360 struct request *req = blk_mq_tag_to_rq(*nvmeq->tags, tag);
361
362 return blk_mq_rq_to_pdu(req);
363}
364
365/*
366 * Called with local interrupts disabled and the q_lock held. May not sleep.
367 */
368static void *nvme_finish_cmd(struct nvme_queue *nvmeq, int tag,
369 nvme_completion_fn *fn)
370{
371 struct nvme_cmd_info *cmd = get_cmd_from_tag(nvmeq, tag);
372 void *ctx;
373 if (tag >= nvmeq->q_depth) {
374 *fn = special_completion;
375 return CMD_CTX_INVALID;
376 }
377 if (fn)
378 *fn = cmd->fn;
379 ctx = cmd->ctx;
380 cmd->fn = special_completion;
381 cmd->ctx = CMD_CTX_COMPLETED;
382 return ctx;
383}
384
385/**
386 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
387 * @nvmeq: The queue to use
388 * @cmd: The command to send
389 *
390 * Safe to use from interrupt context
391 */
392static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
393 struct nvme_command *cmd)
394{
395 u16 tail = nvmeq->sq_tail;
396
397 if (nvmeq->sq_cmds_io)
398 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
399 else
400 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
401
402 if (++tail == nvmeq->q_depth)
403 tail = 0;
404 writel(tail, nvmeq->q_db);
405 nvmeq->sq_tail = tail;
406}
407
408static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
409{
410 unsigned long flags;
411 spin_lock_irqsave(&nvmeq->q_lock, flags);
412 __nvme_submit_cmd(nvmeq, cmd);
413 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
414}
415
416static __le64 **iod_list(struct nvme_iod *iod)
417{
418 return ((void *)iod) + iod->offset;
419}
420
421static inline void iod_init(struct nvme_iod *iod, unsigned nbytes,
422 unsigned nseg, unsigned long private)
423{
424 iod->private = private;
425 iod->offset = offsetof(struct nvme_iod, sg[nseg]);
426 iod->npages = -1;
427 iod->length = nbytes;
428 iod->nents = 0;
429}
430
431static struct nvme_iod *
432__nvme_alloc_iod(unsigned nseg, unsigned bytes, struct nvme_dev *dev,
433 unsigned long priv, gfp_t gfp)
434{
435 struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
436 sizeof(__le64 *) * nvme_npages(bytes, dev) +
437 sizeof(struct scatterlist) * nseg, gfp);
438
439 if (iod)
440 iod_init(iod, bytes, nseg, priv);
441
442 return iod;
443}
444
445static struct nvme_iod *nvme_alloc_iod(struct request *rq, struct nvme_dev *dev,
446 gfp_t gfp)
447{
448 unsigned size = !(rq->cmd_flags & REQ_DISCARD) ? blk_rq_bytes(rq) :
449 sizeof(struct nvme_dsm_range);
450 struct nvme_iod *iod;
451
452 if (rq->nr_phys_segments <= NVME_INT_PAGES &&
453 size <= NVME_INT_BYTES(dev)) {
454 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(rq);
455
456 iod = cmd->iod;
457 iod_init(iod, size, rq->nr_phys_segments,
458 (unsigned long) rq | NVME_INT_MASK);
459 return iod;
460 }
461
462 return __nvme_alloc_iod(rq->nr_phys_segments, size, dev,
463 (unsigned long) rq, gfp);
464}
465
466static void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
467{
468 const int last_prp = dev->page_size / 8 - 1;
469 int i;
470 __le64 **list = iod_list(iod);
471 dma_addr_t prp_dma = iod->first_dma;
472
473 if (iod->npages == 0)
474 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
475 for (i = 0; i < iod->npages; i++) {
476 __le64 *prp_list = list[i];
477 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
478 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
479 prp_dma = next_prp_dma;
480 }
481
482 if (iod_should_kfree(iod))
483 kfree(iod);
484}
485
486static int nvme_error_status(u16 status)
487{
488 switch (status & 0x7ff) {
489 case NVME_SC_SUCCESS:
490 return 0;
491 case NVME_SC_CAP_EXCEEDED:
492 return -ENOSPC;
493 default:
494 return -EIO;
495 }
496}
497
498#ifdef CONFIG_BLK_DEV_INTEGRITY
499static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
500{
501 if (be32_to_cpu(pi->ref_tag) == v)
502 pi->ref_tag = cpu_to_be32(p);
503}
504
505static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
506{
507 if (be32_to_cpu(pi->ref_tag) == p)
508 pi->ref_tag = cpu_to_be32(v);
509}
510
511/**
512 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
513 *
514 * The virtual start sector is the one that was originally submitted by the
515 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
516 * start sector may be different. Remap protection information to match the
517 * physical LBA on writes, and back to the original seed on reads.
518 *
519 * Type 0 and 3 do not have a ref tag, so no remapping required.
520 */
521static void nvme_dif_remap(struct request *req,
522 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
523{
524 struct nvme_ns *ns = req->rq_disk->private_data;
525 struct bio_integrity_payload *bip;
526 struct t10_pi_tuple *pi;
527 void *p, *pmap;
528 u32 i, nlb, ts, phys, virt;
529
530 if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
531 return;
532
533 bip = bio_integrity(req->bio);
534 if (!bip)
535 return;
536
537 pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
538
539 p = pmap;
540 virt = bip_get_seed(bip);
541 phys = nvme_block_nr(ns, blk_rq_pos(req));
542 nlb = (blk_rq_bytes(req) >> ns->lba_shift);
543 ts = ns->disk->queue->integrity.tuple_size;
544
545 for (i = 0; i < nlb; i++, virt++, phys++) {
546 pi = (struct t10_pi_tuple *)p;
547 dif_swap(phys, virt, pi);
548 p += ts;
549 }
550 kunmap_atomic(pmap);
551}
552
553static void nvme_init_integrity(struct nvme_ns *ns)
554{
555 struct blk_integrity integrity;
556
557 switch (ns->pi_type) {
558 case NVME_NS_DPS_PI_TYPE3:
559 integrity.profile = &t10_pi_type3_crc;
560 break;
561 case NVME_NS_DPS_PI_TYPE1:
562 case NVME_NS_DPS_PI_TYPE2:
563 integrity.profile = &t10_pi_type1_crc;
564 break;
565 default:
566 integrity.profile = NULL;
567 break;
568 }
569 integrity.tuple_size = ns->ms;
570 blk_integrity_register(ns->disk, &integrity);
571 blk_queue_max_integrity_segments(ns->queue, 1);
572}
573#else /* CONFIG_BLK_DEV_INTEGRITY */
574static void nvme_dif_remap(struct request *req,
575 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
576{
577}
578static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
579{
580}
581static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
582{
583}
584static void nvme_init_integrity(struct nvme_ns *ns)
585{
586}
587#endif
588
589static void req_completion(struct nvme_queue *nvmeq, void *ctx,
590 struct nvme_completion *cqe)
591{
592 struct nvme_iod *iod = ctx;
593 struct request *req = iod_get_private(iod);
594 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
595 u16 status = le16_to_cpup(&cqe->status) >> 1;
596 bool requeue = false;
597 int error = 0;
598
599 if (unlikely(status)) {
600 if (!(status & NVME_SC_DNR || blk_noretry_request(req))
601 && (jiffies - req->start_time) < req->timeout) {
602 unsigned long flags;
603
604 requeue = true;
605 blk_mq_requeue_request(req);
606 spin_lock_irqsave(req->q->queue_lock, flags);
607 if (!blk_queue_stopped(req->q))
608 blk_mq_kick_requeue_list(req->q);
609 spin_unlock_irqrestore(req->q->queue_lock, flags);
610 goto release_iod;
611 }
612
613 if (req->cmd_type == REQ_TYPE_DRV_PRIV) {
614 if (cmd_rq->ctx == CMD_CTX_CANCELLED)
615 error = -EINTR;
616 else
617 error = status;
618 } else {
619 error = nvme_error_status(status);
620 }
621 }
622
623 if (req->cmd_type == REQ_TYPE_DRV_PRIV) {
624 u32 result = le32_to_cpup(&cqe->result);
625 req->special = (void *)(uintptr_t)result;
626 }
627
628 if (cmd_rq->aborted)
629 dev_warn(nvmeq->dev->dev,
630 "completing aborted command with status:%04x\n",
631 error);
632
633release_iod:
634 if (iod->nents) {
635 dma_unmap_sg(nvmeq->dev->dev, iod->sg, iod->nents,
636 rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
637 if (blk_integrity_rq(req)) {
638 if (!rq_data_dir(req))
639 nvme_dif_remap(req, nvme_dif_complete);
640 dma_unmap_sg(nvmeq->dev->dev, iod->meta_sg, 1,
641 rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
642 }
643 }
644 nvme_free_iod(nvmeq->dev, iod);
645
646 if (likely(!requeue))
647 blk_mq_complete_request(req, error);
648}
649
650/* length is in bytes. gfp flags indicates whether we may sleep. */
651static int nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod,
652 int total_len, gfp_t gfp)
653{
654 struct dma_pool *pool;
655 int length = total_len;
656 struct scatterlist *sg = iod->sg;
657 int dma_len = sg_dma_len(sg);
658 u64 dma_addr = sg_dma_address(sg);
659 u32 page_size = dev->page_size;
660 int offset = dma_addr & (page_size - 1);
661 __le64 *prp_list;
662 __le64 **list = iod_list(iod);
663 dma_addr_t prp_dma;
664 int nprps, i;
665
666 length -= (page_size - offset);
667 if (length <= 0)
668 return total_len;
669
670 dma_len -= (page_size - offset);
671 if (dma_len) {
672 dma_addr += (page_size - offset);
673 } else {
674 sg = sg_next(sg);
675 dma_addr = sg_dma_address(sg);
676 dma_len = sg_dma_len(sg);
677 }
678
679 if (length <= page_size) {
680 iod->first_dma = dma_addr;
681 return total_len;
682 }
683
684 nprps = DIV_ROUND_UP(length, page_size);
685 if (nprps <= (256 / 8)) {
686 pool = dev->prp_small_pool;
687 iod->npages = 0;
688 } else {
689 pool = dev->prp_page_pool;
690 iod->npages = 1;
691 }
692
693 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
694 if (!prp_list) {
695 iod->first_dma = dma_addr;
696 iod->npages = -1;
697 return (total_len - length) + page_size;
698 }
699 list[0] = prp_list;
700 iod->first_dma = prp_dma;
701 i = 0;
702 for (;;) {
703 if (i == page_size >> 3) {
704 __le64 *old_prp_list = prp_list;
705 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
706 if (!prp_list)
707 return total_len - length;
708 list[iod->npages++] = prp_list;
709 prp_list[0] = old_prp_list[i - 1];
710 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
711 i = 1;
712 }
713 prp_list[i++] = cpu_to_le64(dma_addr);
714 dma_len -= page_size;
715 dma_addr += page_size;
716 length -= page_size;
717 if (length <= 0)
718 break;
719 if (dma_len > 0)
720 continue;
721 BUG_ON(dma_len < 0);
722 sg = sg_next(sg);
723 dma_addr = sg_dma_address(sg);
724 dma_len = sg_dma_len(sg);
725 }
726
727 return total_len;
728}
729
730static void nvme_submit_priv(struct nvme_queue *nvmeq, struct request *req,
731 struct nvme_iod *iod)
732{
733 struct nvme_command cmnd;
734
735 memcpy(&cmnd, req->cmd, sizeof(cmnd));
736 cmnd.rw.command_id = req->tag;
737 if (req->nr_phys_segments) {
738 cmnd.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
739 cmnd.rw.prp2 = cpu_to_le64(iod->first_dma);
740 }
741
742 __nvme_submit_cmd(nvmeq, &cmnd);
743}
744
745/*
746 * We reuse the small pool to allocate the 16-byte range here as it is not
747 * worth having a special pool for these or additional cases to handle freeing
748 * the iod.
749 */
750static void nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
751 struct request *req, struct nvme_iod *iod)
752{
753 struct nvme_dsm_range *range =
754 (struct nvme_dsm_range *)iod_list(iod)[0];
755 struct nvme_command cmnd;
756
757 range->cattr = cpu_to_le32(0);
758 range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift);
759 range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
760
761 memset(&cmnd, 0, sizeof(cmnd));
762 cmnd.dsm.opcode = nvme_cmd_dsm;
763 cmnd.dsm.command_id = req->tag;
764 cmnd.dsm.nsid = cpu_to_le32(ns->ns_id);
765 cmnd.dsm.prp1 = cpu_to_le64(iod->first_dma);
766 cmnd.dsm.nr = 0;
767 cmnd.dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
768
769 __nvme_submit_cmd(nvmeq, &cmnd);
770}
771
772static void nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
773 int cmdid)
774{
775 struct nvme_command cmnd;
776
777 memset(&cmnd, 0, sizeof(cmnd));
778 cmnd.common.opcode = nvme_cmd_flush;
779 cmnd.common.command_id = cmdid;
780 cmnd.common.nsid = cpu_to_le32(ns->ns_id);
781
782 __nvme_submit_cmd(nvmeq, &cmnd);
783}
784
785static int nvme_submit_iod(struct nvme_queue *nvmeq, struct nvme_iod *iod,
786 struct nvme_ns *ns)
787{
788 struct request *req = iod_get_private(iod);
789 struct nvme_command cmnd;
790 u16 control = 0;
791 u32 dsmgmt = 0;
792
793 if (req->cmd_flags & REQ_FUA)
794 control |= NVME_RW_FUA;
795 if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
796 control |= NVME_RW_LR;
797
798 if (req->cmd_flags & REQ_RAHEAD)
799 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
800
801 memset(&cmnd, 0, sizeof(cmnd));
802 cmnd.rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read);
803 cmnd.rw.command_id = req->tag;
804 cmnd.rw.nsid = cpu_to_le32(ns->ns_id);
805 cmnd.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
806 cmnd.rw.prp2 = cpu_to_le64(iod->first_dma);
807 cmnd.rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
808 cmnd.rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
809
810 if (ns->ms) {
811 switch (ns->pi_type) {
812 case NVME_NS_DPS_PI_TYPE3:
813 control |= NVME_RW_PRINFO_PRCHK_GUARD;
814 break;
815 case NVME_NS_DPS_PI_TYPE1:
816 case NVME_NS_DPS_PI_TYPE2:
817 control |= NVME_RW_PRINFO_PRCHK_GUARD |
818 NVME_RW_PRINFO_PRCHK_REF;
819 cmnd.rw.reftag = cpu_to_le32(
820 nvme_block_nr(ns, blk_rq_pos(req)));
821 break;
822 }
823 if (blk_integrity_rq(req))
824 cmnd.rw.metadata =
825 cpu_to_le64(sg_dma_address(iod->meta_sg));
826 else
827 control |= NVME_RW_PRINFO_PRACT;
828 }
829
830 cmnd.rw.control = cpu_to_le16(control);
831 cmnd.rw.dsmgmt = cpu_to_le32(dsmgmt);
832
833 __nvme_submit_cmd(nvmeq, &cmnd);
834
835 return 0;
836}
837
838/*
839 * NOTE: ns is NULL when called on the admin queue.
840 */
841static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
842 const struct blk_mq_queue_data *bd)
843{
844 struct nvme_ns *ns = hctx->queue->queuedata;
845 struct nvme_queue *nvmeq = hctx->driver_data;
846 struct nvme_dev *dev = nvmeq->dev;
847 struct request *req = bd->rq;
848 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
849 struct nvme_iod *iod;
850 enum dma_data_direction dma_dir;
851
852 /*
853 * If formated with metadata, require the block layer provide a buffer
854 * unless this namespace is formated such that the metadata can be
855 * stripped/generated by the controller with PRACT=1.
856 */
857 if (ns && ns->ms && !blk_integrity_rq(req)) {
858 if (!(ns->pi_type && ns->ms == 8) &&
859 req->cmd_type != REQ_TYPE_DRV_PRIV) {
860 blk_mq_complete_request(req, -EFAULT);
861 return BLK_MQ_RQ_QUEUE_OK;
862 }
863 }
864
865 iod = nvme_alloc_iod(req, dev, GFP_ATOMIC);
866 if (!iod)
867 return BLK_MQ_RQ_QUEUE_BUSY;
868
869 if (req->cmd_flags & REQ_DISCARD) {
870 void *range;
871 /*
872 * We reuse the small pool to allocate the 16-byte range here
873 * as it is not worth having a special pool for these or
874 * additional cases to handle freeing the iod.
875 */
876 range = dma_pool_alloc(dev->prp_small_pool, GFP_ATOMIC,
877 &iod->first_dma);
878 if (!range)
879 goto retry_cmd;
880 iod_list(iod)[0] = (__le64 *)range;
881 iod->npages = 0;
882 } else if (req->nr_phys_segments) {
883 dma_dir = rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
884
885 sg_init_table(iod->sg, req->nr_phys_segments);
886 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
887 if (!iod->nents)
888 goto error_cmd;
889
890 if (!dma_map_sg(nvmeq->q_dmadev, iod->sg, iod->nents, dma_dir))
891 goto retry_cmd;
892
893 if (blk_rq_bytes(req) !=
894 nvme_setup_prps(dev, iod, blk_rq_bytes(req), GFP_ATOMIC)) {
895 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
896 goto retry_cmd;
897 }
898 if (blk_integrity_rq(req)) {
899 if (blk_rq_count_integrity_sg(req->q, req->bio) != 1) {
900 dma_unmap_sg(dev->dev, iod->sg, iod->nents,
901 dma_dir);
902 goto error_cmd;
903 }
904
905 sg_init_table(iod->meta_sg, 1);
906 if (blk_rq_map_integrity_sg(
907 req->q, req->bio, iod->meta_sg) != 1) {
908 dma_unmap_sg(dev->dev, iod->sg, iod->nents,
909 dma_dir);
910 goto error_cmd;
911 }
912
913 if (rq_data_dir(req))
914 nvme_dif_remap(req, nvme_dif_prep);
915
916 if (!dma_map_sg(nvmeq->q_dmadev, iod->meta_sg, 1, dma_dir)) {
917 dma_unmap_sg(dev->dev, iod->sg, iod->nents,
918 dma_dir);
919 goto error_cmd;
920 }
921 }
922 }
923
924 nvme_set_info(cmd, iod, req_completion);
925 spin_lock_irq(&nvmeq->q_lock);
926 if (req->cmd_type == REQ_TYPE_DRV_PRIV)
927 nvme_submit_priv(nvmeq, req, iod);
928 else if (req->cmd_flags & REQ_DISCARD)
929 nvme_submit_discard(nvmeq, ns, req, iod);
930 else if (req->cmd_flags & REQ_FLUSH)
931 nvme_submit_flush(nvmeq, ns, req->tag);
932 else
933 nvme_submit_iod(nvmeq, iod, ns);
934
935 nvme_process_cq(nvmeq);
936 spin_unlock_irq(&nvmeq->q_lock);
937 return BLK_MQ_RQ_QUEUE_OK;
938
939 error_cmd:
940 nvme_free_iod(dev, iod);
941 return BLK_MQ_RQ_QUEUE_ERROR;
942 retry_cmd:
943 nvme_free_iod(dev, iod);
944 return BLK_MQ_RQ_QUEUE_BUSY;
945}
946
947static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag)
948{
949 u16 head, phase;
950
951 head = nvmeq->cq_head;
952 phase = nvmeq->cq_phase;
953
954 for (;;) {
955 void *ctx;
956 nvme_completion_fn fn;
957 struct nvme_completion cqe = nvmeq->cqes[head];
958 if ((le16_to_cpu(cqe.status) & 1) != phase)
959 break;
960 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
961 if (++head == nvmeq->q_depth) {
962 head = 0;
963 phase = !phase;
964 }
965 if (tag && *tag == cqe.command_id)
966 *tag = -1;
967 ctx = nvme_finish_cmd(nvmeq, cqe.command_id, &fn);
968 fn(nvmeq, ctx, &cqe);
969 }
970
971 /* If the controller ignores the cq head doorbell and continuously
972 * writes to the queue, it is theoretically possible to wrap around
973 * the queue twice and mistakenly return IRQ_NONE. Linux only
974 * requires that 0.1% of your interrupts are handled, so this isn't
975 * a big problem.
976 */
977 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
978 return;
979
980 if (likely(nvmeq->cq_vector >= 0))
981 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
982 nvmeq->cq_head = head;
983 nvmeq->cq_phase = phase;
984
985 nvmeq->cqe_seen = 1;
986}
987
988static void nvme_process_cq(struct nvme_queue *nvmeq)
989{
990 __nvme_process_cq(nvmeq, NULL);
991}
992
993static irqreturn_t nvme_irq(int irq, void *data)
994{
995 irqreturn_t result;
996 struct nvme_queue *nvmeq = data;
997 spin_lock(&nvmeq->q_lock);
998 nvme_process_cq(nvmeq);
999 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
1000 nvmeq->cqe_seen = 0;
1001 spin_unlock(&nvmeq->q_lock);
1002 return result;
1003}
1004
1005static irqreturn_t nvme_irq_check(int irq, void *data)
1006{
1007 struct nvme_queue *nvmeq = data;
1008 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
1009 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
1010 return IRQ_NONE;
1011 return IRQ_WAKE_THREAD;
1012}
1013
1014static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
1015{
1016 struct nvme_queue *nvmeq = hctx->driver_data;
1017
1018 if ((le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) ==
1019 nvmeq->cq_phase) {
1020 spin_lock_irq(&nvmeq->q_lock);
1021 __nvme_process_cq(nvmeq, &tag);
1022 spin_unlock_irq(&nvmeq->q_lock);
1023
1024 if (tag == -1)
1025 return 1;
1026 }
1027
1028 return 0;
1029}
1030
1031/*
1032 * Returns 0 on success. If the result is negative, it's a Linux error code;
1033 * if the result is positive, it's an NVM Express status code
1034 */
1035int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
1036 void *buffer, void __user *ubuffer, unsigned bufflen,
1037 u32 *result, unsigned timeout)
1038{
1039 bool write = cmd->common.opcode & 1;
1040 struct bio *bio = NULL;
1041 struct request *req;
1042 int ret;
1043
1044 req = blk_mq_alloc_request(q, write, 0);
1045 if (IS_ERR(req))
1046 return PTR_ERR(req);
1047
1048 req->cmd_type = REQ_TYPE_DRV_PRIV;
1049 req->cmd_flags |= REQ_FAILFAST_DRIVER;
1050 req->__data_len = 0;
1051 req->__sector = (sector_t) -1;
1052 req->bio = req->biotail = NULL;
1053
1054 req->timeout = timeout ? timeout : ADMIN_TIMEOUT;
1055
1056 req->cmd = (unsigned char *)cmd;
1057 req->cmd_len = sizeof(struct nvme_command);
1058 req->special = (void *)0;
1059
1060 if (buffer && bufflen) {
1061 ret = blk_rq_map_kern(q, req, buffer, bufflen,
1062 __GFP_DIRECT_RECLAIM);
1063 if (ret)
1064 goto out;
1065 } else if (ubuffer && bufflen) {
1066 ret = blk_rq_map_user(q, req, NULL, ubuffer, bufflen,
1067 __GFP_DIRECT_RECLAIM);
1068 if (ret)
1069 goto out;
1070 bio = req->bio;
1071 }
1072
1073 blk_execute_rq(req->q, NULL, req, 0);
1074 if (bio)
1075 blk_rq_unmap_user(bio);
1076 if (result)
1077 *result = (u32)(uintptr_t)req->special;
1078 ret = req->errors;
1079 out:
1080 blk_mq_free_request(req);
1081 return ret;
1082}
1083
1084int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
1085 void *buffer, unsigned bufflen)
1086{
1087 return __nvme_submit_sync_cmd(q, cmd, buffer, NULL, bufflen, NULL, 0);
1088}
1089
1090static int nvme_submit_async_admin_req(struct nvme_dev *dev)
1091{
1092 struct nvme_queue *nvmeq = dev->queues[0];
1093 struct nvme_command c;
1094 struct nvme_cmd_info *cmd_info;
1095 struct request *req;
1096
1097 req = blk_mq_alloc_request(dev->admin_q, WRITE,
1098 BLK_MQ_REQ_NOWAIT | BLK_MQ_REQ_RESERVED);
1099 if (IS_ERR(req))
1100 return PTR_ERR(req);
1101
1102 req->cmd_flags |= REQ_NO_TIMEOUT;
1103 cmd_info = blk_mq_rq_to_pdu(req);
1104 nvme_set_info(cmd_info, NULL, async_req_completion);
1105
1106 memset(&c, 0, sizeof(c));
1107 c.common.opcode = nvme_admin_async_event;
1108 c.common.command_id = req->tag;
1109
1110 blk_mq_free_request(req);
1111 __nvme_submit_cmd(nvmeq, &c);
1112 return 0;
1113}
1114
1115static int nvme_submit_admin_async_cmd(struct nvme_dev *dev,
1116 struct nvme_command *cmd,
1117 struct async_cmd_info *cmdinfo, unsigned timeout)
1118{
1119 struct nvme_queue *nvmeq = dev->queues[0];
1120 struct request *req;
1121 struct nvme_cmd_info *cmd_rq;
1122
1123 req = blk_mq_alloc_request(dev->admin_q, WRITE, 0);
1124 if (IS_ERR(req))
1125 return PTR_ERR(req);
1126
1127 req->timeout = timeout;
1128 cmd_rq = blk_mq_rq_to_pdu(req);
1129 cmdinfo->req = req;
1130 nvme_set_info(cmd_rq, cmdinfo, async_completion);
1131 cmdinfo->status = -EINTR;
1132
1133 cmd->common.command_id = req->tag;
1134
1135 nvme_submit_cmd(nvmeq, cmd);
1136 return 0;
1137}
1138
1139static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1140{
1141 struct nvme_command c;
1142
1143 memset(&c, 0, sizeof(c));
1144 c.delete_queue.opcode = opcode;
1145 c.delete_queue.qid = cpu_to_le16(id);
1146
1147 return nvme_submit_sync_cmd(dev->admin_q, &c, NULL, 0);
1148}
1149
1150static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1151 struct nvme_queue *nvmeq)
1152{
1153 struct nvme_command c;
1154 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
1155
1156 /*
1157 * Note: we (ab)use the fact the the prp fields survive if no data
1158 * is attached to the request.
1159 */
1160 memset(&c, 0, sizeof(c));
1161 c.create_cq.opcode = nvme_admin_create_cq;
1162 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1163 c.create_cq.cqid = cpu_to_le16(qid);
1164 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1165 c.create_cq.cq_flags = cpu_to_le16(flags);
1166 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
1167
1168 return nvme_submit_sync_cmd(dev->admin_q, &c, NULL, 0);
1169}
1170
1171static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1172 struct nvme_queue *nvmeq)
1173{
1174 struct nvme_command c;
1175 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
1176
1177 /*
1178 * Note: we (ab)use the fact the the prp fields survive if no data
1179 * is attached to the request.
1180 */
1181 memset(&c, 0, sizeof(c));
1182 c.create_sq.opcode = nvme_admin_create_sq;
1183 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1184 c.create_sq.sqid = cpu_to_le16(qid);
1185 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1186 c.create_sq.sq_flags = cpu_to_le16(flags);
1187 c.create_sq.cqid = cpu_to_le16(qid);
1188
1189 return nvme_submit_sync_cmd(dev->admin_q, &c, NULL, 0);
1190}
1191
1192static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1193{
1194 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1195}
1196
1197static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1198{
1199 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1200}
1201
1202int nvme_identify_ctrl(struct nvme_dev *dev, struct nvme_id_ctrl **id)
1203{
1204 struct nvme_command c = { };
1205 int error;
1206
1207 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
1208 c.identify.opcode = nvme_admin_identify;
1209 c.identify.cns = cpu_to_le32(1);
1210
1211 *id = kmalloc(sizeof(struct nvme_id_ctrl), GFP_KERNEL);
1212 if (!*id)
1213 return -ENOMEM;
1214
1215 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
1216 sizeof(struct nvme_id_ctrl));
1217 if (error)
1218 kfree(*id);
1219 return error;
1220}
1221
1222int nvme_identify_ns(struct nvme_dev *dev, unsigned nsid,
1223 struct nvme_id_ns **id)
1224{
1225 struct nvme_command c = { };
1226 int error;
1227
1228 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
1229 c.identify.opcode = nvme_admin_identify,
1230 c.identify.nsid = cpu_to_le32(nsid),
1231
1232 *id = kmalloc(sizeof(struct nvme_id_ns), GFP_KERNEL);
1233 if (!*id)
1234 return -ENOMEM;
1235
1236 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
1237 sizeof(struct nvme_id_ns));
1238 if (error)
1239 kfree(*id);
1240 return error;
1241}
1242
1243int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
1244 dma_addr_t dma_addr, u32 *result)
1245{
1246 struct nvme_command c;
1247
1248 memset(&c, 0, sizeof(c));
1249 c.features.opcode = nvme_admin_get_features;
1250 c.features.nsid = cpu_to_le32(nsid);
1251 c.features.prp1 = cpu_to_le64(dma_addr);
1252 c.features.fid = cpu_to_le32(fid);
1253
1254 return __nvme_submit_sync_cmd(dev->admin_q, &c, NULL, NULL, 0,
1255 result, 0);
1256}
1257
1258int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
1259 dma_addr_t dma_addr, u32 *result)
1260{
1261 struct nvme_command c;
1262
1263 memset(&c, 0, sizeof(c));
1264 c.features.opcode = nvme_admin_set_features;
1265 c.features.prp1 = cpu_to_le64(dma_addr);
1266 c.features.fid = cpu_to_le32(fid);
1267 c.features.dword11 = cpu_to_le32(dword11);
1268
1269 return __nvme_submit_sync_cmd(dev->admin_q, &c, NULL, NULL, 0,
1270 result, 0);
1271}
1272
1273int nvme_get_log_page(struct nvme_dev *dev, struct nvme_smart_log **log)
1274{
1275 struct nvme_command c = { };
1276 int error;
1277
1278 c.common.opcode = nvme_admin_get_log_page,
1279 c.common.nsid = cpu_to_le32(0xFFFFFFFF),
1280 c.common.cdw10[0] = cpu_to_le32(
1281 (((sizeof(struct nvme_smart_log) / 4) - 1) << 16) |
1282 NVME_LOG_SMART),
1283
1284 *log = kmalloc(sizeof(struct nvme_smart_log), GFP_KERNEL);
1285 if (!*log)
1286 return -ENOMEM;
1287
1288 error = nvme_submit_sync_cmd(dev->admin_q, &c, *log,
1289 sizeof(struct nvme_smart_log));
1290 if (error)
1291 kfree(*log);
1292 return error;
1293}
1294
1295/**
1296 * nvme_abort_req - Attempt aborting a request
1297 *
1298 * Schedule controller reset if the command was already aborted once before and
1299 * still hasn't been returned to the driver, or if this is the admin queue.
1300 */
1301static void nvme_abort_req(struct request *req)
1302{
1303 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
1304 struct nvme_queue *nvmeq = cmd_rq->nvmeq;
1305 struct nvme_dev *dev = nvmeq->dev;
1306 struct request *abort_req;
1307 struct nvme_cmd_info *abort_cmd;
1308 struct nvme_command cmd;
1309
1310 if (!nvmeq->qid || cmd_rq->aborted) {
1311 spin_lock(&dev_list_lock);
1312 if (!__nvme_reset(dev)) {
1313 dev_warn(dev->dev,
1314 "I/O %d QID %d timeout, reset controller\n",
1315 req->tag, nvmeq->qid);
1316 }
1317 spin_unlock(&dev_list_lock);
1318 return;
1319 }
1320
1321 if (!dev->abort_limit)
1322 return;
1323
1324 abort_req = blk_mq_alloc_request(dev->admin_q, WRITE,
1325 BLK_MQ_REQ_NOWAIT);
1326 if (IS_ERR(abort_req))
1327 return;
1328
1329 abort_cmd = blk_mq_rq_to_pdu(abort_req);
1330 nvme_set_info(abort_cmd, abort_req, abort_completion);
1331
1332 memset(&cmd, 0, sizeof(cmd));
1333 cmd.abort.opcode = nvme_admin_abort_cmd;
1334 cmd.abort.cid = req->tag;
1335 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1336 cmd.abort.command_id = abort_req->tag;
1337
1338 --dev->abort_limit;
1339 cmd_rq->aborted = 1;
1340
1341 dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", req->tag,
1342 nvmeq->qid);
1343 nvme_submit_cmd(dev->queues[0], &cmd);
1344}
1345
1346static void nvme_cancel_queue_ios(struct request *req, void *data, bool reserved)
1347{
1348 struct nvme_queue *nvmeq = data;
1349 void *ctx;
1350 nvme_completion_fn fn;
1351 struct nvme_cmd_info *cmd;
1352 struct nvme_completion cqe;
1353
1354 if (!blk_mq_request_started(req))
1355 return;
1356
1357 cmd = blk_mq_rq_to_pdu(req);
1358
1359 if (cmd->ctx == CMD_CTX_CANCELLED)
1360 return;
1361
1362 if (blk_queue_dying(req->q))
1363 cqe.status = cpu_to_le16((NVME_SC_ABORT_REQ | NVME_SC_DNR) << 1);
1364 else
1365 cqe.status = cpu_to_le16(NVME_SC_ABORT_REQ << 1);
1366
1367
1368 dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n",
1369 req->tag, nvmeq->qid);
1370 ctx = cancel_cmd_info(cmd, &fn);
1371 fn(nvmeq, ctx, &cqe);
1372}
1373
1374static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1375{
1376 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
1377 struct nvme_queue *nvmeq = cmd->nvmeq;
1378
1379 dev_warn(nvmeq->q_dmadev, "Timeout I/O %d QID %d\n", req->tag,
1380 nvmeq->qid);
1381 spin_lock_irq(&nvmeq->q_lock);
1382 nvme_abort_req(req);
1383 spin_unlock_irq(&nvmeq->q_lock);
1384
1385 /*
1386 * The aborted req will be completed on receiving the abort req.
1387 * We enable the timer again. If hit twice, it'll cause a device reset,
1388 * as the device then is in a faulty state.
1389 */
1390 return BLK_EH_RESET_TIMER;
1391}
1392
1393static void nvme_free_queue(struct nvme_queue *nvmeq)
1394{
1395 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1396 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1397 if (nvmeq->sq_cmds)
1398 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1399 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1400 kfree(nvmeq);
1401}
1402
1403static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1404{
1405 int i;
1406
1407 for (i = dev->queue_count - 1; i >= lowest; i--) {
1408 struct nvme_queue *nvmeq = dev->queues[i];
1409 dev->queue_count--;
1410 dev->queues[i] = NULL;
1411 nvme_free_queue(nvmeq);
1412 }
1413}
1414
1415/**
1416 * nvme_suspend_queue - put queue into suspended state
1417 * @nvmeq - queue to suspend
1418 */
1419static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1420{
1421 int vector;
1422
1423 spin_lock_irq(&nvmeq->q_lock);
1424 if (nvmeq->cq_vector == -1) {
1425 spin_unlock_irq(&nvmeq->q_lock);
1426 return 1;
1427 }
1428 vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
1429 nvmeq->dev->online_queues--;
1430 nvmeq->cq_vector = -1;
1431 spin_unlock_irq(&nvmeq->q_lock);
1432
1433 if (!nvmeq->qid && nvmeq->dev->admin_q)
1434 blk_mq_freeze_queue_start(nvmeq->dev->admin_q);
1435
1436 irq_set_affinity_hint(vector, NULL);
1437 free_irq(vector, nvmeq);
1438
1439 return 0;
1440}
1441
1442static void nvme_clear_queue(struct nvme_queue *nvmeq)
1443{
1444 spin_lock_irq(&nvmeq->q_lock);
1445 if (nvmeq->tags && *nvmeq->tags)
1446 blk_mq_all_tag_busy_iter(*nvmeq->tags, nvme_cancel_queue_ios, nvmeq);
1447 spin_unlock_irq(&nvmeq->q_lock);
1448}
1449
1450static void nvme_disable_queue(struct nvme_dev *dev, int qid)
1451{
1452 struct nvme_queue *nvmeq = dev->queues[qid];
1453
1454 if (!nvmeq)
1455 return;
1456 if (nvme_suspend_queue(nvmeq))
1457 return;
1458
1459 /* Don't tell the adapter to delete the admin queue.
1460 * Don't tell a removed adapter to delete IO queues. */
1461 if (qid && readl(&dev->bar->csts) != -1) {
1462 adapter_delete_sq(dev, qid);
1463 adapter_delete_cq(dev, qid);
1464 }
1465
1466 spin_lock_irq(&nvmeq->q_lock);
1467 nvme_process_cq(nvmeq);
1468 spin_unlock_irq(&nvmeq->q_lock);
1469}
1470
1471static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1472 int entry_size)
1473{
1474 int q_depth = dev->q_depth;
1475 unsigned q_size_aligned = roundup(q_depth * entry_size, dev->page_size);
1476
1477 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1478 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1479 mem_per_q = round_down(mem_per_q, dev->page_size);
1480 q_depth = div_u64(mem_per_q, entry_size);
1481
1482 /*
1483 * Ensure the reduced q_depth is above some threshold where it
1484 * would be better to map queues in system memory with the
1485 * original depth
1486 */
1487 if (q_depth < 64)
1488 return -ENOMEM;
1489 }
1490
1491 return q_depth;
1492}
1493
1494static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1495 int qid, int depth)
1496{
1497 if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
1498 unsigned offset = (qid - 1) *
1499 roundup(SQ_SIZE(depth), dev->page_size);
1500 nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset;
1501 nvmeq->sq_cmds_io = dev->cmb + offset;
1502 } else {
1503 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1504 &nvmeq->sq_dma_addr, GFP_KERNEL);
1505 if (!nvmeq->sq_cmds)
1506 return -ENOMEM;
1507 }
1508
1509 return 0;
1510}
1511
1512static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1513 int depth)
1514{
1515 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
1516 if (!nvmeq)
1517 return NULL;
1518
1519 nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
1520 &nvmeq->cq_dma_addr, GFP_KERNEL);
1521 if (!nvmeq->cqes)
1522 goto free_nvmeq;
1523
1524 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1525 goto free_cqdma;
1526
1527 nvmeq->q_dmadev = dev->dev;
1528 nvmeq->dev = dev;
1529 snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1530 dev->instance, qid);
1531 spin_lock_init(&nvmeq->q_lock);
1532 nvmeq->cq_head = 0;
1533 nvmeq->cq_phase = 1;
1534 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1535 nvmeq->q_depth = depth;
1536 nvmeq->qid = qid;
1537 nvmeq->cq_vector = -1;
1538 dev->queues[qid] = nvmeq;
1539
1540 /* make sure queue descriptor is set before queue count, for kthread */
1541 mb();
1542 dev->queue_count++;
1543
1544 return nvmeq;
1545
1546 free_cqdma:
1547 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1548 nvmeq->cq_dma_addr);
1549 free_nvmeq:
1550 kfree(nvmeq);
1551 return NULL;
1552}
1553
1554static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1555 const char *name)
1556{
1557 if (use_threaded_interrupts)
1558 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
1559 nvme_irq_check, nvme_irq, IRQF_SHARED,
1560 name, nvmeq);
1561 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
1562 IRQF_SHARED, name, nvmeq);
1563}
1564
1565static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1566{
1567 struct nvme_dev *dev = nvmeq->dev;
1568
1569 spin_lock_irq(&nvmeq->q_lock);
1570 nvmeq->sq_tail = 0;
1571 nvmeq->cq_head = 0;
1572 nvmeq->cq_phase = 1;
1573 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1574 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1575 dev->online_queues++;
1576 spin_unlock_irq(&nvmeq->q_lock);
1577}
1578
1579static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1580{
1581 struct nvme_dev *dev = nvmeq->dev;
1582 int result;
1583
1584 nvmeq->cq_vector = qid - 1;
1585 result = adapter_alloc_cq(dev, qid, nvmeq);
1586 if (result < 0)
1587 return result;
1588
1589 result = adapter_alloc_sq(dev, qid, nvmeq);
1590 if (result < 0)
1591 goto release_cq;
1592
1593 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1594 if (result < 0)
1595 goto release_sq;
1596
1597 nvme_init_queue(nvmeq, qid);
1598 return result;
1599
1600 release_sq:
1601 adapter_delete_sq(dev, qid);
1602 release_cq:
1603 adapter_delete_cq(dev, qid);
1604 return result;
1605}
1606
1607static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled)
1608{
1609 unsigned long timeout;
1610 u32 bit = enabled ? NVME_CSTS_RDY : 0;
1611
1612 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1613
1614 while ((readl(&dev->bar->csts) & NVME_CSTS_RDY) != bit) {
1615 msleep(100);
1616 if (fatal_signal_pending(current))
1617 return -EINTR;
1618 if (time_after(jiffies, timeout)) {
1619 dev_err(dev->dev,
1620 "Device not ready; aborting %s\n", enabled ?
1621 "initialisation" : "reset");
1622 return -ENODEV;
1623 }
1624 }
1625
1626 return 0;
1627}
1628
1629/*
1630 * If the device has been passed off to us in an enabled state, just clear
1631 * the enabled bit. The spec says we should set the 'shutdown notification
1632 * bits', but doing so may cause the device to complete commands to the
1633 * admin queue ... and we don't know what memory that might be pointing at!
1634 */
1635static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap)
1636{
1637 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1638 dev->ctrl_config &= ~NVME_CC_ENABLE;
1639 writel(dev->ctrl_config, &dev->bar->cc);
1640
1641 return nvme_wait_ready(dev, cap, false);
1642}
1643
1644static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap)
1645{
1646 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1647 dev->ctrl_config |= NVME_CC_ENABLE;
1648 writel(dev->ctrl_config, &dev->bar->cc);
1649
1650 return nvme_wait_ready(dev, cap, true);
1651}
1652
1653static int nvme_shutdown_ctrl(struct nvme_dev *dev)
1654{
1655 unsigned long timeout;
1656
1657 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1658 dev->ctrl_config |= NVME_CC_SHN_NORMAL;
1659
1660 writel(dev->ctrl_config, &dev->bar->cc);
1661
1662 timeout = SHUTDOWN_TIMEOUT + jiffies;
1663 while ((readl(&dev->bar->csts) & NVME_CSTS_SHST_MASK) !=
1664 NVME_CSTS_SHST_CMPLT) {
1665 msleep(100);
1666 if (fatal_signal_pending(current))
1667 return -EINTR;
1668 if (time_after(jiffies, timeout)) {
1669 dev_err(dev->dev,
1670 "Device shutdown incomplete; abort shutdown\n");
1671 return -ENODEV;
1672 }
1673 }
1674
1675 return 0;
1676}
1677
1678static struct blk_mq_ops nvme_mq_admin_ops = {
1679 .queue_rq = nvme_queue_rq,
1680 .map_queue = blk_mq_map_queue,
1681 .init_hctx = nvme_admin_init_hctx,
1682 .exit_hctx = nvme_admin_exit_hctx,
1683 .init_request = nvme_admin_init_request,
1684 .timeout = nvme_timeout,
1685};
1686
1687static struct blk_mq_ops nvme_mq_ops = {
1688 .queue_rq = nvme_queue_rq,
1689 .map_queue = blk_mq_map_queue,
1690 .init_hctx = nvme_init_hctx,
1691 .init_request = nvme_init_request,
1692 .timeout = nvme_timeout,
1693 .poll = nvme_poll,
1694};
1695
1696static void nvme_dev_remove_admin(struct nvme_dev *dev)
1697{
1698 if (dev->admin_q && !blk_queue_dying(dev->admin_q)) {
1699 blk_cleanup_queue(dev->admin_q);
1700 blk_mq_free_tag_set(&dev->admin_tagset);
1701 }
1702}
1703
1704static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1705{
1706 if (!dev->admin_q) {
1707 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1708 dev->admin_tagset.nr_hw_queues = 1;
1709 dev->admin_tagset.queue_depth = NVME_AQ_DEPTH - 1;
1710 dev->admin_tagset.reserved_tags = 1;
1711 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1712 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1713 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
1714 dev->admin_tagset.driver_data = dev;
1715
1716 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1717 return -ENOMEM;
1718
1719 dev->admin_q = blk_mq_init_queue(&dev->admin_tagset);
1720 if (IS_ERR(dev->admin_q)) {
1721 blk_mq_free_tag_set(&dev->admin_tagset);
1722 return -ENOMEM;
1723 }
1724 if (!blk_get_queue(dev->admin_q)) {
1725 nvme_dev_remove_admin(dev);
1726 dev->admin_q = NULL;
1727 return -ENODEV;
1728 }
1729 } else
1730 blk_mq_unfreeze_queue(dev->admin_q);
1731
1732 return 0;
1733}
1734
1735static int nvme_configure_admin_queue(struct nvme_dev *dev)
1736{
1737 int result;
1738 u32 aqa;
1739 u64 cap = lo_hi_readq(&dev->bar->cap);
1740 struct nvme_queue *nvmeq;
1741 /*
1742 * default to a 4K page size, with the intention to update this
1743 * path in the future to accomodate architectures with differing
1744 * kernel and IO page sizes.
1745 */
1746 unsigned page_shift = 12;
1747 unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12;
1748
1749 if (page_shift < dev_page_min) {
1750 dev_err(dev->dev,
1751 "Minimum device page size (%u) too large for "
1752 "host (%u)\n", 1 << dev_page_min,
1753 1 << page_shift);
1754 return -ENODEV;
1755 }
1756
1757 dev->subsystem = readl(&dev->bar->vs) >= NVME_VS(1, 1) ?
1758 NVME_CAP_NSSRC(cap) : 0;
1759
1760 if (dev->subsystem && (readl(&dev->bar->csts) & NVME_CSTS_NSSRO))
1761 writel(NVME_CSTS_NSSRO, &dev->bar->csts);
1762
1763 result = nvme_disable_ctrl(dev, cap);
1764 if (result < 0)
1765 return result;
1766
1767 nvmeq = dev->queues[0];
1768 if (!nvmeq) {
1769 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1770 if (!nvmeq)
1771 return -ENOMEM;
1772 }
1773
1774 aqa = nvmeq->q_depth - 1;
1775 aqa |= aqa << 16;
1776
1777 dev->page_size = 1 << page_shift;
1778
1779 dev->ctrl_config = NVME_CC_CSS_NVM;
1780 dev->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT;
1781 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
1782 dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
1783
1784 writel(aqa, &dev->bar->aqa);
1785 lo_hi_writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
1786 lo_hi_writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
1787
1788 result = nvme_enable_ctrl(dev, cap);
1789 if (result)
1790 goto free_nvmeq;
1791
1792 nvmeq->cq_vector = 0;
1793 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1794 if (result) {
1795 nvmeq->cq_vector = -1;
1796 goto free_nvmeq;
1797 }
1798
1799 return result;
1800
1801 free_nvmeq:
1802 nvme_free_queues(dev, 0);
1803 return result;
1804}
1805
1806static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1807{
1808 struct nvme_dev *dev = ns->dev;
1809 struct nvme_user_io io;
1810 struct nvme_command c;
1811 unsigned length, meta_len;
1812 int status, write;
1813 dma_addr_t meta_dma = 0;
1814 void *meta = NULL;
1815 void __user *metadata;
1816
1817 if (copy_from_user(&io, uio, sizeof(io)))
1818 return -EFAULT;
1819
1820 switch (io.opcode) {
1821 case nvme_cmd_write:
1822 case nvme_cmd_read:
1823 case nvme_cmd_compare:
1824 break;
1825 default:
1826 return -EINVAL;
1827 }
1828
1829 length = (io.nblocks + 1) << ns->lba_shift;
1830 meta_len = (io.nblocks + 1) * ns->ms;
1831 metadata = (void __user *)(uintptr_t)io.metadata;
1832 write = io.opcode & 1;
1833
1834 if (ns->ext) {
1835 length += meta_len;
1836 meta_len = 0;
1837 }
1838 if (meta_len) {
1839 if (((io.metadata & 3) || !io.metadata) && !ns->ext)
1840 return -EINVAL;
1841
1842 meta = dma_alloc_coherent(dev->dev, meta_len,
1843 &meta_dma, GFP_KERNEL);
1844
1845 if (!meta) {
1846 status = -ENOMEM;
1847 goto unmap;
1848 }
1849 if (write) {
1850 if (copy_from_user(meta, metadata, meta_len)) {
1851 status = -EFAULT;
1852 goto unmap;
1853 }
1854 }
1855 }
1856
1857 memset(&c, 0, sizeof(c));
1858 c.rw.opcode = io.opcode;
1859 c.rw.flags = io.flags;
1860 c.rw.nsid = cpu_to_le32(ns->ns_id);
1861 c.rw.slba = cpu_to_le64(io.slba);
1862 c.rw.length = cpu_to_le16(io.nblocks);
1863 c.rw.control = cpu_to_le16(io.control);
1864 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
1865 c.rw.reftag = cpu_to_le32(io.reftag);
1866 c.rw.apptag = cpu_to_le16(io.apptag);
1867 c.rw.appmask = cpu_to_le16(io.appmask);
1868 c.rw.metadata = cpu_to_le64(meta_dma);
1869
1870 status = __nvme_submit_sync_cmd(ns->queue, &c, NULL,
1871 (void __user *)(uintptr_t)io.addr, length, NULL, 0);
1872 unmap:
1873 if (meta) {
1874 if (status == NVME_SC_SUCCESS && !write) {
1875 if (copy_to_user(metadata, meta, meta_len))
1876 status = -EFAULT;
1877 }
1878 dma_free_coherent(dev->dev, meta_len, meta, meta_dma);
1879 }
1880 return status;
1881}
1882
1883static int nvme_user_cmd(struct nvme_dev *dev, struct nvme_ns *ns,
1884 struct nvme_passthru_cmd __user *ucmd)
1885{
1886 struct nvme_passthru_cmd cmd;
1887 struct nvme_command c;
1888 unsigned timeout = 0;
1889 int status;
1890
1891 if (!capable(CAP_SYS_ADMIN))
1892 return -EACCES;
1893 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
1894 return -EFAULT;
1895
1896 memset(&c, 0, sizeof(c));
1897 c.common.opcode = cmd.opcode;
1898 c.common.flags = cmd.flags;
1899 c.common.nsid = cpu_to_le32(cmd.nsid);
1900 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1901 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1902 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1903 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1904 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1905 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1906 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1907 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1908
1909 if (cmd.timeout_ms)
1910 timeout = msecs_to_jiffies(cmd.timeout_ms);
1911
1912 status = __nvme_submit_sync_cmd(ns ? ns->queue : dev->admin_q, &c,
1913 NULL, (void __user *)(uintptr_t)cmd.addr, cmd.data_len,
1914 &cmd.result, timeout);
1915 if (status >= 0) {
1916 if (put_user(cmd.result, &ucmd->result))
1917 return -EFAULT;
1918 }
1919
1920 return status;
1921}
1922
1923static int nvme_subsys_reset(struct nvme_dev *dev)
1924{
1925 if (!dev->subsystem)
1926 return -ENOTTY;
1927
1928 writel(0x4E564D65, &dev->bar->nssr); /* "NVMe" */
1929 return 0;
1930}
1931
1932static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1933 unsigned long arg)
1934{
1935 struct nvme_ns *ns = bdev->bd_disk->private_data;
1936
1937 switch (cmd) {
1938 case NVME_IOCTL_ID:
1939 force_successful_syscall_return();
1940 return ns->ns_id;
1941 case NVME_IOCTL_ADMIN_CMD:
1942 return nvme_user_cmd(ns->dev, NULL, (void __user *)arg);
1943 case NVME_IOCTL_IO_CMD:
1944 return nvme_user_cmd(ns->dev, ns, (void __user *)arg);
1945 case NVME_IOCTL_SUBMIT_IO:
1946 return nvme_submit_io(ns, (void __user *)arg);
1947 case SG_GET_VERSION_NUM:
1948 return nvme_sg_get_version_num((void __user *)arg);
1949 case SG_IO:
1950 return nvme_sg_io(ns, (void __user *)arg);
1951 default:
1952 return -ENOTTY;
1953 }
1954}
1955
1956#ifdef CONFIG_COMPAT
1957static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode,
1958 unsigned int cmd, unsigned long arg)
1959{
1960 switch (cmd) {
1961 case SG_IO:
1962 return -ENOIOCTLCMD;
1963 }
1964 return nvme_ioctl(bdev, mode, cmd, arg);
1965}
1966#else
1967#define nvme_compat_ioctl NULL
1968#endif
1969
1970static void nvme_free_dev(struct kref *kref);
1971static void nvme_free_ns(struct kref *kref)
1972{
1973 struct nvme_ns *ns = container_of(kref, struct nvme_ns, kref);
1974
1975 if (ns->type == NVME_NS_LIGHTNVM)
1976 nvme_nvm_unregister(ns->queue, ns->disk->disk_name);
1977
1978 spin_lock(&dev_list_lock);
1979 ns->disk->private_data = NULL;
1980 spin_unlock(&dev_list_lock);
1981
1982 kref_put(&ns->dev->kref, nvme_free_dev);
1983 put_disk(ns->disk);
1984 kfree(ns);
1985}
1986
1987static int nvme_open(struct block_device *bdev, fmode_t mode)
1988{
1989 int ret = 0;
1990 struct nvme_ns *ns;
1991
1992 spin_lock(&dev_list_lock);
1993 ns = bdev->bd_disk->private_data;
1994 if (!ns)
1995 ret = -ENXIO;
1996 else if (!kref_get_unless_zero(&ns->kref))
1997 ret = -ENXIO;
1998 spin_unlock(&dev_list_lock);
1999
2000 return ret;
2001}
2002
2003static void nvme_release(struct gendisk *disk, fmode_t mode)
2004{
2005 struct nvme_ns *ns = disk->private_data;
2006 kref_put(&ns->kref, nvme_free_ns);
2007}
2008
2009static int nvme_getgeo(struct block_device *bd, struct hd_geometry *geo)
2010{
2011 /* some standard values */
2012 geo->heads = 1 << 6;
2013 geo->sectors = 1 << 5;
2014 geo->cylinders = get_capacity(bd->bd_disk) >> 11;
2015 return 0;
2016}
2017
2018static void nvme_config_discard(struct nvme_ns *ns)
2019{
2020 u32 logical_block_size = queue_logical_block_size(ns->queue);
2021 ns->queue->limits.discard_zeroes_data = 0;
2022 ns->queue->limits.discard_alignment = logical_block_size;
2023 ns->queue->limits.discard_granularity = logical_block_size;
2024 blk_queue_max_discard_sectors(ns->queue, 0xffffffff);
2025 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
2026}
2027
2028static int nvme_revalidate_disk(struct gendisk *disk)
2029{
2030 struct nvme_ns *ns = disk->private_data;
2031 struct nvme_dev *dev = ns->dev;
2032 struct nvme_id_ns *id;
2033 u8 lbaf, pi_type;
2034 u16 old_ms;
2035 unsigned short bs;
2036
2037 if (nvme_identify_ns(dev, ns->ns_id, &id)) {
2038 dev_warn(dev->dev, "%s: Identify failure nvme%dn%d\n", __func__,
2039 dev->instance, ns->ns_id);
2040 return -ENODEV;
2041 }
2042 if (id->ncap == 0) {
2043 kfree(id);
2044 return -ENODEV;
2045 }
2046
2047 if (nvme_nvm_ns_supported(ns, id) && ns->type != NVME_NS_LIGHTNVM) {
2048 if (nvme_nvm_register(ns->queue, disk->disk_name)) {
2049 dev_warn(dev->dev,
2050 "%s: LightNVM init failure\n", __func__);
2051 kfree(id);
2052 return -ENODEV;
2053 }
2054 ns->type = NVME_NS_LIGHTNVM;
2055 }
2056
2057 old_ms = ns->ms;
2058 lbaf = id->flbas & NVME_NS_FLBAS_LBA_MASK;
2059 ns->lba_shift = id->lbaf[lbaf].ds;
2060 ns->ms = le16_to_cpu(id->lbaf[lbaf].ms);
2061 ns->ext = ns->ms && (id->flbas & NVME_NS_FLBAS_META_EXT);
2062
2063 /*
2064 * If identify namespace failed, use default 512 byte block size so
2065 * block layer can use before failing read/write for 0 capacity.
2066 */
2067 if (ns->lba_shift == 0)
2068 ns->lba_shift = 9;
2069 bs = 1 << ns->lba_shift;
2070
2071 /* XXX: PI implementation requires metadata equal t10 pi tuple size */
2072 pi_type = ns->ms == sizeof(struct t10_pi_tuple) ?
2073 id->dps & NVME_NS_DPS_PI_MASK : 0;
2074
2075 blk_mq_freeze_queue(disk->queue);
2076 if (blk_get_integrity(disk) && (ns->pi_type != pi_type ||
2077 ns->ms != old_ms ||
2078 bs != queue_logical_block_size(disk->queue) ||
2079 (ns->ms && ns->ext)))
2080 blk_integrity_unregister(disk);
2081
2082 ns->pi_type = pi_type;
2083 blk_queue_logical_block_size(ns->queue, bs);
2084
2085 if (ns->ms && !ns->ext)
2086 nvme_init_integrity(ns);
2087
2088 if ((ns->ms && !(ns->ms == 8 && ns->pi_type) &&
2089 !blk_get_integrity(disk)) ||
2090 ns->type == NVME_NS_LIGHTNVM)
2091 set_capacity(disk, 0);
2092 else
2093 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
2094
2095 if (dev->oncs & NVME_CTRL_ONCS_DSM)
2096 nvme_config_discard(ns);
2097 blk_mq_unfreeze_queue(disk->queue);
2098
2099 kfree(id);
2100 return 0;
2101}
2102
2103static char nvme_pr_type(enum pr_type type)
2104{
2105 switch (type) {
2106 case PR_WRITE_EXCLUSIVE:
2107 return 1;
2108 case PR_EXCLUSIVE_ACCESS:
2109 return 2;
2110 case PR_WRITE_EXCLUSIVE_REG_ONLY:
2111 return 3;
2112 case PR_EXCLUSIVE_ACCESS_REG_ONLY:
2113 return 4;
2114 case PR_WRITE_EXCLUSIVE_ALL_REGS:
2115 return 5;
2116 case PR_EXCLUSIVE_ACCESS_ALL_REGS:
2117 return 6;
2118 default:
2119 return 0;
2120 }
2121};
2122
2123static int nvme_pr_command(struct block_device *bdev, u32 cdw10,
2124 u64 key, u64 sa_key, u8 op)
2125{
2126 struct nvme_ns *ns = bdev->bd_disk->private_data;
2127 struct nvme_command c;
2128 u8 data[16] = { 0, };
2129
2130 put_unaligned_le64(key, &data[0]);
2131 put_unaligned_le64(sa_key, &data[8]);
2132
2133 memset(&c, 0, sizeof(c));
2134 c.common.opcode = op;
2135 c.common.nsid = cpu_to_le32(ns->ns_id);
2136 c.common.cdw10[0] = cpu_to_le32(cdw10);
2137
2138 return nvme_submit_sync_cmd(ns->queue, &c, data, 16);
2139}
2140
2141static int nvme_pr_register(struct block_device *bdev, u64 old,
2142 u64 new, unsigned flags)
2143{
2144 u32 cdw10;
2145
2146 if (flags & ~PR_FL_IGNORE_KEY)
2147 return -EOPNOTSUPP;
2148
2149 cdw10 = old ? 2 : 0;
2150 cdw10 |= (flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0;
2151 cdw10 |= (1 << 30) | (1 << 31); /* PTPL=1 */
2152 return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_register);
2153}
2154
2155static int nvme_pr_reserve(struct block_device *bdev, u64 key,
2156 enum pr_type type, unsigned flags)
2157{
2158 u32 cdw10;
2159
2160 if (flags & ~PR_FL_IGNORE_KEY)
2161 return -EOPNOTSUPP;
2162
2163 cdw10 = nvme_pr_type(type) << 8;
2164 cdw10 |= ((flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0);
2165 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_acquire);
2166}
2167
2168static int nvme_pr_preempt(struct block_device *bdev, u64 old, u64 new,
2169 enum pr_type type, bool abort)
2170{
2171 u32 cdw10 = nvme_pr_type(type) << 8 | abort ? 2 : 1;
2172 return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_acquire);
2173}
2174
2175static int nvme_pr_clear(struct block_device *bdev, u64 key)
2176{
2177 u32 cdw10 = 1 | (key ? 1 << 3 : 0);
2178 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_register);
2179}
2180
2181static int nvme_pr_release(struct block_device *bdev, u64 key, enum pr_type type)
2182{
2183 u32 cdw10 = nvme_pr_type(type) << 8 | key ? 1 << 3 : 0;
2184 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_release);
2185}
2186
2187static const struct pr_ops nvme_pr_ops = {
2188 .pr_register = nvme_pr_register,
2189 .pr_reserve = nvme_pr_reserve,
2190 .pr_release = nvme_pr_release,
2191 .pr_preempt = nvme_pr_preempt,
2192 .pr_clear = nvme_pr_clear,
2193};
2194
2195static const struct block_device_operations nvme_fops = {
2196 .owner = THIS_MODULE,
2197 .ioctl = nvme_ioctl,
2198 .compat_ioctl = nvme_compat_ioctl,
2199 .open = nvme_open,
2200 .release = nvme_release,
2201 .getgeo = nvme_getgeo,
2202 .revalidate_disk= nvme_revalidate_disk,
2203 .pr_ops = &nvme_pr_ops,
2204};
2205
2206static int nvme_kthread(void *data)
2207{
2208 struct nvme_dev *dev, *next;
2209
2210 while (!kthread_should_stop()) {
2211 set_current_state(TASK_INTERRUPTIBLE);
2212 spin_lock(&dev_list_lock);
2213 list_for_each_entry_safe(dev, next, &dev_list, node) {
2214 int i;
2215 u32 csts = readl(&dev->bar->csts);
2216
2217 if ((dev->subsystem && (csts & NVME_CSTS_NSSRO)) ||
2218 csts & NVME_CSTS_CFS) {
2219 if (!__nvme_reset(dev)) {
2220 dev_warn(dev->dev,
2221 "Failed status: %x, reset controller\n",
2222 readl(&dev->bar->csts));
2223 }
2224 continue;
2225 }
2226 for (i = 0; i < dev->queue_count; i++) {
2227 struct nvme_queue *nvmeq = dev->queues[i];
2228 if (!nvmeq)
2229 continue;
2230 spin_lock_irq(&nvmeq->q_lock);
2231 nvme_process_cq(nvmeq);
2232
2233 while ((i == 0) && (dev->event_limit > 0)) {
2234 if (nvme_submit_async_admin_req(dev))
2235 break;
2236 dev->event_limit--;
2237 }
2238 spin_unlock_irq(&nvmeq->q_lock);
2239 }
2240 }
2241 spin_unlock(&dev_list_lock);
2242 schedule_timeout(round_jiffies_relative(HZ));
2243 }
2244 return 0;
2245}
2246
2247static void nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid)
2248{
2249 struct nvme_ns *ns;
2250 struct gendisk *disk;
2251 int node = dev_to_node(dev->dev);
2252
2253 ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node);
2254 if (!ns)
2255 return;
2256
2257 ns->queue = blk_mq_init_queue(&dev->tagset);
2258 if (IS_ERR(ns->queue))
2259 goto out_free_ns;
2260 queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue);
2261 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
2262 ns->dev = dev;
2263 ns->queue->queuedata = ns;
2264
2265 disk = alloc_disk_node(0, node);
2266 if (!disk)
2267 goto out_free_queue;
2268
2269 kref_init(&ns->kref);
2270 ns->ns_id = nsid;
2271 ns->disk = disk;
2272 ns->lba_shift = 9; /* set to a default value for 512 until disk is validated */
2273 list_add_tail(&ns->list, &dev->namespaces);
2274
2275 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
2276 if (dev->max_hw_sectors) {
2277 blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors);
2278 blk_queue_max_segments(ns->queue,
2279 (dev->max_hw_sectors / (dev->page_size >> 9)) + 1);
2280 }
2281 if (dev->stripe_size)
2282 blk_queue_chunk_sectors(ns->queue, dev->stripe_size >> 9);
2283 if (dev->vwc & NVME_CTRL_VWC_PRESENT)
2284 blk_queue_flush(ns->queue, REQ_FLUSH | REQ_FUA);
2285 blk_queue_virt_boundary(ns->queue, dev->page_size - 1);
2286
2287 disk->major = nvme_major;
2288 disk->first_minor = 0;
2289 disk->fops = &nvme_fops;
2290 disk->private_data = ns;
2291 disk->queue = ns->queue;
2292 disk->driverfs_dev = dev->device;
2293 disk->flags = GENHD_FL_EXT_DEVT;
2294 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
2295
2296 /*
2297 * Initialize capacity to 0 until we establish the namespace format and
2298 * setup integrity extentions if necessary. The revalidate_disk after
2299 * add_disk allows the driver to register with integrity if the format
2300 * requires it.
2301 */
2302 set_capacity(disk, 0);
2303 if (nvme_revalidate_disk(ns->disk))
2304 goto out_free_disk;
2305
2306 kref_get(&dev->kref);
2307 if (ns->type != NVME_NS_LIGHTNVM) {
2308 add_disk(ns->disk);
2309 if (ns->ms) {
2310 struct block_device *bd = bdget_disk(ns->disk, 0);
2311 if (!bd)
2312 return;
2313 if (blkdev_get(bd, FMODE_READ, NULL)) {
2314 bdput(bd);
2315 return;
2316 }
2317 blkdev_reread_part(bd);
2318 blkdev_put(bd, FMODE_READ);
2319 }
2320 }
2321 return;
2322 out_free_disk:
2323 kfree(disk);
2324 list_del(&ns->list);
2325 out_free_queue:
2326 blk_cleanup_queue(ns->queue);
2327 out_free_ns:
2328 kfree(ns);
2329}
2330
2331/*
2332 * Create I/O queues. Failing to create an I/O queue is not an issue,
2333 * we can continue with less than the desired amount of queues, and
2334 * even a controller without I/O queues an still be used to issue
2335 * admin commands. This might be useful to upgrade a buggy firmware
2336 * for example.
2337 */
2338static void nvme_create_io_queues(struct nvme_dev *dev)
2339{
2340 unsigned i;
2341
2342 for (i = dev->queue_count; i <= dev->max_qid; i++)
2343 if (!nvme_alloc_queue(dev, i, dev->q_depth))
2344 break;
2345
2346 for (i = dev->online_queues; i <= dev->queue_count - 1; i++)
2347 if (nvme_create_queue(dev->queues[i], i)) {
2348 nvme_free_queues(dev, i);
2349 break;
2350 }
2351}
2352
2353static int set_queue_count(struct nvme_dev *dev, int count)
2354{
2355 int status;
2356 u32 result;
2357 u32 q_count = (count - 1) | ((count - 1) << 16);
2358
2359 status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
2360 &result);
2361 if (status < 0)
2362 return status;
2363 if (status > 0) {
2364 dev_err(dev->dev, "Could not set queue count (%d)\n", status);
2365 return 0;
2366 }
2367 return min(result & 0xffff, result >> 16) + 1;
2368}
2369
2370static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
2371{
2372 u64 szu, size, offset;
2373 u32 cmbloc;
2374 resource_size_t bar_size;
2375 struct pci_dev *pdev = to_pci_dev(dev->dev);
2376 void __iomem *cmb;
2377 dma_addr_t dma_addr;
2378
2379 if (!use_cmb_sqes)
2380 return NULL;
2381
2382 dev->cmbsz = readl(&dev->bar->cmbsz);
2383 if (!(NVME_CMB_SZ(dev->cmbsz)))
2384 return NULL;
2385
2386 cmbloc = readl(&dev->bar->cmbloc);
2387
2388 szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
2389 size = szu * NVME_CMB_SZ(dev->cmbsz);
2390 offset = szu * NVME_CMB_OFST(cmbloc);
2391 bar_size = pci_resource_len(pdev, NVME_CMB_BIR(cmbloc));
2392
2393 if (offset > bar_size)
2394 return NULL;
2395
2396 /*
2397 * Controllers may support a CMB size larger than their BAR,
2398 * for example, due to being behind a bridge. Reduce the CMB to
2399 * the reported size of the BAR
2400 */
2401 if (size > bar_size - offset)
2402 size = bar_size - offset;
2403
2404 dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(cmbloc)) + offset;
2405 cmb = ioremap_wc(dma_addr, size);
2406 if (!cmb)
2407 return NULL;
2408
2409 dev->cmb_dma_addr = dma_addr;
2410 dev->cmb_size = size;
2411 return cmb;
2412}
2413
2414static inline void nvme_release_cmb(struct nvme_dev *dev)
2415{
2416 if (dev->cmb) {
2417 iounmap(dev->cmb);
2418 dev->cmb = NULL;
2419 }
2420}
2421
2422static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
2423{
2424 return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
2425}
2426
2427static int nvme_setup_io_queues(struct nvme_dev *dev)
2428{
2429 struct nvme_queue *adminq = dev->queues[0];
2430 struct pci_dev *pdev = to_pci_dev(dev->dev);
2431 int result, i, vecs, nr_io_queues, size;
2432
2433 nr_io_queues = num_possible_cpus();
2434 result = set_queue_count(dev, nr_io_queues);
2435 if (result <= 0)
2436 return result;
2437 if (result < nr_io_queues)
2438 nr_io_queues = result;
2439
2440 if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) {
2441 result = nvme_cmb_qdepth(dev, nr_io_queues,
2442 sizeof(struct nvme_command));
2443 if (result > 0)
2444 dev->q_depth = result;
2445 else
2446 nvme_release_cmb(dev);
2447 }
2448
2449 size = db_bar_size(dev, nr_io_queues);
2450 if (size > 8192) {
2451 iounmap(dev->bar);
2452 do {
2453 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
2454 if (dev->bar)
2455 break;
2456 if (!--nr_io_queues)
2457 return -ENOMEM;
2458 size = db_bar_size(dev, nr_io_queues);
2459 } while (1);
2460 dev->dbs = ((void __iomem *)dev->bar) + 4096;
2461 adminq->q_db = dev->dbs;
2462 }
2463
2464 /* Deregister the admin queue's interrupt */
2465 free_irq(dev->entry[0].vector, adminq);
2466
2467 /*
2468 * If we enable msix early due to not intx, disable it again before
2469 * setting up the full range we need.
2470 */
2471 if (!pdev->irq)
2472 pci_disable_msix(pdev);
2473
2474 for (i = 0; i < nr_io_queues; i++)
2475 dev->entry[i].entry = i;
2476 vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
2477 if (vecs < 0) {
2478 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
2479 if (vecs < 0) {
2480 vecs = 1;
2481 } else {
2482 for (i = 0; i < vecs; i++)
2483 dev->entry[i].vector = i + pdev->irq;
2484 }
2485 }
2486
2487 /*
2488 * Should investigate if there's a performance win from allocating
2489 * more queues than interrupt vectors; it might allow the submission
2490 * path to scale better, even if the receive path is limited by the
2491 * number of interrupts.
2492 */
2493 nr_io_queues = vecs;
2494 dev->max_qid = nr_io_queues;
2495
2496 result = queue_request_irq(dev, adminq, adminq->irqname);
2497 if (result) {
2498 adminq->cq_vector = -1;
2499 goto free_queues;
2500 }
2501
2502 /* Free previously allocated queues that are no longer usable */
2503 nvme_free_queues(dev, nr_io_queues + 1);
2504 nvme_create_io_queues(dev);
2505
2506 return 0;
2507
2508 free_queues:
2509 nvme_free_queues(dev, 1);
2510 return result;
2511}
2512
2513static int ns_cmp(void *priv, struct list_head *a, struct list_head *b)
2514{
2515 struct nvme_ns *nsa = container_of(a, struct nvme_ns, list);
2516 struct nvme_ns *nsb = container_of(b, struct nvme_ns, list);
2517
2518 return nsa->ns_id - nsb->ns_id;
2519}
2520
2521static struct nvme_ns *nvme_find_ns(struct nvme_dev *dev, unsigned nsid)
2522{
2523 struct nvme_ns *ns;
2524
2525 list_for_each_entry(ns, &dev->namespaces, list) {
2526 if (ns->ns_id == nsid)
2527 return ns;
2528 if (ns->ns_id > nsid)
2529 break;
2530 }
2531 return NULL;
2532}
2533
2534static inline bool nvme_io_incapable(struct nvme_dev *dev)
2535{
2536 return (!dev->bar || readl(&dev->bar->csts) & NVME_CSTS_CFS ||
2537 dev->online_queues < 2);
2538}
2539
2540static void nvme_ns_remove(struct nvme_ns *ns)
2541{
2542 bool kill = nvme_io_incapable(ns->dev) && !blk_queue_dying(ns->queue);
2543
2544 if (kill)
2545 blk_set_queue_dying(ns->queue);
2546 if (ns->disk->flags & GENHD_FL_UP)
2547 del_gendisk(ns->disk);
2548 if (kill || !blk_queue_dying(ns->queue)) {
2549 blk_mq_abort_requeue_list(ns->queue);
2550 blk_cleanup_queue(ns->queue);
2551 }
2552 list_del_init(&ns->list);
2553 kref_put(&ns->kref, nvme_free_ns);
2554}
2555
2556static void nvme_scan_namespaces(struct nvme_dev *dev, unsigned nn)
2557{
2558 struct nvme_ns *ns, *next;
2559 unsigned i;
2560
2561 for (i = 1; i <= nn; i++) {
2562 ns = nvme_find_ns(dev, i);
2563 if (ns) {
2564 if (revalidate_disk(ns->disk))
2565 nvme_ns_remove(ns);
2566 } else
2567 nvme_alloc_ns(dev, i);
2568 }
2569 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
2570 if (ns->ns_id > nn)
2571 nvme_ns_remove(ns);
2572 }
2573 list_sort(NULL, &dev->namespaces, ns_cmp);
2574}
2575
2576static void nvme_set_irq_hints(struct nvme_dev *dev)
2577{
2578 struct nvme_queue *nvmeq;
2579 int i;
2580
2581 for (i = 0; i < dev->online_queues; i++) {
2582 nvmeq = dev->queues[i];
2583
2584 if (!nvmeq->tags || !(*nvmeq->tags))
2585 continue;
2586
2587 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
2588 blk_mq_tags_cpumask(*nvmeq->tags));
2589 }
2590}
2591
2592static void nvme_dev_scan(struct work_struct *work)
2593{
2594 struct nvme_dev *dev = container_of(work, struct nvme_dev, scan_work);
2595 struct nvme_id_ctrl *ctrl;
2596
2597 if (!dev->tagset.tags)
2598 return;
2599 if (nvme_identify_ctrl(dev, &ctrl))
2600 return;
2601 nvme_scan_namespaces(dev, le32_to_cpup(&ctrl->nn));
2602 kfree(ctrl);
2603 nvme_set_irq_hints(dev);
2604}
2605
2606/*
2607 * Return: error value if an error occurred setting up the queues or calling
2608 * Identify Device. 0 if these succeeded, even if adding some of the
2609 * namespaces failed. At the moment, these failures are silent. TBD which
2610 * failures should be reported.
2611 */
2612static int nvme_dev_add(struct nvme_dev *dev)
2613{
2614 struct pci_dev *pdev = to_pci_dev(dev->dev);
2615 int res;
2616 struct nvme_id_ctrl *ctrl;
2617 int shift = NVME_CAP_MPSMIN(lo_hi_readq(&dev->bar->cap)) + 12;
2618
2619 res = nvme_identify_ctrl(dev, &ctrl);
2620 if (res) {
2621 dev_err(dev->dev, "Identify Controller failed (%d)\n", res);
2622 return -EIO;
2623 }
2624
2625 dev->oncs = le16_to_cpup(&ctrl->oncs);
2626 dev->abort_limit = ctrl->acl + 1;
2627 dev->vwc = ctrl->vwc;
2628 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
2629 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
2630 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
2631 if (ctrl->mdts)
2632 dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9);
2633 else
2634 dev->max_hw_sectors = UINT_MAX;
2635 if ((pdev->vendor == PCI_VENDOR_ID_INTEL) &&
2636 (pdev->device == 0x0953) && ctrl->vs[3]) {
2637 unsigned int max_hw_sectors;
2638
2639 dev->stripe_size = 1 << (ctrl->vs[3] + shift);
2640 max_hw_sectors = dev->stripe_size >> (shift - 9);
2641 if (dev->max_hw_sectors) {
2642 dev->max_hw_sectors = min(max_hw_sectors,
2643 dev->max_hw_sectors);
2644 } else
2645 dev->max_hw_sectors = max_hw_sectors;
2646 }
2647 kfree(ctrl);
2648
2649 if (!dev->tagset.tags) {
2650 dev->tagset.ops = &nvme_mq_ops;
2651 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2652 dev->tagset.timeout = NVME_IO_TIMEOUT;
2653 dev->tagset.numa_node = dev_to_node(dev->dev);
2654 dev->tagset.queue_depth =
2655 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
2656 dev->tagset.cmd_size = nvme_cmd_size(dev);
2657 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2658 dev->tagset.driver_data = dev;
2659
2660 if (blk_mq_alloc_tag_set(&dev->tagset))
2661 return 0;
2662 }
2663 schedule_work(&dev->scan_work);
2664 return 0;
2665}
2666
2667static int nvme_dev_map(struct nvme_dev *dev)
2668{
2669 u64 cap;
2670 int bars, result = -ENOMEM;
2671 struct pci_dev *pdev = to_pci_dev(dev->dev);
2672
2673 if (pci_enable_device_mem(pdev))
2674 return result;
2675
2676 dev->entry[0].vector = pdev->irq;
2677 pci_set_master(pdev);
2678 bars = pci_select_bars(pdev, IORESOURCE_MEM);
2679 if (!bars)
2680 goto disable_pci;
2681
2682 if (pci_request_selected_regions(pdev, bars, "nvme"))
2683 goto disable_pci;
2684
2685 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
2686 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
2687 goto disable;
2688
2689 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
2690 if (!dev->bar)
2691 goto disable;
2692
2693 if (readl(&dev->bar->csts) == -1) {
2694 result = -ENODEV;
2695 goto unmap;
2696 }
2697
2698 /*
2699 * Some devices don't advertse INTx interrupts, pre-enable a single
2700 * MSIX vec for setup. We'll adjust this later.
2701 */
2702 if (!pdev->irq) {
2703 result = pci_enable_msix(pdev, dev->entry, 1);
2704 if (result < 0)
2705 goto unmap;
2706 }
2707
2708 cap = lo_hi_readq(&dev->bar->cap);
2709 dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
2710 dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
2711 dev->dbs = ((void __iomem *)dev->bar) + 4096;
2712 if (readl(&dev->bar->vs) >= NVME_VS(1, 2))
2713 dev->cmb = nvme_map_cmb(dev);
2714
2715 return 0;
2716
2717 unmap:
2718 iounmap(dev->bar);
2719 dev->bar = NULL;
2720 disable:
2721 pci_release_regions(pdev);
2722 disable_pci:
2723 pci_disable_device(pdev);
2724 return result;
2725}
2726
2727static void nvme_dev_unmap(struct nvme_dev *dev)
2728{
2729 struct pci_dev *pdev = to_pci_dev(dev->dev);
2730
2731 if (pdev->msi_enabled)
2732 pci_disable_msi(pdev);
2733 else if (pdev->msix_enabled)
2734 pci_disable_msix(pdev);
2735
2736 if (dev->bar) {
2737 iounmap(dev->bar);
2738 dev->bar = NULL;
2739 pci_release_regions(pdev);
2740 }
2741
2742 if (pci_is_enabled(pdev))
2743 pci_disable_device(pdev);
2744}
2745
2746struct nvme_delq_ctx {
2747 struct task_struct *waiter;
2748 struct kthread_worker *worker;
2749 atomic_t refcount;
2750};
2751
2752static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev)
2753{
2754 dq->waiter = current;
2755 mb();
2756
2757 for (;;) {
2758 set_current_state(TASK_KILLABLE);
2759 if (!atomic_read(&dq->refcount))
2760 break;
2761 if (!schedule_timeout(ADMIN_TIMEOUT) ||
2762 fatal_signal_pending(current)) {
2763 /*
2764 * Disable the controller first since we can't trust it
2765 * at this point, but leave the admin queue enabled
2766 * until all queue deletion requests are flushed.
2767 * FIXME: This may take a while if there are more h/w
2768 * queues than admin tags.
2769 */
2770 set_current_state(TASK_RUNNING);
2771 nvme_disable_ctrl(dev, lo_hi_readq(&dev->bar->cap));
2772 nvme_clear_queue(dev->queues[0]);
2773 flush_kthread_worker(dq->worker);
2774 nvme_disable_queue(dev, 0);
2775 return;
2776 }
2777 }
2778 set_current_state(TASK_RUNNING);
2779}
2780
2781static void nvme_put_dq(struct nvme_delq_ctx *dq)
2782{
2783 atomic_dec(&dq->refcount);
2784 if (dq->waiter)
2785 wake_up_process(dq->waiter);
2786}
2787
2788static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq)
2789{
2790 atomic_inc(&dq->refcount);
2791 return dq;
2792}
2793
2794static void nvme_del_queue_end(struct nvme_queue *nvmeq)
2795{
2796 struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx;
2797 nvme_put_dq(dq);
2798
2799 spin_lock_irq(&nvmeq->q_lock);
2800 nvme_process_cq(nvmeq);
2801 spin_unlock_irq(&nvmeq->q_lock);
2802}
2803
2804static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode,
2805 kthread_work_func_t fn)
2806{
2807 struct nvme_command c;
2808
2809 memset(&c, 0, sizeof(c));
2810 c.delete_queue.opcode = opcode;
2811 c.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2812
2813 init_kthread_work(&nvmeq->cmdinfo.work, fn);
2814 return nvme_submit_admin_async_cmd(nvmeq->dev, &c, &nvmeq->cmdinfo,
2815 ADMIN_TIMEOUT);
2816}
2817
2818static void nvme_del_cq_work_handler(struct kthread_work *work)
2819{
2820 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2821 cmdinfo.work);
2822 nvme_del_queue_end(nvmeq);
2823}
2824
2825static int nvme_delete_cq(struct nvme_queue *nvmeq)
2826{
2827 return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq,
2828 nvme_del_cq_work_handler);
2829}
2830
2831static void nvme_del_sq_work_handler(struct kthread_work *work)
2832{
2833 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2834 cmdinfo.work);
2835 int status = nvmeq->cmdinfo.status;
2836
2837 if (!status)
2838 status = nvme_delete_cq(nvmeq);
2839 if (status)
2840 nvme_del_queue_end(nvmeq);
2841}
2842
2843static int nvme_delete_sq(struct nvme_queue *nvmeq)
2844{
2845 return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq,
2846 nvme_del_sq_work_handler);
2847}
2848
2849static void nvme_del_queue_start(struct kthread_work *work)
2850{
2851 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2852 cmdinfo.work);
2853 if (nvme_delete_sq(nvmeq))
2854 nvme_del_queue_end(nvmeq);
2855}
2856
2857static void nvme_disable_io_queues(struct nvme_dev *dev)
2858{
2859 int i;
2860 DEFINE_KTHREAD_WORKER_ONSTACK(worker);
2861 struct nvme_delq_ctx dq;
2862 struct task_struct *kworker_task = kthread_run(kthread_worker_fn,
2863 &worker, "nvme%d", dev->instance);
2864
2865 if (IS_ERR(kworker_task)) {
2866 dev_err(dev->dev,
2867 "Failed to create queue del task\n");
2868 for (i = dev->queue_count - 1; i > 0; i--)
2869 nvme_disable_queue(dev, i);
2870 return;
2871 }
2872
2873 dq.waiter = NULL;
2874 atomic_set(&dq.refcount, 0);
2875 dq.worker = &worker;
2876 for (i = dev->queue_count - 1; i > 0; i--) {
2877 struct nvme_queue *nvmeq = dev->queues[i];
2878
2879 if (nvme_suspend_queue(nvmeq))
2880 continue;
2881 nvmeq->cmdinfo.ctx = nvme_get_dq(&dq);
2882 nvmeq->cmdinfo.worker = dq.worker;
2883 init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start);
2884 queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work);
2885 }
2886 nvme_wait_dq(&dq, dev);
2887 kthread_stop(kworker_task);
2888}
2889
2890/*
2891* Remove the node from the device list and check
2892* for whether or not we need to stop the nvme_thread.
2893*/
2894static void nvme_dev_list_remove(struct nvme_dev *dev)
2895{
2896 struct task_struct *tmp = NULL;
2897
2898 spin_lock(&dev_list_lock);
2899 list_del_init(&dev->node);
2900 if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) {
2901 tmp = nvme_thread;
2902 nvme_thread = NULL;
2903 }
2904 spin_unlock(&dev_list_lock);
2905
2906 if (tmp)
2907 kthread_stop(tmp);
2908}
2909
2910static void nvme_freeze_queues(struct nvme_dev *dev)
2911{
2912 struct nvme_ns *ns;
2913
2914 list_for_each_entry(ns, &dev->namespaces, list) {
2915 blk_mq_freeze_queue_start(ns->queue);
2916
2917 spin_lock_irq(ns->queue->queue_lock);
2918 queue_flag_set(QUEUE_FLAG_STOPPED, ns->queue);
2919 spin_unlock_irq(ns->queue->queue_lock);
2920
2921 blk_mq_cancel_requeue_work(ns->queue);
2922 blk_mq_stop_hw_queues(ns->queue);
2923 }
2924}
2925
2926static void nvme_unfreeze_queues(struct nvme_dev *dev)
2927{
2928 struct nvme_ns *ns;
2929
2930 list_for_each_entry(ns, &dev->namespaces, list) {
2931 queue_flag_clear_unlocked(QUEUE_FLAG_STOPPED, ns->queue);
2932 blk_mq_unfreeze_queue(ns->queue);
2933 blk_mq_start_stopped_hw_queues(ns->queue, true);
2934 blk_mq_kick_requeue_list(ns->queue);
2935 }
2936}
2937
2938static void nvme_dev_shutdown(struct nvme_dev *dev)
2939{
2940 int i;
2941 u32 csts = -1;
2942
2943 nvme_dev_list_remove(dev);
2944
2945 if (dev->bar) {
2946 nvme_freeze_queues(dev);
2947 csts = readl(&dev->bar->csts);
2948 }
2949 if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
2950 for (i = dev->queue_count - 1; i >= 0; i--) {
2951 struct nvme_queue *nvmeq = dev->queues[i];
2952 nvme_suspend_queue(nvmeq);
2953 }
2954 } else {
2955 nvme_disable_io_queues(dev);
2956 nvme_shutdown_ctrl(dev);
2957 nvme_disable_queue(dev, 0);
2958 }
2959 nvme_dev_unmap(dev);
2960
2961 for (i = dev->queue_count - 1; i >= 0; i--)
2962 nvme_clear_queue(dev->queues[i]);
2963}
2964
2965static void nvme_dev_remove(struct nvme_dev *dev)
2966{
2967 struct nvme_ns *ns, *next;
2968
2969 list_for_each_entry_safe(ns, next, &dev->namespaces, list)
2970 nvme_ns_remove(ns);
2971}
2972
2973static int nvme_setup_prp_pools(struct nvme_dev *dev)
2974{
2975 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2976 PAGE_SIZE, PAGE_SIZE, 0);
2977 if (!dev->prp_page_pool)
2978 return -ENOMEM;
2979
2980 /* Optimisation for I/Os between 4k and 128k */
2981 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2982 256, 256, 0);
2983 if (!dev->prp_small_pool) {
2984 dma_pool_destroy(dev->prp_page_pool);
2985 return -ENOMEM;
2986 }
2987 return 0;
2988}
2989
2990static void nvme_release_prp_pools(struct nvme_dev *dev)
2991{
2992 dma_pool_destroy(dev->prp_page_pool);
2993 dma_pool_destroy(dev->prp_small_pool);
2994}
2995
2996static DEFINE_IDA(nvme_instance_ida);
2997
2998static int nvme_set_instance(struct nvme_dev *dev)
2999{
3000 int instance, error;
3001
3002 do {
3003 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
3004 return -ENODEV;
3005
3006 spin_lock(&dev_list_lock);
3007 error = ida_get_new(&nvme_instance_ida, &instance);
3008 spin_unlock(&dev_list_lock);
3009 } while (error == -EAGAIN);
3010
3011 if (error)
3012 return -ENODEV;
3013
3014 dev->instance = instance;
3015 return 0;
3016}
3017
3018static void nvme_release_instance(struct nvme_dev *dev)
3019{
3020 spin_lock(&dev_list_lock);
3021 ida_remove(&nvme_instance_ida, dev->instance);
3022 spin_unlock(&dev_list_lock);
3023}
3024
3025static void nvme_free_dev(struct kref *kref)
3026{
3027 struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref);
3028
3029 put_device(dev->dev);
3030 put_device(dev->device);
3031 nvme_release_instance(dev);
3032 if (dev->tagset.tags)
3033 blk_mq_free_tag_set(&dev->tagset);
3034 if (dev->admin_q)
3035 blk_put_queue(dev->admin_q);
3036 kfree(dev->queues);
3037 kfree(dev->entry);
3038 kfree(dev);
3039}
3040
3041static int nvme_dev_open(struct inode *inode, struct file *f)
3042{
3043 struct nvme_dev *dev;
3044 int instance = iminor(inode);
3045 int ret = -ENODEV;
3046
3047 spin_lock(&dev_list_lock);
3048 list_for_each_entry(dev, &dev_list, node) {
3049 if (dev->instance == instance) {
3050 if (!dev->admin_q) {
3051 ret = -EWOULDBLOCK;
3052 break;
3053 }
3054 if (!kref_get_unless_zero(&dev->kref))
3055 break;
3056 f->private_data = dev;
3057 ret = 0;
3058 break;
3059 }
3060 }
3061 spin_unlock(&dev_list_lock);
3062
3063 return ret;
3064}
3065
3066static int nvme_dev_release(struct inode *inode, struct file *f)
3067{
3068 struct nvme_dev *dev = f->private_data;
3069 kref_put(&dev->kref, nvme_free_dev);
3070 return 0;
3071}
3072
3073static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
3074{
3075 struct nvme_dev *dev = f->private_data;
3076 struct nvme_ns *ns;
3077
3078 switch (cmd) {
3079 case NVME_IOCTL_ADMIN_CMD:
3080 return nvme_user_cmd(dev, NULL, (void __user *)arg);
3081 case NVME_IOCTL_IO_CMD:
3082 if (list_empty(&dev->namespaces))
3083 return -ENOTTY;
3084 ns = list_first_entry(&dev->namespaces, struct nvme_ns, list);
3085 return nvme_user_cmd(dev, ns, (void __user *)arg);
3086 case NVME_IOCTL_RESET:
3087 dev_warn(dev->dev, "resetting controller\n");
3088 return nvme_reset(dev);
3089 case NVME_IOCTL_SUBSYS_RESET:
3090 return nvme_subsys_reset(dev);
3091 default:
3092 return -ENOTTY;
3093 }
3094}
3095
3096static const struct file_operations nvme_dev_fops = {
3097 .owner = THIS_MODULE,
3098 .open = nvme_dev_open,
3099 .release = nvme_dev_release,
3100 .unlocked_ioctl = nvme_dev_ioctl,
3101 .compat_ioctl = nvme_dev_ioctl,
3102};
3103
3104static void nvme_probe_work(struct work_struct *work)
3105{
3106 struct nvme_dev *dev = container_of(work, struct nvme_dev, probe_work);
3107 bool start_thread = false;
3108 int result;
3109
3110 result = nvme_dev_map(dev);
3111 if (result)
3112 goto out;
3113
3114 result = nvme_configure_admin_queue(dev);
3115 if (result)
3116 goto unmap;
3117
3118 spin_lock(&dev_list_lock);
3119 if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) {
3120 start_thread = true;
3121 nvme_thread = NULL;
3122 }
3123 list_add(&dev->node, &dev_list);
3124 spin_unlock(&dev_list_lock);
3125
3126 if (start_thread) {
3127 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
3128 wake_up_all(&nvme_kthread_wait);
3129 } else
3130 wait_event_killable(nvme_kthread_wait, nvme_thread);
3131
3132 if (IS_ERR_OR_NULL(nvme_thread)) {
3133 result = nvme_thread ? PTR_ERR(nvme_thread) : -EINTR;
3134 goto disable;
3135 }
3136
3137 nvme_init_queue(dev->queues[0], 0);
3138 result = nvme_alloc_admin_tags(dev);
3139 if (result)
3140 goto disable;
3141
3142 result = nvme_setup_io_queues(dev);
3143 if (result)
3144 goto free_tags;
3145
3146 dev->event_limit = 1;
3147
3148 /*
3149 * Keep the controller around but remove all namespaces if we don't have
3150 * any working I/O queue.
3151 */
3152 if (dev->online_queues < 2) {
3153 dev_warn(dev->dev, "IO queues not created\n");
3154 nvme_dev_remove(dev);
3155 } else {
3156 nvme_unfreeze_queues(dev);
3157 nvme_dev_add(dev);
3158 }
3159
3160 return;
3161
3162 free_tags:
3163 nvme_dev_remove_admin(dev);
3164 blk_put_queue(dev->admin_q);
3165 dev->admin_q = NULL;
3166 dev->queues[0]->tags = NULL;
3167 disable:
3168 nvme_disable_queue(dev, 0);
3169 nvme_dev_list_remove(dev);
3170 unmap:
3171 nvme_dev_unmap(dev);
3172 out:
3173 if (!work_busy(&dev->reset_work))
3174 nvme_dead_ctrl(dev);
3175}
3176
3177static int nvme_remove_dead_ctrl(void *arg)
3178{
3179 struct nvme_dev *dev = (struct nvme_dev *)arg;
3180 struct pci_dev *pdev = to_pci_dev(dev->dev);
3181
3182 if (pci_get_drvdata(pdev))
3183 pci_stop_and_remove_bus_device_locked(pdev);
3184 kref_put(&dev->kref, nvme_free_dev);
3185 return 0;
3186}
3187
3188static void nvme_dead_ctrl(struct nvme_dev *dev)
3189{
3190 dev_warn(dev->dev, "Device failed to resume\n");
3191 kref_get(&dev->kref);
3192 if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d",
3193 dev->instance))) {
3194 dev_err(dev->dev,
3195 "Failed to start controller remove task\n");
3196 kref_put(&dev->kref, nvme_free_dev);
3197 }
3198}
3199
3200static void nvme_reset_work(struct work_struct *ws)
3201{
3202 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
3203 bool in_probe = work_busy(&dev->probe_work);
3204
3205 nvme_dev_shutdown(dev);
3206
3207 /* Synchronize with device probe so that work will see failure status
3208 * and exit gracefully without trying to schedule another reset */
3209 flush_work(&dev->probe_work);
3210
3211 /* Fail this device if reset occured during probe to avoid
3212 * infinite initialization loops. */
3213 if (in_probe) {
3214 nvme_dead_ctrl(dev);
3215 return;
3216 }
3217 /* Schedule device resume asynchronously so the reset work is available
3218 * to cleanup errors that may occur during reinitialization */
3219 schedule_work(&dev->probe_work);
3220}
3221
3222static int __nvme_reset(struct nvme_dev *dev)
3223{
3224 if (work_pending(&dev->reset_work))
3225 return -EBUSY;
3226 list_del_init(&dev->node);
3227 queue_work(nvme_workq, &dev->reset_work);
3228 return 0;
3229}
3230
3231static int nvme_reset(struct nvme_dev *dev)
3232{
3233 int ret;
3234
3235 if (!dev->admin_q || blk_queue_dying(dev->admin_q))
3236 return -ENODEV;
3237
3238 spin_lock(&dev_list_lock);
3239 ret = __nvme_reset(dev);
3240 spin_unlock(&dev_list_lock);
3241
3242 if (!ret) {
3243 flush_work(&dev->reset_work);
3244 flush_work(&dev->probe_work);
3245 return 0;
3246 }
3247
3248 return ret;
3249}
3250
3251static ssize_t nvme_sysfs_reset(struct device *dev,
3252 struct device_attribute *attr, const char *buf,
3253 size_t count)
3254{
3255 struct nvme_dev *ndev = dev_get_drvdata(dev);
3256 int ret;
3257
3258 ret = nvme_reset(ndev);
3259 if (ret < 0)
3260 return ret;
3261
3262 return count;
3263}
3264static DEVICE_ATTR(reset_controller, S_IWUSR, NULL, nvme_sysfs_reset);
3265
3266static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
3267{
3268 int node, result = -ENOMEM;
3269 struct nvme_dev *dev;
3270
3271 node = dev_to_node(&pdev->dev);
3272 if (node == NUMA_NO_NODE)
3273 set_dev_node(&pdev->dev, 0);
3274
3275 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
3276 if (!dev)
3277 return -ENOMEM;
3278 dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry),
3279 GFP_KERNEL, node);
3280 if (!dev->entry)
3281 goto free;
3282 dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
3283 GFP_KERNEL, node);
3284 if (!dev->queues)
3285 goto free;
3286
3287 INIT_LIST_HEAD(&dev->namespaces);
3288 INIT_WORK(&dev->reset_work, nvme_reset_work);
3289 dev->dev = get_device(&pdev->dev);
3290 pci_set_drvdata(pdev, dev);
3291 result = nvme_set_instance(dev);
3292 if (result)
3293 goto put_pci;
3294
3295 result = nvme_setup_prp_pools(dev);
3296 if (result)
3297 goto release;
3298
3299 kref_init(&dev->kref);
3300 dev->device = device_create(nvme_class, &pdev->dev,
3301 MKDEV(nvme_char_major, dev->instance),
3302 dev, "nvme%d", dev->instance);
3303 if (IS_ERR(dev->device)) {
3304 result = PTR_ERR(dev->device);
3305 goto release_pools;
3306 }
3307 get_device(dev->device);
3308 dev_set_drvdata(dev->device, dev);
3309
3310 result = device_create_file(dev->device, &dev_attr_reset_controller);
3311 if (result)
3312 goto put_dev;
3313
3314 INIT_LIST_HEAD(&dev->node);
3315 INIT_WORK(&dev->scan_work, nvme_dev_scan);
3316 INIT_WORK(&dev->probe_work, nvme_probe_work);
3317 schedule_work(&dev->probe_work);
3318 return 0;
3319
3320 put_dev:
3321 device_destroy(nvme_class, MKDEV(nvme_char_major, dev->instance));
3322 put_device(dev->device);
3323 release_pools:
3324 nvme_release_prp_pools(dev);
3325 release:
3326 nvme_release_instance(dev);
3327 put_pci:
3328 put_device(dev->dev);
3329 free:
3330 kfree(dev->queues);
3331 kfree(dev->entry);
3332 kfree(dev);
3333 return result;
3334}
3335
3336static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
3337{
3338 struct nvme_dev *dev = pci_get_drvdata(pdev);
3339
3340 if (prepare)
3341 nvme_dev_shutdown(dev);
3342 else
3343 schedule_work(&dev->probe_work);
3344}
3345
3346static void nvme_shutdown(struct pci_dev *pdev)
3347{
3348 struct nvme_dev *dev = pci_get_drvdata(pdev);
3349 nvme_dev_shutdown(dev);
3350}
3351
3352static void nvme_remove(struct pci_dev *pdev)
3353{
3354 struct nvme_dev *dev = pci_get_drvdata(pdev);
3355
3356 spin_lock(&dev_list_lock);
3357 list_del_init(&dev->node);
3358 spin_unlock(&dev_list_lock);
3359
3360 pci_set_drvdata(pdev, NULL);
3361 flush_work(&dev->probe_work);
3362 flush_work(&dev->reset_work);
3363 flush_work(&dev->scan_work);
3364 device_remove_file(dev->device, &dev_attr_reset_controller);
3365 nvme_dev_remove(dev);
3366 nvme_dev_shutdown(dev);
3367 nvme_dev_remove_admin(dev);
3368 device_destroy(nvme_class, MKDEV(nvme_char_major, dev->instance));
3369 nvme_free_queues(dev, 0);
3370 nvme_release_cmb(dev);
3371 nvme_release_prp_pools(dev);
3372 kref_put(&dev->kref, nvme_free_dev);
3373}
3374
3375/* These functions are yet to be implemented */
3376#define nvme_error_detected NULL
3377#define nvme_dump_registers NULL
3378#define nvme_link_reset NULL
3379#define nvme_slot_reset NULL
3380#define nvme_error_resume NULL
3381
3382#ifdef CONFIG_PM_SLEEP
3383static int nvme_suspend(struct device *dev)
3384{
3385 struct pci_dev *pdev = to_pci_dev(dev);
3386 struct nvme_dev *ndev = pci_get_drvdata(pdev);
3387
3388 nvme_dev_shutdown(ndev);
3389 return 0;
3390}
3391
3392static int nvme_resume(struct device *dev)
3393{
3394 struct pci_dev *pdev = to_pci_dev(dev);
3395 struct nvme_dev *ndev = pci_get_drvdata(pdev);
3396
3397 schedule_work(&ndev->probe_work);
3398 return 0;
3399}
3400#endif
3401
3402static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
3403
3404static const struct pci_error_handlers nvme_err_handler = {
3405 .error_detected = nvme_error_detected,
3406 .mmio_enabled = nvme_dump_registers,
3407 .link_reset = nvme_link_reset,
3408 .slot_reset = nvme_slot_reset,
3409 .resume = nvme_error_resume,
3410 .reset_notify = nvme_reset_notify,
3411};
3412
3413/* Move to pci_ids.h later */
3414#define PCI_CLASS_STORAGE_EXPRESS 0x010802
3415
3416static const struct pci_device_id nvme_id_table[] = {
3417 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
3418 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
3419 { 0, }
3420};
3421MODULE_DEVICE_TABLE(pci, nvme_id_table);
3422
3423static struct pci_driver nvme_driver = {
3424 .name = "nvme",
3425 .id_table = nvme_id_table,
3426 .probe = nvme_probe,
3427 .remove = nvme_remove,
3428 .shutdown = nvme_shutdown,
3429 .driver = {
3430 .pm = &nvme_dev_pm_ops,
3431 },
3432 .err_handler = &nvme_err_handler,
3433};
3434
3435static int __init nvme_init(void)
3436{
3437 int result;
3438
3439 init_waitqueue_head(&nvme_kthread_wait);
3440
3441 nvme_workq = create_singlethread_workqueue("nvme");
3442 if (!nvme_workq)
3443 return -ENOMEM;
3444
3445 result = register_blkdev(nvme_major, "nvme");
3446 if (result < 0)
3447 goto kill_workq;
3448 else if (result > 0)
3449 nvme_major = result;
3450
3451 result = __register_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme",
3452 &nvme_dev_fops);
3453 if (result < 0)
3454 goto unregister_blkdev;
3455 else if (result > 0)
3456 nvme_char_major = result;
3457
3458 nvme_class = class_create(THIS_MODULE, "nvme");
3459 if (IS_ERR(nvme_class)) {
3460 result = PTR_ERR(nvme_class);
3461 goto unregister_chrdev;
3462 }
3463
3464 result = pci_register_driver(&nvme_driver);
3465 if (result)
3466 goto destroy_class;
3467 return 0;
3468
3469 destroy_class:
3470 class_destroy(nvme_class);
3471 unregister_chrdev:
3472 __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
3473 unregister_blkdev:
3474 unregister_blkdev(nvme_major, "nvme");
3475 kill_workq:
3476 destroy_workqueue(nvme_workq);
3477 return result;
3478}
3479
3480static void __exit nvme_exit(void)
3481{
3482 pci_unregister_driver(&nvme_driver);
3483 unregister_blkdev(nvme_major, "nvme");
3484 destroy_workqueue(nvme_workq);
3485 class_destroy(nvme_class);
3486 __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
3487 BUG_ON(nvme_thread && !IS_ERR(nvme_thread));
3488 _nvme_check_size();
3489}
3490
3491MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3492MODULE_LICENSE("GPL");
3493MODULE_VERSION("1.0");
3494module_init(nvme_init);
3495module_exit(nvme_exit);
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