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nvme-rdma: default MR page size to 4k
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1/*
2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 */
14
15#include <linux/aer.h>
16#include <linux/bitops.h>
17#include <linux/blkdev.h>
18#include <linux/blk-mq.h>
19#include <linux/blk-mq-pci.h>
20#include <linux/dmi.h>
21#include <linux/init.h>
22#include <linux/interrupt.h>
23#include <linux/io.h>
24#include <linux/mm.h>
25#include <linux/module.h>
26#include <linux/mutex.h>
27#include <linux/pci.h>
28#include <linux/poison.h>
29#include <linux/t10-pi.h>
30#include <linux/timer.h>
31#include <linux/types.h>
32#include <linux/io-64-nonatomic-lo-hi.h>
33#include <asm/unaligned.h>
34#include <linux/sed-opal.h>
35
36#include "nvme.h"
37
38#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
39#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
40
41/*
42 * We handle AEN commands ourselves and don't even let the
43 * block layer know about them.
44 */
45#define NVME_AQ_BLKMQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AERS)
46
47static int use_threaded_interrupts;
48module_param(use_threaded_interrupts, int, 0);
49
50static bool use_cmb_sqes = true;
51module_param(use_cmb_sqes, bool, 0644);
52MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
53
54static unsigned int max_host_mem_size_mb = 128;
55module_param(max_host_mem_size_mb, uint, 0444);
56MODULE_PARM_DESC(max_host_mem_size_mb,
57 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
58
59static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
60static const struct kernel_param_ops io_queue_depth_ops = {
61 .set = io_queue_depth_set,
62 .get = param_get_int,
63};
64
65static int io_queue_depth = 1024;
66module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
67MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
68
69struct nvme_dev;
70struct nvme_queue;
71
72static void nvme_process_cq(struct nvme_queue *nvmeq);
73static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
74
75/*
76 * Represents an NVM Express device. Each nvme_dev is a PCI function.
77 */
78struct nvme_dev {
79 struct nvme_queue **queues;
80 struct blk_mq_tag_set tagset;
81 struct blk_mq_tag_set admin_tagset;
82 u32 __iomem *dbs;
83 struct device *dev;
84 struct dma_pool *prp_page_pool;
85 struct dma_pool *prp_small_pool;
86 unsigned online_queues;
87 unsigned max_qid;
88 int q_depth;
89 u32 db_stride;
90 void __iomem *bar;
91 unsigned long bar_mapped_size;
92 struct work_struct remove_work;
93 struct mutex shutdown_lock;
94 bool subsystem;
95 void __iomem *cmb;
96 dma_addr_t cmb_dma_addr;
97 u64 cmb_size;
98 u32 cmbsz;
99 u32 cmbloc;
100 struct nvme_ctrl ctrl;
101 struct completion ioq_wait;
102
103 /* shadow doorbell buffer support: */
104 u32 *dbbuf_dbs;
105 dma_addr_t dbbuf_dbs_dma_addr;
106 u32 *dbbuf_eis;
107 dma_addr_t dbbuf_eis_dma_addr;
108
109 /* host memory buffer support: */
110 u64 host_mem_size;
111 u32 nr_host_mem_descs;
112 struct nvme_host_mem_buf_desc *host_mem_descs;
113 void **host_mem_desc_bufs;
114};
115
116static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
117{
118 int n = 0, ret;
119
120 ret = kstrtoint(val, 10, &n);
121 if (ret != 0 || n < 2)
122 return -EINVAL;
123
124 return param_set_int(val, kp);
125}
126
127static inline unsigned int sq_idx(unsigned int qid, u32 stride)
128{
129 return qid * 2 * stride;
130}
131
132static inline unsigned int cq_idx(unsigned int qid, u32 stride)
133{
134 return (qid * 2 + 1) * stride;
135}
136
137static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
138{
139 return container_of(ctrl, struct nvme_dev, ctrl);
140}
141
142/*
143 * An NVM Express queue. Each device has at least two (one for admin
144 * commands and one for I/O commands).
145 */
146struct nvme_queue {
147 struct device *q_dmadev;
148 struct nvme_dev *dev;
149 spinlock_t q_lock;
150 struct nvme_command *sq_cmds;
151 struct nvme_command __iomem *sq_cmds_io;
152 volatile struct nvme_completion *cqes;
153 struct blk_mq_tags **tags;
154 dma_addr_t sq_dma_addr;
155 dma_addr_t cq_dma_addr;
156 u32 __iomem *q_db;
157 u16 q_depth;
158 s16 cq_vector;
159 u16 sq_tail;
160 u16 cq_head;
161 u16 qid;
162 u8 cq_phase;
163 u8 cqe_seen;
164 u32 *dbbuf_sq_db;
165 u32 *dbbuf_cq_db;
166 u32 *dbbuf_sq_ei;
167 u32 *dbbuf_cq_ei;
168};
169
170/*
171 * The nvme_iod describes the data in an I/O, including the list of PRP
172 * entries. You can't see it in this data structure because C doesn't let
173 * me express that. Use nvme_init_iod to ensure there's enough space
174 * allocated to store the PRP list.
175 */
176struct nvme_iod {
177 struct nvme_request req;
178 struct nvme_queue *nvmeq;
179 int aborted;
180 int npages; /* In the PRP list. 0 means small pool in use */
181 int nents; /* Used in scatterlist */
182 int length; /* Of data, in bytes */
183 dma_addr_t first_dma;
184 struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
185 struct scatterlist *sg;
186 struct scatterlist inline_sg[0];
187};
188
189/*
190 * Check we didin't inadvertently grow the command struct
191 */
192static inline void _nvme_check_size(void)
193{
194 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
195 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
196 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
197 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
198 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
199 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
200 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
201 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
202 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE);
203 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE);
204 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
205 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
206 BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64);
207}
208
209static inline unsigned int nvme_dbbuf_size(u32 stride)
210{
211 return ((num_possible_cpus() + 1) * 8 * stride);
212}
213
214static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
215{
216 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
217
218 if (dev->dbbuf_dbs)
219 return 0;
220
221 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
222 &dev->dbbuf_dbs_dma_addr,
223 GFP_KERNEL);
224 if (!dev->dbbuf_dbs)
225 return -ENOMEM;
226 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
227 &dev->dbbuf_eis_dma_addr,
228 GFP_KERNEL);
229 if (!dev->dbbuf_eis) {
230 dma_free_coherent(dev->dev, mem_size,
231 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
232 dev->dbbuf_dbs = NULL;
233 return -ENOMEM;
234 }
235
236 return 0;
237}
238
239static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
240{
241 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
242
243 if (dev->dbbuf_dbs) {
244 dma_free_coherent(dev->dev, mem_size,
245 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
246 dev->dbbuf_dbs = NULL;
247 }
248 if (dev->dbbuf_eis) {
249 dma_free_coherent(dev->dev, mem_size,
250 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
251 dev->dbbuf_eis = NULL;
252 }
253}
254
255static void nvme_dbbuf_init(struct nvme_dev *dev,
256 struct nvme_queue *nvmeq, int qid)
257{
258 if (!dev->dbbuf_dbs || !qid)
259 return;
260
261 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
262 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
263 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
264 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
265}
266
267static void nvme_dbbuf_set(struct nvme_dev *dev)
268{
269 struct nvme_command c;
270
271 if (!dev->dbbuf_dbs)
272 return;
273
274 memset(&c, 0, sizeof(c));
275 c.dbbuf.opcode = nvme_admin_dbbuf;
276 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
277 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
278
279 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
280 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
281 /* Free memory and continue on */
282 nvme_dbbuf_dma_free(dev);
283 }
284}
285
286static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
287{
288 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
289}
290
291/* Update dbbuf and return true if an MMIO is required */
292static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
293 volatile u32 *dbbuf_ei)
294{
295 if (dbbuf_db) {
296 u16 old_value;
297
298 /*
299 * Ensure that the queue is written before updating
300 * the doorbell in memory
301 */
302 wmb();
303
304 old_value = *dbbuf_db;
305 *dbbuf_db = value;
306
307 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
308 return false;
309 }
310
311 return true;
312}
313
314/*
315 * Max size of iod being embedded in the request payload
316 */
317#define NVME_INT_PAGES 2
318#define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
319
320/*
321 * Will slightly overestimate the number of pages needed. This is OK
322 * as it only leads to a small amount of wasted memory for the lifetime of
323 * the I/O.
324 */
325static int nvme_npages(unsigned size, struct nvme_dev *dev)
326{
327 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
328 dev->ctrl.page_size);
329 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
330}
331
332static unsigned int nvme_iod_alloc_size(struct nvme_dev *dev,
333 unsigned int size, unsigned int nseg)
334{
335 return sizeof(__le64 *) * nvme_npages(size, dev) +
336 sizeof(struct scatterlist) * nseg;
337}
338
339static unsigned int nvme_cmd_size(struct nvme_dev *dev)
340{
341 return sizeof(struct nvme_iod) +
342 nvme_iod_alloc_size(dev, NVME_INT_BYTES(dev), NVME_INT_PAGES);
343}
344
345static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
346 unsigned int hctx_idx)
347{
348 struct nvme_dev *dev = data;
349 struct nvme_queue *nvmeq = dev->queues[0];
350
351 WARN_ON(hctx_idx != 0);
352 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
353 WARN_ON(nvmeq->tags);
354
355 hctx->driver_data = nvmeq;
356 nvmeq->tags = &dev->admin_tagset.tags[0];
357 return 0;
358}
359
360static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
361{
362 struct nvme_queue *nvmeq = hctx->driver_data;
363
364 nvmeq->tags = NULL;
365}
366
367static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
368 unsigned int hctx_idx)
369{
370 struct nvme_dev *dev = data;
371 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
372
373 if (!nvmeq->tags)
374 nvmeq->tags = &dev->tagset.tags[hctx_idx];
375
376 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
377 hctx->driver_data = nvmeq;
378 return 0;
379}
380
381static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
382 unsigned int hctx_idx, unsigned int numa_node)
383{
384 struct nvme_dev *dev = set->driver_data;
385 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
386 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
387 struct nvme_queue *nvmeq = dev->queues[queue_idx];
388
389 BUG_ON(!nvmeq);
390 iod->nvmeq = nvmeq;
391 return 0;
392}
393
394static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
395{
396 struct nvme_dev *dev = set->driver_data;
397
398 return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev));
399}
400
401/**
402 * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
403 * @nvmeq: The queue to use
404 * @cmd: The command to send
405 *
406 * Safe to use from interrupt context
407 */
408static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
409 struct nvme_command *cmd)
410{
411 u16 tail = nvmeq->sq_tail;
412
413 if (nvmeq->sq_cmds_io)
414 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
415 else
416 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
417
418 if (++tail == nvmeq->q_depth)
419 tail = 0;
420 if (nvme_dbbuf_update_and_check_event(tail, nvmeq->dbbuf_sq_db,
421 nvmeq->dbbuf_sq_ei))
422 writel(tail, nvmeq->q_db);
423 nvmeq->sq_tail = tail;
424}
425
426static __le64 **iod_list(struct request *req)
427{
428 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
429 return (__le64 **)(iod->sg + blk_rq_nr_phys_segments(req));
430}
431
432static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev)
433{
434 struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
435 int nseg = blk_rq_nr_phys_segments(rq);
436 unsigned int size = blk_rq_payload_bytes(rq);
437
438 if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
439 iod->sg = kmalloc(nvme_iod_alloc_size(dev, size, nseg), GFP_ATOMIC);
440 if (!iod->sg)
441 return BLK_STS_RESOURCE;
442 } else {
443 iod->sg = iod->inline_sg;
444 }
445
446 iod->aborted = 0;
447 iod->npages = -1;
448 iod->nents = 0;
449 iod->length = size;
450
451 return BLK_STS_OK;
452}
453
454static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
455{
456 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
457 const int last_prp = dev->ctrl.page_size / 8 - 1;
458 int i;
459 __le64 **list = iod_list(req);
460 dma_addr_t prp_dma = iod->first_dma;
461
462 if (iod->npages == 0)
463 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
464 for (i = 0; i < iod->npages; i++) {
465 __le64 *prp_list = list[i];
466 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
467 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
468 prp_dma = next_prp_dma;
469 }
470
471 if (iod->sg != iod->inline_sg)
472 kfree(iod->sg);
473}
474
475#ifdef CONFIG_BLK_DEV_INTEGRITY
476static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
477{
478 if (be32_to_cpu(pi->ref_tag) == v)
479 pi->ref_tag = cpu_to_be32(p);
480}
481
482static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
483{
484 if (be32_to_cpu(pi->ref_tag) == p)
485 pi->ref_tag = cpu_to_be32(v);
486}
487
488/**
489 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
490 *
491 * The virtual start sector is the one that was originally submitted by the
492 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
493 * start sector may be different. Remap protection information to match the
494 * physical LBA on writes, and back to the original seed on reads.
495 *
496 * Type 0 and 3 do not have a ref tag, so no remapping required.
497 */
498static void nvme_dif_remap(struct request *req,
499 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
500{
501 struct nvme_ns *ns = req->rq_disk->private_data;
502 struct bio_integrity_payload *bip;
503 struct t10_pi_tuple *pi;
504 void *p, *pmap;
505 u32 i, nlb, ts, phys, virt;
506
507 if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
508 return;
509
510 bip = bio_integrity(req->bio);
511 if (!bip)
512 return;
513
514 pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
515
516 p = pmap;
517 virt = bip_get_seed(bip);
518 phys = nvme_block_nr(ns, blk_rq_pos(req));
519 nlb = (blk_rq_bytes(req) >> ns->lba_shift);
520 ts = ns->disk->queue->integrity.tuple_size;
521
522 for (i = 0; i < nlb; i++, virt++, phys++) {
523 pi = (struct t10_pi_tuple *)p;
524 dif_swap(phys, virt, pi);
525 p += ts;
526 }
527 kunmap_atomic(pmap);
528}
529#else /* CONFIG_BLK_DEV_INTEGRITY */
530static void nvme_dif_remap(struct request *req,
531 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
532{
533}
534static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
535{
536}
537static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
538{
539}
540#endif
541
542static blk_status_t nvme_setup_prps(struct nvme_dev *dev, struct request *req)
543{
544 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
545 struct dma_pool *pool;
546 int length = blk_rq_payload_bytes(req);
547 struct scatterlist *sg = iod->sg;
548 int dma_len = sg_dma_len(sg);
549 u64 dma_addr = sg_dma_address(sg);
550 u32 page_size = dev->ctrl.page_size;
551 int offset = dma_addr & (page_size - 1);
552 __le64 *prp_list;
553 __le64 **list = iod_list(req);
554 dma_addr_t prp_dma;
555 int nprps, i;
556
557 length -= (page_size - offset);
558 if (length <= 0)
559 return BLK_STS_OK;
560
561 dma_len -= (page_size - offset);
562 if (dma_len) {
563 dma_addr += (page_size - offset);
564 } else {
565 sg = sg_next(sg);
566 dma_addr = sg_dma_address(sg);
567 dma_len = sg_dma_len(sg);
568 }
569
570 if (length <= page_size) {
571 iod->first_dma = dma_addr;
572 return BLK_STS_OK;
573 }
574
575 nprps = DIV_ROUND_UP(length, page_size);
576 if (nprps <= (256 / 8)) {
577 pool = dev->prp_small_pool;
578 iod->npages = 0;
579 } else {
580 pool = dev->prp_page_pool;
581 iod->npages = 1;
582 }
583
584 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
585 if (!prp_list) {
586 iod->first_dma = dma_addr;
587 iod->npages = -1;
588 return BLK_STS_RESOURCE;
589 }
590 list[0] = prp_list;
591 iod->first_dma = prp_dma;
592 i = 0;
593 for (;;) {
594 if (i == page_size >> 3) {
595 __le64 *old_prp_list = prp_list;
596 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
597 if (!prp_list)
598 return BLK_STS_RESOURCE;
599 list[iod->npages++] = prp_list;
600 prp_list[0] = old_prp_list[i - 1];
601 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
602 i = 1;
603 }
604 prp_list[i++] = cpu_to_le64(dma_addr);
605 dma_len -= page_size;
606 dma_addr += page_size;
607 length -= page_size;
608 if (length <= 0)
609 break;
610 if (dma_len > 0)
611 continue;
612 if (unlikely(dma_len < 0))
613 goto bad_sgl;
614 sg = sg_next(sg);
615 dma_addr = sg_dma_address(sg);
616 dma_len = sg_dma_len(sg);
617 }
618
619 return BLK_STS_OK;
620
621 bad_sgl:
622 if (WARN_ONCE(1, "Invalid SGL for payload:%d nents:%d\n",
623 blk_rq_payload_bytes(req), iod->nents)) {
624 for_each_sg(iod->sg, sg, iod->nents, i) {
625 dma_addr_t phys = sg_phys(sg);
626 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
627 "dma_address:%pad dma_length:%d\n", i, &phys,
628 sg->offset, sg->length,
629 &sg_dma_address(sg),
630 sg_dma_len(sg));
631 }
632 }
633 return BLK_STS_IOERR;
634
635}
636
637static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
638 struct nvme_command *cmnd)
639{
640 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
641 struct request_queue *q = req->q;
642 enum dma_data_direction dma_dir = rq_data_dir(req) ?
643 DMA_TO_DEVICE : DMA_FROM_DEVICE;
644 blk_status_t ret = BLK_STS_IOERR;
645
646 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
647 iod->nents = blk_rq_map_sg(q, req, iod->sg);
648 if (!iod->nents)
649 goto out;
650
651 ret = BLK_STS_RESOURCE;
652 if (!dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir,
653 DMA_ATTR_NO_WARN))
654 goto out;
655
656 ret = nvme_setup_prps(dev, req);
657 if (ret != BLK_STS_OK)
658 goto out_unmap;
659
660 ret = BLK_STS_IOERR;
661 if (blk_integrity_rq(req)) {
662 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
663 goto out_unmap;
664
665 sg_init_table(&iod->meta_sg, 1);
666 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
667 goto out_unmap;
668
669 if (rq_data_dir(req))
670 nvme_dif_remap(req, nvme_dif_prep);
671
672 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
673 goto out_unmap;
674 }
675
676 cmnd->rw.dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
677 cmnd->rw.dptr.prp2 = cpu_to_le64(iod->first_dma);
678 if (blk_integrity_rq(req))
679 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
680 return BLK_STS_OK;
681
682out_unmap:
683 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
684out:
685 return ret;
686}
687
688static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
689{
690 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
691 enum dma_data_direction dma_dir = rq_data_dir(req) ?
692 DMA_TO_DEVICE : DMA_FROM_DEVICE;
693
694 if (iod->nents) {
695 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
696 if (blk_integrity_rq(req)) {
697 if (!rq_data_dir(req))
698 nvme_dif_remap(req, nvme_dif_complete);
699 dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
700 }
701 }
702
703 nvme_cleanup_cmd(req);
704 nvme_free_iod(dev, req);
705}
706
707/*
708 * NOTE: ns is NULL when called on the admin queue.
709 */
710static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
711 const struct blk_mq_queue_data *bd)
712{
713 struct nvme_ns *ns = hctx->queue->queuedata;
714 struct nvme_queue *nvmeq = hctx->driver_data;
715 struct nvme_dev *dev = nvmeq->dev;
716 struct request *req = bd->rq;
717 struct nvme_command cmnd;
718 blk_status_t ret;
719
720 ret = nvme_setup_cmd(ns, req, &cmnd);
721 if (ret)
722 return ret;
723
724 ret = nvme_init_iod(req, dev);
725 if (ret)
726 goto out_free_cmd;
727
728 if (blk_rq_nr_phys_segments(req)) {
729 ret = nvme_map_data(dev, req, &cmnd);
730 if (ret)
731 goto out_cleanup_iod;
732 }
733
734 blk_mq_start_request(req);
735
736 spin_lock_irq(&nvmeq->q_lock);
737 if (unlikely(nvmeq->cq_vector < 0)) {
738 ret = BLK_STS_IOERR;
739 spin_unlock_irq(&nvmeq->q_lock);
740 goto out_cleanup_iod;
741 }
742 __nvme_submit_cmd(nvmeq, &cmnd);
743 nvme_process_cq(nvmeq);
744 spin_unlock_irq(&nvmeq->q_lock);
745 return BLK_STS_OK;
746out_cleanup_iod:
747 nvme_free_iod(dev, req);
748out_free_cmd:
749 nvme_cleanup_cmd(req);
750 return ret;
751}
752
753static void nvme_pci_complete_rq(struct request *req)
754{
755 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
756
757 nvme_unmap_data(iod->nvmeq->dev, req);
758 nvme_complete_rq(req);
759}
760
761/* We read the CQE phase first to check if the rest of the entry is valid */
762static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head,
763 u16 phase)
764{
765 return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase;
766}
767
768static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
769{
770 u16 head = nvmeq->cq_head;
771
772 if (likely(nvmeq->cq_vector >= 0)) {
773 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
774 nvmeq->dbbuf_cq_ei))
775 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
776 }
777}
778
779static inline void nvme_handle_cqe(struct nvme_queue *nvmeq,
780 struct nvme_completion *cqe)
781{
782 struct request *req;
783
784 if (unlikely(cqe->command_id >= nvmeq->q_depth)) {
785 dev_warn(nvmeq->dev->ctrl.device,
786 "invalid id %d completed on queue %d\n",
787 cqe->command_id, le16_to_cpu(cqe->sq_id));
788 return;
789 }
790
791 /*
792 * AEN requests are special as they don't time out and can
793 * survive any kind of queue freeze and often don't respond to
794 * aborts. We don't even bother to allocate a struct request
795 * for them but rather special case them here.
796 */
797 if (unlikely(nvmeq->qid == 0 &&
798 cqe->command_id >= NVME_AQ_BLKMQ_DEPTH)) {
799 nvme_complete_async_event(&nvmeq->dev->ctrl,
800 cqe->status, &cqe->result);
801 return;
802 }
803
804 nvmeq->cqe_seen = 1;
805 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id);
806 nvme_end_request(req, cqe->status, cqe->result);
807}
808
809static inline bool nvme_read_cqe(struct nvme_queue *nvmeq,
810 struct nvme_completion *cqe)
811{
812 if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) {
813 *cqe = nvmeq->cqes[nvmeq->cq_head];
814
815 if (++nvmeq->cq_head == nvmeq->q_depth) {
816 nvmeq->cq_head = 0;
817 nvmeq->cq_phase = !nvmeq->cq_phase;
818 }
819 return true;
820 }
821 return false;
822}
823
824static void nvme_process_cq(struct nvme_queue *nvmeq)
825{
826 struct nvme_completion cqe;
827 int consumed = 0;
828
829 while (nvme_read_cqe(nvmeq, &cqe)) {
830 nvme_handle_cqe(nvmeq, &cqe);
831 consumed++;
832 }
833
834 if (consumed)
835 nvme_ring_cq_doorbell(nvmeq);
836}
837
838static irqreturn_t nvme_irq(int irq, void *data)
839{
840 irqreturn_t result;
841 struct nvme_queue *nvmeq = data;
842 spin_lock(&nvmeq->q_lock);
843 nvme_process_cq(nvmeq);
844 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
845 nvmeq->cqe_seen = 0;
846 spin_unlock(&nvmeq->q_lock);
847 return result;
848}
849
850static irqreturn_t nvme_irq_check(int irq, void *data)
851{
852 struct nvme_queue *nvmeq = data;
853 if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase))
854 return IRQ_WAKE_THREAD;
855 return IRQ_NONE;
856}
857
858static int __nvme_poll(struct nvme_queue *nvmeq, unsigned int tag)
859{
860 struct nvme_completion cqe;
861 int found = 0, consumed = 0;
862
863 if (!nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase))
864 return 0;
865
866 spin_lock_irq(&nvmeq->q_lock);
867 while (nvme_read_cqe(nvmeq, &cqe)) {
868 nvme_handle_cqe(nvmeq, &cqe);
869 consumed++;
870
871 if (tag == cqe.command_id) {
872 found = 1;
873 break;
874 }
875 }
876
877 if (consumed)
878 nvme_ring_cq_doorbell(nvmeq);
879 spin_unlock_irq(&nvmeq->q_lock);
880
881 return found;
882}
883
884static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
885{
886 struct nvme_queue *nvmeq = hctx->driver_data;
887
888 return __nvme_poll(nvmeq, tag);
889}
890
891static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl, int aer_idx)
892{
893 struct nvme_dev *dev = to_nvme_dev(ctrl);
894 struct nvme_queue *nvmeq = dev->queues[0];
895 struct nvme_command c;
896
897 memset(&c, 0, sizeof(c));
898 c.common.opcode = nvme_admin_async_event;
899 c.common.command_id = NVME_AQ_BLKMQ_DEPTH + aer_idx;
900
901 spin_lock_irq(&nvmeq->q_lock);
902 __nvme_submit_cmd(nvmeq, &c);
903 spin_unlock_irq(&nvmeq->q_lock);
904}
905
906static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
907{
908 struct nvme_command c;
909
910 memset(&c, 0, sizeof(c));
911 c.delete_queue.opcode = opcode;
912 c.delete_queue.qid = cpu_to_le16(id);
913
914 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
915}
916
917static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
918 struct nvme_queue *nvmeq)
919{
920 struct nvme_command c;
921 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
922
923 /*
924 * Note: we (ab)use the fact the the prp fields survive if no data
925 * is attached to the request.
926 */
927 memset(&c, 0, sizeof(c));
928 c.create_cq.opcode = nvme_admin_create_cq;
929 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
930 c.create_cq.cqid = cpu_to_le16(qid);
931 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
932 c.create_cq.cq_flags = cpu_to_le16(flags);
933 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
934
935 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
936}
937
938static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
939 struct nvme_queue *nvmeq)
940{
941 struct nvme_command c;
942 int flags = NVME_QUEUE_PHYS_CONTIG;
943
944 /*
945 * Note: we (ab)use the fact the the prp fields survive if no data
946 * is attached to the request.
947 */
948 memset(&c, 0, sizeof(c));
949 c.create_sq.opcode = nvme_admin_create_sq;
950 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
951 c.create_sq.sqid = cpu_to_le16(qid);
952 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
953 c.create_sq.sq_flags = cpu_to_le16(flags);
954 c.create_sq.cqid = cpu_to_le16(qid);
955
956 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
957}
958
959static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
960{
961 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
962}
963
964static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
965{
966 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
967}
968
969static void abort_endio(struct request *req, blk_status_t error)
970{
971 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
972 struct nvme_queue *nvmeq = iod->nvmeq;
973
974 dev_warn(nvmeq->dev->ctrl.device,
975 "Abort status: 0x%x", nvme_req(req)->status);
976 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
977 blk_mq_free_request(req);
978}
979
980static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
981{
982
983 /* If true, indicates loss of adapter communication, possibly by a
984 * NVMe Subsystem reset.
985 */
986 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
987
988 /* If there is a reset ongoing, we shouldn't reset again. */
989 if (dev->ctrl.state == NVME_CTRL_RESETTING)
990 return false;
991
992 /* We shouldn't reset unless the controller is on fatal error state
993 * _or_ if we lost the communication with it.
994 */
995 if (!(csts & NVME_CSTS_CFS) && !nssro)
996 return false;
997
998 /* If PCI error recovery process is happening, we cannot reset or
999 * the recovery mechanism will surely fail.
1000 */
1001 if (pci_channel_offline(to_pci_dev(dev->dev)))
1002 return false;
1003
1004 return true;
1005}
1006
1007static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1008{
1009 /* Read a config register to help see what died. */
1010 u16 pci_status;
1011 int result;
1012
1013 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1014 &pci_status);
1015 if (result == PCIBIOS_SUCCESSFUL)
1016 dev_warn(dev->ctrl.device,
1017 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1018 csts, pci_status);
1019 else
1020 dev_warn(dev->ctrl.device,
1021 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1022 csts, result);
1023}
1024
1025static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1026{
1027 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1028 struct nvme_queue *nvmeq = iod->nvmeq;
1029 struct nvme_dev *dev = nvmeq->dev;
1030 struct request *abort_req;
1031 struct nvme_command cmd;
1032 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1033
1034 /*
1035 * Reset immediately if the controller is failed
1036 */
1037 if (nvme_should_reset(dev, csts)) {
1038 nvme_warn_reset(dev, csts);
1039 nvme_dev_disable(dev, false);
1040 nvme_reset_ctrl(&dev->ctrl);
1041 return BLK_EH_HANDLED;
1042 }
1043
1044 /*
1045 * Did we miss an interrupt?
1046 */
1047 if (__nvme_poll(nvmeq, req->tag)) {
1048 dev_warn(dev->ctrl.device,
1049 "I/O %d QID %d timeout, completion polled\n",
1050 req->tag, nvmeq->qid);
1051 return BLK_EH_HANDLED;
1052 }
1053
1054 /*
1055 * Shutdown immediately if controller times out while starting. The
1056 * reset work will see the pci device disabled when it gets the forced
1057 * cancellation error. All outstanding requests are completed on
1058 * shutdown, so we return BLK_EH_HANDLED.
1059 */
1060 if (dev->ctrl.state == NVME_CTRL_RESETTING) {
1061 dev_warn(dev->ctrl.device,
1062 "I/O %d QID %d timeout, disable controller\n",
1063 req->tag, nvmeq->qid);
1064 nvme_dev_disable(dev, false);
1065 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1066 return BLK_EH_HANDLED;
1067 }
1068
1069 /*
1070 * Shutdown the controller immediately and schedule a reset if the
1071 * command was already aborted once before and still hasn't been
1072 * returned to the driver, or if this is the admin queue.
1073 */
1074 if (!nvmeq->qid || iod->aborted) {
1075 dev_warn(dev->ctrl.device,
1076 "I/O %d QID %d timeout, reset controller\n",
1077 req->tag, nvmeq->qid);
1078 nvme_dev_disable(dev, false);
1079 nvme_reset_ctrl(&dev->ctrl);
1080
1081 /*
1082 * Mark the request as handled, since the inline shutdown
1083 * forces all outstanding requests to complete.
1084 */
1085 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1086 return BLK_EH_HANDLED;
1087 }
1088
1089 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1090 atomic_inc(&dev->ctrl.abort_limit);
1091 return BLK_EH_RESET_TIMER;
1092 }
1093 iod->aborted = 1;
1094
1095 memset(&cmd, 0, sizeof(cmd));
1096 cmd.abort.opcode = nvme_admin_abort_cmd;
1097 cmd.abort.cid = req->tag;
1098 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1099
1100 dev_warn(nvmeq->dev->ctrl.device,
1101 "I/O %d QID %d timeout, aborting\n",
1102 req->tag, nvmeq->qid);
1103
1104 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
1105 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
1106 if (IS_ERR(abort_req)) {
1107 atomic_inc(&dev->ctrl.abort_limit);
1108 return BLK_EH_RESET_TIMER;
1109 }
1110
1111 abort_req->timeout = ADMIN_TIMEOUT;
1112 abort_req->end_io_data = NULL;
1113 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
1114
1115 /*
1116 * The aborted req will be completed on receiving the abort req.
1117 * We enable the timer again. If hit twice, it'll cause a device reset,
1118 * as the device then is in a faulty state.
1119 */
1120 return BLK_EH_RESET_TIMER;
1121}
1122
1123static void nvme_free_queue(struct nvme_queue *nvmeq)
1124{
1125 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1126 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1127 if (nvmeq->sq_cmds)
1128 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1129 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1130 kfree(nvmeq);
1131}
1132
1133static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1134{
1135 int i;
1136
1137 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
1138 struct nvme_queue *nvmeq = dev->queues[i];
1139 dev->ctrl.queue_count--;
1140 dev->queues[i] = NULL;
1141 nvme_free_queue(nvmeq);
1142 }
1143}
1144
1145/**
1146 * nvme_suspend_queue - put queue into suspended state
1147 * @nvmeq - queue to suspend
1148 */
1149static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1150{
1151 int vector;
1152
1153 spin_lock_irq(&nvmeq->q_lock);
1154 if (nvmeq->cq_vector == -1) {
1155 spin_unlock_irq(&nvmeq->q_lock);
1156 return 1;
1157 }
1158 vector = nvmeq->cq_vector;
1159 nvmeq->dev->online_queues--;
1160 nvmeq->cq_vector = -1;
1161 spin_unlock_irq(&nvmeq->q_lock);
1162
1163 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1164 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
1165
1166 pci_free_irq(to_pci_dev(nvmeq->dev->dev), vector, nvmeq);
1167
1168 return 0;
1169}
1170
1171static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1172{
1173 struct nvme_queue *nvmeq = dev->queues[0];
1174
1175 if (!nvmeq)
1176 return;
1177 if (nvme_suspend_queue(nvmeq))
1178 return;
1179
1180 if (shutdown)
1181 nvme_shutdown_ctrl(&dev->ctrl);
1182 else
1183 nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
1184
1185 spin_lock_irq(&nvmeq->q_lock);
1186 nvme_process_cq(nvmeq);
1187 spin_unlock_irq(&nvmeq->q_lock);
1188}
1189
1190static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1191 int entry_size)
1192{
1193 int q_depth = dev->q_depth;
1194 unsigned q_size_aligned = roundup(q_depth * entry_size,
1195 dev->ctrl.page_size);
1196
1197 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1198 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1199 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1200 q_depth = div_u64(mem_per_q, entry_size);
1201
1202 /*
1203 * Ensure the reduced q_depth is above some threshold where it
1204 * would be better to map queues in system memory with the
1205 * original depth
1206 */
1207 if (q_depth < 64)
1208 return -ENOMEM;
1209 }
1210
1211 return q_depth;
1212}
1213
1214static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1215 int qid, int depth)
1216{
1217 if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
1218 unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth),
1219 dev->ctrl.page_size);
1220 nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset;
1221 nvmeq->sq_cmds_io = dev->cmb + offset;
1222 } else {
1223 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1224 &nvmeq->sq_dma_addr, GFP_KERNEL);
1225 if (!nvmeq->sq_cmds)
1226 return -ENOMEM;
1227 }
1228
1229 return 0;
1230}
1231
1232static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1233 int depth, int node)
1234{
1235 struct nvme_queue *nvmeq = kzalloc_node(sizeof(*nvmeq), GFP_KERNEL,
1236 node);
1237 if (!nvmeq)
1238 return NULL;
1239
1240 nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
1241 &nvmeq->cq_dma_addr, GFP_KERNEL);
1242 if (!nvmeq->cqes)
1243 goto free_nvmeq;
1244
1245 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1246 goto free_cqdma;
1247
1248 nvmeq->q_dmadev = dev->dev;
1249 nvmeq->dev = dev;
1250 spin_lock_init(&nvmeq->q_lock);
1251 nvmeq->cq_head = 0;
1252 nvmeq->cq_phase = 1;
1253 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1254 nvmeq->q_depth = depth;
1255 nvmeq->qid = qid;
1256 nvmeq->cq_vector = -1;
1257 dev->queues[qid] = nvmeq;
1258 dev->ctrl.queue_count++;
1259
1260 return nvmeq;
1261
1262 free_cqdma:
1263 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1264 nvmeq->cq_dma_addr);
1265 free_nvmeq:
1266 kfree(nvmeq);
1267 return NULL;
1268}
1269
1270static int queue_request_irq(struct nvme_queue *nvmeq)
1271{
1272 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1273 int nr = nvmeq->dev->ctrl.instance;
1274
1275 if (use_threaded_interrupts) {
1276 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1277 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1278 } else {
1279 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1280 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1281 }
1282}
1283
1284static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1285{
1286 struct nvme_dev *dev = nvmeq->dev;
1287
1288 spin_lock_irq(&nvmeq->q_lock);
1289 nvmeq->sq_tail = 0;
1290 nvmeq->cq_head = 0;
1291 nvmeq->cq_phase = 1;
1292 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1293 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1294 nvme_dbbuf_init(dev, nvmeq, qid);
1295 dev->online_queues++;
1296 spin_unlock_irq(&nvmeq->q_lock);
1297}
1298
1299static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1300{
1301 struct nvme_dev *dev = nvmeq->dev;
1302 int result;
1303
1304 nvmeq->cq_vector = qid - 1;
1305 result = adapter_alloc_cq(dev, qid, nvmeq);
1306 if (result < 0)
1307 return result;
1308
1309 result = adapter_alloc_sq(dev, qid, nvmeq);
1310 if (result < 0)
1311 goto release_cq;
1312
1313 result = queue_request_irq(nvmeq);
1314 if (result < 0)
1315 goto release_sq;
1316
1317 nvme_init_queue(nvmeq, qid);
1318 return result;
1319
1320 release_sq:
1321 adapter_delete_sq(dev, qid);
1322 release_cq:
1323 adapter_delete_cq(dev, qid);
1324 return result;
1325}
1326
1327static const struct blk_mq_ops nvme_mq_admin_ops = {
1328 .queue_rq = nvme_queue_rq,
1329 .complete = nvme_pci_complete_rq,
1330 .init_hctx = nvme_admin_init_hctx,
1331 .exit_hctx = nvme_admin_exit_hctx,
1332 .init_request = nvme_init_request,
1333 .timeout = nvme_timeout,
1334};
1335
1336static const struct blk_mq_ops nvme_mq_ops = {
1337 .queue_rq = nvme_queue_rq,
1338 .complete = nvme_pci_complete_rq,
1339 .init_hctx = nvme_init_hctx,
1340 .init_request = nvme_init_request,
1341 .map_queues = nvme_pci_map_queues,
1342 .timeout = nvme_timeout,
1343 .poll = nvme_poll,
1344};
1345
1346static void nvme_dev_remove_admin(struct nvme_dev *dev)
1347{
1348 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1349 /*
1350 * If the controller was reset during removal, it's possible
1351 * user requests may be waiting on a stopped queue. Start the
1352 * queue to flush these to completion.
1353 */
1354 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1355 blk_cleanup_queue(dev->ctrl.admin_q);
1356 blk_mq_free_tag_set(&dev->admin_tagset);
1357 }
1358}
1359
1360static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1361{
1362 if (!dev->ctrl.admin_q) {
1363 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1364 dev->admin_tagset.nr_hw_queues = 1;
1365
1366 /*
1367 * Subtract one to leave an empty queue entry for 'Full Queue'
1368 * condition. See NVM-Express 1.2 specification, section 4.1.2.
1369 */
1370 dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH - 1;
1371 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1372 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1373 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
1374 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
1375 dev->admin_tagset.driver_data = dev;
1376
1377 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1378 return -ENOMEM;
1379
1380 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1381 if (IS_ERR(dev->ctrl.admin_q)) {
1382 blk_mq_free_tag_set(&dev->admin_tagset);
1383 return -ENOMEM;
1384 }
1385 if (!blk_get_queue(dev->ctrl.admin_q)) {
1386 nvme_dev_remove_admin(dev);
1387 dev->ctrl.admin_q = NULL;
1388 return -ENODEV;
1389 }
1390 } else
1391 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1392
1393 return 0;
1394}
1395
1396static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1397{
1398 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1399}
1400
1401static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1402{
1403 struct pci_dev *pdev = to_pci_dev(dev->dev);
1404
1405 if (size <= dev->bar_mapped_size)
1406 return 0;
1407 if (size > pci_resource_len(pdev, 0))
1408 return -ENOMEM;
1409 if (dev->bar)
1410 iounmap(dev->bar);
1411 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1412 if (!dev->bar) {
1413 dev->bar_mapped_size = 0;
1414 return -ENOMEM;
1415 }
1416 dev->bar_mapped_size = size;
1417 dev->dbs = dev->bar + NVME_REG_DBS;
1418
1419 return 0;
1420}
1421
1422static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
1423{
1424 int result;
1425 u32 aqa;
1426 struct nvme_queue *nvmeq;
1427
1428 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1429 if (result < 0)
1430 return result;
1431
1432 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1433 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
1434
1435 if (dev->subsystem &&
1436 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1437 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1438
1439 result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
1440 if (result < 0)
1441 return result;
1442
1443 nvmeq = dev->queues[0];
1444 if (!nvmeq) {
1445 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH,
1446 dev_to_node(dev->dev));
1447 if (!nvmeq)
1448 return -ENOMEM;
1449 }
1450
1451 aqa = nvmeq->q_depth - 1;
1452 aqa |= aqa << 16;
1453
1454 writel(aqa, dev->bar + NVME_REG_AQA);
1455 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1456 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1457
1458 result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap);
1459 if (result)
1460 return result;
1461
1462 nvmeq->cq_vector = 0;
1463 result = queue_request_irq(nvmeq);
1464 if (result) {
1465 nvmeq->cq_vector = -1;
1466 return result;
1467 }
1468
1469 return result;
1470}
1471
1472static int nvme_create_io_queues(struct nvme_dev *dev)
1473{
1474 unsigned i, max;
1475 int ret = 0;
1476
1477 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
1478 /* vector == qid - 1, match nvme_create_queue */
1479 if (!nvme_alloc_queue(dev, i, dev->q_depth,
1480 pci_irq_get_node(to_pci_dev(dev->dev), i - 1))) {
1481 ret = -ENOMEM;
1482 break;
1483 }
1484 }
1485
1486 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
1487 for (i = dev->online_queues; i <= max; i++) {
1488 ret = nvme_create_queue(dev->queues[i], i);
1489 if (ret)
1490 break;
1491 }
1492
1493 /*
1494 * Ignore failing Create SQ/CQ commands, we can continue with less
1495 * than the desired aount of queues, and even a controller without
1496 * I/O queues an still be used to issue admin commands. This might
1497 * be useful to upgrade a buggy firmware for example.
1498 */
1499 return ret >= 0 ? 0 : ret;
1500}
1501
1502static ssize_t nvme_cmb_show(struct device *dev,
1503 struct device_attribute *attr,
1504 char *buf)
1505{
1506 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1507
1508 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
1509 ndev->cmbloc, ndev->cmbsz);
1510}
1511static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1512
1513static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
1514{
1515 u64 szu, size, offset;
1516 resource_size_t bar_size;
1517 struct pci_dev *pdev = to_pci_dev(dev->dev);
1518 void __iomem *cmb;
1519 dma_addr_t dma_addr;
1520
1521 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1522 if (!(NVME_CMB_SZ(dev->cmbsz)))
1523 return NULL;
1524 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1525
1526 if (!use_cmb_sqes)
1527 return NULL;
1528
1529 szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
1530 size = szu * NVME_CMB_SZ(dev->cmbsz);
1531 offset = szu * NVME_CMB_OFST(dev->cmbloc);
1532 bar_size = pci_resource_len(pdev, NVME_CMB_BIR(dev->cmbloc));
1533
1534 if (offset > bar_size)
1535 return NULL;
1536
1537 /*
1538 * Controllers may support a CMB size larger than their BAR,
1539 * for example, due to being behind a bridge. Reduce the CMB to
1540 * the reported size of the BAR
1541 */
1542 if (size > bar_size - offset)
1543 size = bar_size - offset;
1544
1545 dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(dev->cmbloc)) + offset;
1546 cmb = ioremap_wc(dma_addr, size);
1547 if (!cmb)
1548 return NULL;
1549
1550 dev->cmb_dma_addr = dma_addr;
1551 dev->cmb_size = size;
1552 return cmb;
1553}
1554
1555static inline void nvme_release_cmb(struct nvme_dev *dev)
1556{
1557 if (dev->cmb) {
1558 iounmap(dev->cmb);
1559 dev->cmb = NULL;
1560 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1561 &dev_attr_cmb.attr, NULL);
1562 dev->cmbsz = 0;
1563 }
1564}
1565
1566static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1567{
1568 size_t len = dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs);
1569 struct nvme_command c;
1570 u64 dma_addr;
1571 int ret;
1572
1573 dma_addr = dma_map_single(dev->dev, dev->host_mem_descs, len,
1574 DMA_TO_DEVICE);
1575 if (dma_mapping_error(dev->dev, dma_addr))
1576 return -ENOMEM;
1577
1578 memset(&c, 0, sizeof(c));
1579 c.features.opcode = nvme_admin_set_features;
1580 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1581 c.features.dword11 = cpu_to_le32(bits);
1582 c.features.dword12 = cpu_to_le32(dev->host_mem_size >>
1583 ilog2(dev->ctrl.page_size));
1584 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1585 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1586 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1587
1588 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1589 if (ret) {
1590 dev_warn(dev->ctrl.device,
1591 "failed to set host mem (err %d, flags %#x).\n",
1592 ret, bits);
1593 }
1594 dma_unmap_single(dev->dev, dma_addr, len, DMA_TO_DEVICE);
1595 return ret;
1596}
1597
1598static void nvme_free_host_mem(struct nvme_dev *dev)
1599{
1600 int i;
1601
1602 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1603 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1604 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1605
1606 dma_free_coherent(dev->dev, size, dev->host_mem_desc_bufs[i],
1607 le64_to_cpu(desc->addr));
1608 }
1609
1610 kfree(dev->host_mem_desc_bufs);
1611 dev->host_mem_desc_bufs = NULL;
1612 kfree(dev->host_mem_descs);
1613 dev->host_mem_descs = NULL;
1614}
1615
1616static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1617{
1618 struct nvme_host_mem_buf_desc *descs;
1619 u32 chunk_size, max_entries, len;
1620 int i = 0;
1621 void **bufs;
1622 u64 size = 0, tmp;
1623
1624 /* start big and work our way down */
1625 chunk_size = min(preferred, (u64)PAGE_SIZE << MAX_ORDER);
1626retry:
1627 tmp = (preferred + chunk_size - 1);
1628 do_div(tmp, chunk_size);
1629 max_entries = tmp;
1630 descs = kcalloc(max_entries, sizeof(*descs), GFP_KERNEL);
1631 if (!descs)
1632 goto out;
1633
1634 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1635 if (!bufs)
1636 goto out_free_descs;
1637
1638 for (size = 0; size < preferred; size += len) {
1639 dma_addr_t dma_addr;
1640
1641 len = min_t(u64, chunk_size, preferred - size);
1642 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1643 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1644 if (!bufs[i])
1645 break;
1646
1647 descs[i].addr = cpu_to_le64(dma_addr);
1648 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1649 i++;
1650 }
1651
1652 if (!size || (min && size < min)) {
1653 dev_warn(dev->ctrl.device,
1654 "failed to allocate host memory buffer.\n");
1655 goto out_free_bufs;
1656 }
1657
1658 dev_info(dev->ctrl.device,
1659 "allocated %lld MiB host memory buffer.\n",
1660 size >> ilog2(SZ_1M));
1661 dev->nr_host_mem_descs = i;
1662 dev->host_mem_size = size;
1663 dev->host_mem_descs = descs;
1664 dev->host_mem_desc_bufs = bufs;
1665 return 0;
1666
1667out_free_bufs:
1668 while (--i >= 0) {
1669 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1670
1671 dma_free_coherent(dev->dev, size, bufs[i],
1672 le64_to_cpu(descs[i].addr));
1673 }
1674
1675 kfree(bufs);
1676out_free_descs:
1677 kfree(descs);
1678out:
1679 /* try a smaller chunk size if we failed early */
1680 if (chunk_size >= PAGE_SIZE * 2 && (i == 0 || size < min)) {
1681 chunk_size /= 2;
1682 goto retry;
1683 }
1684 dev->host_mem_descs = NULL;
1685 return -ENOMEM;
1686}
1687
1688static void nvme_setup_host_mem(struct nvme_dev *dev)
1689{
1690 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
1691 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
1692 u64 min = (u64)dev->ctrl.hmmin * 4096;
1693 u32 enable_bits = NVME_HOST_MEM_ENABLE;
1694
1695 preferred = min(preferred, max);
1696 if (min > max) {
1697 dev_warn(dev->ctrl.device,
1698 "min host memory (%lld MiB) above limit (%d MiB).\n",
1699 min >> ilog2(SZ_1M), max_host_mem_size_mb);
1700 nvme_free_host_mem(dev);
1701 return;
1702 }
1703
1704 /*
1705 * If we already have a buffer allocated check if we can reuse it.
1706 */
1707 if (dev->host_mem_descs) {
1708 if (dev->host_mem_size >= min)
1709 enable_bits |= NVME_HOST_MEM_RETURN;
1710 else
1711 nvme_free_host_mem(dev);
1712 }
1713
1714 if (!dev->host_mem_descs) {
1715 if (nvme_alloc_host_mem(dev, min, preferred))
1716 return;
1717 }
1718
1719 if (nvme_set_host_mem(dev, enable_bits))
1720 nvme_free_host_mem(dev);
1721}
1722
1723static int nvme_setup_io_queues(struct nvme_dev *dev)
1724{
1725 struct nvme_queue *adminq = dev->queues[0];
1726 struct pci_dev *pdev = to_pci_dev(dev->dev);
1727 int result, nr_io_queues;
1728 unsigned long size;
1729
1730 nr_io_queues = num_present_cpus();
1731 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
1732 if (result < 0)
1733 return result;
1734
1735 if (nr_io_queues == 0)
1736 return 0;
1737
1738 if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) {
1739 result = nvme_cmb_qdepth(dev, nr_io_queues,
1740 sizeof(struct nvme_command));
1741 if (result > 0)
1742 dev->q_depth = result;
1743 else
1744 nvme_release_cmb(dev);
1745 }
1746
1747 do {
1748 size = db_bar_size(dev, nr_io_queues);
1749 result = nvme_remap_bar(dev, size);
1750 if (!result)
1751 break;
1752 if (!--nr_io_queues)
1753 return -ENOMEM;
1754 } while (1);
1755 adminq->q_db = dev->dbs;
1756
1757 /* Deregister the admin queue's interrupt */
1758 pci_free_irq(pdev, 0, adminq);
1759
1760 /*
1761 * If we enable msix early due to not intx, disable it again before
1762 * setting up the full range we need.
1763 */
1764 pci_free_irq_vectors(pdev);
1765 nr_io_queues = pci_alloc_irq_vectors(pdev, 1, nr_io_queues,
1766 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY);
1767 if (nr_io_queues <= 0)
1768 return -EIO;
1769 dev->max_qid = nr_io_queues;
1770
1771 /*
1772 * Should investigate if there's a performance win from allocating
1773 * more queues than interrupt vectors; it might allow the submission
1774 * path to scale better, even if the receive path is limited by the
1775 * number of interrupts.
1776 */
1777
1778 result = queue_request_irq(adminq);
1779 if (result) {
1780 adminq->cq_vector = -1;
1781 return result;
1782 }
1783 return nvme_create_io_queues(dev);
1784}
1785
1786static void nvme_del_queue_end(struct request *req, blk_status_t error)
1787{
1788 struct nvme_queue *nvmeq = req->end_io_data;
1789
1790 blk_mq_free_request(req);
1791 complete(&nvmeq->dev->ioq_wait);
1792}
1793
1794static void nvme_del_cq_end(struct request *req, blk_status_t error)
1795{
1796 struct nvme_queue *nvmeq = req->end_io_data;
1797
1798 if (!error) {
1799 unsigned long flags;
1800
1801 /*
1802 * We might be called with the AQ q_lock held
1803 * and the I/O queue q_lock should always
1804 * nest inside the AQ one.
1805 */
1806 spin_lock_irqsave_nested(&nvmeq->q_lock, flags,
1807 SINGLE_DEPTH_NESTING);
1808 nvme_process_cq(nvmeq);
1809 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
1810 }
1811
1812 nvme_del_queue_end(req, error);
1813}
1814
1815static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
1816{
1817 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
1818 struct request *req;
1819 struct nvme_command cmd;
1820
1821 memset(&cmd, 0, sizeof(cmd));
1822 cmd.delete_queue.opcode = opcode;
1823 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
1824
1825 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
1826 if (IS_ERR(req))
1827 return PTR_ERR(req);
1828
1829 req->timeout = ADMIN_TIMEOUT;
1830 req->end_io_data = nvmeq;
1831
1832 blk_execute_rq_nowait(q, NULL, req, false,
1833 opcode == nvme_admin_delete_cq ?
1834 nvme_del_cq_end : nvme_del_queue_end);
1835 return 0;
1836}
1837
1838static void nvme_disable_io_queues(struct nvme_dev *dev, int queues)
1839{
1840 int pass;
1841 unsigned long timeout;
1842 u8 opcode = nvme_admin_delete_sq;
1843
1844 for (pass = 0; pass < 2; pass++) {
1845 int sent = 0, i = queues;
1846
1847 reinit_completion(&dev->ioq_wait);
1848 retry:
1849 timeout = ADMIN_TIMEOUT;
1850 for (; i > 0; i--, sent++)
1851 if (nvme_delete_queue(dev->queues[i], opcode))
1852 break;
1853
1854 while (sent--) {
1855 timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout);
1856 if (timeout == 0)
1857 return;
1858 if (i)
1859 goto retry;
1860 }
1861 opcode = nvme_admin_delete_cq;
1862 }
1863}
1864
1865/*
1866 * Return: error value if an error occurred setting up the queues or calling
1867 * Identify Device. 0 if these succeeded, even if adding some of the
1868 * namespaces failed. At the moment, these failures are silent. TBD which
1869 * failures should be reported.
1870 */
1871static int nvme_dev_add(struct nvme_dev *dev)
1872{
1873 if (!dev->ctrl.tagset) {
1874 dev->tagset.ops = &nvme_mq_ops;
1875 dev->tagset.nr_hw_queues = dev->online_queues - 1;
1876 dev->tagset.timeout = NVME_IO_TIMEOUT;
1877 dev->tagset.numa_node = dev_to_node(dev->dev);
1878 dev->tagset.queue_depth =
1879 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
1880 dev->tagset.cmd_size = nvme_cmd_size(dev);
1881 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
1882 dev->tagset.driver_data = dev;
1883
1884 if (blk_mq_alloc_tag_set(&dev->tagset))
1885 return 0;
1886 dev->ctrl.tagset = &dev->tagset;
1887
1888 nvme_dbbuf_set(dev);
1889 } else {
1890 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
1891
1892 /* Free previously allocated queues that are no longer usable */
1893 nvme_free_queues(dev, dev->online_queues);
1894 }
1895
1896 return 0;
1897}
1898
1899static int nvme_pci_enable(struct nvme_dev *dev)
1900{
1901 int result = -ENOMEM;
1902 struct pci_dev *pdev = to_pci_dev(dev->dev);
1903
1904 if (pci_enable_device_mem(pdev))
1905 return result;
1906
1907 pci_set_master(pdev);
1908
1909 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
1910 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
1911 goto disable;
1912
1913 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
1914 result = -ENODEV;
1915 goto disable;
1916 }
1917
1918 /*
1919 * Some devices and/or platforms don't advertise or work with INTx
1920 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
1921 * adjust this later.
1922 */
1923 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
1924 if (result < 0)
1925 return result;
1926
1927 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1928
1929 dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1,
1930 io_queue_depth);
1931 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
1932 dev->dbs = dev->bar + 4096;
1933
1934 /*
1935 * Temporary fix for the Apple controller found in the MacBook8,1 and
1936 * some MacBook7,1 to avoid controller resets and data loss.
1937 */
1938 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
1939 dev->q_depth = 2;
1940 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
1941 "set queue depth=%u to work around controller resets\n",
1942 dev->q_depth);
1943 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
1944 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
1945 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
1946 dev->q_depth = 64;
1947 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
1948 "set queue depth=%u\n", dev->q_depth);
1949 }
1950
1951 /*
1952 * CMBs can currently only exist on >=1.2 PCIe devices. We only
1953 * populate sysfs if a CMB is implemented. Since nvme_dev_attrs_group
1954 * has no name we can pass NULL as final argument to
1955 * sysfs_add_file_to_group.
1956 */
1957
1958 if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2, 0)) {
1959 dev->cmb = nvme_map_cmb(dev);
1960 if (dev->cmb) {
1961 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1962 &dev_attr_cmb.attr, NULL))
1963 dev_warn(dev->ctrl.device,
1964 "failed to add sysfs attribute for CMB\n");
1965 }
1966 }
1967
1968 pci_enable_pcie_error_reporting(pdev);
1969 pci_save_state(pdev);
1970 return 0;
1971
1972 disable:
1973 pci_disable_device(pdev);
1974 return result;
1975}
1976
1977static void nvme_dev_unmap(struct nvme_dev *dev)
1978{
1979 if (dev->bar)
1980 iounmap(dev->bar);
1981 pci_release_mem_regions(to_pci_dev(dev->dev));
1982}
1983
1984static void nvme_pci_disable(struct nvme_dev *dev)
1985{
1986 struct pci_dev *pdev = to_pci_dev(dev->dev);
1987
1988 nvme_release_cmb(dev);
1989 pci_free_irq_vectors(pdev);
1990
1991 if (pci_is_enabled(pdev)) {
1992 pci_disable_pcie_error_reporting(pdev);
1993 pci_disable_device(pdev);
1994 }
1995}
1996
1997static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
1998{
1999 int i, queues;
2000 bool dead = true;
2001 struct pci_dev *pdev = to_pci_dev(dev->dev);
2002
2003 mutex_lock(&dev->shutdown_lock);
2004 if (pci_is_enabled(pdev)) {
2005 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2006
2007 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2008 dev->ctrl.state == NVME_CTRL_RESETTING)
2009 nvme_start_freeze(&dev->ctrl);
2010 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2011 pdev->error_state != pci_channel_io_normal);
2012 }
2013
2014 /*
2015 * Give the controller a chance to complete all entered requests if
2016 * doing a safe shutdown.
2017 */
2018 if (!dead) {
2019 if (shutdown)
2020 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
2021
2022 /*
2023 * If the controller is still alive tell it to stop using the
2024 * host memory buffer. In theory the shutdown / reset should
2025 * make sure that it doesn't access the host memoery anymore,
2026 * but I'd rather be safe than sorry..
2027 */
2028 if (dev->host_mem_descs)
2029 nvme_set_host_mem(dev, 0);
2030
2031 }
2032 nvme_stop_queues(&dev->ctrl);
2033
2034 queues = dev->online_queues - 1;
2035 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
2036 nvme_suspend_queue(dev->queues[i]);
2037
2038 if (dead) {
2039 /* A device might become IO incapable very soon during
2040 * probe, before the admin queue is configured. Thus,
2041 * queue_count can be 0 here.
2042 */
2043 if (dev->ctrl.queue_count)
2044 nvme_suspend_queue(dev->queues[0]);
2045 } else {
2046 nvme_disable_io_queues(dev, queues);
2047 nvme_disable_admin_queue(dev, shutdown);
2048 }
2049 nvme_pci_disable(dev);
2050
2051 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2052 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
2053
2054 /*
2055 * The driver will not be starting up queues again if shutting down so
2056 * must flush all entered requests to their failed completion to avoid
2057 * deadlocking blk-mq hot-cpu notifier.
2058 */
2059 if (shutdown)
2060 nvme_start_queues(&dev->ctrl);
2061 mutex_unlock(&dev->shutdown_lock);
2062}
2063
2064static int nvme_setup_prp_pools(struct nvme_dev *dev)
2065{
2066 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2067 PAGE_SIZE, PAGE_SIZE, 0);
2068 if (!dev->prp_page_pool)
2069 return -ENOMEM;
2070
2071 /* Optimisation for I/Os between 4k and 128k */
2072 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2073 256, 256, 0);
2074 if (!dev->prp_small_pool) {
2075 dma_pool_destroy(dev->prp_page_pool);
2076 return -ENOMEM;
2077 }
2078 return 0;
2079}
2080
2081static void nvme_release_prp_pools(struct nvme_dev *dev)
2082{
2083 dma_pool_destroy(dev->prp_page_pool);
2084 dma_pool_destroy(dev->prp_small_pool);
2085}
2086
2087static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2088{
2089 struct nvme_dev *dev = to_nvme_dev(ctrl);
2090
2091 nvme_dbbuf_dma_free(dev);
2092 put_device(dev->dev);
2093 if (dev->tagset.tags)
2094 blk_mq_free_tag_set(&dev->tagset);
2095 if (dev->ctrl.admin_q)
2096 blk_put_queue(dev->ctrl.admin_q);
2097 kfree(dev->queues);
2098 free_opal_dev(dev->ctrl.opal_dev);
2099 kfree(dev);
2100}
2101
2102static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
2103{
2104 dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
2105
2106 kref_get(&dev->ctrl.kref);
2107 nvme_dev_disable(dev, false);
2108 if (!schedule_work(&dev->remove_work))
2109 nvme_put_ctrl(&dev->ctrl);
2110}
2111
2112static void nvme_reset_work(struct work_struct *work)
2113{
2114 struct nvme_dev *dev =
2115 container_of(work, struct nvme_dev, ctrl.reset_work);
2116 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2117 int result = -ENODEV;
2118
2119 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING))
2120 goto out;
2121
2122 /*
2123 * If we're called to reset a live controller first shut it down before
2124 * moving on.
2125 */
2126 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2127 nvme_dev_disable(dev, false);
2128
2129 result = nvme_pci_enable(dev);
2130 if (result)
2131 goto out;
2132
2133 result = nvme_pci_configure_admin_queue(dev);
2134 if (result)
2135 goto out;
2136
2137 nvme_init_queue(dev->queues[0], 0);
2138 result = nvme_alloc_admin_tags(dev);
2139 if (result)
2140 goto out;
2141
2142 result = nvme_init_identify(&dev->ctrl);
2143 if (result)
2144 goto out;
2145
2146 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2147 if (!dev->ctrl.opal_dev)
2148 dev->ctrl.opal_dev =
2149 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2150 else if (was_suspend)
2151 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2152 } else {
2153 free_opal_dev(dev->ctrl.opal_dev);
2154 dev->ctrl.opal_dev = NULL;
2155 }
2156
2157 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2158 result = nvme_dbbuf_dma_alloc(dev);
2159 if (result)
2160 dev_warn(dev->dev,
2161 "unable to allocate dma for dbbuf\n");
2162 }
2163
2164 if (dev->ctrl.hmpre)
2165 nvme_setup_host_mem(dev);
2166
2167 result = nvme_setup_io_queues(dev);
2168 if (result)
2169 goto out;
2170
2171 /*
2172 * Keep the controller around but remove all namespaces if we don't have
2173 * any working I/O queue.
2174 */
2175 if (dev->online_queues < 2) {
2176 dev_warn(dev->ctrl.device, "IO queues not created\n");
2177 nvme_kill_queues(&dev->ctrl);
2178 nvme_remove_namespaces(&dev->ctrl);
2179 } else {
2180 nvme_start_queues(&dev->ctrl);
2181 nvme_wait_freeze(&dev->ctrl);
2182 nvme_dev_add(dev);
2183 nvme_unfreeze(&dev->ctrl);
2184 }
2185
2186 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2187 dev_warn(dev->ctrl.device, "failed to mark controller live\n");
2188 goto out;
2189 }
2190
2191 nvme_start_ctrl(&dev->ctrl);
2192 return;
2193
2194 out:
2195 nvme_remove_dead_ctrl(dev, result);
2196}
2197
2198static void nvme_remove_dead_ctrl_work(struct work_struct *work)
2199{
2200 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
2201 struct pci_dev *pdev = to_pci_dev(dev->dev);
2202
2203 nvme_kill_queues(&dev->ctrl);
2204 if (pci_get_drvdata(pdev))
2205 device_release_driver(&pdev->dev);
2206 nvme_put_ctrl(&dev->ctrl);
2207}
2208
2209static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2210{
2211 *val = readl(to_nvme_dev(ctrl)->bar + off);
2212 return 0;
2213}
2214
2215static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2216{
2217 writel(val, to_nvme_dev(ctrl)->bar + off);
2218 return 0;
2219}
2220
2221static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2222{
2223 *val = readq(to_nvme_dev(ctrl)->bar + off);
2224 return 0;
2225}
2226
2227static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2228 .name = "pcie",
2229 .module = THIS_MODULE,
2230 .flags = NVME_F_METADATA_SUPPORTED,
2231 .reg_read32 = nvme_pci_reg_read32,
2232 .reg_write32 = nvme_pci_reg_write32,
2233 .reg_read64 = nvme_pci_reg_read64,
2234 .free_ctrl = nvme_pci_free_ctrl,
2235 .submit_async_event = nvme_pci_submit_async_event,
2236};
2237
2238static int nvme_dev_map(struct nvme_dev *dev)
2239{
2240 struct pci_dev *pdev = to_pci_dev(dev->dev);
2241
2242 if (pci_request_mem_regions(pdev, "nvme"))
2243 return -ENODEV;
2244
2245 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
2246 goto release;
2247
2248 return 0;
2249 release:
2250 pci_release_mem_regions(pdev);
2251 return -ENODEV;
2252}
2253
2254static unsigned long check_dell_samsung_bug(struct pci_dev *pdev)
2255{
2256 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2257 /*
2258 * Several Samsung devices seem to drop off the PCIe bus
2259 * randomly when APST is on and uses the deepest sleep state.
2260 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2261 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2262 * 950 PRO 256GB", but it seems to be restricted to two Dell
2263 * laptops.
2264 */
2265 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2266 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2267 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2268 return NVME_QUIRK_NO_DEEPEST_PS;
2269 }
2270
2271 return 0;
2272}
2273
2274static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2275{
2276 int node, result = -ENOMEM;
2277 struct nvme_dev *dev;
2278 unsigned long quirks = id->driver_data;
2279
2280 node = dev_to_node(&pdev->dev);
2281 if (node == NUMA_NO_NODE)
2282 set_dev_node(&pdev->dev, first_memory_node);
2283
2284 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2285 if (!dev)
2286 return -ENOMEM;
2287 dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
2288 GFP_KERNEL, node);
2289 if (!dev->queues)
2290 goto free;
2291
2292 dev->dev = get_device(&pdev->dev);
2293 pci_set_drvdata(pdev, dev);
2294
2295 result = nvme_dev_map(dev);
2296 if (result)
2297 goto put_pci;
2298
2299 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
2300 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
2301 mutex_init(&dev->shutdown_lock);
2302 init_completion(&dev->ioq_wait);
2303
2304 result = nvme_setup_prp_pools(dev);
2305 if (result)
2306 goto unmap;
2307
2308 quirks |= check_dell_samsung_bug(pdev);
2309
2310 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2311 quirks);
2312 if (result)
2313 goto release_pools;
2314
2315 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING);
2316 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2317
2318 queue_work(nvme_wq, &dev->ctrl.reset_work);
2319 return 0;
2320
2321 release_pools:
2322 nvme_release_prp_pools(dev);
2323 unmap:
2324 nvme_dev_unmap(dev);
2325 put_pci:
2326 put_device(dev->dev);
2327 free:
2328 kfree(dev->queues);
2329 kfree(dev);
2330 return result;
2331}
2332
2333static void nvme_reset_prepare(struct pci_dev *pdev)
2334{
2335 struct nvme_dev *dev = pci_get_drvdata(pdev);
2336 nvme_dev_disable(dev, false);
2337}
2338
2339static void nvme_reset_done(struct pci_dev *pdev)
2340{
2341 struct nvme_dev *dev = pci_get_drvdata(pdev);
2342 nvme_reset_ctrl(&dev->ctrl);
2343}
2344
2345static void nvme_shutdown(struct pci_dev *pdev)
2346{
2347 struct nvme_dev *dev = pci_get_drvdata(pdev);
2348 nvme_dev_disable(dev, true);
2349}
2350
2351/*
2352 * The driver's remove may be called on a device in a partially initialized
2353 * state. This function must not have any dependencies on the device state in
2354 * order to proceed.
2355 */
2356static void nvme_remove(struct pci_dev *pdev)
2357{
2358 struct nvme_dev *dev = pci_get_drvdata(pdev);
2359
2360 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2361
2362 cancel_work_sync(&dev->ctrl.reset_work);
2363 pci_set_drvdata(pdev, NULL);
2364
2365 if (!pci_device_is_present(pdev)) {
2366 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
2367 nvme_dev_disable(dev, false);
2368 }
2369
2370 flush_work(&dev->ctrl.reset_work);
2371 nvme_stop_ctrl(&dev->ctrl);
2372 nvme_remove_namespaces(&dev->ctrl);
2373 nvme_dev_disable(dev, true);
2374 nvme_free_host_mem(dev);
2375 nvme_dev_remove_admin(dev);
2376 nvme_free_queues(dev, 0);
2377 nvme_uninit_ctrl(&dev->ctrl);
2378 nvme_release_prp_pools(dev);
2379 nvme_dev_unmap(dev);
2380 nvme_put_ctrl(&dev->ctrl);
2381}
2382
2383static int nvme_pci_sriov_configure(struct pci_dev *pdev, int numvfs)
2384{
2385 int ret = 0;
2386
2387 if (numvfs == 0) {
2388 if (pci_vfs_assigned(pdev)) {
2389 dev_warn(&pdev->dev,
2390 "Cannot disable SR-IOV VFs while assigned\n");
2391 return -EPERM;
2392 }
2393 pci_disable_sriov(pdev);
2394 return 0;
2395 }
2396
2397 ret = pci_enable_sriov(pdev, numvfs);
2398 return ret ? ret : numvfs;
2399}
2400
2401#ifdef CONFIG_PM_SLEEP
2402static int nvme_suspend(struct device *dev)
2403{
2404 struct pci_dev *pdev = to_pci_dev(dev);
2405 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2406
2407 nvme_dev_disable(ndev, true);
2408 return 0;
2409}
2410
2411static int nvme_resume(struct device *dev)
2412{
2413 struct pci_dev *pdev = to_pci_dev(dev);
2414 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2415
2416 nvme_reset_ctrl(&ndev->ctrl);
2417 return 0;
2418}
2419#endif
2420
2421static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
2422
2423static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2424 pci_channel_state_t state)
2425{
2426 struct nvme_dev *dev = pci_get_drvdata(pdev);
2427
2428 /*
2429 * A frozen channel requires a reset. When detected, this method will
2430 * shutdown the controller to quiesce. The controller will be restarted
2431 * after the slot reset through driver's slot_reset callback.
2432 */
2433 switch (state) {
2434 case pci_channel_io_normal:
2435 return PCI_ERS_RESULT_CAN_RECOVER;
2436 case pci_channel_io_frozen:
2437 dev_warn(dev->ctrl.device,
2438 "frozen state error detected, reset controller\n");
2439 nvme_dev_disable(dev, false);
2440 return PCI_ERS_RESULT_NEED_RESET;
2441 case pci_channel_io_perm_failure:
2442 dev_warn(dev->ctrl.device,
2443 "failure state error detected, request disconnect\n");
2444 return PCI_ERS_RESULT_DISCONNECT;
2445 }
2446 return PCI_ERS_RESULT_NEED_RESET;
2447}
2448
2449static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2450{
2451 struct nvme_dev *dev = pci_get_drvdata(pdev);
2452
2453 dev_info(dev->ctrl.device, "restart after slot reset\n");
2454 pci_restore_state(pdev);
2455 nvme_reset_ctrl(&dev->ctrl);
2456 return PCI_ERS_RESULT_RECOVERED;
2457}
2458
2459static void nvme_error_resume(struct pci_dev *pdev)
2460{
2461 pci_cleanup_aer_uncorrect_error_status(pdev);
2462}
2463
2464static const struct pci_error_handlers nvme_err_handler = {
2465 .error_detected = nvme_error_detected,
2466 .slot_reset = nvme_slot_reset,
2467 .resume = nvme_error_resume,
2468 .reset_prepare = nvme_reset_prepare,
2469 .reset_done = nvme_reset_done,
2470};
2471
2472static const struct pci_device_id nvme_id_table[] = {
2473 { PCI_VDEVICE(INTEL, 0x0953),
2474 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2475 NVME_QUIRK_DEALLOCATE_ZEROES, },
2476 { PCI_VDEVICE(INTEL, 0x0a53),
2477 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2478 NVME_QUIRK_DEALLOCATE_ZEROES, },
2479 { PCI_VDEVICE(INTEL, 0x0a54),
2480 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2481 NVME_QUIRK_DEALLOCATE_ZEROES, },
2482 { PCI_VDEVICE(INTEL, 0x0a55),
2483 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2484 NVME_QUIRK_DEALLOCATE_ZEROES, },
2485 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
2486 .driver_data = NVME_QUIRK_NO_DEEPEST_PS },
2487 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
2488 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
2489 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
2490 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2491 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
2492 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2493 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
2494 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2495 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
2496 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2497 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2498 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
2499 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
2500 { 0, }
2501};
2502MODULE_DEVICE_TABLE(pci, nvme_id_table);
2503
2504static struct pci_driver nvme_driver = {
2505 .name = "nvme",
2506 .id_table = nvme_id_table,
2507 .probe = nvme_probe,
2508 .remove = nvme_remove,
2509 .shutdown = nvme_shutdown,
2510 .driver = {
2511 .pm = &nvme_dev_pm_ops,
2512 },
2513 .sriov_configure = nvme_pci_sriov_configure,
2514 .err_handler = &nvme_err_handler,
2515};
2516
2517static int __init nvme_init(void)
2518{
2519 return pci_register_driver(&nvme_driver);
2520}
2521
2522static void __exit nvme_exit(void)
2523{
2524 pci_unregister_driver(&nvme_driver);
2525 _nvme_check_size();
2526}
2527
2528MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2529MODULE_LICENSE("GPL");
2530MODULE_VERSION("1.0");
2531module_init(nvme_init);
2532module_exit(nvme_exit);
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