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1 | /* Low-level parallel-port routines for 8255-based PC-style hardware. | |
2 | * | |
3 | * Authors: Phil Blundell <philb@gnu.org> | |
4 | * Tim Waugh <tim@cyberelk.demon.co.uk> | |
5 | * Jose Renau <renau@acm.org> | |
6 | * David Campbell | |
7 | * Andrea Arcangeli | |
8 | * | |
9 | * based on work by Grant Guenther <grant@torque.net> and Phil Blundell. | |
10 | * | |
11 | * Cleaned up include files - Russell King <linux@arm.uk.linux.org> | |
12 | * DMA support - Bert De Jonghe <bert@sophis.be> | |
13 | * Many ECP bugs fixed. Fred Barnes & Jamie Lokier, 1999 | |
14 | * More PCI support now conditional on CONFIG_PCI, 03/2001, Paul G. | |
15 | * Various hacks, Fred Barnes, 04/2001 | |
16 | * Updated probing logic - Adam Belay <ambx1@neo.rr.com> | |
17 | */ | |
18 | ||
19 | /* This driver should work with any hardware that is broadly compatible | |
20 | * with that in the IBM PC. This applies to the majority of integrated | |
21 | * I/O chipsets that are commonly available. The expected register | |
22 | * layout is: | |
23 | * | |
24 | * base+0 data | |
25 | * base+1 status | |
26 | * base+2 control | |
27 | * | |
28 | * In addition, there are some optional registers: | |
29 | * | |
30 | * base+3 EPP address | |
31 | * base+4 EPP data | |
32 | * base+0x400 ECP config A | |
33 | * base+0x401 ECP config B | |
34 | * base+0x402 ECP control | |
35 | * | |
36 | * All registers are 8 bits wide and read/write. If your hardware differs | |
37 | * only in register addresses (eg because your registers are on 32-bit | |
38 | * word boundaries) then you can alter the constants in parport_pc.h to | |
39 | * accommodate this. | |
40 | * | |
41 | * Note that the ECP registers may not start at offset 0x400 for PCI cards, | |
42 | * but rather will start at port->base_hi. | |
43 | */ | |
44 | ||
45 | #include <linux/module.h> | |
46 | #include <linux/init.h> | |
47 | #include <linux/sched.h> | |
48 | #include <linux/delay.h> | |
49 | #include <linux/errno.h> | |
50 | #include <linux/interrupt.h> | |
51 | #include <linux/ioport.h> | |
52 | #include <linux/kernel.h> | |
53 | #include <linux/slab.h> | |
54 | #include <linux/dma-mapping.h> | |
55 | #include <linux/pci.h> | |
56 | #include <linux/pnp.h> | |
57 | #include <linux/platform_device.h> | |
58 | #include <linux/sysctl.h> | |
59 | #include <linux/io.h> | |
60 | #include <linux/uaccess.h> | |
61 | ||
62 | #include <asm/dma.h> | |
63 | ||
64 | #include <linux/parport.h> | |
65 | #include <linux/parport_pc.h> | |
66 | #include <linux/via.h> | |
67 | #include <asm/parport.h> | |
68 | ||
69 | #define PARPORT_PC_MAX_PORTS PARPORT_MAX | |
70 | ||
71 | #ifdef CONFIG_ISA_DMA_API | |
72 | #define HAS_DMA | |
73 | #endif | |
74 | ||
75 | /* ECR modes */ | |
76 | #define ECR_SPP 00 | |
77 | #define ECR_PS2 01 | |
78 | #define ECR_PPF 02 | |
79 | #define ECR_ECP 03 | |
80 | #define ECR_EPP 04 | |
81 | #define ECR_VND 05 | |
82 | #define ECR_TST 06 | |
83 | #define ECR_CNF 07 | |
84 | #define ECR_MODE_MASK 0xe0 | |
85 | #define ECR_WRITE(p, v) frob_econtrol((p), 0xff, (v)) | |
86 | ||
87 | #undef DEBUG | |
88 | ||
89 | #ifdef DEBUG | |
90 | #define DPRINTK printk | |
91 | #else | |
92 | #define DPRINTK(stuff...) | |
93 | #endif | |
94 | ||
95 | ||
96 | #define NR_SUPERIOS 3 | |
97 | static struct superio_struct { /* For Super-IO chips autodetection */ | |
98 | int io; | |
99 | int irq; | |
100 | int dma; | |
101 | } superios[NR_SUPERIOS] = { {0,},}; | |
102 | ||
103 | static int user_specified; | |
104 | #if defined(CONFIG_PARPORT_PC_SUPERIO) || \ | |
105 | (defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO)) | |
106 | static int verbose_probing; | |
107 | #endif | |
108 | static int pci_registered_parport; | |
109 | static int pnp_registered_parport; | |
110 | ||
111 | /* frob_control, but for ECR */ | |
112 | static void frob_econtrol(struct parport *pb, unsigned char m, | |
113 | unsigned char v) | |
114 | { | |
115 | unsigned char ectr = 0; | |
116 | ||
117 | if (m != 0xff) | |
118 | ectr = inb(ECONTROL(pb)); | |
119 | ||
120 | DPRINTK(KERN_DEBUG "frob_econtrol(%02x,%02x): %02x -> %02x\n", | |
121 | m, v, ectr, (ectr & ~m) ^ v); | |
122 | ||
123 | outb((ectr & ~m) ^ v, ECONTROL(pb)); | |
124 | } | |
125 | ||
126 | static inline void frob_set_mode(struct parport *p, int mode) | |
127 | { | |
128 | frob_econtrol(p, ECR_MODE_MASK, mode << 5); | |
129 | } | |
130 | ||
131 | #ifdef CONFIG_PARPORT_PC_FIFO | |
132 | /* Safely change the mode bits in the ECR | |
133 | Returns: | |
134 | 0 : Success | |
135 | -EBUSY: Could not drain FIFO in some finite amount of time, | |
136 | mode not changed! | |
137 | */ | |
138 | static int change_mode(struct parport *p, int m) | |
139 | { | |
140 | const struct parport_pc_private *priv = p->physport->private_data; | |
141 | unsigned char oecr; | |
142 | int mode; | |
143 | ||
144 | DPRINTK(KERN_INFO "parport change_mode ECP-ISA to mode 0x%02x\n", m); | |
145 | ||
146 | if (!priv->ecr) { | |
147 | printk(KERN_DEBUG "change_mode: but there's no ECR!\n"); | |
148 | return 0; | |
149 | } | |
150 | ||
151 | /* Bits <7:5> contain the mode. */ | |
152 | oecr = inb(ECONTROL(p)); | |
153 | mode = (oecr >> 5) & 0x7; | |
154 | if (mode == m) | |
155 | return 0; | |
156 | ||
157 | if (mode >= 2 && !(priv->ctr & 0x20)) { | |
158 | /* This mode resets the FIFO, so we may | |
159 | * have to wait for it to drain first. */ | |
160 | unsigned long expire = jiffies + p->physport->cad->timeout; | |
161 | int counter; | |
162 | switch (mode) { | |
163 | case ECR_PPF: /* Parallel Port FIFO mode */ | |
164 | case ECR_ECP: /* ECP Parallel Port mode */ | |
165 | /* Busy wait for 200us */ | |
166 | for (counter = 0; counter < 40; counter++) { | |
167 | if (inb(ECONTROL(p)) & 0x01) | |
168 | break; | |
169 | if (signal_pending(current)) | |
170 | break; | |
171 | udelay(5); | |
172 | } | |
173 | ||
174 | /* Poll slowly. */ | |
175 | while (!(inb(ECONTROL(p)) & 0x01)) { | |
176 | if (time_after_eq(jiffies, expire)) | |
177 | /* The FIFO is stuck. */ | |
178 | return -EBUSY; | |
179 | schedule_timeout_interruptible( | |
180 | msecs_to_jiffies(10)); | |
181 | if (signal_pending(current)) | |
182 | break; | |
183 | } | |
184 | } | |
185 | } | |
186 | ||
187 | if (mode >= 2 && m >= 2) { | |
188 | /* We have to go through mode 001 */ | |
189 | oecr &= ~(7 << 5); | |
190 | oecr |= ECR_PS2 << 5; | |
191 | ECR_WRITE(p, oecr); | |
192 | } | |
193 | ||
194 | /* Set the mode. */ | |
195 | oecr &= ~(7 << 5); | |
196 | oecr |= m << 5; | |
197 | ECR_WRITE(p, oecr); | |
198 | return 0; | |
199 | } | |
200 | #endif /* FIFO support */ | |
201 | ||
202 | /* | |
203 | * Clear TIMEOUT BIT in EPP MODE | |
204 | * | |
205 | * This is also used in SPP detection. | |
206 | */ | |
207 | static int clear_epp_timeout(struct parport *pb) | |
208 | { | |
209 | unsigned char r; | |
210 | ||
211 | if (!(parport_pc_read_status(pb) & 0x01)) | |
212 | return 1; | |
213 | ||
214 | /* To clear timeout some chips require double read */ | |
215 | parport_pc_read_status(pb); | |
216 | r = parport_pc_read_status(pb); | |
217 | outb(r | 0x01, STATUS(pb)); /* Some reset by writing 1 */ | |
218 | outb(r & 0xfe, STATUS(pb)); /* Others by writing 0 */ | |
219 | r = parport_pc_read_status(pb); | |
220 | ||
221 | return !(r & 0x01); | |
222 | } | |
223 | ||
224 | /* | |
225 | * Access functions. | |
226 | * | |
227 | * Most of these aren't static because they may be used by the | |
228 | * parport_xxx_yyy macros. extern __inline__ versions of several | |
229 | * of these are in parport_pc.h. | |
230 | */ | |
231 | ||
232 | static void parport_pc_init_state(struct pardevice *dev, | |
233 | struct parport_state *s) | |
234 | { | |
235 | s->u.pc.ctr = 0xc; | |
236 | if (dev->irq_func && | |
237 | dev->port->irq != PARPORT_IRQ_NONE) | |
238 | /* Set ackIntEn */ | |
239 | s->u.pc.ctr |= 0x10; | |
240 | ||
241 | s->u.pc.ecr = 0x34; /* NetMos chip can cause problems 0x24; | |
242 | * D.Gruszka VScom */ | |
243 | } | |
244 | ||
245 | static void parport_pc_save_state(struct parport *p, struct parport_state *s) | |
246 | { | |
247 | const struct parport_pc_private *priv = p->physport->private_data; | |
248 | s->u.pc.ctr = priv->ctr; | |
249 | if (priv->ecr) | |
250 | s->u.pc.ecr = inb(ECONTROL(p)); | |
251 | } | |
252 | ||
253 | static void parport_pc_restore_state(struct parport *p, | |
254 | struct parport_state *s) | |
255 | { | |
256 | struct parport_pc_private *priv = p->physport->private_data; | |
257 | register unsigned char c = s->u.pc.ctr & priv->ctr_writable; | |
258 | outb(c, CONTROL(p)); | |
259 | priv->ctr = c; | |
260 | if (priv->ecr) | |
261 | ECR_WRITE(p, s->u.pc.ecr); | |
262 | } | |
263 | ||
264 | #ifdef CONFIG_PARPORT_1284 | |
265 | static size_t parport_pc_epp_read_data(struct parport *port, void *buf, | |
266 | size_t length, int flags) | |
267 | { | |
268 | size_t got = 0; | |
269 | ||
270 | if (flags & PARPORT_W91284PIC) { | |
271 | unsigned char status; | |
272 | size_t left = length; | |
273 | ||
274 | /* use knowledge about data lines..: | |
275 | * nFault is 0 if there is at least 1 byte in the Warp's FIFO | |
276 | * pError is 1 if there are 16 bytes in the Warp's FIFO | |
277 | */ | |
278 | status = inb(STATUS(port)); | |
279 | ||
280 | while (!(status & 0x08) && got < length) { | |
281 | if (left >= 16 && (status & 0x20) && !(status & 0x08)) { | |
282 | /* can grab 16 bytes from warp fifo */ | |
283 | if (!((long)buf & 0x03)) | |
284 | insl(EPPDATA(port), buf, 4); | |
285 | else | |
286 | insb(EPPDATA(port), buf, 16); | |
287 | buf += 16; | |
288 | got += 16; | |
289 | left -= 16; | |
290 | } else { | |
291 | /* grab single byte from the warp fifo */ | |
292 | *((char *)buf) = inb(EPPDATA(port)); | |
293 | buf++; | |
294 | got++; | |
295 | left--; | |
296 | } | |
297 | status = inb(STATUS(port)); | |
298 | if (status & 0x01) { | |
299 | /* EPP timeout should never occur... */ | |
300 | printk(KERN_DEBUG | |
301 | "%s: EPP timeout occurred while talking to w91284pic (should not have done)\n", port->name); | |
302 | clear_epp_timeout(port); | |
303 | } | |
304 | } | |
305 | return got; | |
306 | } | |
307 | if ((flags & PARPORT_EPP_FAST) && (length > 1)) { | |
308 | if (!(((long)buf | length) & 0x03)) | |
309 | insl(EPPDATA(port), buf, (length >> 2)); | |
310 | else | |
311 | insb(EPPDATA(port), buf, length); | |
312 | if (inb(STATUS(port)) & 0x01) { | |
313 | clear_epp_timeout(port); | |
314 | return -EIO; | |
315 | } | |
316 | return length; | |
317 | } | |
318 | for (; got < length; got++) { | |
319 | *((char *)buf) = inb(EPPDATA(port)); | |
320 | buf++; | |
321 | if (inb(STATUS(port)) & 0x01) { | |
322 | /* EPP timeout */ | |
323 | clear_epp_timeout(port); | |
324 | break; | |
325 | } | |
326 | } | |
327 | ||
328 | return got; | |
329 | } | |
330 | ||
331 | static size_t parport_pc_epp_write_data(struct parport *port, const void *buf, | |
332 | size_t length, int flags) | |
333 | { | |
334 | size_t written = 0; | |
335 | ||
336 | if ((flags & PARPORT_EPP_FAST) && (length > 1)) { | |
337 | if (!(((long)buf | length) & 0x03)) | |
338 | outsl(EPPDATA(port), buf, (length >> 2)); | |
339 | else | |
340 | outsb(EPPDATA(port), buf, length); | |
341 | if (inb(STATUS(port)) & 0x01) { | |
342 | clear_epp_timeout(port); | |
343 | return -EIO; | |
344 | } | |
345 | return length; | |
346 | } | |
347 | for (; written < length; written++) { | |
348 | outb(*((char *)buf), EPPDATA(port)); | |
349 | buf++; | |
350 | if (inb(STATUS(port)) & 0x01) { | |
351 | clear_epp_timeout(port); | |
352 | break; | |
353 | } | |
354 | } | |
355 | ||
356 | return written; | |
357 | } | |
358 | ||
359 | static size_t parport_pc_epp_read_addr(struct parport *port, void *buf, | |
360 | size_t length, int flags) | |
361 | { | |
362 | size_t got = 0; | |
363 | ||
364 | if ((flags & PARPORT_EPP_FAST) && (length > 1)) { | |
365 | insb(EPPADDR(port), buf, length); | |
366 | if (inb(STATUS(port)) & 0x01) { | |
367 | clear_epp_timeout(port); | |
368 | return -EIO; | |
369 | } | |
370 | return length; | |
371 | } | |
372 | for (; got < length; got++) { | |
373 | *((char *)buf) = inb(EPPADDR(port)); | |
374 | buf++; | |
375 | if (inb(STATUS(port)) & 0x01) { | |
376 | clear_epp_timeout(port); | |
377 | break; | |
378 | } | |
379 | } | |
380 | ||
381 | return got; | |
382 | } | |
383 | ||
384 | static size_t parport_pc_epp_write_addr(struct parport *port, | |
385 | const void *buf, size_t length, | |
386 | int flags) | |
387 | { | |
388 | size_t written = 0; | |
389 | ||
390 | if ((flags & PARPORT_EPP_FAST) && (length > 1)) { | |
391 | outsb(EPPADDR(port), buf, length); | |
392 | if (inb(STATUS(port)) & 0x01) { | |
393 | clear_epp_timeout(port); | |
394 | return -EIO; | |
395 | } | |
396 | return length; | |
397 | } | |
398 | for (; written < length; written++) { | |
399 | outb(*((char *)buf), EPPADDR(port)); | |
400 | buf++; | |
401 | if (inb(STATUS(port)) & 0x01) { | |
402 | clear_epp_timeout(port); | |
403 | break; | |
404 | } | |
405 | } | |
406 | ||
407 | return written; | |
408 | } | |
409 | ||
410 | static size_t parport_pc_ecpepp_read_data(struct parport *port, void *buf, | |
411 | size_t length, int flags) | |
412 | { | |
413 | size_t got; | |
414 | ||
415 | frob_set_mode(port, ECR_EPP); | |
416 | parport_pc_data_reverse(port); | |
417 | parport_pc_write_control(port, 0x4); | |
418 | got = parport_pc_epp_read_data(port, buf, length, flags); | |
419 | frob_set_mode(port, ECR_PS2); | |
420 | ||
421 | return got; | |
422 | } | |
423 | ||
424 | static size_t parport_pc_ecpepp_write_data(struct parport *port, | |
425 | const void *buf, size_t length, | |
426 | int flags) | |
427 | { | |
428 | size_t written; | |
429 | ||
430 | frob_set_mode(port, ECR_EPP); | |
431 | parport_pc_write_control(port, 0x4); | |
432 | parport_pc_data_forward(port); | |
433 | written = parport_pc_epp_write_data(port, buf, length, flags); | |
434 | frob_set_mode(port, ECR_PS2); | |
435 | ||
436 | return written; | |
437 | } | |
438 | ||
439 | static size_t parport_pc_ecpepp_read_addr(struct parport *port, void *buf, | |
440 | size_t length, int flags) | |
441 | { | |
442 | size_t got; | |
443 | ||
444 | frob_set_mode(port, ECR_EPP); | |
445 | parport_pc_data_reverse(port); | |
446 | parport_pc_write_control(port, 0x4); | |
447 | got = parport_pc_epp_read_addr(port, buf, length, flags); | |
448 | frob_set_mode(port, ECR_PS2); | |
449 | ||
450 | return got; | |
451 | } | |
452 | ||
453 | static size_t parport_pc_ecpepp_write_addr(struct parport *port, | |
454 | const void *buf, size_t length, | |
455 | int flags) | |
456 | { | |
457 | size_t written; | |
458 | ||
459 | frob_set_mode(port, ECR_EPP); | |
460 | parport_pc_write_control(port, 0x4); | |
461 | parport_pc_data_forward(port); | |
462 | written = parport_pc_epp_write_addr(port, buf, length, flags); | |
463 | frob_set_mode(port, ECR_PS2); | |
464 | ||
465 | return written; | |
466 | } | |
467 | #endif /* IEEE 1284 support */ | |
468 | ||
469 | #ifdef CONFIG_PARPORT_PC_FIFO | |
470 | static size_t parport_pc_fifo_write_block_pio(struct parport *port, | |
471 | const void *buf, size_t length) | |
472 | { | |
473 | int ret = 0; | |
474 | const unsigned char *bufp = buf; | |
475 | size_t left = length; | |
476 | unsigned long expire = jiffies + port->physport->cad->timeout; | |
477 | const int fifo = FIFO(port); | |
478 | int poll_for = 8; /* 80 usecs */ | |
479 | const struct parport_pc_private *priv = port->physport->private_data; | |
480 | const int fifo_depth = priv->fifo_depth; | |
481 | ||
482 | port = port->physport; | |
483 | ||
484 | /* We don't want to be interrupted every character. */ | |
485 | parport_pc_disable_irq(port); | |
486 | /* set nErrIntrEn and serviceIntr */ | |
487 | frob_econtrol(port, (1<<4) | (1<<2), (1<<4) | (1<<2)); | |
488 | ||
489 | /* Forward mode. */ | |
490 | parport_pc_data_forward(port); /* Must be in PS2 mode */ | |
491 | ||
492 | while (left) { | |
493 | unsigned char byte; | |
494 | unsigned char ecrval = inb(ECONTROL(port)); | |
495 | int i = 0; | |
496 | ||
497 | if (need_resched() && time_before(jiffies, expire)) | |
498 | /* Can't yield the port. */ | |
499 | schedule(); | |
500 | ||
501 | /* Anyone else waiting for the port? */ | |
502 | if (port->waithead) { | |
503 | printk(KERN_DEBUG "Somebody wants the port\n"); | |
504 | break; | |
505 | } | |
506 | ||
507 | if (ecrval & 0x02) { | |
508 | /* FIFO is full. Wait for interrupt. */ | |
509 | ||
510 | /* Clear serviceIntr */ | |
511 | ECR_WRITE(port, ecrval & ~(1<<2)); | |
512 | false_alarm: | |
513 | ret = parport_wait_event(port, HZ); | |
514 | if (ret < 0) | |
515 | break; | |
516 | ret = 0; | |
517 | if (!time_before(jiffies, expire)) { | |
518 | /* Timed out. */ | |
519 | printk(KERN_DEBUG "FIFO write timed out\n"); | |
520 | break; | |
521 | } | |
522 | ecrval = inb(ECONTROL(port)); | |
523 | if (!(ecrval & (1<<2))) { | |
524 | if (need_resched() && | |
525 | time_before(jiffies, expire)) | |
526 | schedule(); | |
527 | ||
528 | goto false_alarm; | |
529 | } | |
530 | ||
531 | continue; | |
532 | } | |
533 | ||
534 | /* Can't fail now. */ | |
535 | expire = jiffies + port->cad->timeout; | |
536 | ||
537 | poll: | |
538 | if (signal_pending(current)) | |
539 | break; | |
540 | ||
541 | if (ecrval & 0x01) { | |
542 | /* FIFO is empty. Blast it full. */ | |
543 | const int n = left < fifo_depth ? left : fifo_depth; | |
544 | outsb(fifo, bufp, n); | |
545 | bufp += n; | |
546 | left -= n; | |
547 | ||
548 | /* Adjust the poll time. */ | |
549 | if (i < (poll_for - 2)) | |
550 | poll_for--; | |
551 | continue; | |
552 | } else if (i++ < poll_for) { | |
553 | udelay(10); | |
554 | ecrval = inb(ECONTROL(port)); | |
555 | goto poll; | |
556 | } | |
557 | ||
558 | /* Half-full(call me an optimist) */ | |
559 | byte = *bufp++; | |
560 | outb(byte, fifo); | |
561 | left--; | |
562 | } | |
563 | dump_parport_state("leave fifo_write_block_pio", port); | |
564 | return length - left; | |
565 | } | |
566 | ||
567 | #ifdef HAS_DMA | |
568 | static size_t parport_pc_fifo_write_block_dma(struct parport *port, | |
569 | const void *buf, size_t length) | |
570 | { | |
571 | int ret = 0; | |
572 | unsigned long dmaflag; | |
573 | size_t left = length; | |
574 | const struct parport_pc_private *priv = port->physport->private_data; | |
575 | struct device *dev = port->physport->dev; | |
576 | dma_addr_t dma_addr, dma_handle; | |
577 | size_t maxlen = 0x10000; /* max 64k per DMA transfer */ | |
578 | unsigned long start = (unsigned long) buf; | |
579 | unsigned long end = (unsigned long) buf + length - 1; | |
580 | ||
581 | dump_parport_state("enter fifo_write_block_dma", port); | |
582 | if (end < MAX_DMA_ADDRESS) { | |
583 | /* If it would cross a 64k boundary, cap it at the end. */ | |
584 | if ((start ^ end) & ~0xffffUL) | |
585 | maxlen = 0x10000 - (start & 0xffff); | |
586 | ||
587 | dma_addr = dma_handle = dma_map_single(dev, (void *)buf, length, | |
588 | DMA_TO_DEVICE); | |
589 | } else { | |
590 | /* above 16 MB we use a bounce buffer as ISA-DMA | |
591 | is not possible */ | |
592 | maxlen = PAGE_SIZE; /* sizeof(priv->dma_buf) */ | |
593 | dma_addr = priv->dma_handle; | |
594 | dma_handle = 0; | |
595 | } | |
596 | ||
597 | port = port->physport; | |
598 | ||
599 | /* We don't want to be interrupted every character. */ | |
600 | parport_pc_disable_irq(port); | |
601 | /* set nErrIntrEn and serviceIntr */ | |
602 | frob_econtrol(port, (1<<4) | (1<<2), (1<<4) | (1<<2)); | |
603 | ||
604 | /* Forward mode. */ | |
605 | parport_pc_data_forward(port); /* Must be in PS2 mode */ | |
606 | ||
607 | while (left) { | |
608 | unsigned long expire = jiffies + port->physport->cad->timeout; | |
609 | ||
610 | size_t count = left; | |
611 | ||
612 | if (count > maxlen) | |
613 | count = maxlen; | |
614 | ||
615 | if (!dma_handle) /* bounce buffer ! */ | |
616 | memcpy(priv->dma_buf, buf, count); | |
617 | ||
618 | dmaflag = claim_dma_lock(); | |
619 | disable_dma(port->dma); | |
620 | clear_dma_ff(port->dma); | |
621 | set_dma_mode(port->dma, DMA_MODE_WRITE); | |
622 | set_dma_addr(port->dma, dma_addr); | |
623 | set_dma_count(port->dma, count); | |
624 | ||
625 | /* Set DMA mode */ | |
626 | frob_econtrol(port, 1<<3, 1<<3); | |
627 | ||
628 | /* Clear serviceIntr */ | |
629 | frob_econtrol(port, 1<<2, 0); | |
630 | ||
631 | enable_dma(port->dma); | |
632 | release_dma_lock(dmaflag); | |
633 | ||
634 | /* assume DMA will be successful */ | |
635 | left -= count; | |
636 | buf += count; | |
637 | if (dma_handle) | |
638 | dma_addr += count; | |
639 | ||
640 | /* Wait for interrupt. */ | |
641 | false_alarm: | |
642 | ret = parport_wait_event(port, HZ); | |
643 | if (ret < 0) | |
644 | break; | |
645 | ret = 0; | |
646 | if (!time_before(jiffies, expire)) { | |
647 | /* Timed out. */ | |
648 | printk(KERN_DEBUG "DMA write timed out\n"); | |
649 | break; | |
650 | } | |
651 | /* Is serviceIntr set? */ | |
652 | if (!(inb(ECONTROL(port)) & (1<<2))) { | |
653 | cond_resched(); | |
654 | ||
655 | goto false_alarm; | |
656 | } | |
657 | ||
658 | dmaflag = claim_dma_lock(); | |
659 | disable_dma(port->dma); | |
660 | clear_dma_ff(port->dma); | |
661 | count = get_dma_residue(port->dma); | |
662 | release_dma_lock(dmaflag); | |
663 | ||
664 | cond_resched(); /* Can't yield the port. */ | |
665 | ||
666 | /* Anyone else waiting for the port? */ | |
667 | if (port->waithead) { | |
668 | printk(KERN_DEBUG "Somebody wants the port\n"); | |
669 | break; | |
670 | } | |
671 | ||
672 | /* update for possible DMA residue ! */ | |
673 | buf -= count; | |
674 | left += count; | |
675 | if (dma_handle) | |
676 | dma_addr -= count; | |
677 | } | |
678 | ||
679 | /* Maybe got here through break, so adjust for DMA residue! */ | |
680 | dmaflag = claim_dma_lock(); | |
681 | disable_dma(port->dma); | |
682 | clear_dma_ff(port->dma); | |
683 | left += get_dma_residue(port->dma); | |
684 | release_dma_lock(dmaflag); | |
685 | ||
686 | /* Turn off DMA mode */ | |
687 | frob_econtrol(port, 1<<3, 0); | |
688 | ||
689 | if (dma_handle) | |
690 | dma_unmap_single(dev, dma_handle, length, DMA_TO_DEVICE); | |
691 | ||
692 | dump_parport_state("leave fifo_write_block_dma", port); | |
693 | return length - left; | |
694 | } | |
695 | #endif | |
696 | ||
697 | static inline size_t parport_pc_fifo_write_block(struct parport *port, | |
698 | const void *buf, size_t length) | |
699 | { | |
700 | #ifdef HAS_DMA | |
701 | if (port->dma != PARPORT_DMA_NONE) | |
702 | return parport_pc_fifo_write_block_dma(port, buf, length); | |
703 | #endif | |
704 | return parport_pc_fifo_write_block_pio(port, buf, length); | |
705 | } | |
706 | ||
707 | /* Parallel Port FIFO mode (ECP chipsets) */ | |
708 | static size_t parport_pc_compat_write_block_pio(struct parport *port, | |
709 | const void *buf, size_t length, | |
710 | int flags) | |
711 | { | |
712 | size_t written; | |
713 | int r; | |
714 | unsigned long expire; | |
715 | const struct parport_pc_private *priv = port->physport->private_data; | |
716 | ||
717 | /* Special case: a timeout of zero means we cannot call schedule(). | |
718 | * Also if O_NONBLOCK is set then use the default implementation. */ | |
719 | if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK) | |
720 | return parport_ieee1284_write_compat(port, buf, | |
721 | length, flags); | |
722 | ||
723 | /* Set up parallel port FIFO mode.*/ | |
724 | parport_pc_data_forward(port); /* Must be in PS2 mode */ | |
725 | parport_pc_frob_control(port, PARPORT_CONTROL_STROBE, 0); | |
726 | r = change_mode(port, ECR_PPF); /* Parallel port FIFO */ | |
727 | if (r) | |
728 | printk(KERN_DEBUG "%s: Warning change_mode ECR_PPF failed\n", | |
729 | port->name); | |
730 | ||
731 | port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA; | |
732 | ||
733 | /* Write the data to the FIFO. */ | |
734 | written = parport_pc_fifo_write_block(port, buf, length); | |
735 | ||
736 | /* Finish up. */ | |
737 | /* For some hardware we don't want to touch the mode until | |
738 | * the FIFO is empty, so allow 4 seconds for each position | |
739 | * in the fifo. | |
740 | */ | |
741 | expire = jiffies + (priv->fifo_depth * HZ * 4); | |
742 | do { | |
743 | /* Wait for the FIFO to empty */ | |
744 | r = change_mode(port, ECR_PS2); | |
745 | if (r != -EBUSY) | |
746 | break; | |
747 | } while (time_before(jiffies, expire)); | |
748 | if (r == -EBUSY) { | |
749 | ||
750 | printk(KERN_DEBUG "%s: FIFO is stuck\n", port->name); | |
751 | ||
752 | /* Prevent further data transfer. */ | |
753 | frob_set_mode(port, ECR_TST); | |
754 | ||
755 | /* Adjust for the contents of the FIFO. */ | |
756 | for (written -= priv->fifo_depth; ; written++) { | |
757 | if (inb(ECONTROL(port)) & 0x2) { | |
758 | /* Full up. */ | |
759 | break; | |
760 | } | |
761 | outb(0, FIFO(port)); | |
762 | } | |
763 | ||
764 | /* Reset the FIFO and return to PS2 mode. */ | |
765 | frob_set_mode(port, ECR_PS2); | |
766 | } | |
767 | ||
768 | r = parport_wait_peripheral(port, | |
769 | PARPORT_STATUS_BUSY, | |
770 | PARPORT_STATUS_BUSY); | |
771 | if (r) | |
772 | printk(KERN_DEBUG | |
773 | "%s: BUSY timeout (%d) in compat_write_block_pio\n", | |
774 | port->name, r); | |
775 | ||
776 | port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE; | |
777 | ||
778 | return written; | |
779 | } | |
780 | ||
781 | /* ECP */ | |
782 | #ifdef CONFIG_PARPORT_1284 | |
783 | static size_t parport_pc_ecp_write_block_pio(struct parport *port, | |
784 | const void *buf, size_t length, | |
785 | int flags) | |
786 | { | |
787 | size_t written; | |
788 | int r; | |
789 | unsigned long expire; | |
790 | const struct parport_pc_private *priv = port->physport->private_data; | |
791 | ||
792 | /* Special case: a timeout of zero means we cannot call schedule(). | |
793 | * Also if O_NONBLOCK is set then use the default implementation. */ | |
794 | if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK) | |
795 | return parport_ieee1284_ecp_write_data(port, buf, | |
796 | length, flags); | |
797 | ||
798 | /* Switch to forward mode if necessary. */ | |
799 | if (port->physport->ieee1284.phase != IEEE1284_PH_FWD_IDLE) { | |
800 | /* Event 47: Set nInit high. */ | |
801 | parport_frob_control(port, | |
802 | PARPORT_CONTROL_INIT | |
803 | | PARPORT_CONTROL_AUTOFD, | |
804 | PARPORT_CONTROL_INIT | |
805 | | PARPORT_CONTROL_AUTOFD); | |
806 | ||
807 | /* Event 49: PError goes high. */ | |
808 | r = parport_wait_peripheral(port, | |
809 | PARPORT_STATUS_PAPEROUT, | |
810 | PARPORT_STATUS_PAPEROUT); | |
811 | if (r) { | |
812 | printk(KERN_DEBUG "%s: PError timeout (%d) " | |
813 | "in ecp_write_block_pio\n", port->name, r); | |
814 | } | |
815 | } | |
816 | ||
817 | /* Set up ECP parallel port mode.*/ | |
818 | parport_pc_data_forward(port); /* Must be in PS2 mode */ | |
819 | parport_pc_frob_control(port, | |
820 | PARPORT_CONTROL_STROBE | | |
821 | PARPORT_CONTROL_AUTOFD, | |
822 | 0); | |
823 | r = change_mode(port, ECR_ECP); /* ECP FIFO */ | |
824 | if (r) | |
825 | printk(KERN_DEBUG "%s: Warning change_mode ECR_ECP failed\n", | |
826 | port->name); | |
827 | port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA; | |
828 | ||
829 | /* Write the data to the FIFO. */ | |
830 | written = parport_pc_fifo_write_block(port, buf, length); | |
831 | ||
832 | /* Finish up. */ | |
833 | /* For some hardware we don't want to touch the mode until | |
834 | * the FIFO is empty, so allow 4 seconds for each position | |
835 | * in the fifo. | |
836 | */ | |
837 | expire = jiffies + (priv->fifo_depth * (HZ * 4)); | |
838 | do { | |
839 | /* Wait for the FIFO to empty */ | |
840 | r = change_mode(port, ECR_PS2); | |
841 | if (r != -EBUSY) | |
842 | break; | |
843 | } while (time_before(jiffies, expire)); | |
844 | if (r == -EBUSY) { | |
845 | ||
846 | printk(KERN_DEBUG "%s: FIFO is stuck\n", port->name); | |
847 | ||
848 | /* Prevent further data transfer. */ | |
849 | frob_set_mode(port, ECR_TST); | |
850 | ||
851 | /* Adjust for the contents of the FIFO. */ | |
852 | for (written -= priv->fifo_depth; ; written++) { | |
853 | if (inb(ECONTROL(port)) & 0x2) { | |
854 | /* Full up. */ | |
855 | break; | |
856 | } | |
857 | outb(0, FIFO(port)); | |
858 | } | |
859 | ||
860 | /* Reset the FIFO and return to PS2 mode. */ | |
861 | frob_set_mode(port, ECR_PS2); | |
862 | ||
863 | /* Host transfer recovery. */ | |
864 | parport_pc_data_reverse(port); /* Must be in PS2 mode */ | |
865 | udelay(5); | |
866 | parport_frob_control(port, PARPORT_CONTROL_INIT, 0); | |
867 | r = parport_wait_peripheral(port, PARPORT_STATUS_PAPEROUT, 0); | |
868 | if (r) | |
869 | printk(KERN_DEBUG "%s: PE,1 timeout (%d) " | |
870 | "in ecp_write_block_pio\n", port->name, r); | |
871 | ||
872 | parport_frob_control(port, | |
873 | PARPORT_CONTROL_INIT, | |
874 | PARPORT_CONTROL_INIT); | |
875 | r = parport_wait_peripheral(port, | |
876 | PARPORT_STATUS_PAPEROUT, | |
877 | PARPORT_STATUS_PAPEROUT); | |
878 | if (r) | |
879 | printk(KERN_DEBUG "%s: PE,2 timeout (%d) " | |
880 | "in ecp_write_block_pio\n", port->name, r); | |
881 | } | |
882 | ||
883 | r = parport_wait_peripheral(port, | |
884 | PARPORT_STATUS_BUSY, | |
885 | PARPORT_STATUS_BUSY); | |
886 | if (r) | |
887 | printk(KERN_DEBUG | |
888 | "%s: BUSY timeout (%d) in ecp_write_block_pio\n", | |
889 | port->name, r); | |
890 | ||
891 | port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE; | |
892 | ||
893 | return written; | |
894 | } | |
895 | #endif /* IEEE 1284 support */ | |
896 | #endif /* Allowed to use FIFO/DMA */ | |
897 | ||
898 | ||
899 | /* | |
900 | * ****************************************** | |
901 | * INITIALISATION AND MODULE STUFF BELOW HERE | |
902 | * ****************************************** | |
903 | */ | |
904 | ||
905 | /* GCC is not inlining extern inline function later overwriten to non-inline, | |
906 | so we use outlined_ variants here. */ | |
907 | static const struct parport_operations parport_pc_ops = { | |
908 | .write_data = parport_pc_write_data, | |
909 | .read_data = parport_pc_read_data, | |
910 | ||
911 | .write_control = parport_pc_write_control, | |
912 | .read_control = parport_pc_read_control, | |
913 | .frob_control = parport_pc_frob_control, | |
914 | ||
915 | .read_status = parport_pc_read_status, | |
916 | ||
917 | .enable_irq = parport_pc_enable_irq, | |
918 | .disable_irq = parport_pc_disable_irq, | |
919 | ||
920 | .data_forward = parport_pc_data_forward, | |
921 | .data_reverse = parport_pc_data_reverse, | |
922 | ||
923 | .init_state = parport_pc_init_state, | |
924 | .save_state = parport_pc_save_state, | |
925 | .restore_state = parport_pc_restore_state, | |
926 | ||
927 | .epp_write_data = parport_ieee1284_epp_write_data, | |
928 | .epp_read_data = parport_ieee1284_epp_read_data, | |
929 | .epp_write_addr = parport_ieee1284_epp_write_addr, | |
930 | .epp_read_addr = parport_ieee1284_epp_read_addr, | |
931 | ||
932 | .ecp_write_data = parport_ieee1284_ecp_write_data, | |
933 | .ecp_read_data = parport_ieee1284_ecp_read_data, | |
934 | .ecp_write_addr = parport_ieee1284_ecp_write_addr, | |
935 | ||
936 | .compat_write_data = parport_ieee1284_write_compat, | |
937 | .nibble_read_data = parport_ieee1284_read_nibble, | |
938 | .byte_read_data = parport_ieee1284_read_byte, | |
939 | ||
940 | .owner = THIS_MODULE, | |
941 | }; | |
942 | ||
943 | #ifdef CONFIG_PARPORT_PC_SUPERIO | |
944 | ||
945 | static struct superio_struct *find_free_superio(void) | |
946 | { | |
947 | int i; | |
948 | for (i = 0; i < NR_SUPERIOS; i++) | |
949 | if (superios[i].io == 0) | |
950 | return &superios[i]; | |
951 | return NULL; | |
952 | } | |
953 | ||
954 | ||
955 | /* Super-IO chipset detection, Winbond, SMSC */ | |
956 | static void show_parconfig_smsc37c669(int io, int key) | |
957 | { | |
958 | int cr1, cr4, cra, cr23, cr26, cr27; | |
959 | struct superio_struct *s; | |
960 | ||
961 | static const char *const modes[] = { | |
962 | "SPP and Bidirectional (PS/2)", | |
963 | "EPP and SPP", | |
964 | "ECP", | |
965 | "ECP and EPP" }; | |
966 | ||
967 | outb(key, io); | |
968 | outb(key, io); | |
969 | outb(1, io); | |
970 | cr1 = inb(io + 1); | |
971 | outb(4, io); | |
972 | cr4 = inb(io + 1); | |
973 | outb(0x0a, io); | |
974 | cra = inb(io + 1); | |
975 | outb(0x23, io); | |
976 | cr23 = inb(io + 1); | |
977 | outb(0x26, io); | |
978 | cr26 = inb(io + 1); | |
979 | outb(0x27, io); | |
980 | cr27 = inb(io + 1); | |
981 | outb(0xaa, io); | |
982 | ||
983 | if (verbose_probing) { | |
984 | printk(KERN_INFO | |
985 | "SMSC 37c669 LPT Config: cr_1=0x%02x, 4=0x%02x, " | |
986 | "A=0x%2x, 23=0x%02x, 26=0x%02x, 27=0x%02x\n", | |
987 | cr1, cr4, cra, cr23, cr26, cr27); | |
988 | ||
989 | /* The documentation calls DMA and IRQ-Lines by letters, so | |
990 | the board maker can/will wire them | |
991 | appropriately/randomly... G=reserved H=IDE-irq, */ | |
992 | printk(KERN_INFO | |
993 | "SMSC LPT Config: io=0x%04x, irq=%c, dma=%c, fifo threshold=%d\n", | |
994 | cr23 * 4, | |
995 | (cr27 & 0x0f) ? 'A' - 1 + (cr27 & 0x0f) : '-', | |
996 | (cr26 & 0x0f) ? 'A' - 1 + (cr26 & 0x0f) : '-', | |
997 | cra & 0x0f); | |
998 | printk(KERN_INFO "SMSC LPT Config: enabled=%s power=%s\n", | |
999 | (cr23 * 4 >= 0x100) ? "yes" : "no", | |
1000 | (cr1 & 4) ? "yes" : "no"); | |
1001 | printk(KERN_INFO | |
1002 | "SMSC LPT Config: Port mode=%s, EPP version =%s\n", | |
1003 | (cr1 & 0x08) ? "Standard mode only (SPP)" | |
1004 | : modes[cr4 & 0x03], | |
1005 | (cr4 & 0x40) ? "1.7" : "1.9"); | |
1006 | } | |
1007 | ||
1008 | /* Heuristics ! BIOS setup for this mainboard device limits | |
1009 | the choices to standard settings, i.e. io-address and IRQ | |
1010 | are related, however DMA can be 1 or 3, assume DMA_A=DMA1, | |
1011 | DMA_C=DMA3 (this is true e.g. for TYAN 1564D Tomcat IV) */ | |
1012 | if (cr23 * 4 >= 0x100) { /* if active */ | |
1013 | s = find_free_superio(); | |
1014 | if (s == NULL) | |
1015 | printk(KERN_INFO "Super-IO: too many chips!\n"); | |
1016 | else { | |
1017 | int d; | |
1018 | switch (cr23 * 4) { | |
1019 | case 0x3bc: | |
1020 | s->io = 0x3bc; | |
1021 | s->irq = 7; | |
1022 | break; | |
1023 | case 0x378: | |
1024 | s->io = 0x378; | |
1025 | s->irq = 7; | |
1026 | break; | |
1027 | case 0x278: | |
1028 | s->io = 0x278; | |
1029 | s->irq = 5; | |
1030 | } | |
1031 | d = (cr26 & 0x0f); | |
1032 | if (d == 1 || d == 3) | |
1033 | s->dma = d; | |
1034 | else | |
1035 | s->dma = PARPORT_DMA_NONE; | |
1036 | } | |
1037 | } | |
1038 | } | |
1039 | ||
1040 | ||
1041 | static void show_parconfig_winbond(int io, int key) | |
1042 | { | |
1043 | int cr30, cr60, cr61, cr70, cr74, crf0; | |
1044 | struct superio_struct *s; | |
1045 | static const char *const modes[] = { | |
1046 | "Standard (SPP) and Bidirectional(PS/2)", /* 0 */ | |
1047 | "EPP-1.9 and SPP", | |
1048 | "ECP", | |
1049 | "ECP and EPP-1.9", | |
1050 | "Standard (SPP)", | |
1051 | "EPP-1.7 and SPP", /* 5 */ | |
1052 | "undefined!", | |
1053 | "ECP and EPP-1.7" }; | |
1054 | static char *const irqtypes[] = { | |
1055 | "pulsed low, high-Z", | |
1056 | "follows nACK" }; | |
1057 | ||
1058 | /* The registers are called compatible-PnP because the | |
1059 | register layout is modelled after ISA-PnP, the access | |
1060 | method is just another ... */ | |
1061 | outb(key, io); | |
1062 | outb(key, io); | |
1063 | outb(0x07, io); /* Register 7: Select Logical Device */ | |
1064 | outb(0x01, io + 1); /* LD1 is Parallel Port */ | |
1065 | outb(0x30, io); | |
1066 | cr30 = inb(io + 1); | |
1067 | outb(0x60, io); | |
1068 | cr60 = inb(io + 1); | |
1069 | outb(0x61, io); | |
1070 | cr61 = inb(io + 1); | |
1071 | outb(0x70, io); | |
1072 | cr70 = inb(io + 1); | |
1073 | outb(0x74, io); | |
1074 | cr74 = inb(io + 1); | |
1075 | outb(0xf0, io); | |
1076 | crf0 = inb(io + 1); | |
1077 | outb(0xaa, io); | |
1078 | ||
1079 | if (verbose_probing) { | |
1080 | printk(KERN_INFO | |
1081 | "Winbond LPT Config: cr_30=%02x 60,61=%02x%02x 70=%02x 74=%02x, f0=%02x\n", | |
1082 | cr30, cr60, cr61, cr70, cr74, crf0); | |
1083 | printk(KERN_INFO "Winbond LPT Config: active=%s, io=0x%02x%02x irq=%d, ", | |
1084 | (cr30 & 0x01) ? "yes" : "no", cr60, cr61, cr70 & 0x0f); | |
1085 | if ((cr74 & 0x07) > 3) | |
1086 | printk("dma=none\n"); | |
1087 | else | |
1088 | printk("dma=%d\n", cr74 & 0x07); | |
1089 | printk(KERN_INFO | |
1090 | "Winbond LPT Config: irqtype=%s, ECP fifo threshold=%d\n", | |
1091 | irqtypes[crf0>>7], (crf0>>3)&0x0f); | |
1092 | printk(KERN_INFO "Winbond LPT Config: Port mode=%s\n", | |
1093 | modes[crf0 & 0x07]); | |
1094 | } | |
1095 | ||
1096 | if (cr30 & 0x01) { /* the settings can be interrogated later ... */ | |
1097 | s = find_free_superio(); | |
1098 | if (s == NULL) | |
1099 | printk(KERN_INFO "Super-IO: too many chips!\n"); | |
1100 | else { | |
1101 | s->io = (cr60 << 8) | cr61; | |
1102 | s->irq = cr70 & 0x0f; | |
1103 | s->dma = (((cr74 & 0x07) > 3) ? | |
1104 | PARPORT_DMA_NONE : (cr74 & 0x07)); | |
1105 | } | |
1106 | } | |
1107 | } | |
1108 | ||
1109 | static void decode_winbond(int efer, int key, int devid, int devrev, int oldid) | |
1110 | { | |
1111 | const char *type = "unknown"; | |
1112 | int id, progif = 2; | |
1113 | ||
1114 | if (devid == devrev) | |
1115 | /* simple heuristics, we happened to read some | |
1116 | non-winbond register */ | |
1117 | return; | |
1118 | ||
1119 | id = (devid << 8) | devrev; | |
1120 | ||
1121 | /* Values are from public data sheets pdf files, I can just | |
1122 | confirm 83977TF is correct :-) */ | |
1123 | if (id == 0x9771) | |
1124 | type = "83977F/AF"; | |
1125 | else if (id == 0x9773) | |
1126 | type = "83977TF / SMSC 97w33x/97w34x"; | |
1127 | else if (id == 0x9774) | |
1128 | type = "83977ATF"; | |
1129 | else if ((id & ~0x0f) == 0x5270) | |
1130 | type = "83977CTF / SMSC 97w36x"; | |
1131 | else if ((id & ~0x0f) == 0x52f0) | |
1132 | type = "83977EF / SMSC 97w35x"; | |
1133 | else if ((id & ~0x0f) == 0x5210) | |
1134 | type = "83627"; | |
1135 | else if ((id & ~0x0f) == 0x6010) | |
1136 | type = "83697HF"; | |
1137 | else if ((oldid & 0x0f) == 0x0a) { | |
1138 | type = "83877F"; | |
1139 | progif = 1; | |
1140 | } else if ((oldid & 0x0f) == 0x0b) { | |
1141 | type = "83877AF"; | |
1142 | progif = 1; | |
1143 | } else if ((oldid & 0x0f) == 0x0c) { | |
1144 | type = "83877TF"; | |
1145 | progif = 1; | |
1146 | } else if ((oldid & 0x0f) == 0x0d) { | |
1147 | type = "83877ATF"; | |
1148 | progif = 1; | |
1149 | } else | |
1150 | progif = 0; | |
1151 | ||
1152 | if (verbose_probing) | |
1153 | printk(KERN_INFO "Winbond chip at EFER=0x%x key=0x%02x " | |
1154 | "devid=%02x devrev=%02x oldid=%02x type=%s\n", | |
1155 | efer, key, devid, devrev, oldid, type); | |
1156 | ||
1157 | if (progif == 2) | |
1158 | show_parconfig_winbond(efer, key); | |
1159 | } | |
1160 | ||
1161 | static void decode_smsc(int efer, int key, int devid, int devrev) | |
1162 | { | |
1163 | const char *type = "unknown"; | |
1164 | void (*func)(int io, int key); | |
1165 | int id; | |
1166 | ||
1167 | if (devid == devrev) | |
1168 | /* simple heuristics, we happened to read some | |
1169 | non-smsc register */ | |
1170 | return; | |
1171 | ||
1172 | func = NULL; | |
1173 | id = (devid << 8) | devrev; | |
1174 | ||
1175 | if (id == 0x0302) { | |
1176 | type = "37c669"; | |
1177 | func = show_parconfig_smsc37c669; | |
1178 | } else if (id == 0x6582) | |
1179 | type = "37c665IR"; | |
1180 | else if (devid == 0x65) | |
1181 | type = "37c665GT"; | |
1182 | else if (devid == 0x66) | |
1183 | type = "37c666GT"; | |
1184 | ||
1185 | if (verbose_probing) | |
1186 | printk(KERN_INFO "SMSC chip at EFER=0x%x " | |
1187 | "key=0x%02x devid=%02x devrev=%02x type=%s\n", | |
1188 | efer, key, devid, devrev, type); | |
1189 | ||
1190 | if (func) | |
1191 | func(efer, key); | |
1192 | } | |
1193 | ||
1194 | ||
1195 | static void winbond_check(int io, int key) | |
1196 | { | |
1197 | int origval, devid, devrev, oldid, x_devid, x_devrev, x_oldid; | |
1198 | ||
1199 | if (!request_region(io, 3, __func__)) | |
1200 | return; | |
1201 | ||
1202 | origval = inb(io); /* Save original value */ | |
1203 | ||
1204 | /* First probe without key */ | |
1205 | outb(0x20, io); | |
1206 | x_devid = inb(io + 1); | |
1207 | outb(0x21, io); | |
1208 | x_devrev = inb(io + 1); | |
1209 | outb(0x09, io); | |
1210 | x_oldid = inb(io + 1); | |
1211 | ||
1212 | outb(key, io); | |
1213 | outb(key, io); /* Write Magic Sequence to EFER, extended | |
1214 | function enable register */ | |
1215 | outb(0x20, io); /* Write EFIR, extended function index register */ | |
1216 | devid = inb(io + 1); /* Read EFDR, extended function data register */ | |
1217 | outb(0x21, io); | |
1218 | devrev = inb(io + 1); | |
1219 | outb(0x09, io); | |
1220 | oldid = inb(io + 1); | |
1221 | outb(0xaa, io); /* Magic Seal */ | |
1222 | ||
1223 | outb(origval, io); /* in case we poked some entirely different hardware */ | |
1224 | ||
1225 | if ((x_devid == devid) && (x_devrev == devrev) && (x_oldid == oldid)) | |
1226 | goto out; /* protection against false positives */ | |
1227 | ||
1228 | decode_winbond(io, key, devid, devrev, oldid); | |
1229 | out: | |
1230 | release_region(io, 3); | |
1231 | } | |
1232 | ||
1233 | static void winbond_check2(int io, int key) | |
1234 | { | |
1235 | int origval[3], devid, devrev, oldid, x_devid, x_devrev, x_oldid; | |
1236 | ||
1237 | if (!request_region(io, 3, __func__)) | |
1238 | return; | |
1239 | ||
1240 | origval[0] = inb(io); /* Save original values */ | |
1241 | origval[1] = inb(io + 1); | |
1242 | origval[2] = inb(io + 2); | |
1243 | ||
1244 | /* First probe without the key */ | |
1245 | outb(0x20, io + 2); | |
1246 | x_devid = inb(io + 2); | |
1247 | outb(0x21, io + 1); | |
1248 | x_devrev = inb(io + 2); | |
1249 | outb(0x09, io + 1); | |
1250 | x_oldid = inb(io + 2); | |
1251 | ||
1252 | outb(key, io); /* Write Magic Byte to EFER, extended | |
1253 | function enable register */ | |
1254 | outb(0x20, io + 2); /* Write EFIR, extended function index register */ | |
1255 | devid = inb(io + 2); /* Read EFDR, extended function data register */ | |
1256 | outb(0x21, io + 1); | |
1257 | devrev = inb(io + 2); | |
1258 | outb(0x09, io + 1); | |
1259 | oldid = inb(io + 2); | |
1260 | outb(0xaa, io); /* Magic Seal */ | |
1261 | ||
1262 | outb(origval[0], io); /* in case we poked some entirely different hardware */ | |
1263 | outb(origval[1], io + 1); | |
1264 | outb(origval[2], io + 2); | |
1265 | ||
1266 | if (x_devid == devid && x_devrev == devrev && x_oldid == oldid) | |
1267 | goto out; /* protection against false positives */ | |
1268 | ||
1269 | decode_winbond(io, key, devid, devrev, oldid); | |
1270 | out: | |
1271 | release_region(io, 3); | |
1272 | } | |
1273 | ||
1274 | static void smsc_check(int io, int key) | |
1275 | { | |
1276 | int origval, id, rev, oldid, oldrev, x_id, x_rev, x_oldid, x_oldrev; | |
1277 | ||
1278 | if (!request_region(io, 3, __func__)) | |
1279 | return; | |
1280 | ||
1281 | origval = inb(io); /* Save original value */ | |
1282 | ||
1283 | /* First probe without the key */ | |
1284 | outb(0x0d, io); | |
1285 | x_oldid = inb(io + 1); | |
1286 | outb(0x0e, io); | |
1287 | x_oldrev = inb(io + 1); | |
1288 | outb(0x20, io); | |
1289 | x_id = inb(io + 1); | |
1290 | outb(0x21, io); | |
1291 | x_rev = inb(io + 1); | |
1292 | ||
1293 | outb(key, io); | |
1294 | outb(key, io); /* Write Magic Sequence to EFER, extended | |
1295 | function enable register */ | |
1296 | outb(0x0d, io); /* Write EFIR, extended function index register */ | |
1297 | oldid = inb(io + 1); /* Read EFDR, extended function data register */ | |
1298 | outb(0x0e, io); | |
1299 | oldrev = inb(io + 1); | |
1300 | outb(0x20, io); | |
1301 | id = inb(io + 1); | |
1302 | outb(0x21, io); | |
1303 | rev = inb(io + 1); | |
1304 | outb(0xaa, io); /* Magic Seal */ | |
1305 | ||
1306 | outb(origval, io); /* in case we poked some entirely different hardware */ | |
1307 | ||
1308 | if (x_id == id && x_oldrev == oldrev && | |
1309 | x_oldid == oldid && x_rev == rev) | |
1310 | goto out; /* protection against false positives */ | |
1311 | ||
1312 | decode_smsc(io, key, oldid, oldrev); | |
1313 | out: | |
1314 | release_region(io, 3); | |
1315 | } | |
1316 | ||
1317 | ||
1318 | static void detect_and_report_winbond(void) | |
1319 | { | |
1320 | if (verbose_probing) | |
1321 | printk(KERN_DEBUG "Winbond Super-IO detection, now testing ports 3F0,370,250,4E,2E ...\n"); | |
1322 | winbond_check(0x3f0, 0x87); | |
1323 | winbond_check(0x370, 0x87); | |
1324 | winbond_check(0x2e , 0x87); | |
1325 | winbond_check(0x4e , 0x87); | |
1326 | winbond_check(0x3f0, 0x86); | |
1327 | winbond_check2(0x250, 0x88); | |
1328 | winbond_check2(0x250, 0x89); | |
1329 | } | |
1330 | ||
1331 | static void detect_and_report_smsc(void) | |
1332 | { | |
1333 | if (verbose_probing) | |
1334 | printk(KERN_DEBUG "SMSC Super-IO detection, now testing Ports 2F0, 370 ...\n"); | |
1335 | smsc_check(0x3f0, 0x55); | |
1336 | smsc_check(0x370, 0x55); | |
1337 | smsc_check(0x3f0, 0x44); | |
1338 | smsc_check(0x370, 0x44); | |
1339 | } | |
1340 | ||
1341 | static void detect_and_report_it87(void) | |
1342 | { | |
1343 | u16 dev; | |
1344 | u8 origval, r; | |
1345 | if (verbose_probing) | |
1346 | printk(KERN_DEBUG "IT8705 Super-IO detection, now testing port 2E ...\n"); | |
1347 | if (!request_muxed_region(0x2e, 2, __func__)) | |
1348 | return; | |
1349 | origval = inb(0x2e); /* Save original value */ | |
1350 | outb(0x87, 0x2e); | |
1351 | outb(0x01, 0x2e); | |
1352 | outb(0x55, 0x2e); | |
1353 | outb(0x55, 0x2e); | |
1354 | outb(0x20, 0x2e); | |
1355 | dev = inb(0x2f) << 8; | |
1356 | outb(0x21, 0x2e); | |
1357 | dev |= inb(0x2f); | |
1358 | if (dev == 0x8712 || dev == 0x8705 || dev == 0x8715 || | |
1359 | dev == 0x8716 || dev == 0x8718 || dev == 0x8726) { | |
1360 | printk(KERN_INFO "IT%04X SuperIO detected.\n", dev); | |
1361 | outb(0x07, 0x2E); /* Parallel Port */ | |
1362 | outb(0x03, 0x2F); | |
1363 | outb(0xF0, 0x2E); /* BOOT 0x80 off */ | |
1364 | r = inb(0x2f); | |
1365 | outb(0xF0, 0x2E); | |
1366 | outb(r | 8, 0x2F); | |
1367 | outb(0x02, 0x2E); /* Lock */ | |
1368 | outb(0x02, 0x2F); | |
1369 | } else { | |
1370 | outb(origval, 0x2e); /* Oops, sorry to disturb */ | |
1371 | } | |
1372 | release_region(0x2e, 2); | |
1373 | } | |
1374 | #endif /* CONFIG_PARPORT_PC_SUPERIO */ | |
1375 | ||
1376 | static struct superio_struct *find_superio(struct parport *p) | |
1377 | { | |
1378 | int i; | |
1379 | for (i = 0; i < NR_SUPERIOS; i++) | |
1380 | if (superios[i].io != p->base) | |
1381 | return &superios[i]; | |
1382 | return NULL; | |
1383 | } | |
1384 | ||
1385 | static int get_superio_dma(struct parport *p) | |
1386 | { | |
1387 | struct superio_struct *s = find_superio(p); | |
1388 | if (s) | |
1389 | return s->dma; | |
1390 | return PARPORT_DMA_NONE; | |
1391 | } | |
1392 | ||
1393 | static int get_superio_irq(struct parport *p) | |
1394 | { | |
1395 | struct superio_struct *s = find_superio(p); | |
1396 | if (s) | |
1397 | return s->irq; | |
1398 | return PARPORT_IRQ_NONE; | |
1399 | } | |
1400 | ||
1401 | ||
1402 | /* --- Mode detection ------------------------------------- */ | |
1403 | ||
1404 | /* | |
1405 | * Checks for port existence, all ports support SPP MODE | |
1406 | * Returns: | |
1407 | * 0 : No parallel port at this address | |
1408 | * PARPORT_MODE_PCSPP : SPP port detected | |
1409 | * (if the user specified an ioport himself, | |
1410 | * this shall always be the case!) | |
1411 | * | |
1412 | */ | |
1413 | static int parport_SPP_supported(struct parport *pb) | |
1414 | { | |
1415 | unsigned char r, w; | |
1416 | ||
1417 | /* | |
1418 | * first clear an eventually pending EPP timeout | |
1419 | * I (sailer@ife.ee.ethz.ch) have an SMSC chipset | |
1420 | * that does not even respond to SPP cycles if an EPP | |
1421 | * timeout is pending | |
1422 | */ | |
1423 | clear_epp_timeout(pb); | |
1424 | ||
1425 | /* Do a simple read-write test to make sure the port exists. */ | |
1426 | w = 0xc; | |
1427 | outb(w, CONTROL(pb)); | |
1428 | ||
1429 | /* Is there a control register that we can read from? Some | |
1430 | * ports don't allow reads, so read_control just returns a | |
1431 | * software copy. Some ports _do_ allow reads, so bypass the | |
1432 | * software copy here. In addition, some bits aren't | |
1433 | * writable. */ | |
1434 | r = inb(CONTROL(pb)); | |
1435 | if ((r & 0xf) == w) { | |
1436 | w = 0xe; | |
1437 | outb(w, CONTROL(pb)); | |
1438 | r = inb(CONTROL(pb)); | |
1439 | outb(0xc, CONTROL(pb)); | |
1440 | if ((r & 0xf) == w) | |
1441 | return PARPORT_MODE_PCSPP; | |
1442 | } | |
1443 | ||
1444 | if (user_specified) | |
1445 | /* That didn't work, but the user thinks there's a | |
1446 | * port here. */ | |
1447 | printk(KERN_INFO "parport 0x%lx (WARNING): CTR: " | |
1448 | "wrote 0x%02x, read 0x%02x\n", pb->base, w, r); | |
1449 | ||
1450 | /* Try the data register. The data lines aren't tri-stated at | |
1451 | * this stage, so we expect back what we wrote. */ | |
1452 | w = 0xaa; | |
1453 | parport_pc_write_data(pb, w); | |
1454 | r = parport_pc_read_data(pb); | |
1455 | if (r == w) { | |
1456 | w = 0x55; | |
1457 | parport_pc_write_data(pb, w); | |
1458 | r = parport_pc_read_data(pb); | |
1459 | if (r == w) | |
1460 | return PARPORT_MODE_PCSPP; | |
1461 | } | |
1462 | ||
1463 | if (user_specified) { | |
1464 | /* Didn't work, but the user is convinced this is the | |
1465 | * place. */ | |
1466 | printk(KERN_INFO "parport 0x%lx (WARNING): DATA: " | |
1467 | "wrote 0x%02x, read 0x%02x\n", pb->base, w, r); | |
1468 | printk(KERN_INFO "parport 0x%lx: You gave this address, " | |
1469 | "but there is probably no parallel port there!\n", | |
1470 | pb->base); | |
1471 | } | |
1472 | ||
1473 | /* It's possible that we can't read the control register or | |
1474 | * the data register. In that case just believe the user. */ | |
1475 | if (user_specified) | |
1476 | return PARPORT_MODE_PCSPP; | |
1477 | ||
1478 | return 0; | |
1479 | } | |
1480 | ||
1481 | /* Check for ECR | |
1482 | * | |
1483 | * Old style XT ports alias io ports every 0x400, hence accessing ECR | |
1484 | * on these cards actually accesses the CTR. | |
1485 | * | |
1486 | * Modern cards don't do this but reading from ECR will return 0xff | |
1487 | * regardless of what is written here if the card does NOT support | |
1488 | * ECP. | |
1489 | * | |
1490 | * We first check to see if ECR is the same as CTR. If not, the low | |
1491 | * two bits of ECR aren't writable, so we check by writing ECR and | |
1492 | * reading it back to see if it's what we expect. | |
1493 | */ | |
1494 | static int parport_ECR_present(struct parport *pb) | |
1495 | { | |
1496 | struct parport_pc_private *priv = pb->private_data; | |
1497 | unsigned char r = 0xc; | |
1498 | ||
1499 | outb(r, CONTROL(pb)); | |
1500 | if ((inb(ECONTROL(pb)) & 0x3) == (r & 0x3)) { | |
1501 | outb(r ^ 0x2, CONTROL(pb)); /* Toggle bit 1 */ | |
1502 | ||
1503 | r = inb(CONTROL(pb)); | |
1504 | if ((inb(ECONTROL(pb)) & 0x2) == (r & 0x2)) | |
1505 | goto no_reg; /* Sure that no ECR register exists */ | |
1506 | } | |
1507 | ||
1508 | if ((inb(ECONTROL(pb)) & 0x3) != 0x1) | |
1509 | goto no_reg; | |
1510 | ||
1511 | ECR_WRITE(pb, 0x34); | |
1512 | if (inb(ECONTROL(pb)) != 0x35) | |
1513 | goto no_reg; | |
1514 | ||
1515 | priv->ecr = 1; | |
1516 | outb(0xc, CONTROL(pb)); | |
1517 | ||
1518 | /* Go to mode 000 */ | |
1519 | frob_set_mode(pb, ECR_SPP); | |
1520 | ||
1521 | return 1; | |
1522 | ||
1523 | no_reg: | |
1524 | outb(0xc, CONTROL(pb)); | |
1525 | return 0; | |
1526 | } | |
1527 | ||
1528 | #ifdef CONFIG_PARPORT_1284 | |
1529 | /* Detect PS/2 support. | |
1530 | * | |
1531 | * Bit 5 (0x20) sets the PS/2 data direction; setting this high | |
1532 | * allows us to read data from the data lines. In theory we would get back | |
1533 | * 0xff but any peripheral attached to the port may drag some or all of the | |
1534 | * lines down to zero. So if we get back anything that isn't the contents | |
1535 | * of the data register we deem PS/2 support to be present. | |
1536 | * | |
1537 | * Some SPP ports have "half PS/2" ability - you can't turn off the line | |
1538 | * drivers, but an external peripheral with sufficiently beefy drivers of | |
1539 | * its own can overpower them and assert its own levels onto the bus, from | |
1540 | * where they can then be read back as normal. Ports with this property | |
1541 | * and the right type of device attached are likely to fail the SPP test, | |
1542 | * (as they will appear to have stuck bits) and so the fact that they might | |
1543 | * be misdetected here is rather academic. | |
1544 | */ | |
1545 | ||
1546 | static int parport_PS2_supported(struct parport *pb) | |
1547 | { | |
1548 | int ok = 0; | |
1549 | ||
1550 | clear_epp_timeout(pb); | |
1551 | ||
1552 | /* try to tri-state the buffer */ | |
1553 | parport_pc_data_reverse(pb); | |
1554 | ||
1555 | parport_pc_write_data(pb, 0x55); | |
1556 | if (parport_pc_read_data(pb) != 0x55) | |
1557 | ok++; | |
1558 | ||
1559 | parport_pc_write_data(pb, 0xaa); | |
1560 | if (parport_pc_read_data(pb) != 0xaa) | |
1561 | ok++; | |
1562 | ||
1563 | /* cancel input mode */ | |
1564 | parport_pc_data_forward(pb); | |
1565 | ||
1566 | if (ok) { | |
1567 | pb->modes |= PARPORT_MODE_TRISTATE; | |
1568 | } else { | |
1569 | struct parport_pc_private *priv = pb->private_data; | |
1570 | priv->ctr_writable &= ~0x20; | |
1571 | } | |
1572 | ||
1573 | return ok; | |
1574 | } | |
1575 | ||
1576 | #ifdef CONFIG_PARPORT_PC_FIFO | |
1577 | static int parport_ECP_supported(struct parport *pb) | |
1578 | { | |
1579 | int i; | |
1580 | int config, configb; | |
1581 | int pword; | |
1582 | struct parport_pc_private *priv = pb->private_data; | |
1583 | /* Translate ECP intrLine to ISA irq value */ | |
1584 | static const int intrline[] = { 0, 7, 9, 10, 11, 14, 15, 5 }; | |
1585 | ||
1586 | /* If there is no ECR, we have no hope of supporting ECP. */ | |
1587 | if (!priv->ecr) | |
1588 | return 0; | |
1589 | ||
1590 | /* Find out FIFO depth */ | |
1591 | ECR_WRITE(pb, ECR_SPP << 5); /* Reset FIFO */ | |
1592 | ECR_WRITE(pb, ECR_TST << 5); /* TEST FIFO */ | |
1593 | for (i = 0; i < 1024 && !(inb(ECONTROL(pb)) & 0x02); i++) | |
1594 | outb(0xaa, FIFO(pb)); | |
1595 | ||
1596 | /* | |
1597 | * Using LGS chipset it uses ECR register, but | |
1598 | * it doesn't support ECP or FIFO MODE | |
1599 | */ | |
1600 | if (i == 1024) { | |
1601 | ECR_WRITE(pb, ECR_SPP << 5); | |
1602 | return 0; | |
1603 | } | |
1604 | ||
1605 | priv->fifo_depth = i; | |
1606 | if (verbose_probing) | |
1607 | printk(KERN_DEBUG "0x%lx: FIFO is %d bytes\n", pb->base, i); | |
1608 | ||
1609 | /* Find out writeIntrThreshold */ | |
1610 | frob_econtrol(pb, 1<<2, 1<<2); | |
1611 | frob_econtrol(pb, 1<<2, 0); | |
1612 | for (i = 1; i <= priv->fifo_depth; i++) { | |
1613 | inb(FIFO(pb)); | |
1614 | udelay(50); | |
1615 | if (inb(ECONTROL(pb)) & (1<<2)) | |
1616 | break; | |
1617 | } | |
1618 | ||
1619 | if (i <= priv->fifo_depth) { | |
1620 | if (verbose_probing) | |
1621 | printk(KERN_DEBUG "0x%lx: writeIntrThreshold is %d\n", | |
1622 | pb->base, i); | |
1623 | } else | |
1624 | /* Number of bytes we know we can write if we get an | |
1625 | interrupt. */ | |
1626 | i = 0; | |
1627 | ||
1628 | priv->writeIntrThreshold = i; | |
1629 | ||
1630 | /* Find out readIntrThreshold */ | |
1631 | frob_set_mode(pb, ECR_PS2); /* Reset FIFO and enable PS2 */ | |
1632 | parport_pc_data_reverse(pb); /* Must be in PS2 mode */ | |
1633 | frob_set_mode(pb, ECR_TST); /* Test FIFO */ | |
1634 | frob_econtrol(pb, 1<<2, 1<<2); | |
1635 | frob_econtrol(pb, 1<<2, 0); | |
1636 | for (i = 1; i <= priv->fifo_depth; i++) { | |
1637 | outb(0xaa, FIFO(pb)); | |
1638 | if (inb(ECONTROL(pb)) & (1<<2)) | |
1639 | break; | |
1640 | } | |
1641 | ||
1642 | if (i <= priv->fifo_depth) { | |
1643 | if (verbose_probing) | |
1644 | printk(KERN_INFO "0x%lx: readIntrThreshold is %d\n", | |
1645 | pb->base, i); | |
1646 | } else | |
1647 | /* Number of bytes we can read if we get an interrupt. */ | |
1648 | i = 0; | |
1649 | ||
1650 | priv->readIntrThreshold = i; | |
1651 | ||
1652 | ECR_WRITE(pb, ECR_SPP << 5); /* Reset FIFO */ | |
1653 | ECR_WRITE(pb, 0xf4); /* Configuration mode */ | |
1654 | config = inb(CONFIGA(pb)); | |
1655 | pword = (config >> 4) & 0x7; | |
1656 | switch (pword) { | |
1657 | case 0: | |
1658 | pword = 2; | |
1659 | printk(KERN_WARNING "0x%lx: Unsupported pword size!\n", | |
1660 | pb->base); | |
1661 | break; | |
1662 | case 2: | |
1663 | pword = 4; | |
1664 | printk(KERN_WARNING "0x%lx: Unsupported pword size!\n", | |
1665 | pb->base); | |
1666 | break; | |
1667 | default: | |
1668 | printk(KERN_WARNING "0x%lx: Unknown implementation ID\n", | |
1669 | pb->base); | |
1670 | /* Assume 1 */ | |
1671 | case 1: | |
1672 | pword = 1; | |
1673 | } | |
1674 | priv->pword = pword; | |
1675 | ||
1676 | if (verbose_probing) { | |
1677 | printk(KERN_DEBUG "0x%lx: PWord is %d bits\n", | |
1678 | pb->base, 8 * pword); | |
1679 | ||
1680 | printk(KERN_DEBUG "0x%lx: Interrupts are ISA-%s\n", pb->base, | |
1681 | config & 0x80 ? "Level" : "Pulses"); | |
1682 | ||
1683 | configb = inb(CONFIGB(pb)); | |
1684 | printk(KERN_DEBUG "0x%lx: ECP port cfgA=0x%02x cfgB=0x%02x\n", | |
1685 | pb->base, config, configb); | |
1686 | printk(KERN_DEBUG "0x%lx: ECP settings irq=", pb->base); | |
1687 | if ((configb >> 3) & 0x07) | |
1688 | printk("%d", intrline[(configb >> 3) & 0x07]); | |
1689 | else | |
1690 | printk("<none or set by other means>"); | |
1691 | printk(" dma="); | |
1692 | if ((configb & 0x03) == 0x00) | |
1693 | printk("<none or set by other means>\n"); | |
1694 | else | |
1695 | printk("%d\n", configb & 0x07); | |
1696 | } | |
1697 | ||
1698 | /* Go back to mode 000 */ | |
1699 | frob_set_mode(pb, ECR_SPP); | |
1700 | ||
1701 | return 1; | |
1702 | } | |
1703 | #endif | |
1704 | ||
1705 | static int parport_ECPPS2_supported(struct parport *pb) | |
1706 | { | |
1707 | const struct parport_pc_private *priv = pb->private_data; | |
1708 | int result; | |
1709 | unsigned char oecr; | |
1710 | ||
1711 | if (!priv->ecr) | |
1712 | return 0; | |
1713 | ||
1714 | oecr = inb(ECONTROL(pb)); | |
1715 | ECR_WRITE(pb, ECR_PS2 << 5); | |
1716 | result = parport_PS2_supported(pb); | |
1717 | ECR_WRITE(pb, oecr); | |
1718 | return result; | |
1719 | } | |
1720 | ||
1721 | /* EPP mode detection */ | |
1722 | ||
1723 | static int parport_EPP_supported(struct parport *pb) | |
1724 | { | |
1725 | const struct parport_pc_private *priv = pb->private_data; | |
1726 | ||
1727 | /* | |
1728 | * Theory: | |
1729 | * Bit 0 of STR is the EPP timeout bit, this bit is 0 | |
1730 | * when EPP is possible and is set high when an EPP timeout | |
1731 | * occurs (EPP uses the HALT line to stop the CPU while it does | |
1732 | * the byte transfer, an EPP timeout occurs if the attached | |
1733 | * device fails to respond after 10 micro seconds). | |
1734 | * | |
1735 | * This bit is cleared by either reading it (National Semi) | |
1736 | * or writing a 1 to the bit (SMC, UMC, WinBond), others ??? | |
1737 | * This bit is always high in non EPP modes. | |
1738 | */ | |
1739 | ||
1740 | /* If EPP timeout bit clear then EPP available */ | |
1741 | if (!clear_epp_timeout(pb)) | |
1742 | return 0; /* No way to clear timeout */ | |
1743 | ||
1744 | /* Check for Intel bug. */ | |
1745 | if (priv->ecr) { | |
1746 | unsigned char i; | |
1747 | for (i = 0x00; i < 0x80; i += 0x20) { | |
1748 | ECR_WRITE(pb, i); | |
1749 | if (clear_epp_timeout(pb)) { | |
1750 | /* Phony EPP in ECP. */ | |
1751 | return 0; | |
1752 | } | |
1753 | } | |
1754 | } | |
1755 | ||
1756 | pb->modes |= PARPORT_MODE_EPP; | |
1757 | ||
1758 | /* Set up access functions to use EPP hardware. */ | |
1759 | pb->ops->epp_read_data = parport_pc_epp_read_data; | |
1760 | pb->ops->epp_write_data = parport_pc_epp_write_data; | |
1761 | pb->ops->epp_read_addr = parport_pc_epp_read_addr; | |
1762 | pb->ops->epp_write_addr = parport_pc_epp_write_addr; | |
1763 | ||
1764 | return 1; | |
1765 | } | |
1766 | ||
1767 | static int parport_ECPEPP_supported(struct parport *pb) | |
1768 | { | |
1769 | struct parport_pc_private *priv = pb->private_data; | |
1770 | int result; | |
1771 | unsigned char oecr; | |
1772 | ||
1773 | if (!priv->ecr) | |
1774 | return 0; | |
1775 | ||
1776 | oecr = inb(ECONTROL(pb)); | |
1777 | /* Search for SMC style EPP+ECP mode */ | |
1778 | ECR_WRITE(pb, 0x80); | |
1779 | outb(0x04, CONTROL(pb)); | |
1780 | result = parport_EPP_supported(pb); | |
1781 | ||
1782 | ECR_WRITE(pb, oecr); | |
1783 | ||
1784 | if (result) { | |
1785 | /* Set up access functions to use ECP+EPP hardware. */ | |
1786 | pb->ops->epp_read_data = parport_pc_ecpepp_read_data; | |
1787 | pb->ops->epp_write_data = parport_pc_ecpepp_write_data; | |
1788 | pb->ops->epp_read_addr = parport_pc_ecpepp_read_addr; | |
1789 | pb->ops->epp_write_addr = parport_pc_ecpepp_write_addr; | |
1790 | } | |
1791 | ||
1792 | return result; | |
1793 | } | |
1794 | ||
1795 | #else /* No IEEE 1284 support */ | |
1796 | ||
1797 | /* Don't bother probing for modes we know we won't use. */ | |
1798 | static int parport_PS2_supported(struct parport *pb) { return 0; } | |
1799 | #ifdef CONFIG_PARPORT_PC_FIFO | |
1800 | static int parport_ECP_supported(struct parport *pb) | |
1801 | { | |
1802 | return 0; | |
1803 | } | |
1804 | #endif | |
1805 | static int parport_EPP_supported(struct parport *pb) | |
1806 | { | |
1807 | return 0; | |
1808 | } | |
1809 | ||
1810 | static int parport_ECPEPP_supported(struct parport *pb) | |
1811 | { | |
1812 | return 0; | |
1813 | } | |
1814 | ||
1815 | static int parport_ECPPS2_supported(struct parport *pb) | |
1816 | { | |
1817 | return 0; | |
1818 | } | |
1819 | ||
1820 | #endif /* No IEEE 1284 support */ | |
1821 | ||
1822 | /* --- IRQ detection -------------------------------------- */ | |
1823 | ||
1824 | /* Only if supports ECP mode */ | |
1825 | static int programmable_irq_support(struct parport *pb) | |
1826 | { | |
1827 | int irq, intrLine; | |
1828 | unsigned char oecr = inb(ECONTROL(pb)); | |
1829 | static const int lookup[8] = { | |
1830 | PARPORT_IRQ_NONE, 7, 9, 10, 11, 14, 15, 5 | |
1831 | }; | |
1832 | ||
1833 | ECR_WRITE(pb, ECR_CNF << 5); /* Configuration MODE */ | |
1834 | ||
1835 | intrLine = (inb(CONFIGB(pb)) >> 3) & 0x07; | |
1836 | irq = lookup[intrLine]; | |
1837 | ||
1838 | ECR_WRITE(pb, oecr); | |
1839 | return irq; | |
1840 | } | |
1841 | ||
1842 | static int irq_probe_ECP(struct parport *pb) | |
1843 | { | |
1844 | int i; | |
1845 | unsigned long irqs; | |
1846 | ||
1847 | irqs = probe_irq_on(); | |
1848 | ||
1849 | ECR_WRITE(pb, ECR_SPP << 5); /* Reset FIFO */ | |
1850 | ECR_WRITE(pb, (ECR_TST << 5) | 0x04); | |
1851 | ECR_WRITE(pb, ECR_TST << 5); | |
1852 | ||
1853 | /* If Full FIFO sure that writeIntrThreshold is generated */ | |
1854 | for (i = 0; i < 1024 && !(inb(ECONTROL(pb)) & 0x02) ; i++) | |
1855 | outb(0xaa, FIFO(pb)); | |
1856 | ||
1857 | pb->irq = probe_irq_off(irqs); | |
1858 | ECR_WRITE(pb, ECR_SPP << 5); | |
1859 | ||
1860 | if (pb->irq <= 0) | |
1861 | pb->irq = PARPORT_IRQ_NONE; | |
1862 | ||
1863 | return pb->irq; | |
1864 | } | |
1865 | ||
1866 | /* | |
1867 | * This detection seems that only works in National Semiconductors | |
1868 | * This doesn't work in SMC, LGS, and Winbond | |
1869 | */ | |
1870 | static int irq_probe_EPP(struct parport *pb) | |
1871 | { | |
1872 | #ifndef ADVANCED_DETECT | |
1873 | return PARPORT_IRQ_NONE; | |
1874 | #else | |
1875 | int irqs; | |
1876 | unsigned char oecr; | |
1877 | ||
1878 | if (pb->modes & PARPORT_MODE_PCECR) | |
1879 | oecr = inb(ECONTROL(pb)); | |
1880 | ||
1881 | irqs = probe_irq_on(); | |
1882 | ||
1883 | if (pb->modes & PARPORT_MODE_PCECR) | |
1884 | frob_econtrol(pb, 0x10, 0x10); | |
1885 | ||
1886 | clear_epp_timeout(pb); | |
1887 | parport_pc_frob_control(pb, 0x20, 0x20); | |
1888 | parport_pc_frob_control(pb, 0x10, 0x10); | |
1889 | clear_epp_timeout(pb); | |
1890 | ||
1891 | /* Device isn't expecting an EPP read | |
1892 | * and generates an IRQ. | |
1893 | */ | |
1894 | parport_pc_read_epp(pb); | |
1895 | udelay(20); | |
1896 | ||
1897 | pb->irq = probe_irq_off(irqs); | |
1898 | if (pb->modes & PARPORT_MODE_PCECR) | |
1899 | ECR_WRITE(pb, oecr); | |
1900 | parport_pc_write_control(pb, 0xc); | |
1901 | ||
1902 | if (pb->irq <= 0) | |
1903 | pb->irq = PARPORT_IRQ_NONE; | |
1904 | ||
1905 | return pb->irq; | |
1906 | #endif /* Advanced detection */ | |
1907 | } | |
1908 | ||
1909 | static int irq_probe_SPP(struct parport *pb) | |
1910 | { | |
1911 | /* Don't even try to do this. */ | |
1912 | return PARPORT_IRQ_NONE; | |
1913 | } | |
1914 | ||
1915 | /* We will attempt to share interrupt requests since other devices | |
1916 | * such as sound cards and network cards seem to like using the | |
1917 | * printer IRQs. | |
1918 | * | |
1919 | * When ECP is available we can autoprobe for IRQs. | |
1920 | * NOTE: If we can autoprobe it, we can register the IRQ. | |
1921 | */ | |
1922 | static int parport_irq_probe(struct parport *pb) | |
1923 | { | |
1924 | struct parport_pc_private *priv = pb->private_data; | |
1925 | ||
1926 | if (priv->ecr) { | |
1927 | pb->irq = programmable_irq_support(pb); | |
1928 | ||
1929 | if (pb->irq == PARPORT_IRQ_NONE) | |
1930 | pb->irq = irq_probe_ECP(pb); | |
1931 | } | |
1932 | ||
1933 | if ((pb->irq == PARPORT_IRQ_NONE) && priv->ecr && | |
1934 | (pb->modes & PARPORT_MODE_EPP)) | |
1935 | pb->irq = irq_probe_EPP(pb); | |
1936 | ||
1937 | clear_epp_timeout(pb); | |
1938 | ||
1939 | if (pb->irq == PARPORT_IRQ_NONE && (pb->modes & PARPORT_MODE_EPP)) | |
1940 | pb->irq = irq_probe_EPP(pb); | |
1941 | ||
1942 | clear_epp_timeout(pb); | |
1943 | ||
1944 | if (pb->irq == PARPORT_IRQ_NONE) | |
1945 | pb->irq = irq_probe_SPP(pb); | |
1946 | ||
1947 | if (pb->irq == PARPORT_IRQ_NONE) | |
1948 | pb->irq = get_superio_irq(pb); | |
1949 | ||
1950 | return pb->irq; | |
1951 | } | |
1952 | ||
1953 | /* --- DMA detection -------------------------------------- */ | |
1954 | ||
1955 | /* Only if chipset conforms to ECP ISA Interface Standard */ | |
1956 | static int programmable_dma_support(struct parport *p) | |
1957 | { | |
1958 | unsigned char oecr = inb(ECONTROL(p)); | |
1959 | int dma; | |
1960 | ||
1961 | frob_set_mode(p, ECR_CNF); | |
1962 | ||
1963 | dma = inb(CONFIGB(p)) & 0x07; | |
1964 | /* 000: Indicates jumpered 8-bit DMA if read-only. | |
1965 | 100: Indicates jumpered 16-bit DMA if read-only. */ | |
1966 | if ((dma & 0x03) == 0) | |
1967 | dma = PARPORT_DMA_NONE; | |
1968 | ||
1969 | ECR_WRITE(p, oecr); | |
1970 | return dma; | |
1971 | } | |
1972 | ||
1973 | static int parport_dma_probe(struct parport *p) | |
1974 | { | |
1975 | const struct parport_pc_private *priv = p->private_data; | |
1976 | if (priv->ecr) /* ask ECP chipset first */ | |
1977 | p->dma = programmable_dma_support(p); | |
1978 | if (p->dma == PARPORT_DMA_NONE) { | |
1979 | /* ask known Super-IO chips proper, although these | |
1980 | claim ECP compatible, some don't report their DMA | |
1981 | conforming to ECP standards */ | |
1982 | p->dma = get_superio_dma(p); | |
1983 | } | |
1984 | ||
1985 | return p->dma; | |
1986 | } | |
1987 | ||
1988 | /* --- Initialisation code -------------------------------- */ | |
1989 | ||
1990 | static LIST_HEAD(ports_list); | |
1991 | static DEFINE_SPINLOCK(ports_lock); | |
1992 | ||
1993 | struct parport *parport_pc_probe_port(unsigned long int base, | |
1994 | unsigned long int base_hi, | |
1995 | int irq, int dma, | |
1996 | struct device *dev, | |
1997 | int irqflags) | |
1998 | { | |
1999 | struct parport_pc_private *priv; | |
2000 | struct parport_operations *ops; | |
2001 | struct parport *p; | |
2002 | int probedirq = PARPORT_IRQ_NONE; | |
2003 | struct resource *base_res; | |
2004 | struct resource *ECR_res = NULL; | |
2005 | struct resource *EPP_res = NULL; | |
2006 | struct platform_device *pdev = NULL; | |
2007 | ||
2008 | if (!dev) { | |
2009 | /* We need a physical device to attach to, but none was | |
2010 | * provided. Create our own. */ | |
2011 | pdev = platform_device_register_simple("parport_pc", | |
2012 | base, NULL, 0); | |
2013 | if (IS_ERR(pdev)) | |
2014 | return NULL; | |
2015 | dev = &pdev->dev; | |
2016 | ||
2017 | dev->coherent_dma_mask = DMA_BIT_MASK(24); | |
2018 | dev->dma_mask = &dev->coherent_dma_mask; | |
2019 | } | |
2020 | ||
2021 | ops = kmalloc(sizeof(struct parport_operations), GFP_KERNEL); | |
2022 | if (!ops) | |
2023 | goto out1; | |
2024 | ||
2025 | priv = kmalloc(sizeof(struct parport_pc_private), GFP_KERNEL); | |
2026 | if (!priv) | |
2027 | goto out2; | |
2028 | ||
2029 | /* a misnomer, actually - it's allocate and reserve parport number */ | |
2030 | p = parport_register_port(base, irq, dma, ops); | |
2031 | if (!p) | |
2032 | goto out3; | |
2033 | ||
2034 | base_res = request_region(base, 3, p->name); | |
2035 | if (!base_res) | |
2036 | goto out4; | |
2037 | ||
2038 | memcpy(ops, &parport_pc_ops, sizeof(struct parport_operations)); | |
2039 | priv->ctr = 0xc; | |
2040 | priv->ctr_writable = ~0x10; | |
2041 | priv->ecr = 0; | |
2042 | priv->fifo_depth = 0; | |
2043 | priv->dma_buf = NULL; | |
2044 | priv->dma_handle = 0; | |
2045 | INIT_LIST_HEAD(&priv->list); | |
2046 | priv->port = p; | |
2047 | ||
2048 | p->dev = dev; | |
2049 | p->base_hi = base_hi; | |
2050 | p->modes = PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT; | |
2051 | p->private_data = priv; | |
2052 | ||
2053 | if (base_hi) { | |
2054 | ECR_res = request_region(base_hi, 3, p->name); | |
2055 | if (ECR_res) | |
2056 | parport_ECR_present(p); | |
2057 | } | |
2058 | ||
2059 | if (base != 0x3bc) { | |
2060 | EPP_res = request_region(base+0x3, 5, p->name); | |
2061 | if (EPP_res) | |
2062 | if (!parport_EPP_supported(p)) | |
2063 | parport_ECPEPP_supported(p); | |
2064 | } | |
2065 | if (!parport_SPP_supported(p)) | |
2066 | /* No port. */ | |
2067 | goto out5; | |
2068 | if (priv->ecr) | |
2069 | parport_ECPPS2_supported(p); | |
2070 | else | |
2071 | parport_PS2_supported(p); | |
2072 | ||
2073 | p->size = (p->modes & PARPORT_MODE_EPP) ? 8 : 3; | |
2074 | ||
2075 | printk(KERN_INFO "%s: PC-style at 0x%lx", p->name, p->base); | |
2076 | if (p->base_hi && priv->ecr) | |
2077 | printk(KERN_CONT " (0x%lx)", p->base_hi); | |
2078 | if (p->irq == PARPORT_IRQ_AUTO) { | |
2079 | p->irq = PARPORT_IRQ_NONE; | |
2080 | parport_irq_probe(p); | |
2081 | } else if (p->irq == PARPORT_IRQ_PROBEONLY) { | |
2082 | p->irq = PARPORT_IRQ_NONE; | |
2083 | parport_irq_probe(p); | |
2084 | probedirq = p->irq; | |
2085 | p->irq = PARPORT_IRQ_NONE; | |
2086 | } | |
2087 | if (p->irq != PARPORT_IRQ_NONE) { | |
2088 | printk(KERN_CONT ", irq %d", p->irq); | |
2089 | priv->ctr_writable |= 0x10; | |
2090 | ||
2091 | if (p->dma == PARPORT_DMA_AUTO) { | |
2092 | p->dma = PARPORT_DMA_NONE; | |
2093 | parport_dma_probe(p); | |
2094 | } | |
2095 | } | |
2096 | if (p->dma == PARPORT_DMA_AUTO) /* To use DMA, giving the irq | |
2097 | is mandatory (see above) */ | |
2098 | p->dma = PARPORT_DMA_NONE; | |
2099 | ||
2100 | #ifdef CONFIG_PARPORT_PC_FIFO | |
2101 | if (parport_ECP_supported(p) && | |
2102 | p->dma != PARPORT_DMA_NOFIFO && | |
2103 | priv->fifo_depth > 0 && p->irq != PARPORT_IRQ_NONE) { | |
2104 | p->modes |= PARPORT_MODE_ECP | PARPORT_MODE_COMPAT; | |
2105 | p->ops->compat_write_data = parport_pc_compat_write_block_pio; | |
2106 | #ifdef CONFIG_PARPORT_1284 | |
2107 | p->ops->ecp_write_data = parport_pc_ecp_write_block_pio; | |
2108 | /* currently broken, but working on it.. (FB) */ | |
2109 | /* p->ops->ecp_read_data = parport_pc_ecp_read_block_pio; */ | |
2110 | #endif /* IEEE 1284 support */ | |
2111 | if (p->dma != PARPORT_DMA_NONE) { | |
2112 | printk(KERN_CONT ", dma %d", p->dma); | |
2113 | p->modes |= PARPORT_MODE_DMA; | |
2114 | } else | |
2115 | printk(KERN_CONT ", using FIFO"); | |
2116 | } else | |
2117 | /* We can't use the DMA channel after all. */ | |
2118 | p->dma = PARPORT_DMA_NONE; | |
2119 | #endif /* Allowed to use FIFO/DMA */ | |
2120 | ||
2121 | printk(KERN_CONT " ["); | |
2122 | ||
2123 | #define printmode(x) \ | |
2124 | {\ | |
2125 | if (p->modes & PARPORT_MODE_##x) {\ | |
2126 | printk(KERN_CONT "%s%s", f ? "," : "", #x);\ | |
2127 | f++;\ | |
2128 | } \ | |
2129 | } | |
2130 | ||
2131 | { | |
2132 | int f = 0; | |
2133 | printmode(PCSPP); | |
2134 | printmode(TRISTATE); | |
2135 | printmode(COMPAT) | |
2136 | printmode(EPP); | |
2137 | printmode(ECP); | |
2138 | printmode(DMA); | |
2139 | } | |
2140 | #undef printmode | |
2141 | #ifndef CONFIG_PARPORT_1284 | |
2142 | printk(KERN_CONT "(,...)"); | |
2143 | #endif /* CONFIG_PARPORT_1284 */ | |
2144 | printk(KERN_CONT "]\n"); | |
2145 | if (probedirq != PARPORT_IRQ_NONE) | |
2146 | printk(KERN_INFO "%s: irq %d detected\n", p->name, probedirq); | |
2147 | ||
2148 | /* If No ECP release the ports grabbed above. */ | |
2149 | if (ECR_res && (p->modes & PARPORT_MODE_ECP) == 0) { | |
2150 | release_region(base_hi, 3); | |
2151 | ECR_res = NULL; | |
2152 | } | |
2153 | /* Likewise for EEP ports */ | |
2154 | if (EPP_res && (p->modes & PARPORT_MODE_EPP) == 0) { | |
2155 | release_region(base+3, 5); | |
2156 | EPP_res = NULL; | |
2157 | } | |
2158 | if (p->irq != PARPORT_IRQ_NONE) { | |
2159 | if (request_irq(p->irq, parport_irq_handler, | |
2160 | irqflags, p->name, p)) { | |
2161 | printk(KERN_WARNING "%s: irq %d in use, " | |
2162 | "resorting to polled operation\n", | |
2163 | p->name, p->irq); | |
2164 | p->irq = PARPORT_IRQ_NONE; | |
2165 | p->dma = PARPORT_DMA_NONE; | |
2166 | } | |
2167 | ||
2168 | #ifdef CONFIG_PARPORT_PC_FIFO | |
2169 | #ifdef HAS_DMA | |
2170 | if (p->dma != PARPORT_DMA_NONE) { | |
2171 | if (request_dma(p->dma, p->name)) { | |
2172 | printk(KERN_WARNING "%s: dma %d in use, " | |
2173 | "resorting to PIO operation\n", | |
2174 | p->name, p->dma); | |
2175 | p->dma = PARPORT_DMA_NONE; | |
2176 | } else { | |
2177 | priv->dma_buf = | |
2178 | dma_alloc_coherent(dev, | |
2179 | PAGE_SIZE, | |
2180 | &priv->dma_handle, | |
2181 | GFP_KERNEL); | |
2182 | if (!priv->dma_buf) { | |
2183 | printk(KERN_WARNING "%s: " | |
2184 | "cannot get buffer for DMA, " | |
2185 | "resorting to PIO operation\n", | |
2186 | p->name); | |
2187 | free_dma(p->dma); | |
2188 | p->dma = PARPORT_DMA_NONE; | |
2189 | } | |
2190 | } | |
2191 | } | |
2192 | #endif | |
2193 | #endif | |
2194 | } | |
2195 | ||
2196 | /* Done probing. Now put the port into a sensible start-up state. */ | |
2197 | if (priv->ecr) | |
2198 | /* | |
2199 | * Put the ECP detected port in PS2 mode. | |
2200 | * Do this also for ports that have ECR but don't do ECP. | |
2201 | */ | |
2202 | ECR_WRITE(p, 0x34); | |
2203 | ||
2204 | parport_pc_write_data(p, 0); | |
2205 | parport_pc_data_forward(p); | |
2206 | ||
2207 | /* Now that we've told the sharing engine about the port, and | |
2208 | found out its characteristics, let the high-level drivers | |
2209 | know about it. */ | |
2210 | spin_lock(&ports_lock); | |
2211 | list_add(&priv->list, &ports_list); | |
2212 | spin_unlock(&ports_lock); | |
2213 | parport_announce_port(p); | |
2214 | ||
2215 | return p; | |
2216 | ||
2217 | out5: | |
2218 | if (ECR_res) | |
2219 | release_region(base_hi, 3); | |
2220 | if (EPP_res) | |
2221 | release_region(base+0x3, 5); | |
2222 | release_region(base, 3); | |
2223 | out4: | |
2224 | parport_put_port(p); | |
2225 | out3: | |
2226 | kfree(priv); | |
2227 | out2: | |
2228 | kfree(ops); | |
2229 | out1: | |
2230 | if (pdev) | |
2231 | platform_device_unregister(pdev); | |
2232 | return NULL; | |
2233 | } | |
2234 | EXPORT_SYMBOL(parport_pc_probe_port); | |
2235 | ||
2236 | void parport_pc_unregister_port(struct parport *p) | |
2237 | { | |
2238 | struct parport_pc_private *priv = p->private_data; | |
2239 | struct parport_operations *ops = p->ops; | |
2240 | ||
2241 | parport_remove_port(p); | |
2242 | spin_lock(&ports_lock); | |
2243 | list_del_init(&priv->list); | |
2244 | spin_unlock(&ports_lock); | |
2245 | #if defined(CONFIG_PARPORT_PC_FIFO) && defined(HAS_DMA) | |
2246 | if (p->dma != PARPORT_DMA_NONE) | |
2247 | free_dma(p->dma); | |
2248 | #endif | |
2249 | if (p->irq != PARPORT_IRQ_NONE) | |
2250 | free_irq(p->irq, p); | |
2251 | release_region(p->base, 3); | |
2252 | if (p->size > 3) | |
2253 | release_region(p->base + 3, p->size - 3); | |
2254 | if (p->modes & PARPORT_MODE_ECP) | |
2255 | release_region(p->base_hi, 3); | |
2256 | #if defined(CONFIG_PARPORT_PC_FIFO) && defined(HAS_DMA) | |
2257 | if (priv->dma_buf) | |
2258 | dma_free_coherent(p->physport->dev, PAGE_SIZE, | |
2259 | priv->dma_buf, | |
2260 | priv->dma_handle); | |
2261 | #endif | |
2262 | kfree(p->private_data); | |
2263 | parport_put_port(p); | |
2264 | kfree(ops); /* hope no-one cached it */ | |
2265 | } | |
2266 | EXPORT_SYMBOL(parport_pc_unregister_port); | |
2267 | ||
2268 | #ifdef CONFIG_PCI | |
2269 | ||
2270 | /* ITE support maintained by Rich Liu <richliu@poorman.org> */ | |
2271 | static int sio_ite_8872_probe(struct pci_dev *pdev, int autoirq, int autodma, | |
2272 | const struct parport_pc_via_data *via) | |
2273 | { | |
2274 | short inta_addr[6] = { 0x2A0, 0x2C0, 0x220, 0x240, 0x1E0 }; | |
2275 | u32 ite8872set; | |
2276 | u32 ite8872_lpt, ite8872_lpthi; | |
2277 | u8 ite8872_irq, type; | |
2278 | int irq; | |
2279 | int i; | |
2280 | ||
2281 | DPRINTK(KERN_DEBUG "sio_ite_8872_probe()\n"); | |
2282 | ||
2283 | /* make sure which one chip */ | |
2284 | for (i = 0; i < 5; i++) { | |
2285 | if (request_region(inta_addr[i], 32, "it887x")) { | |
2286 | int test; | |
2287 | pci_write_config_dword(pdev, 0x60, | |
2288 | 0xe5000000 | inta_addr[i]); | |
2289 | pci_write_config_dword(pdev, 0x78, | |
2290 | 0x00000000 | inta_addr[i]); | |
2291 | test = inb(inta_addr[i]); | |
2292 | if (test != 0xff) | |
2293 | break; | |
2294 | release_region(inta_addr[i], 32); | |
2295 | } | |
2296 | } | |
2297 | if (i >= 5) { | |
2298 | printk(KERN_INFO "parport_pc: cannot find ITE8872 INTA\n"); | |
2299 | return 0; | |
2300 | } | |
2301 | ||
2302 | type = inb(inta_addr[i] + 0x18); | |
2303 | type &= 0x0f; | |
2304 | ||
2305 | switch (type) { | |
2306 | case 0x2: | |
2307 | printk(KERN_INFO "parport_pc: ITE8871 found (1P)\n"); | |
2308 | ite8872set = 0x64200000; | |
2309 | break; | |
2310 | case 0xa: | |
2311 | printk(KERN_INFO "parport_pc: ITE8875 found (1P)\n"); | |
2312 | ite8872set = 0x64200000; | |
2313 | break; | |
2314 | case 0xe: | |
2315 | printk(KERN_INFO "parport_pc: ITE8872 found (2S1P)\n"); | |
2316 | ite8872set = 0x64e00000; | |
2317 | break; | |
2318 | case 0x6: | |
2319 | printk(KERN_INFO "parport_pc: ITE8873 found (1S)\n"); | |
2320 | release_region(inta_addr[i], 32); | |
2321 | return 0; | |
2322 | case 0x8: | |
2323 | printk(KERN_INFO "parport_pc: ITE8874 found (2S)\n"); | |
2324 | release_region(inta_addr[i], 32); | |
2325 | return 0; | |
2326 | default: | |
2327 | printk(KERN_INFO "parport_pc: unknown ITE887x\n"); | |
2328 | printk(KERN_INFO "parport_pc: please mail 'lspci -nvv' " | |
2329 | "output to Rich.Liu@ite.com.tw\n"); | |
2330 | release_region(inta_addr[i], 32); | |
2331 | return 0; | |
2332 | } | |
2333 | ||
2334 | pci_read_config_byte(pdev, 0x3c, &ite8872_irq); | |
2335 | pci_read_config_dword(pdev, 0x1c, &ite8872_lpt); | |
2336 | ite8872_lpt &= 0x0000ff00; | |
2337 | pci_read_config_dword(pdev, 0x20, &ite8872_lpthi); | |
2338 | ite8872_lpthi &= 0x0000ff00; | |
2339 | pci_write_config_dword(pdev, 0x6c, 0xe3000000 | ite8872_lpt); | |
2340 | pci_write_config_dword(pdev, 0x70, 0xe3000000 | ite8872_lpthi); | |
2341 | pci_write_config_dword(pdev, 0x80, (ite8872_lpthi<<16) | ite8872_lpt); | |
2342 | /* SET SPP&EPP , Parallel Port NO DMA , Enable All Function */ | |
2343 | /* SET Parallel IRQ */ | |
2344 | pci_write_config_dword(pdev, 0x9c, | |
2345 | ite8872set | (ite8872_irq * 0x11111)); | |
2346 | ||
2347 | DPRINTK(KERN_DEBUG "ITE887x: The IRQ is %d.\n", ite8872_irq); | |
2348 | DPRINTK(KERN_DEBUG "ITE887x: The PARALLEL I/O port is 0x%x.\n", | |
2349 | ite8872_lpt); | |
2350 | DPRINTK(KERN_DEBUG "ITE887x: The PARALLEL I/O porthi is 0x%x.\n", | |
2351 | ite8872_lpthi); | |
2352 | ||
2353 | /* Let the user (or defaults) steer us away from interrupts */ | |
2354 | irq = ite8872_irq; | |
2355 | if (autoirq != PARPORT_IRQ_AUTO) | |
2356 | irq = PARPORT_IRQ_NONE; | |
2357 | ||
2358 | /* | |
2359 | * Release the resource so that parport_pc_probe_port can get it. | |
2360 | */ | |
2361 | release_region(inta_addr[i], 32); | |
2362 | if (parport_pc_probe_port(ite8872_lpt, ite8872_lpthi, | |
2363 | irq, PARPORT_DMA_NONE, &pdev->dev, 0)) { | |
2364 | printk(KERN_INFO | |
2365 | "parport_pc: ITE 8872 parallel port: io=0x%X", | |
2366 | ite8872_lpt); | |
2367 | if (irq != PARPORT_IRQ_NONE) | |
2368 | printk(", irq=%d", irq); | |
2369 | printk("\n"); | |
2370 | return 1; | |
2371 | } | |
2372 | ||
2373 | return 0; | |
2374 | } | |
2375 | ||
2376 | /* VIA 8231 support by Pavel Fedin <sonic_amiga@rambler.ru> | |
2377 | based on VIA 686a support code by Jeff Garzik <jgarzik@pobox.com> */ | |
2378 | static int parport_init_mode; | |
2379 | ||
2380 | /* Data for two known VIA chips */ | |
2381 | static struct parport_pc_via_data via_686a_data = { | |
2382 | 0x51, | |
2383 | 0x50, | |
2384 | 0x85, | |
2385 | 0x02, | |
2386 | 0xE2, | |
2387 | 0xF0, | |
2388 | 0xE6 | |
2389 | }; | |
2390 | static struct parport_pc_via_data via_8231_data = { | |
2391 | 0x45, | |
2392 | 0x44, | |
2393 | 0x50, | |
2394 | 0x04, | |
2395 | 0xF2, | |
2396 | 0xFA, | |
2397 | 0xF6 | |
2398 | }; | |
2399 | ||
2400 | static int sio_via_probe(struct pci_dev *pdev, int autoirq, int autodma, | |
2401 | const struct parport_pc_via_data *via) | |
2402 | { | |
2403 | u8 tmp, tmp2, siofunc; | |
2404 | u8 ppcontrol = 0; | |
2405 | int dma, irq; | |
2406 | unsigned port1, port2; | |
2407 | unsigned have_epp = 0; | |
2408 | ||
2409 | printk(KERN_DEBUG "parport_pc: VIA 686A/8231 detected\n"); | |
2410 | ||
2411 | switch (parport_init_mode) { | |
2412 | case 1: | |
2413 | printk(KERN_DEBUG "parport_pc: setting SPP mode\n"); | |
2414 | siofunc = VIA_FUNCTION_PARPORT_SPP; | |
2415 | break; | |
2416 | case 2: | |
2417 | printk(KERN_DEBUG "parport_pc: setting PS/2 mode\n"); | |
2418 | siofunc = VIA_FUNCTION_PARPORT_SPP; | |
2419 | ppcontrol = VIA_PARPORT_BIDIR; | |
2420 | break; | |
2421 | case 3: | |
2422 | printk(KERN_DEBUG "parport_pc: setting EPP mode\n"); | |
2423 | siofunc = VIA_FUNCTION_PARPORT_EPP; | |
2424 | ppcontrol = VIA_PARPORT_BIDIR; | |
2425 | have_epp = 1; | |
2426 | break; | |
2427 | case 4: | |
2428 | printk(KERN_DEBUG "parport_pc: setting ECP mode\n"); | |
2429 | siofunc = VIA_FUNCTION_PARPORT_ECP; | |
2430 | ppcontrol = VIA_PARPORT_BIDIR; | |
2431 | break; | |
2432 | case 5: | |
2433 | printk(KERN_DEBUG "parport_pc: setting EPP+ECP mode\n"); | |
2434 | siofunc = VIA_FUNCTION_PARPORT_ECP; | |
2435 | ppcontrol = VIA_PARPORT_BIDIR|VIA_PARPORT_ECPEPP; | |
2436 | have_epp = 1; | |
2437 | break; | |
2438 | default: | |
2439 | printk(KERN_DEBUG | |
2440 | "parport_pc: probing current configuration\n"); | |
2441 | siofunc = VIA_FUNCTION_PROBE; | |
2442 | break; | |
2443 | } | |
2444 | /* | |
2445 | * unlock super i/o configuration | |
2446 | */ | |
2447 | pci_read_config_byte(pdev, via->via_pci_superio_config_reg, &tmp); | |
2448 | tmp |= via->via_pci_superio_config_data; | |
2449 | pci_write_config_byte(pdev, via->via_pci_superio_config_reg, tmp); | |
2450 | ||
2451 | /* Bits 1-0: Parallel Port Mode / Enable */ | |
2452 | outb(via->viacfg_function, VIA_CONFIG_INDEX); | |
2453 | tmp = inb(VIA_CONFIG_DATA); | |
2454 | /* Bit 5: EPP+ECP enable; bit 7: PS/2 bidirectional port enable */ | |
2455 | outb(via->viacfg_parport_control, VIA_CONFIG_INDEX); | |
2456 | tmp2 = inb(VIA_CONFIG_DATA); | |
2457 | if (siofunc == VIA_FUNCTION_PROBE) { | |
2458 | siofunc = tmp & VIA_FUNCTION_PARPORT_DISABLE; | |
2459 | ppcontrol = tmp2; | |
2460 | } else { | |
2461 | tmp &= ~VIA_FUNCTION_PARPORT_DISABLE; | |
2462 | tmp |= siofunc; | |
2463 | outb(via->viacfg_function, VIA_CONFIG_INDEX); | |
2464 | outb(tmp, VIA_CONFIG_DATA); | |
2465 | tmp2 &= ~(VIA_PARPORT_BIDIR|VIA_PARPORT_ECPEPP); | |
2466 | tmp2 |= ppcontrol; | |
2467 | outb(via->viacfg_parport_control, VIA_CONFIG_INDEX); | |
2468 | outb(tmp2, VIA_CONFIG_DATA); | |
2469 | } | |
2470 | ||
2471 | /* Parallel Port I/O Base Address, bits 9-2 */ | |
2472 | outb(via->viacfg_parport_base, VIA_CONFIG_INDEX); | |
2473 | port1 = inb(VIA_CONFIG_DATA) << 2; | |
2474 | ||
2475 | printk(KERN_DEBUG "parport_pc: Current parallel port base: 0x%X\n", | |
2476 | port1); | |
2477 | if (port1 == 0x3BC && have_epp) { | |
2478 | outb(via->viacfg_parport_base, VIA_CONFIG_INDEX); | |
2479 | outb((0x378 >> 2), VIA_CONFIG_DATA); | |
2480 | printk(KERN_DEBUG | |
2481 | "parport_pc: Parallel port base changed to 0x378\n"); | |
2482 | port1 = 0x378; | |
2483 | } | |
2484 | ||
2485 | /* | |
2486 | * lock super i/o configuration | |
2487 | */ | |
2488 | pci_read_config_byte(pdev, via->via_pci_superio_config_reg, &tmp); | |
2489 | tmp &= ~via->via_pci_superio_config_data; | |
2490 | pci_write_config_byte(pdev, via->via_pci_superio_config_reg, tmp); | |
2491 | ||
2492 | if (siofunc == VIA_FUNCTION_PARPORT_DISABLE) { | |
2493 | printk(KERN_INFO "parport_pc: VIA parallel port disabled in BIOS\n"); | |
2494 | return 0; | |
2495 | } | |
2496 | ||
2497 | /* Bits 7-4: PnP Routing for Parallel Port IRQ */ | |
2498 | pci_read_config_byte(pdev, via->via_pci_parport_irq_reg, &tmp); | |
2499 | irq = ((tmp & VIA_IRQCONTROL_PARALLEL) >> 4); | |
2500 | ||
2501 | if (siofunc == VIA_FUNCTION_PARPORT_ECP) { | |
2502 | /* Bits 3-2: PnP Routing for Parallel Port DMA */ | |
2503 | pci_read_config_byte(pdev, via->via_pci_parport_dma_reg, &tmp); | |
2504 | dma = ((tmp & VIA_DMACONTROL_PARALLEL) >> 2); | |
2505 | } else | |
2506 | /* if ECP not enabled, DMA is not enabled, assumed | |
2507 | bogus 'dma' value */ | |
2508 | dma = PARPORT_DMA_NONE; | |
2509 | ||
2510 | /* Let the user (or defaults) steer us away from interrupts and DMA */ | |
2511 | if (autoirq == PARPORT_IRQ_NONE) { | |
2512 | irq = PARPORT_IRQ_NONE; | |
2513 | dma = PARPORT_DMA_NONE; | |
2514 | } | |
2515 | if (autodma == PARPORT_DMA_NONE) | |
2516 | dma = PARPORT_DMA_NONE; | |
2517 | ||
2518 | switch (port1) { | |
2519 | case 0x3bc: | |
2520 | port2 = 0x7bc; break; | |
2521 | case 0x378: | |
2522 | port2 = 0x778; break; | |
2523 | case 0x278: | |
2524 | port2 = 0x678; break; | |
2525 | default: | |
2526 | printk(KERN_INFO | |
2527 | "parport_pc: Weird VIA parport base 0x%X, ignoring\n", | |
2528 | port1); | |
2529 | return 0; | |
2530 | } | |
2531 | ||
2532 | /* filter bogus IRQs */ | |
2533 | switch (irq) { | |
2534 | case 0: | |
2535 | case 2: | |
2536 | case 8: | |
2537 | case 13: | |
2538 | irq = PARPORT_IRQ_NONE; | |
2539 | break; | |
2540 | ||
2541 | default: /* do nothing */ | |
2542 | break; | |
2543 | } | |
2544 | ||
2545 | /* finally, do the probe with values obtained */ | |
2546 | if (parport_pc_probe_port(port1, port2, irq, dma, &pdev->dev, 0)) { | |
2547 | printk(KERN_INFO | |
2548 | "parport_pc: VIA parallel port: io=0x%X", port1); | |
2549 | if (irq != PARPORT_IRQ_NONE) | |
2550 | printk(", irq=%d", irq); | |
2551 | if (dma != PARPORT_DMA_NONE) | |
2552 | printk(", dma=%d", dma); | |
2553 | printk("\n"); | |
2554 | return 1; | |
2555 | } | |
2556 | ||
2557 | printk(KERN_WARNING "parport_pc: Strange, can't probe VIA parallel port: io=0x%X, irq=%d, dma=%d\n", | |
2558 | port1, irq, dma); | |
2559 | return 0; | |
2560 | } | |
2561 | ||
2562 | ||
2563 | enum parport_pc_sio_types { | |
2564 | sio_via_686a = 0, /* Via VT82C686A motherboard Super I/O */ | |
2565 | sio_via_8231, /* Via VT8231 south bridge integrated Super IO */ | |
2566 | sio_ite_8872, | |
2567 | last_sio | |
2568 | }; | |
2569 | ||
2570 | /* each element directly indexed from enum list, above */ | |
2571 | static struct parport_pc_superio { | |
2572 | int (*probe) (struct pci_dev *pdev, int autoirq, int autodma, | |
2573 | const struct parport_pc_via_data *via); | |
2574 | const struct parport_pc_via_data *via; | |
2575 | } parport_pc_superio_info[] = { | |
2576 | { sio_via_probe, &via_686a_data, }, | |
2577 | { sio_via_probe, &via_8231_data, }, | |
2578 | { sio_ite_8872_probe, NULL, }, | |
2579 | }; | |
2580 | ||
2581 | enum parport_pc_pci_cards { | |
2582 | siig_1p_10x = last_sio, | |
2583 | siig_2p_10x, | |
2584 | siig_1p_20x, | |
2585 | siig_2p_20x, | |
2586 | lava_parallel, | |
2587 | lava_parallel_dual_a, | |
2588 | lava_parallel_dual_b, | |
2589 | boca_ioppar, | |
2590 | plx_9050, | |
2591 | timedia_4006a, | |
2592 | timedia_4014, | |
2593 | timedia_4008a, | |
2594 | timedia_4018, | |
2595 | timedia_9018a, | |
2596 | syba_2p_epp, | |
2597 | syba_1p_ecp, | |
2598 | titan_010l, | |
2599 | titan_1284p1, | |
2600 | titan_1284p2, | |
2601 | avlab_1p, | |
2602 | avlab_2p, | |
2603 | oxsemi_952, | |
2604 | oxsemi_954, | |
2605 | oxsemi_840, | |
2606 | oxsemi_pcie_pport, | |
2607 | aks_0100, | |
2608 | mobility_pp, | |
2609 | netmos_9705, | |
2610 | netmos_9715, | |
2611 | netmos_9755, | |
2612 | netmos_9805, | |
2613 | netmos_9815, | |
2614 | netmos_9901, | |
2615 | netmos_9865, | |
2616 | quatech_sppxp100, | |
2617 | }; | |
2618 | ||
2619 | ||
2620 | /* each element directly indexed from enum list, above | |
2621 | * (but offset by last_sio) */ | |
2622 | static struct parport_pc_pci { | |
2623 | int numports; | |
2624 | struct { /* BAR (base address registers) numbers in the config | |
2625 | space header */ | |
2626 | int lo; | |
2627 | int hi; | |
2628 | /* -1 if not there, >6 for offset-method (max BAR is 6) */ | |
2629 | } addr[4]; | |
2630 | ||
2631 | /* If set, this is called immediately after pci_enable_device. | |
2632 | * If it returns non-zero, no probing will take place and the | |
2633 | * ports will not be used. */ | |
2634 | int (*preinit_hook) (struct pci_dev *pdev, int autoirq, int autodma); | |
2635 | ||
2636 | /* If set, this is called after probing for ports. If 'failed' | |
2637 | * is non-zero we couldn't use any of the ports. */ | |
2638 | void (*postinit_hook) (struct pci_dev *pdev, int failed); | |
2639 | } cards[] = { | |
2640 | /* siig_1p_10x */ { 1, { { 2, 3 }, } }, | |
2641 | /* siig_2p_10x */ { 2, { { 2, 3 }, { 4, 5 }, } }, | |
2642 | /* siig_1p_20x */ { 1, { { 0, 1 }, } }, | |
2643 | /* siig_2p_20x */ { 2, { { 0, 1 }, { 2, 3 }, } }, | |
2644 | /* lava_parallel */ { 1, { { 0, -1 }, } }, | |
2645 | /* lava_parallel_dual_a */ { 1, { { 0, -1 }, } }, | |
2646 | /* lava_parallel_dual_b */ { 1, { { 0, -1 }, } }, | |
2647 | /* boca_ioppar */ { 1, { { 0, -1 }, } }, | |
2648 | /* plx_9050 */ { 2, { { 4, -1 }, { 5, -1 }, } }, | |
2649 | /* timedia_4006a */ { 1, { { 0, -1 }, } }, | |
2650 | /* timedia_4014 */ { 2, { { 0, -1 }, { 2, -1 }, } }, | |
2651 | /* timedia_4008a */ { 1, { { 0, 1 }, } }, | |
2652 | /* timedia_4018 */ { 2, { { 0, 1 }, { 2, 3 }, } }, | |
2653 | /* timedia_9018a */ { 2, { { 0, 1 }, { 2, 3 }, } }, | |
2654 | /* SYBA uses fixed offsets in | |
2655 | a 1K io window */ | |
2656 | /* syba_2p_epp AP138B */ { 2, { { 0, 0x078 }, { 0, 0x178 }, } }, | |
2657 | /* syba_1p_ecp W83787 */ { 1, { { 0, 0x078 }, } }, | |
2658 | /* titan_010l */ { 1, { { 3, -1 }, } }, | |
2659 | /* titan_1284p1 */ { 1, { { 0, 1 }, } }, | |
2660 | /* titan_1284p2 */ { 2, { { 0, 1 }, { 2, 3 }, } }, | |
2661 | /* avlab_1p */ { 1, { { 0, 1}, } }, | |
2662 | /* avlab_2p */ { 2, { { 0, 1}, { 2, 3 },} }, | |
2663 | /* The Oxford Semi cards are unusual: 954 doesn't support ECP, | |
2664 | * and 840 locks up if you write 1 to bit 2! */ | |
2665 | /* oxsemi_952 */ { 1, { { 0, 1 }, } }, | |
2666 | /* oxsemi_954 */ { 1, { { 0, -1 }, } }, | |
2667 | /* oxsemi_840 */ { 1, { { 0, 1 }, } }, | |
2668 | /* oxsemi_pcie_pport */ { 1, { { 0, 1 }, } }, | |
2669 | /* aks_0100 */ { 1, { { 0, -1 }, } }, | |
2670 | /* mobility_pp */ { 1, { { 0, 1 }, } }, | |
2671 | ||
2672 | /* The netmos entries below are untested */ | |
2673 | /* netmos_9705 */ { 1, { { 0, -1 }, } }, | |
2674 | /* netmos_9715 */ { 2, { { 0, 1 }, { 2, 3 },} }, | |
2675 | /* netmos_9755 */ { 2, { { 0, 1 }, { 2, 3 },} }, | |
2676 | /* netmos_9805 */ { 1, { { 0, -1 }, } }, | |
2677 | /* netmos_9815 */ { 2, { { 0, -1 }, { 2, -1 }, } }, | |
2678 | /* netmos_9901 */ { 1, { { 0, -1 }, } }, | |
2679 | /* netmos_9865 */ { 1, { { 0, -1 }, } }, | |
2680 | /* quatech_sppxp100 */ { 1, { { 0, 1 }, } }, | |
2681 | }; | |
2682 | ||
2683 | static const struct pci_device_id parport_pc_pci_tbl[] = { | |
2684 | /* Super-IO onboard chips */ | |
2685 | { 0x1106, 0x0686, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_686a }, | |
2686 | { 0x1106, 0x8231, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_8231 }, | |
2687 | { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872, | |
2688 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_ite_8872 }, | |
2689 | ||
2690 | /* PCI cards */ | |
2691 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_10x, | |
2692 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_10x }, | |
2693 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_10x, | |
2694 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_10x }, | |
2695 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_20x, | |
2696 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_20x }, | |
2697 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_20x, | |
2698 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_20x }, | |
2699 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PARALLEL, | |
2700 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel }, | |
2701 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_A, | |
2702 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_a }, | |
2703 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_B, | |
2704 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_b }, | |
2705 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_BOCA_IOPPAR, | |
2706 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, boca_ioppar }, | |
2707 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, | |
2708 | PCI_SUBVENDOR_ID_EXSYS, PCI_SUBDEVICE_ID_EXSYS_4014, 0, 0, plx_9050 }, | |
2709 | /* PCI_VENDOR_ID_TIMEDIA/SUNIX has many differing cards ...*/ | |
2710 | { 0x1409, 0x7268, 0x1409, 0x0101, 0, 0, timedia_4006a }, | |
2711 | { 0x1409, 0x7268, 0x1409, 0x0102, 0, 0, timedia_4014 }, | |
2712 | { 0x1409, 0x7268, 0x1409, 0x0103, 0, 0, timedia_4008a }, | |
2713 | { 0x1409, 0x7268, 0x1409, 0x0104, 0, 0, timedia_4018 }, | |
2714 | { 0x1409, 0x7268, 0x1409, 0x9018, 0, 0, timedia_9018a }, | |
2715 | { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_2P_EPP, | |
2716 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_2p_epp }, | |
2717 | { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_1P_ECP, | |
2718 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_1p_ecp }, | |
2719 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_010L, | |
2720 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, titan_010l }, | |
2721 | { 0x9710, 0x9805, 0x1000, 0x0010, 0, 0, titan_1284p1 }, | |
2722 | { 0x9710, 0x9815, 0x1000, 0x0020, 0, 0, titan_1284p2 }, | |
2723 | /* PCI_VENDOR_ID_AVLAB/Intek21 has another bunch of cards ...*/ | |
2724 | /* AFAVLAB_TK9902 */ | |
2725 | { 0x14db, 0x2120, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1p}, | |
2726 | { 0x14db, 0x2121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2p}, | |
2727 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952PP, | |
2728 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_952 }, | |
2729 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954PP, | |
2730 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_954 }, | |
2731 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_12PCI840, | |
2732 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_840 }, | |
2733 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe840, | |
2734 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport }, | |
2735 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe840_G, | |
2736 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport }, | |
2737 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_0, | |
2738 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport }, | |
2739 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_0_G, | |
2740 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport }, | |
2741 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1, | |
2742 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport }, | |
2743 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_G, | |
2744 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport }, | |
2745 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_U, | |
2746 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport }, | |
2747 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_GU, | |
2748 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport }, | |
2749 | { PCI_VENDOR_ID_AKS, PCI_DEVICE_ID_AKS_ALADDINCARD, | |
2750 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, aks_0100 }, | |
2751 | { 0x14f2, 0x0121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, mobility_pp }, | |
2752 | /* NetMos communication controllers */ | |
2753 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9705, | |
2754 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9705 }, | |
2755 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9715, | |
2756 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9715 }, | |
2757 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9755, | |
2758 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9755 }, | |
2759 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9805, | |
2760 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9805 }, | |
2761 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9815, | |
2762 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9815 }, | |
2763 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901, | |
2764 | 0xA000, 0x2000, 0, 0, netmos_9901 }, | |
2765 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, | |
2766 | 0xA000, 0x1000, 0, 0, netmos_9865 }, | |
2767 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, | |
2768 | 0xA000, 0x2000, 0, 0, netmos_9865 }, | |
2769 | /* Quatech SPPXP-100 Parallel port PCI ExpressCard */ | |
2770 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SPPXP_100, | |
2771 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, quatech_sppxp100 }, | |
2772 | { 0, } /* terminate list */ | |
2773 | }; | |
2774 | MODULE_DEVICE_TABLE(pci, parport_pc_pci_tbl); | |
2775 | ||
2776 | struct pci_parport_data { | |
2777 | int num; | |
2778 | struct parport *ports[2]; | |
2779 | }; | |
2780 | ||
2781 | static int parport_pc_pci_probe(struct pci_dev *dev, | |
2782 | const struct pci_device_id *id) | |
2783 | { | |
2784 | int err, count, n, i = id->driver_data; | |
2785 | struct pci_parport_data *data; | |
2786 | ||
2787 | if (i < last_sio) | |
2788 | /* This is an onboard Super-IO and has already been probed */ | |
2789 | return 0; | |
2790 | ||
2791 | /* This is a PCI card */ | |
2792 | i -= last_sio; | |
2793 | count = 0; | |
2794 | err = pci_enable_device(dev); | |
2795 | if (err) | |
2796 | return err; | |
2797 | ||
2798 | data = kmalloc(sizeof(struct pci_parport_data), GFP_KERNEL); | |
2799 | if (!data) | |
2800 | return -ENOMEM; | |
2801 | ||
2802 | if (cards[i].preinit_hook && | |
2803 | cards[i].preinit_hook(dev, PARPORT_IRQ_NONE, PARPORT_DMA_NONE)) { | |
2804 | kfree(data); | |
2805 | return -ENODEV; | |
2806 | } | |
2807 | ||
2808 | for (n = 0; n < cards[i].numports; n++) { | |
2809 | int lo = cards[i].addr[n].lo; | |
2810 | int hi = cards[i].addr[n].hi; | |
2811 | int irq; | |
2812 | unsigned long io_lo, io_hi; | |
2813 | io_lo = pci_resource_start(dev, lo); | |
2814 | io_hi = 0; | |
2815 | if ((hi >= 0) && (hi <= 6)) | |
2816 | io_hi = pci_resource_start(dev, hi); | |
2817 | else if (hi > 6) | |
2818 | io_lo += hi; /* Reinterpret the meaning of | |
2819 | "hi" as an offset (see SYBA | |
2820 | def.) */ | |
2821 | /* TODO: test if sharing interrupts works */ | |
2822 | irq = dev->irq; | |
2823 | if (irq == IRQ_NONE) { | |
2824 | printk(KERN_DEBUG | |
2825 | "PCI parallel port detected: %04x:%04x, I/O at %#lx(%#lx)\n", | |
2826 | parport_pc_pci_tbl[i + last_sio].vendor, | |
2827 | parport_pc_pci_tbl[i + last_sio].device, | |
2828 | io_lo, io_hi); | |
2829 | irq = PARPORT_IRQ_NONE; | |
2830 | } else { | |
2831 | printk(KERN_DEBUG | |
2832 | "PCI parallel port detected: %04x:%04x, I/O at %#lx(%#lx), IRQ %d\n", | |
2833 | parport_pc_pci_tbl[i + last_sio].vendor, | |
2834 | parport_pc_pci_tbl[i + last_sio].device, | |
2835 | io_lo, io_hi, irq); | |
2836 | } | |
2837 | data->ports[count] = | |
2838 | parport_pc_probe_port(io_lo, io_hi, irq, | |
2839 | PARPORT_DMA_NONE, &dev->dev, | |
2840 | IRQF_SHARED); | |
2841 | if (data->ports[count]) | |
2842 | count++; | |
2843 | } | |
2844 | ||
2845 | data->num = count; | |
2846 | ||
2847 | if (cards[i].postinit_hook) | |
2848 | cards[i].postinit_hook(dev, count == 0); | |
2849 | ||
2850 | if (count) { | |
2851 | pci_set_drvdata(dev, data); | |
2852 | return 0; | |
2853 | } | |
2854 | ||
2855 | kfree(data); | |
2856 | ||
2857 | return -ENODEV; | |
2858 | } | |
2859 | ||
2860 | static void parport_pc_pci_remove(struct pci_dev *dev) | |
2861 | { | |
2862 | struct pci_parport_data *data = pci_get_drvdata(dev); | |
2863 | int i; | |
2864 | ||
2865 | pci_set_drvdata(dev, NULL); | |
2866 | ||
2867 | if (data) { | |
2868 | for (i = data->num - 1; i >= 0; i--) | |
2869 | parport_pc_unregister_port(data->ports[i]); | |
2870 | ||
2871 | kfree(data); | |
2872 | } | |
2873 | } | |
2874 | ||
2875 | static struct pci_driver parport_pc_pci_driver = { | |
2876 | .name = "parport_pc", | |
2877 | .id_table = parport_pc_pci_tbl, | |
2878 | .probe = parport_pc_pci_probe, | |
2879 | .remove = parport_pc_pci_remove, | |
2880 | }; | |
2881 | ||
2882 | static int __init parport_pc_init_superio(int autoirq, int autodma) | |
2883 | { | |
2884 | const struct pci_device_id *id; | |
2885 | struct pci_dev *pdev = NULL; | |
2886 | int ret = 0; | |
2887 | ||
2888 | for_each_pci_dev(pdev) { | |
2889 | id = pci_match_id(parport_pc_pci_tbl, pdev); | |
2890 | if (id == NULL || id->driver_data >= last_sio) | |
2891 | continue; | |
2892 | ||
2893 | if (parport_pc_superio_info[id->driver_data].probe( | |
2894 | pdev, autoirq, autodma, | |
2895 | parport_pc_superio_info[id->driver_data].via)) { | |
2896 | ret++; | |
2897 | } | |
2898 | } | |
2899 | ||
2900 | return ret; /* number of devices found */ | |
2901 | } | |
2902 | #else | |
2903 | static struct pci_driver parport_pc_pci_driver; | |
2904 | static int __init parport_pc_init_superio(int autoirq, int autodma) | |
2905 | { | |
2906 | return 0; | |
2907 | } | |
2908 | #endif /* CONFIG_PCI */ | |
2909 | ||
2910 | #ifdef CONFIG_PNP | |
2911 | ||
2912 | static const struct pnp_device_id parport_pc_pnp_tbl[] = { | |
2913 | /* Standard LPT Printer Port */ | |
2914 | {.id = "PNP0400", .driver_data = 0}, | |
2915 | /* ECP Printer Port */ | |
2916 | {.id = "PNP0401", .driver_data = 0}, | |
2917 | { } | |
2918 | }; | |
2919 | ||
2920 | MODULE_DEVICE_TABLE(pnp, parport_pc_pnp_tbl); | |
2921 | ||
2922 | static int parport_pc_pnp_probe(struct pnp_dev *dev, | |
2923 | const struct pnp_device_id *id) | |
2924 | { | |
2925 | struct parport *pdata; | |
2926 | unsigned long io_lo, io_hi; | |
2927 | int dma, irq; | |
2928 | ||
2929 | if (pnp_port_valid(dev, 0) && | |
2930 | !(pnp_port_flags(dev, 0) & IORESOURCE_DISABLED)) { | |
2931 | io_lo = pnp_port_start(dev, 0); | |
2932 | } else | |
2933 | return -EINVAL; | |
2934 | ||
2935 | if (pnp_port_valid(dev, 1) && | |
2936 | !(pnp_port_flags(dev, 1) & IORESOURCE_DISABLED)) { | |
2937 | io_hi = pnp_port_start(dev, 1); | |
2938 | } else | |
2939 | io_hi = 0; | |
2940 | ||
2941 | if (pnp_irq_valid(dev, 0) && | |
2942 | !(pnp_irq_flags(dev, 0) & IORESOURCE_DISABLED)) { | |
2943 | irq = pnp_irq(dev, 0); | |
2944 | } else | |
2945 | irq = PARPORT_IRQ_NONE; | |
2946 | ||
2947 | if (pnp_dma_valid(dev, 0) && | |
2948 | !(pnp_dma_flags(dev, 0) & IORESOURCE_DISABLED)) { | |
2949 | dma = pnp_dma(dev, 0); | |
2950 | } else | |
2951 | dma = PARPORT_DMA_NONE; | |
2952 | ||
2953 | dev_info(&dev->dev, "reported by %s\n", dev->protocol->name); | |
2954 | pdata = parport_pc_probe_port(io_lo, io_hi, irq, dma, &dev->dev, 0); | |
2955 | if (pdata == NULL) | |
2956 | return -ENODEV; | |
2957 | ||
2958 | pnp_set_drvdata(dev, pdata); | |
2959 | return 0; | |
2960 | } | |
2961 | ||
2962 | static void parport_pc_pnp_remove(struct pnp_dev *dev) | |
2963 | { | |
2964 | struct parport *pdata = (struct parport *)pnp_get_drvdata(dev); | |
2965 | if (!pdata) | |
2966 | return; | |
2967 | ||
2968 | parport_pc_unregister_port(pdata); | |
2969 | } | |
2970 | ||
2971 | /* we only need the pnp layer to activate the device, at least for now */ | |
2972 | static struct pnp_driver parport_pc_pnp_driver = { | |
2973 | .name = "parport_pc", | |
2974 | .id_table = parport_pc_pnp_tbl, | |
2975 | .probe = parport_pc_pnp_probe, | |
2976 | .remove = parport_pc_pnp_remove, | |
2977 | }; | |
2978 | ||
2979 | #else | |
2980 | static struct pnp_driver parport_pc_pnp_driver; | |
2981 | #endif /* CONFIG_PNP */ | |
2982 | ||
2983 | static int parport_pc_platform_probe(struct platform_device *pdev) | |
2984 | { | |
2985 | /* Always succeed, the actual probing is done in | |
2986 | * parport_pc_probe_port(). */ | |
2987 | return 0; | |
2988 | } | |
2989 | ||
2990 | static struct platform_driver parport_pc_platform_driver = { | |
2991 | .driver = { | |
2992 | .owner = THIS_MODULE, | |
2993 | .name = "parport_pc", | |
2994 | }, | |
2995 | .probe = parport_pc_platform_probe, | |
2996 | }; | |
2997 | ||
2998 | /* This is called by parport_pc_find_nonpci_ports (in asm/parport.h) */ | |
2999 | static int __attribute__((unused)) | |
3000 | parport_pc_find_isa_ports(int autoirq, int autodma) | |
3001 | { | |
3002 | int count = 0; | |
3003 | ||
3004 | if (parport_pc_probe_port(0x3bc, 0x7bc, autoirq, autodma, NULL, 0)) | |
3005 | count++; | |
3006 | if (parport_pc_probe_port(0x378, 0x778, autoirq, autodma, NULL, 0)) | |
3007 | count++; | |
3008 | if (parport_pc_probe_port(0x278, 0x678, autoirq, autodma, NULL, 0)) | |
3009 | count++; | |
3010 | ||
3011 | return count; | |
3012 | } | |
3013 | ||
3014 | /* This function is called by parport_pc_init if the user didn't | |
3015 | * specify any ports to probe. Its job is to find some ports. Order | |
3016 | * is important here -- we want ISA ports to be registered first, | |
3017 | * followed by PCI cards (for least surprise), but before that we want | |
3018 | * to do chipset-specific tests for some onboard ports that we know | |
3019 | * about. | |
3020 | * | |
3021 | * autoirq is PARPORT_IRQ_NONE, PARPORT_IRQ_AUTO, or PARPORT_IRQ_PROBEONLY | |
3022 | * autodma is PARPORT_DMA_NONE or PARPORT_DMA_AUTO | |
3023 | */ | |
3024 | static void __init parport_pc_find_ports(int autoirq, int autodma) | |
3025 | { | |
3026 | int count = 0, err; | |
3027 | ||
3028 | #ifdef CONFIG_PARPORT_PC_SUPERIO | |
3029 | detect_and_report_it87(); | |
3030 | detect_and_report_winbond(); | |
3031 | detect_and_report_smsc(); | |
3032 | #endif | |
3033 | ||
3034 | /* Onboard SuperIO chipsets that show themselves on the PCI bus. */ | |
3035 | count += parport_pc_init_superio(autoirq, autodma); | |
3036 | ||
3037 | /* PnP ports, skip detection if SuperIO already found them */ | |
3038 | if (!count) { | |
3039 | err = pnp_register_driver(&parport_pc_pnp_driver); | |
3040 | if (!err) | |
3041 | pnp_registered_parport = 1; | |
3042 | } | |
3043 | ||
3044 | /* ISA ports and whatever (see asm/parport.h). */ | |
3045 | parport_pc_find_nonpci_ports(autoirq, autodma); | |
3046 | ||
3047 | err = pci_register_driver(&parport_pc_pci_driver); | |
3048 | if (!err) | |
3049 | pci_registered_parport = 1; | |
3050 | } | |
3051 | ||
3052 | /* | |
3053 | * Piles of crap below pretend to be a parser for module and kernel | |
3054 | * parameters. Say "thank you" to whoever had come up with that | |
3055 | * syntax and keep in mind that code below is a cleaned up version. | |
3056 | */ | |
3057 | ||
3058 | static int __initdata io[PARPORT_PC_MAX_PORTS+1] = { | |
3059 | [0 ... PARPORT_PC_MAX_PORTS] = 0 | |
3060 | }; | |
3061 | static int __initdata io_hi[PARPORT_PC_MAX_PORTS+1] = { | |
3062 | [0 ... PARPORT_PC_MAX_PORTS] = PARPORT_IOHI_AUTO | |
3063 | }; | |
3064 | static int __initdata dmaval[PARPORT_PC_MAX_PORTS] = { | |
3065 | [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_DMA_NONE | |
3066 | }; | |
3067 | static int __initdata irqval[PARPORT_PC_MAX_PORTS] = { | |
3068 | [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_IRQ_PROBEONLY | |
3069 | }; | |
3070 | ||
3071 | static int __init parport_parse_param(const char *s, int *val, | |
3072 | int automatic, int none, int nofifo) | |
3073 | { | |
3074 | if (!s) | |
3075 | return 0; | |
3076 | if (!strncmp(s, "auto", 4)) | |
3077 | *val = automatic; | |
3078 | else if (!strncmp(s, "none", 4)) | |
3079 | *val = none; | |
3080 | else if (nofifo && !strncmp(s, "nofifo", 6)) | |
3081 | *val = nofifo; | |
3082 | else { | |
3083 | char *ep; | |
3084 | unsigned long r = simple_strtoul(s, &ep, 0); | |
3085 | if (ep != s) | |
3086 | *val = r; | |
3087 | else { | |
3088 | printk(KERN_ERR "parport: bad specifier `%s'\n", s); | |
3089 | return -1; | |
3090 | } | |
3091 | } | |
3092 | return 0; | |
3093 | } | |
3094 | ||
3095 | static int __init parport_parse_irq(const char *irqstr, int *val) | |
3096 | { | |
3097 | return parport_parse_param(irqstr, val, PARPORT_IRQ_AUTO, | |
3098 | PARPORT_IRQ_NONE, 0); | |
3099 | } | |
3100 | ||
3101 | static int __init parport_parse_dma(const char *dmastr, int *val) | |
3102 | { | |
3103 | return parport_parse_param(dmastr, val, PARPORT_DMA_AUTO, | |
3104 | PARPORT_DMA_NONE, PARPORT_DMA_NOFIFO); | |
3105 | } | |
3106 | ||
3107 | #ifdef CONFIG_PCI | |
3108 | static int __init parport_init_mode_setup(char *str) | |
3109 | { | |
3110 | printk(KERN_DEBUG | |
3111 | "parport_pc.c: Specified parameter parport_init_mode=%s\n", str); | |
3112 | ||
3113 | if (!strcmp(str, "spp")) | |
3114 | parport_init_mode = 1; | |
3115 | if (!strcmp(str, "ps2")) | |
3116 | parport_init_mode = 2; | |
3117 | if (!strcmp(str, "epp")) | |
3118 | parport_init_mode = 3; | |
3119 | if (!strcmp(str, "ecp")) | |
3120 | parport_init_mode = 4; | |
3121 | if (!strcmp(str, "ecpepp")) | |
3122 | parport_init_mode = 5; | |
3123 | return 1; | |
3124 | } | |
3125 | #endif | |
3126 | ||
3127 | #ifdef MODULE | |
3128 | static char *irq[PARPORT_PC_MAX_PORTS]; | |
3129 | static char *dma[PARPORT_PC_MAX_PORTS]; | |
3130 | ||
3131 | MODULE_PARM_DESC(io, "Base I/O address (SPP regs)"); | |
3132 | module_param_array(io, int, NULL, 0); | |
3133 | MODULE_PARM_DESC(io_hi, "Base I/O address (ECR)"); | |
3134 | module_param_array(io_hi, int, NULL, 0); | |
3135 | MODULE_PARM_DESC(irq, "IRQ line"); | |
3136 | module_param_array(irq, charp, NULL, 0); | |
3137 | MODULE_PARM_DESC(dma, "DMA channel"); | |
3138 | module_param_array(dma, charp, NULL, 0); | |
3139 | #if defined(CONFIG_PARPORT_PC_SUPERIO) || \ | |
3140 | (defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO)) | |
3141 | MODULE_PARM_DESC(verbose_probing, "Log chit-chat during initialisation"); | |
3142 | module_param(verbose_probing, int, 0644); | |
3143 | #endif | |
3144 | #ifdef CONFIG_PCI | |
3145 | static char *init_mode; | |
3146 | MODULE_PARM_DESC(init_mode, | |
3147 | "Initialise mode for VIA VT8231 port (spp, ps2, epp, ecp or ecpepp)"); | |
3148 | module_param(init_mode, charp, 0); | |
3149 | #endif | |
3150 | ||
3151 | static int __init parse_parport_params(void) | |
3152 | { | |
3153 | unsigned int i; | |
3154 | int val; | |
3155 | ||
3156 | #ifdef CONFIG_PCI | |
3157 | if (init_mode) | |
3158 | parport_init_mode_setup(init_mode); | |
3159 | #endif | |
3160 | ||
3161 | for (i = 0; i < PARPORT_PC_MAX_PORTS && io[i]; i++) { | |
3162 | if (parport_parse_irq(irq[i], &val)) | |
3163 | return 1; | |
3164 | irqval[i] = val; | |
3165 | if (parport_parse_dma(dma[i], &val)) | |
3166 | return 1; | |
3167 | dmaval[i] = val; | |
3168 | } | |
3169 | if (!io[0]) { | |
3170 | /* The user can make us use any IRQs or DMAs we find. */ | |
3171 | if (irq[0] && !parport_parse_irq(irq[0], &val)) | |
3172 | switch (val) { | |
3173 | case PARPORT_IRQ_NONE: | |
3174 | case PARPORT_IRQ_AUTO: | |
3175 | irqval[0] = val; | |
3176 | break; | |
3177 | default: | |
3178 | printk(KERN_WARNING | |
3179 | "parport_pc: irq specified " | |
3180 | "without base address. Use 'io=' " | |
3181 | "to specify one\n"); | |
3182 | } | |
3183 | ||
3184 | if (dma[0] && !parport_parse_dma(dma[0], &val)) | |
3185 | switch (val) { | |
3186 | case PARPORT_DMA_NONE: | |
3187 | case PARPORT_DMA_AUTO: | |
3188 | dmaval[0] = val; | |
3189 | break; | |
3190 | default: | |
3191 | printk(KERN_WARNING | |
3192 | "parport_pc: dma specified " | |
3193 | "without base address. Use 'io=' " | |
3194 | "to specify one\n"); | |
3195 | } | |
3196 | } | |
3197 | return 0; | |
3198 | } | |
3199 | ||
3200 | #else | |
3201 | ||
3202 | static int parport_setup_ptr __initdata; | |
3203 | ||
3204 | /* | |
3205 | * Acceptable parameters: | |
3206 | * | |
3207 | * parport=0 | |
3208 | * parport=auto | |
3209 | * parport=0xBASE[,IRQ[,DMA]] | |
3210 | * | |
3211 | * IRQ/DMA may be numeric or 'auto' or 'none' | |
3212 | */ | |
3213 | static int __init parport_setup(char *str) | |
3214 | { | |
3215 | char *endptr; | |
3216 | char *sep; | |
3217 | int val; | |
3218 | ||
3219 | if (!str || !*str || (*str == '0' && !*(str+1))) { | |
3220 | /* Disable parport if "parport=0" in cmdline */ | |
3221 | io[0] = PARPORT_DISABLE; | |
3222 | return 1; | |
3223 | } | |
3224 | ||
3225 | if (!strncmp(str, "auto", 4)) { | |
3226 | irqval[0] = PARPORT_IRQ_AUTO; | |
3227 | dmaval[0] = PARPORT_DMA_AUTO; | |
3228 | return 1; | |
3229 | } | |
3230 | ||
3231 | val = simple_strtoul(str, &endptr, 0); | |
3232 | if (endptr == str) { | |
3233 | printk(KERN_WARNING "parport=%s not understood\n", str); | |
3234 | return 1; | |
3235 | } | |
3236 | ||
3237 | if (parport_setup_ptr == PARPORT_PC_MAX_PORTS) { | |
3238 | printk(KERN_ERR "parport=%s ignored, too many ports\n", str); | |
3239 | return 1; | |
3240 | } | |
3241 | ||
3242 | io[parport_setup_ptr] = val; | |
3243 | irqval[parport_setup_ptr] = PARPORT_IRQ_NONE; | |
3244 | dmaval[parport_setup_ptr] = PARPORT_DMA_NONE; | |
3245 | ||
3246 | sep = strchr(str, ','); | |
3247 | if (sep++) { | |
3248 | if (parport_parse_irq(sep, &val)) | |
3249 | return 1; | |
3250 | irqval[parport_setup_ptr] = val; | |
3251 | sep = strchr(sep, ','); | |
3252 | if (sep++) { | |
3253 | if (parport_parse_dma(sep, &val)) | |
3254 | return 1; | |
3255 | dmaval[parport_setup_ptr] = val; | |
3256 | } | |
3257 | } | |
3258 | parport_setup_ptr++; | |
3259 | return 1; | |
3260 | } | |
3261 | ||
3262 | static int __init parse_parport_params(void) | |
3263 | { | |
3264 | return io[0] == PARPORT_DISABLE; | |
3265 | } | |
3266 | ||
3267 | __setup("parport=", parport_setup); | |
3268 | ||
3269 | /* | |
3270 | * Acceptable parameters: | |
3271 | * | |
3272 | * parport_init_mode=[spp|ps2|epp|ecp|ecpepp] | |
3273 | */ | |
3274 | #ifdef CONFIG_PCI | |
3275 | __setup("parport_init_mode=", parport_init_mode_setup); | |
3276 | #endif | |
3277 | #endif | |
3278 | ||
3279 | /* "Parser" ends here */ | |
3280 | ||
3281 | static int __init parport_pc_init(void) | |
3282 | { | |
3283 | int err; | |
3284 | ||
3285 | if (parse_parport_params()) | |
3286 | return -EINVAL; | |
3287 | ||
3288 | err = platform_driver_register(&parport_pc_platform_driver); | |
3289 | if (err) | |
3290 | return err; | |
3291 | ||
3292 | if (io[0]) { | |
3293 | int i; | |
3294 | /* Only probe the ports we were given. */ | |
3295 | user_specified = 1; | |
3296 | for (i = 0; i < PARPORT_PC_MAX_PORTS; i++) { | |
3297 | if (!io[i]) | |
3298 | break; | |
3299 | if (io_hi[i] == PARPORT_IOHI_AUTO) | |
3300 | io_hi[i] = 0x400 + io[i]; | |
3301 | parport_pc_probe_port(io[i], io_hi[i], | |
3302 | irqval[i], dmaval[i], NULL, 0); | |
3303 | } | |
3304 | } else | |
3305 | parport_pc_find_ports(irqval[0], dmaval[0]); | |
3306 | ||
3307 | return 0; | |
3308 | } | |
3309 | ||
3310 | static void __exit parport_pc_exit(void) | |
3311 | { | |
3312 | if (pci_registered_parport) | |
3313 | pci_unregister_driver(&parport_pc_pci_driver); | |
3314 | if (pnp_registered_parport) | |
3315 | pnp_unregister_driver(&parport_pc_pnp_driver); | |
3316 | platform_driver_unregister(&parport_pc_platform_driver); | |
3317 | ||
3318 | while (!list_empty(&ports_list)) { | |
3319 | struct parport_pc_private *priv; | |
3320 | struct parport *port; | |
3321 | priv = list_entry(ports_list.next, | |
3322 | struct parport_pc_private, list); | |
3323 | port = priv->port; | |
3324 | if (port->dev && port->dev->bus == &platform_bus_type) | |
3325 | platform_device_unregister( | |
3326 | to_platform_device(port->dev)); | |
3327 | parport_pc_unregister_port(port); | |
3328 | } | |
3329 | } | |
3330 | ||
3331 | MODULE_AUTHOR("Phil Blundell, Tim Waugh, others"); | |
3332 | MODULE_DESCRIPTION("PC-style parallel port driver"); | |
3333 | MODULE_LICENSE("GPL"); | |
3334 | module_init(parport_pc_init) | |
3335 | module_exit(parport_pc_exit) |