[mirror_ubuntu-artful-kernel.git] / drivers / pinctrl / sh-pfc / gpio.c

/*
 * SuperH Pin Function Controller GPIO driver.
 *
 * Copyright (C) 2008 Magnus Damm
 * Copyright (C) 2009 - 2012 Paul Mundt
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */

#include <linux/device.h>
#include <linux/gpio.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/pinctrl/consumer.h>
#include <linux/slab.h>
#include <linux/spinlock.h>

#include "core.h"

struct sh_pfc_gpio_data_reg {
	const struct pinmux_data_reg *info;
	u32 shadow;
};

struct sh_pfc_gpio_pin {
	u8 dbit;
	u8 dreg;
};

struct sh_pfc_chip {
	struct sh_pfc			*pfc;
	struct gpio_chip		gpio_chip;

	struct sh_pfc_window		*mem;
	struct sh_pfc_gpio_data_reg	*regs;
	struct sh_pfc_gpio_pin		*pins;
};

static struct sh_pfc_chip *gpio_to_pfc_chip(struct gpio_chip *gc)
{
	return container_of(gc, struct sh_pfc_chip, gpio_chip);
}

static struct sh_pfc *gpio_to_pfc(struct gpio_chip *gc)
{
	return gpio_to_pfc_chip(gc)->pfc;
}

static void gpio_get_data_reg(struct sh_pfc_chip *chip, unsigned int offset,
			      struct sh_pfc_gpio_data_reg **reg,
			      unsigned int *bit)
{
	int idx = sh_pfc_get_pin_index(chip->pfc, offset);
	struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[idx];

	*reg = &chip->regs[gpio_pin->dreg];
	*bit = gpio_pin->dbit;
}

static u32 gpio_read_data_reg(struct sh_pfc_chip *chip,
			      const struct pinmux_data_reg *dreg)
{
	phys_addr_t address = dreg->reg;
	void __iomem *mem = address - chip->mem->phys + chip->mem->virt;

	return sh_pfc_read_raw_reg(mem, dreg->reg_width);
}

static void gpio_write_data_reg(struct sh_pfc_chip *chip,
				const struct pinmux_data_reg *dreg, u32 value)
{
	phys_addr_t address = dreg->reg;
	void __iomem *mem = address - chip->mem->phys + chip->mem->virt;

	sh_pfc_write_raw_reg(mem, dreg->reg_width, value);
}

static void gpio_setup_data_reg(struct sh_pfc_chip *chip, unsigned idx)
{
	struct sh_pfc *pfc = chip->pfc;
	struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[idx];
	const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
	const struct pinmux_data_reg *dreg;
	unsigned int bit;
	unsigned int i;

	for (i = 0, dreg = pfc->info->data_regs; dreg->reg_width; ++i, ++dreg) {
		for (bit = 0; bit < dreg->reg_width; bit++) {
			if (dreg->enum_ids[bit] == pin->enum_id) {
				gpio_pin->dreg = i;
				gpio_pin->dbit = bit;
				return;
			}
		}
	}

	BUG();
}

static int gpio_setup_data_regs(struct sh_pfc_chip *chip)
{
	struct sh_pfc *pfc = chip->pfc;
	const struct pinmux_data_reg *dreg;
	unsigned int i;

	/* Count the number of data registers, allocate memory and initialize
	 * them.
	 */
	for (i = 0; pfc->info->data_regs[i].reg_width; ++i)
		;

	chip->regs = devm_kzalloc(pfc->dev, i * sizeof(*chip->regs),
				  GFP_KERNEL);
	if (chip->regs == NULL)
		return -ENOMEM;

	for (i = 0, dreg = pfc->info->data_regs; dreg->reg_width; ++i, ++dreg) {
		chip->regs[i].info = dreg;
		chip->regs[i].shadow = gpio_read_data_reg(chip, dreg);
	}

	for (i = 0; i < pfc->info->nr_pins; i++) {
		if (pfc->info->pins[i].enum_id == 0)
			continue;

		gpio_setup_data_reg(chip, i);
	}

	return 0;
}

/* -----------------------------------------------------------------------------
 * Pin GPIOs
 */

static int gpio_pin_request(struct gpio_chip *gc, unsigned offset)
{
	struct sh_pfc *pfc = gpio_to_pfc(gc);
	int idx = sh_pfc_get_pin_index(pfc, offset);

	if (idx < 0 || pfc->info->pins[idx].enum_id == 0)
		return -EINVAL;

	return pinctrl_request_gpio(offset);
}

static void gpio_pin_free(struct gpio_chip *gc, unsigned offset)
{
	return pinctrl_free_gpio(offset);
}

static void gpio_pin_set_value(struct sh_pfc_chip *chip, unsigned offset,
			       int value)
{
	struct sh_pfc_gpio_data_reg *reg;
	unsigned int bit;
	unsigned int pos;

	gpio_get_data_reg(chip, offset, &reg, &bit);

	pos = reg->info->reg_width - (bit + 1);

	if (value)
		reg->shadow |= BIT(pos);
	else
		reg->shadow &= ~BIT(pos);

	gpio_write_data_reg(chip, reg->info, reg->shadow);
}

static int gpio_pin_direction_input(struct gpio_chip *gc, unsigned offset)
{
	return pinctrl_gpio_direction_input(offset);
}

static int gpio_pin_direction_output(struct gpio_chip *gc, unsigned offset,
				    int value)
{
	gpio_pin_set_value(gpio_to_pfc_chip(gc), offset, value);

	return pinctrl_gpio_direction_output(offset);
}

static int gpio_pin_get(struct gpio_chip *gc, unsigned offset)
{
	struct sh_pfc_chip *chip = gpio_to_pfc_chip(gc);
	struct sh_pfc_gpio_data_reg *reg;
	unsigned int bit;
	unsigned int pos;

	gpio_get_data_reg(chip, offset, &reg, &bit);

	pos = reg->info->reg_width - (bit + 1);

	return (gpio_read_data_reg(chip, reg->info) >> pos) & 1;
}

static void gpio_pin_set(struct gpio_chip *gc, unsigned offset, int value)
{
	gpio_pin_set_value(gpio_to_pfc_chip(gc), offset, value);
}

static int gpio_pin_to_irq(struct gpio_chip *gc, unsigned offset)
{
	struct sh_pfc *pfc = gpio_to_pfc(gc);
	unsigned int i, k;

	for (i = 0; i < pfc->info->gpio_irq_size; i++) {
		const short *gpios = pfc->info->gpio_irq[i].gpios;

		for (k = 0; gpios[k] >= 0; k++) {
			if (gpios[k] == offset)
				goto found;
		}
	}

	return -ENOSYS;

found:
	if (pfc->num_irqs)
		return pfc->irqs[i];
	else
		return pfc->info->gpio_irq[i].irq;
}

static int gpio_pin_setup(struct sh_pfc_chip *chip)
{
	struct sh_pfc *pfc = chip->pfc;
	struct gpio_chip *gc = &chip->gpio_chip;
	int ret;

	chip->pins = devm_kzalloc(pfc->dev, pfc->info->nr_pins *
				  sizeof(*chip->pins), GFP_KERNEL);
	if (chip->pins == NULL)
		return -ENOMEM;

	ret = gpio_setup_data_regs(chip);
	if (ret < 0)
		return ret;

	gc->request = gpio_pin_request;
	gc->free = gpio_pin_free;
	gc->direction_input = gpio_pin_direction_input;
	gc->get = gpio_pin_get;
	gc->direction_output = gpio_pin_direction_output;
	gc->set = gpio_pin_set;
	gc->to_irq = gpio_pin_to_irq;

	gc->label = pfc->info->name;
	gc->dev = pfc->dev;
	gc->owner = THIS_MODULE;
	gc->base = 0;
	gc->ngpio = pfc->nr_gpio_pins;

	return 0;
}

/* -----------------------------------------------------------------------------
 * Function GPIOs
 */

static int gpio_function_request(struct gpio_chip *gc, unsigned offset)
{
	static bool __print_once;
	struct sh_pfc *pfc = gpio_to_pfc(gc);
	unsigned int mark = pfc->info->func_gpios[offset].enum_id;
	unsigned long flags;
	int ret;

	if (!__print_once) {
		dev_notice(pfc->dev,
			   "Use of GPIO API for function requests is deprecated."
			   " Convert to pinctrl\n");
		__print_once = true;
	}

	if (mark == 0)
		return -EINVAL;

	spin_lock_irqsave(&pfc->lock, flags);
	ret = sh_pfc_config_mux(pfc, mark, PINMUX_TYPE_FUNCTION);
	spin_unlock_irqrestore(&pfc->lock, flags);

	return ret;
}

static void gpio_function_free(struct gpio_chip *gc, unsigned offset)
{
}

static int gpio_function_setup(struct sh_pfc_chip *chip)
{
	struct sh_pfc *pfc = chip->pfc;
	struct gpio_chip *gc = &chip->gpio_chip;

	gc->request = gpio_function_request;
	gc->free = gpio_function_free;

	gc->label = pfc->info->name;
	gc->owner = THIS_MODULE;
	gc->base = pfc->nr_gpio_pins;
	gc->ngpio = pfc->info->nr_func_gpios;

	return 0;
}

/* -----------------------------------------------------------------------------
 * Register/unregister
 */

static struct sh_pfc_chip *
sh_pfc_add_gpiochip(struct sh_pfc *pfc, int(*setup)(struct sh_pfc_chip *),
		    struct sh_pfc_window *mem)
{
	struct sh_pfc_chip *chip;
	int ret;

	chip = devm_kzalloc(pfc->dev, sizeof(*chip), GFP_KERNEL);
	if (unlikely(!chip))
		return ERR_PTR(-ENOMEM);

	chip->mem = mem;
	chip->pfc = pfc;

	ret = setup(chip);
	if (ret < 0)
		return ERR_PTR(ret);

	ret = gpiochip_add(&chip->gpio_chip);
	if (unlikely(ret < 0))
		return ERR_PTR(ret);

	dev_info(pfc->dev, "%s handling gpio %u -> %u\n",
		 chip->gpio_chip.label, chip->gpio_chip.base,
		 chip->gpio_chip.base + chip->gpio_chip.ngpio - 1);

	return chip;
}

int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
{
	struct sh_pfc_chip *chip;
	phys_addr_t address;
	unsigned int i;
	int ret;

	if (pfc->info->data_regs == NULL)
		return 0;

	/* Find the memory window that contain the GPIO registers. Boards that
	 * register a separate GPIO device will not supply a memory resource
	 * that covers the data registers. In that case don't try to handle
	 * GPIOs.
	 */
	address = pfc->info->data_regs[0].reg;
	for (i = 0; i < pfc->num_windows; ++i) {
		struct sh_pfc_window *window = &pfc->windows[i];

		if (address >= window->phys &&
		    address < window->phys + window->size)
			break;
	}

	if (i == pfc->num_windows)
		return 0;

	/* If we have IRQ resources make sure their number is correct. */
	if (pfc->num_irqs && pfc->num_irqs != pfc->info->gpio_irq_size) {
		dev_err(pfc->dev, "invalid number of IRQ resources\n");
		return -EINVAL;
	}

	/* Register the real GPIOs chip. */
	chip = sh_pfc_add_gpiochip(pfc, gpio_pin_setup, &pfc->windows[i]);
	if (IS_ERR(chip))
		return PTR_ERR(chip);

	pfc->gpio = chip;

	/* Register the GPIO to pin mappings. As pins with GPIO ports must come
	 * first in the ranges, skip the pins without GPIO ports by stopping at
	 * the first range that contains such a pin.
	 */
	for (i = 0; i < pfc->nr_ranges; ++i) {
		const struct sh_pfc_pin_range *range = &pfc->ranges[i];

		if (range->start >= pfc->nr_gpio_pins)
			break;

		ret = gpiochip_add_pin_range(&chip->gpio_chip,
					     dev_name(pfc->dev),
					     range->start, range->start,
					     range->end - range->start + 1);
		if (ret < 0)
			return ret;
	}

	/* Register the function GPIOs chip. */
	if (pfc->info->nr_func_gpios == 0)
		return 0;

	chip = sh_pfc_add_gpiochip(pfc, gpio_function_setup, NULL);
	if (IS_ERR(chip))
		return PTR_ERR(chip);

	pfc->func = chip;

	return 0;
}

int sh_pfc_unregister_gpiochip(struct sh_pfc *pfc)
{
	gpiochip_remove(&pfc->gpio->gpio_chip);
	gpiochip_remove(&pfc->func->gpio_chip);

	return 0;
}
Commit	Line	Data
	1	/*
	2	* SuperH Pin Function Controller GPIO driver.
	3	*
	4	* Copyright (C) 2008 Magnus Damm
	5	* Copyright (C) 2009 - 2012 Paul Mundt
	6	*
	7	* This file is subject to the terms and conditions of the GNU General Public
	8	* License. See the file "COPYING" in the main directory of this archive
	9	* for more details.
	10	*/
	11
	12	#include <linux/device.h>
	13	#include <linux/gpio.h>
	14	#include <linux/init.h>
	15	#include <linux/module.h>
	16	#include <linux/pinctrl/consumer.h>
	17	#include <linux/slab.h>
	18	#include <linux/spinlock.h>
	19
	20	#include "core.h"
	21
	22	struct sh_pfc_gpio_data_reg {
	23	const struct pinmux_data_reg *info;
	24	u32 shadow;
	25	};
	26
	27	struct sh_pfc_gpio_pin {
	28	u8 dbit;
	29	u8 dreg;
	30	};
	31
	32	struct sh_pfc_chip {
	33	struct sh_pfc *pfc;
	34	struct gpio_chip gpio_chip;
	35
	36	struct sh_pfc_window *mem;
	37	struct sh_pfc_gpio_data_reg *regs;
	38	struct sh_pfc_gpio_pin *pins;
	39	};
	40
	41	static struct sh_pfc_chip gpio_to_pfc_chip(struct gpio_chip gc)
	42	{
	43	return container_of(gc, struct sh_pfc_chip, gpio_chip);
	44	}
	45
	46	static struct sh_pfc gpio_to_pfc(struct gpio_chip gc)
	47	{
	48	return gpio_to_pfc_chip(gc)->pfc;
	49	}
	50
	51	static void gpio_get_data_reg(struct sh_pfc_chip *chip, unsigned int offset,
	52	struct sh_pfc_gpio_data_reg **reg,
	53	unsigned int *bit)
	54	{
	55	int idx = sh_pfc_get_pin_index(chip->pfc, offset);
	56	struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[idx];
	57
	58	*reg = &chip->regs[gpio_pin->dreg];
	59	*bit = gpio_pin->dbit;
	60	}
	61
	62	static u32 gpio_read_data_reg(struct sh_pfc_chip *chip,
	63	const struct pinmux_data_reg *dreg)
	64	{
	65	phys_addr_t address = dreg->reg;
	66	void __iomem *mem = address - chip->mem->phys + chip->mem->virt;
	67
	68	return sh_pfc_read_raw_reg(mem, dreg->reg_width);
	69	}
	70
	71	static void gpio_write_data_reg(struct sh_pfc_chip *chip,
	72	const struct pinmux_data_reg *dreg, u32 value)
	73	{
	74	phys_addr_t address = dreg->reg;
	75	void __iomem *mem = address - chip->mem->phys + chip->mem->virt;
	76
	77	sh_pfc_write_raw_reg(mem, dreg->reg_width, value);
	78	}
	79
	80	static void gpio_setup_data_reg(struct sh_pfc_chip *chip, unsigned idx)
	81	{
	82	struct sh_pfc *pfc = chip->pfc;
	83	struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[idx];
	84	const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
	85	const struct pinmux_data_reg *dreg;
	86	unsigned int bit;
	87	unsigned int i;
	88
	89	for (i = 0, dreg = pfc->info->data_regs; dreg->reg_width; ++i, ++dreg) {
	90	for (bit = 0; bit < dreg->reg_width; bit++) {
	91	if (dreg->enum_ids[bit] == pin->enum_id) {
	92	gpio_pin->dreg = i;
	93	gpio_pin->dbit = bit;
	94	return;
	95	}
	96	}
	97	}
	98
	99	BUG();
	100	}
	101
	102	static int gpio_setup_data_regs(struct sh_pfc_chip *chip)
	103	{
	104	struct sh_pfc *pfc = chip->pfc;
	105	const struct pinmux_data_reg *dreg;
	106	unsigned int i;
	107
	108	/* Count the number of data registers, allocate memory and initialize
	109	* them.
	110	*/
	111	for (i = 0; pfc->info->data_regs[i].reg_width; ++i)
	112	;
	113
	114	chip->regs = devm_kzalloc(pfc->dev, i * sizeof(*chip->regs),
	115	GFP_KERNEL);
	116	if (chip->regs == NULL)
	117	return -ENOMEM;
	118
	119	for (i = 0, dreg = pfc->info->data_regs; dreg->reg_width; ++i, ++dreg) {
	120	chip->regs[i].info = dreg;
	121	chip->regs[i].shadow = gpio_read_data_reg(chip, dreg);
	122	}
	123
	124	for (i = 0; i < pfc->info->nr_pins; i++) {
	125	if (pfc->info->pins[i].enum_id == 0)
	126	continue;
	127
	128	gpio_setup_data_reg(chip, i);
	129	}
	130
	131	return 0;
	132	}
	133
	134	/* -----------------------------------------------------------------------------
	135	* Pin GPIOs
	136	*/
	137
	138	static int gpio_pin_request(struct gpio_chip *gc, unsigned offset)
	139	{
	140	struct sh_pfc *pfc = gpio_to_pfc(gc);
	141	int idx = sh_pfc_get_pin_index(pfc, offset);
	142
	143	if (idx < 0 \|\| pfc->info->pins[idx].enum_id == 0)
	144	return -EINVAL;
	145
	146	return pinctrl_request_gpio(offset);
	147	}
	148
	149	static void gpio_pin_free(struct gpio_chip *gc, unsigned offset)
	150	{
	151	return pinctrl_free_gpio(offset);
	152	}
	153
	154	static void gpio_pin_set_value(struct sh_pfc_chip *chip, unsigned offset,
	155	int value)
	156	{
	157	struct sh_pfc_gpio_data_reg *reg;
	158	unsigned int bit;
	159	unsigned int pos;
	160
	161	gpio_get_data_reg(chip, offset, &reg, &bit);
	162
	163	pos = reg->info->reg_width - (bit + 1);
	164
	165	if (value)
	166	reg->shadow \|= BIT(pos);
	167	else
	168	reg->shadow &= ~BIT(pos);
	169
	170	gpio_write_data_reg(chip, reg->info, reg->shadow);
	171	}
	172
	173	static int gpio_pin_direction_input(struct gpio_chip *gc, unsigned offset)
	174	{
	175	return pinctrl_gpio_direction_input(offset);
	176	}
	177
	178	static int gpio_pin_direction_output(struct gpio_chip *gc, unsigned offset,
	179	int value)
	180	{
	181	gpio_pin_set_value(gpio_to_pfc_chip(gc), offset, value);
	182
	183	return pinctrl_gpio_direction_output(offset);
	184	}
	185
	186	static int gpio_pin_get(struct gpio_chip *gc, unsigned offset)
	187	{
	188	struct sh_pfc_chip *chip = gpio_to_pfc_chip(gc);
	189	struct sh_pfc_gpio_data_reg *reg;
	190	unsigned int bit;
	191	unsigned int pos;
	192
	193	gpio_get_data_reg(chip, offset, &reg, &bit);
	194
	195	pos = reg->info->reg_width - (bit + 1);
	196
	197	return (gpio_read_data_reg(chip, reg->info) >> pos) & 1;
	198	}
	199
	200	static void gpio_pin_set(struct gpio_chip *gc, unsigned offset, int value)
	201	{
	202	gpio_pin_set_value(gpio_to_pfc_chip(gc), offset, value);
	203	}
	204
	205	static int gpio_pin_to_irq(struct gpio_chip *gc, unsigned offset)
	206	{
	207	struct sh_pfc *pfc = gpio_to_pfc(gc);
	208	unsigned int i, k;
	209
	210	for (i = 0; i < pfc->info->gpio_irq_size; i++) {
	211	const short *gpios = pfc->info->gpio_irq[i].gpios;
	212
	213	for (k = 0; gpios[k] >= 0; k++) {
	214	if (gpios[k] == offset)
	215	goto found;
	216	}
	217	}
	218
	219	return -ENOSYS;
	220
	221	found:
	222	if (pfc->num_irqs)
	223	return pfc->irqs[i];
	224	else
	225	return pfc->info->gpio_irq[i].irq;
	226	}
	227
	228	static int gpio_pin_setup(struct sh_pfc_chip *chip)
	229	{
	230	struct sh_pfc *pfc = chip->pfc;
	231	struct gpio_chip *gc = &chip->gpio_chip;
	232	int ret;
	233
	234	chip->pins = devm_kzalloc(pfc->dev, pfc->info->nr_pins *
	235	sizeof(*chip->pins), GFP_KERNEL);
	236	if (chip->pins == NULL)
	237	return -ENOMEM;
	238
	239	ret = gpio_setup_data_regs(chip);
	240	if (ret < 0)
	241	return ret;
	242
	243	gc->request = gpio_pin_request;
	244	gc->free = gpio_pin_free;
	245	gc->direction_input = gpio_pin_direction_input;
	246	gc->get = gpio_pin_get;
	247	gc->direction_output = gpio_pin_direction_output;
	248	gc->set = gpio_pin_set;
	249	gc->to_irq = gpio_pin_to_irq;
	250
	251	gc->label = pfc->info->name;
	252	gc->dev = pfc->dev;
	253	gc->owner = THIS_MODULE;
	254	gc->base = 0;
	255	gc->ngpio = pfc->nr_gpio_pins;
	256
	257	return 0;
	258	}
	259
	260	/* -----------------------------------------------------------------------------
	261	* Function GPIOs
	262	*/
	263
	264	static int gpio_function_request(struct gpio_chip *gc, unsigned offset)
	265	{
	266	static bool __print_once;
	267	struct sh_pfc *pfc = gpio_to_pfc(gc);
	268	unsigned int mark = pfc->info->func_gpios[offset].enum_id;
	269	unsigned long flags;
	270	int ret;
	271
	272	if (!__print_once) {
	273	dev_notice(pfc->dev,
	274	"Use of GPIO API for function requests is deprecated."
	275	" Convert to pinctrl\n");
	276	__print_once = true;
	277	}
	278
	279	if (mark == 0)
	280	return -EINVAL;
	281
	282	spin_lock_irqsave(&pfc->lock, flags);
	283	ret = sh_pfc_config_mux(pfc, mark, PINMUX_TYPE_FUNCTION);
	284	spin_unlock_irqrestore(&pfc->lock, flags);
	285
	286	return ret;
	287	}
	288
	289	static void gpio_function_free(struct gpio_chip *gc, unsigned offset)
	290	{
	291	}
	292
	293	static int gpio_function_setup(struct sh_pfc_chip *chip)
	294	{
	295	struct sh_pfc *pfc = chip->pfc;
	296	struct gpio_chip *gc = &chip->gpio_chip;
	297
	298	gc->request = gpio_function_request;
	299	gc->free = gpio_function_free;
	300
	301	gc->label = pfc->info->name;
	302	gc->owner = THIS_MODULE;
	303	gc->base = pfc->nr_gpio_pins;
	304	gc->ngpio = pfc->info->nr_func_gpios;
	305
	306	return 0;
	307	}
	308
	309	/* -----------------------------------------------------------------------------
	310	* Register/unregister
	311	*/
	312
	313	static struct sh_pfc_chip *
	314	sh_pfc_add_gpiochip(struct sh_pfc pfc, int(setup)(struct sh_pfc_chip *),
	315	struct sh_pfc_window *mem)
	316	{
	317	struct sh_pfc_chip *chip;
	318	int ret;
	319
	320	chip = devm_kzalloc(pfc->dev, sizeof(*chip), GFP_KERNEL);
	321	if (unlikely(!chip))
	322	return ERR_PTR(-ENOMEM);
	323
	324	chip->mem = mem;
	325	chip->pfc = pfc;
	326
	327	ret = setup(chip);
	328	if (ret < 0)
	329	return ERR_PTR(ret);
	330
	331	ret = gpiochip_add(&chip->gpio_chip);
	332	if (unlikely(ret < 0))
	333	return ERR_PTR(ret);
	334
	335	dev_info(pfc->dev, "%s handling gpio %u -> %u\n",
	336	chip->gpio_chip.label, chip->gpio_chip.base,
	337	chip->gpio_chip.base + chip->gpio_chip.ngpio - 1);
	338
	339	return chip;
	340	}
	341
	342	int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
	343	{
	344	struct sh_pfc_chip *chip;
	345	phys_addr_t address;
	346	unsigned int i;
	347	int ret;
	348
	349	if (pfc->info->data_regs == NULL)
	350	return 0;
	351
	352	/* Find the memory window that contain the GPIO registers. Boards that
	353	* register a separate GPIO device will not supply a memory resource
	354	* that covers the data registers. In that case don't try to handle
	355	* GPIOs.
	356	*/
	357	address = pfc->info->data_regs[0].reg;
	358	for (i = 0; i < pfc->num_windows; ++i) {
	359	struct sh_pfc_window *window = &pfc->windows[i];
	360
	361	if (address >= window->phys &&
	362	address < window->phys + window->size)
	363	break;
	364	}
	365
	366	if (i == pfc->num_windows)
	367	return 0;
	368
	369	/* If we have IRQ resources make sure their number is correct. */
	370	if (pfc->num_irqs && pfc->num_irqs != pfc->info->gpio_irq_size) {
	371	dev_err(pfc->dev, "invalid number of IRQ resources\n");
	372	return -EINVAL;
	373	}
	374
	375	/* Register the real GPIOs chip. */
	376	chip = sh_pfc_add_gpiochip(pfc, gpio_pin_setup, &pfc->windows[i]);
	377	if (IS_ERR(chip))
	378	return PTR_ERR(chip);
	379
	380	pfc->gpio = chip;
	381
	382	/* Register the GPIO to pin mappings. As pins with GPIO ports must come
	383	* first in the ranges, skip the pins without GPIO ports by stopping at
	384	* the first range that contains such a pin.
	385	*/
	386	for (i = 0; i < pfc->nr_ranges; ++i) {
	387	const struct sh_pfc_pin_range *range = &pfc->ranges[i];
	388
	389	if (range->start >= pfc->nr_gpio_pins)
	390	break;
	391
	392	ret = gpiochip_add_pin_range(&chip->gpio_chip,
	393	dev_name(pfc->dev),
	394	range->start, range->start,
	395	range->end - range->start + 1);
	396	if (ret < 0)
	397	return ret;
	398	}
	399
	400	/* Register the function GPIOs chip. */
	401	if (pfc->info->nr_func_gpios == 0)
	402	return 0;
	403
	404	chip = sh_pfc_add_gpiochip(pfc, gpio_function_setup, NULL);
	405	if (IS_ERR(chip))
	406	return PTR_ERR(chip);
	407
	408	pfc->func = chip;
	409
	410	return 0;
	411	}
	412
	413	int sh_pfc_unregister_gpiochip(struct sh_pfc *pfc)
	414	{
	415	gpiochip_remove(&pfc->gpio->gpio_chip);
	416	gpiochip_remove(&pfc->func->gpio_chip);
	417
	418	return 0;
	419	}