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1 | // SPDX-License-Identifier: GPL-2.0 | |
2 | /* | |
3 | * R-Mobile TPU PWM driver | |
4 | * | |
5 | * Copyright (C) 2012 Renesas Solutions Corp. | |
6 | */ | |
7 | ||
8 | #include <linux/clk.h> | |
9 | #include <linux/err.h> | |
10 | #include <linux/io.h> | |
11 | #include <linux/init.h> | |
12 | #include <linux/ioport.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/mutex.h> | |
15 | #include <linux/of.h> | |
16 | #include <linux/platform_device.h> | |
17 | #include <linux/pm_runtime.h> | |
18 | #include <linux/pwm.h> | |
19 | #include <linux/slab.h> | |
20 | #include <linux/spinlock.h> | |
21 | ||
22 | #define TPU_CHANNEL_MAX 4 | |
23 | ||
24 | #define TPU_TSTR 0x00 /* Timer start register (shared) */ | |
25 | ||
26 | #define TPU_TCRn 0x00 /* Timer control register */ | |
27 | #define TPU_TCR_CCLR_NONE (0 << 5) | |
28 | #define TPU_TCR_CCLR_TGRA (1 << 5) | |
29 | #define TPU_TCR_CCLR_TGRB (2 << 5) | |
30 | #define TPU_TCR_CCLR_TGRC (5 << 5) | |
31 | #define TPU_TCR_CCLR_TGRD (6 << 5) | |
32 | #define TPU_TCR_CKEG_RISING (0 << 3) | |
33 | #define TPU_TCR_CKEG_FALLING (1 << 3) | |
34 | #define TPU_TCR_CKEG_BOTH (2 << 3) | |
35 | #define TPU_TMDRn 0x04 /* Timer mode register */ | |
36 | #define TPU_TMDR_BFWT (1 << 6) | |
37 | #define TPU_TMDR_BFB (1 << 5) | |
38 | #define TPU_TMDR_BFA (1 << 4) | |
39 | #define TPU_TMDR_MD_NORMAL (0 << 0) | |
40 | #define TPU_TMDR_MD_PWM (2 << 0) | |
41 | #define TPU_TIORn 0x08 /* Timer I/O control register */ | |
42 | #define TPU_TIOR_IOA_0 (0 << 0) | |
43 | #define TPU_TIOR_IOA_0_CLR (1 << 0) | |
44 | #define TPU_TIOR_IOA_0_SET (2 << 0) | |
45 | #define TPU_TIOR_IOA_0_TOGGLE (3 << 0) | |
46 | #define TPU_TIOR_IOA_1 (4 << 0) | |
47 | #define TPU_TIOR_IOA_1_CLR (5 << 0) | |
48 | #define TPU_TIOR_IOA_1_SET (6 << 0) | |
49 | #define TPU_TIOR_IOA_1_TOGGLE (7 << 0) | |
50 | #define TPU_TIERn 0x0c /* Timer interrupt enable register */ | |
51 | #define TPU_TSRn 0x10 /* Timer status register */ | |
52 | #define TPU_TCNTn 0x14 /* Timer counter */ | |
53 | #define TPU_TGRAn 0x18 /* Timer general register A */ | |
54 | #define TPU_TGRBn 0x1c /* Timer general register B */ | |
55 | #define TPU_TGRCn 0x20 /* Timer general register C */ | |
56 | #define TPU_TGRDn 0x24 /* Timer general register D */ | |
57 | ||
58 | #define TPU_CHANNEL_OFFSET 0x10 | |
59 | #define TPU_CHANNEL_SIZE 0x40 | |
60 | ||
61 | enum tpu_pin_state { | |
62 | TPU_PIN_INACTIVE, /* Pin is driven inactive */ | |
63 | TPU_PIN_PWM, /* Pin is driven by PWM */ | |
64 | TPU_PIN_ACTIVE, /* Pin is driven active */ | |
65 | }; | |
66 | ||
67 | struct tpu_device; | |
68 | ||
69 | struct tpu_pwm_device { | |
70 | bool timer_on; /* Whether the timer is running */ | |
71 | ||
72 | struct tpu_device *tpu; | |
73 | unsigned int channel; /* Channel number in the TPU */ | |
74 | ||
75 | enum pwm_polarity polarity; | |
76 | unsigned int prescaler; | |
77 | u16 period; | |
78 | u16 duty; | |
79 | }; | |
80 | ||
81 | struct tpu_device { | |
82 | struct platform_device *pdev; | |
83 | struct pwm_chip chip; | |
84 | spinlock_t lock; | |
85 | ||
86 | void __iomem *base; | |
87 | struct clk *clk; | |
88 | }; | |
89 | ||
90 | #define to_tpu_device(c) container_of(c, struct tpu_device, chip) | |
91 | ||
92 | static void tpu_pwm_write(struct tpu_pwm_device *pwm, int reg_nr, u16 value) | |
93 | { | |
94 | void __iomem *base = pwm->tpu->base + TPU_CHANNEL_OFFSET | |
95 | + pwm->channel * TPU_CHANNEL_SIZE; | |
96 | ||
97 | iowrite16(value, base + reg_nr); | |
98 | } | |
99 | ||
100 | static void tpu_pwm_set_pin(struct tpu_pwm_device *pwm, | |
101 | enum tpu_pin_state state) | |
102 | { | |
103 | static const char * const states[] = { "inactive", "PWM", "active" }; | |
104 | ||
105 | dev_dbg(&pwm->tpu->pdev->dev, "%u: configuring pin as %s\n", | |
106 | pwm->channel, states[state]); | |
107 | ||
108 | switch (state) { | |
109 | case TPU_PIN_INACTIVE: | |
110 | tpu_pwm_write(pwm, TPU_TIORn, | |
111 | pwm->polarity == PWM_POLARITY_INVERSED ? | |
112 | TPU_TIOR_IOA_1 : TPU_TIOR_IOA_0); | |
113 | break; | |
114 | case TPU_PIN_PWM: | |
115 | tpu_pwm_write(pwm, TPU_TIORn, | |
116 | pwm->polarity == PWM_POLARITY_INVERSED ? | |
117 | TPU_TIOR_IOA_0_SET : TPU_TIOR_IOA_1_CLR); | |
118 | break; | |
119 | case TPU_PIN_ACTIVE: | |
120 | tpu_pwm_write(pwm, TPU_TIORn, | |
121 | pwm->polarity == PWM_POLARITY_INVERSED ? | |
122 | TPU_TIOR_IOA_0 : TPU_TIOR_IOA_1); | |
123 | break; | |
124 | } | |
125 | } | |
126 | ||
127 | static void tpu_pwm_start_stop(struct tpu_pwm_device *pwm, int start) | |
128 | { | |
129 | unsigned long flags; | |
130 | u16 value; | |
131 | ||
132 | spin_lock_irqsave(&pwm->tpu->lock, flags); | |
133 | value = ioread16(pwm->tpu->base + TPU_TSTR); | |
134 | ||
135 | if (start) | |
136 | value |= 1 << pwm->channel; | |
137 | else | |
138 | value &= ~(1 << pwm->channel); | |
139 | ||
140 | iowrite16(value, pwm->tpu->base + TPU_TSTR); | |
141 | spin_unlock_irqrestore(&pwm->tpu->lock, flags); | |
142 | } | |
143 | ||
144 | static int tpu_pwm_timer_start(struct tpu_pwm_device *pwm) | |
145 | { | |
146 | int ret; | |
147 | ||
148 | if (!pwm->timer_on) { | |
149 | /* Wake up device and enable clock. */ | |
150 | pm_runtime_get_sync(&pwm->tpu->pdev->dev); | |
151 | ret = clk_prepare_enable(pwm->tpu->clk); | |
152 | if (ret) { | |
153 | dev_err(&pwm->tpu->pdev->dev, "cannot enable clock\n"); | |
154 | return ret; | |
155 | } | |
156 | pwm->timer_on = true; | |
157 | } | |
158 | ||
159 | /* | |
160 | * Make sure the channel is stopped, as we need to reconfigure it | |
161 | * completely. First drive the pin to the inactive state to avoid | |
162 | * glitches. | |
163 | */ | |
164 | tpu_pwm_set_pin(pwm, TPU_PIN_INACTIVE); | |
165 | tpu_pwm_start_stop(pwm, false); | |
166 | ||
167 | /* | |
168 | * - Clear TCNT on TGRB match | |
169 | * - Count on rising edge | |
170 | * - Set prescaler | |
171 | * - Output 0 until TGRA, output 1 until TGRB (active low polarity) | |
172 | * - Output 1 until TGRA, output 0 until TGRB (active high polarity | |
173 | * - PWM mode | |
174 | */ | |
175 | tpu_pwm_write(pwm, TPU_TCRn, TPU_TCR_CCLR_TGRB | TPU_TCR_CKEG_RISING | | |
176 | pwm->prescaler); | |
177 | tpu_pwm_write(pwm, TPU_TMDRn, TPU_TMDR_MD_PWM); | |
178 | tpu_pwm_set_pin(pwm, TPU_PIN_PWM); | |
179 | tpu_pwm_write(pwm, TPU_TGRAn, pwm->duty); | |
180 | tpu_pwm_write(pwm, TPU_TGRBn, pwm->period); | |
181 | ||
182 | dev_dbg(&pwm->tpu->pdev->dev, "%u: TGRA 0x%04x TGRB 0x%04x\n", | |
183 | pwm->channel, pwm->duty, pwm->period); | |
184 | ||
185 | /* Start the channel. */ | |
186 | tpu_pwm_start_stop(pwm, true); | |
187 | ||
188 | return 0; | |
189 | } | |
190 | ||
191 | static void tpu_pwm_timer_stop(struct tpu_pwm_device *pwm) | |
192 | { | |
193 | if (!pwm->timer_on) | |
194 | return; | |
195 | ||
196 | /* Disable channel. */ | |
197 | tpu_pwm_start_stop(pwm, false); | |
198 | ||
199 | /* Stop clock and mark device as idle. */ | |
200 | clk_disable_unprepare(pwm->tpu->clk); | |
201 | pm_runtime_put(&pwm->tpu->pdev->dev); | |
202 | ||
203 | pwm->timer_on = false; | |
204 | } | |
205 | ||
206 | /* ----------------------------------------------------------------------------- | |
207 | * PWM API | |
208 | */ | |
209 | ||
210 | static int tpu_pwm_request(struct pwm_chip *chip, struct pwm_device *_pwm) | |
211 | { | |
212 | struct tpu_device *tpu = to_tpu_device(chip); | |
213 | struct tpu_pwm_device *pwm; | |
214 | ||
215 | if (_pwm->hwpwm >= TPU_CHANNEL_MAX) | |
216 | return -EINVAL; | |
217 | ||
218 | pwm = kzalloc(sizeof(*pwm), GFP_KERNEL); | |
219 | if (pwm == NULL) | |
220 | return -ENOMEM; | |
221 | ||
222 | pwm->tpu = tpu; | |
223 | pwm->channel = _pwm->hwpwm; | |
224 | pwm->polarity = PWM_POLARITY_NORMAL; | |
225 | pwm->prescaler = 0; | |
226 | pwm->period = 0; | |
227 | pwm->duty = 0; | |
228 | ||
229 | pwm->timer_on = false; | |
230 | ||
231 | pwm_set_chip_data(_pwm, pwm); | |
232 | ||
233 | return 0; | |
234 | } | |
235 | ||
236 | static void tpu_pwm_free(struct pwm_chip *chip, struct pwm_device *_pwm) | |
237 | { | |
238 | struct tpu_pwm_device *pwm = pwm_get_chip_data(_pwm); | |
239 | ||
240 | tpu_pwm_timer_stop(pwm); | |
241 | kfree(pwm); | |
242 | } | |
243 | ||
244 | static int tpu_pwm_config(struct pwm_chip *chip, struct pwm_device *_pwm, | |
245 | int duty_ns, int period_ns) | |
246 | { | |
247 | static const unsigned int prescalers[] = { 1, 4, 16, 64 }; | |
248 | struct tpu_pwm_device *pwm = pwm_get_chip_data(_pwm); | |
249 | struct tpu_device *tpu = to_tpu_device(chip); | |
250 | unsigned int prescaler; | |
251 | bool duty_only = false; | |
252 | u32 clk_rate; | |
253 | u32 period; | |
254 | u32 duty; | |
255 | int ret; | |
256 | ||
257 | /* | |
258 | * Pick a prescaler to avoid overflowing the counter. | |
259 | * TODO: Pick the highest acceptable prescaler. | |
260 | */ | |
261 | clk_rate = clk_get_rate(tpu->clk); | |
262 | ||
263 | for (prescaler = 0; prescaler < ARRAY_SIZE(prescalers); ++prescaler) { | |
264 | period = clk_rate / prescalers[prescaler] | |
265 | / (NSEC_PER_SEC / period_ns); | |
266 | if (period <= 0xffff) | |
267 | break; | |
268 | } | |
269 | ||
270 | if (prescaler == ARRAY_SIZE(prescalers) || period == 0) { | |
271 | dev_err(&tpu->pdev->dev, "clock rate mismatch\n"); | |
272 | return -ENOTSUPP; | |
273 | } | |
274 | ||
275 | if (duty_ns) { | |
276 | duty = clk_rate / prescalers[prescaler] | |
277 | / (NSEC_PER_SEC / duty_ns); | |
278 | if (duty > period) | |
279 | return -EINVAL; | |
280 | } else { | |
281 | duty = 0; | |
282 | } | |
283 | ||
284 | dev_dbg(&tpu->pdev->dev, | |
285 | "rate %u, prescaler %u, period %u, duty %u\n", | |
286 | clk_rate, prescalers[prescaler], period, duty); | |
287 | ||
288 | if (pwm->prescaler == prescaler && pwm->period == period) | |
289 | duty_only = true; | |
290 | ||
291 | pwm->prescaler = prescaler; | |
292 | pwm->period = period; | |
293 | pwm->duty = duty; | |
294 | ||
295 | /* If the channel is disabled we're done. */ | |
296 | if (!pwm_is_enabled(_pwm)) | |
297 | return 0; | |
298 | ||
299 | if (duty_only && pwm->timer_on) { | |
300 | /* | |
301 | * If only the duty cycle changed and the timer is already | |
302 | * running, there's no need to reconfigure it completely, Just | |
303 | * modify the duty cycle. | |
304 | */ | |
305 | tpu_pwm_write(pwm, TPU_TGRAn, pwm->duty); | |
306 | dev_dbg(&tpu->pdev->dev, "%u: TGRA 0x%04x\n", pwm->channel, | |
307 | pwm->duty); | |
308 | } else { | |
309 | /* Otherwise perform a full reconfiguration. */ | |
310 | ret = tpu_pwm_timer_start(pwm); | |
311 | if (ret < 0) | |
312 | return ret; | |
313 | } | |
314 | ||
315 | if (duty == 0 || duty == period) { | |
316 | /* | |
317 | * To avoid running the timer when not strictly required, handle | |
318 | * 0% and 100% duty cycles as fixed levels and stop the timer. | |
319 | */ | |
320 | tpu_pwm_set_pin(pwm, duty ? TPU_PIN_ACTIVE : TPU_PIN_INACTIVE); | |
321 | tpu_pwm_timer_stop(pwm); | |
322 | } | |
323 | ||
324 | return 0; | |
325 | } | |
326 | ||
327 | static int tpu_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *_pwm, | |
328 | enum pwm_polarity polarity) | |
329 | { | |
330 | struct tpu_pwm_device *pwm = pwm_get_chip_data(_pwm); | |
331 | ||
332 | pwm->polarity = polarity; | |
333 | ||
334 | return 0; | |
335 | } | |
336 | ||
337 | static int tpu_pwm_enable(struct pwm_chip *chip, struct pwm_device *_pwm) | |
338 | { | |
339 | struct tpu_pwm_device *pwm = pwm_get_chip_data(_pwm); | |
340 | int ret; | |
341 | ||
342 | ret = tpu_pwm_timer_start(pwm); | |
343 | if (ret < 0) | |
344 | return ret; | |
345 | ||
346 | /* | |
347 | * To avoid running the timer when not strictly required, handle 0% and | |
348 | * 100% duty cycles as fixed levels and stop the timer. | |
349 | */ | |
350 | if (pwm->duty == 0 || pwm->duty == pwm->period) { | |
351 | tpu_pwm_set_pin(pwm, pwm->duty ? | |
352 | TPU_PIN_ACTIVE : TPU_PIN_INACTIVE); | |
353 | tpu_pwm_timer_stop(pwm); | |
354 | } | |
355 | ||
356 | return 0; | |
357 | } | |
358 | ||
359 | static void tpu_pwm_disable(struct pwm_chip *chip, struct pwm_device *_pwm) | |
360 | { | |
361 | struct tpu_pwm_device *pwm = pwm_get_chip_data(_pwm); | |
362 | ||
363 | /* The timer must be running to modify the pin output configuration. */ | |
364 | tpu_pwm_timer_start(pwm); | |
365 | tpu_pwm_set_pin(pwm, TPU_PIN_INACTIVE); | |
366 | tpu_pwm_timer_stop(pwm); | |
367 | } | |
368 | ||
369 | static const struct pwm_ops tpu_pwm_ops = { | |
370 | .request = tpu_pwm_request, | |
371 | .free = tpu_pwm_free, | |
372 | .config = tpu_pwm_config, | |
373 | .set_polarity = tpu_pwm_set_polarity, | |
374 | .enable = tpu_pwm_enable, | |
375 | .disable = tpu_pwm_disable, | |
376 | .owner = THIS_MODULE, | |
377 | }; | |
378 | ||
379 | /* ----------------------------------------------------------------------------- | |
380 | * Probe and remove | |
381 | */ | |
382 | ||
383 | static int tpu_probe(struct platform_device *pdev) | |
384 | { | |
385 | struct tpu_device *tpu; | |
386 | struct resource *res; | |
387 | int ret; | |
388 | ||
389 | tpu = devm_kzalloc(&pdev->dev, sizeof(*tpu), GFP_KERNEL); | |
390 | if (tpu == NULL) | |
391 | return -ENOMEM; | |
392 | ||
393 | spin_lock_init(&tpu->lock); | |
394 | tpu->pdev = pdev; | |
395 | ||
396 | /* Map memory, get clock and pin control. */ | |
397 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
398 | tpu->base = devm_ioremap_resource(&pdev->dev, res); | |
399 | if (IS_ERR(tpu->base)) | |
400 | return PTR_ERR(tpu->base); | |
401 | ||
402 | tpu->clk = devm_clk_get(&pdev->dev, NULL); | |
403 | if (IS_ERR(tpu->clk)) { | |
404 | dev_err(&pdev->dev, "cannot get clock\n"); | |
405 | return PTR_ERR(tpu->clk); | |
406 | } | |
407 | ||
408 | /* Initialize and register the device. */ | |
409 | platform_set_drvdata(pdev, tpu); | |
410 | ||
411 | tpu->chip.dev = &pdev->dev; | |
412 | tpu->chip.ops = &tpu_pwm_ops; | |
413 | tpu->chip.of_xlate = of_pwm_xlate_with_flags; | |
414 | tpu->chip.of_pwm_n_cells = 3; | |
415 | tpu->chip.base = -1; | |
416 | tpu->chip.npwm = TPU_CHANNEL_MAX; | |
417 | ||
418 | ret = pwmchip_add(&tpu->chip); | |
419 | if (ret < 0) { | |
420 | dev_err(&pdev->dev, "failed to register PWM chip\n"); | |
421 | return ret; | |
422 | } | |
423 | ||
424 | dev_info(&pdev->dev, "TPU PWM %d registered\n", tpu->pdev->id); | |
425 | ||
426 | pm_runtime_enable(&pdev->dev); | |
427 | ||
428 | return 0; | |
429 | } | |
430 | ||
431 | static int tpu_remove(struct platform_device *pdev) | |
432 | { | |
433 | struct tpu_device *tpu = platform_get_drvdata(pdev); | |
434 | int ret; | |
435 | ||
436 | ret = pwmchip_remove(&tpu->chip); | |
437 | if (ret) | |
438 | return ret; | |
439 | ||
440 | pm_runtime_disable(&pdev->dev); | |
441 | ||
442 | return 0; | |
443 | } | |
444 | ||
445 | #ifdef CONFIG_OF | |
446 | static const struct of_device_id tpu_of_table[] = { | |
447 | { .compatible = "renesas,tpu-r8a73a4", }, | |
448 | { .compatible = "renesas,tpu-r8a7740", }, | |
449 | { .compatible = "renesas,tpu-r8a7790", }, | |
450 | { .compatible = "renesas,tpu", }, | |
451 | { }, | |
452 | }; | |
453 | ||
454 | MODULE_DEVICE_TABLE(of, tpu_of_table); | |
455 | #endif | |
456 | ||
457 | static struct platform_driver tpu_driver = { | |
458 | .probe = tpu_probe, | |
459 | .remove = tpu_remove, | |
460 | .driver = { | |
461 | .name = "renesas-tpu-pwm", | |
462 | .of_match_table = of_match_ptr(tpu_of_table), | |
463 | } | |
464 | }; | |
465 | ||
466 | module_platform_driver(tpu_driver); | |
467 | ||
468 | MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>"); | |
469 | MODULE_DESCRIPTION("Renesas TPU PWM Driver"); | |
470 | MODULE_LICENSE("GPL v2"); | |
471 | MODULE_ALIAS("platform:renesas-tpu-pwm"); |