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1 | /* | |
2 | * ipr.h -- driver for IBM Power Linux RAID adapters | |
3 | * | |
4 | * Written By: Brian King <brking@us.ibm.com>, IBM Corporation | |
5 | * | |
6 | * Copyright (C) 2003, 2004 IBM Corporation | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | * | |
22 | * Alan Cox <alan@lxorguk.ukuu.org.uk> - Removed several careless u32/dma_addr_t errors | |
23 | * that broke 64bit platforms. | |
24 | */ | |
25 | ||
26 | #ifndef _IPR_H | |
27 | #define _IPR_H | |
28 | ||
29 | #include <asm/unaligned.h> | |
30 | #include <linux/types.h> | |
31 | #include <linux/completion.h> | |
32 | #include <linux/libata.h> | |
33 | #include <linux/list.h> | |
34 | #include <linux/kref.h> | |
35 | #include <linux/blk-iopoll.h> | |
36 | #include <scsi/scsi.h> | |
37 | #include <scsi/scsi_cmnd.h> | |
38 | ||
39 | /* | |
40 | * Literals | |
41 | */ | |
42 | #define IPR_DRIVER_VERSION "2.6.2" | |
43 | #define IPR_DRIVER_DATE "(June 11, 2015)" | |
44 | ||
45 | /* | |
46 | * IPR_MAX_CMD_PER_LUN: This defines the maximum number of outstanding | |
47 | * ops per device for devices not running tagged command queuing. | |
48 | * This can be adjusted at runtime through sysfs device attributes. | |
49 | */ | |
50 | #define IPR_MAX_CMD_PER_LUN 6 | |
51 | #define IPR_MAX_CMD_PER_ATA_LUN 1 | |
52 | ||
53 | /* | |
54 | * IPR_NUM_BASE_CMD_BLKS: This defines the maximum number of | |
55 | * ops the mid-layer can send to the adapter. | |
56 | */ | |
57 | #define IPR_NUM_BASE_CMD_BLKS (ioa_cfg->max_cmds) | |
58 | ||
59 | #define PCI_DEVICE_ID_IBM_OBSIDIAN_E 0x0339 | |
60 | ||
61 | #define PCI_DEVICE_ID_IBM_CROC_FPGA_E2 0x033D | |
62 | #define PCI_DEVICE_ID_IBM_CROCODILE 0x034A | |
63 | ||
64 | #define IPR_SUBS_DEV_ID_2780 0x0264 | |
65 | #define IPR_SUBS_DEV_ID_5702 0x0266 | |
66 | #define IPR_SUBS_DEV_ID_5703 0x0278 | |
67 | #define IPR_SUBS_DEV_ID_572E 0x028D | |
68 | #define IPR_SUBS_DEV_ID_573E 0x02D3 | |
69 | #define IPR_SUBS_DEV_ID_573D 0x02D4 | |
70 | #define IPR_SUBS_DEV_ID_571A 0x02C0 | |
71 | #define IPR_SUBS_DEV_ID_571B 0x02BE | |
72 | #define IPR_SUBS_DEV_ID_571E 0x02BF | |
73 | #define IPR_SUBS_DEV_ID_571F 0x02D5 | |
74 | #define IPR_SUBS_DEV_ID_572A 0x02C1 | |
75 | #define IPR_SUBS_DEV_ID_572B 0x02C2 | |
76 | #define IPR_SUBS_DEV_ID_572F 0x02C3 | |
77 | #define IPR_SUBS_DEV_ID_574E 0x030A | |
78 | #define IPR_SUBS_DEV_ID_575B 0x030D | |
79 | #define IPR_SUBS_DEV_ID_575C 0x0338 | |
80 | #define IPR_SUBS_DEV_ID_57B3 0x033A | |
81 | #define IPR_SUBS_DEV_ID_57B7 0x0360 | |
82 | #define IPR_SUBS_DEV_ID_57B8 0x02C2 | |
83 | ||
84 | #define IPR_SUBS_DEV_ID_57B4 0x033B | |
85 | #define IPR_SUBS_DEV_ID_57B2 0x035F | |
86 | #define IPR_SUBS_DEV_ID_57C0 0x0352 | |
87 | #define IPR_SUBS_DEV_ID_57C3 0x0353 | |
88 | #define IPR_SUBS_DEV_ID_57C4 0x0354 | |
89 | #define IPR_SUBS_DEV_ID_57C6 0x0357 | |
90 | #define IPR_SUBS_DEV_ID_57CC 0x035C | |
91 | ||
92 | #define IPR_SUBS_DEV_ID_57B5 0x033C | |
93 | #define IPR_SUBS_DEV_ID_57CE 0x035E | |
94 | #define IPR_SUBS_DEV_ID_57B1 0x0355 | |
95 | ||
96 | #define IPR_SUBS_DEV_ID_574D 0x0356 | |
97 | #define IPR_SUBS_DEV_ID_57C8 0x035D | |
98 | ||
99 | #define IPR_SUBS_DEV_ID_57D5 0x03FB | |
100 | #define IPR_SUBS_DEV_ID_57D6 0x03FC | |
101 | #define IPR_SUBS_DEV_ID_57D7 0x03FF | |
102 | #define IPR_SUBS_DEV_ID_57D8 0x03FE | |
103 | #define IPR_SUBS_DEV_ID_57D9 0x046D | |
104 | #define IPR_SUBS_DEV_ID_57DA 0x04CA | |
105 | #define IPR_SUBS_DEV_ID_57EB 0x0474 | |
106 | #define IPR_SUBS_DEV_ID_57EC 0x0475 | |
107 | #define IPR_SUBS_DEV_ID_57ED 0x0499 | |
108 | #define IPR_SUBS_DEV_ID_57EE 0x049A | |
109 | #define IPR_SUBS_DEV_ID_57EF 0x049B | |
110 | #define IPR_SUBS_DEV_ID_57F0 0x049C | |
111 | #define IPR_SUBS_DEV_ID_2CCA 0x04C7 | |
112 | #define IPR_SUBS_DEV_ID_2CD2 0x04C8 | |
113 | #define IPR_SUBS_DEV_ID_2CCD 0x04C9 | |
114 | #define IPR_NAME "ipr" | |
115 | ||
116 | /* | |
117 | * Return codes | |
118 | */ | |
119 | #define IPR_RC_JOB_CONTINUE 1 | |
120 | #define IPR_RC_JOB_RETURN 2 | |
121 | ||
122 | /* | |
123 | * IOASCs | |
124 | */ | |
125 | #define IPR_IOASC_NR_INIT_CMD_REQUIRED 0x02040200 | |
126 | #define IPR_IOASC_NR_IOA_RESET_REQUIRED 0x02048000 | |
127 | #define IPR_IOASC_SYNC_REQUIRED 0x023f0000 | |
128 | #define IPR_IOASC_MED_DO_NOT_REALLOC 0x03110C00 | |
129 | #define IPR_IOASC_HW_SEL_TIMEOUT 0x04050000 | |
130 | #define IPR_IOASC_HW_DEV_BUS_STATUS 0x04448500 | |
131 | #define IPR_IOASC_IOASC_MASK 0xFFFFFF00 | |
132 | #define IPR_IOASC_SCSI_STATUS_MASK 0x000000FF | |
133 | #define IPR_IOASC_HW_CMD_FAILED 0x046E0000 | |
134 | #define IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT 0x05240000 | |
135 | #define IPR_IOASC_IR_RESOURCE_HANDLE 0x05250000 | |
136 | #define IPR_IOASC_IR_NO_CMDS_TO_2ND_IOA 0x05258100 | |
137 | #define IPR_IOASA_IR_DUAL_IOA_DISABLED 0x052C8000 | |
138 | #define IPR_IOASC_BUS_WAS_RESET 0x06290000 | |
139 | #define IPR_IOASC_BUS_WAS_RESET_BY_OTHER 0x06298000 | |
140 | #define IPR_IOASC_ABORTED_CMD_TERM_BY_HOST 0x0B5A0000 | |
141 | #define IPR_IOASC_IR_NON_OPTIMIZED 0x05258200 | |
142 | ||
143 | #define IPR_FIRST_DRIVER_IOASC 0x10000000 | |
144 | #define IPR_IOASC_IOA_WAS_RESET 0x10000001 | |
145 | #define IPR_IOASC_PCI_ACCESS_ERROR 0x10000002 | |
146 | ||
147 | /* Driver data flags */ | |
148 | #define IPR_USE_LONG_TRANSOP_TIMEOUT 0x00000001 | |
149 | #define IPR_USE_PCI_WARM_RESET 0x00000002 | |
150 | ||
151 | #define IPR_DEFAULT_MAX_ERROR_DUMP 984 | |
152 | #define IPR_NUM_LOG_HCAMS 2 | |
153 | #define IPR_NUM_CFG_CHG_HCAMS 2 | |
154 | #define IPR_NUM_HCAMS (IPR_NUM_LOG_HCAMS + IPR_NUM_CFG_CHG_HCAMS) | |
155 | ||
156 | #define IPR_MAX_SIS64_TARGETS_PER_BUS 1024 | |
157 | #define IPR_MAX_SIS64_LUNS_PER_TARGET 0xffffffff | |
158 | ||
159 | #define IPR_MAX_NUM_TARGETS_PER_BUS 256 | |
160 | #define IPR_MAX_NUM_LUNS_PER_TARGET 256 | |
161 | #define IPR_VSET_BUS 0xff | |
162 | #define IPR_IOA_BUS 0xff | |
163 | #define IPR_IOA_TARGET 0xff | |
164 | #define IPR_IOA_LUN 0xff | |
165 | #define IPR_MAX_NUM_BUSES 16 | |
166 | ||
167 | #define IPR_NUM_RESET_RELOAD_RETRIES 3 | |
168 | ||
169 | /* We need resources for HCAMS, IOA reset, IOA bringdown, and ERP */ | |
170 | #define IPR_NUM_INTERNAL_CMD_BLKS (IPR_NUM_HCAMS + \ | |
171 | ((IPR_NUM_RESET_RELOAD_RETRIES + 1) * 2) + 4) | |
172 | ||
173 | #define IPR_MAX_COMMANDS 100 | |
174 | #define IPR_NUM_CMD_BLKS (IPR_NUM_BASE_CMD_BLKS + \ | |
175 | IPR_NUM_INTERNAL_CMD_BLKS) | |
176 | ||
177 | #define IPR_MAX_PHYSICAL_DEVS 192 | |
178 | #define IPR_DEFAULT_SIS64_DEVS 1024 | |
179 | #define IPR_MAX_SIS64_DEVS 4096 | |
180 | ||
181 | #define IPR_MAX_SGLIST 64 | |
182 | #define IPR_IOA_MAX_SECTORS 32767 | |
183 | #define IPR_VSET_MAX_SECTORS 512 | |
184 | #define IPR_MAX_CDB_LEN 16 | |
185 | #define IPR_MAX_HRRQ_RETRIES 3 | |
186 | ||
187 | #define IPR_DEFAULT_BUS_WIDTH 16 | |
188 | #define IPR_80MBs_SCSI_RATE ((80 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8)) | |
189 | #define IPR_U160_SCSI_RATE ((160 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8)) | |
190 | #define IPR_U320_SCSI_RATE ((320 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8)) | |
191 | #define IPR_MAX_SCSI_RATE(width) ((320 * 10) / ((width) / 8)) | |
192 | ||
193 | #define IPR_IOA_RES_HANDLE 0xffffffff | |
194 | #define IPR_INVALID_RES_HANDLE 0 | |
195 | #define IPR_IOA_RES_ADDR 0x00ffffff | |
196 | ||
197 | /* | |
198 | * Adapter Commands | |
199 | */ | |
200 | #define IPR_CANCEL_REQUEST 0xC0 | |
201 | #define IPR_CANCEL_64BIT_IOARCB 0x01 | |
202 | #define IPR_QUERY_RSRC_STATE 0xC2 | |
203 | #define IPR_RESET_DEVICE 0xC3 | |
204 | #define IPR_RESET_TYPE_SELECT 0x80 | |
205 | #define IPR_LUN_RESET 0x40 | |
206 | #define IPR_TARGET_RESET 0x20 | |
207 | #define IPR_BUS_RESET 0x10 | |
208 | #define IPR_ATA_PHY_RESET 0x80 | |
209 | #define IPR_ID_HOST_RR_Q 0xC4 | |
210 | #define IPR_QUERY_IOA_CONFIG 0xC5 | |
211 | #define IPR_CANCEL_ALL_REQUESTS 0xCE | |
212 | #define IPR_HOST_CONTROLLED_ASYNC 0xCF | |
213 | #define IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE 0x01 | |
214 | #define IPR_HCAM_CDB_OP_CODE_LOG_DATA 0x02 | |
215 | #define IPR_SET_SUPPORTED_DEVICES 0xFB | |
216 | #define IPR_SET_ALL_SUPPORTED_DEVICES 0x80 | |
217 | #define IPR_IOA_SHUTDOWN 0xF7 | |
218 | #define IPR_WR_BUF_DOWNLOAD_AND_SAVE 0x05 | |
219 | ||
220 | /* | |
221 | * Timeouts | |
222 | */ | |
223 | #define IPR_SHUTDOWN_TIMEOUT (ipr_fastfail ? 60 * HZ : 10 * 60 * HZ) | |
224 | #define IPR_VSET_RW_TIMEOUT (ipr_fastfail ? 30 * HZ : 2 * 60 * HZ) | |
225 | #define IPR_ABBREV_SHUTDOWN_TIMEOUT (10 * HZ) | |
226 | #define IPR_DUAL_IOA_ABBR_SHUTDOWN_TO (2 * 60 * HZ) | |
227 | #define IPR_DEVICE_RESET_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ) | |
228 | #define IPR_CANCEL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ) | |
229 | #define IPR_CANCEL_ALL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ) | |
230 | #define IPR_ABORT_TASK_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ) | |
231 | #define IPR_INTERNAL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ) | |
232 | #define IPR_WRITE_BUFFER_TIMEOUT (30 * 60 * HZ) | |
233 | #define IPR_SET_SUP_DEVICE_TIMEOUT (2 * 60 * HZ) | |
234 | #define IPR_REQUEST_SENSE_TIMEOUT (10 * HZ) | |
235 | #define IPR_OPERATIONAL_TIMEOUT (5 * 60) | |
236 | #define IPR_LONG_OPERATIONAL_TIMEOUT (12 * 60) | |
237 | #define IPR_WAIT_FOR_RESET_TIMEOUT (2 * HZ) | |
238 | #define IPR_CHECK_FOR_RESET_TIMEOUT (HZ / 10) | |
239 | #define IPR_WAIT_FOR_BIST_TIMEOUT (2 * HZ) | |
240 | #define IPR_PCI_ERROR_RECOVERY_TIMEOUT (120 * HZ) | |
241 | #define IPR_PCI_RESET_TIMEOUT (HZ / 2) | |
242 | #define IPR_SIS32_DUMP_TIMEOUT (15 * HZ) | |
243 | #define IPR_SIS64_DUMP_TIMEOUT (40 * HZ) | |
244 | #define IPR_DUMP_DELAY_SECONDS 4 | |
245 | #define IPR_DUMP_DELAY_TIMEOUT (IPR_DUMP_DELAY_SECONDS * HZ) | |
246 | ||
247 | /* | |
248 | * SCSI Literals | |
249 | */ | |
250 | #define IPR_VENDOR_ID_LEN 8 | |
251 | #define IPR_PROD_ID_LEN 16 | |
252 | #define IPR_SERIAL_NUM_LEN 8 | |
253 | ||
254 | /* | |
255 | * Hardware literals | |
256 | */ | |
257 | #define IPR_FMT2_MBX_ADDR_MASK 0x0fffffff | |
258 | #define IPR_FMT2_MBX_BAR_SEL_MASK 0xf0000000 | |
259 | #define IPR_FMT2_MKR_BAR_SEL_SHIFT 28 | |
260 | #define IPR_GET_FMT2_BAR_SEL(mbx) \ | |
261 | (((mbx) & IPR_FMT2_MBX_BAR_SEL_MASK) >> IPR_FMT2_MKR_BAR_SEL_SHIFT) | |
262 | #define IPR_SDT_FMT2_BAR0_SEL 0x0 | |
263 | #define IPR_SDT_FMT2_BAR1_SEL 0x1 | |
264 | #define IPR_SDT_FMT2_BAR2_SEL 0x2 | |
265 | #define IPR_SDT_FMT2_BAR3_SEL 0x3 | |
266 | #define IPR_SDT_FMT2_BAR4_SEL 0x4 | |
267 | #define IPR_SDT_FMT2_BAR5_SEL 0x5 | |
268 | #define IPR_SDT_FMT2_EXP_ROM_SEL 0x8 | |
269 | #define IPR_FMT2_SDT_READY_TO_USE 0xC4D4E3F2 | |
270 | #define IPR_FMT3_SDT_READY_TO_USE 0xC4D4E3F3 | |
271 | #define IPR_DOORBELL 0x82800000 | |
272 | #define IPR_RUNTIME_RESET 0x40000000 | |
273 | ||
274 | #define IPR_IPL_INIT_MIN_STAGE_TIME 5 | |
275 | #define IPR_IPL_INIT_DEFAULT_STAGE_TIME 30 | |
276 | #define IPR_IPL_INIT_STAGE_UNKNOWN 0x0 | |
277 | #define IPR_IPL_INIT_STAGE_TRANSOP 0xB0000000 | |
278 | #define IPR_IPL_INIT_STAGE_MASK 0xff000000 | |
279 | #define IPR_IPL_INIT_STAGE_TIME_MASK 0x0000ffff | |
280 | #define IPR_PCII_IPL_STAGE_CHANGE (0x80000000 >> 0) | |
281 | ||
282 | #define IPR_PCII_MAILBOX_STABLE (0x80000000 >> 4) | |
283 | #define IPR_WAIT_FOR_MAILBOX (2 * HZ) | |
284 | ||
285 | #define IPR_PCII_IOA_TRANS_TO_OPER (0x80000000 >> 0) | |
286 | #define IPR_PCII_IOARCB_XFER_FAILED (0x80000000 >> 3) | |
287 | #define IPR_PCII_IOA_UNIT_CHECKED (0x80000000 >> 4) | |
288 | #define IPR_PCII_NO_HOST_RRQ (0x80000000 >> 5) | |
289 | #define IPR_PCII_CRITICAL_OPERATION (0x80000000 >> 6) | |
290 | #define IPR_PCII_IO_DEBUG_ACKNOWLEDGE (0x80000000 >> 7) | |
291 | #define IPR_PCII_IOARRIN_LOST (0x80000000 >> 27) | |
292 | #define IPR_PCII_MMIO_ERROR (0x80000000 >> 28) | |
293 | #define IPR_PCII_PROC_ERR_STATE (0x80000000 >> 29) | |
294 | #define IPR_PCII_HRRQ_UPDATED (0x80000000 >> 30) | |
295 | #define IPR_PCII_CORE_ISSUED_RST_REQ (0x80000000 >> 31) | |
296 | ||
297 | #define IPR_PCII_ERROR_INTERRUPTS \ | |
298 | (IPR_PCII_IOARCB_XFER_FAILED | IPR_PCII_IOA_UNIT_CHECKED | \ | |
299 | IPR_PCII_NO_HOST_RRQ | IPR_PCII_IOARRIN_LOST | IPR_PCII_MMIO_ERROR) | |
300 | ||
301 | #define IPR_PCII_OPER_INTERRUPTS \ | |
302 | (IPR_PCII_ERROR_INTERRUPTS | IPR_PCII_HRRQ_UPDATED | IPR_PCII_IOA_TRANS_TO_OPER) | |
303 | ||
304 | #define IPR_UPROCI_RESET_ALERT (0x80000000 >> 7) | |
305 | #define IPR_UPROCI_IO_DEBUG_ALERT (0x80000000 >> 9) | |
306 | #define IPR_UPROCI_SIS64_START_BIST (0x80000000 >> 23) | |
307 | ||
308 | #define IPR_LDUMP_MAX_LONG_ACK_DELAY_IN_USEC 200000 /* 200 ms */ | |
309 | #define IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC 200000 /* 200 ms */ | |
310 | ||
311 | /* | |
312 | * Dump literals | |
313 | */ | |
314 | #define IPR_FMT2_MAX_IOA_DUMP_SIZE (4 * 1024 * 1024) | |
315 | #define IPR_FMT3_MAX_IOA_DUMP_SIZE (80 * 1024 * 1024) | |
316 | #define IPR_FMT2_NUM_SDT_ENTRIES 511 | |
317 | #define IPR_FMT3_NUM_SDT_ENTRIES 0xFFF | |
318 | #define IPR_FMT2_MAX_NUM_DUMP_PAGES ((IPR_FMT2_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1) | |
319 | #define IPR_FMT3_MAX_NUM_DUMP_PAGES ((IPR_FMT3_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1) | |
320 | ||
321 | /* | |
322 | * Misc literals | |
323 | */ | |
324 | #define IPR_NUM_IOADL_ENTRIES IPR_MAX_SGLIST | |
325 | #define IPR_MAX_MSIX_VECTORS 0x10 | |
326 | #define IPR_MAX_HRRQ_NUM 0x10 | |
327 | #define IPR_INIT_HRRQ 0x0 | |
328 | ||
329 | /* | |
330 | * Adapter interface types | |
331 | */ | |
332 | ||
333 | struct ipr_res_addr { | |
334 | u8 reserved; | |
335 | u8 bus; | |
336 | u8 target; | |
337 | u8 lun; | |
338 | #define IPR_GET_PHYS_LOC(res_addr) \ | |
339 | (((res_addr).bus << 16) | ((res_addr).target << 8) | (res_addr).lun) | |
340 | }__attribute__((packed, aligned (4))); | |
341 | ||
342 | struct ipr_std_inq_vpids { | |
343 | u8 vendor_id[IPR_VENDOR_ID_LEN]; | |
344 | u8 product_id[IPR_PROD_ID_LEN]; | |
345 | }__attribute__((packed)); | |
346 | ||
347 | struct ipr_vpd { | |
348 | struct ipr_std_inq_vpids vpids; | |
349 | u8 sn[IPR_SERIAL_NUM_LEN]; | |
350 | }__attribute__((packed)); | |
351 | ||
352 | struct ipr_ext_vpd { | |
353 | struct ipr_vpd vpd; | |
354 | __be32 wwid[2]; | |
355 | }__attribute__((packed)); | |
356 | ||
357 | struct ipr_ext_vpd64 { | |
358 | struct ipr_vpd vpd; | |
359 | __be32 wwid[4]; | |
360 | }__attribute__((packed)); | |
361 | ||
362 | struct ipr_std_inq_data { | |
363 | u8 peri_qual_dev_type; | |
364 | #define IPR_STD_INQ_PERI_QUAL(peri) ((peri) >> 5) | |
365 | #define IPR_STD_INQ_PERI_DEV_TYPE(peri) ((peri) & 0x1F) | |
366 | ||
367 | u8 removeable_medium_rsvd; | |
368 | #define IPR_STD_INQ_REMOVEABLE_MEDIUM 0x80 | |
369 | ||
370 | #define IPR_IS_DASD_DEVICE(std_inq) \ | |
371 | ((IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_DISK) && \ | |
372 | !(((std_inq).removeable_medium_rsvd) & IPR_STD_INQ_REMOVEABLE_MEDIUM)) | |
373 | ||
374 | #define IPR_IS_SES_DEVICE(std_inq) \ | |
375 | (IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_ENCLOSURE) | |
376 | ||
377 | u8 version; | |
378 | u8 aen_naca_fmt; | |
379 | u8 additional_len; | |
380 | u8 sccs_rsvd; | |
381 | u8 bq_enc_multi; | |
382 | u8 sync_cmdq_flags; | |
383 | ||
384 | struct ipr_std_inq_vpids vpids; | |
385 | ||
386 | u8 ros_rsvd_ram_rsvd[4]; | |
387 | ||
388 | u8 serial_num[IPR_SERIAL_NUM_LEN]; | |
389 | }__attribute__ ((packed)); | |
390 | ||
391 | #define IPR_RES_TYPE_AF_DASD 0x00 | |
392 | #define IPR_RES_TYPE_GENERIC_SCSI 0x01 | |
393 | #define IPR_RES_TYPE_VOLUME_SET 0x02 | |
394 | #define IPR_RES_TYPE_REMOTE_AF_DASD 0x03 | |
395 | #define IPR_RES_TYPE_GENERIC_ATA 0x04 | |
396 | #define IPR_RES_TYPE_ARRAY 0x05 | |
397 | #define IPR_RES_TYPE_IOAFP 0xff | |
398 | ||
399 | struct ipr_config_table_entry { | |
400 | u8 proto; | |
401 | #define IPR_PROTO_SATA 0x02 | |
402 | #define IPR_PROTO_SATA_ATAPI 0x03 | |
403 | #define IPR_PROTO_SAS_STP 0x06 | |
404 | #define IPR_PROTO_SAS_STP_ATAPI 0x07 | |
405 | u8 array_id; | |
406 | u8 flags; | |
407 | #define IPR_IS_IOA_RESOURCE 0x80 | |
408 | u8 rsvd_subtype; | |
409 | ||
410 | #define IPR_QUEUEING_MODEL(res) ((((res)->flags) & 0x70) >> 4) | |
411 | #define IPR_QUEUE_FROZEN_MODEL 0 | |
412 | #define IPR_QUEUE_NACA_MODEL 1 | |
413 | ||
414 | struct ipr_res_addr res_addr; | |
415 | __be32 res_handle; | |
416 | __be32 lun_wwn[2]; | |
417 | struct ipr_std_inq_data std_inq_data; | |
418 | }__attribute__ ((packed, aligned (4))); | |
419 | ||
420 | struct ipr_config_table_entry64 { | |
421 | u8 res_type; | |
422 | u8 proto; | |
423 | u8 vset_num; | |
424 | u8 array_id; | |
425 | __be16 flags; | |
426 | __be16 res_flags; | |
427 | #define IPR_QUEUEING_MODEL64(res) ((((res)->res_flags) & 0x7000) >> 12) | |
428 | __be32 res_handle; | |
429 | u8 dev_id_type; | |
430 | u8 reserved[3]; | |
431 | __be64 dev_id; | |
432 | __be64 lun; | |
433 | __be64 lun_wwn[2]; | |
434 | #define IPR_MAX_RES_PATH_LENGTH 48 | |
435 | __be64 res_path; | |
436 | struct ipr_std_inq_data std_inq_data; | |
437 | u8 reserved2[4]; | |
438 | __be64 reserved3[2]; | |
439 | u8 reserved4[8]; | |
440 | }__attribute__ ((packed, aligned (8))); | |
441 | ||
442 | struct ipr_config_table_hdr { | |
443 | u8 num_entries; | |
444 | u8 flags; | |
445 | #define IPR_UCODE_DOWNLOAD_REQ 0x10 | |
446 | __be16 reserved; | |
447 | }__attribute__((packed, aligned (4))); | |
448 | ||
449 | struct ipr_config_table_hdr64 { | |
450 | __be16 num_entries; | |
451 | __be16 reserved; | |
452 | u8 flags; | |
453 | u8 reserved2[11]; | |
454 | }__attribute__((packed, aligned (4))); | |
455 | ||
456 | struct ipr_config_table { | |
457 | struct ipr_config_table_hdr hdr; | |
458 | struct ipr_config_table_entry dev[0]; | |
459 | }__attribute__((packed, aligned (4))); | |
460 | ||
461 | struct ipr_config_table64 { | |
462 | struct ipr_config_table_hdr64 hdr64; | |
463 | struct ipr_config_table_entry64 dev[0]; | |
464 | }__attribute__((packed, aligned (8))); | |
465 | ||
466 | struct ipr_config_table_entry_wrapper { | |
467 | union { | |
468 | struct ipr_config_table_entry *cfgte; | |
469 | struct ipr_config_table_entry64 *cfgte64; | |
470 | } u; | |
471 | }; | |
472 | ||
473 | struct ipr_hostrcb_cfg_ch_not { | |
474 | union { | |
475 | struct ipr_config_table_entry cfgte; | |
476 | struct ipr_config_table_entry64 cfgte64; | |
477 | } u; | |
478 | u8 reserved[936]; | |
479 | }__attribute__((packed, aligned (4))); | |
480 | ||
481 | struct ipr_supported_device { | |
482 | __be16 data_length; | |
483 | u8 reserved; | |
484 | u8 num_records; | |
485 | struct ipr_std_inq_vpids vpids; | |
486 | u8 reserved2[16]; | |
487 | }__attribute__((packed, aligned (4))); | |
488 | ||
489 | struct ipr_hrr_queue { | |
490 | struct ipr_ioa_cfg *ioa_cfg; | |
491 | __be32 *host_rrq; | |
492 | dma_addr_t host_rrq_dma; | |
493 | #define IPR_HRRQ_REQ_RESP_HANDLE_MASK 0xfffffffc | |
494 | #define IPR_HRRQ_RESP_BIT_SET 0x00000002 | |
495 | #define IPR_HRRQ_TOGGLE_BIT 0x00000001 | |
496 | #define IPR_HRRQ_REQ_RESP_HANDLE_SHIFT 2 | |
497 | #define IPR_ID_HRRQ_SELE_ENABLE 0x02 | |
498 | volatile __be32 *hrrq_start; | |
499 | volatile __be32 *hrrq_end; | |
500 | volatile __be32 *hrrq_curr; | |
501 | ||
502 | struct list_head hrrq_free_q; | |
503 | struct list_head hrrq_pending_q; | |
504 | spinlock_t _lock; | |
505 | spinlock_t *lock; | |
506 | ||
507 | volatile u32 toggle_bit; | |
508 | u32 size; | |
509 | u32 min_cmd_id; | |
510 | u32 max_cmd_id; | |
511 | u8 allow_interrupts:1; | |
512 | u8 ioa_is_dead:1; | |
513 | u8 allow_cmds:1; | |
514 | u8 removing_ioa:1; | |
515 | ||
516 | struct blk_iopoll iopoll; | |
517 | }; | |
518 | ||
519 | /* Command packet structure */ | |
520 | struct ipr_cmd_pkt { | |
521 | u8 reserved; /* Reserved by IOA */ | |
522 | u8 hrrq_id; | |
523 | u8 request_type; | |
524 | #define IPR_RQTYPE_SCSICDB 0x00 | |
525 | #define IPR_RQTYPE_IOACMD 0x01 | |
526 | #define IPR_RQTYPE_HCAM 0x02 | |
527 | #define IPR_RQTYPE_ATA_PASSTHRU 0x04 | |
528 | #define IPR_RQTYPE_PIPE 0x05 | |
529 | ||
530 | u8 reserved2; | |
531 | ||
532 | u8 flags_hi; | |
533 | #define IPR_FLAGS_HI_WRITE_NOT_READ 0x80 | |
534 | #define IPR_FLAGS_HI_NO_ULEN_CHK 0x20 | |
535 | #define IPR_FLAGS_HI_SYNC_OVERRIDE 0x10 | |
536 | #define IPR_FLAGS_HI_SYNC_COMPLETE 0x08 | |
537 | #define IPR_FLAGS_HI_NO_LINK_DESC 0x04 | |
538 | ||
539 | u8 flags_lo; | |
540 | #define IPR_FLAGS_LO_ALIGNED_BFR 0x20 | |
541 | #define IPR_FLAGS_LO_DELAY_AFTER_RST 0x10 | |
542 | #define IPR_FLAGS_LO_UNTAGGED_TASK 0x00 | |
543 | #define IPR_FLAGS_LO_SIMPLE_TASK 0x02 | |
544 | #define IPR_FLAGS_LO_ORDERED_TASK 0x04 | |
545 | #define IPR_FLAGS_LO_HEAD_OF_Q_TASK 0x06 | |
546 | #define IPR_FLAGS_LO_ACA_TASK 0x08 | |
547 | ||
548 | u8 cdb[16]; | |
549 | __be16 timeout; | |
550 | }__attribute__ ((packed, aligned(4))); | |
551 | ||
552 | struct ipr_ioarcb_ata_regs { /* 22 bytes */ | |
553 | u8 flags; | |
554 | #define IPR_ATA_FLAG_PACKET_CMD 0x80 | |
555 | #define IPR_ATA_FLAG_XFER_TYPE_DMA 0x40 | |
556 | #define IPR_ATA_FLAG_STATUS_ON_GOOD_COMPLETION 0x20 | |
557 | u8 reserved[3]; | |
558 | ||
559 | __be16 data; | |
560 | u8 feature; | |
561 | u8 nsect; | |
562 | u8 lbal; | |
563 | u8 lbam; | |
564 | u8 lbah; | |
565 | u8 device; | |
566 | u8 command; | |
567 | u8 reserved2[3]; | |
568 | u8 hob_feature; | |
569 | u8 hob_nsect; | |
570 | u8 hob_lbal; | |
571 | u8 hob_lbam; | |
572 | u8 hob_lbah; | |
573 | u8 ctl; | |
574 | }__attribute__ ((packed, aligned(2))); | |
575 | ||
576 | struct ipr_ioadl_desc { | |
577 | __be32 flags_and_data_len; | |
578 | #define IPR_IOADL_FLAGS_MASK 0xff000000 | |
579 | #define IPR_IOADL_GET_FLAGS(x) (be32_to_cpu(x) & IPR_IOADL_FLAGS_MASK) | |
580 | #define IPR_IOADL_DATA_LEN_MASK 0x00ffffff | |
581 | #define IPR_IOADL_GET_DATA_LEN(x) (be32_to_cpu(x) & IPR_IOADL_DATA_LEN_MASK) | |
582 | #define IPR_IOADL_FLAGS_READ 0x48000000 | |
583 | #define IPR_IOADL_FLAGS_READ_LAST 0x49000000 | |
584 | #define IPR_IOADL_FLAGS_WRITE 0x68000000 | |
585 | #define IPR_IOADL_FLAGS_WRITE_LAST 0x69000000 | |
586 | #define IPR_IOADL_FLAGS_LAST 0x01000000 | |
587 | ||
588 | __be32 address; | |
589 | }__attribute__((packed, aligned (8))); | |
590 | ||
591 | struct ipr_ioadl64_desc { | |
592 | __be32 flags; | |
593 | __be32 data_len; | |
594 | __be64 address; | |
595 | }__attribute__((packed, aligned (16))); | |
596 | ||
597 | struct ipr_ata64_ioadl { | |
598 | struct ipr_ioarcb_ata_regs regs; | |
599 | u16 reserved[5]; | |
600 | struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES]; | |
601 | }__attribute__((packed, aligned (16))); | |
602 | ||
603 | struct ipr_ioarcb_add_data { | |
604 | union { | |
605 | struct ipr_ioarcb_ata_regs regs; | |
606 | struct ipr_ioadl_desc ioadl[5]; | |
607 | __be32 add_cmd_parms[10]; | |
608 | } u; | |
609 | }__attribute__ ((packed, aligned (4))); | |
610 | ||
611 | struct ipr_ioarcb_sis64_add_addr_ecb { | |
612 | __be64 ioasa_host_pci_addr; | |
613 | __be64 data_ioadl_addr; | |
614 | __be64 reserved; | |
615 | __be32 ext_control_buf[4]; | |
616 | }__attribute__((packed, aligned (8))); | |
617 | ||
618 | /* IOA Request Control Block 128 bytes */ | |
619 | struct ipr_ioarcb { | |
620 | union { | |
621 | __be32 ioarcb_host_pci_addr; | |
622 | __be64 ioarcb_host_pci_addr64; | |
623 | } a; | |
624 | __be32 res_handle; | |
625 | __be32 host_response_handle; | |
626 | __be32 reserved1; | |
627 | __be32 reserved2; | |
628 | __be32 reserved3; | |
629 | ||
630 | __be32 data_transfer_length; | |
631 | __be32 read_data_transfer_length; | |
632 | __be32 write_ioadl_addr; | |
633 | __be32 ioadl_len; | |
634 | __be32 read_ioadl_addr; | |
635 | __be32 read_ioadl_len; | |
636 | ||
637 | __be32 ioasa_host_pci_addr; | |
638 | __be16 ioasa_len; | |
639 | __be16 reserved4; | |
640 | ||
641 | struct ipr_cmd_pkt cmd_pkt; | |
642 | ||
643 | __be16 add_cmd_parms_offset; | |
644 | __be16 add_cmd_parms_len; | |
645 | ||
646 | union { | |
647 | struct ipr_ioarcb_add_data add_data; | |
648 | struct ipr_ioarcb_sis64_add_addr_ecb sis64_addr_data; | |
649 | } u; | |
650 | ||
651 | }__attribute__((packed, aligned (4))); | |
652 | ||
653 | struct ipr_ioasa_vset { | |
654 | __be32 failing_lba_hi; | |
655 | __be32 failing_lba_lo; | |
656 | __be32 reserved; | |
657 | }__attribute__((packed, aligned (4))); | |
658 | ||
659 | struct ipr_ioasa_af_dasd { | |
660 | __be32 failing_lba; | |
661 | __be32 reserved[2]; | |
662 | }__attribute__((packed, aligned (4))); | |
663 | ||
664 | struct ipr_ioasa_gpdd { | |
665 | u8 end_state; | |
666 | u8 bus_phase; | |
667 | __be16 reserved; | |
668 | __be32 ioa_data[2]; | |
669 | }__attribute__((packed, aligned (4))); | |
670 | ||
671 | struct ipr_ioasa_gata { | |
672 | u8 error; | |
673 | u8 nsect; /* Interrupt reason */ | |
674 | u8 lbal; | |
675 | u8 lbam; | |
676 | u8 lbah; | |
677 | u8 device; | |
678 | u8 status; | |
679 | u8 alt_status; /* ATA CTL */ | |
680 | u8 hob_nsect; | |
681 | u8 hob_lbal; | |
682 | u8 hob_lbam; | |
683 | u8 hob_lbah; | |
684 | }__attribute__((packed, aligned (4))); | |
685 | ||
686 | struct ipr_auto_sense { | |
687 | __be16 auto_sense_len; | |
688 | __be16 ioa_data_len; | |
689 | __be32 data[SCSI_SENSE_BUFFERSIZE/sizeof(__be32)]; | |
690 | }; | |
691 | ||
692 | struct ipr_ioasa_hdr { | |
693 | __be32 ioasc; | |
694 | #define IPR_IOASC_SENSE_KEY(ioasc) ((ioasc) >> 24) | |
695 | #define IPR_IOASC_SENSE_CODE(ioasc) (((ioasc) & 0x00ff0000) >> 16) | |
696 | #define IPR_IOASC_SENSE_QUAL(ioasc) (((ioasc) & 0x0000ff00) >> 8) | |
697 | #define IPR_IOASC_SENSE_STATUS(ioasc) ((ioasc) & 0x000000ff) | |
698 | ||
699 | __be16 ret_stat_len; /* Length of the returned IOASA */ | |
700 | ||
701 | __be16 avail_stat_len; /* Total Length of status available. */ | |
702 | ||
703 | __be32 residual_data_len; /* number of bytes in the host data */ | |
704 | /* buffers that were not used by the IOARCB command. */ | |
705 | ||
706 | __be32 ilid; | |
707 | #define IPR_NO_ILID 0 | |
708 | #define IPR_DRIVER_ILID 0xffffffff | |
709 | ||
710 | __be32 fd_ioasc; | |
711 | ||
712 | __be32 fd_phys_locator; | |
713 | ||
714 | __be32 fd_res_handle; | |
715 | ||
716 | __be32 ioasc_specific; /* status code specific field */ | |
717 | #define IPR_ADDITIONAL_STATUS_FMT 0x80000000 | |
718 | #define IPR_AUTOSENSE_VALID 0x40000000 | |
719 | #define IPR_ATA_DEVICE_WAS_RESET 0x20000000 | |
720 | #define IPR_IOASC_SPECIFIC_MASK 0x00ffffff | |
721 | #define IPR_FIELD_POINTER_VALID (0x80000000 >> 8) | |
722 | #define IPR_FIELD_POINTER_MASK 0x0000ffff | |
723 | ||
724 | }__attribute__((packed, aligned (4))); | |
725 | ||
726 | struct ipr_ioasa { | |
727 | struct ipr_ioasa_hdr hdr; | |
728 | ||
729 | union { | |
730 | struct ipr_ioasa_vset vset; | |
731 | struct ipr_ioasa_af_dasd dasd; | |
732 | struct ipr_ioasa_gpdd gpdd; | |
733 | struct ipr_ioasa_gata gata; | |
734 | } u; | |
735 | ||
736 | struct ipr_auto_sense auto_sense; | |
737 | }__attribute__((packed, aligned (4))); | |
738 | ||
739 | struct ipr_ioasa64 { | |
740 | struct ipr_ioasa_hdr hdr; | |
741 | u8 fd_res_path[8]; | |
742 | ||
743 | union { | |
744 | struct ipr_ioasa_vset vset; | |
745 | struct ipr_ioasa_af_dasd dasd; | |
746 | struct ipr_ioasa_gpdd gpdd; | |
747 | struct ipr_ioasa_gata gata; | |
748 | } u; | |
749 | ||
750 | struct ipr_auto_sense auto_sense; | |
751 | }__attribute__((packed, aligned (4))); | |
752 | ||
753 | struct ipr_mode_parm_hdr { | |
754 | u8 length; | |
755 | u8 medium_type; | |
756 | u8 device_spec_parms; | |
757 | u8 block_desc_len; | |
758 | }__attribute__((packed)); | |
759 | ||
760 | struct ipr_mode_pages { | |
761 | struct ipr_mode_parm_hdr hdr; | |
762 | u8 data[255 - sizeof(struct ipr_mode_parm_hdr)]; | |
763 | }__attribute__((packed)); | |
764 | ||
765 | struct ipr_mode_page_hdr { | |
766 | u8 ps_page_code; | |
767 | #define IPR_MODE_PAGE_PS 0x80 | |
768 | #define IPR_GET_MODE_PAGE_CODE(hdr) ((hdr)->ps_page_code & 0x3F) | |
769 | u8 page_length; | |
770 | }__attribute__ ((packed)); | |
771 | ||
772 | struct ipr_dev_bus_entry { | |
773 | struct ipr_res_addr res_addr; | |
774 | u8 flags; | |
775 | #define IPR_SCSI_ATTR_ENABLE_QAS 0x80 | |
776 | #define IPR_SCSI_ATTR_DISABLE_QAS 0x40 | |
777 | #define IPR_SCSI_ATTR_QAS_MASK 0xC0 | |
778 | #define IPR_SCSI_ATTR_ENABLE_TM 0x20 | |
779 | #define IPR_SCSI_ATTR_NO_TERM_PWR 0x10 | |
780 | #define IPR_SCSI_ATTR_TM_SUPPORTED 0x08 | |
781 | #define IPR_SCSI_ATTR_LVD_TO_SE_NOT_ALLOWED 0x04 | |
782 | ||
783 | u8 scsi_id; | |
784 | u8 bus_width; | |
785 | u8 extended_reset_delay; | |
786 | #define IPR_EXTENDED_RESET_DELAY 7 | |
787 | ||
788 | __be32 max_xfer_rate; | |
789 | ||
790 | u8 spinup_delay; | |
791 | u8 reserved3; | |
792 | __be16 reserved4; | |
793 | }__attribute__((packed, aligned (4))); | |
794 | ||
795 | struct ipr_mode_page28 { | |
796 | struct ipr_mode_page_hdr hdr; | |
797 | u8 num_entries; | |
798 | u8 entry_length; | |
799 | struct ipr_dev_bus_entry bus[0]; | |
800 | }__attribute__((packed)); | |
801 | ||
802 | struct ipr_mode_page24 { | |
803 | struct ipr_mode_page_hdr hdr; | |
804 | u8 flags; | |
805 | #define IPR_ENABLE_DUAL_IOA_AF 0x80 | |
806 | }__attribute__((packed)); | |
807 | ||
808 | struct ipr_ioa_vpd { | |
809 | struct ipr_std_inq_data std_inq_data; | |
810 | u8 ascii_part_num[12]; | |
811 | u8 reserved[40]; | |
812 | u8 ascii_plant_code[4]; | |
813 | }__attribute__((packed)); | |
814 | ||
815 | struct ipr_inquiry_page3 { | |
816 | u8 peri_qual_dev_type; | |
817 | u8 page_code; | |
818 | u8 reserved1; | |
819 | u8 page_length; | |
820 | u8 ascii_len; | |
821 | u8 reserved2[3]; | |
822 | u8 load_id[4]; | |
823 | u8 major_release; | |
824 | u8 card_type; | |
825 | u8 minor_release[2]; | |
826 | u8 ptf_number[4]; | |
827 | u8 patch_number[4]; | |
828 | }__attribute__((packed)); | |
829 | ||
830 | struct ipr_inquiry_cap { | |
831 | u8 peri_qual_dev_type; | |
832 | u8 page_code; | |
833 | u8 reserved1; | |
834 | u8 page_length; | |
835 | u8 ascii_len; | |
836 | u8 reserved2; | |
837 | u8 sis_version[2]; | |
838 | u8 cap; | |
839 | #define IPR_CAP_DUAL_IOA_RAID 0x80 | |
840 | u8 reserved3[15]; | |
841 | }__attribute__((packed)); | |
842 | ||
843 | #define IPR_INQUIRY_PAGE0_ENTRIES 20 | |
844 | struct ipr_inquiry_page0 { | |
845 | u8 peri_qual_dev_type; | |
846 | u8 page_code; | |
847 | u8 reserved1; | |
848 | u8 len; | |
849 | u8 page[IPR_INQUIRY_PAGE0_ENTRIES]; | |
850 | }__attribute__((packed)); | |
851 | ||
852 | struct ipr_hostrcb_device_data_entry { | |
853 | struct ipr_vpd vpd; | |
854 | struct ipr_res_addr dev_res_addr; | |
855 | struct ipr_vpd new_vpd; | |
856 | struct ipr_vpd ioa_last_with_dev_vpd; | |
857 | struct ipr_vpd cfc_last_with_dev_vpd; | |
858 | __be32 ioa_data[5]; | |
859 | }__attribute__((packed, aligned (4))); | |
860 | ||
861 | struct ipr_hostrcb_device_data_entry_enhanced { | |
862 | struct ipr_ext_vpd vpd; | |
863 | u8 ccin[4]; | |
864 | struct ipr_res_addr dev_res_addr; | |
865 | struct ipr_ext_vpd new_vpd; | |
866 | u8 new_ccin[4]; | |
867 | struct ipr_ext_vpd ioa_last_with_dev_vpd; | |
868 | struct ipr_ext_vpd cfc_last_with_dev_vpd; | |
869 | }__attribute__((packed, aligned (4))); | |
870 | ||
871 | struct ipr_hostrcb64_device_data_entry_enhanced { | |
872 | struct ipr_ext_vpd vpd; | |
873 | u8 ccin[4]; | |
874 | u8 res_path[8]; | |
875 | struct ipr_ext_vpd new_vpd; | |
876 | u8 new_ccin[4]; | |
877 | struct ipr_ext_vpd ioa_last_with_dev_vpd; | |
878 | struct ipr_ext_vpd cfc_last_with_dev_vpd; | |
879 | }__attribute__((packed, aligned (4))); | |
880 | ||
881 | struct ipr_hostrcb_array_data_entry { | |
882 | struct ipr_vpd vpd; | |
883 | struct ipr_res_addr expected_dev_res_addr; | |
884 | struct ipr_res_addr dev_res_addr; | |
885 | }__attribute__((packed, aligned (4))); | |
886 | ||
887 | struct ipr_hostrcb64_array_data_entry { | |
888 | struct ipr_ext_vpd vpd; | |
889 | u8 ccin[4]; | |
890 | u8 expected_res_path[8]; | |
891 | u8 res_path[8]; | |
892 | }__attribute__((packed, aligned (4))); | |
893 | ||
894 | struct ipr_hostrcb_array_data_entry_enhanced { | |
895 | struct ipr_ext_vpd vpd; | |
896 | u8 ccin[4]; | |
897 | struct ipr_res_addr expected_dev_res_addr; | |
898 | struct ipr_res_addr dev_res_addr; | |
899 | }__attribute__((packed, aligned (4))); | |
900 | ||
901 | struct ipr_hostrcb_type_ff_error { | |
902 | __be32 ioa_data[758]; | |
903 | }__attribute__((packed, aligned (4))); | |
904 | ||
905 | struct ipr_hostrcb_type_01_error { | |
906 | __be32 seek_counter; | |
907 | __be32 read_counter; | |
908 | u8 sense_data[32]; | |
909 | __be32 ioa_data[236]; | |
910 | }__attribute__((packed, aligned (4))); | |
911 | ||
912 | struct ipr_hostrcb_type_21_error { | |
913 | __be32 wwn[4]; | |
914 | u8 res_path[8]; | |
915 | u8 primary_problem_desc[32]; | |
916 | u8 second_problem_desc[32]; | |
917 | __be32 sense_data[8]; | |
918 | __be32 cdb[4]; | |
919 | __be32 residual_trans_length; | |
920 | __be32 length_of_error; | |
921 | __be32 ioa_data[236]; | |
922 | }__attribute__((packed, aligned (4))); | |
923 | ||
924 | struct ipr_hostrcb_type_02_error { | |
925 | struct ipr_vpd ioa_vpd; | |
926 | struct ipr_vpd cfc_vpd; | |
927 | struct ipr_vpd ioa_last_attached_to_cfc_vpd; | |
928 | struct ipr_vpd cfc_last_attached_to_ioa_vpd; | |
929 | __be32 ioa_data[3]; | |
930 | }__attribute__((packed, aligned (4))); | |
931 | ||
932 | struct ipr_hostrcb_type_12_error { | |
933 | struct ipr_ext_vpd ioa_vpd; | |
934 | struct ipr_ext_vpd cfc_vpd; | |
935 | struct ipr_ext_vpd ioa_last_attached_to_cfc_vpd; | |
936 | struct ipr_ext_vpd cfc_last_attached_to_ioa_vpd; | |
937 | __be32 ioa_data[3]; | |
938 | }__attribute__((packed, aligned (4))); | |
939 | ||
940 | struct ipr_hostrcb_type_03_error { | |
941 | struct ipr_vpd ioa_vpd; | |
942 | struct ipr_vpd cfc_vpd; | |
943 | __be32 errors_detected; | |
944 | __be32 errors_logged; | |
945 | u8 ioa_data[12]; | |
946 | struct ipr_hostrcb_device_data_entry dev[3]; | |
947 | }__attribute__((packed, aligned (4))); | |
948 | ||
949 | struct ipr_hostrcb_type_13_error { | |
950 | struct ipr_ext_vpd ioa_vpd; | |
951 | struct ipr_ext_vpd cfc_vpd; | |
952 | __be32 errors_detected; | |
953 | __be32 errors_logged; | |
954 | struct ipr_hostrcb_device_data_entry_enhanced dev[3]; | |
955 | }__attribute__((packed, aligned (4))); | |
956 | ||
957 | struct ipr_hostrcb_type_23_error { | |
958 | struct ipr_ext_vpd ioa_vpd; | |
959 | struct ipr_ext_vpd cfc_vpd; | |
960 | __be32 errors_detected; | |
961 | __be32 errors_logged; | |
962 | struct ipr_hostrcb64_device_data_entry_enhanced dev[3]; | |
963 | }__attribute__((packed, aligned (4))); | |
964 | ||
965 | struct ipr_hostrcb_type_04_error { | |
966 | struct ipr_vpd ioa_vpd; | |
967 | struct ipr_vpd cfc_vpd; | |
968 | u8 ioa_data[12]; | |
969 | struct ipr_hostrcb_array_data_entry array_member[10]; | |
970 | __be32 exposed_mode_adn; | |
971 | __be32 array_id; | |
972 | struct ipr_vpd incomp_dev_vpd; | |
973 | __be32 ioa_data2; | |
974 | struct ipr_hostrcb_array_data_entry array_member2[8]; | |
975 | struct ipr_res_addr last_func_vset_res_addr; | |
976 | u8 vset_serial_num[IPR_SERIAL_NUM_LEN]; | |
977 | u8 protection_level[8]; | |
978 | }__attribute__((packed, aligned (4))); | |
979 | ||
980 | struct ipr_hostrcb_type_14_error { | |
981 | struct ipr_ext_vpd ioa_vpd; | |
982 | struct ipr_ext_vpd cfc_vpd; | |
983 | __be32 exposed_mode_adn; | |
984 | __be32 array_id; | |
985 | struct ipr_res_addr last_func_vset_res_addr; | |
986 | u8 vset_serial_num[IPR_SERIAL_NUM_LEN]; | |
987 | u8 protection_level[8]; | |
988 | __be32 num_entries; | |
989 | struct ipr_hostrcb_array_data_entry_enhanced array_member[18]; | |
990 | }__attribute__((packed, aligned (4))); | |
991 | ||
992 | struct ipr_hostrcb_type_24_error { | |
993 | struct ipr_ext_vpd ioa_vpd; | |
994 | struct ipr_ext_vpd cfc_vpd; | |
995 | u8 reserved[2]; | |
996 | u8 exposed_mode_adn; | |
997 | #define IPR_INVALID_ARRAY_DEV_NUM 0xff | |
998 | u8 array_id; | |
999 | u8 last_res_path[8]; | |
1000 | u8 protection_level[8]; | |
1001 | struct ipr_ext_vpd64 array_vpd; | |
1002 | u8 description[16]; | |
1003 | u8 reserved2[3]; | |
1004 | u8 num_entries; | |
1005 | struct ipr_hostrcb64_array_data_entry array_member[32]; | |
1006 | }__attribute__((packed, aligned (4))); | |
1007 | ||
1008 | struct ipr_hostrcb_type_07_error { | |
1009 | u8 failure_reason[64]; | |
1010 | struct ipr_vpd vpd; | |
1011 | __be32 data[222]; | |
1012 | }__attribute__((packed, aligned (4))); | |
1013 | ||
1014 | struct ipr_hostrcb_type_17_error { | |
1015 | u8 failure_reason[64]; | |
1016 | struct ipr_ext_vpd vpd; | |
1017 | __be32 data[476]; | |
1018 | }__attribute__((packed, aligned (4))); | |
1019 | ||
1020 | struct ipr_hostrcb_config_element { | |
1021 | u8 type_status; | |
1022 | #define IPR_PATH_CFG_TYPE_MASK 0xF0 | |
1023 | #define IPR_PATH_CFG_NOT_EXIST 0x00 | |
1024 | #define IPR_PATH_CFG_IOA_PORT 0x10 | |
1025 | #define IPR_PATH_CFG_EXP_PORT 0x20 | |
1026 | #define IPR_PATH_CFG_DEVICE_PORT 0x30 | |
1027 | #define IPR_PATH_CFG_DEVICE_LUN 0x40 | |
1028 | ||
1029 | #define IPR_PATH_CFG_STATUS_MASK 0x0F | |
1030 | #define IPR_PATH_CFG_NO_PROB 0x00 | |
1031 | #define IPR_PATH_CFG_DEGRADED 0x01 | |
1032 | #define IPR_PATH_CFG_FAILED 0x02 | |
1033 | #define IPR_PATH_CFG_SUSPECT 0x03 | |
1034 | #define IPR_PATH_NOT_DETECTED 0x04 | |
1035 | #define IPR_PATH_INCORRECT_CONN 0x05 | |
1036 | ||
1037 | u8 cascaded_expander; | |
1038 | u8 phy; | |
1039 | u8 link_rate; | |
1040 | #define IPR_PHY_LINK_RATE_MASK 0x0F | |
1041 | ||
1042 | __be32 wwid[2]; | |
1043 | }__attribute__((packed, aligned (4))); | |
1044 | ||
1045 | struct ipr_hostrcb64_config_element { | |
1046 | __be16 length; | |
1047 | u8 descriptor_id; | |
1048 | #define IPR_DESCRIPTOR_MASK 0xC0 | |
1049 | #define IPR_DESCRIPTOR_SIS64 0x00 | |
1050 | ||
1051 | u8 reserved; | |
1052 | u8 type_status; | |
1053 | ||
1054 | u8 reserved2[2]; | |
1055 | u8 link_rate; | |
1056 | ||
1057 | u8 res_path[8]; | |
1058 | __be32 wwid[2]; | |
1059 | }__attribute__((packed, aligned (8))); | |
1060 | ||
1061 | struct ipr_hostrcb_fabric_desc { | |
1062 | __be16 length; | |
1063 | u8 ioa_port; | |
1064 | u8 cascaded_expander; | |
1065 | u8 phy; | |
1066 | u8 path_state; | |
1067 | #define IPR_PATH_ACTIVE_MASK 0xC0 | |
1068 | #define IPR_PATH_NO_INFO 0x00 | |
1069 | #define IPR_PATH_ACTIVE 0x40 | |
1070 | #define IPR_PATH_NOT_ACTIVE 0x80 | |
1071 | ||
1072 | #define IPR_PATH_STATE_MASK 0x0F | |
1073 | #define IPR_PATH_STATE_NO_INFO 0x00 | |
1074 | #define IPR_PATH_HEALTHY 0x01 | |
1075 | #define IPR_PATH_DEGRADED 0x02 | |
1076 | #define IPR_PATH_FAILED 0x03 | |
1077 | ||
1078 | __be16 num_entries; | |
1079 | struct ipr_hostrcb_config_element elem[1]; | |
1080 | }__attribute__((packed, aligned (4))); | |
1081 | ||
1082 | struct ipr_hostrcb64_fabric_desc { | |
1083 | __be16 length; | |
1084 | u8 descriptor_id; | |
1085 | ||
1086 | u8 reserved[2]; | |
1087 | u8 path_state; | |
1088 | ||
1089 | u8 reserved2[2]; | |
1090 | u8 res_path[8]; | |
1091 | u8 reserved3[6]; | |
1092 | __be16 num_entries; | |
1093 | struct ipr_hostrcb64_config_element elem[1]; | |
1094 | }__attribute__((packed, aligned (8))); | |
1095 | ||
1096 | #define for_each_hrrq(hrrq, ioa_cfg) \ | |
1097 | for (hrrq = (ioa_cfg)->hrrq; \ | |
1098 | hrrq < ((ioa_cfg)->hrrq + (ioa_cfg)->hrrq_num); hrrq++) | |
1099 | ||
1100 | #define for_each_fabric_cfg(fabric, cfg) \ | |
1101 | for (cfg = (fabric)->elem; \ | |
1102 | cfg < ((fabric)->elem + be16_to_cpu((fabric)->num_entries)); \ | |
1103 | cfg++) | |
1104 | ||
1105 | struct ipr_hostrcb_type_20_error { | |
1106 | u8 failure_reason[64]; | |
1107 | u8 reserved[3]; | |
1108 | u8 num_entries; | |
1109 | struct ipr_hostrcb_fabric_desc desc[1]; | |
1110 | }__attribute__((packed, aligned (4))); | |
1111 | ||
1112 | struct ipr_hostrcb_type_30_error { | |
1113 | u8 failure_reason[64]; | |
1114 | u8 reserved[3]; | |
1115 | u8 num_entries; | |
1116 | struct ipr_hostrcb64_fabric_desc desc[1]; | |
1117 | }__attribute__((packed, aligned (4))); | |
1118 | ||
1119 | struct ipr_hostrcb_error { | |
1120 | __be32 fd_ioasc; | |
1121 | struct ipr_res_addr fd_res_addr; | |
1122 | __be32 fd_res_handle; | |
1123 | __be32 prc; | |
1124 | union { | |
1125 | struct ipr_hostrcb_type_ff_error type_ff_error; | |
1126 | struct ipr_hostrcb_type_01_error type_01_error; | |
1127 | struct ipr_hostrcb_type_02_error type_02_error; | |
1128 | struct ipr_hostrcb_type_03_error type_03_error; | |
1129 | struct ipr_hostrcb_type_04_error type_04_error; | |
1130 | struct ipr_hostrcb_type_07_error type_07_error; | |
1131 | struct ipr_hostrcb_type_12_error type_12_error; | |
1132 | struct ipr_hostrcb_type_13_error type_13_error; | |
1133 | struct ipr_hostrcb_type_14_error type_14_error; | |
1134 | struct ipr_hostrcb_type_17_error type_17_error; | |
1135 | struct ipr_hostrcb_type_20_error type_20_error; | |
1136 | } u; | |
1137 | }__attribute__((packed, aligned (4))); | |
1138 | ||
1139 | struct ipr_hostrcb64_error { | |
1140 | __be32 fd_ioasc; | |
1141 | __be32 ioa_fw_level; | |
1142 | __be32 fd_res_handle; | |
1143 | __be32 prc; | |
1144 | __be64 fd_dev_id; | |
1145 | __be64 fd_lun; | |
1146 | u8 fd_res_path[8]; | |
1147 | __be64 time_stamp; | |
1148 | u8 reserved[16]; | |
1149 | union { | |
1150 | struct ipr_hostrcb_type_ff_error type_ff_error; | |
1151 | struct ipr_hostrcb_type_12_error type_12_error; | |
1152 | struct ipr_hostrcb_type_17_error type_17_error; | |
1153 | struct ipr_hostrcb_type_21_error type_21_error; | |
1154 | struct ipr_hostrcb_type_23_error type_23_error; | |
1155 | struct ipr_hostrcb_type_24_error type_24_error; | |
1156 | struct ipr_hostrcb_type_30_error type_30_error; | |
1157 | } u; | |
1158 | }__attribute__((packed, aligned (8))); | |
1159 | ||
1160 | struct ipr_hostrcb_raw { | |
1161 | __be32 data[sizeof(struct ipr_hostrcb_error)/sizeof(__be32)]; | |
1162 | }__attribute__((packed, aligned (4))); | |
1163 | ||
1164 | struct ipr_hcam { | |
1165 | u8 op_code; | |
1166 | #define IPR_HOST_RCB_OP_CODE_CONFIG_CHANGE 0xE1 | |
1167 | #define IPR_HOST_RCB_OP_CODE_LOG_DATA 0xE2 | |
1168 | ||
1169 | u8 notify_type; | |
1170 | #define IPR_HOST_RCB_NOTIF_TYPE_EXISTING_CHANGED 0x00 | |
1171 | #define IPR_HOST_RCB_NOTIF_TYPE_NEW_ENTRY 0x01 | |
1172 | #define IPR_HOST_RCB_NOTIF_TYPE_REM_ENTRY 0x02 | |
1173 | #define IPR_HOST_RCB_NOTIF_TYPE_ERROR_LOG_ENTRY 0x10 | |
1174 | #define IPR_HOST_RCB_NOTIF_TYPE_INFORMATION_ENTRY 0x11 | |
1175 | ||
1176 | u8 notifications_lost; | |
1177 | #define IPR_HOST_RCB_NO_NOTIFICATIONS_LOST 0 | |
1178 | #define IPR_HOST_RCB_NOTIFICATIONS_LOST 0x80 | |
1179 | ||
1180 | u8 flags; | |
1181 | #define IPR_HOSTRCB_INTERNAL_OPER 0x80 | |
1182 | #define IPR_HOSTRCB_ERR_RESP_SENT 0x40 | |
1183 | ||
1184 | u8 overlay_id; | |
1185 | #define IPR_HOST_RCB_OVERLAY_ID_1 0x01 | |
1186 | #define IPR_HOST_RCB_OVERLAY_ID_2 0x02 | |
1187 | #define IPR_HOST_RCB_OVERLAY_ID_3 0x03 | |
1188 | #define IPR_HOST_RCB_OVERLAY_ID_4 0x04 | |
1189 | #define IPR_HOST_RCB_OVERLAY_ID_6 0x06 | |
1190 | #define IPR_HOST_RCB_OVERLAY_ID_7 0x07 | |
1191 | #define IPR_HOST_RCB_OVERLAY_ID_12 0x12 | |
1192 | #define IPR_HOST_RCB_OVERLAY_ID_13 0x13 | |
1193 | #define IPR_HOST_RCB_OVERLAY_ID_14 0x14 | |
1194 | #define IPR_HOST_RCB_OVERLAY_ID_16 0x16 | |
1195 | #define IPR_HOST_RCB_OVERLAY_ID_17 0x17 | |
1196 | #define IPR_HOST_RCB_OVERLAY_ID_20 0x20 | |
1197 | #define IPR_HOST_RCB_OVERLAY_ID_21 0x21 | |
1198 | #define IPR_HOST_RCB_OVERLAY_ID_23 0x23 | |
1199 | #define IPR_HOST_RCB_OVERLAY_ID_24 0x24 | |
1200 | #define IPR_HOST_RCB_OVERLAY_ID_26 0x26 | |
1201 | #define IPR_HOST_RCB_OVERLAY_ID_30 0x30 | |
1202 | #define IPR_HOST_RCB_OVERLAY_ID_DEFAULT 0xFF | |
1203 | ||
1204 | u8 reserved1[3]; | |
1205 | __be32 ilid; | |
1206 | __be32 time_since_last_ioa_reset; | |
1207 | __be32 reserved2; | |
1208 | __be32 length; | |
1209 | ||
1210 | union { | |
1211 | struct ipr_hostrcb_error error; | |
1212 | struct ipr_hostrcb64_error error64; | |
1213 | struct ipr_hostrcb_cfg_ch_not ccn; | |
1214 | struct ipr_hostrcb_raw raw; | |
1215 | } u; | |
1216 | }__attribute__((packed, aligned (4))); | |
1217 | ||
1218 | struct ipr_hostrcb { | |
1219 | struct ipr_hcam hcam; | |
1220 | dma_addr_t hostrcb_dma; | |
1221 | struct list_head queue; | |
1222 | struct ipr_ioa_cfg *ioa_cfg; | |
1223 | char rp_buffer[IPR_MAX_RES_PATH_LENGTH]; | |
1224 | }; | |
1225 | ||
1226 | /* IPR smart dump table structures */ | |
1227 | struct ipr_sdt_entry { | |
1228 | __be32 start_token; | |
1229 | __be32 end_token; | |
1230 | u8 reserved[4]; | |
1231 | ||
1232 | u8 flags; | |
1233 | #define IPR_SDT_ENDIAN 0x80 | |
1234 | #define IPR_SDT_VALID_ENTRY 0x20 | |
1235 | ||
1236 | u8 resv; | |
1237 | __be16 priority; | |
1238 | }__attribute__((packed, aligned (4))); | |
1239 | ||
1240 | struct ipr_sdt_header { | |
1241 | __be32 state; | |
1242 | __be32 num_entries; | |
1243 | __be32 num_entries_used; | |
1244 | __be32 dump_size; | |
1245 | }__attribute__((packed, aligned (4))); | |
1246 | ||
1247 | struct ipr_sdt { | |
1248 | struct ipr_sdt_header hdr; | |
1249 | struct ipr_sdt_entry entry[IPR_FMT3_NUM_SDT_ENTRIES]; | |
1250 | }__attribute__((packed, aligned (4))); | |
1251 | ||
1252 | struct ipr_uc_sdt { | |
1253 | struct ipr_sdt_header hdr; | |
1254 | struct ipr_sdt_entry entry[1]; | |
1255 | }__attribute__((packed, aligned (4))); | |
1256 | ||
1257 | /* | |
1258 | * Driver types | |
1259 | */ | |
1260 | struct ipr_bus_attributes { | |
1261 | u8 bus; | |
1262 | u8 qas_enabled; | |
1263 | u8 bus_width; | |
1264 | u8 reserved; | |
1265 | u32 max_xfer_rate; | |
1266 | }; | |
1267 | ||
1268 | struct ipr_sata_port { | |
1269 | struct ipr_ioa_cfg *ioa_cfg; | |
1270 | struct ata_port *ap; | |
1271 | struct ipr_resource_entry *res; | |
1272 | struct ipr_ioasa_gata ioasa; | |
1273 | }; | |
1274 | ||
1275 | struct ipr_resource_entry { | |
1276 | u8 needs_sync_complete:1; | |
1277 | u8 in_erp:1; | |
1278 | u8 add_to_ml:1; | |
1279 | u8 del_from_ml:1; | |
1280 | u8 resetting_device:1; | |
1281 | u8 reset_occurred:1; | |
1282 | u8 raw_mode:1; | |
1283 | ||
1284 | u32 bus; /* AKA channel */ | |
1285 | u32 target; /* AKA id */ | |
1286 | u32 lun; | |
1287 | #define IPR_ARRAY_VIRTUAL_BUS 0x1 | |
1288 | #define IPR_VSET_VIRTUAL_BUS 0x2 | |
1289 | #define IPR_IOAFP_VIRTUAL_BUS 0x3 | |
1290 | ||
1291 | #define IPR_GET_RES_PHYS_LOC(res) \ | |
1292 | (((res)->bus << 24) | ((res)->target << 8) | (res)->lun) | |
1293 | ||
1294 | u8 ata_class; | |
1295 | u8 type; | |
1296 | ||
1297 | u16 flags; | |
1298 | u16 res_flags; | |
1299 | ||
1300 | u8 qmodel; | |
1301 | struct ipr_std_inq_data std_inq_data; | |
1302 | ||
1303 | __be32 res_handle; | |
1304 | __be64 dev_id; | |
1305 | u64 lun_wwn; | |
1306 | struct scsi_lun dev_lun; | |
1307 | u8 res_path[8]; | |
1308 | ||
1309 | struct ipr_ioa_cfg *ioa_cfg; | |
1310 | struct scsi_device *sdev; | |
1311 | struct ipr_sata_port *sata_port; | |
1312 | struct list_head queue; | |
1313 | }; /* struct ipr_resource_entry */ | |
1314 | ||
1315 | struct ipr_resource_hdr { | |
1316 | u16 num_entries; | |
1317 | u16 reserved; | |
1318 | }; | |
1319 | ||
1320 | struct ipr_misc_cbs { | |
1321 | struct ipr_ioa_vpd ioa_vpd; | |
1322 | struct ipr_inquiry_page0 page0_data; | |
1323 | struct ipr_inquiry_page3 page3_data; | |
1324 | struct ipr_inquiry_cap cap; | |
1325 | struct ipr_mode_pages mode_pages; | |
1326 | struct ipr_supported_device supp_dev; | |
1327 | }; | |
1328 | ||
1329 | struct ipr_interrupt_offsets { | |
1330 | unsigned long set_interrupt_mask_reg; | |
1331 | unsigned long clr_interrupt_mask_reg; | |
1332 | unsigned long clr_interrupt_mask_reg32; | |
1333 | unsigned long sense_interrupt_mask_reg; | |
1334 | unsigned long sense_interrupt_mask_reg32; | |
1335 | unsigned long clr_interrupt_reg; | |
1336 | unsigned long clr_interrupt_reg32; | |
1337 | ||
1338 | unsigned long sense_interrupt_reg; | |
1339 | unsigned long sense_interrupt_reg32; | |
1340 | unsigned long ioarrin_reg; | |
1341 | unsigned long sense_uproc_interrupt_reg; | |
1342 | unsigned long sense_uproc_interrupt_reg32; | |
1343 | unsigned long set_uproc_interrupt_reg; | |
1344 | unsigned long set_uproc_interrupt_reg32; | |
1345 | unsigned long clr_uproc_interrupt_reg; | |
1346 | unsigned long clr_uproc_interrupt_reg32; | |
1347 | ||
1348 | unsigned long init_feedback_reg; | |
1349 | ||
1350 | unsigned long dump_addr_reg; | |
1351 | unsigned long dump_data_reg; | |
1352 | ||
1353 | #define IPR_ENDIAN_SWAP_KEY 0x00080800 | |
1354 | unsigned long endian_swap_reg; | |
1355 | }; | |
1356 | ||
1357 | struct ipr_interrupts { | |
1358 | void __iomem *set_interrupt_mask_reg; | |
1359 | void __iomem *clr_interrupt_mask_reg; | |
1360 | void __iomem *clr_interrupt_mask_reg32; | |
1361 | void __iomem *sense_interrupt_mask_reg; | |
1362 | void __iomem *sense_interrupt_mask_reg32; | |
1363 | void __iomem *clr_interrupt_reg; | |
1364 | void __iomem *clr_interrupt_reg32; | |
1365 | ||
1366 | void __iomem *sense_interrupt_reg; | |
1367 | void __iomem *sense_interrupt_reg32; | |
1368 | void __iomem *ioarrin_reg; | |
1369 | void __iomem *sense_uproc_interrupt_reg; | |
1370 | void __iomem *sense_uproc_interrupt_reg32; | |
1371 | void __iomem *set_uproc_interrupt_reg; | |
1372 | void __iomem *set_uproc_interrupt_reg32; | |
1373 | void __iomem *clr_uproc_interrupt_reg; | |
1374 | void __iomem *clr_uproc_interrupt_reg32; | |
1375 | ||
1376 | void __iomem *init_feedback_reg; | |
1377 | ||
1378 | void __iomem *dump_addr_reg; | |
1379 | void __iomem *dump_data_reg; | |
1380 | ||
1381 | void __iomem *endian_swap_reg; | |
1382 | }; | |
1383 | ||
1384 | struct ipr_chip_cfg_t { | |
1385 | u32 mailbox; | |
1386 | u16 max_cmds; | |
1387 | u8 cache_line_size; | |
1388 | u8 clear_isr; | |
1389 | u32 iopoll_weight; | |
1390 | struct ipr_interrupt_offsets regs; | |
1391 | }; | |
1392 | ||
1393 | struct ipr_chip_t { | |
1394 | u16 vendor; | |
1395 | u16 device; | |
1396 | u16 intr_type; | |
1397 | #define IPR_USE_LSI 0x00 | |
1398 | #define IPR_USE_MSI 0x01 | |
1399 | #define IPR_USE_MSIX 0x02 | |
1400 | u16 sis_type; | |
1401 | #define IPR_SIS32 0x00 | |
1402 | #define IPR_SIS64 0x01 | |
1403 | u16 bist_method; | |
1404 | #define IPR_PCI_CFG 0x00 | |
1405 | #define IPR_MMIO 0x01 | |
1406 | const struct ipr_chip_cfg_t *cfg; | |
1407 | }; | |
1408 | ||
1409 | enum ipr_shutdown_type { | |
1410 | IPR_SHUTDOWN_NORMAL = 0x00, | |
1411 | IPR_SHUTDOWN_PREPARE_FOR_NORMAL = 0x40, | |
1412 | IPR_SHUTDOWN_ABBREV = 0x80, | |
1413 | IPR_SHUTDOWN_NONE = 0x100, | |
1414 | IPR_SHUTDOWN_QUIESCE = 0x101, | |
1415 | }; | |
1416 | ||
1417 | struct ipr_trace_entry { | |
1418 | u32 time; | |
1419 | ||
1420 | u8 op_code; | |
1421 | u8 ata_op_code; | |
1422 | u8 type; | |
1423 | #define IPR_TRACE_START 0x00 | |
1424 | #define IPR_TRACE_FINISH 0xff | |
1425 | u8 cmd_index; | |
1426 | ||
1427 | __be32 res_handle; | |
1428 | union { | |
1429 | u32 ioasc; | |
1430 | u32 add_data; | |
1431 | u32 res_addr; | |
1432 | } u; | |
1433 | }; | |
1434 | ||
1435 | struct ipr_sglist { | |
1436 | u32 order; | |
1437 | u32 num_sg; | |
1438 | u32 num_dma_sg; | |
1439 | u32 buffer_len; | |
1440 | struct scatterlist scatterlist[1]; | |
1441 | }; | |
1442 | ||
1443 | enum ipr_sdt_state { | |
1444 | INACTIVE, | |
1445 | WAIT_FOR_DUMP, | |
1446 | GET_DUMP, | |
1447 | READ_DUMP, | |
1448 | ABORT_DUMP, | |
1449 | DUMP_OBTAINED | |
1450 | }; | |
1451 | ||
1452 | /* Per-controller data */ | |
1453 | struct ipr_ioa_cfg { | |
1454 | char eye_catcher[8]; | |
1455 | #define IPR_EYECATCHER "iprcfg" | |
1456 | ||
1457 | struct list_head queue; | |
1458 | ||
1459 | u8 in_reset_reload:1; | |
1460 | u8 in_ioa_bringdown:1; | |
1461 | u8 ioa_unit_checked:1; | |
1462 | u8 dump_taken:1; | |
1463 | u8 scan_done:1; | |
1464 | u8 needs_hard_reset:1; | |
1465 | u8 dual_raid:1; | |
1466 | u8 needs_warm_reset:1; | |
1467 | u8 msi_received:1; | |
1468 | u8 sis64:1; | |
1469 | u8 dump_timeout:1; | |
1470 | u8 cfg_locked:1; | |
1471 | u8 clear_isr:1; | |
1472 | u8 probe_done:1; | |
1473 | ||
1474 | u8 revid; | |
1475 | ||
1476 | /* | |
1477 | * Bitmaps for SIS64 generated target values | |
1478 | */ | |
1479 | unsigned long target_ids[BITS_TO_LONGS(IPR_MAX_SIS64_DEVS)]; | |
1480 | unsigned long array_ids[BITS_TO_LONGS(IPR_MAX_SIS64_DEVS)]; | |
1481 | unsigned long vset_ids[BITS_TO_LONGS(IPR_MAX_SIS64_DEVS)]; | |
1482 | ||
1483 | u16 type; /* CCIN of the card */ | |
1484 | ||
1485 | u8 log_level; | |
1486 | #define IPR_MAX_LOG_LEVEL 4 | |
1487 | #define IPR_DEFAULT_LOG_LEVEL 2 | |
1488 | ||
1489 | #define IPR_NUM_TRACE_INDEX_BITS 8 | |
1490 | #define IPR_NUM_TRACE_ENTRIES (1 << IPR_NUM_TRACE_INDEX_BITS) | |
1491 | #define IPR_TRACE_INDEX_MASK (IPR_NUM_TRACE_ENTRIES - 1) | |
1492 | #define IPR_TRACE_SIZE (sizeof(struct ipr_trace_entry) * IPR_NUM_TRACE_ENTRIES) | |
1493 | char trace_start[8]; | |
1494 | #define IPR_TRACE_START_LABEL "trace" | |
1495 | struct ipr_trace_entry *trace; | |
1496 | atomic_t trace_index; | |
1497 | ||
1498 | char cfg_table_start[8]; | |
1499 | #define IPR_CFG_TBL_START "cfg" | |
1500 | union { | |
1501 | struct ipr_config_table *cfg_table; | |
1502 | struct ipr_config_table64 *cfg_table64; | |
1503 | } u; | |
1504 | dma_addr_t cfg_table_dma; | |
1505 | u32 cfg_table_size; | |
1506 | u32 max_devs_supported; | |
1507 | ||
1508 | char resource_table_label[8]; | |
1509 | #define IPR_RES_TABLE_LABEL "res_tbl" | |
1510 | struct ipr_resource_entry *res_entries; | |
1511 | struct list_head free_res_q; | |
1512 | struct list_head used_res_q; | |
1513 | ||
1514 | char ipr_hcam_label[8]; | |
1515 | #define IPR_HCAM_LABEL "hcams" | |
1516 | struct ipr_hostrcb *hostrcb[IPR_NUM_HCAMS]; | |
1517 | dma_addr_t hostrcb_dma[IPR_NUM_HCAMS]; | |
1518 | struct list_head hostrcb_free_q; | |
1519 | struct list_head hostrcb_pending_q; | |
1520 | ||
1521 | struct ipr_hrr_queue hrrq[IPR_MAX_HRRQ_NUM]; | |
1522 | u32 hrrq_num; | |
1523 | atomic_t hrrq_index; | |
1524 | u16 identify_hrrq_index; | |
1525 | ||
1526 | struct ipr_bus_attributes bus_attr[IPR_MAX_NUM_BUSES]; | |
1527 | ||
1528 | unsigned int transop_timeout; | |
1529 | const struct ipr_chip_cfg_t *chip_cfg; | |
1530 | const struct ipr_chip_t *ipr_chip; | |
1531 | ||
1532 | void __iomem *hdw_dma_regs; /* iomapped PCI memory space */ | |
1533 | unsigned long hdw_dma_regs_pci; /* raw PCI memory space */ | |
1534 | void __iomem *ioa_mailbox; | |
1535 | struct ipr_interrupts regs; | |
1536 | ||
1537 | u16 saved_pcix_cmd_reg; | |
1538 | u16 reset_retries; | |
1539 | ||
1540 | u32 errors_logged; | |
1541 | u32 doorbell; | |
1542 | ||
1543 | struct Scsi_Host *host; | |
1544 | struct pci_dev *pdev; | |
1545 | struct ipr_sglist *ucode_sglist; | |
1546 | u8 saved_mode_page_len; | |
1547 | ||
1548 | struct work_struct work_q; | |
1549 | struct workqueue_struct *reset_work_q; | |
1550 | ||
1551 | wait_queue_head_t reset_wait_q; | |
1552 | wait_queue_head_t msi_wait_q; | |
1553 | wait_queue_head_t eeh_wait_q; | |
1554 | ||
1555 | struct ipr_dump *dump; | |
1556 | enum ipr_sdt_state sdt_state; | |
1557 | ||
1558 | struct ipr_misc_cbs *vpd_cbs; | |
1559 | dma_addr_t vpd_cbs_dma; | |
1560 | ||
1561 | struct dma_pool *ipr_cmd_pool; | |
1562 | ||
1563 | struct ipr_cmnd *reset_cmd; | |
1564 | int (*reset) (struct ipr_cmnd *); | |
1565 | ||
1566 | struct ata_host ata_host; | |
1567 | char ipr_cmd_label[8]; | |
1568 | #define IPR_CMD_LABEL "ipr_cmd" | |
1569 | u32 max_cmds; | |
1570 | struct ipr_cmnd **ipr_cmnd_list; | |
1571 | dma_addr_t *ipr_cmnd_list_dma; | |
1572 | ||
1573 | u16 intr_flag; | |
1574 | unsigned int nvectors; | |
1575 | ||
1576 | struct { | |
1577 | unsigned short vec; | |
1578 | char desc[22]; | |
1579 | } vectors_info[IPR_MAX_MSIX_VECTORS]; | |
1580 | ||
1581 | u32 iopoll_weight; | |
1582 | ||
1583 | }; /* struct ipr_ioa_cfg */ | |
1584 | ||
1585 | struct ipr_cmnd { | |
1586 | struct ipr_ioarcb ioarcb; | |
1587 | union { | |
1588 | struct ipr_ioadl_desc ioadl[IPR_NUM_IOADL_ENTRIES]; | |
1589 | struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES]; | |
1590 | struct ipr_ata64_ioadl ata_ioadl; | |
1591 | } i; | |
1592 | union { | |
1593 | struct ipr_ioasa ioasa; | |
1594 | struct ipr_ioasa64 ioasa64; | |
1595 | } s; | |
1596 | struct list_head queue; | |
1597 | struct scsi_cmnd *scsi_cmd; | |
1598 | struct ata_queued_cmd *qc; | |
1599 | struct completion completion; | |
1600 | struct timer_list timer; | |
1601 | struct work_struct work; | |
1602 | void (*fast_done) (struct ipr_cmnd *); | |
1603 | void (*done) (struct ipr_cmnd *); | |
1604 | int (*job_step) (struct ipr_cmnd *); | |
1605 | int (*job_step_failed) (struct ipr_cmnd *); | |
1606 | u16 cmd_index; | |
1607 | u8 sense_buffer[SCSI_SENSE_BUFFERSIZE]; | |
1608 | dma_addr_t sense_buffer_dma; | |
1609 | unsigned short dma_use_sg; | |
1610 | dma_addr_t dma_addr; | |
1611 | struct ipr_cmnd *sibling; | |
1612 | union { | |
1613 | enum ipr_shutdown_type shutdown_type; | |
1614 | struct ipr_hostrcb *hostrcb; | |
1615 | unsigned long time_left; | |
1616 | unsigned long scratch; | |
1617 | struct ipr_resource_entry *res; | |
1618 | struct scsi_device *sdev; | |
1619 | } u; | |
1620 | ||
1621 | struct completion *eh_comp; | |
1622 | struct ipr_hrr_queue *hrrq; | |
1623 | struct ipr_ioa_cfg *ioa_cfg; | |
1624 | }; | |
1625 | ||
1626 | struct ipr_ses_table_entry { | |
1627 | char product_id[17]; | |
1628 | char compare_product_id_byte[17]; | |
1629 | u32 max_bus_speed_limit; /* MB/sec limit for this backplane */ | |
1630 | }; | |
1631 | ||
1632 | struct ipr_dump_header { | |
1633 | u32 eye_catcher; | |
1634 | #define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2 | |
1635 | u32 len; | |
1636 | u32 num_entries; | |
1637 | u32 first_entry_offset; | |
1638 | u32 status; | |
1639 | #define IPR_DUMP_STATUS_SUCCESS 0 | |
1640 | #define IPR_DUMP_STATUS_QUAL_SUCCESS 2 | |
1641 | #define IPR_DUMP_STATUS_FAILED 0xffffffff | |
1642 | u32 os; | |
1643 | #define IPR_DUMP_OS_LINUX 0x4C4E5558 | |
1644 | u32 driver_name; | |
1645 | #define IPR_DUMP_DRIVER_NAME 0x49505232 | |
1646 | }__attribute__((packed, aligned (4))); | |
1647 | ||
1648 | struct ipr_dump_entry_header { | |
1649 | u32 eye_catcher; | |
1650 | #define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2 | |
1651 | u32 len; | |
1652 | u32 num_elems; | |
1653 | u32 offset; | |
1654 | u32 data_type; | |
1655 | #define IPR_DUMP_DATA_TYPE_ASCII 0x41534349 | |
1656 | #define IPR_DUMP_DATA_TYPE_BINARY 0x42494E41 | |
1657 | u32 id; | |
1658 | #define IPR_DUMP_IOA_DUMP_ID 0x494F4131 | |
1659 | #define IPR_DUMP_LOCATION_ID 0x4C4F4341 | |
1660 | #define IPR_DUMP_TRACE_ID 0x54524143 | |
1661 | #define IPR_DUMP_DRIVER_VERSION_ID 0x44525652 | |
1662 | #define IPR_DUMP_DRIVER_TYPE_ID 0x54595045 | |
1663 | #define IPR_DUMP_IOA_CTRL_BLK 0x494F4342 | |
1664 | #define IPR_DUMP_PEND_OPS 0x414F5053 | |
1665 | u32 status; | |
1666 | }__attribute__((packed, aligned (4))); | |
1667 | ||
1668 | struct ipr_dump_location_entry { | |
1669 | struct ipr_dump_entry_header hdr; | |
1670 | u8 location[20]; | |
1671 | }__attribute__((packed)); | |
1672 | ||
1673 | struct ipr_dump_trace_entry { | |
1674 | struct ipr_dump_entry_header hdr; | |
1675 | u32 trace[IPR_TRACE_SIZE / sizeof(u32)]; | |
1676 | }__attribute__((packed, aligned (4))); | |
1677 | ||
1678 | struct ipr_dump_version_entry { | |
1679 | struct ipr_dump_entry_header hdr; | |
1680 | u8 version[sizeof(IPR_DRIVER_VERSION)]; | |
1681 | }; | |
1682 | ||
1683 | struct ipr_dump_ioa_type_entry { | |
1684 | struct ipr_dump_entry_header hdr; | |
1685 | u32 type; | |
1686 | u32 fw_version; | |
1687 | }; | |
1688 | ||
1689 | struct ipr_driver_dump { | |
1690 | struct ipr_dump_header hdr; | |
1691 | struct ipr_dump_version_entry version_entry; | |
1692 | struct ipr_dump_location_entry location_entry; | |
1693 | struct ipr_dump_ioa_type_entry ioa_type_entry; | |
1694 | struct ipr_dump_trace_entry trace_entry; | |
1695 | }__attribute__((packed)); | |
1696 | ||
1697 | struct ipr_ioa_dump { | |
1698 | struct ipr_dump_entry_header hdr; | |
1699 | struct ipr_sdt sdt; | |
1700 | __be32 **ioa_data; | |
1701 | u32 reserved; | |
1702 | u32 next_page_index; | |
1703 | u32 page_offset; | |
1704 | u32 format; | |
1705 | }__attribute__((packed, aligned (4))); | |
1706 | ||
1707 | struct ipr_dump { | |
1708 | struct kref kref; | |
1709 | struct ipr_ioa_cfg *ioa_cfg; | |
1710 | struct ipr_driver_dump driver_dump; | |
1711 | struct ipr_ioa_dump ioa_dump; | |
1712 | }; | |
1713 | ||
1714 | struct ipr_error_table_t { | |
1715 | u32 ioasc; | |
1716 | int log_ioasa; | |
1717 | int log_hcam; | |
1718 | char *error; | |
1719 | }; | |
1720 | ||
1721 | struct ipr_software_inq_lid_info { | |
1722 | __be32 load_id; | |
1723 | __be32 timestamp[3]; | |
1724 | }__attribute__((packed, aligned (4))); | |
1725 | ||
1726 | struct ipr_ucode_image_header { | |
1727 | __be32 header_length; | |
1728 | __be32 lid_table_offset; | |
1729 | u8 major_release; | |
1730 | u8 card_type; | |
1731 | u8 minor_release[2]; | |
1732 | u8 reserved[20]; | |
1733 | char eyecatcher[16]; | |
1734 | __be32 num_lids; | |
1735 | struct ipr_software_inq_lid_info lid[1]; | |
1736 | }__attribute__((packed, aligned (4))); | |
1737 | ||
1738 | /* | |
1739 | * Macros | |
1740 | */ | |
1741 | #define IPR_DBG_CMD(CMD) if (ipr_debug) { CMD; } | |
1742 | ||
1743 | #ifdef CONFIG_SCSI_IPR_TRACE | |
1744 | #define ipr_create_trace_file(kobj, attr) sysfs_create_bin_file(kobj, attr) | |
1745 | #define ipr_remove_trace_file(kobj, attr) sysfs_remove_bin_file(kobj, attr) | |
1746 | #else | |
1747 | #define ipr_create_trace_file(kobj, attr) 0 | |
1748 | #define ipr_remove_trace_file(kobj, attr) do { } while(0) | |
1749 | #endif | |
1750 | ||
1751 | #ifdef CONFIG_SCSI_IPR_DUMP | |
1752 | #define ipr_create_dump_file(kobj, attr) sysfs_create_bin_file(kobj, attr) | |
1753 | #define ipr_remove_dump_file(kobj, attr) sysfs_remove_bin_file(kobj, attr) | |
1754 | #else | |
1755 | #define ipr_create_dump_file(kobj, attr) 0 | |
1756 | #define ipr_remove_dump_file(kobj, attr) do { } while(0) | |
1757 | #endif | |
1758 | ||
1759 | /* | |
1760 | * Error logging macros | |
1761 | */ | |
1762 | #define ipr_err(...) printk(KERN_ERR IPR_NAME ": "__VA_ARGS__) | |
1763 | #define ipr_info(...) printk(KERN_INFO IPR_NAME ": "__VA_ARGS__) | |
1764 | #define ipr_dbg(...) IPR_DBG_CMD(printk(KERN_INFO IPR_NAME ": "__VA_ARGS__)) | |
1765 | ||
1766 | #define ipr_res_printk(level, ioa_cfg, bus, target, lun, fmt, ...) \ | |
1767 | printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \ | |
1768 | bus, target, lun, ##__VA_ARGS__) | |
1769 | ||
1770 | #define ipr_res_err(ioa_cfg, res, fmt, ...) \ | |
1771 | ipr_res_printk(KERN_ERR, ioa_cfg, (res)->bus, (res)->target, (res)->lun, fmt, ##__VA_ARGS__) | |
1772 | ||
1773 | #define ipr_ra_printk(level, ioa_cfg, ra, fmt, ...) \ | |
1774 | printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \ | |
1775 | (ra).bus, (ra).target, (ra).lun, ##__VA_ARGS__) | |
1776 | ||
1777 | #define ipr_ra_err(ioa_cfg, ra, fmt, ...) \ | |
1778 | ipr_ra_printk(KERN_ERR, ioa_cfg, ra, fmt, ##__VA_ARGS__) | |
1779 | ||
1780 | #define ipr_phys_res_err(ioa_cfg, res, fmt, ...) \ | |
1781 | { \ | |
1782 | if ((res).bus >= IPR_MAX_NUM_BUSES) { \ | |
1783 | ipr_err(fmt": unknown\n", ##__VA_ARGS__); \ | |
1784 | } else { \ | |
1785 | ipr_err(fmt": %d:%d:%d:%d\n", \ | |
1786 | ##__VA_ARGS__, (ioa_cfg)->host->host_no, \ | |
1787 | (res).bus, (res).target, (res).lun); \ | |
1788 | } \ | |
1789 | } | |
1790 | ||
1791 | #define ipr_hcam_err(hostrcb, fmt, ...) \ | |
1792 | { \ | |
1793 | if (ipr_is_device(hostrcb)) { \ | |
1794 | if ((hostrcb)->ioa_cfg->sis64) { \ | |
1795 | printk(KERN_ERR IPR_NAME ": %s: " fmt, \ | |
1796 | ipr_format_res_path(hostrcb->ioa_cfg, \ | |
1797 | hostrcb->hcam.u.error64.fd_res_path, \ | |
1798 | hostrcb->rp_buffer, \ | |
1799 | sizeof(hostrcb->rp_buffer)), \ | |
1800 | __VA_ARGS__); \ | |
1801 | } else { \ | |
1802 | ipr_ra_err((hostrcb)->ioa_cfg, \ | |
1803 | (hostrcb)->hcam.u.error.fd_res_addr, \ | |
1804 | fmt, __VA_ARGS__); \ | |
1805 | } \ | |
1806 | } else { \ | |
1807 | dev_err(&(hostrcb)->ioa_cfg->pdev->dev, fmt, __VA_ARGS__); \ | |
1808 | } \ | |
1809 | } | |
1810 | ||
1811 | #define ipr_trace ipr_dbg("%s: %s: Line: %d\n",\ | |
1812 | __FILE__, __func__, __LINE__) | |
1813 | ||
1814 | #define ENTER IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Entering %s\n", __func__)) | |
1815 | #define LEAVE IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Leaving %s\n", __func__)) | |
1816 | ||
1817 | #define ipr_err_separator \ | |
1818 | ipr_err("----------------------------------------------------------\n") | |
1819 | ||
1820 | ||
1821 | /* | |
1822 | * Inlines | |
1823 | */ | |
1824 | ||
1825 | /** | |
1826 | * ipr_is_ioa_resource - Determine if a resource is the IOA | |
1827 | * @res: resource entry struct | |
1828 | * | |
1829 | * Return value: | |
1830 | * 1 if IOA / 0 if not IOA | |
1831 | **/ | |
1832 | static inline int ipr_is_ioa_resource(struct ipr_resource_entry *res) | |
1833 | { | |
1834 | return res->type == IPR_RES_TYPE_IOAFP; | |
1835 | } | |
1836 | ||
1837 | /** | |
1838 | * ipr_is_af_dasd_device - Determine if a resource is an AF DASD | |
1839 | * @res: resource entry struct | |
1840 | * | |
1841 | * Return value: | |
1842 | * 1 if AF DASD / 0 if not AF DASD | |
1843 | **/ | |
1844 | static inline int ipr_is_af_dasd_device(struct ipr_resource_entry *res) | |
1845 | { | |
1846 | return res->type == IPR_RES_TYPE_AF_DASD || | |
1847 | res->type == IPR_RES_TYPE_REMOTE_AF_DASD; | |
1848 | } | |
1849 | ||
1850 | /** | |
1851 | * ipr_is_vset_device - Determine if a resource is a VSET | |
1852 | * @res: resource entry struct | |
1853 | * | |
1854 | * Return value: | |
1855 | * 1 if VSET / 0 if not VSET | |
1856 | **/ | |
1857 | static inline int ipr_is_vset_device(struct ipr_resource_entry *res) | |
1858 | { | |
1859 | return res->type == IPR_RES_TYPE_VOLUME_SET; | |
1860 | } | |
1861 | ||
1862 | /** | |
1863 | * ipr_is_gscsi - Determine if a resource is a generic scsi resource | |
1864 | * @res: resource entry struct | |
1865 | * | |
1866 | * Return value: | |
1867 | * 1 if GSCSI / 0 if not GSCSI | |
1868 | **/ | |
1869 | static inline int ipr_is_gscsi(struct ipr_resource_entry *res) | |
1870 | { | |
1871 | return res->type == IPR_RES_TYPE_GENERIC_SCSI; | |
1872 | } | |
1873 | ||
1874 | /** | |
1875 | * ipr_is_scsi_disk - Determine if a resource is a SCSI disk | |
1876 | * @res: resource entry struct | |
1877 | * | |
1878 | * Return value: | |
1879 | * 1 if SCSI disk / 0 if not SCSI disk | |
1880 | **/ | |
1881 | static inline int ipr_is_scsi_disk(struct ipr_resource_entry *res) | |
1882 | { | |
1883 | if (ipr_is_af_dasd_device(res) || | |
1884 | (ipr_is_gscsi(res) && IPR_IS_DASD_DEVICE(res->std_inq_data))) | |
1885 | return 1; | |
1886 | else | |
1887 | return 0; | |
1888 | } | |
1889 | ||
1890 | /** | |
1891 | * ipr_is_gata - Determine if a resource is a generic ATA resource | |
1892 | * @res: resource entry struct | |
1893 | * | |
1894 | * Return value: | |
1895 | * 1 if GATA / 0 if not GATA | |
1896 | **/ | |
1897 | static inline int ipr_is_gata(struct ipr_resource_entry *res) | |
1898 | { | |
1899 | return res->type == IPR_RES_TYPE_GENERIC_ATA; | |
1900 | } | |
1901 | ||
1902 | /** | |
1903 | * ipr_is_naca_model - Determine if a resource is using NACA queueing model | |
1904 | * @res: resource entry struct | |
1905 | * | |
1906 | * Return value: | |
1907 | * 1 if NACA queueing model / 0 if not NACA queueing model | |
1908 | **/ | |
1909 | static inline int ipr_is_naca_model(struct ipr_resource_entry *res) | |
1910 | { | |
1911 | if (ipr_is_gscsi(res) && res->qmodel == IPR_QUEUE_NACA_MODEL) | |
1912 | return 1; | |
1913 | return 0; | |
1914 | } | |
1915 | ||
1916 | /** | |
1917 | * ipr_is_device - Determine if the hostrcb structure is related to a device | |
1918 | * @hostrcb: host resource control blocks struct | |
1919 | * | |
1920 | * Return value: | |
1921 | * 1 if AF / 0 if not AF | |
1922 | **/ | |
1923 | static inline int ipr_is_device(struct ipr_hostrcb *hostrcb) | |
1924 | { | |
1925 | struct ipr_res_addr *res_addr; | |
1926 | u8 *res_path; | |
1927 | ||
1928 | if (hostrcb->ioa_cfg->sis64) { | |
1929 | res_path = &hostrcb->hcam.u.error64.fd_res_path[0]; | |
1930 | if ((res_path[0] == 0x00 || res_path[0] == 0x80 || | |
1931 | res_path[0] == 0x81) && res_path[2] != 0xFF) | |
1932 | return 1; | |
1933 | } else { | |
1934 | res_addr = &hostrcb->hcam.u.error.fd_res_addr; | |
1935 | ||
1936 | if ((res_addr->bus < IPR_MAX_NUM_BUSES) && | |
1937 | (res_addr->target < (IPR_MAX_NUM_TARGETS_PER_BUS - 1))) | |
1938 | return 1; | |
1939 | } | |
1940 | return 0; | |
1941 | } | |
1942 | ||
1943 | /** | |
1944 | * ipr_sdt_is_fmt2 - Determine if a SDT address is in format 2 | |
1945 | * @sdt_word: SDT address | |
1946 | * | |
1947 | * Return value: | |
1948 | * 1 if format 2 / 0 if not | |
1949 | **/ | |
1950 | static inline int ipr_sdt_is_fmt2(u32 sdt_word) | |
1951 | { | |
1952 | u32 bar_sel = IPR_GET_FMT2_BAR_SEL(sdt_word); | |
1953 | ||
1954 | switch (bar_sel) { | |
1955 | case IPR_SDT_FMT2_BAR0_SEL: | |
1956 | case IPR_SDT_FMT2_BAR1_SEL: | |
1957 | case IPR_SDT_FMT2_BAR2_SEL: | |
1958 | case IPR_SDT_FMT2_BAR3_SEL: | |
1959 | case IPR_SDT_FMT2_BAR4_SEL: | |
1960 | case IPR_SDT_FMT2_BAR5_SEL: | |
1961 | case IPR_SDT_FMT2_EXP_ROM_SEL: | |
1962 | return 1; | |
1963 | }; | |
1964 | ||
1965 | return 0; | |
1966 | } | |
1967 | ||
1968 | #ifndef writeq | |
1969 | static inline void writeq(u64 val, void __iomem *addr) | |
1970 | { | |
1971 | writel(((u32) (val >> 32)), addr); | |
1972 | writel(((u32) (val)), (addr + 4)); | |
1973 | } | |
1974 | #endif | |
1975 | ||
1976 | #endif /* _IPR_H */ |