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1 | /* | |
2 | * QLogic Fibre Channel HBA Driver | |
3 | * Copyright (c) 2003-2014 QLogic Corporation | |
4 | * | |
5 | * See LICENSE.qla2xxx for copyright and licensing details. | |
6 | */ | |
7 | #include "qla_def.h" | |
8 | ||
9 | #include <linux/moduleparam.h> | |
10 | #include <linux/vmalloc.h> | |
11 | #include <linux/delay.h> | |
12 | #include <linux/kthread.h> | |
13 | #include <linux/mutex.h> | |
14 | #include <linux/kobject.h> | |
15 | #include <linux/slab.h> | |
16 | #include <scsi/scsi_tcq.h> | |
17 | #include <scsi/scsicam.h> | |
18 | #include <scsi/scsi_transport.h> | |
19 | #include <scsi/scsi_transport_fc.h> | |
20 | ||
21 | #include "qla_target.h" | |
22 | ||
23 | /* | |
24 | * Driver version | |
25 | */ | |
26 | char qla2x00_version_str[40]; | |
27 | ||
28 | static int apidev_major; | |
29 | ||
30 | /* | |
31 | * SRB allocation cache | |
32 | */ | |
33 | static struct kmem_cache *srb_cachep; | |
34 | ||
35 | /* | |
36 | * CT6 CTX allocation cache | |
37 | */ | |
38 | static struct kmem_cache *ctx_cachep; | |
39 | /* | |
40 | * error level for logging | |
41 | */ | |
42 | int ql_errlev = ql_log_all; | |
43 | ||
44 | static int ql2xenableclass2; | |
45 | module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR); | |
46 | MODULE_PARM_DESC(ql2xenableclass2, | |
47 | "Specify if Class 2 operations are supported from the very " | |
48 | "beginning. Default is 0 - class 2 not supported."); | |
49 | ||
50 | ||
51 | int ql2xlogintimeout = 20; | |
52 | module_param(ql2xlogintimeout, int, S_IRUGO); | |
53 | MODULE_PARM_DESC(ql2xlogintimeout, | |
54 | "Login timeout value in seconds."); | |
55 | ||
56 | int qlport_down_retry; | |
57 | module_param(qlport_down_retry, int, S_IRUGO); | |
58 | MODULE_PARM_DESC(qlport_down_retry, | |
59 | "Maximum number of command retries to a port that returns " | |
60 | "a PORT-DOWN status."); | |
61 | ||
62 | int ql2xplogiabsentdevice; | |
63 | module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR); | |
64 | MODULE_PARM_DESC(ql2xplogiabsentdevice, | |
65 | "Option to enable PLOGI to devices that are not present after " | |
66 | "a Fabric scan. This is needed for several broken switches. " | |
67 | "Default is 0 - no PLOGI. 1 - perfom PLOGI."); | |
68 | ||
69 | int ql2xloginretrycount = 0; | |
70 | module_param(ql2xloginretrycount, int, S_IRUGO); | |
71 | MODULE_PARM_DESC(ql2xloginretrycount, | |
72 | "Specify an alternate value for the NVRAM login retry count."); | |
73 | ||
74 | int ql2xallocfwdump = 1; | |
75 | module_param(ql2xallocfwdump, int, S_IRUGO); | |
76 | MODULE_PARM_DESC(ql2xallocfwdump, | |
77 | "Option to enable allocation of memory for a firmware dump " | |
78 | "during HBA initialization. Memory allocation requirements " | |
79 | "vary by ISP type. Default is 1 - allocate memory."); | |
80 | ||
81 | int ql2xextended_error_logging; | |
82 | module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); | |
83 | MODULE_PARM_DESC(ql2xextended_error_logging, | |
84 | "Option to enable extended error logging,\n" | |
85 | "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n" | |
86 | "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n" | |
87 | "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n" | |
88 | "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n" | |
89 | "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n" | |
90 | "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n" | |
91 | "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n" | |
92 | "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n" | |
93 | "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n" | |
94 | "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n" | |
95 | "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n" | |
96 | "\t\t0x1e400000 - Preferred value for capturing essential " | |
97 | "debug information (equivalent to old " | |
98 | "ql2xextended_error_logging=1).\n" | |
99 | "\t\tDo LOGICAL OR of the value to enable more than one level"); | |
100 | ||
101 | int ql2xshiftctondsd = 6; | |
102 | module_param(ql2xshiftctondsd, int, S_IRUGO); | |
103 | MODULE_PARM_DESC(ql2xshiftctondsd, | |
104 | "Set to control shifting of command type processing " | |
105 | "based on total number of SG elements."); | |
106 | ||
107 | int ql2xfdmienable=1; | |
108 | module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR); | |
109 | MODULE_PARM_DESC(ql2xfdmienable, | |
110 | "Enables FDMI registrations. " | |
111 | "0 - no FDMI. Default is 1 - perform FDMI."); | |
112 | ||
113 | #define MAX_Q_DEPTH 32 | |
114 | static int ql2xmaxqdepth = MAX_Q_DEPTH; | |
115 | module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR); | |
116 | MODULE_PARM_DESC(ql2xmaxqdepth, | |
117 | "Maximum queue depth to set for each LUN. " | |
118 | "Default is 32."); | |
119 | ||
120 | int ql2xenabledif = 2; | |
121 | module_param(ql2xenabledif, int, S_IRUGO); | |
122 | MODULE_PARM_DESC(ql2xenabledif, | |
123 | " Enable T10-CRC-DIF:\n" | |
124 | " Default is 2.\n" | |
125 | " 0 -- No DIF Support\n" | |
126 | " 1 -- Enable DIF for all types\n" | |
127 | " 2 -- Enable DIF for all types, except Type 0.\n"); | |
128 | ||
129 | int ql2xenablehba_err_chk = 2; | |
130 | module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR); | |
131 | MODULE_PARM_DESC(ql2xenablehba_err_chk, | |
132 | " Enable T10-CRC-DIF Error isolation by HBA:\n" | |
133 | " Default is 2.\n" | |
134 | " 0 -- Error isolation disabled\n" | |
135 | " 1 -- Error isolation enabled only for DIX Type 0\n" | |
136 | " 2 -- Error isolation enabled for all Types\n"); | |
137 | ||
138 | int ql2xiidmaenable=1; | |
139 | module_param(ql2xiidmaenable, int, S_IRUGO); | |
140 | MODULE_PARM_DESC(ql2xiidmaenable, | |
141 | "Enables iIDMA settings " | |
142 | "Default is 1 - perform iIDMA. 0 - no iIDMA."); | |
143 | ||
144 | int ql2xmaxqueues = 1; | |
145 | module_param(ql2xmaxqueues, int, S_IRUGO); | |
146 | MODULE_PARM_DESC(ql2xmaxqueues, | |
147 | "Enables MQ settings " | |
148 | "Default is 1 for single queue. Set it to number " | |
149 | "of queues in MQ mode."); | |
150 | ||
151 | int ql2xmultique_tag; | |
152 | module_param(ql2xmultique_tag, int, S_IRUGO); | |
153 | MODULE_PARM_DESC(ql2xmultique_tag, | |
154 | "Enables CPU affinity settings for the driver " | |
155 | "Default is 0 for no affinity of request and response IO. " | |
156 | "Set it to 1 to turn on the cpu affinity."); | |
157 | ||
158 | int ql2xfwloadbin; | |
159 | module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR); | |
160 | MODULE_PARM_DESC(ql2xfwloadbin, | |
161 | "Option to specify location from which to load ISP firmware:.\n" | |
162 | " 2 -- load firmware via the request_firmware() (hotplug).\n" | |
163 | " interface.\n" | |
164 | " 1 -- load firmware from flash.\n" | |
165 | " 0 -- use default semantics.\n"); | |
166 | ||
167 | int ql2xetsenable; | |
168 | module_param(ql2xetsenable, int, S_IRUGO); | |
169 | MODULE_PARM_DESC(ql2xetsenable, | |
170 | "Enables firmware ETS burst." | |
171 | "Default is 0 - skip ETS enablement."); | |
172 | ||
173 | int ql2xdbwr = 1; | |
174 | module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR); | |
175 | MODULE_PARM_DESC(ql2xdbwr, | |
176 | "Option to specify scheme for request queue posting.\n" | |
177 | " 0 -- Regular doorbell.\n" | |
178 | " 1 -- CAMRAM doorbell (faster).\n"); | |
179 | ||
180 | int ql2xtargetreset = 1; | |
181 | module_param(ql2xtargetreset, int, S_IRUGO); | |
182 | MODULE_PARM_DESC(ql2xtargetreset, | |
183 | "Enable target reset." | |
184 | "Default is 1 - use hw defaults."); | |
185 | ||
186 | int ql2xgffidenable; | |
187 | module_param(ql2xgffidenable, int, S_IRUGO); | |
188 | MODULE_PARM_DESC(ql2xgffidenable, | |
189 | "Enables GFF_ID checks of port type. " | |
190 | "Default is 0 - Do not use GFF_ID information."); | |
191 | ||
192 | int ql2xasynctmfenable; | |
193 | module_param(ql2xasynctmfenable, int, S_IRUGO); | |
194 | MODULE_PARM_DESC(ql2xasynctmfenable, | |
195 | "Enables issue of TM IOCBs asynchronously via IOCB mechanism" | |
196 | "Default is 0 - Issue TM IOCBs via mailbox mechanism."); | |
197 | ||
198 | int ql2xdontresethba; | |
199 | module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR); | |
200 | MODULE_PARM_DESC(ql2xdontresethba, | |
201 | "Option to specify reset behaviour.\n" | |
202 | " 0 (Default) -- Reset on failure.\n" | |
203 | " 1 -- Do not reset on failure.\n"); | |
204 | ||
205 | uint64_t ql2xmaxlun = MAX_LUNS; | |
206 | module_param(ql2xmaxlun, ullong, S_IRUGO); | |
207 | MODULE_PARM_DESC(ql2xmaxlun, | |
208 | "Defines the maximum LU number to register with the SCSI " | |
209 | "midlayer. Default is 65535."); | |
210 | ||
211 | int ql2xmdcapmask = 0x1F; | |
212 | module_param(ql2xmdcapmask, int, S_IRUGO); | |
213 | MODULE_PARM_DESC(ql2xmdcapmask, | |
214 | "Set the Minidump driver capture mask level. " | |
215 | "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F."); | |
216 | ||
217 | int ql2xmdenable = 1; | |
218 | module_param(ql2xmdenable, int, S_IRUGO); | |
219 | MODULE_PARM_DESC(ql2xmdenable, | |
220 | "Enable/disable MiniDump. " | |
221 | "0 - MiniDump disabled. " | |
222 | "1 (Default) - MiniDump enabled."); | |
223 | ||
224 | /* | |
225 | * SCSI host template entry points | |
226 | */ | |
227 | static int qla2xxx_slave_configure(struct scsi_device * device); | |
228 | static int qla2xxx_slave_alloc(struct scsi_device *); | |
229 | static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time); | |
230 | static void qla2xxx_scan_start(struct Scsi_Host *); | |
231 | static void qla2xxx_slave_destroy(struct scsi_device *); | |
232 | static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd); | |
233 | static int qla2xxx_eh_abort(struct scsi_cmnd *); | |
234 | static int qla2xxx_eh_device_reset(struct scsi_cmnd *); | |
235 | static int qla2xxx_eh_target_reset(struct scsi_cmnd *); | |
236 | static int qla2xxx_eh_bus_reset(struct scsi_cmnd *); | |
237 | static int qla2xxx_eh_host_reset(struct scsi_cmnd *); | |
238 | ||
239 | static int qla2x00_change_queue_depth(struct scsi_device *, int, int); | |
240 | static void qla2x00_clear_drv_active(struct qla_hw_data *); | |
241 | static void qla2x00_free_device(scsi_qla_host_t *); | |
242 | static void qla83xx_disable_laser(scsi_qla_host_t *vha); | |
243 | ||
244 | struct scsi_host_template qla2xxx_driver_template = { | |
245 | .module = THIS_MODULE, | |
246 | .name = QLA2XXX_DRIVER_NAME, | |
247 | .queuecommand = qla2xxx_queuecommand, | |
248 | ||
249 | .eh_abort_handler = qla2xxx_eh_abort, | |
250 | .eh_device_reset_handler = qla2xxx_eh_device_reset, | |
251 | .eh_target_reset_handler = qla2xxx_eh_target_reset, | |
252 | .eh_bus_reset_handler = qla2xxx_eh_bus_reset, | |
253 | .eh_host_reset_handler = qla2xxx_eh_host_reset, | |
254 | ||
255 | .slave_configure = qla2xxx_slave_configure, | |
256 | ||
257 | .slave_alloc = qla2xxx_slave_alloc, | |
258 | .slave_destroy = qla2xxx_slave_destroy, | |
259 | .scan_finished = qla2xxx_scan_finished, | |
260 | .scan_start = qla2xxx_scan_start, | |
261 | .change_queue_depth = qla2x00_change_queue_depth, | |
262 | .change_queue_type = scsi_change_queue_type, | |
263 | .this_id = -1, | |
264 | .cmd_per_lun = 3, | |
265 | .use_clustering = ENABLE_CLUSTERING, | |
266 | .sg_tablesize = SG_ALL, | |
267 | ||
268 | .max_sectors = 0xFFFF, | |
269 | .shost_attrs = qla2x00_host_attrs, | |
270 | ||
271 | .supported_mode = MODE_INITIATOR, | |
272 | .use_blk_tags = 1, | |
273 | }; | |
274 | ||
275 | static struct scsi_transport_template *qla2xxx_transport_template = NULL; | |
276 | struct scsi_transport_template *qla2xxx_transport_vport_template = NULL; | |
277 | ||
278 | /* TODO Convert to inlines | |
279 | * | |
280 | * Timer routines | |
281 | */ | |
282 | ||
283 | __inline__ void | |
284 | qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval) | |
285 | { | |
286 | init_timer(&vha->timer); | |
287 | vha->timer.expires = jiffies + interval * HZ; | |
288 | vha->timer.data = (unsigned long)vha; | |
289 | vha->timer.function = (void (*)(unsigned long))func; | |
290 | add_timer(&vha->timer); | |
291 | vha->timer_active = 1; | |
292 | } | |
293 | ||
294 | static inline void | |
295 | qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval) | |
296 | { | |
297 | /* Currently used for 82XX only. */ | |
298 | if (vha->device_flags & DFLG_DEV_FAILED) { | |
299 | ql_dbg(ql_dbg_timer, vha, 0x600d, | |
300 | "Device in a failed state, returning.\n"); | |
301 | return; | |
302 | } | |
303 | ||
304 | mod_timer(&vha->timer, jiffies + interval * HZ); | |
305 | } | |
306 | ||
307 | static __inline__ void | |
308 | qla2x00_stop_timer(scsi_qla_host_t *vha) | |
309 | { | |
310 | del_timer_sync(&vha->timer); | |
311 | vha->timer_active = 0; | |
312 | } | |
313 | ||
314 | static int qla2x00_do_dpc(void *data); | |
315 | ||
316 | static void qla2x00_rst_aen(scsi_qla_host_t *); | |
317 | ||
318 | static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t, | |
319 | struct req_que **, struct rsp_que **); | |
320 | static void qla2x00_free_fw_dump(struct qla_hw_data *); | |
321 | static void qla2x00_mem_free(struct qla_hw_data *); | |
322 | ||
323 | /* -------------------------------------------------------------------------- */ | |
324 | static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req, | |
325 | struct rsp_que *rsp) | |
326 | { | |
327 | scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); | |
328 | ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues, | |
329 | GFP_KERNEL); | |
330 | if (!ha->req_q_map) { | |
331 | ql_log(ql_log_fatal, vha, 0x003b, | |
332 | "Unable to allocate memory for request queue ptrs.\n"); | |
333 | goto fail_req_map; | |
334 | } | |
335 | ||
336 | ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues, | |
337 | GFP_KERNEL); | |
338 | if (!ha->rsp_q_map) { | |
339 | ql_log(ql_log_fatal, vha, 0x003c, | |
340 | "Unable to allocate memory for response queue ptrs.\n"); | |
341 | goto fail_rsp_map; | |
342 | } | |
343 | /* | |
344 | * Make sure we record at least the request and response queue zero in | |
345 | * case we need to free them if part of the probe fails. | |
346 | */ | |
347 | ha->rsp_q_map[0] = rsp; | |
348 | ha->req_q_map[0] = req; | |
349 | set_bit(0, ha->rsp_qid_map); | |
350 | set_bit(0, ha->req_qid_map); | |
351 | return 1; | |
352 | ||
353 | fail_rsp_map: | |
354 | kfree(ha->req_q_map); | |
355 | ha->req_q_map = NULL; | |
356 | fail_req_map: | |
357 | return -ENOMEM; | |
358 | } | |
359 | ||
360 | static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req) | |
361 | { | |
362 | if (IS_QLAFX00(ha)) { | |
363 | if (req && req->ring_fx00) | |
364 | dma_free_coherent(&ha->pdev->dev, | |
365 | (req->length_fx00 + 1) * sizeof(request_t), | |
366 | req->ring_fx00, req->dma_fx00); | |
367 | } else if (req && req->ring) | |
368 | dma_free_coherent(&ha->pdev->dev, | |
369 | (req->length + 1) * sizeof(request_t), | |
370 | req->ring, req->dma); | |
371 | ||
372 | if (req) | |
373 | kfree(req->outstanding_cmds); | |
374 | ||
375 | kfree(req); | |
376 | req = NULL; | |
377 | } | |
378 | ||
379 | static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp) | |
380 | { | |
381 | if (IS_QLAFX00(ha)) { | |
382 | if (rsp && rsp->ring) | |
383 | dma_free_coherent(&ha->pdev->dev, | |
384 | (rsp->length_fx00 + 1) * sizeof(request_t), | |
385 | rsp->ring_fx00, rsp->dma_fx00); | |
386 | } else if (rsp && rsp->ring) { | |
387 | dma_free_coherent(&ha->pdev->dev, | |
388 | (rsp->length + 1) * sizeof(response_t), | |
389 | rsp->ring, rsp->dma); | |
390 | } | |
391 | kfree(rsp); | |
392 | rsp = NULL; | |
393 | } | |
394 | ||
395 | static void qla2x00_free_queues(struct qla_hw_data *ha) | |
396 | { | |
397 | struct req_que *req; | |
398 | struct rsp_que *rsp; | |
399 | int cnt; | |
400 | ||
401 | for (cnt = 0; cnt < ha->max_req_queues; cnt++) { | |
402 | req = ha->req_q_map[cnt]; | |
403 | qla2x00_free_req_que(ha, req); | |
404 | } | |
405 | kfree(ha->req_q_map); | |
406 | ha->req_q_map = NULL; | |
407 | ||
408 | for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) { | |
409 | rsp = ha->rsp_q_map[cnt]; | |
410 | qla2x00_free_rsp_que(ha, rsp); | |
411 | } | |
412 | kfree(ha->rsp_q_map); | |
413 | ha->rsp_q_map = NULL; | |
414 | } | |
415 | ||
416 | static int qla25xx_setup_mode(struct scsi_qla_host *vha) | |
417 | { | |
418 | uint16_t options = 0; | |
419 | int ques, req, ret; | |
420 | struct qla_hw_data *ha = vha->hw; | |
421 | ||
422 | if (!(ha->fw_attributes & BIT_6)) { | |
423 | ql_log(ql_log_warn, vha, 0x00d8, | |
424 | "Firmware is not multi-queue capable.\n"); | |
425 | goto fail; | |
426 | } | |
427 | if (ql2xmultique_tag) { | |
428 | /* create a request queue for IO */ | |
429 | options |= BIT_7; | |
430 | req = qla25xx_create_req_que(ha, options, 0, 0, -1, | |
431 | QLA_DEFAULT_QUE_QOS); | |
432 | if (!req) { | |
433 | ql_log(ql_log_warn, vha, 0x00e0, | |
434 | "Failed to create request queue.\n"); | |
435 | goto fail; | |
436 | } | |
437 | ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1); | |
438 | vha->req = ha->req_q_map[req]; | |
439 | options |= BIT_1; | |
440 | for (ques = 1; ques < ha->max_rsp_queues; ques++) { | |
441 | ret = qla25xx_create_rsp_que(ha, options, 0, 0, req); | |
442 | if (!ret) { | |
443 | ql_log(ql_log_warn, vha, 0x00e8, | |
444 | "Failed to create response queue.\n"); | |
445 | goto fail2; | |
446 | } | |
447 | } | |
448 | ha->flags.cpu_affinity_enabled = 1; | |
449 | ql_dbg(ql_dbg_multiq, vha, 0xc007, | |
450 | "CPU affinity mode enalbed, " | |
451 | "no. of response queues:%d no. of request queues:%d.\n", | |
452 | ha->max_rsp_queues, ha->max_req_queues); | |
453 | ql_dbg(ql_dbg_init, vha, 0x00e9, | |
454 | "CPU affinity mode enalbed, " | |
455 | "no. of response queues:%d no. of request queues:%d.\n", | |
456 | ha->max_rsp_queues, ha->max_req_queues); | |
457 | } | |
458 | return 0; | |
459 | fail2: | |
460 | qla25xx_delete_queues(vha); | |
461 | destroy_workqueue(ha->wq); | |
462 | ha->wq = NULL; | |
463 | vha->req = ha->req_q_map[0]; | |
464 | fail: | |
465 | ha->mqenable = 0; | |
466 | kfree(ha->req_q_map); | |
467 | kfree(ha->rsp_q_map); | |
468 | ha->max_req_queues = ha->max_rsp_queues = 1; | |
469 | return 1; | |
470 | } | |
471 | ||
472 | static char * | |
473 | qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str) | |
474 | { | |
475 | struct qla_hw_data *ha = vha->hw; | |
476 | static char *pci_bus_modes[] = { | |
477 | "33", "66", "100", "133", | |
478 | }; | |
479 | uint16_t pci_bus; | |
480 | ||
481 | strcpy(str, "PCI"); | |
482 | pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9; | |
483 | if (pci_bus) { | |
484 | strcat(str, "-X ("); | |
485 | strcat(str, pci_bus_modes[pci_bus]); | |
486 | } else { | |
487 | pci_bus = (ha->pci_attr & BIT_8) >> 8; | |
488 | strcat(str, " ("); | |
489 | strcat(str, pci_bus_modes[pci_bus]); | |
490 | } | |
491 | strcat(str, " MHz)"); | |
492 | ||
493 | return (str); | |
494 | } | |
495 | ||
496 | static char * | |
497 | qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str) | |
498 | { | |
499 | static char *pci_bus_modes[] = { "33", "66", "100", "133", }; | |
500 | struct qla_hw_data *ha = vha->hw; | |
501 | uint32_t pci_bus; | |
502 | ||
503 | if (pci_is_pcie(ha->pdev)) { | |
504 | char lwstr[6]; | |
505 | uint32_t lstat, lspeed, lwidth; | |
506 | ||
507 | pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat); | |
508 | lspeed = lstat & PCI_EXP_LNKCAP_SLS; | |
509 | lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4; | |
510 | ||
511 | strcpy(str, "PCIe ("); | |
512 | switch (lspeed) { | |
513 | case 1: | |
514 | strcat(str, "2.5GT/s "); | |
515 | break; | |
516 | case 2: | |
517 | strcat(str, "5.0GT/s "); | |
518 | break; | |
519 | case 3: | |
520 | strcat(str, "8.0GT/s "); | |
521 | break; | |
522 | default: | |
523 | strcat(str, "<unknown> "); | |
524 | break; | |
525 | } | |
526 | snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth); | |
527 | strcat(str, lwstr); | |
528 | ||
529 | return str; | |
530 | } | |
531 | ||
532 | strcpy(str, "PCI"); | |
533 | pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8; | |
534 | if (pci_bus == 0 || pci_bus == 8) { | |
535 | strcat(str, " ("); | |
536 | strcat(str, pci_bus_modes[pci_bus >> 3]); | |
537 | } else { | |
538 | strcat(str, "-X "); | |
539 | if (pci_bus & BIT_2) | |
540 | strcat(str, "Mode 2"); | |
541 | else | |
542 | strcat(str, "Mode 1"); | |
543 | strcat(str, " ("); | |
544 | strcat(str, pci_bus_modes[pci_bus & ~BIT_2]); | |
545 | } | |
546 | strcat(str, " MHz)"); | |
547 | ||
548 | return str; | |
549 | } | |
550 | ||
551 | static char * | |
552 | qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) | |
553 | { | |
554 | char un_str[10]; | |
555 | struct qla_hw_data *ha = vha->hw; | |
556 | ||
557 | snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version, | |
558 | ha->fw_minor_version, ha->fw_subminor_version); | |
559 | ||
560 | if (ha->fw_attributes & BIT_9) { | |
561 | strcat(str, "FLX"); | |
562 | return (str); | |
563 | } | |
564 | ||
565 | switch (ha->fw_attributes & 0xFF) { | |
566 | case 0x7: | |
567 | strcat(str, "EF"); | |
568 | break; | |
569 | case 0x17: | |
570 | strcat(str, "TP"); | |
571 | break; | |
572 | case 0x37: | |
573 | strcat(str, "IP"); | |
574 | break; | |
575 | case 0x77: | |
576 | strcat(str, "VI"); | |
577 | break; | |
578 | default: | |
579 | sprintf(un_str, "(%x)", ha->fw_attributes); | |
580 | strcat(str, un_str); | |
581 | break; | |
582 | } | |
583 | if (ha->fw_attributes & 0x100) | |
584 | strcat(str, "X"); | |
585 | ||
586 | return (str); | |
587 | } | |
588 | ||
589 | static char * | |
590 | qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) | |
591 | { | |
592 | struct qla_hw_data *ha = vha->hw; | |
593 | ||
594 | snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version, | |
595 | ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes); | |
596 | return str; | |
597 | } | |
598 | ||
599 | void | |
600 | qla2x00_sp_free_dma(void *vha, void *ptr) | |
601 | { | |
602 | srb_t *sp = (srb_t *)ptr; | |
603 | struct scsi_cmnd *cmd = GET_CMD_SP(sp); | |
604 | struct qla_hw_data *ha = sp->fcport->vha->hw; | |
605 | void *ctx = GET_CMD_CTX_SP(sp); | |
606 | ||
607 | if (sp->flags & SRB_DMA_VALID) { | |
608 | scsi_dma_unmap(cmd); | |
609 | sp->flags &= ~SRB_DMA_VALID; | |
610 | } | |
611 | ||
612 | if (sp->flags & SRB_CRC_PROT_DMA_VALID) { | |
613 | dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), | |
614 | scsi_prot_sg_count(cmd), cmd->sc_data_direction); | |
615 | sp->flags &= ~SRB_CRC_PROT_DMA_VALID; | |
616 | } | |
617 | ||
618 | if (sp->flags & SRB_CRC_CTX_DSD_VALID) { | |
619 | /* List assured to be having elements */ | |
620 | qla2x00_clean_dsd_pool(ha, sp, NULL); | |
621 | sp->flags &= ~SRB_CRC_CTX_DSD_VALID; | |
622 | } | |
623 | ||
624 | if (sp->flags & SRB_CRC_CTX_DMA_VALID) { | |
625 | dma_pool_free(ha->dl_dma_pool, ctx, | |
626 | ((struct crc_context *)ctx)->crc_ctx_dma); | |
627 | sp->flags &= ~SRB_CRC_CTX_DMA_VALID; | |
628 | } | |
629 | ||
630 | if (sp->flags & SRB_FCP_CMND_DMA_VALID) { | |
631 | struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx; | |
632 | ||
633 | dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, | |
634 | ctx1->fcp_cmnd_dma); | |
635 | list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); | |
636 | ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; | |
637 | ha->gbl_dsd_avail += ctx1->dsd_use_cnt; | |
638 | mempool_free(ctx1, ha->ctx_mempool); | |
639 | ctx1 = NULL; | |
640 | } | |
641 | ||
642 | CMD_SP(cmd) = NULL; | |
643 | qla2x00_rel_sp(sp->fcport->vha, sp); | |
644 | } | |
645 | ||
646 | static void | |
647 | qla2x00_sp_compl(void *data, void *ptr, int res) | |
648 | { | |
649 | struct qla_hw_data *ha = (struct qla_hw_data *)data; | |
650 | srb_t *sp = (srb_t *)ptr; | |
651 | struct scsi_cmnd *cmd = GET_CMD_SP(sp); | |
652 | ||
653 | cmd->result = res; | |
654 | ||
655 | if (atomic_read(&sp->ref_count) == 0) { | |
656 | ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015, | |
657 | "SP reference-count to ZERO -- sp=%p cmd=%p.\n", | |
658 | sp, GET_CMD_SP(sp)); | |
659 | if (ql2xextended_error_logging & ql_dbg_io) | |
660 | BUG(); | |
661 | return; | |
662 | } | |
663 | if (!atomic_dec_and_test(&sp->ref_count)) | |
664 | return; | |
665 | ||
666 | qla2x00_sp_free_dma(ha, sp); | |
667 | cmd->scsi_done(cmd); | |
668 | } | |
669 | ||
670 | /* If we are SP1 here, we need to still take and release the host_lock as SP1 | |
671 | * does not have the changes necessary to avoid taking host->host_lock. | |
672 | */ | |
673 | static int | |
674 | qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) | |
675 | { | |
676 | scsi_qla_host_t *vha = shost_priv(host); | |
677 | fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; | |
678 | struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); | |
679 | struct qla_hw_data *ha = vha->hw; | |
680 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); | |
681 | srb_t *sp; | |
682 | int rval; | |
683 | ||
684 | if (ha->flags.eeh_busy) { | |
685 | if (ha->flags.pci_channel_io_perm_failure) { | |
686 | ql_dbg(ql_dbg_aer, vha, 0x9010, | |
687 | "PCI Channel IO permanent failure, exiting " | |
688 | "cmd=%p.\n", cmd); | |
689 | cmd->result = DID_NO_CONNECT << 16; | |
690 | } else { | |
691 | ql_dbg(ql_dbg_aer, vha, 0x9011, | |
692 | "EEH_Busy, Requeuing the cmd=%p.\n", cmd); | |
693 | cmd->result = DID_REQUEUE << 16; | |
694 | } | |
695 | goto qc24_fail_command; | |
696 | } | |
697 | ||
698 | rval = fc_remote_port_chkready(rport); | |
699 | if (rval) { | |
700 | cmd->result = rval; | |
701 | ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003, | |
702 | "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", | |
703 | cmd, rval); | |
704 | goto qc24_fail_command; | |
705 | } | |
706 | ||
707 | if (!vha->flags.difdix_supported && | |
708 | scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) { | |
709 | ql_dbg(ql_dbg_io, vha, 0x3004, | |
710 | "DIF Cap not reg, fail DIF capable cmd's:%p.\n", | |
711 | cmd); | |
712 | cmd->result = DID_NO_CONNECT << 16; | |
713 | goto qc24_fail_command; | |
714 | } | |
715 | ||
716 | if (!fcport) { | |
717 | cmd->result = DID_NO_CONNECT << 16; | |
718 | goto qc24_fail_command; | |
719 | } | |
720 | ||
721 | if (atomic_read(&fcport->state) != FCS_ONLINE) { | |
722 | if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || | |
723 | atomic_read(&base_vha->loop_state) == LOOP_DEAD) { | |
724 | ql_dbg(ql_dbg_io, vha, 0x3005, | |
725 | "Returning DNC, fcport_state=%d loop_state=%d.\n", | |
726 | atomic_read(&fcport->state), | |
727 | atomic_read(&base_vha->loop_state)); | |
728 | cmd->result = DID_NO_CONNECT << 16; | |
729 | goto qc24_fail_command; | |
730 | } | |
731 | goto qc24_target_busy; | |
732 | } | |
733 | ||
734 | /* | |
735 | * Return target busy if we've received a non-zero retry_delay_timer | |
736 | * in a FCP_RSP. | |
737 | */ | |
738 | if (time_after(jiffies, fcport->retry_delay_timestamp)) | |
739 | fcport->retry_delay_timestamp = 0; | |
740 | else | |
741 | goto qc24_target_busy; | |
742 | ||
743 | sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC); | |
744 | if (!sp) | |
745 | goto qc24_host_busy; | |
746 | ||
747 | sp->u.scmd.cmd = cmd; | |
748 | sp->type = SRB_SCSI_CMD; | |
749 | atomic_set(&sp->ref_count, 1); | |
750 | CMD_SP(cmd) = (void *)sp; | |
751 | sp->free = qla2x00_sp_free_dma; | |
752 | sp->done = qla2x00_sp_compl; | |
753 | ||
754 | rval = ha->isp_ops->start_scsi(sp); | |
755 | if (rval != QLA_SUCCESS) { | |
756 | ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013, | |
757 | "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); | |
758 | goto qc24_host_busy_free_sp; | |
759 | } | |
760 | ||
761 | return 0; | |
762 | ||
763 | qc24_host_busy_free_sp: | |
764 | qla2x00_sp_free_dma(ha, sp); | |
765 | ||
766 | qc24_host_busy: | |
767 | return SCSI_MLQUEUE_HOST_BUSY; | |
768 | ||
769 | qc24_target_busy: | |
770 | return SCSI_MLQUEUE_TARGET_BUSY; | |
771 | ||
772 | qc24_fail_command: | |
773 | cmd->scsi_done(cmd); | |
774 | ||
775 | return 0; | |
776 | } | |
777 | ||
778 | /* | |
779 | * qla2x00_eh_wait_on_command | |
780 | * Waits for the command to be returned by the Firmware for some | |
781 | * max time. | |
782 | * | |
783 | * Input: | |
784 | * cmd = Scsi Command to wait on. | |
785 | * | |
786 | * Return: | |
787 | * Not Found : 0 | |
788 | * Found : 1 | |
789 | */ | |
790 | static int | |
791 | qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd) | |
792 | { | |
793 | #define ABORT_POLLING_PERIOD 1000 | |
794 | #define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD)) | |
795 | unsigned long wait_iter = ABORT_WAIT_ITER; | |
796 | scsi_qla_host_t *vha = shost_priv(cmd->device->host); | |
797 | struct qla_hw_data *ha = vha->hw; | |
798 | int ret = QLA_SUCCESS; | |
799 | ||
800 | if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) { | |
801 | ql_dbg(ql_dbg_taskm, vha, 0x8005, | |
802 | "Return:eh_wait.\n"); | |
803 | return ret; | |
804 | } | |
805 | ||
806 | while (CMD_SP(cmd) && wait_iter--) { | |
807 | msleep(ABORT_POLLING_PERIOD); | |
808 | } | |
809 | if (CMD_SP(cmd)) | |
810 | ret = QLA_FUNCTION_FAILED; | |
811 | ||
812 | return ret; | |
813 | } | |
814 | ||
815 | /* | |
816 | * qla2x00_wait_for_hba_online | |
817 | * Wait till the HBA is online after going through | |
818 | * <= MAX_RETRIES_OF_ISP_ABORT or | |
819 | * finally HBA is disabled ie marked offline | |
820 | * | |
821 | * Input: | |
822 | * ha - pointer to host adapter structure | |
823 | * | |
824 | * Note: | |
825 | * Does context switching-Release SPIN_LOCK | |
826 | * (if any) before calling this routine. | |
827 | * | |
828 | * Return: | |
829 | * Success (Adapter is online) : 0 | |
830 | * Failed (Adapter is offline/disabled) : 1 | |
831 | */ | |
832 | int | |
833 | qla2x00_wait_for_hba_online(scsi_qla_host_t *vha) | |
834 | { | |
835 | int return_status; | |
836 | unsigned long wait_online; | |
837 | struct qla_hw_data *ha = vha->hw; | |
838 | scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); | |
839 | ||
840 | wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ); | |
841 | while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || | |
842 | test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || | |
843 | test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || | |
844 | ha->dpc_active) && time_before(jiffies, wait_online)) { | |
845 | ||
846 | msleep(1000); | |
847 | } | |
848 | if (base_vha->flags.online) | |
849 | return_status = QLA_SUCCESS; | |
850 | else | |
851 | return_status = QLA_FUNCTION_FAILED; | |
852 | ||
853 | return (return_status); | |
854 | } | |
855 | ||
856 | /* | |
857 | * qla2x00_wait_for_hba_ready | |
858 | * Wait till the HBA is ready before doing driver unload | |
859 | * | |
860 | * Input: | |
861 | * ha - pointer to host adapter structure | |
862 | * | |
863 | * Note: | |
864 | * Does context switching-Release SPIN_LOCK | |
865 | * (if any) before calling this routine. | |
866 | * | |
867 | */ | |
868 | static void | |
869 | qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha) | |
870 | { | |
871 | struct qla_hw_data *ha = vha->hw; | |
872 | ||
873 | while (((qla2x00_reset_active(vha)) || ha->dpc_active || | |
874 | ha->flags.mbox_busy) || | |
875 | test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) || | |
876 | test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) | |
877 | msleep(1000); | |
878 | } | |
879 | ||
880 | int | |
881 | qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha) | |
882 | { | |
883 | int return_status; | |
884 | unsigned long wait_reset; | |
885 | struct qla_hw_data *ha = vha->hw; | |
886 | scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); | |
887 | ||
888 | wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); | |
889 | while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || | |
890 | test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || | |
891 | test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || | |
892 | ha->dpc_active) && time_before(jiffies, wait_reset)) { | |
893 | ||
894 | msleep(1000); | |
895 | ||
896 | if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) && | |
897 | ha->flags.chip_reset_done) | |
898 | break; | |
899 | } | |
900 | if (ha->flags.chip_reset_done) | |
901 | return_status = QLA_SUCCESS; | |
902 | else | |
903 | return_status = QLA_FUNCTION_FAILED; | |
904 | ||
905 | return return_status; | |
906 | } | |
907 | ||
908 | static void | |
909 | sp_get(struct srb *sp) | |
910 | { | |
911 | atomic_inc(&sp->ref_count); | |
912 | } | |
913 | ||
914 | /************************************************************************** | |
915 | * qla2xxx_eh_abort | |
916 | * | |
917 | * Description: | |
918 | * The abort function will abort the specified command. | |
919 | * | |
920 | * Input: | |
921 | * cmd = Linux SCSI command packet to be aborted. | |
922 | * | |
923 | * Returns: | |
924 | * Either SUCCESS or FAILED. | |
925 | * | |
926 | * Note: | |
927 | * Only return FAILED if command not returned by firmware. | |
928 | **************************************************************************/ | |
929 | static int | |
930 | qla2xxx_eh_abort(struct scsi_cmnd *cmd) | |
931 | { | |
932 | scsi_qla_host_t *vha = shost_priv(cmd->device->host); | |
933 | srb_t *sp; | |
934 | int ret; | |
935 | unsigned int id; | |
936 | uint64_t lun; | |
937 | unsigned long flags; | |
938 | int rval, wait = 0; | |
939 | struct qla_hw_data *ha = vha->hw; | |
940 | ||
941 | if (!CMD_SP(cmd)) | |
942 | return SUCCESS; | |
943 | ||
944 | ret = fc_block_scsi_eh(cmd); | |
945 | if (ret != 0) | |
946 | return ret; | |
947 | ret = SUCCESS; | |
948 | ||
949 | id = cmd->device->id; | |
950 | lun = cmd->device->lun; | |
951 | ||
952 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
953 | sp = (srb_t *) CMD_SP(cmd); | |
954 | if (!sp) { | |
955 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
956 | return SUCCESS; | |
957 | } | |
958 | ||
959 | ql_dbg(ql_dbg_taskm, vha, 0x8002, | |
960 | "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p\n", | |
961 | vha->host_no, id, lun, sp, cmd); | |
962 | ||
963 | /* Get a reference to the sp and drop the lock.*/ | |
964 | sp_get(sp); | |
965 | ||
966 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
967 | rval = ha->isp_ops->abort_command(sp); | |
968 | if (rval) { | |
969 | if (rval == QLA_FUNCTION_PARAMETER_ERROR) { | |
970 | /* | |
971 | * Decrement the ref_count since we can't find the | |
972 | * command | |
973 | */ | |
974 | atomic_dec(&sp->ref_count); | |
975 | ret = SUCCESS; | |
976 | } else | |
977 | ret = FAILED; | |
978 | ||
979 | ql_dbg(ql_dbg_taskm, vha, 0x8003, | |
980 | "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval); | |
981 | } else { | |
982 | ql_dbg(ql_dbg_taskm, vha, 0x8004, | |
983 | "Abort command mbx success cmd=%p.\n", cmd); | |
984 | wait = 1; | |
985 | } | |
986 | ||
987 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
988 | /* | |
989 | * Clear the slot in the oustanding_cmds array if we can't find the | |
990 | * command to reclaim the resources. | |
991 | */ | |
992 | if (rval == QLA_FUNCTION_PARAMETER_ERROR) | |
993 | vha->req->outstanding_cmds[sp->handle] = NULL; | |
994 | sp->done(ha, sp, 0); | |
995 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
996 | ||
997 | /* Did the command return during mailbox execution? */ | |
998 | if (ret == FAILED && !CMD_SP(cmd)) | |
999 | ret = SUCCESS; | |
1000 | ||
1001 | /* Wait for the command to be returned. */ | |
1002 | if (wait) { | |
1003 | if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) { | |
1004 | ql_log(ql_log_warn, vha, 0x8006, | |
1005 | "Abort handler timed out cmd=%p.\n", cmd); | |
1006 | ret = FAILED; | |
1007 | } | |
1008 | } | |
1009 | ||
1010 | ql_log(ql_log_info, vha, 0x801c, | |
1011 | "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n", | |
1012 | vha->host_no, id, lun, wait, ret); | |
1013 | ||
1014 | return ret; | |
1015 | } | |
1016 | ||
1017 | int | |
1018 | qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t, | |
1019 | uint64_t l, enum nexus_wait_type type) | |
1020 | { | |
1021 | int cnt, match, status; | |
1022 | unsigned long flags; | |
1023 | struct qla_hw_data *ha = vha->hw; | |
1024 | struct req_que *req; | |
1025 | srb_t *sp; | |
1026 | struct scsi_cmnd *cmd; | |
1027 | ||
1028 | status = QLA_SUCCESS; | |
1029 | ||
1030 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
1031 | req = vha->req; | |
1032 | for (cnt = 1; status == QLA_SUCCESS && | |
1033 | cnt < req->num_outstanding_cmds; cnt++) { | |
1034 | sp = req->outstanding_cmds[cnt]; | |
1035 | if (!sp) | |
1036 | continue; | |
1037 | if (sp->type != SRB_SCSI_CMD) | |
1038 | continue; | |
1039 | if (vha->vp_idx != sp->fcport->vha->vp_idx) | |
1040 | continue; | |
1041 | match = 0; | |
1042 | cmd = GET_CMD_SP(sp); | |
1043 | switch (type) { | |
1044 | case WAIT_HOST: | |
1045 | match = 1; | |
1046 | break; | |
1047 | case WAIT_TARGET: | |
1048 | match = cmd->device->id == t; | |
1049 | break; | |
1050 | case WAIT_LUN: | |
1051 | match = (cmd->device->id == t && | |
1052 | cmd->device->lun == l); | |
1053 | break; | |
1054 | } | |
1055 | if (!match) | |
1056 | continue; | |
1057 | ||
1058 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1059 | status = qla2x00_eh_wait_on_command(cmd); | |
1060 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
1061 | } | |
1062 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1063 | ||
1064 | return status; | |
1065 | } | |
1066 | ||
1067 | static char *reset_errors[] = { | |
1068 | "HBA not online", | |
1069 | "HBA not ready", | |
1070 | "Task management failed", | |
1071 | "Waiting for command completions", | |
1072 | }; | |
1073 | ||
1074 | static int | |
1075 | __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type, | |
1076 | struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int)) | |
1077 | { | |
1078 | scsi_qla_host_t *vha = shost_priv(cmd->device->host); | |
1079 | fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; | |
1080 | int err; | |
1081 | ||
1082 | if (!fcport) { | |
1083 | return FAILED; | |
1084 | } | |
1085 | ||
1086 | err = fc_block_scsi_eh(cmd); | |
1087 | if (err != 0) | |
1088 | return err; | |
1089 | ||
1090 | ql_log(ql_log_info, vha, 0x8009, | |
1091 | "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no, | |
1092 | cmd->device->id, cmd->device->lun, cmd); | |
1093 | ||
1094 | err = 0; | |
1095 | if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { | |
1096 | ql_log(ql_log_warn, vha, 0x800a, | |
1097 | "Wait for hba online failed for cmd=%p.\n", cmd); | |
1098 | goto eh_reset_failed; | |
1099 | } | |
1100 | err = 2; | |
1101 | if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1) | |
1102 | != QLA_SUCCESS) { | |
1103 | ql_log(ql_log_warn, vha, 0x800c, | |
1104 | "do_reset failed for cmd=%p.\n", cmd); | |
1105 | goto eh_reset_failed; | |
1106 | } | |
1107 | err = 3; | |
1108 | if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id, | |
1109 | cmd->device->lun, type) != QLA_SUCCESS) { | |
1110 | ql_log(ql_log_warn, vha, 0x800d, | |
1111 | "wait for pending cmds failed for cmd=%p.\n", cmd); | |
1112 | goto eh_reset_failed; | |
1113 | } | |
1114 | ||
1115 | ql_log(ql_log_info, vha, 0x800e, | |
1116 | "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name, | |
1117 | vha->host_no, cmd->device->id, cmd->device->lun, cmd); | |
1118 | ||
1119 | return SUCCESS; | |
1120 | ||
1121 | eh_reset_failed: | |
1122 | ql_log(ql_log_info, vha, 0x800f, | |
1123 | "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name, | |
1124 | reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun, | |
1125 | cmd); | |
1126 | return FAILED; | |
1127 | } | |
1128 | ||
1129 | static int | |
1130 | qla2xxx_eh_device_reset(struct scsi_cmnd *cmd) | |
1131 | { | |
1132 | scsi_qla_host_t *vha = shost_priv(cmd->device->host); | |
1133 | struct qla_hw_data *ha = vha->hw; | |
1134 | ||
1135 | return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd, | |
1136 | ha->isp_ops->lun_reset); | |
1137 | } | |
1138 | ||
1139 | static int | |
1140 | qla2xxx_eh_target_reset(struct scsi_cmnd *cmd) | |
1141 | { | |
1142 | scsi_qla_host_t *vha = shost_priv(cmd->device->host); | |
1143 | struct qla_hw_data *ha = vha->hw; | |
1144 | ||
1145 | return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd, | |
1146 | ha->isp_ops->target_reset); | |
1147 | } | |
1148 | ||
1149 | /************************************************************************** | |
1150 | * qla2xxx_eh_bus_reset | |
1151 | * | |
1152 | * Description: | |
1153 | * The bus reset function will reset the bus and abort any executing | |
1154 | * commands. | |
1155 | * | |
1156 | * Input: | |
1157 | * cmd = Linux SCSI command packet of the command that cause the | |
1158 | * bus reset. | |
1159 | * | |
1160 | * Returns: | |
1161 | * SUCCESS/FAILURE (defined as macro in scsi.h). | |
1162 | * | |
1163 | **************************************************************************/ | |
1164 | static int | |
1165 | qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd) | |
1166 | { | |
1167 | scsi_qla_host_t *vha = shost_priv(cmd->device->host); | |
1168 | fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; | |
1169 | int ret = FAILED; | |
1170 | unsigned int id; | |
1171 | uint64_t lun; | |
1172 | ||
1173 | id = cmd->device->id; | |
1174 | lun = cmd->device->lun; | |
1175 | ||
1176 | if (!fcport) { | |
1177 | return ret; | |
1178 | } | |
1179 | ||
1180 | ret = fc_block_scsi_eh(cmd); | |
1181 | if (ret != 0) | |
1182 | return ret; | |
1183 | ret = FAILED; | |
1184 | ||
1185 | ql_log(ql_log_info, vha, 0x8012, | |
1186 | "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); | |
1187 | ||
1188 | if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { | |
1189 | ql_log(ql_log_fatal, vha, 0x8013, | |
1190 | "Wait for hba online failed board disabled.\n"); | |
1191 | goto eh_bus_reset_done; | |
1192 | } | |
1193 | ||
1194 | if (qla2x00_loop_reset(vha) == QLA_SUCCESS) | |
1195 | ret = SUCCESS; | |
1196 | ||
1197 | if (ret == FAILED) | |
1198 | goto eh_bus_reset_done; | |
1199 | ||
1200 | /* Flush outstanding commands. */ | |
1201 | if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) != | |
1202 | QLA_SUCCESS) { | |
1203 | ql_log(ql_log_warn, vha, 0x8014, | |
1204 | "Wait for pending commands failed.\n"); | |
1205 | ret = FAILED; | |
1206 | } | |
1207 | ||
1208 | eh_bus_reset_done: | |
1209 | ql_log(ql_log_warn, vha, 0x802b, | |
1210 | "BUS RESET %s nexus=%ld:%d:%llu.\n", | |
1211 | (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); | |
1212 | ||
1213 | return ret; | |
1214 | } | |
1215 | ||
1216 | /************************************************************************** | |
1217 | * qla2xxx_eh_host_reset | |
1218 | * | |
1219 | * Description: | |
1220 | * The reset function will reset the Adapter. | |
1221 | * | |
1222 | * Input: | |
1223 | * cmd = Linux SCSI command packet of the command that cause the | |
1224 | * adapter reset. | |
1225 | * | |
1226 | * Returns: | |
1227 | * Either SUCCESS or FAILED. | |
1228 | * | |
1229 | * Note: | |
1230 | **************************************************************************/ | |
1231 | static int | |
1232 | qla2xxx_eh_host_reset(struct scsi_cmnd *cmd) | |
1233 | { | |
1234 | scsi_qla_host_t *vha = shost_priv(cmd->device->host); | |
1235 | struct qla_hw_data *ha = vha->hw; | |
1236 | int ret = FAILED; | |
1237 | unsigned int id; | |
1238 | uint64_t lun; | |
1239 | scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); | |
1240 | ||
1241 | id = cmd->device->id; | |
1242 | lun = cmd->device->lun; | |
1243 | ||
1244 | ql_log(ql_log_info, vha, 0x8018, | |
1245 | "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); | |
1246 | ||
1247 | /* | |
1248 | * No point in issuing another reset if one is active. Also do not | |
1249 | * attempt a reset if we are updating flash. | |
1250 | */ | |
1251 | if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING) | |
1252 | goto eh_host_reset_lock; | |
1253 | ||
1254 | if (vha != base_vha) { | |
1255 | if (qla2x00_vp_abort_isp(vha)) | |
1256 | goto eh_host_reset_lock; | |
1257 | } else { | |
1258 | if (IS_P3P_TYPE(vha->hw)) { | |
1259 | if (!qla82xx_fcoe_ctx_reset(vha)) { | |
1260 | /* Ctx reset success */ | |
1261 | ret = SUCCESS; | |
1262 | goto eh_host_reset_lock; | |
1263 | } | |
1264 | /* fall thru if ctx reset failed */ | |
1265 | } | |
1266 | if (ha->wq) | |
1267 | flush_workqueue(ha->wq); | |
1268 | ||
1269 | set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); | |
1270 | if (ha->isp_ops->abort_isp(base_vha)) { | |
1271 | clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); | |
1272 | /* failed. schedule dpc to try */ | |
1273 | set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); | |
1274 | ||
1275 | if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { | |
1276 | ql_log(ql_log_warn, vha, 0x802a, | |
1277 | "wait for hba online failed.\n"); | |
1278 | goto eh_host_reset_lock; | |
1279 | } | |
1280 | } | |
1281 | clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); | |
1282 | } | |
1283 | ||
1284 | /* Waiting for command to be returned to OS.*/ | |
1285 | if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) == | |
1286 | QLA_SUCCESS) | |
1287 | ret = SUCCESS; | |
1288 | ||
1289 | eh_host_reset_lock: | |
1290 | ql_log(ql_log_info, vha, 0x8017, | |
1291 | "ADAPTER RESET %s nexus=%ld:%d:%llu.\n", | |
1292 | (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); | |
1293 | ||
1294 | return ret; | |
1295 | } | |
1296 | ||
1297 | /* | |
1298 | * qla2x00_loop_reset | |
1299 | * Issue loop reset. | |
1300 | * | |
1301 | * Input: | |
1302 | * ha = adapter block pointer. | |
1303 | * | |
1304 | * Returns: | |
1305 | * 0 = success | |
1306 | */ | |
1307 | int | |
1308 | qla2x00_loop_reset(scsi_qla_host_t *vha) | |
1309 | { | |
1310 | int ret; | |
1311 | struct fc_port *fcport; | |
1312 | struct qla_hw_data *ha = vha->hw; | |
1313 | ||
1314 | if (IS_QLAFX00(ha)) { | |
1315 | return qlafx00_loop_reset(vha); | |
1316 | } | |
1317 | ||
1318 | if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) { | |
1319 | list_for_each_entry(fcport, &vha->vp_fcports, list) { | |
1320 | if (fcport->port_type != FCT_TARGET) | |
1321 | continue; | |
1322 | ||
1323 | ret = ha->isp_ops->target_reset(fcport, 0, 0); | |
1324 | if (ret != QLA_SUCCESS) { | |
1325 | ql_dbg(ql_dbg_taskm, vha, 0x802c, | |
1326 | "Bus Reset failed: Reset=%d " | |
1327 | "d_id=%x.\n", ret, fcport->d_id.b24); | |
1328 | } | |
1329 | } | |
1330 | } | |
1331 | ||
1332 | ||
1333 | if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) { | |
1334 | atomic_set(&vha->loop_state, LOOP_DOWN); | |
1335 | atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); | |
1336 | qla2x00_mark_all_devices_lost(vha, 0); | |
1337 | ret = qla2x00_full_login_lip(vha); | |
1338 | if (ret != QLA_SUCCESS) { | |
1339 | ql_dbg(ql_dbg_taskm, vha, 0x802d, | |
1340 | "full_login_lip=%d.\n", ret); | |
1341 | } | |
1342 | } | |
1343 | ||
1344 | if (ha->flags.enable_lip_reset) { | |
1345 | ret = qla2x00_lip_reset(vha); | |
1346 | if (ret != QLA_SUCCESS) | |
1347 | ql_dbg(ql_dbg_taskm, vha, 0x802e, | |
1348 | "lip_reset failed (%d).\n", ret); | |
1349 | } | |
1350 | ||
1351 | /* Issue marker command only when we are going to start the I/O */ | |
1352 | vha->marker_needed = 1; | |
1353 | ||
1354 | return QLA_SUCCESS; | |
1355 | } | |
1356 | ||
1357 | void | |
1358 | qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res) | |
1359 | { | |
1360 | int que, cnt; | |
1361 | unsigned long flags; | |
1362 | srb_t *sp; | |
1363 | struct qla_hw_data *ha = vha->hw; | |
1364 | struct req_que *req; | |
1365 | ||
1366 | qlt_host_reset_handler(ha); | |
1367 | ||
1368 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
1369 | for (que = 0; que < ha->max_req_queues; que++) { | |
1370 | req = ha->req_q_map[que]; | |
1371 | if (!req) | |
1372 | continue; | |
1373 | if (!req->outstanding_cmds) | |
1374 | continue; | |
1375 | for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { | |
1376 | sp = req->outstanding_cmds[cnt]; | |
1377 | if (sp) { | |
1378 | req->outstanding_cmds[cnt] = NULL; | |
1379 | sp->done(vha, sp, res); | |
1380 | } | |
1381 | } | |
1382 | } | |
1383 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1384 | } | |
1385 | ||
1386 | static int | |
1387 | qla2xxx_slave_alloc(struct scsi_device *sdev) | |
1388 | { | |
1389 | struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); | |
1390 | ||
1391 | if (!rport || fc_remote_port_chkready(rport)) | |
1392 | return -ENXIO; | |
1393 | ||
1394 | sdev->hostdata = *(fc_port_t **)rport->dd_data; | |
1395 | ||
1396 | return 0; | |
1397 | } | |
1398 | ||
1399 | static int | |
1400 | qla2xxx_slave_configure(struct scsi_device *sdev) | |
1401 | { | |
1402 | scsi_qla_host_t *vha = shost_priv(sdev->host); | |
1403 | struct req_que *req = vha->req; | |
1404 | ||
1405 | if (IS_T10_PI_CAPABLE(vha->hw)) | |
1406 | blk_queue_update_dma_alignment(sdev->request_queue, 0x7); | |
1407 | ||
1408 | scsi_adjust_queue_depth(sdev, req->max_q_depth); | |
1409 | return 0; | |
1410 | } | |
1411 | ||
1412 | static void | |
1413 | qla2xxx_slave_destroy(struct scsi_device *sdev) | |
1414 | { | |
1415 | sdev->hostdata = NULL; | |
1416 | } | |
1417 | ||
1418 | static void qla2x00_handle_queue_full(struct scsi_device *sdev, int qdepth) | |
1419 | { | |
1420 | fc_port_t *fcport = (struct fc_port *) sdev->hostdata; | |
1421 | ||
1422 | if (!scsi_track_queue_full(sdev, qdepth)) | |
1423 | return; | |
1424 | ||
1425 | ql_dbg(ql_dbg_io, fcport->vha, 0x3029, | |
1426 | "Queue depth adjusted-down to %d for nexus=%ld:%d:%llu.\n", | |
1427 | sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun); | |
1428 | } | |
1429 | ||
1430 | static void qla2x00_adjust_sdev_qdepth_up(struct scsi_device *sdev, int qdepth) | |
1431 | { | |
1432 | fc_port_t *fcport = sdev->hostdata; | |
1433 | struct scsi_qla_host *vha = fcport->vha; | |
1434 | struct req_que *req = NULL; | |
1435 | ||
1436 | req = vha->req; | |
1437 | if (!req) | |
1438 | return; | |
1439 | ||
1440 | if (req->max_q_depth <= sdev->queue_depth || req->max_q_depth < qdepth) | |
1441 | return; | |
1442 | ||
1443 | scsi_adjust_queue_depth(sdev, qdepth); | |
1444 | ||
1445 | ql_dbg(ql_dbg_io, vha, 0x302a, | |
1446 | "Queue depth adjusted-up to %d for nexus=%ld:%d:%llu.\n", | |
1447 | sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun); | |
1448 | } | |
1449 | ||
1450 | static int | |
1451 | qla2x00_change_queue_depth(struct scsi_device *sdev, int qdepth, int reason) | |
1452 | { | |
1453 | switch (reason) { | |
1454 | case SCSI_QDEPTH_DEFAULT: | |
1455 | scsi_adjust_queue_depth(sdev, qdepth); | |
1456 | break; | |
1457 | case SCSI_QDEPTH_QFULL: | |
1458 | qla2x00_handle_queue_full(sdev, qdepth); | |
1459 | break; | |
1460 | case SCSI_QDEPTH_RAMP_UP: | |
1461 | qla2x00_adjust_sdev_qdepth_up(sdev, qdepth); | |
1462 | break; | |
1463 | default: | |
1464 | return -EOPNOTSUPP; | |
1465 | } | |
1466 | ||
1467 | return sdev->queue_depth; | |
1468 | } | |
1469 | ||
1470 | /** | |
1471 | * qla2x00_config_dma_addressing() - Configure OS DMA addressing method. | |
1472 | * @ha: HA context | |
1473 | * | |
1474 | * At exit, the @ha's flags.enable_64bit_addressing set to indicated | |
1475 | * supported addressing method. | |
1476 | */ | |
1477 | static void | |
1478 | qla2x00_config_dma_addressing(struct qla_hw_data *ha) | |
1479 | { | |
1480 | /* Assume a 32bit DMA mask. */ | |
1481 | ha->flags.enable_64bit_addressing = 0; | |
1482 | ||
1483 | if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { | |
1484 | /* Any upper-dword bits set? */ | |
1485 | if (MSD(dma_get_required_mask(&ha->pdev->dev)) && | |
1486 | !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) { | |
1487 | /* Ok, a 64bit DMA mask is applicable. */ | |
1488 | ha->flags.enable_64bit_addressing = 1; | |
1489 | ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64; | |
1490 | ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64; | |
1491 | return; | |
1492 | } | |
1493 | } | |
1494 | ||
1495 | dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); | |
1496 | pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32)); | |
1497 | } | |
1498 | ||
1499 | static void | |
1500 | qla2x00_enable_intrs(struct qla_hw_data *ha) | |
1501 | { | |
1502 | unsigned long flags = 0; | |
1503 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | |
1504 | ||
1505 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
1506 | ha->interrupts_on = 1; | |
1507 | /* enable risc and host interrupts */ | |
1508 | WRT_REG_WORD(®->ictrl, ICR_EN_INT | ICR_EN_RISC); | |
1509 | RD_REG_WORD(®->ictrl); | |
1510 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1511 | ||
1512 | } | |
1513 | ||
1514 | static void | |
1515 | qla2x00_disable_intrs(struct qla_hw_data *ha) | |
1516 | { | |
1517 | unsigned long flags = 0; | |
1518 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | |
1519 | ||
1520 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
1521 | ha->interrupts_on = 0; | |
1522 | /* disable risc and host interrupts */ | |
1523 | WRT_REG_WORD(®->ictrl, 0); | |
1524 | RD_REG_WORD(®->ictrl); | |
1525 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1526 | } | |
1527 | ||
1528 | static void | |
1529 | qla24xx_enable_intrs(struct qla_hw_data *ha) | |
1530 | { | |
1531 | unsigned long flags = 0; | |
1532 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; | |
1533 | ||
1534 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
1535 | ha->interrupts_on = 1; | |
1536 | WRT_REG_DWORD(®->ictrl, ICRX_EN_RISC_INT); | |
1537 | RD_REG_DWORD(®->ictrl); | |
1538 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1539 | } | |
1540 | ||
1541 | static void | |
1542 | qla24xx_disable_intrs(struct qla_hw_data *ha) | |
1543 | { | |
1544 | unsigned long flags = 0; | |
1545 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; | |
1546 | ||
1547 | if (IS_NOPOLLING_TYPE(ha)) | |
1548 | return; | |
1549 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
1550 | ha->interrupts_on = 0; | |
1551 | WRT_REG_DWORD(®->ictrl, 0); | |
1552 | RD_REG_DWORD(®->ictrl); | |
1553 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1554 | } | |
1555 | ||
1556 | static int | |
1557 | qla2x00_iospace_config(struct qla_hw_data *ha) | |
1558 | { | |
1559 | resource_size_t pio; | |
1560 | uint16_t msix; | |
1561 | int cpus; | |
1562 | ||
1563 | if (pci_request_selected_regions(ha->pdev, ha->bars, | |
1564 | QLA2XXX_DRIVER_NAME)) { | |
1565 | ql_log_pci(ql_log_fatal, ha->pdev, 0x0011, | |
1566 | "Failed to reserve PIO/MMIO regions (%s), aborting.\n", | |
1567 | pci_name(ha->pdev)); | |
1568 | goto iospace_error_exit; | |
1569 | } | |
1570 | if (!(ha->bars & 1)) | |
1571 | goto skip_pio; | |
1572 | ||
1573 | /* We only need PIO for Flash operations on ISP2312 v2 chips. */ | |
1574 | pio = pci_resource_start(ha->pdev, 0); | |
1575 | if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) { | |
1576 | if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { | |
1577 | ql_log_pci(ql_log_warn, ha->pdev, 0x0012, | |
1578 | "Invalid pci I/O region size (%s).\n", | |
1579 | pci_name(ha->pdev)); | |
1580 | pio = 0; | |
1581 | } | |
1582 | } else { | |
1583 | ql_log_pci(ql_log_warn, ha->pdev, 0x0013, | |
1584 | "Region #0 no a PIO resource (%s).\n", | |
1585 | pci_name(ha->pdev)); | |
1586 | pio = 0; | |
1587 | } | |
1588 | ha->pio_address = pio; | |
1589 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014, | |
1590 | "PIO address=%llu.\n", | |
1591 | (unsigned long long)ha->pio_address); | |
1592 | ||
1593 | skip_pio: | |
1594 | /* Use MMIO operations for all accesses. */ | |
1595 | if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) { | |
1596 | ql_log_pci(ql_log_fatal, ha->pdev, 0x0015, | |
1597 | "Region #1 not an MMIO resource (%s), aborting.\n", | |
1598 | pci_name(ha->pdev)); | |
1599 | goto iospace_error_exit; | |
1600 | } | |
1601 | if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) { | |
1602 | ql_log_pci(ql_log_fatal, ha->pdev, 0x0016, | |
1603 | "Invalid PCI mem region size (%s), aborting.\n", | |
1604 | pci_name(ha->pdev)); | |
1605 | goto iospace_error_exit; | |
1606 | } | |
1607 | ||
1608 | ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN); | |
1609 | if (!ha->iobase) { | |
1610 | ql_log_pci(ql_log_fatal, ha->pdev, 0x0017, | |
1611 | "Cannot remap MMIO (%s), aborting.\n", | |
1612 | pci_name(ha->pdev)); | |
1613 | goto iospace_error_exit; | |
1614 | } | |
1615 | ||
1616 | /* Determine queue resources */ | |
1617 | ha->max_req_queues = ha->max_rsp_queues = 1; | |
1618 | if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) || | |
1619 | (ql2xmaxqueues > 1 && ql2xmultique_tag) || | |
1620 | (!IS_QLA25XX(ha) && !IS_QLA81XX(ha))) | |
1621 | goto mqiobase_exit; | |
1622 | ||
1623 | ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3), | |
1624 | pci_resource_len(ha->pdev, 3)); | |
1625 | if (ha->mqiobase) { | |
1626 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018, | |
1627 | "MQIO Base=%p.\n", ha->mqiobase); | |
1628 | /* Read MSIX vector size of the board */ | |
1629 | pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix); | |
1630 | ha->msix_count = msix; | |
1631 | /* Max queues are bounded by available msix vectors */ | |
1632 | /* queue 0 uses two msix vectors */ | |
1633 | if (ql2xmultique_tag) { | |
1634 | cpus = num_online_cpus(); | |
1635 | ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ? | |
1636 | (cpus + 1) : (ha->msix_count - 1); | |
1637 | ha->max_req_queues = 2; | |
1638 | } else if (ql2xmaxqueues > 1) { | |
1639 | ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ? | |
1640 | QLA_MQ_SIZE : ql2xmaxqueues; | |
1641 | ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008, | |
1642 | "QoS mode set, max no of request queues:%d.\n", | |
1643 | ha->max_req_queues); | |
1644 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019, | |
1645 | "QoS mode set, max no of request queues:%d.\n", | |
1646 | ha->max_req_queues); | |
1647 | } | |
1648 | ql_log_pci(ql_log_info, ha->pdev, 0x001a, | |
1649 | "MSI-X vector count: %d.\n", msix); | |
1650 | } else | |
1651 | ql_log_pci(ql_log_info, ha->pdev, 0x001b, | |
1652 | "BAR 3 not enabled.\n"); | |
1653 | ||
1654 | mqiobase_exit: | |
1655 | ha->msix_count = ha->max_rsp_queues + 1; | |
1656 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c, | |
1657 | "MSIX Count:%d.\n", ha->msix_count); | |
1658 | return (0); | |
1659 | ||
1660 | iospace_error_exit: | |
1661 | return (-ENOMEM); | |
1662 | } | |
1663 | ||
1664 | ||
1665 | static int | |
1666 | qla83xx_iospace_config(struct qla_hw_data *ha) | |
1667 | { | |
1668 | uint16_t msix; | |
1669 | int cpus; | |
1670 | ||
1671 | if (pci_request_selected_regions(ha->pdev, ha->bars, | |
1672 | QLA2XXX_DRIVER_NAME)) { | |
1673 | ql_log_pci(ql_log_fatal, ha->pdev, 0x0117, | |
1674 | "Failed to reserve PIO/MMIO regions (%s), aborting.\n", | |
1675 | pci_name(ha->pdev)); | |
1676 | ||
1677 | goto iospace_error_exit; | |
1678 | } | |
1679 | ||
1680 | /* Use MMIO operations for all accesses. */ | |
1681 | if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { | |
1682 | ql_log_pci(ql_log_warn, ha->pdev, 0x0118, | |
1683 | "Invalid pci I/O region size (%s).\n", | |
1684 | pci_name(ha->pdev)); | |
1685 | goto iospace_error_exit; | |
1686 | } | |
1687 | if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { | |
1688 | ql_log_pci(ql_log_warn, ha->pdev, 0x0119, | |
1689 | "Invalid PCI mem region size (%s), aborting\n", | |
1690 | pci_name(ha->pdev)); | |
1691 | goto iospace_error_exit; | |
1692 | } | |
1693 | ||
1694 | ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN); | |
1695 | if (!ha->iobase) { | |
1696 | ql_log_pci(ql_log_fatal, ha->pdev, 0x011a, | |
1697 | "Cannot remap MMIO (%s), aborting.\n", | |
1698 | pci_name(ha->pdev)); | |
1699 | goto iospace_error_exit; | |
1700 | } | |
1701 | ||
1702 | /* 64bit PCI BAR - BAR2 will correspoond to region 4 */ | |
1703 | /* 83XX 26XX always use MQ type access for queues | |
1704 | * - mbar 2, a.k.a region 4 */ | |
1705 | ha->max_req_queues = ha->max_rsp_queues = 1; | |
1706 | ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4), | |
1707 | pci_resource_len(ha->pdev, 4)); | |
1708 | ||
1709 | if (!ha->mqiobase) { | |
1710 | ql_log_pci(ql_log_fatal, ha->pdev, 0x011d, | |
1711 | "BAR2/region4 not enabled\n"); | |
1712 | goto mqiobase_exit; | |
1713 | } | |
1714 | ||
1715 | ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2), | |
1716 | pci_resource_len(ha->pdev, 2)); | |
1717 | if (ha->msixbase) { | |
1718 | /* Read MSIX vector size of the board */ | |
1719 | pci_read_config_word(ha->pdev, | |
1720 | QLA_83XX_PCI_MSIX_CONTROL, &msix); | |
1721 | ha->msix_count = msix; | |
1722 | /* Max queues are bounded by available msix vectors */ | |
1723 | /* queue 0 uses two msix vectors */ | |
1724 | if (ql2xmultique_tag) { | |
1725 | cpus = num_online_cpus(); | |
1726 | ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ? | |
1727 | (cpus + 1) : (ha->msix_count - 1); | |
1728 | ha->max_req_queues = 2; | |
1729 | } else if (ql2xmaxqueues > 1) { | |
1730 | ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ? | |
1731 | QLA_MQ_SIZE : ql2xmaxqueues; | |
1732 | ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc00c, | |
1733 | "QoS mode set, max no of request queues:%d.\n", | |
1734 | ha->max_req_queues); | |
1735 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, | |
1736 | "QoS mode set, max no of request queues:%d.\n", | |
1737 | ha->max_req_queues); | |
1738 | } | |
1739 | ql_log_pci(ql_log_info, ha->pdev, 0x011c, | |
1740 | "MSI-X vector count: %d.\n", msix); | |
1741 | } else | |
1742 | ql_log_pci(ql_log_info, ha->pdev, 0x011e, | |
1743 | "BAR 1 not enabled.\n"); | |
1744 | ||
1745 | mqiobase_exit: | |
1746 | ha->msix_count = ha->max_rsp_queues + 1; | |
1747 | ||
1748 | qlt_83xx_iospace_config(ha); | |
1749 | ||
1750 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f, | |
1751 | "MSIX Count:%d.\n", ha->msix_count); | |
1752 | return 0; | |
1753 | ||
1754 | iospace_error_exit: | |
1755 | return -ENOMEM; | |
1756 | } | |
1757 | ||
1758 | static struct isp_operations qla2100_isp_ops = { | |
1759 | .pci_config = qla2100_pci_config, | |
1760 | .reset_chip = qla2x00_reset_chip, | |
1761 | .chip_diag = qla2x00_chip_diag, | |
1762 | .config_rings = qla2x00_config_rings, | |
1763 | .reset_adapter = qla2x00_reset_adapter, | |
1764 | .nvram_config = qla2x00_nvram_config, | |
1765 | .update_fw_options = qla2x00_update_fw_options, | |
1766 | .load_risc = qla2x00_load_risc, | |
1767 | .pci_info_str = qla2x00_pci_info_str, | |
1768 | .fw_version_str = qla2x00_fw_version_str, | |
1769 | .intr_handler = qla2100_intr_handler, | |
1770 | .enable_intrs = qla2x00_enable_intrs, | |
1771 | .disable_intrs = qla2x00_disable_intrs, | |
1772 | .abort_command = qla2x00_abort_command, | |
1773 | .target_reset = qla2x00_abort_target, | |
1774 | .lun_reset = qla2x00_lun_reset, | |
1775 | .fabric_login = qla2x00_login_fabric, | |
1776 | .fabric_logout = qla2x00_fabric_logout, | |
1777 | .calc_req_entries = qla2x00_calc_iocbs_32, | |
1778 | .build_iocbs = qla2x00_build_scsi_iocbs_32, | |
1779 | .prep_ms_iocb = qla2x00_prep_ms_iocb, | |
1780 | .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, | |
1781 | .read_nvram = qla2x00_read_nvram_data, | |
1782 | .write_nvram = qla2x00_write_nvram_data, | |
1783 | .fw_dump = qla2100_fw_dump, | |
1784 | .beacon_on = NULL, | |
1785 | .beacon_off = NULL, | |
1786 | .beacon_blink = NULL, | |
1787 | .read_optrom = qla2x00_read_optrom_data, | |
1788 | .write_optrom = qla2x00_write_optrom_data, | |
1789 | .get_flash_version = qla2x00_get_flash_version, | |
1790 | .start_scsi = qla2x00_start_scsi, | |
1791 | .abort_isp = qla2x00_abort_isp, | |
1792 | .iospace_config = qla2x00_iospace_config, | |
1793 | .initialize_adapter = qla2x00_initialize_adapter, | |
1794 | }; | |
1795 | ||
1796 | static struct isp_operations qla2300_isp_ops = { | |
1797 | .pci_config = qla2300_pci_config, | |
1798 | .reset_chip = qla2x00_reset_chip, | |
1799 | .chip_diag = qla2x00_chip_diag, | |
1800 | .config_rings = qla2x00_config_rings, | |
1801 | .reset_adapter = qla2x00_reset_adapter, | |
1802 | .nvram_config = qla2x00_nvram_config, | |
1803 | .update_fw_options = qla2x00_update_fw_options, | |
1804 | .load_risc = qla2x00_load_risc, | |
1805 | .pci_info_str = qla2x00_pci_info_str, | |
1806 | .fw_version_str = qla2x00_fw_version_str, | |
1807 | .intr_handler = qla2300_intr_handler, | |
1808 | .enable_intrs = qla2x00_enable_intrs, | |
1809 | .disable_intrs = qla2x00_disable_intrs, | |
1810 | .abort_command = qla2x00_abort_command, | |
1811 | .target_reset = qla2x00_abort_target, | |
1812 | .lun_reset = qla2x00_lun_reset, | |
1813 | .fabric_login = qla2x00_login_fabric, | |
1814 | .fabric_logout = qla2x00_fabric_logout, | |
1815 | .calc_req_entries = qla2x00_calc_iocbs_32, | |
1816 | .build_iocbs = qla2x00_build_scsi_iocbs_32, | |
1817 | .prep_ms_iocb = qla2x00_prep_ms_iocb, | |
1818 | .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, | |
1819 | .read_nvram = qla2x00_read_nvram_data, | |
1820 | .write_nvram = qla2x00_write_nvram_data, | |
1821 | .fw_dump = qla2300_fw_dump, | |
1822 | .beacon_on = qla2x00_beacon_on, | |
1823 | .beacon_off = qla2x00_beacon_off, | |
1824 | .beacon_blink = qla2x00_beacon_blink, | |
1825 | .read_optrom = qla2x00_read_optrom_data, | |
1826 | .write_optrom = qla2x00_write_optrom_data, | |
1827 | .get_flash_version = qla2x00_get_flash_version, | |
1828 | .start_scsi = qla2x00_start_scsi, | |
1829 | .abort_isp = qla2x00_abort_isp, | |
1830 | .iospace_config = qla2x00_iospace_config, | |
1831 | .initialize_adapter = qla2x00_initialize_adapter, | |
1832 | }; | |
1833 | ||
1834 | static struct isp_operations qla24xx_isp_ops = { | |
1835 | .pci_config = qla24xx_pci_config, | |
1836 | .reset_chip = qla24xx_reset_chip, | |
1837 | .chip_diag = qla24xx_chip_diag, | |
1838 | .config_rings = qla24xx_config_rings, | |
1839 | .reset_adapter = qla24xx_reset_adapter, | |
1840 | .nvram_config = qla24xx_nvram_config, | |
1841 | .update_fw_options = qla24xx_update_fw_options, | |
1842 | .load_risc = qla24xx_load_risc, | |
1843 | .pci_info_str = qla24xx_pci_info_str, | |
1844 | .fw_version_str = qla24xx_fw_version_str, | |
1845 | .intr_handler = qla24xx_intr_handler, | |
1846 | .enable_intrs = qla24xx_enable_intrs, | |
1847 | .disable_intrs = qla24xx_disable_intrs, | |
1848 | .abort_command = qla24xx_abort_command, | |
1849 | .target_reset = qla24xx_abort_target, | |
1850 | .lun_reset = qla24xx_lun_reset, | |
1851 | .fabric_login = qla24xx_login_fabric, | |
1852 | .fabric_logout = qla24xx_fabric_logout, | |
1853 | .calc_req_entries = NULL, | |
1854 | .build_iocbs = NULL, | |
1855 | .prep_ms_iocb = qla24xx_prep_ms_iocb, | |
1856 | .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, | |
1857 | .read_nvram = qla24xx_read_nvram_data, | |
1858 | .write_nvram = qla24xx_write_nvram_data, | |
1859 | .fw_dump = qla24xx_fw_dump, | |
1860 | .beacon_on = qla24xx_beacon_on, | |
1861 | .beacon_off = qla24xx_beacon_off, | |
1862 | .beacon_blink = qla24xx_beacon_blink, | |
1863 | .read_optrom = qla24xx_read_optrom_data, | |
1864 | .write_optrom = qla24xx_write_optrom_data, | |
1865 | .get_flash_version = qla24xx_get_flash_version, | |
1866 | .start_scsi = qla24xx_start_scsi, | |
1867 | .abort_isp = qla2x00_abort_isp, | |
1868 | .iospace_config = qla2x00_iospace_config, | |
1869 | .initialize_adapter = qla2x00_initialize_adapter, | |
1870 | }; | |
1871 | ||
1872 | static struct isp_operations qla25xx_isp_ops = { | |
1873 | .pci_config = qla25xx_pci_config, | |
1874 | .reset_chip = qla24xx_reset_chip, | |
1875 | .chip_diag = qla24xx_chip_diag, | |
1876 | .config_rings = qla24xx_config_rings, | |
1877 | .reset_adapter = qla24xx_reset_adapter, | |
1878 | .nvram_config = qla24xx_nvram_config, | |
1879 | .update_fw_options = qla24xx_update_fw_options, | |
1880 | .load_risc = qla24xx_load_risc, | |
1881 | .pci_info_str = qla24xx_pci_info_str, | |
1882 | .fw_version_str = qla24xx_fw_version_str, | |
1883 | .intr_handler = qla24xx_intr_handler, | |
1884 | .enable_intrs = qla24xx_enable_intrs, | |
1885 | .disable_intrs = qla24xx_disable_intrs, | |
1886 | .abort_command = qla24xx_abort_command, | |
1887 | .target_reset = qla24xx_abort_target, | |
1888 | .lun_reset = qla24xx_lun_reset, | |
1889 | .fabric_login = qla24xx_login_fabric, | |
1890 | .fabric_logout = qla24xx_fabric_logout, | |
1891 | .calc_req_entries = NULL, | |
1892 | .build_iocbs = NULL, | |
1893 | .prep_ms_iocb = qla24xx_prep_ms_iocb, | |
1894 | .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, | |
1895 | .read_nvram = qla25xx_read_nvram_data, | |
1896 | .write_nvram = qla25xx_write_nvram_data, | |
1897 | .fw_dump = qla25xx_fw_dump, | |
1898 | .beacon_on = qla24xx_beacon_on, | |
1899 | .beacon_off = qla24xx_beacon_off, | |
1900 | .beacon_blink = qla24xx_beacon_blink, | |
1901 | .read_optrom = qla25xx_read_optrom_data, | |
1902 | .write_optrom = qla24xx_write_optrom_data, | |
1903 | .get_flash_version = qla24xx_get_flash_version, | |
1904 | .start_scsi = qla24xx_dif_start_scsi, | |
1905 | .abort_isp = qla2x00_abort_isp, | |
1906 | .iospace_config = qla2x00_iospace_config, | |
1907 | .initialize_adapter = qla2x00_initialize_adapter, | |
1908 | }; | |
1909 | ||
1910 | static struct isp_operations qla81xx_isp_ops = { | |
1911 | .pci_config = qla25xx_pci_config, | |
1912 | .reset_chip = qla24xx_reset_chip, | |
1913 | .chip_diag = qla24xx_chip_diag, | |
1914 | .config_rings = qla24xx_config_rings, | |
1915 | .reset_adapter = qla24xx_reset_adapter, | |
1916 | .nvram_config = qla81xx_nvram_config, | |
1917 | .update_fw_options = qla81xx_update_fw_options, | |
1918 | .load_risc = qla81xx_load_risc, | |
1919 | .pci_info_str = qla24xx_pci_info_str, | |
1920 | .fw_version_str = qla24xx_fw_version_str, | |
1921 | .intr_handler = qla24xx_intr_handler, | |
1922 | .enable_intrs = qla24xx_enable_intrs, | |
1923 | .disable_intrs = qla24xx_disable_intrs, | |
1924 | .abort_command = qla24xx_abort_command, | |
1925 | .target_reset = qla24xx_abort_target, | |
1926 | .lun_reset = qla24xx_lun_reset, | |
1927 | .fabric_login = qla24xx_login_fabric, | |
1928 | .fabric_logout = qla24xx_fabric_logout, | |
1929 | .calc_req_entries = NULL, | |
1930 | .build_iocbs = NULL, | |
1931 | .prep_ms_iocb = qla24xx_prep_ms_iocb, | |
1932 | .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, | |
1933 | .read_nvram = NULL, | |
1934 | .write_nvram = NULL, | |
1935 | .fw_dump = qla81xx_fw_dump, | |
1936 | .beacon_on = qla24xx_beacon_on, | |
1937 | .beacon_off = qla24xx_beacon_off, | |
1938 | .beacon_blink = qla83xx_beacon_blink, | |
1939 | .read_optrom = qla25xx_read_optrom_data, | |
1940 | .write_optrom = qla24xx_write_optrom_data, | |
1941 | .get_flash_version = qla24xx_get_flash_version, | |
1942 | .start_scsi = qla24xx_dif_start_scsi, | |
1943 | .abort_isp = qla2x00_abort_isp, | |
1944 | .iospace_config = qla2x00_iospace_config, | |
1945 | .initialize_adapter = qla2x00_initialize_adapter, | |
1946 | }; | |
1947 | ||
1948 | static struct isp_operations qla82xx_isp_ops = { | |
1949 | .pci_config = qla82xx_pci_config, | |
1950 | .reset_chip = qla82xx_reset_chip, | |
1951 | .chip_diag = qla24xx_chip_diag, | |
1952 | .config_rings = qla82xx_config_rings, | |
1953 | .reset_adapter = qla24xx_reset_adapter, | |
1954 | .nvram_config = qla81xx_nvram_config, | |
1955 | .update_fw_options = qla24xx_update_fw_options, | |
1956 | .load_risc = qla82xx_load_risc, | |
1957 | .pci_info_str = qla24xx_pci_info_str, | |
1958 | .fw_version_str = qla24xx_fw_version_str, | |
1959 | .intr_handler = qla82xx_intr_handler, | |
1960 | .enable_intrs = qla82xx_enable_intrs, | |
1961 | .disable_intrs = qla82xx_disable_intrs, | |
1962 | .abort_command = qla24xx_abort_command, | |
1963 | .target_reset = qla24xx_abort_target, | |
1964 | .lun_reset = qla24xx_lun_reset, | |
1965 | .fabric_login = qla24xx_login_fabric, | |
1966 | .fabric_logout = qla24xx_fabric_logout, | |
1967 | .calc_req_entries = NULL, | |
1968 | .build_iocbs = NULL, | |
1969 | .prep_ms_iocb = qla24xx_prep_ms_iocb, | |
1970 | .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, | |
1971 | .read_nvram = qla24xx_read_nvram_data, | |
1972 | .write_nvram = qla24xx_write_nvram_data, | |
1973 | .fw_dump = qla82xx_fw_dump, | |
1974 | .beacon_on = qla82xx_beacon_on, | |
1975 | .beacon_off = qla82xx_beacon_off, | |
1976 | .beacon_blink = NULL, | |
1977 | .read_optrom = qla82xx_read_optrom_data, | |
1978 | .write_optrom = qla82xx_write_optrom_data, | |
1979 | .get_flash_version = qla82xx_get_flash_version, | |
1980 | .start_scsi = qla82xx_start_scsi, | |
1981 | .abort_isp = qla82xx_abort_isp, | |
1982 | .iospace_config = qla82xx_iospace_config, | |
1983 | .initialize_adapter = qla2x00_initialize_adapter, | |
1984 | }; | |
1985 | ||
1986 | static struct isp_operations qla8044_isp_ops = { | |
1987 | .pci_config = qla82xx_pci_config, | |
1988 | .reset_chip = qla82xx_reset_chip, | |
1989 | .chip_diag = qla24xx_chip_diag, | |
1990 | .config_rings = qla82xx_config_rings, | |
1991 | .reset_adapter = qla24xx_reset_adapter, | |
1992 | .nvram_config = qla81xx_nvram_config, | |
1993 | .update_fw_options = qla24xx_update_fw_options, | |
1994 | .load_risc = qla82xx_load_risc, | |
1995 | .pci_info_str = qla24xx_pci_info_str, | |
1996 | .fw_version_str = qla24xx_fw_version_str, | |
1997 | .intr_handler = qla8044_intr_handler, | |
1998 | .enable_intrs = qla82xx_enable_intrs, | |
1999 | .disable_intrs = qla82xx_disable_intrs, | |
2000 | .abort_command = qla24xx_abort_command, | |
2001 | .target_reset = qla24xx_abort_target, | |
2002 | .lun_reset = qla24xx_lun_reset, | |
2003 | .fabric_login = qla24xx_login_fabric, | |
2004 | .fabric_logout = qla24xx_fabric_logout, | |
2005 | .calc_req_entries = NULL, | |
2006 | .build_iocbs = NULL, | |
2007 | .prep_ms_iocb = qla24xx_prep_ms_iocb, | |
2008 | .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, | |
2009 | .read_nvram = NULL, | |
2010 | .write_nvram = NULL, | |
2011 | .fw_dump = qla8044_fw_dump, | |
2012 | .beacon_on = qla82xx_beacon_on, | |
2013 | .beacon_off = qla82xx_beacon_off, | |
2014 | .beacon_blink = NULL, | |
2015 | .read_optrom = qla8044_read_optrom_data, | |
2016 | .write_optrom = qla8044_write_optrom_data, | |
2017 | .get_flash_version = qla82xx_get_flash_version, | |
2018 | .start_scsi = qla82xx_start_scsi, | |
2019 | .abort_isp = qla8044_abort_isp, | |
2020 | .iospace_config = qla82xx_iospace_config, | |
2021 | .initialize_adapter = qla2x00_initialize_adapter, | |
2022 | }; | |
2023 | ||
2024 | static struct isp_operations qla83xx_isp_ops = { | |
2025 | .pci_config = qla25xx_pci_config, | |
2026 | .reset_chip = qla24xx_reset_chip, | |
2027 | .chip_diag = qla24xx_chip_diag, | |
2028 | .config_rings = qla24xx_config_rings, | |
2029 | .reset_adapter = qla24xx_reset_adapter, | |
2030 | .nvram_config = qla81xx_nvram_config, | |
2031 | .update_fw_options = qla81xx_update_fw_options, | |
2032 | .load_risc = qla81xx_load_risc, | |
2033 | .pci_info_str = qla24xx_pci_info_str, | |
2034 | .fw_version_str = qla24xx_fw_version_str, | |
2035 | .intr_handler = qla24xx_intr_handler, | |
2036 | .enable_intrs = qla24xx_enable_intrs, | |
2037 | .disable_intrs = qla24xx_disable_intrs, | |
2038 | .abort_command = qla24xx_abort_command, | |
2039 | .target_reset = qla24xx_abort_target, | |
2040 | .lun_reset = qla24xx_lun_reset, | |
2041 | .fabric_login = qla24xx_login_fabric, | |
2042 | .fabric_logout = qla24xx_fabric_logout, | |
2043 | .calc_req_entries = NULL, | |
2044 | .build_iocbs = NULL, | |
2045 | .prep_ms_iocb = qla24xx_prep_ms_iocb, | |
2046 | .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, | |
2047 | .read_nvram = NULL, | |
2048 | .write_nvram = NULL, | |
2049 | .fw_dump = qla83xx_fw_dump, | |
2050 | .beacon_on = qla24xx_beacon_on, | |
2051 | .beacon_off = qla24xx_beacon_off, | |
2052 | .beacon_blink = qla83xx_beacon_blink, | |
2053 | .read_optrom = qla25xx_read_optrom_data, | |
2054 | .write_optrom = qla24xx_write_optrom_data, | |
2055 | .get_flash_version = qla24xx_get_flash_version, | |
2056 | .start_scsi = qla24xx_dif_start_scsi, | |
2057 | .abort_isp = qla2x00_abort_isp, | |
2058 | .iospace_config = qla83xx_iospace_config, | |
2059 | .initialize_adapter = qla2x00_initialize_adapter, | |
2060 | }; | |
2061 | ||
2062 | static struct isp_operations qlafx00_isp_ops = { | |
2063 | .pci_config = qlafx00_pci_config, | |
2064 | .reset_chip = qlafx00_soft_reset, | |
2065 | .chip_diag = qlafx00_chip_diag, | |
2066 | .config_rings = qlafx00_config_rings, | |
2067 | .reset_adapter = qlafx00_soft_reset, | |
2068 | .nvram_config = NULL, | |
2069 | .update_fw_options = NULL, | |
2070 | .load_risc = NULL, | |
2071 | .pci_info_str = qlafx00_pci_info_str, | |
2072 | .fw_version_str = qlafx00_fw_version_str, | |
2073 | .intr_handler = qlafx00_intr_handler, | |
2074 | .enable_intrs = qlafx00_enable_intrs, | |
2075 | .disable_intrs = qlafx00_disable_intrs, | |
2076 | .abort_command = qla24xx_async_abort_command, | |
2077 | .target_reset = qlafx00_abort_target, | |
2078 | .lun_reset = qlafx00_lun_reset, | |
2079 | .fabric_login = NULL, | |
2080 | .fabric_logout = NULL, | |
2081 | .calc_req_entries = NULL, | |
2082 | .build_iocbs = NULL, | |
2083 | .prep_ms_iocb = qla24xx_prep_ms_iocb, | |
2084 | .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, | |
2085 | .read_nvram = qla24xx_read_nvram_data, | |
2086 | .write_nvram = qla24xx_write_nvram_data, | |
2087 | .fw_dump = NULL, | |
2088 | .beacon_on = qla24xx_beacon_on, | |
2089 | .beacon_off = qla24xx_beacon_off, | |
2090 | .beacon_blink = NULL, | |
2091 | .read_optrom = qla24xx_read_optrom_data, | |
2092 | .write_optrom = qla24xx_write_optrom_data, | |
2093 | .get_flash_version = qla24xx_get_flash_version, | |
2094 | .start_scsi = qlafx00_start_scsi, | |
2095 | .abort_isp = qlafx00_abort_isp, | |
2096 | .iospace_config = qlafx00_iospace_config, | |
2097 | .initialize_adapter = qlafx00_initialize_adapter, | |
2098 | }; | |
2099 | ||
2100 | static struct isp_operations qla27xx_isp_ops = { | |
2101 | .pci_config = qla25xx_pci_config, | |
2102 | .reset_chip = qla24xx_reset_chip, | |
2103 | .chip_diag = qla24xx_chip_diag, | |
2104 | .config_rings = qla24xx_config_rings, | |
2105 | .reset_adapter = qla24xx_reset_adapter, | |
2106 | .nvram_config = qla81xx_nvram_config, | |
2107 | .update_fw_options = qla81xx_update_fw_options, | |
2108 | .load_risc = qla81xx_load_risc, | |
2109 | .pci_info_str = qla24xx_pci_info_str, | |
2110 | .fw_version_str = qla24xx_fw_version_str, | |
2111 | .intr_handler = qla24xx_intr_handler, | |
2112 | .enable_intrs = qla24xx_enable_intrs, | |
2113 | .disable_intrs = qla24xx_disable_intrs, | |
2114 | .abort_command = qla24xx_abort_command, | |
2115 | .target_reset = qla24xx_abort_target, | |
2116 | .lun_reset = qla24xx_lun_reset, | |
2117 | .fabric_login = qla24xx_login_fabric, | |
2118 | .fabric_logout = qla24xx_fabric_logout, | |
2119 | .calc_req_entries = NULL, | |
2120 | .build_iocbs = NULL, | |
2121 | .prep_ms_iocb = qla24xx_prep_ms_iocb, | |
2122 | .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, | |
2123 | .read_nvram = NULL, | |
2124 | .write_nvram = NULL, | |
2125 | .fw_dump = qla27xx_fwdump, | |
2126 | .beacon_on = qla24xx_beacon_on, | |
2127 | .beacon_off = qla24xx_beacon_off, | |
2128 | .beacon_blink = qla83xx_beacon_blink, | |
2129 | .read_optrom = qla25xx_read_optrom_data, | |
2130 | .write_optrom = qla24xx_write_optrom_data, | |
2131 | .get_flash_version = qla24xx_get_flash_version, | |
2132 | .start_scsi = qla24xx_dif_start_scsi, | |
2133 | .abort_isp = qla2x00_abort_isp, | |
2134 | .iospace_config = qla83xx_iospace_config, | |
2135 | .initialize_adapter = qla2x00_initialize_adapter, | |
2136 | }; | |
2137 | ||
2138 | static inline void | |
2139 | qla2x00_set_isp_flags(struct qla_hw_data *ha) | |
2140 | { | |
2141 | ha->device_type = DT_EXTENDED_IDS; | |
2142 | switch (ha->pdev->device) { | |
2143 | case PCI_DEVICE_ID_QLOGIC_ISP2100: | |
2144 | ha->device_type |= DT_ISP2100; | |
2145 | ha->device_type &= ~DT_EXTENDED_IDS; | |
2146 | ha->fw_srisc_address = RISC_START_ADDRESS_2100; | |
2147 | break; | |
2148 | case PCI_DEVICE_ID_QLOGIC_ISP2200: | |
2149 | ha->device_type |= DT_ISP2200; | |
2150 | ha->device_type &= ~DT_EXTENDED_IDS; | |
2151 | ha->fw_srisc_address = RISC_START_ADDRESS_2100; | |
2152 | break; | |
2153 | case PCI_DEVICE_ID_QLOGIC_ISP2300: | |
2154 | ha->device_type |= DT_ISP2300; | |
2155 | ha->device_type |= DT_ZIO_SUPPORTED; | |
2156 | ha->fw_srisc_address = RISC_START_ADDRESS_2300; | |
2157 | break; | |
2158 | case PCI_DEVICE_ID_QLOGIC_ISP2312: | |
2159 | ha->device_type |= DT_ISP2312; | |
2160 | ha->device_type |= DT_ZIO_SUPPORTED; | |
2161 | ha->fw_srisc_address = RISC_START_ADDRESS_2300; | |
2162 | break; | |
2163 | case PCI_DEVICE_ID_QLOGIC_ISP2322: | |
2164 | ha->device_type |= DT_ISP2322; | |
2165 | ha->device_type |= DT_ZIO_SUPPORTED; | |
2166 | if (ha->pdev->subsystem_vendor == 0x1028 && | |
2167 | ha->pdev->subsystem_device == 0x0170) | |
2168 | ha->device_type |= DT_OEM_001; | |
2169 | ha->fw_srisc_address = RISC_START_ADDRESS_2300; | |
2170 | break; | |
2171 | case PCI_DEVICE_ID_QLOGIC_ISP6312: | |
2172 | ha->device_type |= DT_ISP6312; | |
2173 | ha->fw_srisc_address = RISC_START_ADDRESS_2300; | |
2174 | break; | |
2175 | case PCI_DEVICE_ID_QLOGIC_ISP6322: | |
2176 | ha->device_type |= DT_ISP6322; | |
2177 | ha->fw_srisc_address = RISC_START_ADDRESS_2300; | |
2178 | break; | |
2179 | case PCI_DEVICE_ID_QLOGIC_ISP2422: | |
2180 | ha->device_type |= DT_ISP2422; | |
2181 | ha->device_type |= DT_ZIO_SUPPORTED; | |
2182 | ha->device_type |= DT_FWI2; | |
2183 | ha->device_type |= DT_IIDMA; | |
2184 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; | |
2185 | break; | |
2186 | case PCI_DEVICE_ID_QLOGIC_ISP2432: | |
2187 | ha->device_type |= DT_ISP2432; | |
2188 | ha->device_type |= DT_ZIO_SUPPORTED; | |
2189 | ha->device_type |= DT_FWI2; | |
2190 | ha->device_type |= DT_IIDMA; | |
2191 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; | |
2192 | break; | |
2193 | case PCI_DEVICE_ID_QLOGIC_ISP8432: | |
2194 | ha->device_type |= DT_ISP8432; | |
2195 | ha->device_type |= DT_ZIO_SUPPORTED; | |
2196 | ha->device_type |= DT_FWI2; | |
2197 | ha->device_type |= DT_IIDMA; | |
2198 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; | |
2199 | break; | |
2200 | case PCI_DEVICE_ID_QLOGIC_ISP5422: | |
2201 | ha->device_type |= DT_ISP5422; | |
2202 | ha->device_type |= DT_FWI2; | |
2203 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; | |
2204 | break; | |
2205 | case PCI_DEVICE_ID_QLOGIC_ISP5432: | |
2206 | ha->device_type |= DT_ISP5432; | |
2207 | ha->device_type |= DT_FWI2; | |
2208 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; | |
2209 | break; | |
2210 | case PCI_DEVICE_ID_QLOGIC_ISP2532: | |
2211 | ha->device_type |= DT_ISP2532; | |
2212 | ha->device_type |= DT_ZIO_SUPPORTED; | |
2213 | ha->device_type |= DT_FWI2; | |
2214 | ha->device_type |= DT_IIDMA; | |
2215 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; | |
2216 | break; | |
2217 | case PCI_DEVICE_ID_QLOGIC_ISP8001: | |
2218 | ha->device_type |= DT_ISP8001; | |
2219 | ha->device_type |= DT_ZIO_SUPPORTED; | |
2220 | ha->device_type |= DT_FWI2; | |
2221 | ha->device_type |= DT_IIDMA; | |
2222 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; | |
2223 | break; | |
2224 | case PCI_DEVICE_ID_QLOGIC_ISP8021: | |
2225 | ha->device_type |= DT_ISP8021; | |
2226 | ha->device_type |= DT_ZIO_SUPPORTED; | |
2227 | ha->device_type |= DT_FWI2; | |
2228 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; | |
2229 | /* Initialize 82XX ISP flags */ | |
2230 | qla82xx_init_flags(ha); | |
2231 | break; | |
2232 | case PCI_DEVICE_ID_QLOGIC_ISP8044: | |
2233 | ha->device_type |= DT_ISP8044; | |
2234 | ha->device_type |= DT_ZIO_SUPPORTED; | |
2235 | ha->device_type |= DT_FWI2; | |
2236 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; | |
2237 | /* Initialize 82XX ISP flags */ | |
2238 | qla82xx_init_flags(ha); | |
2239 | break; | |
2240 | case PCI_DEVICE_ID_QLOGIC_ISP2031: | |
2241 | ha->device_type |= DT_ISP2031; | |
2242 | ha->device_type |= DT_ZIO_SUPPORTED; | |
2243 | ha->device_type |= DT_FWI2; | |
2244 | ha->device_type |= DT_IIDMA; | |
2245 | ha->device_type |= DT_T10_PI; | |
2246 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; | |
2247 | break; | |
2248 | case PCI_DEVICE_ID_QLOGIC_ISP8031: | |
2249 | ha->device_type |= DT_ISP8031; | |
2250 | ha->device_type |= DT_ZIO_SUPPORTED; | |
2251 | ha->device_type |= DT_FWI2; | |
2252 | ha->device_type |= DT_IIDMA; | |
2253 | ha->device_type |= DT_T10_PI; | |
2254 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; | |
2255 | break; | |
2256 | case PCI_DEVICE_ID_QLOGIC_ISPF001: | |
2257 | ha->device_type |= DT_ISPFX00; | |
2258 | break; | |
2259 | case PCI_DEVICE_ID_QLOGIC_ISP2071: | |
2260 | ha->device_type |= DT_ISP2071; | |
2261 | ha->device_type |= DT_ZIO_SUPPORTED; | |
2262 | ha->device_type |= DT_FWI2; | |
2263 | ha->device_type |= DT_IIDMA; | |
2264 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; | |
2265 | break; | |
2266 | case PCI_DEVICE_ID_QLOGIC_ISP2271: | |
2267 | ha->device_type |= DT_ISP2271; | |
2268 | ha->device_type |= DT_ZIO_SUPPORTED; | |
2269 | ha->device_type |= DT_FWI2; | |
2270 | ha->device_type |= DT_IIDMA; | |
2271 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; | |
2272 | break; | |
2273 | } | |
2274 | ||
2275 | if (IS_QLA82XX(ha)) | |
2276 | ha->port_no = ha->portnum & 1; | |
2277 | else { | |
2278 | /* Get adapter physical port no from interrupt pin register. */ | |
2279 | pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no); | |
2280 | if (IS_QLA27XX(ha)) | |
2281 | ha->port_no--; | |
2282 | else | |
2283 | ha->port_no = !(ha->port_no & 1); | |
2284 | } | |
2285 | ||
2286 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b, | |
2287 | "device_type=0x%x port=%d fw_srisc_address=0x%x.\n", | |
2288 | ha->device_type, ha->port_no, ha->fw_srisc_address); | |
2289 | } | |
2290 | ||
2291 | static void | |
2292 | qla2xxx_scan_start(struct Scsi_Host *shost) | |
2293 | { | |
2294 | scsi_qla_host_t *vha = shost_priv(shost); | |
2295 | ||
2296 | if (vha->hw->flags.running_gold_fw) | |
2297 | return; | |
2298 | ||
2299 | set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); | |
2300 | set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); | |
2301 | set_bit(RSCN_UPDATE, &vha->dpc_flags); | |
2302 | set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags); | |
2303 | } | |
2304 | ||
2305 | static int | |
2306 | qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time) | |
2307 | { | |
2308 | scsi_qla_host_t *vha = shost_priv(shost); | |
2309 | ||
2310 | if (!vha->host) | |
2311 | return 1; | |
2312 | if (time > vha->hw->loop_reset_delay * HZ) | |
2313 | return 1; | |
2314 | ||
2315 | return atomic_read(&vha->loop_state) == LOOP_READY; | |
2316 | } | |
2317 | ||
2318 | /* | |
2319 | * PCI driver interface | |
2320 | */ | |
2321 | static int | |
2322 | qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) | |
2323 | { | |
2324 | int ret = -ENODEV; | |
2325 | struct Scsi_Host *host; | |
2326 | scsi_qla_host_t *base_vha = NULL; | |
2327 | struct qla_hw_data *ha; | |
2328 | char pci_info[30]; | |
2329 | char fw_str[30], wq_name[30]; | |
2330 | struct scsi_host_template *sht; | |
2331 | int bars, mem_only = 0; | |
2332 | uint16_t req_length = 0, rsp_length = 0; | |
2333 | struct req_que *req = NULL; | |
2334 | struct rsp_que *rsp = NULL; | |
2335 | bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO); | |
2336 | sht = &qla2xxx_driver_template; | |
2337 | if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 || | |
2338 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 || | |
2339 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 || | |
2340 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 || | |
2341 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 || | |
2342 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 || | |
2343 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 || | |
2344 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 || | |
2345 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 || | |
2346 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 || | |
2347 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 || | |
2348 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 || | |
2349 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 || | |
2350 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271) { | |
2351 | bars = pci_select_bars(pdev, IORESOURCE_MEM); | |
2352 | mem_only = 1; | |
2353 | ql_dbg_pci(ql_dbg_init, pdev, 0x0007, | |
2354 | "Mem only adapter.\n"); | |
2355 | } | |
2356 | ql_dbg_pci(ql_dbg_init, pdev, 0x0008, | |
2357 | "Bars=%d.\n", bars); | |
2358 | ||
2359 | if (mem_only) { | |
2360 | if (pci_enable_device_mem(pdev)) | |
2361 | goto probe_out; | |
2362 | } else { | |
2363 | if (pci_enable_device(pdev)) | |
2364 | goto probe_out; | |
2365 | } | |
2366 | ||
2367 | /* This may fail but that's ok */ | |
2368 | pci_enable_pcie_error_reporting(pdev); | |
2369 | ||
2370 | ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL); | |
2371 | if (!ha) { | |
2372 | ql_log_pci(ql_log_fatal, pdev, 0x0009, | |
2373 | "Unable to allocate memory for ha.\n"); | |
2374 | goto probe_out; | |
2375 | } | |
2376 | ql_dbg_pci(ql_dbg_init, pdev, 0x000a, | |
2377 | "Memory allocated for ha=%p.\n", ha); | |
2378 | ha->pdev = pdev; | |
2379 | ha->tgt.enable_class_2 = ql2xenableclass2; | |
2380 | INIT_LIST_HEAD(&ha->tgt.q_full_list); | |
2381 | spin_lock_init(&ha->tgt.q_full_lock); | |
2382 | ||
2383 | /* Clear our data area */ | |
2384 | ha->bars = bars; | |
2385 | ha->mem_only = mem_only; | |
2386 | spin_lock_init(&ha->hardware_lock); | |
2387 | spin_lock_init(&ha->vport_slock); | |
2388 | mutex_init(&ha->selflogin_lock); | |
2389 | mutex_init(&ha->optrom_mutex); | |
2390 | ||
2391 | /* Set ISP-type information. */ | |
2392 | qla2x00_set_isp_flags(ha); | |
2393 | ||
2394 | /* Set EEH reset type to fundamental if required by hba */ | |
2395 | if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) || | |
2396 | IS_QLA83XX(ha) || IS_QLA27XX(ha)) | |
2397 | pdev->needs_freset = 1; | |
2398 | ||
2399 | ha->prev_topology = 0; | |
2400 | ha->init_cb_size = sizeof(init_cb_t); | |
2401 | ha->link_data_rate = PORT_SPEED_UNKNOWN; | |
2402 | ha->optrom_size = OPTROM_SIZE_2300; | |
2403 | ||
2404 | /* Assign ISP specific operations. */ | |
2405 | if (IS_QLA2100(ha)) { | |
2406 | ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; | |
2407 | ha->mbx_count = MAILBOX_REGISTER_COUNT_2100; | |
2408 | req_length = REQUEST_ENTRY_CNT_2100; | |
2409 | rsp_length = RESPONSE_ENTRY_CNT_2100; | |
2410 | ha->max_loop_id = SNS_LAST_LOOP_ID_2100; | |
2411 | ha->gid_list_info_size = 4; | |
2412 | ha->flash_conf_off = ~0; | |
2413 | ha->flash_data_off = ~0; | |
2414 | ha->nvram_conf_off = ~0; | |
2415 | ha->nvram_data_off = ~0; | |
2416 | ha->isp_ops = &qla2100_isp_ops; | |
2417 | } else if (IS_QLA2200(ha)) { | |
2418 | ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; | |
2419 | ha->mbx_count = MAILBOX_REGISTER_COUNT_2200; | |
2420 | req_length = REQUEST_ENTRY_CNT_2200; | |
2421 | rsp_length = RESPONSE_ENTRY_CNT_2100; | |
2422 | ha->max_loop_id = SNS_LAST_LOOP_ID_2100; | |
2423 | ha->gid_list_info_size = 4; | |
2424 | ha->flash_conf_off = ~0; | |
2425 | ha->flash_data_off = ~0; | |
2426 | ha->nvram_conf_off = ~0; | |
2427 | ha->nvram_data_off = ~0; | |
2428 | ha->isp_ops = &qla2100_isp_ops; | |
2429 | } else if (IS_QLA23XX(ha)) { | |
2430 | ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; | |
2431 | ha->mbx_count = MAILBOX_REGISTER_COUNT; | |
2432 | req_length = REQUEST_ENTRY_CNT_2200; | |
2433 | rsp_length = RESPONSE_ENTRY_CNT_2300; | |
2434 | ha->max_loop_id = SNS_LAST_LOOP_ID_2300; | |
2435 | ha->gid_list_info_size = 6; | |
2436 | if (IS_QLA2322(ha) || IS_QLA6322(ha)) | |
2437 | ha->optrom_size = OPTROM_SIZE_2322; | |
2438 | ha->flash_conf_off = ~0; | |
2439 | ha->flash_data_off = ~0; | |
2440 | ha->nvram_conf_off = ~0; | |
2441 | ha->nvram_data_off = ~0; | |
2442 | ha->isp_ops = &qla2300_isp_ops; | |
2443 | } else if (IS_QLA24XX_TYPE(ha)) { | |
2444 | ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; | |
2445 | ha->mbx_count = MAILBOX_REGISTER_COUNT; | |
2446 | req_length = REQUEST_ENTRY_CNT_24XX; | |
2447 | rsp_length = RESPONSE_ENTRY_CNT_2300; | |
2448 | ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; | |
2449 | ha->max_loop_id = SNS_LAST_LOOP_ID_2300; | |
2450 | ha->init_cb_size = sizeof(struct mid_init_cb_24xx); | |
2451 | ha->gid_list_info_size = 8; | |
2452 | ha->optrom_size = OPTROM_SIZE_24XX; | |
2453 | ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX; | |
2454 | ha->isp_ops = &qla24xx_isp_ops; | |
2455 | ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; | |
2456 | ha->flash_data_off = FARX_ACCESS_FLASH_DATA; | |
2457 | ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; | |
2458 | ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; | |
2459 | } else if (IS_QLA25XX(ha)) { | |
2460 | ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; | |
2461 | ha->mbx_count = MAILBOX_REGISTER_COUNT; | |
2462 | req_length = REQUEST_ENTRY_CNT_24XX; | |
2463 | rsp_length = RESPONSE_ENTRY_CNT_2300; | |
2464 | ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; | |
2465 | ha->max_loop_id = SNS_LAST_LOOP_ID_2300; | |
2466 | ha->init_cb_size = sizeof(struct mid_init_cb_24xx); | |
2467 | ha->gid_list_info_size = 8; | |
2468 | ha->optrom_size = OPTROM_SIZE_25XX; | |
2469 | ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; | |
2470 | ha->isp_ops = &qla25xx_isp_ops; | |
2471 | ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; | |
2472 | ha->flash_data_off = FARX_ACCESS_FLASH_DATA; | |
2473 | ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; | |
2474 | ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; | |
2475 | } else if (IS_QLA81XX(ha)) { | |
2476 | ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; | |
2477 | ha->mbx_count = MAILBOX_REGISTER_COUNT; | |
2478 | req_length = REQUEST_ENTRY_CNT_24XX; | |
2479 | rsp_length = RESPONSE_ENTRY_CNT_2300; | |
2480 | ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; | |
2481 | ha->max_loop_id = SNS_LAST_LOOP_ID_2300; | |
2482 | ha->init_cb_size = sizeof(struct mid_init_cb_81xx); | |
2483 | ha->gid_list_info_size = 8; | |
2484 | ha->optrom_size = OPTROM_SIZE_81XX; | |
2485 | ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; | |
2486 | ha->isp_ops = &qla81xx_isp_ops; | |
2487 | ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; | |
2488 | ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; | |
2489 | ha->nvram_conf_off = ~0; | |
2490 | ha->nvram_data_off = ~0; | |
2491 | } else if (IS_QLA82XX(ha)) { | |
2492 | ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; | |
2493 | ha->mbx_count = MAILBOX_REGISTER_COUNT; | |
2494 | req_length = REQUEST_ENTRY_CNT_82XX; | |
2495 | rsp_length = RESPONSE_ENTRY_CNT_82XX; | |
2496 | ha->max_loop_id = SNS_LAST_LOOP_ID_2300; | |
2497 | ha->init_cb_size = sizeof(struct mid_init_cb_81xx); | |
2498 | ha->gid_list_info_size = 8; | |
2499 | ha->optrom_size = OPTROM_SIZE_82XX; | |
2500 | ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; | |
2501 | ha->isp_ops = &qla82xx_isp_ops; | |
2502 | ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; | |
2503 | ha->flash_data_off = FARX_ACCESS_FLASH_DATA; | |
2504 | ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; | |
2505 | ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; | |
2506 | } else if (IS_QLA8044(ha)) { | |
2507 | ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; | |
2508 | ha->mbx_count = MAILBOX_REGISTER_COUNT; | |
2509 | req_length = REQUEST_ENTRY_CNT_82XX; | |
2510 | rsp_length = RESPONSE_ENTRY_CNT_82XX; | |
2511 | ha->max_loop_id = SNS_LAST_LOOP_ID_2300; | |
2512 | ha->init_cb_size = sizeof(struct mid_init_cb_81xx); | |
2513 | ha->gid_list_info_size = 8; | |
2514 | ha->optrom_size = OPTROM_SIZE_83XX; | |
2515 | ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; | |
2516 | ha->isp_ops = &qla8044_isp_ops; | |
2517 | ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; | |
2518 | ha->flash_data_off = FARX_ACCESS_FLASH_DATA; | |
2519 | ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; | |
2520 | ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; | |
2521 | } else if (IS_QLA83XX(ha)) { | |
2522 | ha->portnum = PCI_FUNC(ha->pdev->devfn); | |
2523 | ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; | |
2524 | ha->mbx_count = MAILBOX_REGISTER_COUNT; | |
2525 | req_length = REQUEST_ENTRY_CNT_83XX; | |
2526 | rsp_length = RESPONSE_ENTRY_CNT_2300; | |
2527 | ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; | |
2528 | ha->max_loop_id = SNS_LAST_LOOP_ID_2300; | |
2529 | ha->init_cb_size = sizeof(struct mid_init_cb_81xx); | |
2530 | ha->gid_list_info_size = 8; | |
2531 | ha->optrom_size = OPTROM_SIZE_83XX; | |
2532 | ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; | |
2533 | ha->isp_ops = &qla83xx_isp_ops; | |
2534 | ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; | |
2535 | ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; | |
2536 | ha->nvram_conf_off = ~0; | |
2537 | ha->nvram_data_off = ~0; | |
2538 | } else if (IS_QLAFX00(ha)) { | |
2539 | ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00; | |
2540 | ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00; | |
2541 | ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00; | |
2542 | req_length = REQUEST_ENTRY_CNT_FX00; | |
2543 | rsp_length = RESPONSE_ENTRY_CNT_FX00; | |
2544 | ha->isp_ops = &qlafx00_isp_ops; | |
2545 | ha->port_down_retry_count = 30; /* default value */ | |
2546 | ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL; | |
2547 | ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL; | |
2548 | ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL; | |
2549 | ha->mr.fw_hbt_en = 1; | |
2550 | ha->mr.host_info_resend = false; | |
2551 | ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL; | |
2552 | } else if (IS_QLA27XX(ha)) { | |
2553 | ha->portnum = PCI_FUNC(ha->pdev->devfn); | |
2554 | ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; | |
2555 | ha->mbx_count = MAILBOX_REGISTER_COUNT; | |
2556 | req_length = REQUEST_ENTRY_CNT_24XX; | |
2557 | rsp_length = RESPONSE_ENTRY_CNT_2300; | |
2558 | ha->max_loop_id = SNS_LAST_LOOP_ID_2300; | |
2559 | ha->init_cb_size = sizeof(struct mid_init_cb_81xx); | |
2560 | ha->gid_list_info_size = 8; | |
2561 | ha->optrom_size = OPTROM_SIZE_83XX; | |
2562 | ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; | |
2563 | ha->isp_ops = &qla27xx_isp_ops; | |
2564 | ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; | |
2565 | ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; | |
2566 | ha->nvram_conf_off = ~0; | |
2567 | ha->nvram_data_off = ~0; | |
2568 | } | |
2569 | ||
2570 | ql_dbg_pci(ql_dbg_init, pdev, 0x001e, | |
2571 | "mbx_count=%d, req_length=%d, " | |
2572 | "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, " | |
2573 | "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, " | |
2574 | "max_fibre_devices=%d.\n", | |
2575 | ha->mbx_count, req_length, rsp_length, ha->max_loop_id, | |
2576 | ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size, | |
2577 | ha->nvram_npiv_size, ha->max_fibre_devices); | |
2578 | ql_dbg_pci(ql_dbg_init, pdev, 0x001f, | |
2579 | "isp_ops=%p, flash_conf_off=%d, " | |
2580 | "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n", | |
2581 | ha->isp_ops, ha->flash_conf_off, ha->flash_data_off, | |
2582 | ha->nvram_conf_off, ha->nvram_data_off); | |
2583 | ||
2584 | /* Configure PCI I/O space */ | |
2585 | ret = ha->isp_ops->iospace_config(ha); | |
2586 | if (ret) | |
2587 | goto iospace_config_failed; | |
2588 | ||
2589 | ql_log_pci(ql_log_info, pdev, 0x001d, | |
2590 | "Found an ISP%04X irq %d iobase 0x%p.\n", | |
2591 | pdev->device, pdev->irq, ha->iobase); | |
2592 | mutex_init(&ha->vport_lock); | |
2593 | init_completion(&ha->mbx_cmd_comp); | |
2594 | complete(&ha->mbx_cmd_comp); | |
2595 | init_completion(&ha->mbx_intr_comp); | |
2596 | init_completion(&ha->dcbx_comp); | |
2597 | init_completion(&ha->lb_portup_comp); | |
2598 | ||
2599 | set_bit(0, (unsigned long *) ha->vp_idx_map); | |
2600 | ||
2601 | qla2x00_config_dma_addressing(ha); | |
2602 | ql_dbg_pci(ql_dbg_init, pdev, 0x0020, | |
2603 | "64 Bit addressing is %s.\n", | |
2604 | ha->flags.enable_64bit_addressing ? "enable" : | |
2605 | "disable"); | |
2606 | ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp); | |
2607 | if (ret) { | |
2608 | ql_log_pci(ql_log_fatal, pdev, 0x0031, | |
2609 | "Failed to allocate memory for adapter, aborting.\n"); | |
2610 | ||
2611 | goto probe_hw_failed; | |
2612 | } | |
2613 | ||
2614 | req->max_q_depth = MAX_Q_DEPTH; | |
2615 | if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU) | |
2616 | req->max_q_depth = ql2xmaxqdepth; | |
2617 | ||
2618 | ||
2619 | base_vha = qla2x00_create_host(sht, ha); | |
2620 | if (!base_vha) { | |
2621 | ret = -ENOMEM; | |
2622 | qla2x00_mem_free(ha); | |
2623 | qla2x00_free_req_que(ha, req); | |
2624 | qla2x00_free_rsp_que(ha, rsp); | |
2625 | goto probe_hw_failed; | |
2626 | } | |
2627 | ||
2628 | pci_set_drvdata(pdev, base_vha); | |
2629 | set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); | |
2630 | ||
2631 | host = base_vha->host; | |
2632 | base_vha->req = req; | |
2633 | if (IS_QLA2XXX_MIDTYPE(ha)) | |
2634 | base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx; | |
2635 | else | |
2636 | base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER + | |
2637 | base_vha->vp_idx; | |
2638 | ||
2639 | /* Setup fcport template structure. */ | |
2640 | ha->mr.fcport.vha = base_vha; | |
2641 | ha->mr.fcport.port_type = FCT_UNKNOWN; | |
2642 | ha->mr.fcport.loop_id = FC_NO_LOOP_ID; | |
2643 | qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED); | |
2644 | ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED; | |
2645 | ha->mr.fcport.scan_state = 1; | |
2646 | ||
2647 | /* Set the SG table size based on ISP type */ | |
2648 | if (!IS_FWI2_CAPABLE(ha)) { | |
2649 | if (IS_QLA2100(ha)) | |
2650 | host->sg_tablesize = 32; | |
2651 | } else { | |
2652 | if (!IS_QLA82XX(ha)) | |
2653 | host->sg_tablesize = QLA_SG_ALL; | |
2654 | } | |
2655 | host->max_id = ha->max_fibre_devices; | |
2656 | host->cmd_per_lun = 3; | |
2657 | host->unique_id = host->host_no; | |
2658 | if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) | |
2659 | host->max_cmd_len = 32; | |
2660 | else | |
2661 | host->max_cmd_len = MAX_CMDSZ; | |
2662 | host->max_channel = MAX_BUSES - 1; | |
2663 | /* Older HBAs support only 16-bit LUNs */ | |
2664 | if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) && | |
2665 | ql2xmaxlun > 0xffff) | |
2666 | host->max_lun = 0xffff; | |
2667 | else | |
2668 | host->max_lun = ql2xmaxlun; | |
2669 | host->transportt = qla2xxx_transport_template; | |
2670 | sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC); | |
2671 | ||
2672 | ql_dbg(ql_dbg_init, base_vha, 0x0033, | |
2673 | "max_id=%d this_id=%d " | |
2674 | "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d " | |
2675 | "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id, | |
2676 | host->this_id, host->cmd_per_lun, host->unique_id, | |
2677 | host->max_cmd_len, host->max_channel, host->max_lun, | |
2678 | host->transportt, sht->vendor_id); | |
2679 | ||
2680 | que_init: | |
2681 | /* Alloc arrays of request and response ring ptrs */ | |
2682 | if (!qla2x00_alloc_queues(ha, req, rsp)) { | |
2683 | ql_log(ql_log_fatal, base_vha, 0x003d, | |
2684 | "Failed to allocate memory for queue pointers..." | |
2685 | "aborting.\n"); | |
2686 | goto probe_init_failed; | |
2687 | } | |
2688 | ||
2689 | qlt_probe_one_stage1(base_vha, ha); | |
2690 | ||
2691 | /* Set up the irqs */ | |
2692 | ret = qla2x00_request_irqs(ha, rsp); | |
2693 | if (ret) | |
2694 | goto probe_init_failed; | |
2695 | ||
2696 | pci_save_state(pdev); | |
2697 | ||
2698 | /* Assign back pointers */ | |
2699 | rsp->req = req; | |
2700 | req->rsp = rsp; | |
2701 | ||
2702 | if (IS_QLAFX00(ha)) { | |
2703 | ha->rsp_q_map[0] = rsp; | |
2704 | ha->req_q_map[0] = req; | |
2705 | set_bit(0, ha->req_qid_map); | |
2706 | set_bit(0, ha->rsp_qid_map); | |
2707 | } | |
2708 | ||
2709 | /* FWI2-capable only. */ | |
2710 | req->req_q_in = &ha->iobase->isp24.req_q_in; | |
2711 | req->req_q_out = &ha->iobase->isp24.req_q_out; | |
2712 | rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in; | |
2713 | rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out; | |
2714 | if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) { | |
2715 | req->req_q_in = &ha->mqiobase->isp25mq.req_q_in; | |
2716 | req->req_q_out = &ha->mqiobase->isp25mq.req_q_out; | |
2717 | rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in; | |
2718 | rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out; | |
2719 | } | |
2720 | ||
2721 | if (IS_QLAFX00(ha)) { | |
2722 | req->req_q_in = &ha->iobase->ispfx00.req_q_in; | |
2723 | req->req_q_out = &ha->iobase->ispfx00.req_q_out; | |
2724 | rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in; | |
2725 | rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out; | |
2726 | } | |
2727 | ||
2728 | if (IS_P3P_TYPE(ha)) { | |
2729 | req->req_q_out = &ha->iobase->isp82.req_q_out[0]; | |
2730 | rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0]; | |
2731 | rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0]; | |
2732 | } | |
2733 | ||
2734 | ql_dbg(ql_dbg_multiq, base_vha, 0xc009, | |
2735 | "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", | |
2736 | ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); | |
2737 | ql_dbg(ql_dbg_multiq, base_vha, 0xc00a, | |
2738 | "req->req_q_in=%p req->req_q_out=%p " | |
2739 | "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", | |
2740 | req->req_q_in, req->req_q_out, | |
2741 | rsp->rsp_q_in, rsp->rsp_q_out); | |
2742 | ql_dbg(ql_dbg_init, base_vha, 0x003e, | |
2743 | "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", | |
2744 | ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); | |
2745 | ql_dbg(ql_dbg_init, base_vha, 0x003f, | |
2746 | "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", | |
2747 | req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out); | |
2748 | ||
2749 | if (ha->isp_ops->initialize_adapter(base_vha)) { | |
2750 | ql_log(ql_log_fatal, base_vha, 0x00d6, | |
2751 | "Failed to initialize adapter - Adapter flags %x.\n", | |
2752 | base_vha->device_flags); | |
2753 | ||
2754 | if (IS_QLA82XX(ha)) { | |
2755 | qla82xx_idc_lock(ha); | |
2756 | qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, | |
2757 | QLA8XXX_DEV_FAILED); | |
2758 | qla82xx_idc_unlock(ha); | |
2759 | ql_log(ql_log_fatal, base_vha, 0x00d7, | |
2760 | "HW State: FAILED.\n"); | |
2761 | } else if (IS_QLA8044(ha)) { | |
2762 | qla8044_idc_lock(ha); | |
2763 | qla8044_wr_direct(base_vha, | |
2764 | QLA8044_CRB_DEV_STATE_INDEX, | |
2765 | QLA8XXX_DEV_FAILED); | |
2766 | qla8044_idc_unlock(ha); | |
2767 | ql_log(ql_log_fatal, base_vha, 0x0150, | |
2768 | "HW State: FAILED.\n"); | |
2769 | } | |
2770 | ||
2771 | ret = -ENODEV; | |
2772 | goto probe_failed; | |
2773 | } | |
2774 | ||
2775 | if (IS_QLAFX00(ha)) | |
2776 | host->can_queue = QLAFX00_MAX_CANQUEUE; | |
2777 | else | |
2778 | host->can_queue = req->num_outstanding_cmds - 10; | |
2779 | ||
2780 | ql_dbg(ql_dbg_init, base_vha, 0x0032, | |
2781 | "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n", | |
2782 | host->can_queue, base_vha->req, | |
2783 | base_vha->mgmt_svr_loop_id, host->sg_tablesize); | |
2784 | ||
2785 | if (ha->mqenable) { | |
2786 | if (qla25xx_setup_mode(base_vha)) { | |
2787 | ql_log(ql_log_warn, base_vha, 0x00ec, | |
2788 | "Failed to create queues, falling back to single queue mode.\n"); | |
2789 | goto que_init; | |
2790 | } | |
2791 | } | |
2792 | ||
2793 | if (ha->flags.running_gold_fw) | |
2794 | goto skip_dpc; | |
2795 | ||
2796 | /* | |
2797 | * Startup the kernel thread for this host adapter | |
2798 | */ | |
2799 | ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha, | |
2800 | "%s_dpc", base_vha->host_str); | |
2801 | if (IS_ERR(ha->dpc_thread)) { | |
2802 | ql_log(ql_log_fatal, base_vha, 0x00ed, | |
2803 | "Failed to start DPC thread.\n"); | |
2804 | ret = PTR_ERR(ha->dpc_thread); | |
2805 | goto probe_failed; | |
2806 | } | |
2807 | ql_dbg(ql_dbg_init, base_vha, 0x00ee, | |
2808 | "DPC thread started successfully.\n"); | |
2809 | ||
2810 | /* | |
2811 | * If we're not coming up in initiator mode, we might sit for | |
2812 | * a while without waking up the dpc thread, which leads to a | |
2813 | * stuck process warning. So just kick the dpc once here and | |
2814 | * let the kthread start (and go back to sleep in qla2x00_do_dpc). | |
2815 | */ | |
2816 | qla2xxx_wake_dpc(base_vha); | |
2817 | ||
2818 | INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error); | |
2819 | ||
2820 | if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) { | |
2821 | sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no); | |
2822 | ha->dpc_lp_wq = create_singlethread_workqueue(wq_name); | |
2823 | INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen); | |
2824 | ||
2825 | sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no); | |
2826 | ha->dpc_hp_wq = create_singlethread_workqueue(wq_name); | |
2827 | INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work); | |
2828 | INIT_WORK(&ha->idc_state_handler, | |
2829 | qla83xx_idc_state_handler_work); | |
2830 | INIT_WORK(&ha->nic_core_unrecoverable, | |
2831 | qla83xx_nic_core_unrecoverable_work); | |
2832 | } | |
2833 | ||
2834 | skip_dpc: | |
2835 | list_add_tail(&base_vha->list, &ha->vp_list); | |
2836 | base_vha->host->irq = ha->pdev->irq; | |
2837 | ||
2838 | /* Initialized the timer */ | |
2839 | qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL); | |
2840 | ql_dbg(ql_dbg_init, base_vha, 0x00ef, | |
2841 | "Started qla2x00_timer with " | |
2842 | "interval=%d.\n", WATCH_INTERVAL); | |
2843 | ql_dbg(ql_dbg_init, base_vha, 0x00f0, | |
2844 | "Detected hba at address=%p.\n", | |
2845 | ha); | |
2846 | ||
2847 | if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) { | |
2848 | if (ha->fw_attributes & BIT_4) { | |
2849 | int prot = 0, guard; | |
2850 | base_vha->flags.difdix_supported = 1; | |
2851 | ql_dbg(ql_dbg_init, base_vha, 0x00f1, | |
2852 | "Registering for DIF/DIX type 1 and 3 protection.\n"); | |
2853 | if (ql2xenabledif == 1) | |
2854 | prot = SHOST_DIX_TYPE0_PROTECTION; | |
2855 | scsi_host_set_prot(host, | |
2856 | prot | SHOST_DIF_TYPE1_PROTECTION | |
2857 | | SHOST_DIF_TYPE2_PROTECTION | |
2858 | | SHOST_DIF_TYPE3_PROTECTION | |
2859 | | SHOST_DIX_TYPE1_PROTECTION | |
2860 | | SHOST_DIX_TYPE2_PROTECTION | |
2861 | | SHOST_DIX_TYPE3_PROTECTION); | |
2862 | ||
2863 | guard = SHOST_DIX_GUARD_CRC; | |
2864 | ||
2865 | if (IS_PI_IPGUARD_CAPABLE(ha) && | |
2866 | (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha))) | |
2867 | guard |= SHOST_DIX_GUARD_IP; | |
2868 | ||
2869 | scsi_host_set_guard(host, guard); | |
2870 | } else | |
2871 | base_vha->flags.difdix_supported = 0; | |
2872 | } | |
2873 | ||
2874 | ha->isp_ops->enable_intrs(ha); | |
2875 | ||
2876 | if (IS_QLAFX00(ha)) { | |
2877 | ret = qlafx00_fx_disc(base_vha, | |
2878 | &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO); | |
2879 | host->sg_tablesize = (ha->mr.extended_io_enabled) ? | |
2880 | QLA_SG_ALL : 128; | |
2881 | } | |
2882 | ||
2883 | ret = scsi_add_host(host, &pdev->dev); | |
2884 | if (ret) | |
2885 | goto probe_failed; | |
2886 | ||
2887 | base_vha->flags.init_done = 1; | |
2888 | base_vha->flags.online = 1; | |
2889 | ha->prev_minidump_failed = 0; | |
2890 | ||
2891 | ql_dbg(ql_dbg_init, base_vha, 0x00f2, | |
2892 | "Init done and hba is online.\n"); | |
2893 | ||
2894 | if (qla_ini_mode_enabled(base_vha)) | |
2895 | scsi_scan_host(host); | |
2896 | else | |
2897 | ql_dbg(ql_dbg_init, base_vha, 0x0122, | |
2898 | "skipping scsi_scan_host() for non-initiator port\n"); | |
2899 | ||
2900 | qla2x00_alloc_sysfs_attr(base_vha); | |
2901 | ||
2902 | if (IS_QLAFX00(ha)) { | |
2903 | ret = qlafx00_fx_disc(base_vha, | |
2904 | &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO); | |
2905 | ||
2906 | /* Register system information */ | |
2907 | ret = qlafx00_fx_disc(base_vha, | |
2908 | &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO); | |
2909 | } | |
2910 | ||
2911 | qla2x00_init_host_attr(base_vha); | |
2912 | ||
2913 | qla2x00_dfs_setup(base_vha); | |
2914 | ||
2915 | ql_log(ql_log_info, base_vha, 0x00fb, | |
2916 | "QLogic %s - %s.\n", ha->model_number, ha->model_desc); | |
2917 | ql_log(ql_log_info, base_vha, 0x00fc, | |
2918 | "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n", | |
2919 | pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info), | |
2920 | pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-', | |
2921 | base_vha->host_no, | |
2922 | ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str))); | |
2923 | ||
2924 | qlt_add_target(ha, base_vha); | |
2925 | ||
2926 | clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); | |
2927 | return 0; | |
2928 | ||
2929 | probe_init_failed: | |
2930 | qla2x00_free_req_que(ha, req); | |
2931 | ha->req_q_map[0] = NULL; | |
2932 | clear_bit(0, ha->req_qid_map); | |
2933 | qla2x00_free_rsp_que(ha, rsp); | |
2934 | ha->rsp_q_map[0] = NULL; | |
2935 | clear_bit(0, ha->rsp_qid_map); | |
2936 | ha->max_req_queues = ha->max_rsp_queues = 0; | |
2937 | ||
2938 | probe_failed: | |
2939 | if (base_vha->timer_active) | |
2940 | qla2x00_stop_timer(base_vha); | |
2941 | base_vha->flags.online = 0; | |
2942 | if (ha->dpc_thread) { | |
2943 | struct task_struct *t = ha->dpc_thread; | |
2944 | ||
2945 | ha->dpc_thread = NULL; | |
2946 | kthread_stop(t); | |
2947 | } | |
2948 | ||
2949 | qla2x00_free_device(base_vha); | |
2950 | ||
2951 | scsi_host_put(base_vha->host); | |
2952 | ||
2953 | probe_hw_failed: | |
2954 | qla2x00_clear_drv_active(ha); | |
2955 | ||
2956 | iospace_config_failed: | |
2957 | if (IS_P3P_TYPE(ha)) { | |
2958 | if (!ha->nx_pcibase) | |
2959 | iounmap((device_reg_t *)ha->nx_pcibase); | |
2960 | if (!ql2xdbwr) | |
2961 | iounmap((device_reg_t *)ha->nxdb_wr_ptr); | |
2962 | } else { | |
2963 | if (ha->iobase) | |
2964 | iounmap(ha->iobase); | |
2965 | if (ha->cregbase) | |
2966 | iounmap(ha->cregbase); | |
2967 | } | |
2968 | pci_release_selected_regions(ha->pdev, ha->bars); | |
2969 | kfree(ha); | |
2970 | ha = NULL; | |
2971 | ||
2972 | probe_out: | |
2973 | pci_disable_device(pdev); | |
2974 | return ret; | |
2975 | } | |
2976 | ||
2977 | static void | |
2978 | qla2x00_shutdown(struct pci_dev *pdev) | |
2979 | { | |
2980 | scsi_qla_host_t *vha; | |
2981 | struct qla_hw_data *ha; | |
2982 | ||
2983 | if (!atomic_read(&pdev->enable_cnt)) | |
2984 | return; | |
2985 | ||
2986 | vha = pci_get_drvdata(pdev); | |
2987 | ha = vha->hw; | |
2988 | ||
2989 | /* Notify ISPFX00 firmware */ | |
2990 | if (IS_QLAFX00(ha)) | |
2991 | qlafx00_driver_shutdown(vha, 20); | |
2992 | ||
2993 | /* Turn-off FCE trace */ | |
2994 | if (ha->flags.fce_enabled) { | |
2995 | qla2x00_disable_fce_trace(vha, NULL, NULL); | |
2996 | ha->flags.fce_enabled = 0; | |
2997 | } | |
2998 | ||
2999 | /* Turn-off EFT trace */ | |
3000 | if (ha->eft) | |
3001 | qla2x00_disable_eft_trace(vha); | |
3002 | ||
3003 | /* Stop currently executing firmware. */ | |
3004 | qla2x00_try_to_stop_firmware(vha); | |
3005 | ||
3006 | /* Turn adapter off line */ | |
3007 | vha->flags.online = 0; | |
3008 | ||
3009 | /* turn-off interrupts on the card */ | |
3010 | if (ha->interrupts_on) { | |
3011 | vha->flags.init_done = 0; | |
3012 | ha->isp_ops->disable_intrs(ha); | |
3013 | } | |
3014 | ||
3015 | qla2x00_free_irqs(vha); | |
3016 | ||
3017 | qla2x00_free_fw_dump(ha); | |
3018 | ||
3019 | pci_disable_pcie_error_reporting(pdev); | |
3020 | pci_disable_device(pdev); | |
3021 | } | |
3022 | ||
3023 | /* Deletes all the virtual ports for a given ha */ | |
3024 | static void | |
3025 | qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha) | |
3026 | { | |
3027 | struct Scsi_Host *scsi_host; | |
3028 | scsi_qla_host_t *vha; | |
3029 | unsigned long flags; | |
3030 | ||
3031 | mutex_lock(&ha->vport_lock); | |
3032 | while (ha->cur_vport_count) { | |
3033 | spin_lock_irqsave(&ha->vport_slock, flags); | |
3034 | ||
3035 | BUG_ON(base_vha->list.next == &ha->vp_list); | |
3036 | /* This assumes first entry in ha->vp_list is always base vha */ | |
3037 | vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list); | |
3038 | scsi_host = scsi_host_get(vha->host); | |
3039 | ||
3040 | spin_unlock_irqrestore(&ha->vport_slock, flags); | |
3041 | mutex_unlock(&ha->vport_lock); | |
3042 | ||
3043 | fc_vport_terminate(vha->fc_vport); | |
3044 | scsi_host_put(vha->host); | |
3045 | ||
3046 | mutex_lock(&ha->vport_lock); | |
3047 | } | |
3048 | mutex_unlock(&ha->vport_lock); | |
3049 | } | |
3050 | ||
3051 | /* Stops all deferred work threads */ | |
3052 | static void | |
3053 | qla2x00_destroy_deferred_work(struct qla_hw_data *ha) | |
3054 | { | |
3055 | /* Flush the work queue and remove it */ | |
3056 | if (ha->wq) { | |
3057 | flush_workqueue(ha->wq); | |
3058 | destroy_workqueue(ha->wq); | |
3059 | ha->wq = NULL; | |
3060 | } | |
3061 | ||
3062 | /* Cancel all work and destroy DPC workqueues */ | |
3063 | if (ha->dpc_lp_wq) { | |
3064 | cancel_work_sync(&ha->idc_aen); | |
3065 | destroy_workqueue(ha->dpc_lp_wq); | |
3066 | ha->dpc_lp_wq = NULL; | |
3067 | } | |
3068 | ||
3069 | if (ha->dpc_hp_wq) { | |
3070 | cancel_work_sync(&ha->nic_core_reset); | |
3071 | cancel_work_sync(&ha->idc_state_handler); | |
3072 | cancel_work_sync(&ha->nic_core_unrecoverable); | |
3073 | destroy_workqueue(ha->dpc_hp_wq); | |
3074 | ha->dpc_hp_wq = NULL; | |
3075 | } | |
3076 | ||
3077 | /* Kill the kernel thread for this host */ | |
3078 | if (ha->dpc_thread) { | |
3079 | struct task_struct *t = ha->dpc_thread; | |
3080 | ||
3081 | /* | |
3082 | * qla2xxx_wake_dpc checks for ->dpc_thread | |
3083 | * so we need to zero it out. | |
3084 | */ | |
3085 | ha->dpc_thread = NULL; | |
3086 | kthread_stop(t); | |
3087 | } | |
3088 | } | |
3089 | ||
3090 | static void | |
3091 | qla2x00_unmap_iobases(struct qla_hw_data *ha) | |
3092 | { | |
3093 | if (IS_QLA82XX(ha)) { | |
3094 | ||
3095 | iounmap((device_reg_t *)ha->nx_pcibase); | |
3096 | if (!ql2xdbwr) | |
3097 | iounmap((device_reg_t *)ha->nxdb_wr_ptr); | |
3098 | } else { | |
3099 | if (ha->iobase) | |
3100 | iounmap(ha->iobase); | |
3101 | ||
3102 | if (ha->cregbase) | |
3103 | iounmap(ha->cregbase); | |
3104 | ||
3105 | if (ha->mqiobase) | |
3106 | iounmap(ha->mqiobase); | |
3107 | ||
3108 | if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase) | |
3109 | iounmap(ha->msixbase); | |
3110 | } | |
3111 | } | |
3112 | ||
3113 | static void | |
3114 | qla2x00_clear_drv_active(struct qla_hw_data *ha) | |
3115 | { | |
3116 | if (IS_QLA8044(ha)) { | |
3117 | qla8044_idc_lock(ha); | |
3118 | qla8044_clear_drv_active(ha); | |
3119 | qla8044_idc_unlock(ha); | |
3120 | } else if (IS_QLA82XX(ha)) { | |
3121 | qla82xx_idc_lock(ha); | |
3122 | qla82xx_clear_drv_active(ha); | |
3123 | qla82xx_idc_unlock(ha); | |
3124 | } | |
3125 | } | |
3126 | ||
3127 | static void | |
3128 | qla2x00_remove_one(struct pci_dev *pdev) | |
3129 | { | |
3130 | scsi_qla_host_t *base_vha; | |
3131 | struct qla_hw_data *ha; | |
3132 | ||
3133 | base_vha = pci_get_drvdata(pdev); | |
3134 | ha = base_vha->hw; | |
3135 | ||
3136 | /* Indicate device removal to prevent future board_disable and wait | |
3137 | * until any pending board_disable has completed. */ | |
3138 | set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags); | |
3139 | cancel_work_sync(&ha->board_disable); | |
3140 | ||
3141 | /* | |
3142 | * If the PCI device is disabled then there was a PCI-disconnect and | |
3143 | * qla2x00_disable_board_on_pci_error has taken care of most of the | |
3144 | * resources. | |
3145 | */ | |
3146 | if (!atomic_read(&pdev->enable_cnt)) { | |
3147 | scsi_host_put(base_vha->host); | |
3148 | kfree(ha); | |
3149 | pci_set_drvdata(pdev, NULL); | |
3150 | return; | |
3151 | } | |
3152 | ||
3153 | qla2x00_wait_for_hba_ready(base_vha); | |
3154 | ||
3155 | set_bit(UNLOADING, &base_vha->dpc_flags); | |
3156 | ||
3157 | if (IS_QLAFX00(ha)) | |
3158 | qlafx00_driver_shutdown(base_vha, 20); | |
3159 | ||
3160 | qla2x00_delete_all_vps(ha, base_vha); | |
3161 | ||
3162 | if (IS_QLA8031(ha)) { | |
3163 | ql_dbg(ql_dbg_p3p, base_vha, 0xb07e, | |
3164 | "Clearing fcoe driver presence.\n"); | |
3165 | if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS) | |
3166 | ql_dbg(ql_dbg_p3p, base_vha, 0xb079, | |
3167 | "Error while clearing DRV-Presence.\n"); | |
3168 | } | |
3169 | ||
3170 | qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); | |
3171 | ||
3172 | qla2x00_dfs_remove(base_vha); | |
3173 | ||
3174 | qla84xx_put_chip(base_vha); | |
3175 | ||
3176 | /* Laser should be disabled only for ISP2031 */ | |
3177 | if (IS_QLA2031(ha)) | |
3178 | qla83xx_disable_laser(base_vha); | |
3179 | ||
3180 | /* Disable timer */ | |
3181 | if (base_vha->timer_active) | |
3182 | qla2x00_stop_timer(base_vha); | |
3183 | ||
3184 | base_vha->flags.online = 0; | |
3185 | ||
3186 | qla2x00_destroy_deferred_work(ha); | |
3187 | ||
3188 | qlt_remove_target(ha, base_vha); | |
3189 | ||
3190 | qla2x00_free_sysfs_attr(base_vha, true); | |
3191 | ||
3192 | fc_remove_host(base_vha->host); | |
3193 | ||
3194 | scsi_remove_host(base_vha->host); | |
3195 | ||
3196 | qla2x00_free_device(base_vha); | |
3197 | ||
3198 | qla2x00_clear_drv_active(ha); | |
3199 | ||
3200 | scsi_host_put(base_vha->host); | |
3201 | ||
3202 | qla2x00_unmap_iobases(ha); | |
3203 | ||
3204 | pci_release_selected_regions(ha->pdev, ha->bars); | |
3205 | kfree(ha); | |
3206 | ha = NULL; | |
3207 | ||
3208 | pci_disable_pcie_error_reporting(pdev); | |
3209 | ||
3210 | pci_disable_device(pdev); | |
3211 | } | |
3212 | ||
3213 | static void | |
3214 | qla2x00_free_device(scsi_qla_host_t *vha) | |
3215 | { | |
3216 | struct qla_hw_data *ha = vha->hw; | |
3217 | ||
3218 | qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); | |
3219 | ||
3220 | /* Disable timer */ | |
3221 | if (vha->timer_active) | |
3222 | qla2x00_stop_timer(vha); | |
3223 | ||
3224 | qla25xx_delete_queues(vha); | |
3225 | ||
3226 | if (ha->flags.fce_enabled) | |
3227 | qla2x00_disable_fce_trace(vha, NULL, NULL); | |
3228 | ||
3229 | if (ha->eft) | |
3230 | qla2x00_disable_eft_trace(vha); | |
3231 | ||
3232 | /* Stop currently executing firmware. */ | |
3233 | qla2x00_try_to_stop_firmware(vha); | |
3234 | ||
3235 | vha->flags.online = 0; | |
3236 | ||
3237 | /* turn-off interrupts on the card */ | |
3238 | if (ha->interrupts_on) { | |
3239 | vha->flags.init_done = 0; | |
3240 | ha->isp_ops->disable_intrs(ha); | |
3241 | } | |
3242 | ||
3243 | qla2x00_free_irqs(vha); | |
3244 | ||
3245 | qla2x00_free_fcports(vha); | |
3246 | ||
3247 | qla2x00_mem_free(ha); | |
3248 | ||
3249 | qla82xx_md_free(vha); | |
3250 | ||
3251 | qla2x00_free_queues(ha); | |
3252 | } | |
3253 | ||
3254 | void qla2x00_free_fcports(struct scsi_qla_host *vha) | |
3255 | { | |
3256 | fc_port_t *fcport, *tfcport; | |
3257 | ||
3258 | list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) { | |
3259 | list_del(&fcport->list); | |
3260 | qla2x00_clear_loop_id(fcport); | |
3261 | kfree(fcport); | |
3262 | fcport = NULL; | |
3263 | } | |
3264 | } | |
3265 | ||
3266 | static inline void | |
3267 | qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport, | |
3268 | int defer) | |
3269 | { | |
3270 | struct fc_rport *rport; | |
3271 | scsi_qla_host_t *base_vha; | |
3272 | unsigned long flags; | |
3273 | ||
3274 | if (!fcport->rport) | |
3275 | return; | |
3276 | ||
3277 | rport = fcport->rport; | |
3278 | if (defer) { | |
3279 | base_vha = pci_get_drvdata(vha->hw->pdev); | |
3280 | spin_lock_irqsave(vha->host->host_lock, flags); | |
3281 | fcport->drport = rport; | |
3282 | spin_unlock_irqrestore(vha->host->host_lock, flags); | |
3283 | set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags); | |
3284 | qla2xxx_wake_dpc(base_vha); | |
3285 | } else { | |
3286 | fc_remote_port_delete(rport); | |
3287 | qlt_fc_port_deleted(vha, fcport); | |
3288 | } | |
3289 | } | |
3290 | ||
3291 | /* | |
3292 | * qla2x00_mark_device_lost Updates fcport state when device goes offline. | |
3293 | * | |
3294 | * Input: ha = adapter block pointer. fcport = port structure pointer. | |
3295 | * | |
3296 | * Return: None. | |
3297 | * | |
3298 | * Context: | |
3299 | */ | |
3300 | void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport, | |
3301 | int do_login, int defer) | |
3302 | { | |
3303 | if (IS_QLAFX00(vha->hw)) { | |
3304 | qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); | |
3305 | qla2x00_schedule_rport_del(vha, fcport, defer); | |
3306 | return; | |
3307 | } | |
3308 | ||
3309 | if (atomic_read(&fcport->state) == FCS_ONLINE && | |
3310 | vha->vp_idx == fcport->vha->vp_idx) { | |
3311 | qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); | |
3312 | qla2x00_schedule_rport_del(vha, fcport, defer); | |
3313 | } | |
3314 | /* | |
3315 | * We may need to retry the login, so don't change the state of the | |
3316 | * port but do the retries. | |
3317 | */ | |
3318 | if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD) | |
3319 | qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); | |
3320 | ||
3321 | if (!do_login) | |
3322 | return; | |
3323 | ||
3324 | if (fcport->login_retry == 0) { | |
3325 | fcport->login_retry = vha->hw->login_retry_count; | |
3326 | set_bit(RELOGIN_NEEDED, &vha->dpc_flags); | |
3327 | ||
3328 | ql_dbg(ql_dbg_disc, vha, 0x2067, | |
3329 | "Port login retry %8phN, id = 0x%04x retry cnt=%d.\n", | |
3330 | fcport->port_name, fcport->loop_id, fcport->login_retry); | |
3331 | } | |
3332 | } | |
3333 | ||
3334 | /* | |
3335 | * qla2x00_mark_all_devices_lost | |
3336 | * Updates fcport state when device goes offline. | |
3337 | * | |
3338 | * Input: | |
3339 | * ha = adapter block pointer. | |
3340 | * fcport = port structure pointer. | |
3341 | * | |
3342 | * Return: | |
3343 | * None. | |
3344 | * | |
3345 | * Context: | |
3346 | */ | |
3347 | void | |
3348 | qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer) | |
3349 | { | |
3350 | fc_port_t *fcport; | |
3351 | ||
3352 | list_for_each_entry(fcport, &vha->vp_fcports, list) { | |
3353 | if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx) | |
3354 | continue; | |
3355 | ||
3356 | /* | |
3357 | * No point in marking the device as lost, if the device is | |
3358 | * already DEAD. | |
3359 | */ | |
3360 | if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD) | |
3361 | continue; | |
3362 | if (atomic_read(&fcport->state) == FCS_ONLINE) { | |
3363 | qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); | |
3364 | if (defer) | |
3365 | qla2x00_schedule_rport_del(vha, fcport, defer); | |
3366 | else if (vha->vp_idx == fcport->vha->vp_idx) | |
3367 | qla2x00_schedule_rport_del(vha, fcport, defer); | |
3368 | } | |
3369 | } | |
3370 | } | |
3371 | ||
3372 | /* | |
3373 | * qla2x00_mem_alloc | |
3374 | * Allocates adapter memory. | |
3375 | * | |
3376 | * Returns: | |
3377 | * 0 = success. | |
3378 | * !0 = failure. | |
3379 | */ | |
3380 | static int | |
3381 | qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len, | |
3382 | struct req_que **req, struct rsp_que **rsp) | |
3383 | { | |
3384 | char name[16]; | |
3385 | ||
3386 | ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size, | |
3387 | &ha->init_cb_dma, GFP_KERNEL); | |
3388 | if (!ha->init_cb) | |
3389 | goto fail; | |
3390 | ||
3391 | if (qlt_mem_alloc(ha) < 0) | |
3392 | goto fail_free_init_cb; | |
3393 | ||
3394 | ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, | |
3395 | qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL); | |
3396 | if (!ha->gid_list) | |
3397 | goto fail_free_tgt_mem; | |
3398 | ||
3399 | ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep); | |
3400 | if (!ha->srb_mempool) | |
3401 | goto fail_free_gid_list; | |
3402 | ||
3403 | if (IS_P3P_TYPE(ha)) { | |
3404 | /* Allocate cache for CT6 Ctx. */ | |
3405 | if (!ctx_cachep) { | |
3406 | ctx_cachep = kmem_cache_create("qla2xxx_ctx", | |
3407 | sizeof(struct ct6_dsd), 0, | |
3408 | SLAB_HWCACHE_ALIGN, NULL); | |
3409 | if (!ctx_cachep) | |
3410 | goto fail_free_gid_list; | |
3411 | } | |
3412 | ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ, | |
3413 | ctx_cachep); | |
3414 | if (!ha->ctx_mempool) | |
3415 | goto fail_free_srb_mempool; | |
3416 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021, | |
3417 | "ctx_cachep=%p ctx_mempool=%p.\n", | |
3418 | ctx_cachep, ha->ctx_mempool); | |
3419 | } | |
3420 | ||
3421 | /* Get memory for cached NVRAM */ | |
3422 | ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL); | |
3423 | if (!ha->nvram) | |
3424 | goto fail_free_ctx_mempool; | |
3425 | ||
3426 | snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME, | |
3427 | ha->pdev->device); | |
3428 | ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev, | |
3429 | DMA_POOL_SIZE, 8, 0); | |
3430 | if (!ha->s_dma_pool) | |
3431 | goto fail_free_nvram; | |
3432 | ||
3433 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022, | |
3434 | "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n", | |
3435 | ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool); | |
3436 | ||
3437 | if (IS_P3P_TYPE(ha) || ql2xenabledif) { | |
3438 | ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev, | |
3439 | DSD_LIST_DMA_POOL_SIZE, 8, 0); | |
3440 | if (!ha->dl_dma_pool) { | |
3441 | ql_log_pci(ql_log_fatal, ha->pdev, 0x0023, | |
3442 | "Failed to allocate memory for dl_dma_pool.\n"); | |
3443 | goto fail_s_dma_pool; | |
3444 | } | |
3445 | ||
3446 | ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev, | |
3447 | FCP_CMND_DMA_POOL_SIZE, 8, 0); | |
3448 | if (!ha->fcp_cmnd_dma_pool) { | |
3449 | ql_log_pci(ql_log_fatal, ha->pdev, 0x0024, | |
3450 | "Failed to allocate memory for fcp_cmnd_dma_pool.\n"); | |
3451 | goto fail_dl_dma_pool; | |
3452 | } | |
3453 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025, | |
3454 | "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n", | |
3455 | ha->dl_dma_pool, ha->fcp_cmnd_dma_pool); | |
3456 | } | |
3457 | ||
3458 | /* Allocate memory for SNS commands */ | |
3459 | if (IS_QLA2100(ha) || IS_QLA2200(ha)) { | |
3460 | /* Get consistent memory allocated for SNS commands */ | |
3461 | ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev, | |
3462 | sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL); | |
3463 | if (!ha->sns_cmd) | |
3464 | goto fail_dma_pool; | |
3465 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026, | |
3466 | "sns_cmd: %p.\n", ha->sns_cmd); | |
3467 | } else { | |
3468 | /* Get consistent memory allocated for MS IOCB */ | |
3469 | ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, | |
3470 | &ha->ms_iocb_dma); | |
3471 | if (!ha->ms_iocb) | |
3472 | goto fail_dma_pool; | |
3473 | /* Get consistent memory allocated for CT SNS commands */ | |
3474 | ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev, | |
3475 | sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL); | |
3476 | if (!ha->ct_sns) | |
3477 | goto fail_free_ms_iocb; | |
3478 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027, | |
3479 | "ms_iocb=%p ct_sns=%p.\n", | |
3480 | ha->ms_iocb, ha->ct_sns); | |
3481 | } | |
3482 | ||
3483 | /* Allocate memory for request ring */ | |
3484 | *req = kzalloc(sizeof(struct req_que), GFP_KERNEL); | |
3485 | if (!*req) { | |
3486 | ql_log_pci(ql_log_fatal, ha->pdev, 0x0028, | |
3487 | "Failed to allocate memory for req.\n"); | |
3488 | goto fail_req; | |
3489 | } | |
3490 | (*req)->length = req_len; | |
3491 | (*req)->ring = dma_alloc_coherent(&ha->pdev->dev, | |
3492 | ((*req)->length + 1) * sizeof(request_t), | |
3493 | &(*req)->dma, GFP_KERNEL); | |
3494 | if (!(*req)->ring) { | |
3495 | ql_log_pci(ql_log_fatal, ha->pdev, 0x0029, | |
3496 | "Failed to allocate memory for req_ring.\n"); | |
3497 | goto fail_req_ring; | |
3498 | } | |
3499 | /* Allocate memory for response ring */ | |
3500 | *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL); | |
3501 | if (!*rsp) { | |
3502 | ql_log_pci(ql_log_fatal, ha->pdev, 0x002a, | |
3503 | "Failed to allocate memory for rsp.\n"); | |
3504 | goto fail_rsp; | |
3505 | } | |
3506 | (*rsp)->hw = ha; | |
3507 | (*rsp)->length = rsp_len; | |
3508 | (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev, | |
3509 | ((*rsp)->length + 1) * sizeof(response_t), | |
3510 | &(*rsp)->dma, GFP_KERNEL); | |
3511 | if (!(*rsp)->ring) { | |
3512 | ql_log_pci(ql_log_fatal, ha->pdev, 0x002b, | |
3513 | "Failed to allocate memory for rsp_ring.\n"); | |
3514 | goto fail_rsp_ring; | |
3515 | } | |
3516 | (*req)->rsp = *rsp; | |
3517 | (*rsp)->req = *req; | |
3518 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c, | |
3519 | "req=%p req->length=%d req->ring=%p rsp=%p " | |
3520 | "rsp->length=%d rsp->ring=%p.\n", | |
3521 | *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length, | |
3522 | (*rsp)->ring); | |
3523 | /* Allocate memory for NVRAM data for vports */ | |
3524 | if (ha->nvram_npiv_size) { | |
3525 | ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) * | |
3526 | ha->nvram_npiv_size, GFP_KERNEL); | |
3527 | if (!ha->npiv_info) { | |
3528 | ql_log_pci(ql_log_fatal, ha->pdev, 0x002d, | |
3529 | "Failed to allocate memory for npiv_info.\n"); | |
3530 | goto fail_npiv_info; | |
3531 | } | |
3532 | } else | |
3533 | ha->npiv_info = NULL; | |
3534 | ||
3535 | /* Get consistent memory allocated for EX-INIT-CB. */ | |
3536 | if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) { | |
3537 | ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, | |
3538 | &ha->ex_init_cb_dma); | |
3539 | if (!ha->ex_init_cb) | |
3540 | goto fail_ex_init_cb; | |
3541 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e, | |
3542 | "ex_init_cb=%p.\n", ha->ex_init_cb); | |
3543 | } | |
3544 | ||
3545 | INIT_LIST_HEAD(&ha->gbl_dsd_list); | |
3546 | ||
3547 | /* Get consistent memory allocated for Async Port-Database. */ | |
3548 | if (!IS_FWI2_CAPABLE(ha)) { | |
3549 | ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, | |
3550 | &ha->async_pd_dma); | |
3551 | if (!ha->async_pd) | |
3552 | goto fail_async_pd; | |
3553 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f, | |
3554 | "async_pd=%p.\n", ha->async_pd); | |
3555 | } | |
3556 | ||
3557 | INIT_LIST_HEAD(&ha->vp_list); | |
3558 | ||
3559 | /* Allocate memory for our loop_id bitmap */ | |
3560 | ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long), | |
3561 | GFP_KERNEL); | |
3562 | if (!ha->loop_id_map) | |
3563 | goto fail_async_pd; | |
3564 | else { | |
3565 | qla2x00_set_reserved_loop_ids(ha); | |
3566 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123, | |
3567 | "loop_id_map=%p.\n", ha->loop_id_map); | |
3568 | } | |
3569 | ||
3570 | return 0; | |
3571 | ||
3572 | fail_async_pd: | |
3573 | dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma); | |
3574 | fail_ex_init_cb: | |
3575 | kfree(ha->npiv_info); | |
3576 | fail_npiv_info: | |
3577 | dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) * | |
3578 | sizeof(response_t), (*rsp)->ring, (*rsp)->dma); | |
3579 | (*rsp)->ring = NULL; | |
3580 | (*rsp)->dma = 0; | |
3581 | fail_rsp_ring: | |
3582 | kfree(*rsp); | |
3583 | fail_rsp: | |
3584 | dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) * | |
3585 | sizeof(request_t), (*req)->ring, (*req)->dma); | |
3586 | (*req)->ring = NULL; | |
3587 | (*req)->dma = 0; | |
3588 | fail_req_ring: | |
3589 | kfree(*req); | |
3590 | fail_req: | |
3591 | dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), | |
3592 | ha->ct_sns, ha->ct_sns_dma); | |
3593 | ha->ct_sns = NULL; | |
3594 | ha->ct_sns_dma = 0; | |
3595 | fail_free_ms_iocb: | |
3596 | dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); | |
3597 | ha->ms_iocb = NULL; | |
3598 | ha->ms_iocb_dma = 0; | |
3599 | fail_dma_pool: | |
3600 | if (IS_QLA82XX(ha) || ql2xenabledif) { | |
3601 | dma_pool_destroy(ha->fcp_cmnd_dma_pool); | |
3602 | ha->fcp_cmnd_dma_pool = NULL; | |
3603 | } | |
3604 | fail_dl_dma_pool: | |
3605 | if (IS_QLA82XX(ha) || ql2xenabledif) { | |
3606 | dma_pool_destroy(ha->dl_dma_pool); | |
3607 | ha->dl_dma_pool = NULL; | |
3608 | } | |
3609 | fail_s_dma_pool: | |
3610 | dma_pool_destroy(ha->s_dma_pool); | |
3611 | ha->s_dma_pool = NULL; | |
3612 | fail_free_nvram: | |
3613 | kfree(ha->nvram); | |
3614 | ha->nvram = NULL; | |
3615 | fail_free_ctx_mempool: | |
3616 | mempool_destroy(ha->ctx_mempool); | |
3617 | ha->ctx_mempool = NULL; | |
3618 | fail_free_srb_mempool: | |
3619 | mempool_destroy(ha->srb_mempool); | |
3620 | ha->srb_mempool = NULL; | |
3621 | fail_free_gid_list: | |
3622 | dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), | |
3623 | ha->gid_list, | |
3624 | ha->gid_list_dma); | |
3625 | ha->gid_list = NULL; | |
3626 | ha->gid_list_dma = 0; | |
3627 | fail_free_tgt_mem: | |
3628 | qlt_mem_free(ha); | |
3629 | fail_free_init_cb: | |
3630 | dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb, | |
3631 | ha->init_cb_dma); | |
3632 | ha->init_cb = NULL; | |
3633 | ha->init_cb_dma = 0; | |
3634 | fail: | |
3635 | ql_log(ql_log_fatal, NULL, 0x0030, | |
3636 | "Memory allocation failure.\n"); | |
3637 | return -ENOMEM; | |
3638 | } | |
3639 | ||
3640 | /* | |
3641 | * qla2x00_free_fw_dump | |
3642 | * Frees fw dump stuff. | |
3643 | * | |
3644 | * Input: | |
3645 | * ha = adapter block pointer | |
3646 | */ | |
3647 | static void | |
3648 | qla2x00_free_fw_dump(struct qla_hw_data *ha) | |
3649 | { | |
3650 | if (ha->fce) | |
3651 | dma_free_coherent(&ha->pdev->dev, | |
3652 | FCE_SIZE, ha->fce, ha->fce_dma); | |
3653 | ||
3654 | if (ha->eft) | |
3655 | dma_free_coherent(&ha->pdev->dev, | |
3656 | EFT_SIZE, ha->eft, ha->eft_dma); | |
3657 | ||
3658 | if (ha->fw_dump) | |
3659 | vfree(ha->fw_dump); | |
3660 | if (ha->fw_dump_template) | |
3661 | vfree(ha->fw_dump_template); | |
3662 | ||
3663 | ha->fce = NULL; | |
3664 | ha->fce_dma = 0; | |
3665 | ha->eft = NULL; | |
3666 | ha->eft_dma = 0; | |
3667 | ha->fw_dumped = 0; | |
3668 | ha->fw_dump_cap_flags = 0; | |
3669 | ha->fw_dump_reading = 0; | |
3670 | ha->fw_dump = NULL; | |
3671 | ha->fw_dump_len = 0; | |
3672 | ha->fw_dump_template = NULL; | |
3673 | ha->fw_dump_template_len = 0; | |
3674 | } | |
3675 | ||
3676 | /* | |
3677 | * qla2x00_mem_free | |
3678 | * Frees all adapter allocated memory. | |
3679 | * | |
3680 | * Input: | |
3681 | * ha = adapter block pointer. | |
3682 | */ | |
3683 | static void | |
3684 | qla2x00_mem_free(struct qla_hw_data *ha) | |
3685 | { | |
3686 | qla2x00_free_fw_dump(ha); | |
3687 | ||
3688 | if (ha->mctp_dump) | |
3689 | dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump, | |
3690 | ha->mctp_dump_dma); | |
3691 | ||
3692 | if (ha->srb_mempool) | |
3693 | mempool_destroy(ha->srb_mempool); | |
3694 | ||
3695 | if (ha->dcbx_tlv) | |
3696 | dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE, | |
3697 | ha->dcbx_tlv, ha->dcbx_tlv_dma); | |
3698 | ||
3699 | if (ha->xgmac_data) | |
3700 | dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE, | |
3701 | ha->xgmac_data, ha->xgmac_data_dma); | |
3702 | ||
3703 | if (ha->sns_cmd) | |
3704 | dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), | |
3705 | ha->sns_cmd, ha->sns_cmd_dma); | |
3706 | ||
3707 | if (ha->ct_sns) | |
3708 | dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), | |
3709 | ha->ct_sns, ha->ct_sns_dma); | |
3710 | ||
3711 | if (ha->sfp_data) | |
3712 | dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma); | |
3713 | ||
3714 | if (ha->ms_iocb) | |
3715 | dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); | |
3716 | ||
3717 | if (ha->ex_init_cb) | |
3718 | dma_pool_free(ha->s_dma_pool, | |
3719 | ha->ex_init_cb, ha->ex_init_cb_dma); | |
3720 | ||
3721 | if (ha->async_pd) | |
3722 | dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); | |
3723 | ||
3724 | if (ha->s_dma_pool) | |
3725 | dma_pool_destroy(ha->s_dma_pool); | |
3726 | ||
3727 | if (ha->gid_list) | |
3728 | dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), | |
3729 | ha->gid_list, ha->gid_list_dma); | |
3730 | ||
3731 | if (IS_QLA82XX(ha)) { | |
3732 | if (!list_empty(&ha->gbl_dsd_list)) { | |
3733 | struct dsd_dma *dsd_ptr, *tdsd_ptr; | |
3734 | ||
3735 | /* clean up allocated prev pool */ | |
3736 | list_for_each_entry_safe(dsd_ptr, | |
3737 | tdsd_ptr, &ha->gbl_dsd_list, list) { | |
3738 | dma_pool_free(ha->dl_dma_pool, | |
3739 | dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma); | |
3740 | list_del(&dsd_ptr->list); | |
3741 | kfree(dsd_ptr); | |
3742 | } | |
3743 | } | |
3744 | } | |
3745 | ||
3746 | if (ha->dl_dma_pool) | |
3747 | dma_pool_destroy(ha->dl_dma_pool); | |
3748 | ||
3749 | if (ha->fcp_cmnd_dma_pool) | |
3750 | dma_pool_destroy(ha->fcp_cmnd_dma_pool); | |
3751 | ||
3752 | if (ha->ctx_mempool) | |
3753 | mempool_destroy(ha->ctx_mempool); | |
3754 | ||
3755 | qlt_mem_free(ha); | |
3756 | ||
3757 | if (ha->init_cb) | |
3758 | dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, | |
3759 | ha->init_cb, ha->init_cb_dma); | |
3760 | vfree(ha->optrom_buffer); | |
3761 | kfree(ha->nvram); | |
3762 | kfree(ha->npiv_info); | |
3763 | kfree(ha->swl); | |
3764 | kfree(ha->loop_id_map); | |
3765 | ||
3766 | ha->srb_mempool = NULL; | |
3767 | ha->ctx_mempool = NULL; | |
3768 | ha->sns_cmd = NULL; | |
3769 | ha->sns_cmd_dma = 0; | |
3770 | ha->ct_sns = NULL; | |
3771 | ha->ct_sns_dma = 0; | |
3772 | ha->ms_iocb = NULL; | |
3773 | ha->ms_iocb_dma = 0; | |
3774 | ha->init_cb = NULL; | |
3775 | ha->init_cb_dma = 0; | |
3776 | ha->ex_init_cb = NULL; | |
3777 | ha->ex_init_cb_dma = 0; | |
3778 | ha->async_pd = NULL; | |
3779 | ha->async_pd_dma = 0; | |
3780 | ||
3781 | ha->s_dma_pool = NULL; | |
3782 | ha->dl_dma_pool = NULL; | |
3783 | ha->fcp_cmnd_dma_pool = NULL; | |
3784 | ||
3785 | ha->gid_list = NULL; | |
3786 | ha->gid_list_dma = 0; | |
3787 | ||
3788 | ha->tgt.atio_ring = NULL; | |
3789 | ha->tgt.atio_dma = 0; | |
3790 | ha->tgt.tgt_vp_map = NULL; | |
3791 | } | |
3792 | ||
3793 | struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht, | |
3794 | struct qla_hw_data *ha) | |
3795 | { | |
3796 | struct Scsi_Host *host; | |
3797 | struct scsi_qla_host *vha = NULL; | |
3798 | ||
3799 | host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t)); | |
3800 | if (host == NULL) { | |
3801 | ql_log_pci(ql_log_fatal, ha->pdev, 0x0107, | |
3802 | "Failed to allocate host from the scsi layer, aborting.\n"); | |
3803 | goto fail; | |
3804 | } | |
3805 | ||
3806 | /* Clear our data area */ | |
3807 | vha = shost_priv(host); | |
3808 | memset(vha, 0, sizeof(scsi_qla_host_t)); | |
3809 | ||
3810 | vha->host = host; | |
3811 | vha->host_no = host->host_no; | |
3812 | vha->hw = ha; | |
3813 | ||
3814 | INIT_LIST_HEAD(&vha->vp_fcports); | |
3815 | INIT_LIST_HEAD(&vha->work_list); | |
3816 | INIT_LIST_HEAD(&vha->list); | |
3817 | ||
3818 | spin_lock_init(&vha->work_lock); | |
3819 | ||
3820 | sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no); | |
3821 | ql_dbg(ql_dbg_init, vha, 0x0041, | |
3822 | "Allocated the host=%p hw=%p vha=%p dev_name=%s", | |
3823 | vha->host, vha->hw, vha, | |
3824 | dev_name(&(ha->pdev->dev))); | |
3825 | ||
3826 | return vha; | |
3827 | ||
3828 | fail: | |
3829 | return vha; | |
3830 | } | |
3831 | ||
3832 | static struct qla_work_evt * | |
3833 | qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type) | |
3834 | { | |
3835 | struct qla_work_evt *e; | |
3836 | uint8_t bail; | |
3837 | ||
3838 | QLA_VHA_MARK_BUSY(vha, bail); | |
3839 | if (bail) | |
3840 | return NULL; | |
3841 | ||
3842 | e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC); | |
3843 | if (!e) { | |
3844 | QLA_VHA_MARK_NOT_BUSY(vha); | |
3845 | return NULL; | |
3846 | } | |
3847 | ||
3848 | INIT_LIST_HEAD(&e->list); | |
3849 | e->type = type; | |
3850 | e->flags = QLA_EVT_FLAG_FREE; | |
3851 | return e; | |
3852 | } | |
3853 | ||
3854 | static int | |
3855 | qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e) | |
3856 | { | |
3857 | unsigned long flags; | |
3858 | ||
3859 | spin_lock_irqsave(&vha->work_lock, flags); | |
3860 | list_add_tail(&e->list, &vha->work_list); | |
3861 | spin_unlock_irqrestore(&vha->work_lock, flags); | |
3862 | qla2xxx_wake_dpc(vha); | |
3863 | ||
3864 | return QLA_SUCCESS; | |
3865 | } | |
3866 | ||
3867 | int | |
3868 | qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code, | |
3869 | u32 data) | |
3870 | { | |
3871 | struct qla_work_evt *e; | |
3872 | ||
3873 | e = qla2x00_alloc_work(vha, QLA_EVT_AEN); | |
3874 | if (!e) | |
3875 | return QLA_FUNCTION_FAILED; | |
3876 | ||
3877 | e->u.aen.code = code; | |
3878 | e->u.aen.data = data; | |
3879 | return qla2x00_post_work(vha, e); | |
3880 | } | |
3881 | ||
3882 | int | |
3883 | qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb) | |
3884 | { | |
3885 | struct qla_work_evt *e; | |
3886 | ||
3887 | e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK); | |
3888 | if (!e) | |
3889 | return QLA_FUNCTION_FAILED; | |
3890 | ||
3891 | memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t)); | |
3892 | return qla2x00_post_work(vha, e); | |
3893 | } | |
3894 | ||
3895 | #define qla2x00_post_async_work(name, type) \ | |
3896 | int qla2x00_post_async_##name##_work( \ | |
3897 | struct scsi_qla_host *vha, \ | |
3898 | fc_port_t *fcport, uint16_t *data) \ | |
3899 | { \ | |
3900 | struct qla_work_evt *e; \ | |
3901 | \ | |
3902 | e = qla2x00_alloc_work(vha, type); \ | |
3903 | if (!e) \ | |
3904 | return QLA_FUNCTION_FAILED; \ | |
3905 | \ | |
3906 | e->u.logio.fcport = fcport; \ | |
3907 | if (data) { \ | |
3908 | e->u.logio.data[0] = data[0]; \ | |
3909 | e->u.logio.data[1] = data[1]; \ | |
3910 | } \ | |
3911 | return qla2x00_post_work(vha, e); \ | |
3912 | } | |
3913 | ||
3914 | qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN); | |
3915 | qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE); | |
3916 | qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT); | |
3917 | qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE); | |
3918 | qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC); | |
3919 | qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE); | |
3920 | ||
3921 | int | |
3922 | qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code) | |
3923 | { | |
3924 | struct qla_work_evt *e; | |
3925 | ||
3926 | e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT); | |
3927 | if (!e) | |
3928 | return QLA_FUNCTION_FAILED; | |
3929 | ||
3930 | e->u.uevent.code = code; | |
3931 | return qla2x00_post_work(vha, e); | |
3932 | } | |
3933 | ||
3934 | static void | |
3935 | qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code) | |
3936 | { | |
3937 | char event_string[40]; | |
3938 | char *envp[] = { event_string, NULL }; | |
3939 | ||
3940 | switch (code) { | |
3941 | case QLA_UEVENT_CODE_FW_DUMP: | |
3942 | snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld", | |
3943 | vha->host_no); | |
3944 | break; | |
3945 | default: | |
3946 | /* do nothing */ | |
3947 | break; | |
3948 | } | |
3949 | kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp); | |
3950 | } | |
3951 | ||
3952 | int | |
3953 | qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode, | |
3954 | uint32_t *data, int cnt) | |
3955 | { | |
3956 | struct qla_work_evt *e; | |
3957 | ||
3958 | e = qla2x00_alloc_work(vha, QLA_EVT_AENFX); | |
3959 | if (!e) | |
3960 | return QLA_FUNCTION_FAILED; | |
3961 | ||
3962 | e->u.aenfx.evtcode = evtcode; | |
3963 | e->u.aenfx.count = cnt; | |
3964 | memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt); | |
3965 | return qla2x00_post_work(vha, e); | |
3966 | } | |
3967 | ||
3968 | void | |
3969 | qla2x00_do_work(struct scsi_qla_host *vha) | |
3970 | { | |
3971 | struct qla_work_evt *e, *tmp; | |
3972 | unsigned long flags; | |
3973 | LIST_HEAD(work); | |
3974 | ||
3975 | spin_lock_irqsave(&vha->work_lock, flags); | |
3976 | list_splice_init(&vha->work_list, &work); | |
3977 | spin_unlock_irqrestore(&vha->work_lock, flags); | |
3978 | ||
3979 | list_for_each_entry_safe(e, tmp, &work, list) { | |
3980 | list_del_init(&e->list); | |
3981 | ||
3982 | switch (e->type) { | |
3983 | case QLA_EVT_AEN: | |
3984 | fc_host_post_event(vha->host, fc_get_event_number(), | |
3985 | e->u.aen.code, e->u.aen.data); | |
3986 | break; | |
3987 | case QLA_EVT_IDC_ACK: | |
3988 | qla81xx_idc_ack(vha, e->u.idc_ack.mb); | |
3989 | break; | |
3990 | case QLA_EVT_ASYNC_LOGIN: | |
3991 | qla2x00_async_login(vha, e->u.logio.fcport, | |
3992 | e->u.logio.data); | |
3993 | break; | |
3994 | case QLA_EVT_ASYNC_LOGIN_DONE: | |
3995 | qla2x00_async_login_done(vha, e->u.logio.fcport, | |
3996 | e->u.logio.data); | |
3997 | break; | |
3998 | case QLA_EVT_ASYNC_LOGOUT: | |
3999 | qla2x00_async_logout(vha, e->u.logio.fcport); | |
4000 | break; | |
4001 | case QLA_EVT_ASYNC_LOGOUT_DONE: | |
4002 | qla2x00_async_logout_done(vha, e->u.logio.fcport, | |
4003 | e->u.logio.data); | |
4004 | break; | |
4005 | case QLA_EVT_ASYNC_ADISC: | |
4006 | qla2x00_async_adisc(vha, e->u.logio.fcport, | |
4007 | e->u.logio.data); | |
4008 | break; | |
4009 | case QLA_EVT_ASYNC_ADISC_DONE: | |
4010 | qla2x00_async_adisc_done(vha, e->u.logio.fcport, | |
4011 | e->u.logio.data); | |
4012 | break; | |
4013 | case QLA_EVT_UEVENT: | |
4014 | qla2x00_uevent_emit(vha, e->u.uevent.code); | |
4015 | break; | |
4016 | case QLA_EVT_AENFX: | |
4017 | qlafx00_process_aen(vha, e); | |
4018 | break; | |
4019 | } | |
4020 | if (e->flags & QLA_EVT_FLAG_FREE) | |
4021 | kfree(e); | |
4022 | ||
4023 | /* For each work completed decrement vha ref count */ | |
4024 | QLA_VHA_MARK_NOT_BUSY(vha); | |
4025 | } | |
4026 | } | |
4027 | ||
4028 | /* Relogins all the fcports of a vport | |
4029 | * Context: dpc thread | |
4030 | */ | |
4031 | void qla2x00_relogin(struct scsi_qla_host *vha) | |
4032 | { | |
4033 | fc_port_t *fcport; | |
4034 | int status; | |
4035 | uint16_t next_loopid = 0; | |
4036 | struct qla_hw_data *ha = vha->hw; | |
4037 | uint16_t data[2]; | |
4038 | ||
4039 | list_for_each_entry(fcport, &vha->vp_fcports, list) { | |
4040 | /* | |
4041 | * If the port is not ONLINE then try to login | |
4042 | * to it if we haven't run out of retries. | |
4043 | */ | |
4044 | if (atomic_read(&fcport->state) != FCS_ONLINE && | |
4045 | fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) { | |
4046 | fcport->login_retry--; | |
4047 | if (fcport->flags & FCF_FABRIC_DEVICE) { | |
4048 | if (fcport->flags & FCF_FCP2_DEVICE) | |
4049 | ha->isp_ops->fabric_logout(vha, | |
4050 | fcport->loop_id, | |
4051 | fcport->d_id.b.domain, | |
4052 | fcport->d_id.b.area, | |
4053 | fcport->d_id.b.al_pa); | |
4054 | ||
4055 | if (fcport->loop_id == FC_NO_LOOP_ID) { | |
4056 | fcport->loop_id = next_loopid = | |
4057 | ha->min_external_loopid; | |
4058 | status = qla2x00_find_new_loop_id( | |
4059 | vha, fcport); | |
4060 | if (status != QLA_SUCCESS) { | |
4061 | /* Ran out of IDs to use */ | |
4062 | break; | |
4063 | } | |
4064 | } | |
4065 | ||
4066 | if (IS_ALOGIO_CAPABLE(ha)) { | |
4067 | fcport->flags |= FCF_ASYNC_SENT; | |
4068 | data[0] = 0; | |
4069 | data[1] = QLA_LOGIO_LOGIN_RETRIED; | |
4070 | status = qla2x00_post_async_login_work( | |
4071 | vha, fcport, data); | |
4072 | if (status == QLA_SUCCESS) | |
4073 | continue; | |
4074 | /* Attempt a retry. */ | |
4075 | status = 1; | |
4076 | } else { | |
4077 | status = qla2x00_fabric_login(vha, | |
4078 | fcport, &next_loopid); | |
4079 | if (status == QLA_SUCCESS) { | |
4080 | int status2; | |
4081 | uint8_t opts; | |
4082 | ||
4083 | opts = 0; | |
4084 | if (fcport->flags & | |
4085 | FCF_FCP2_DEVICE) | |
4086 | opts |= BIT_1; | |
4087 | status2 = | |
4088 | qla2x00_get_port_database( | |
4089 | vha, fcport, opts); | |
4090 | if (status2 != QLA_SUCCESS) | |
4091 | status = 1; | |
4092 | } | |
4093 | } | |
4094 | } else | |
4095 | status = qla2x00_local_device_login(vha, | |
4096 | fcport); | |
4097 | ||
4098 | if (status == QLA_SUCCESS) { | |
4099 | fcport->old_loop_id = fcport->loop_id; | |
4100 | ||
4101 | ql_dbg(ql_dbg_disc, vha, 0x2003, | |
4102 | "Port login OK: logged in ID 0x%x.\n", | |
4103 | fcport->loop_id); | |
4104 | ||
4105 | qla2x00_update_fcport(vha, fcport); | |
4106 | ||
4107 | } else if (status == 1) { | |
4108 | set_bit(RELOGIN_NEEDED, &vha->dpc_flags); | |
4109 | /* retry the login again */ | |
4110 | ql_dbg(ql_dbg_disc, vha, 0x2007, | |
4111 | "Retrying %d login again loop_id 0x%x.\n", | |
4112 | fcport->login_retry, fcport->loop_id); | |
4113 | } else { | |
4114 | fcport->login_retry = 0; | |
4115 | } | |
4116 | ||
4117 | if (fcport->login_retry == 0 && status != QLA_SUCCESS) | |
4118 | qla2x00_clear_loop_id(fcport); | |
4119 | } | |
4120 | if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) | |
4121 | break; | |
4122 | } | |
4123 | } | |
4124 | ||
4125 | /* Schedule work on any of the dpc-workqueues */ | |
4126 | void | |
4127 | qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code) | |
4128 | { | |
4129 | struct qla_hw_data *ha = base_vha->hw; | |
4130 | ||
4131 | switch (work_code) { | |
4132 | case MBA_IDC_AEN: /* 0x8200 */ | |
4133 | if (ha->dpc_lp_wq) | |
4134 | queue_work(ha->dpc_lp_wq, &ha->idc_aen); | |
4135 | break; | |
4136 | ||
4137 | case QLA83XX_NIC_CORE_RESET: /* 0x1 */ | |
4138 | if (!ha->flags.nic_core_reset_hdlr_active) { | |
4139 | if (ha->dpc_hp_wq) | |
4140 | queue_work(ha->dpc_hp_wq, &ha->nic_core_reset); | |
4141 | } else | |
4142 | ql_dbg(ql_dbg_p3p, base_vha, 0xb05e, | |
4143 | "NIC Core reset is already active. Skip " | |
4144 | "scheduling it again.\n"); | |
4145 | break; | |
4146 | case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */ | |
4147 | if (ha->dpc_hp_wq) | |
4148 | queue_work(ha->dpc_hp_wq, &ha->idc_state_handler); | |
4149 | break; | |
4150 | case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */ | |
4151 | if (ha->dpc_hp_wq) | |
4152 | queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable); | |
4153 | break; | |
4154 | default: | |
4155 | ql_log(ql_log_warn, base_vha, 0xb05f, | |
4156 | "Unknow work-code=0x%x.\n", work_code); | |
4157 | } | |
4158 | ||
4159 | return; | |
4160 | } | |
4161 | ||
4162 | /* Work: Perform NIC Core Unrecoverable state handling */ | |
4163 | void | |
4164 | qla83xx_nic_core_unrecoverable_work(struct work_struct *work) | |
4165 | { | |
4166 | struct qla_hw_data *ha = | |
4167 | container_of(work, struct qla_hw_data, nic_core_unrecoverable); | |
4168 | scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); | |
4169 | uint32_t dev_state = 0; | |
4170 | ||
4171 | qla83xx_idc_lock(base_vha, 0); | |
4172 | qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); | |
4173 | qla83xx_reset_ownership(base_vha); | |
4174 | if (ha->flags.nic_core_reset_owner) { | |
4175 | ha->flags.nic_core_reset_owner = 0; | |
4176 | qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, | |
4177 | QLA8XXX_DEV_FAILED); | |
4178 | ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n"); | |
4179 | qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); | |
4180 | } | |
4181 | qla83xx_idc_unlock(base_vha, 0); | |
4182 | } | |
4183 | ||
4184 | /* Work: Execute IDC state handler */ | |
4185 | void | |
4186 | qla83xx_idc_state_handler_work(struct work_struct *work) | |
4187 | { | |
4188 | struct qla_hw_data *ha = | |
4189 | container_of(work, struct qla_hw_data, idc_state_handler); | |
4190 | scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); | |
4191 | uint32_t dev_state = 0; | |
4192 | ||
4193 | qla83xx_idc_lock(base_vha, 0); | |
4194 | qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); | |
4195 | if (dev_state == QLA8XXX_DEV_FAILED || | |
4196 | dev_state == QLA8XXX_DEV_NEED_QUIESCENT) | |
4197 | qla83xx_idc_state_handler(base_vha); | |
4198 | qla83xx_idc_unlock(base_vha, 0); | |
4199 | } | |
4200 | ||
4201 | static int | |
4202 | qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha) | |
4203 | { | |
4204 | int rval = QLA_SUCCESS; | |
4205 | unsigned long heart_beat_wait = jiffies + (1 * HZ); | |
4206 | uint32_t heart_beat_counter1, heart_beat_counter2; | |
4207 | ||
4208 | do { | |
4209 | if (time_after(jiffies, heart_beat_wait)) { | |
4210 | ql_dbg(ql_dbg_p3p, base_vha, 0xb07c, | |
4211 | "Nic Core f/w is not alive.\n"); | |
4212 | rval = QLA_FUNCTION_FAILED; | |
4213 | break; | |
4214 | } | |
4215 | ||
4216 | qla83xx_idc_lock(base_vha, 0); | |
4217 | qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, | |
4218 | &heart_beat_counter1); | |
4219 | qla83xx_idc_unlock(base_vha, 0); | |
4220 | msleep(100); | |
4221 | qla83xx_idc_lock(base_vha, 0); | |
4222 | qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, | |
4223 | &heart_beat_counter2); | |
4224 | qla83xx_idc_unlock(base_vha, 0); | |
4225 | } while (heart_beat_counter1 == heart_beat_counter2); | |
4226 | ||
4227 | return rval; | |
4228 | } | |
4229 | ||
4230 | /* Work: Perform NIC Core Reset handling */ | |
4231 | void | |
4232 | qla83xx_nic_core_reset_work(struct work_struct *work) | |
4233 | { | |
4234 | struct qla_hw_data *ha = | |
4235 | container_of(work, struct qla_hw_data, nic_core_reset); | |
4236 | scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); | |
4237 | uint32_t dev_state = 0; | |
4238 | ||
4239 | if (IS_QLA2031(ha)) { | |
4240 | if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS) | |
4241 | ql_log(ql_log_warn, base_vha, 0xb081, | |
4242 | "Failed to dump mctp\n"); | |
4243 | return; | |
4244 | } | |
4245 | ||
4246 | if (!ha->flags.nic_core_reset_hdlr_active) { | |
4247 | if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) { | |
4248 | qla83xx_idc_lock(base_vha, 0); | |
4249 | qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, | |
4250 | &dev_state); | |
4251 | qla83xx_idc_unlock(base_vha, 0); | |
4252 | if (dev_state != QLA8XXX_DEV_NEED_RESET) { | |
4253 | ql_dbg(ql_dbg_p3p, base_vha, 0xb07a, | |
4254 | "Nic Core f/w is alive.\n"); | |
4255 | return; | |
4256 | } | |
4257 | } | |
4258 | ||
4259 | ha->flags.nic_core_reset_hdlr_active = 1; | |
4260 | if (qla83xx_nic_core_reset(base_vha)) { | |
4261 | /* NIC Core reset failed. */ | |
4262 | ql_dbg(ql_dbg_p3p, base_vha, 0xb061, | |
4263 | "NIC Core reset failed.\n"); | |
4264 | } | |
4265 | ha->flags.nic_core_reset_hdlr_active = 0; | |
4266 | } | |
4267 | } | |
4268 | ||
4269 | /* Work: Handle 8200 IDC aens */ | |
4270 | void | |
4271 | qla83xx_service_idc_aen(struct work_struct *work) | |
4272 | { | |
4273 | struct qla_hw_data *ha = | |
4274 | container_of(work, struct qla_hw_data, idc_aen); | |
4275 | scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); | |
4276 | uint32_t dev_state, idc_control; | |
4277 | ||
4278 | qla83xx_idc_lock(base_vha, 0); | |
4279 | qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); | |
4280 | qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control); | |
4281 | qla83xx_idc_unlock(base_vha, 0); | |
4282 | if (dev_state == QLA8XXX_DEV_NEED_RESET) { | |
4283 | if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) { | |
4284 | ql_dbg(ql_dbg_p3p, base_vha, 0xb062, | |
4285 | "Application requested NIC Core Reset.\n"); | |
4286 | qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); | |
4287 | } else if (qla83xx_check_nic_core_fw_alive(base_vha) == | |
4288 | QLA_SUCCESS) { | |
4289 | ql_dbg(ql_dbg_p3p, base_vha, 0xb07b, | |
4290 | "Other protocol driver requested NIC Core Reset.\n"); | |
4291 | qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); | |
4292 | } | |
4293 | } else if (dev_state == QLA8XXX_DEV_FAILED || | |
4294 | dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { | |
4295 | qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); | |
4296 | } | |
4297 | } | |
4298 | ||
4299 | static void | |
4300 | qla83xx_wait_logic(void) | |
4301 | { | |
4302 | int i; | |
4303 | ||
4304 | /* Yield CPU */ | |
4305 | if (!in_interrupt()) { | |
4306 | /* | |
4307 | * Wait about 200ms before retrying again. | |
4308 | * This controls the number of retries for single | |
4309 | * lock operation. | |
4310 | */ | |
4311 | msleep(100); | |
4312 | schedule(); | |
4313 | } else { | |
4314 | for (i = 0; i < 20; i++) | |
4315 | cpu_relax(); /* This a nop instr on i386 */ | |
4316 | } | |
4317 | } | |
4318 | ||
4319 | static int | |
4320 | qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha) | |
4321 | { | |
4322 | int rval; | |
4323 | uint32_t data; | |
4324 | uint32_t idc_lck_rcvry_stage_mask = 0x3; | |
4325 | uint32_t idc_lck_rcvry_owner_mask = 0x3c; | |
4326 | struct qla_hw_data *ha = base_vha->hw; | |
4327 | ql_dbg(ql_dbg_p3p, base_vha, 0xb086, | |
4328 | "Trying force recovery of the IDC lock.\n"); | |
4329 | ||
4330 | rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data); | |
4331 | if (rval) | |
4332 | return rval; | |
4333 | ||
4334 | if ((data & idc_lck_rcvry_stage_mask) > 0) { | |
4335 | return QLA_SUCCESS; | |
4336 | } else { | |
4337 | data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2); | |
4338 | rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, | |
4339 | data); | |
4340 | if (rval) | |
4341 | return rval; | |
4342 | ||
4343 | msleep(200); | |
4344 | ||
4345 | rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, | |
4346 | &data); | |
4347 | if (rval) | |
4348 | return rval; | |
4349 | ||
4350 | if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) { | |
4351 | data &= (IDC_LOCK_RECOVERY_STAGE2 | | |
4352 | ~(idc_lck_rcvry_stage_mask)); | |
4353 | rval = qla83xx_wr_reg(base_vha, | |
4354 | QLA83XX_IDC_LOCK_RECOVERY, data); | |
4355 | if (rval) | |
4356 | return rval; | |
4357 | ||
4358 | /* Forcefully perform IDC UnLock */ | |
4359 | rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, | |
4360 | &data); | |
4361 | if (rval) | |
4362 | return rval; | |
4363 | /* Clear lock-id by setting 0xff */ | |
4364 | rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, | |
4365 | 0xff); | |
4366 | if (rval) | |
4367 | return rval; | |
4368 | /* Clear lock-recovery by setting 0x0 */ | |
4369 | rval = qla83xx_wr_reg(base_vha, | |
4370 | QLA83XX_IDC_LOCK_RECOVERY, 0x0); | |
4371 | if (rval) | |
4372 | return rval; | |
4373 | } else | |
4374 | return QLA_SUCCESS; | |
4375 | } | |
4376 | ||
4377 | return rval; | |
4378 | } | |
4379 | ||
4380 | static int | |
4381 | qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha) | |
4382 | { | |
4383 | int rval = QLA_SUCCESS; | |
4384 | uint32_t o_drv_lockid, n_drv_lockid; | |
4385 | unsigned long lock_recovery_timeout; | |
4386 | ||
4387 | lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT; | |
4388 | retry_lockid: | |
4389 | rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid); | |
4390 | if (rval) | |
4391 | goto exit; | |
4392 | ||
4393 | /* MAX wait time before forcing IDC Lock recovery = 2 secs */ | |
4394 | if (time_after_eq(jiffies, lock_recovery_timeout)) { | |
4395 | if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS) | |
4396 | return QLA_SUCCESS; | |
4397 | else | |
4398 | return QLA_FUNCTION_FAILED; | |
4399 | } | |
4400 | ||
4401 | rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid); | |
4402 | if (rval) | |
4403 | goto exit; | |
4404 | ||
4405 | if (o_drv_lockid == n_drv_lockid) { | |
4406 | qla83xx_wait_logic(); | |
4407 | goto retry_lockid; | |
4408 | } else | |
4409 | return QLA_SUCCESS; | |
4410 | ||
4411 | exit: | |
4412 | return rval; | |
4413 | } | |
4414 | ||
4415 | void | |
4416 | qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id) | |
4417 | { | |
4418 | uint16_t options = (requester_id << 15) | BIT_6; | |
4419 | uint32_t data; | |
4420 | uint32_t lock_owner; | |
4421 | struct qla_hw_data *ha = base_vha->hw; | |
4422 | ||
4423 | /* IDC-lock implementation using driver-lock/lock-id remote registers */ | |
4424 | retry_lock: | |
4425 | if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data) | |
4426 | == QLA_SUCCESS) { | |
4427 | if (data) { | |
4428 | /* Setting lock-id to our function-number */ | |
4429 | qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, | |
4430 | ha->portnum); | |
4431 | } else { | |
4432 | qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, | |
4433 | &lock_owner); | |
4434 | ql_dbg(ql_dbg_p3p, base_vha, 0xb063, | |
4435 | "Failed to acquire IDC lock, acquired by %d, " | |
4436 | "retrying...\n", lock_owner); | |
4437 | ||
4438 | /* Retry/Perform IDC-Lock recovery */ | |
4439 | if (qla83xx_idc_lock_recovery(base_vha) | |
4440 | == QLA_SUCCESS) { | |
4441 | qla83xx_wait_logic(); | |
4442 | goto retry_lock; | |
4443 | } else | |
4444 | ql_log(ql_log_warn, base_vha, 0xb075, | |
4445 | "IDC Lock recovery FAILED.\n"); | |
4446 | } | |
4447 | ||
4448 | } | |
4449 | ||
4450 | return; | |
4451 | ||
4452 | /* XXX: IDC-lock implementation using access-control mbx */ | |
4453 | retry_lock2: | |
4454 | if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { | |
4455 | ql_dbg(ql_dbg_p3p, base_vha, 0xb072, | |
4456 | "Failed to acquire IDC lock. retrying...\n"); | |
4457 | /* Retry/Perform IDC-Lock recovery */ | |
4458 | if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) { | |
4459 | qla83xx_wait_logic(); | |
4460 | goto retry_lock2; | |
4461 | } else | |
4462 | ql_log(ql_log_warn, base_vha, 0xb076, | |
4463 | "IDC Lock recovery FAILED.\n"); | |
4464 | } | |
4465 | ||
4466 | return; | |
4467 | } | |
4468 | ||
4469 | void | |
4470 | qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id) | |
4471 | { | |
4472 | uint16_t options = (requester_id << 15) | BIT_7, retry; | |
4473 | uint32_t data; | |
4474 | struct qla_hw_data *ha = base_vha->hw; | |
4475 | ||
4476 | /* IDC-unlock implementation using driver-unlock/lock-id | |
4477 | * remote registers | |
4478 | */ | |
4479 | retry = 0; | |
4480 | retry_unlock: | |
4481 | if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data) | |
4482 | == QLA_SUCCESS) { | |
4483 | if (data == ha->portnum) { | |
4484 | qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data); | |
4485 | /* Clearing lock-id by setting 0xff */ | |
4486 | qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff); | |
4487 | } else if (retry < 10) { | |
4488 | /* SV: XXX: IDC unlock retrying needed here? */ | |
4489 | ||
4490 | /* Retry for IDC-unlock */ | |
4491 | qla83xx_wait_logic(); | |
4492 | retry++; | |
4493 | ql_dbg(ql_dbg_p3p, base_vha, 0xb064, | |
4494 | "Failed to release IDC lock, retyring=%d\n", retry); | |
4495 | goto retry_unlock; | |
4496 | } | |
4497 | } else if (retry < 10) { | |
4498 | /* Retry for IDC-unlock */ | |
4499 | qla83xx_wait_logic(); | |
4500 | retry++; | |
4501 | ql_dbg(ql_dbg_p3p, base_vha, 0xb065, | |
4502 | "Failed to read drv-lockid, retyring=%d\n", retry); | |
4503 | goto retry_unlock; | |
4504 | } | |
4505 | ||
4506 | return; | |
4507 | ||
4508 | /* XXX: IDC-unlock implementation using access-control mbx */ | |
4509 | retry = 0; | |
4510 | retry_unlock2: | |
4511 | if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { | |
4512 | if (retry < 10) { | |
4513 | /* Retry for IDC-unlock */ | |
4514 | qla83xx_wait_logic(); | |
4515 | retry++; | |
4516 | ql_dbg(ql_dbg_p3p, base_vha, 0xb066, | |
4517 | "Failed to release IDC lock, retyring=%d\n", retry); | |
4518 | goto retry_unlock2; | |
4519 | } | |
4520 | } | |
4521 | ||
4522 | return; | |
4523 | } | |
4524 | ||
4525 | int | |
4526 | __qla83xx_set_drv_presence(scsi_qla_host_t *vha) | |
4527 | { | |
4528 | int rval = QLA_SUCCESS; | |
4529 | struct qla_hw_data *ha = vha->hw; | |
4530 | uint32_t drv_presence; | |
4531 | ||
4532 | rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); | |
4533 | if (rval == QLA_SUCCESS) { | |
4534 | drv_presence |= (1 << ha->portnum); | |
4535 | rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, | |
4536 | drv_presence); | |
4537 | } | |
4538 | ||
4539 | return rval; | |
4540 | } | |
4541 | ||
4542 | int | |
4543 | qla83xx_set_drv_presence(scsi_qla_host_t *vha) | |
4544 | { | |
4545 | int rval = QLA_SUCCESS; | |
4546 | ||
4547 | qla83xx_idc_lock(vha, 0); | |
4548 | rval = __qla83xx_set_drv_presence(vha); | |
4549 | qla83xx_idc_unlock(vha, 0); | |
4550 | ||
4551 | return rval; | |
4552 | } | |
4553 | ||
4554 | int | |
4555 | __qla83xx_clear_drv_presence(scsi_qla_host_t *vha) | |
4556 | { | |
4557 | int rval = QLA_SUCCESS; | |
4558 | struct qla_hw_data *ha = vha->hw; | |
4559 | uint32_t drv_presence; | |
4560 | ||
4561 | rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); | |
4562 | if (rval == QLA_SUCCESS) { | |
4563 | drv_presence &= ~(1 << ha->portnum); | |
4564 | rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, | |
4565 | drv_presence); | |
4566 | } | |
4567 | ||
4568 | return rval; | |
4569 | } | |
4570 | ||
4571 | int | |
4572 | qla83xx_clear_drv_presence(scsi_qla_host_t *vha) | |
4573 | { | |
4574 | int rval = QLA_SUCCESS; | |
4575 | ||
4576 | qla83xx_idc_lock(vha, 0); | |
4577 | rval = __qla83xx_clear_drv_presence(vha); | |
4578 | qla83xx_idc_unlock(vha, 0); | |
4579 | ||
4580 | return rval; | |
4581 | } | |
4582 | ||
4583 | static void | |
4584 | qla83xx_need_reset_handler(scsi_qla_host_t *vha) | |
4585 | { | |
4586 | struct qla_hw_data *ha = vha->hw; | |
4587 | uint32_t drv_ack, drv_presence; | |
4588 | unsigned long ack_timeout; | |
4589 | ||
4590 | /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */ | |
4591 | ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); | |
4592 | while (1) { | |
4593 | qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); | |
4594 | qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); | |
4595 | if ((drv_ack & drv_presence) == drv_presence) | |
4596 | break; | |
4597 | ||
4598 | if (time_after_eq(jiffies, ack_timeout)) { | |
4599 | ql_log(ql_log_warn, vha, 0xb067, | |
4600 | "RESET ACK TIMEOUT! drv_presence=0x%x " | |
4601 | "drv_ack=0x%x\n", drv_presence, drv_ack); | |
4602 | /* | |
4603 | * The function(s) which did not ack in time are forced | |
4604 | * to withdraw any further participation in the IDC | |
4605 | * reset. | |
4606 | */ | |
4607 | if (drv_ack != drv_presence) | |
4608 | qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, | |
4609 | drv_ack); | |
4610 | break; | |
4611 | } | |
4612 | ||
4613 | qla83xx_idc_unlock(vha, 0); | |
4614 | msleep(1000); | |
4615 | qla83xx_idc_lock(vha, 0); | |
4616 | } | |
4617 | ||
4618 | qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD); | |
4619 | ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n"); | |
4620 | } | |
4621 | ||
4622 | static int | |
4623 | qla83xx_device_bootstrap(scsi_qla_host_t *vha) | |
4624 | { | |
4625 | int rval = QLA_SUCCESS; | |
4626 | uint32_t idc_control; | |
4627 | ||
4628 | qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING); | |
4629 | ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n"); | |
4630 | ||
4631 | /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */ | |
4632 | __qla83xx_get_idc_control(vha, &idc_control); | |
4633 | idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET; | |
4634 | __qla83xx_set_idc_control(vha, 0); | |
4635 | ||
4636 | qla83xx_idc_unlock(vha, 0); | |
4637 | rval = qla83xx_restart_nic_firmware(vha); | |
4638 | qla83xx_idc_lock(vha, 0); | |
4639 | ||
4640 | if (rval != QLA_SUCCESS) { | |
4641 | ql_log(ql_log_fatal, vha, 0xb06a, | |
4642 | "Failed to restart NIC f/w.\n"); | |
4643 | qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED); | |
4644 | ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n"); | |
4645 | } else { | |
4646 | ql_dbg(ql_dbg_p3p, vha, 0xb06c, | |
4647 | "Success in restarting nic f/w.\n"); | |
4648 | qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY); | |
4649 | ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n"); | |
4650 | } | |
4651 | ||
4652 | return rval; | |
4653 | } | |
4654 | ||
4655 | /* Assumes idc_lock always held on entry */ | |
4656 | int | |
4657 | qla83xx_idc_state_handler(scsi_qla_host_t *base_vha) | |
4658 | { | |
4659 | struct qla_hw_data *ha = base_vha->hw; | |
4660 | int rval = QLA_SUCCESS; | |
4661 | unsigned long dev_init_timeout; | |
4662 | uint32_t dev_state; | |
4663 | ||
4664 | /* Wait for MAX-INIT-TIMEOUT for the device to go ready */ | |
4665 | dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); | |
4666 | ||
4667 | while (1) { | |
4668 | ||
4669 | if (time_after_eq(jiffies, dev_init_timeout)) { | |
4670 | ql_log(ql_log_warn, base_vha, 0xb06e, | |
4671 | "Initialization TIMEOUT!\n"); | |
4672 | /* Init timeout. Disable further NIC Core | |
4673 | * communication. | |
4674 | */ | |
4675 | qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, | |
4676 | QLA8XXX_DEV_FAILED); | |
4677 | ql_log(ql_log_info, base_vha, 0xb06f, | |
4678 | "HW State: FAILED.\n"); | |
4679 | } | |
4680 | ||
4681 | qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); | |
4682 | switch (dev_state) { | |
4683 | case QLA8XXX_DEV_READY: | |
4684 | if (ha->flags.nic_core_reset_owner) | |
4685 | qla83xx_idc_audit(base_vha, | |
4686 | IDC_AUDIT_COMPLETION); | |
4687 | ha->flags.nic_core_reset_owner = 0; | |
4688 | ql_dbg(ql_dbg_p3p, base_vha, 0xb070, | |
4689 | "Reset_owner reset by 0x%x.\n", | |
4690 | ha->portnum); | |
4691 | goto exit; | |
4692 | case QLA8XXX_DEV_COLD: | |
4693 | if (ha->flags.nic_core_reset_owner) | |
4694 | rval = qla83xx_device_bootstrap(base_vha); | |
4695 | else { | |
4696 | /* Wait for AEN to change device-state */ | |
4697 | qla83xx_idc_unlock(base_vha, 0); | |
4698 | msleep(1000); | |
4699 | qla83xx_idc_lock(base_vha, 0); | |
4700 | } | |
4701 | break; | |
4702 | case QLA8XXX_DEV_INITIALIZING: | |
4703 | /* Wait for AEN to change device-state */ | |
4704 | qla83xx_idc_unlock(base_vha, 0); | |
4705 | msleep(1000); | |
4706 | qla83xx_idc_lock(base_vha, 0); | |
4707 | break; | |
4708 | case QLA8XXX_DEV_NEED_RESET: | |
4709 | if (!ql2xdontresethba && ha->flags.nic_core_reset_owner) | |
4710 | qla83xx_need_reset_handler(base_vha); | |
4711 | else { | |
4712 | /* Wait for AEN to change device-state */ | |
4713 | qla83xx_idc_unlock(base_vha, 0); | |
4714 | msleep(1000); | |
4715 | qla83xx_idc_lock(base_vha, 0); | |
4716 | } | |
4717 | /* reset timeout value after need reset handler */ | |
4718 | dev_init_timeout = jiffies + | |
4719 | (ha->fcoe_dev_init_timeout * HZ); | |
4720 | break; | |
4721 | case QLA8XXX_DEV_NEED_QUIESCENT: | |
4722 | /* XXX: DEBUG for now */ | |
4723 | qla83xx_idc_unlock(base_vha, 0); | |
4724 | msleep(1000); | |
4725 | qla83xx_idc_lock(base_vha, 0); | |
4726 | break; | |
4727 | case QLA8XXX_DEV_QUIESCENT: | |
4728 | /* XXX: DEBUG for now */ | |
4729 | if (ha->flags.quiesce_owner) | |
4730 | goto exit; | |
4731 | ||
4732 | qla83xx_idc_unlock(base_vha, 0); | |
4733 | msleep(1000); | |
4734 | qla83xx_idc_lock(base_vha, 0); | |
4735 | dev_init_timeout = jiffies + | |
4736 | (ha->fcoe_dev_init_timeout * HZ); | |
4737 | break; | |
4738 | case QLA8XXX_DEV_FAILED: | |
4739 | if (ha->flags.nic_core_reset_owner) | |
4740 | qla83xx_idc_audit(base_vha, | |
4741 | IDC_AUDIT_COMPLETION); | |
4742 | ha->flags.nic_core_reset_owner = 0; | |
4743 | __qla83xx_clear_drv_presence(base_vha); | |
4744 | qla83xx_idc_unlock(base_vha, 0); | |
4745 | qla8xxx_dev_failed_handler(base_vha); | |
4746 | rval = QLA_FUNCTION_FAILED; | |
4747 | qla83xx_idc_lock(base_vha, 0); | |
4748 | goto exit; | |
4749 | case QLA8XXX_BAD_VALUE: | |
4750 | qla83xx_idc_unlock(base_vha, 0); | |
4751 | msleep(1000); | |
4752 | qla83xx_idc_lock(base_vha, 0); | |
4753 | break; | |
4754 | default: | |
4755 | ql_log(ql_log_warn, base_vha, 0xb071, | |
4756 | "Unknow Device State: %x.\n", dev_state); | |
4757 | qla83xx_idc_unlock(base_vha, 0); | |
4758 | qla8xxx_dev_failed_handler(base_vha); | |
4759 | rval = QLA_FUNCTION_FAILED; | |
4760 | qla83xx_idc_lock(base_vha, 0); | |
4761 | goto exit; | |
4762 | } | |
4763 | } | |
4764 | ||
4765 | exit: | |
4766 | return rval; | |
4767 | } | |
4768 | ||
4769 | void | |
4770 | qla2x00_disable_board_on_pci_error(struct work_struct *work) | |
4771 | { | |
4772 | struct qla_hw_data *ha = container_of(work, struct qla_hw_data, | |
4773 | board_disable); | |
4774 | struct pci_dev *pdev = ha->pdev; | |
4775 | scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); | |
4776 | ||
4777 | ql_log(ql_log_warn, base_vha, 0x015b, | |
4778 | "Disabling adapter.\n"); | |
4779 | ||
4780 | set_bit(UNLOADING, &base_vha->dpc_flags); | |
4781 | ||
4782 | qla2x00_delete_all_vps(ha, base_vha); | |
4783 | ||
4784 | qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); | |
4785 | ||
4786 | qla2x00_dfs_remove(base_vha); | |
4787 | ||
4788 | qla84xx_put_chip(base_vha); | |
4789 | ||
4790 | if (base_vha->timer_active) | |
4791 | qla2x00_stop_timer(base_vha); | |
4792 | ||
4793 | base_vha->flags.online = 0; | |
4794 | ||
4795 | qla2x00_destroy_deferred_work(ha); | |
4796 | ||
4797 | /* | |
4798 | * Do not try to stop beacon blink as it will issue a mailbox | |
4799 | * command. | |
4800 | */ | |
4801 | qla2x00_free_sysfs_attr(base_vha, false); | |
4802 | ||
4803 | fc_remove_host(base_vha->host); | |
4804 | ||
4805 | scsi_remove_host(base_vha->host); | |
4806 | ||
4807 | base_vha->flags.init_done = 0; | |
4808 | qla25xx_delete_queues(base_vha); | |
4809 | qla2x00_free_irqs(base_vha); | |
4810 | qla2x00_free_fcports(base_vha); | |
4811 | qla2x00_mem_free(ha); | |
4812 | qla82xx_md_free(base_vha); | |
4813 | qla2x00_free_queues(ha); | |
4814 | ||
4815 | qla2x00_unmap_iobases(ha); | |
4816 | ||
4817 | pci_release_selected_regions(ha->pdev, ha->bars); | |
4818 | pci_disable_pcie_error_reporting(pdev); | |
4819 | pci_disable_device(pdev); | |
4820 | ||
4821 | /* | |
4822 | * Let qla2x00_remove_one cleanup qla_hw_data on device removal. | |
4823 | */ | |
4824 | } | |
4825 | ||
4826 | /************************************************************************** | |
4827 | * qla2x00_do_dpc | |
4828 | * This kernel thread is a task that is schedule by the interrupt handler | |
4829 | * to perform the background processing for interrupts. | |
4830 | * | |
4831 | * Notes: | |
4832 | * This task always run in the context of a kernel thread. It | |
4833 | * is kick-off by the driver's detect code and starts up | |
4834 | * up one per adapter. It immediately goes to sleep and waits for | |
4835 | * some fibre event. When either the interrupt handler or | |
4836 | * the timer routine detects a event it will one of the task | |
4837 | * bits then wake us up. | |
4838 | **************************************************************************/ | |
4839 | static int | |
4840 | qla2x00_do_dpc(void *data) | |
4841 | { | |
4842 | int rval; | |
4843 | scsi_qla_host_t *base_vha; | |
4844 | struct qla_hw_data *ha; | |
4845 | ||
4846 | ha = (struct qla_hw_data *)data; | |
4847 | base_vha = pci_get_drvdata(ha->pdev); | |
4848 | ||
4849 | set_user_nice(current, MIN_NICE); | |
4850 | ||
4851 | set_current_state(TASK_INTERRUPTIBLE); | |
4852 | while (!kthread_should_stop()) { | |
4853 | ql_dbg(ql_dbg_dpc, base_vha, 0x4000, | |
4854 | "DPC handler sleeping.\n"); | |
4855 | ||
4856 | schedule(); | |
4857 | ||
4858 | if (!base_vha->flags.init_done || ha->flags.mbox_busy) | |
4859 | goto end_loop; | |
4860 | ||
4861 | if (ha->flags.eeh_busy) { | |
4862 | ql_dbg(ql_dbg_dpc, base_vha, 0x4003, | |
4863 | "eeh_busy=%d.\n", ha->flags.eeh_busy); | |
4864 | goto end_loop; | |
4865 | } | |
4866 | ||
4867 | ha->dpc_active = 1; | |
4868 | ||
4869 | ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001, | |
4870 | "DPC handler waking up, dpc_flags=0x%lx.\n", | |
4871 | base_vha->dpc_flags); | |
4872 | ||
4873 | qla2x00_do_work(base_vha); | |
4874 | ||
4875 | if (IS_P3P_TYPE(ha)) { | |
4876 | if (IS_QLA8044(ha)) { | |
4877 | if (test_and_clear_bit(ISP_UNRECOVERABLE, | |
4878 | &base_vha->dpc_flags)) { | |
4879 | qla8044_idc_lock(ha); | |
4880 | qla8044_wr_direct(base_vha, | |
4881 | QLA8044_CRB_DEV_STATE_INDEX, | |
4882 | QLA8XXX_DEV_FAILED); | |
4883 | qla8044_idc_unlock(ha); | |
4884 | ql_log(ql_log_info, base_vha, 0x4004, | |
4885 | "HW State: FAILED.\n"); | |
4886 | qla8044_device_state_handler(base_vha); | |
4887 | continue; | |
4888 | } | |
4889 | ||
4890 | } else { | |
4891 | if (test_and_clear_bit(ISP_UNRECOVERABLE, | |
4892 | &base_vha->dpc_flags)) { | |
4893 | qla82xx_idc_lock(ha); | |
4894 | qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, | |
4895 | QLA8XXX_DEV_FAILED); | |
4896 | qla82xx_idc_unlock(ha); | |
4897 | ql_log(ql_log_info, base_vha, 0x0151, | |
4898 | "HW State: FAILED.\n"); | |
4899 | qla82xx_device_state_handler(base_vha); | |
4900 | continue; | |
4901 | } | |
4902 | } | |
4903 | ||
4904 | if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED, | |
4905 | &base_vha->dpc_flags)) { | |
4906 | ||
4907 | ql_dbg(ql_dbg_dpc, base_vha, 0x4005, | |
4908 | "FCoE context reset scheduled.\n"); | |
4909 | if (!(test_and_set_bit(ABORT_ISP_ACTIVE, | |
4910 | &base_vha->dpc_flags))) { | |
4911 | if (qla82xx_fcoe_ctx_reset(base_vha)) { | |
4912 | /* FCoE-ctx reset failed. | |
4913 | * Escalate to chip-reset | |
4914 | */ | |
4915 | set_bit(ISP_ABORT_NEEDED, | |
4916 | &base_vha->dpc_flags); | |
4917 | } | |
4918 | clear_bit(ABORT_ISP_ACTIVE, | |
4919 | &base_vha->dpc_flags); | |
4920 | } | |
4921 | ||
4922 | ql_dbg(ql_dbg_dpc, base_vha, 0x4006, | |
4923 | "FCoE context reset end.\n"); | |
4924 | } | |
4925 | } else if (IS_QLAFX00(ha)) { | |
4926 | if (test_and_clear_bit(ISP_UNRECOVERABLE, | |
4927 | &base_vha->dpc_flags)) { | |
4928 | ql_dbg(ql_dbg_dpc, base_vha, 0x4020, | |
4929 | "Firmware Reset Recovery\n"); | |
4930 | if (qlafx00_reset_initialize(base_vha)) { | |
4931 | /* Failed. Abort isp later. */ | |
4932 | if (!test_bit(UNLOADING, | |
4933 | &base_vha->dpc_flags)) { | |
4934 | set_bit(ISP_UNRECOVERABLE, | |
4935 | &base_vha->dpc_flags); | |
4936 | ql_dbg(ql_dbg_dpc, base_vha, | |
4937 | 0x4021, | |
4938 | "Reset Recovery Failed\n"); | |
4939 | } | |
4940 | } | |
4941 | } | |
4942 | ||
4943 | if (test_and_clear_bit(FX00_TARGET_SCAN, | |
4944 | &base_vha->dpc_flags)) { | |
4945 | ql_dbg(ql_dbg_dpc, base_vha, 0x4022, | |
4946 | "ISPFx00 Target Scan scheduled\n"); | |
4947 | if (qlafx00_rescan_isp(base_vha)) { | |
4948 | if (!test_bit(UNLOADING, | |
4949 | &base_vha->dpc_flags)) | |
4950 | set_bit(ISP_UNRECOVERABLE, | |
4951 | &base_vha->dpc_flags); | |
4952 | ql_dbg(ql_dbg_dpc, base_vha, 0x401e, | |
4953 | "ISPFx00 Target Scan Failed\n"); | |
4954 | } | |
4955 | ql_dbg(ql_dbg_dpc, base_vha, 0x401f, | |
4956 | "ISPFx00 Target Scan End\n"); | |
4957 | } | |
4958 | if (test_and_clear_bit(FX00_HOST_INFO_RESEND, | |
4959 | &base_vha->dpc_flags)) { | |
4960 | ql_dbg(ql_dbg_dpc, base_vha, 0x4023, | |
4961 | "ISPFx00 Host Info resend scheduled\n"); | |
4962 | qlafx00_fx_disc(base_vha, | |
4963 | &base_vha->hw->mr.fcport, | |
4964 | FXDISC_REG_HOST_INFO); | |
4965 | } | |
4966 | } | |
4967 | ||
4968 | if (test_and_clear_bit(ISP_ABORT_NEEDED, | |
4969 | &base_vha->dpc_flags)) { | |
4970 | ||
4971 | ql_dbg(ql_dbg_dpc, base_vha, 0x4007, | |
4972 | "ISP abort scheduled.\n"); | |
4973 | if (!(test_and_set_bit(ABORT_ISP_ACTIVE, | |
4974 | &base_vha->dpc_flags))) { | |
4975 | ||
4976 | if (ha->isp_ops->abort_isp(base_vha)) { | |
4977 | /* failed. retry later */ | |
4978 | set_bit(ISP_ABORT_NEEDED, | |
4979 | &base_vha->dpc_flags); | |
4980 | } | |
4981 | clear_bit(ABORT_ISP_ACTIVE, | |
4982 | &base_vha->dpc_flags); | |
4983 | } | |
4984 | ||
4985 | ql_dbg(ql_dbg_dpc, base_vha, 0x4008, | |
4986 | "ISP abort end.\n"); | |
4987 | } | |
4988 | ||
4989 | if (test_and_clear_bit(FCPORT_UPDATE_NEEDED, | |
4990 | &base_vha->dpc_flags)) { | |
4991 | qla2x00_update_fcports(base_vha); | |
4992 | } | |
4993 | ||
4994 | if (test_bit(SCR_PENDING, &base_vha->dpc_flags)) { | |
4995 | int ret; | |
4996 | ret = qla2x00_send_change_request(base_vha, 0x3, 0); | |
4997 | if (ret != QLA_SUCCESS) | |
4998 | ql_log(ql_log_warn, base_vha, 0x121, | |
4999 | "Failed to enable receiving of RSCN " | |
5000 | "requests: 0x%x.\n", ret); | |
5001 | clear_bit(SCR_PENDING, &base_vha->dpc_flags); | |
5002 | } | |
5003 | ||
5004 | if (IS_QLAFX00(ha)) | |
5005 | goto loop_resync_check; | |
5006 | ||
5007 | if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) { | |
5008 | ql_dbg(ql_dbg_dpc, base_vha, 0x4009, | |
5009 | "Quiescence mode scheduled.\n"); | |
5010 | if (IS_P3P_TYPE(ha)) { | |
5011 | if (IS_QLA82XX(ha)) | |
5012 | qla82xx_device_state_handler(base_vha); | |
5013 | if (IS_QLA8044(ha)) | |
5014 | qla8044_device_state_handler(base_vha); | |
5015 | clear_bit(ISP_QUIESCE_NEEDED, | |
5016 | &base_vha->dpc_flags); | |
5017 | if (!ha->flags.quiesce_owner) { | |
5018 | qla2x00_perform_loop_resync(base_vha); | |
5019 | if (IS_QLA82XX(ha)) { | |
5020 | qla82xx_idc_lock(ha); | |
5021 | qla82xx_clear_qsnt_ready( | |
5022 | base_vha); | |
5023 | qla82xx_idc_unlock(ha); | |
5024 | } else if (IS_QLA8044(ha)) { | |
5025 | qla8044_idc_lock(ha); | |
5026 | qla8044_clear_qsnt_ready( | |
5027 | base_vha); | |
5028 | qla8044_idc_unlock(ha); | |
5029 | } | |
5030 | } | |
5031 | } else { | |
5032 | clear_bit(ISP_QUIESCE_NEEDED, | |
5033 | &base_vha->dpc_flags); | |
5034 | qla2x00_quiesce_io(base_vha); | |
5035 | } | |
5036 | ql_dbg(ql_dbg_dpc, base_vha, 0x400a, | |
5037 | "Quiescence mode end.\n"); | |
5038 | } | |
5039 | ||
5040 | if (test_and_clear_bit(RESET_MARKER_NEEDED, | |
5041 | &base_vha->dpc_flags) && | |
5042 | (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) { | |
5043 | ||
5044 | ql_dbg(ql_dbg_dpc, base_vha, 0x400b, | |
5045 | "Reset marker scheduled.\n"); | |
5046 | qla2x00_rst_aen(base_vha); | |
5047 | clear_bit(RESET_ACTIVE, &base_vha->dpc_flags); | |
5048 | ql_dbg(ql_dbg_dpc, base_vha, 0x400c, | |
5049 | "Reset marker end.\n"); | |
5050 | } | |
5051 | ||
5052 | /* Retry each device up to login retry count */ | |
5053 | if ((test_and_clear_bit(RELOGIN_NEEDED, | |
5054 | &base_vha->dpc_flags)) && | |
5055 | !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) && | |
5056 | atomic_read(&base_vha->loop_state) != LOOP_DOWN) { | |
5057 | ||
5058 | ql_dbg(ql_dbg_dpc, base_vha, 0x400d, | |
5059 | "Relogin scheduled.\n"); | |
5060 | qla2x00_relogin(base_vha); | |
5061 | ql_dbg(ql_dbg_dpc, base_vha, 0x400e, | |
5062 | "Relogin end.\n"); | |
5063 | } | |
5064 | loop_resync_check: | |
5065 | if (test_and_clear_bit(LOOP_RESYNC_NEEDED, | |
5066 | &base_vha->dpc_flags)) { | |
5067 | ||
5068 | ql_dbg(ql_dbg_dpc, base_vha, 0x400f, | |
5069 | "Loop resync scheduled.\n"); | |
5070 | ||
5071 | if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE, | |
5072 | &base_vha->dpc_flags))) { | |
5073 | ||
5074 | rval = qla2x00_loop_resync(base_vha); | |
5075 | ||
5076 | clear_bit(LOOP_RESYNC_ACTIVE, | |
5077 | &base_vha->dpc_flags); | |
5078 | } | |
5079 | ||
5080 | ql_dbg(ql_dbg_dpc, base_vha, 0x4010, | |
5081 | "Loop resync end.\n"); | |
5082 | } | |
5083 | ||
5084 | if (IS_QLAFX00(ha)) | |
5085 | goto intr_on_check; | |
5086 | ||
5087 | if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) && | |
5088 | atomic_read(&base_vha->loop_state) == LOOP_READY) { | |
5089 | clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags); | |
5090 | qla2xxx_flash_npiv_conf(base_vha); | |
5091 | } | |
5092 | ||
5093 | intr_on_check: | |
5094 | if (!ha->interrupts_on) | |
5095 | ha->isp_ops->enable_intrs(ha); | |
5096 | ||
5097 | if (test_and_clear_bit(BEACON_BLINK_NEEDED, | |
5098 | &base_vha->dpc_flags)) { | |
5099 | if (ha->beacon_blink_led == 1) | |
5100 | ha->isp_ops->beacon_blink(base_vha); | |
5101 | } | |
5102 | ||
5103 | if (!IS_QLAFX00(ha)) | |
5104 | qla2x00_do_dpc_all_vps(base_vha); | |
5105 | ||
5106 | ha->dpc_active = 0; | |
5107 | end_loop: | |
5108 | set_current_state(TASK_INTERRUPTIBLE); | |
5109 | } /* End of while(1) */ | |
5110 | __set_current_state(TASK_RUNNING); | |
5111 | ||
5112 | ql_dbg(ql_dbg_dpc, base_vha, 0x4011, | |
5113 | "DPC handler exiting.\n"); | |
5114 | ||
5115 | /* | |
5116 | * Make sure that nobody tries to wake us up again. | |
5117 | */ | |
5118 | ha->dpc_active = 0; | |
5119 | ||
5120 | /* Cleanup any residual CTX SRBs. */ | |
5121 | qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); | |
5122 | ||
5123 | return 0; | |
5124 | } | |
5125 | ||
5126 | void | |
5127 | qla2xxx_wake_dpc(struct scsi_qla_host *vha) | |
5128 | { | |
5129 | struct qla_hw_data *ha = vha->hw; | |
5130 | struct task_struct *t = ha->dpc_thread; | |
5131 | ||
5132 | if (!test_bit(UNLOADING, &vha->dpc_flags) && t) | |
5133 | wake_up_process(t); | |
5134 | } | |
5135 | ||
5136 | /* | |
5137 | * qla2x00_rst_aen | |
5138 | * Processes asynchronous reset. | |
5139 | * | |
5140 | * Input: | |
5141 | * ha = adapter block pointer. | |
5142 | */ | |
5143 | static void | |
5144 | qla2x00_rst_aen(scsi_qla_host_t *vha) | |
5145 | { | |
5146 | if (vha->flags.online && !vha->flags.reset_active && | |
5147 | !atomic_read(&vha->loop_down_timer) && | |
5148 | !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) { | |
5149 | do { | |
5150 | clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); | |
5151 | ||
5152 | /* | |
5153 | * Issue marker command only when we are going to start | |
5154 | * the I/O. | |
5155 | */ | |
5156 | vha->marker_needed = 1; | |
5157 | } while (!atomic_read(&vha->loop_down_timer) && | |
5158 | (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags))); | |
5159 | } | |
5160 | } | |
5161 | ||
5162 | /************************************************************************** | |
5163 | * qla2x00_timer | |
5164 | * | |
5165 | * Description: | |
5166 | * One second timer | |
5167 | * | |
5168 | * Context: Interrupt | |
5169 | ***************************************************************************/ | |
5170 | void | |
5171 | qla2x00_timer(scsi_qla_host_t *vha) | |
5172 | { | |
5173 | unsigned long cpu_flags = 0; | |
5174 | int start_dpc = 0; | |
5175 | int index; | |
5176 | srb_t *sp; | |
5177 | uint16_t w; | |
5178 | struct qla_hw_data *ha = vha->hw; | |
5179 | struct req_que *req; | |
5180 | ||
5181 | if (ha->flags.eeh_busy) { | |
5182 | ql_dbg(ql_dbg_timer, vha, 0x6000, | |
5183 | "EEH = %d, restarting timer.\n", | |
5184 | ha->flags.eeh_busy); | |
5185 | qla2x00_restart_timer(vha, WATCH_INTERVAL); | |
5186 | return; | |
5187 | } | |
5188 | ||
5189 | /* | |
5190 | * Hardware read to raise pending EEH errors during mailbox waits. If | |
5191 | * the read returns -1 then disable the board. | |
5192 | */ | |
5193 | if (!pci_channel_offline(ha->pdev)) { | |
5194 | pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w); | |
5195 | qla2x00_check_reg16_for_disconnect(vha, w); | |
5196 | } | |
5197 | ||
5198 | /* Make sure qla82xx_watchdog is run only for physical port */ | |
5199 | if (!vha->vp_idx && IS_P3P_TYPE(ha)) { | |
5200 | if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) | |
5201 | start_dpc++; | |
5202 | if (IS_QLA82XX(ha)) | |
5203 | qla82xx_watchdog(vha); | |
5204 | else if (IS_QLA8044(ha)) | |
5205 | qla8044_watchdog(vha); | |
5206 | } | |
5207 | ||
5208 | if (!vha->vp_idx && IS_QLAFX00(ha)) | |
5209 | qlafx00_timer_routine(vha); | |
5210 | ||
5211 | /* Loop down handler. */ | |
5212 | if (atomic_read(&vha->loop_down_timer) > 0 && | |
5213 | !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) && | |
5214 | !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags)) | |
5215 | && vha->flags.online) { | |
5216 | ||
5217 | if (atomic_read(&vha->loop_down_timer) == | |
5218 | vha->loop_down_abort_time) { | |
5219 | ||
5220 | ql_log(ql_log_info, vha, 0x6008, | |
5221 | "Loop down - aborting the queues before time expires.\n"); | |
5222 | ||
5223 | if (!IS_QLA2100(ha) && vha->link_down_timeout) | |
5224 | atomic_set(&vha->loop_state, LOOP_DEAD); | |
5225 | ||
5226 | /* | |
5227 | * Schedule an ISP abort to return any FCP2-device | |
5228 | * commands. | |
5229 | */ | |
5230 | /* NPIV - scan physical port only */ | |
5231 | if (!vha->vp_idx) { | |
5232 | spin_lock_irqsave(&ha->hardware_lock, | |
5233 | cpu_flags); | |
5234 | req = ha->req_q_map[0]; | |
5235 | for (index = 1; | |
5236 | index < req->num_outstanding_cmds; | |
5237 | index++) { | |
5238 | fc_port_t *sfcp; | |
5239 | ||
5240 | sp = req->outstanding_cmds[index]; | |
5241 | if (!sp) | |
5242 | continue; | |
5243 | if (sp->type != SRB_SCSI_CMD) | |
5244 | continue; | |
5245 | sfcp = sp->fcport; | |
5246 | if (!(sfcp->flags & FCF_FCP2_DEVICE)) | |
5247 | continue; | |
5248 | ||
5249 | if (IS_QLA82XX(ha)) | |
5250 | set_bit(FCOE_CTX_RESET_NEEDED, | |
5251 | &vha->dpc_flags); | |
5252 | else | |
5253 | set_bit(ISP_ABORT_NEEDED, | |
5254 | &vha->dpc_flags); | |
5255 | break; | |
5256 | } | |
5257 | spin_unlock_irqrestore(&ha->hardware_lock, | |
5258 | cpu_flags); | |
5259 | } | |
5260 | start_dpc++; | |
5261 | } | |
5262 | ||
5263 | /* if the loop has been down for 4 minutes, reinit adapter */ | |
5264 | if (atomic_dec_and_test(&vha->loop_down_timer) != 0) { | |
5265 | if (!(vha->device_flags & DFLG_NO_CABLE)) { | |
5266 | ql_log(ql_log_warn, vha, 0x6009, | |
5267 | "Loop down - aborting ISP.\n"); | |
5268 | ||
5269 | if (IS_QLA82XX(ha)) | |
5270 | set_bit(FCOE_CTX_RESET_NEEDED, | |
5271 | &vha->dpc_flags); | |
5272 | else | |
5273 | set_bit(ISP_ABORT_NEEDED, | |
5274 | &vha->dpc_flags); | |
5275 | } | |
5276 | } | |
5277 | ql_dbg(ql_dbg_timer, vha, 0x600a, | |
5278 | "Loop down - seconds remaining %d.\n", | |
5279 | atomic_read(&vha->loop_down_timer)); | |
5280 | } | |
5281 | /* Check if beacon LED needs to be blinked for physical host only */ | |
5282 | if (!vha->vp_idx && (ha->beacon_blink_led == 1)) { | |
5283 | /* There is no beacon_blink function for ISP82xx */ | |
5284 | if (!IS_P3P_TYPE(ha)) { | |
5285 | set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags); | |
5286 | start_dpc++; | |
5287 | } | |
5288 | } | |
5289 | ||
5290 | /* Process any deferred work. */ | |
5291 | if (!list_empty(&vha->work_list)) | |
5292 | start_dpc++; | |
5293 | ||
5294 | /* Schedule the DPC routine if needed */ | |
5295 | if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) || | |
5296 | test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) || | |
5297 | test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) || | |
5298 | start_dpc || | |
5299 | test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) || | |
5300 | test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) || | |
5301 | test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) || | |
5302 | test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || | |
5303 | test_bit(VP_DPC_NEEDED, &vha->dpc_flags) || | |
5304 | test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) { | |
5305 | ql_dbg(ql_dbg_timer, vha, 0x600b, | |
5306 | "isp_abort_needed=%d loop_resync_needed=%d " | |
5307 | "fcport_update_needed=%d start_dpc=%d " | |
5308 | "reset_marker_needed=%d", | |
5309 | test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags), | |
5310 | test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags), | |
5311 | test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags), | |
5312 | start_dpc, | |
5313 | test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)); | |
5314 | ql_dbg(ql_dbg_timer, vha, 0x600c, | |
5315 | "beacon_blink_needed=%d isp_unrecoverable=%d " | |
5316 | "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d " | |
5317 | "relogin_needed=%d.\n", | |
5318 | test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags), | |
5319 | test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags), | |
5320 | test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags), | |
5321 | test_bit(VP_DPC_NEEDED, &vha->dpc_flags), | |
5322 | test_bit(RELOGIN_NEEDED, &vha->dpc_flags)); | |
5323 | qla2xxx_wake_dpc(vha); | |
5324 | } | |
5325 | ||
5326 | qla2x00_restart_timer(vha, WATCH_INTERVAL); | |
5327 | } | |
5328 | ||
5329 | /* Firmware interface routines. */ | |
5330 | ||
5331 | #define FW_BLOBS 11 | |
5332 | #define FW_ISP21XX 0 | |
5333 | #define FW_ISP22XX 1 | |
5334 | #define FW_ISP2300 2 | |
5335 | #define FW_ISP2322 3 | |
5336 | #define FW_ISP24XX 4 | |
5337 | #define FW_ISP25XX 5 | |
5338 | #define FW_ISP81XX 6 | |
5339 | #define FW_ISP82XX 7 | |
5340 | #define FW_ISP2031 8 | |
5341 | #define FW_ISP8031 9 | |
5342 | #define FW_ISP27XX 10 | |
5343 | ||
5344 | #define FW_FILE_ISP21XX "ql2100_fw.bin" | |
5345 | #define FW_FILE_ISP22XX "ql2200_fw.bin" | |
5346 | #define FW_FILE_ISP2300 "ql2300_fw.bin" | |
5347 | #define FW_FILE_ISP2322 "ql2322_fw.bin" | |
5348 | #define FW_FILE_ISP24XX "ql2400_fw.bin" | |
5349 | #define FW_FILE_ISP25XX "ql2500_fw.bin" | |
5350 | #define FW_FILE_ISP81XX "ql8100_fw.bin" | |
5351 | #define FW_FILE_ISP82XX "ql8200_fw.bin" | |
5352 | #define FW_FILE_ISP2031 "ql2600_fw.bin" | |
5353 | #define FW_FILE_ISP8031 "ql8300_fw.bin" | |
5354 | #define FW_FILE_ISP27XX "ql2700_fw.bin" | |
5355 | ||
5356 | ||
5357 | static DEFINE_MUTEX(qla_fw_lock); | |
5358 | ||
5359 | static struct fw_blob qla_fw_blobs[FW_BLOBS] = { | |
5360 | { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, }, | |
5361 | { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, }, | |
5362 | { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, }, | |
5363 | { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, }, | |
5364 | { .name = FW_FILE_ISP24XX, }, | |
5365 | { .name = FW_FILE_ISP25XX, }, | |
5366 | { .name = FW_FILE_ISP81XX, }, | |
5367 | { .name = FW_FILE_ISP82XX, }, | |
5368 | { .name = FW_FILE_ISP2031, }, | |
5369 | { .name = FW_FILE_ISP8031, }, | |
5370 | { .name = FW_FILE_ISP27XX, }, | |
5371 | }; | |
5372 | ||
5373 | struct fw_blob * | |
5374 | qla2x00_request_firmware(scsi_qla_host_t *vha) | |
5375 | { | |
5376 | struct qla_hw_data *ha = vha->hw; | |
5377 | struct fw_blob *blob; | |
5378 | ||
5379 | if (IS_QLA2100(ha)) { | |
5380 | blob = &qla_fw_blobs[FW_ISP21XX]; | |
5381 | } else if (IS_QLA2200(ha)) { | |
5382 | blob = &qla_fw_blobs[FW_ISP22XX]; | |
5383 | } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { | |
5384 | blob = &qla_fw_blobs[FW_ISP2300]; | |
5385 | } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) { | |
5386 | blob = &qla_fw_blobs[FW_ISP2322]; | |
5387 | } else if (IS_QLA24XX_TYPE(ha)) { | |
5388 | blob = &qla_fw_blobs[FW_ISP24XX]; | |
5389 | } else if (IS_QLA25XX(ha)) { | |
5390 | blob = &qla_fw_blobs[FW_ISP25XX]; | |
5391 | } else if (IS_QLA81XX(ha)) { | |
5392 | blob = &qla_fw_blobs[FW_ISP81XX]; | |
5393 | } else if (IS_QLA82XX(ha)) { | |
5394 | blob = &qla_fw_blobs[FW_ISP82XX]; | |
5395 | } else if (IS_QLA2031(ha)) { | |
5396 | blob = &qla_fw_blobs[FW_ISP2031]; | |
5397 | } else if (IS_QLA8031(ha)) { | |
5398 | blob = &qla_fw_blobs[FW_ISP8031]; | |
5399 | } else if (IS_QLA27XX(ha)) { | |
5400 | blob = &qla_fw_blobs[FW_ISP27XX]; | |
5401 | } else { | |
5402 | return NULL; | |
5403 | } | |
5404 | ||
5405 | mutex_lock(&qla_fw_lock); | |
5406 | if (blob->fw) | |
5407 | goto out; | |
5408 | ||
5409 | if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) { | |
5410 | ql_log(ql_log_warn, vha, 0x0063, | |
5411 | "Failed to load firmware image (%s).\n", blob->name); | |
5412 | blob->fw = NULL; | |
5413 | blob = NULL; | |
5414 | goto out; | |
5415 | } | |
5416 | ||
5417 | out: | |
5418 | mutex_unlock(&qla_fw_lock); | |
5419 | return blob; | |
5420 | } | |
5421 | ||
5422 | static void | |
5423 | qla2x00_release_firmware(void) | |
5424 | { | |
5425 | int idx; | |
5426 | ||
5427 | mutex_lock(&qla_fw_lock); | |
5428 | for (idx = 0; idx < FW_BLOBS; idx++) | |
5429 | release_firmware(qla_fw_blobs[idx].fw); | |
5430 | mutex_unlock(&qla_fw_lock); | |
5431 | } | |
5432 | ||
5433 | static pci_ers_result_t | |
5434 | qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) | |
5435 | { | |
5436 | scsi_qla_host_t *vha = pci_get_drvdata(pdev); | |
5437 | struct qla_hw_data *ha = vha->hw; | |
5438 | ||
5439 | ql_dbg(ql_dbg_aer, vha, 0x9000, | |
5440 | "PCI error detected, state %x.\n", state); | |
5441 | ||
5442 | switch (state) { | |
5443 | case pci_channel_io_normal: | |
5444 | ha->flags.eeh_busy = 0; | |
5445 | return PCI_ERS_RESULT_CAN_RECOVER; | |
5446 | case pci_channel_io_frozen: | |
5447 | ha->flags.eeh_busy = 1; | |
5448 | /* For ISP82XX complete any pending mailbox cmd */ | |
5449 | if (IS_QLA82XX(ha)) { | |
5450 | ha->flags.isp82xx_fw_hung = 1; | |
5451 | ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n"); | |
5452 | qla82xx_clear_pending_mbx(vha); | |
5453 | } | |
5454 | qla2x00_free_irqs(vha); | |
5455 | pci_disable_device(pdev); | |
5456 | /* Return back all IOs */ | |
5457 | qla2x00_abort_all_cmds(vha, DID_RESET << 16); | |
5458 | return PCI_ERS_RESULT_NEED_RESET; | |
5459 | case pci_channel_io_perm_failure: | |
5460 | ha->flags.pci_channel_io_perm_failure = 1; | |
5461 | qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); | |
5462 | return PCI_ERS_RESULT_DISCONNECT; | |
5463 | } | |
5464 | return PCI_ERS_RESULT_NEED_RESET; | |
5465 | } | |
5466 | ||
5467 | static pci_ers_result_t | |
5468 | qla2xxx_pci_mmio_enabled(struct pci_dev *pdev) | |
5469 | { | |
5470 | int risc_paused = 0; | |
5471 | uint32_t stat; | |
5472 | unsigned long flags; | |
5473 | scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); | |
5474 | struct qla_hw_data *ha = base_vha->hw; | |
5475 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | |
5476 | struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; | |
5477 | ||
5478 | if (IS_QLA82XX(ha)) | |
5479 | return PCI_ERS_RESULT_RECOVERED; | |
5480 | ||
5481 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
5482 | if (IS_QLA2100(ha) || IS_QLA2200(ha)){ | |
5483 | stat = RD_REG_DWORD(®->hccr); | |
5484 | if (stat & HCCR_RISC_PAUSE) | |
5485 | risc_paused = 1; | |
5486 | } else if (IS_QLA23XX(ha)) { | |
5487 | stat = RD_REG_DWORD(®->u.isp2300.host_status); | |
5488 | if (stat & HSR_RISC_PAUSED) | |
5489 | risc_paused = 1; | |
5490 | } else if (IS_FWI2_CAPABLE(ha)) { | |
5491 | stat = RD_REG_DWORD(®24->host_status); | |
5492 | if (stat & HSRX_RISC_PAUSED) | |
5493 | risc_paused = 1; | |
5494 | } | |
5495 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
5496 | ||
5497 | if (risc_paused) { | |
5498 | ql_log(ql_log_info, base_vha, 0x9003, | |
5499 | "RISC paused -- mmio_enabled, Dumping firmware.\n"); | |
5500 | ha->isp_ops->fw_dump(base_vha, 0); | |
5501 | ||
5502 | return PCI_ERS_RESULT_NEED_RESET; | |
5503 | } else | |
5504 | return PCI_ERS_RESULT_RECOVERED; | |
5505 | } | |
5506 | ||
5507 | static uint32_t | |
5508 | qla82xx_error_recovery(scsi_qla_host_t *base_vha) | |
5509 | { | |
5510 | uint32_t rval = QLA_FUNCTION_FAILED; | |
5511 | uint32_t drv_active = 0; | |
5512 | struct qla_hw_data *ha = base_vha->hw; | |
5513 | int fn; | |
5514 | struct pci_dev *other_pdev = NULL; | |
5515 | ||
5516 | ql_dbg(ql_dbg_aer, base_vha, 0x9006, | |
5517 | "Entered %s.\n", __func__); | |
5518 | ||
5519 | set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); | |
5520 | ||
5521 | if (base_vha->flags.online) { | |
5522 | /* Abort all outstanding commands, | |
5523 | * so as to be requeued later */ | |
5524 | qla2x00_abort_isp_cleanup(base_vha); | |
5525 | } | |
5526 | ||
5527 | ||
5528 | fn = PCI_FUNC(ha->pdev->devfn); | |
5529 | while (fn > 0) { | |
5530 | fn--; | |
5531 | ql_dbg(ql_dbg_aer, base_vha, 0x9007, | |
5532 | "Finding pci device at function = 0x%x.\n", fn); | |
5533 | other_pdev = | |
5534 | pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus), | |
5535 | ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn), | |
5536 | fn)); | |
5537 | ||
5538 | if (!other_pdev) | |
5539 | continue; | |
5540 | if (atomic_read(&other_pdev->enable_cnt)) { | |
5541 | ql_dbg(ql_dbg_aer, base_vha, 0x9008, | |
5542 | "Found PCI func available and enable at 0x%x.\n", | |
5543 | fn); | |
5544 | pci_dev_put(other_pdev); | |
5545 | break; | |
5546 | } | |
5547 | pci_dev_put(other_pdev); | |
5548 | } | |
5549 | ||
5550 | if (!fn) { | |
5551 | /* Reset owner */ | |
5552 | ql_dbg(ql_dbg_aer, base_vha, 0x9009, | |
5553 | "This devfn is reset owner = 0x%x.\n", | |
5554 | ha->pdev->devfn); | |
5555 | qla82xx_idc_lock(ha); | |
5556 | ||
5557 | qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, | |
5558 | QLA8XXX_DEV_INITIALIZING); | |
5559 | ||
5560 | qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, | |
5561 | QLA82XX_IDC_VERSION); | |
5562 | ||
5563 | drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); | |
5564 | ql_dbg(ql_dbg_aer, base_vha, 0x900a, | |
5565 | "drv_active = 0x%x.\n", drv_active); | |
5566 | ||
5567 | qla82xx_idc_unlock(ha); | |
5568 | /* Reset if device is not already reset | |
5569 | * drv_active would be 0 if a reset has already been done | |
5570 | */ | |
5571 | if (drv_active) | |
5572 | rval = qla82xx_start_firmware(base_vha); | |
5573 | else | |
5574 | rval = QLA_SUCCESS; | |
5575 | qla82xx_idc_lock(ha); | |
5576 | ||
5577 | if (rval != QLA_SUCCESS) { | |
5578 | ql_log(ql_log_info, base_vha, 0x900b, | |
5579 | "HW State: FAILED.\n"); | |
5580 | qla82xx_clear_drv_active(ha); | |
5581 | qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, | |
5582 | QLA8XXX_DEV_FAILED); | |
5583 | } else { | |
5584 | ql_log(ql_log_info, base_vha, 0x900c, | |
5585 | "HW State: READY.\n"); | |
5586 | qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, | |
5587 | QLA8XXX_DEV_READY); | |
5588 | qla82xx_idc_unlock(ha); | |
5589 | ha->flags.isp82xx_fw_hung = 0; | |
5590 | rval = qla82xx_restart_isp(base_vha); | |
5591 | qla82xx_idc_lock(ha); | |
5592 | /* Clear driver state register */ | |
5593 | qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0); | |
5594 | qla82xx_set_drv_active(base_vha); | |
5595 | } | |
5596 | qla82xx_idc_unlock(ha); | |
5597 | } else { | |
5598 | ql_dbg(ql_dbg_aer, base_vha, 0x900d, | |
5599 | "This devfn is not reset owner = 0x%x.\n", | |
5600 | ha->pdev->devfn); | |
5601 | if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) == | |
5602 | QLA8XXX_DEV_READY)) { | |
5603 | ha->flags.isp82xx_fw_hung = 0; | |
5604 | rval = qla82xx_restart_isp(base_vha); | |
5605 | qla82xx_idc_lock(ha); | |
5606 | qla82xx_set_drv_active(base_vha); | |
5607 | qla82xx_idc_unlock(ha); | |
5608 | } | |
5609 | } | |
5610 | clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); | |
5611 | ||
5612 | return rval; | |
5613 | } | |
5614 | ||
5615 | static pci_ers_result_t | |
5616 | qla2xxx_pci_slot_reset(struct pci_dev *pdev) | |
5617 | { | |
5618 | pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT; | |
5619 | scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); | |
5620 | struct qla_hw_data *ha = base_vha->hw; | |
5621 | struct rsp_que *rsp; | |
5622 | int rc, retries = 10; | |
5623 | ||
5624 | ql_dbg(ql_dbg_aer, base_vha, 0x9004, | |
5625 | "Slot Reset.\n"); | |
5626 | ||
5627 | /* Workaround: qla2xxx driver which access hardware earlier | |
5628 | * needs error state to be pci_channel_io_online. | |
5629 | * Otherwise mailbox command timesout. | |
5630 | */ | |
5631 | pdev->error_state = pci_channel_io_normal; | |
5632 | ||
5633 | pci_restore_state(pdev); | |
5634 | ||
5635 | /* pci_restore_state() clears the saved_state flag of the device | |
5636 | * save restored state which resets saved_state flag | |
5637 | */ | |
5638 | pci_save_state(pdev); | |
5639 | ||
5640 | if (ha->mem_only) | |
5641 | rc = pci_enable_device_mem(pdev); | |
5642 | else | |
5643 | rc = pci_enable_device(pdev); | |
5644 | ||
5645 | if (rc) { | |
5646 | ql_log(ql_log_warn, base_vha, 0x9005, | |
5647 | "Can't re-enable PCI device after reset.\n"); | |
5648 | goto exit_slot_reset; | |
5649 | } | |
5650 | ||
5651 | rsp = ha->rsp_q_map[0]; | |
5652 | if (qla2x00_request_irqs(ha, rsp)) | |
5653 | goto exit_slot_reset; | |
5654 | ||
5655 | if (ha->isp_ops->pci_config(base_vha)) | |
5656 | goto exit_slot_reset; | |
5657 | ||
5658 | if (IS_QLA82XX(ha)) { | |
5659 | if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) { | |
5660 | ret = PCI_ERS_RESULT_RECOVERED; | |
5661 | goto exit_slot_reset; | |
5662 | } else | |
5663 | goto exit_slot_reset; | |
5664 | } | |
5665 | ||
5666 | while (ha->flags.mbox_busy && retries--) | |
5667 | msleep(1000); | |
5668 | ||
5669 | set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); | |
5670 | if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS) | |
5671 | ret = PCI_ERS_RESULT_RECOVERED; | |
5672 | clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); | |
5673 | ||
5674 | ||
5675 | exit_slot_reset: | |
5676 | ql_dbg(ql_dbg_aer, base_vha, 0x900e, | |
5677 | "slot_reset return %x.\n", ret); | |
5678 | ||
5679 | return ret; | |
5680 | } | |
5681 | ||
5682 | static void | |
5683 | qla2xxx_pci_resume(struct pci_dev *pdev) | |
5684 | { | |
5685 | scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); | |
5686 | struct qla_hw_data *ha = base_vha->hw; | |
5687 | int ret; | |
5688 | ||
5689 | ql_dbg(ql_dbg_aer, base_vha, 0x900f, | |
5690 | "pci_resume.\n"); | |
5691 | ||
5692 | ret = qla2x00_wait_for_hba_online(base_vha); | |
5693 | if (ret != QLA_SUCCESS) { | |
5694 | ql_log(ql_log_fatal, base_vha, 0x9002, | |
5695 | "The device failed to resume I/O from slot/link_reset.\n"); | |
5696 | } | |
5697 | ||
5698 | pci_cleanup_aer_uncorrect_error_status(pdev); | |
5699 | ||
5700 | ha->flags.eeh_busy = 0; | |
5701 | } | |
5702 | ||
5703 | static void | |
5704 | qla83xx_disable_laser(scsi_qla_host_t *vha) | |
5705 | { | |
5706 | uint32_t reg, data, fn; | |
5707 | struct qla_hw_data *ha = vha->hw; | |
5708 | struct device_reg_24xx __iomem *isp_reg = &ha->iobase->isp24; | |
5709 | ||
5710 | /* pci func #/port # */ | |
5711 | ql_dbg(ql_dbg_init, vha, 0x004b, | |
5712 | "Disabling Laser for hba: %p\n", vha); | |
5713 | ||
5714 | fn = (RD_REG_DWORD(&isp_reg->ctrl_status) & | |
5715 | (BIT_15|BIT_14|BIT_13|BIT_12)); | |
5716 | ||
5717 | fn = (fn >> 12); | |
5718 | ||
5719 | if (fn & 1) | |
5720 | reg = PORT_1_2031; | |
5721 | else | |
5722 | reg = PORT_0_2031; | |
5723 | ||
5724 | data = LASER_OFF_2031; | |
5725 | ||
5726 | qla83xx_wr_reg(vha, reg, data); | |
5727 | } | |
5728 | ||
5729 | static const struct pci_error_handlers qla2xxx_err_handler = { | |
5730 | .error_detected = qla2xxx_pci_error_detected, | |
5731 | .mmio_enabled = qla2xxx_pci_mmio_enabled, | |
5732 | .slot_reset = qla2xxx_pci_slot_reset, | |
5733 | .resume = qla2xxx_pci_resume, | |
5734 | }; | |
5735 | ||
5736 | static struct pci_device_id qla2xxx_pci_tbl[] = { | |
5737 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) }, | |
5738 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) }, | |
5739 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) }, | |
5740 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) }, | |
5741 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) }, | |
5742 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) }, | |
5743 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) }, | |
5744 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) }, | |
5745 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) }, | |
5746 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) }, | |
5747 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) }, | |
5748 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) }, | |
5749 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) }, | |
5750 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) }, | |
5751 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) }, | |
5752 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) }, | |
5753 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) }, | |
5754 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) }, | |
5755 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) }, | |
5756 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) }, | |
5757 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) }, | |
5758 | { 0 }, | |
5759 | }; | |
5760 | MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl); | |
5761 | ||
5762 | static struct pci_driver qla2xxx_pci_driver = { | |
5763 | .name = QLA2XXX_DRIVER_NAME, | |
5764 | .driver = { | |
5765 | .owner = THIS_MODULE, | |
5766 | }, | |
5767 | .id_table = qla2xxx_pci_tbl, | |
5768 | .probe = qla2x00_probe_one, | |
5769 | .remove = qla2x00_remove_one, | |
5770 | .shutdown = qla2x00_shutdown, | |
5771 | .err_handler = &qla2xxx_err_handler, | |
5772 | }; | |
5773 | ||
5774 | static const struct file_operations apidev_fops = { | |
5775 | .owner = THIS_MODULE, | |
5776 | .llseek = noop_llseek, | |
5777 | }; | |
5778 | ||
5779 | /** | |
5780 | * qla2x00_module_init - Module initialization. | |
5781 | **/ | |
5782 | static int __init | |
5783 | qla2x00_module_init(void) | |
5784 | { | |
5785 | int ret = 0; | |
5786 | ||
5787 | /* Allocate cache for SRBs. */ | |
5788 | srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0, | |
5789 | SLAB_HWCACHE_ALIGN, NULL); | |
5790 | if (srb_cachep == NULL) { | |
5791 | ql_log(ql_log_fatal, NULL, 0x0001, | |
5792 | "Unable to allocate SRB cache...Failing load!.\n"); | |
5793 | return -ENOMEM; | |
5794 | } | |
5795 | ||
5796 | /* Initialize target kmem_cache and mem_pools */ | |
5797 | ret = qlt_init(); | |
5798 | if (ret < 0) { | |
5799 | kmem_cache_destroy(srb_cachep); | |
5800 | return ret; | |
5801 | } else if (ret > 0) { | |
5802 | /* | |
5803 | * If initiator mode is explictly disabled by qlt_init(), | |
5804 | * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from | |
5805 | * performing scsi_scan_target() during LOOP UP event. | |
5806 | */ | |
5807 | qla2xxx_transport_functions.disable_target_scan = 1; | |
5808 | qla2xxx_transport_vport_functions.disable_target_scan = 1; | |
5809 | } | |
5810 | ||
5811 | /* Derive version string. */ | |
5812 | strcpy(qla2x00_version_str, QLA2XXX_VERSION); | |
5813 | if (ql2xextended_error_logging) | |
5814 | strcat(qla2x00_version_str, "-debug"); | |
5815 | ||
5816 | qla2xxx_transport_template = | |
5817 | fc_attach_transport(&qla2xxx_transport_functions); | |
5818 | if (!qla2xxx_transport_template) { | |
5819 | kmem_cache_destroy(srb_cachep); | |
5820 | ql_log(ql_log_fatal, NULL, 0x0002, | |
5821 | "fc_attach_transport failed...Failing load!.\n"); | |
5822 | qlt_exit(); | |
5823 | return -ENODEV; | |
5824 | } | |
5825 | ||
5826 | apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops); | |
5827 | if (apidev_major < 0) { | |
5828 | ql_log(ql_log_fatal, NULL, 0x0003, | |
5829 | "Unable to register char device %s.\n", QLA2XXX_APIDEV); | |
5830 | } | |
5831 | ||
5832 | qla2xxx_transport_vport_template = | |
5833 | fc_attach_transport(&qla2xxx_transport_vport_functions); | |
5834 | if (!qla2xxx_transport_vport_template) { | |
5835 | kmem_cache_destroy(srb_cachep); | |
5836 | qlt_exit(); | |
5837 | fc_release_transport(qla2xxx_transport_template); | |
5838 | ql_log(ql_log_fatal, NULL, 0x0004, | |
5839 | "fc_attach_transport vport failed...Failing load!.\n"); | |
5840 | return -ENODEV; | |
5841 | } | |
5842 | ql_log(ql_log_info, NULL, 0x0005, | |
5843 | "QLogic Fibre Channel HBA Driver: %s.\n", | |
5844 | qla2x00_version_str); | |
5845 | ret = pci_register_driver(&qla2xxx_pci_driver); | |
5846 | if (ret) { | |
5847 | kmem_cache_destroy(srb_cachep); | |
5848 | qlt_exit(); | |
5849 | fc_release_transport(qla2xxx_transport_template); | |
5850 | fc_release_transport(qla2xxx_transport_vport_template); | |
5851 | ql_log(ql_log_fatal, NULL, 0x0006, | |
5852 | "pci_register_driver failed...ret=%d Failing load!.\n", | |
5853 | ret); | |
5854 | } | |
5855 | return ret; | |
5856 | } | |
5857 | ||
5858 | /** | |
5859 | * qla2x00_module_exit - Module cleanup. | |
5860 | **/ | |
5861 | static void __exit | |
5862 | qla2x00_module_exit(void) | |
5863 | { | |
5864 | unregister_chrdev(apidev_major, QLA2XXX_APIDEV); | |
5865 | pci_unregister_driver(&qla2xxx_pci_driver); | |
5866 | qla2x00_release_firmware(); | |
5867 | kmem_cache_destroy(srb_cachep); | |
5868 | qlt_exit(); | |
5869 | if (ctx_cachep) | |
5870 | kmem_cache_destroy(ctx_cachep); | |
5871 | fc_release_transport(qla2xxx_transport_template); | |
5872 | fc_release_transport(qla2xxx_transport_vport_template); | |
5873 | } | |
5874 | ||
5875 | module_init(qla2x00_module_init); | |
5876 | module_exit(qla2x00_module_exit); | |
5877 | ||
5878 | MODULE_AUTHOR("QLogic Corporation"); | |
5879 | MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver"); | |
5880 | MODULE_LICENSE("GPL"); | |
5881 | MODULE_VERSION(QLA2XXX_VERSION); | |
5882 | MODULE_FIRMWARE(FW_FILE_ISP21XX); | |
5883 | MODULE_FIRMWARE(FW_FILE_ISP22XX); | |
5884 | MODULE_FIRMWARE(FW_FILE_ISP2300); | |
5885 | MODULE_FIRMWARE(FW_FILE_ISP2322); | |
5886 | MODULE_FIRMWARE(FW_FILE_ISP24XX); | |
5887 | MODULE_FIRMWARE(FW_FILE_ISP25XX); |