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1 | /* | |
2 | * Copyright (C) 2009 Samsung Electronics Ltd. | |
3 | * Jaswinder Singh <jassi.brar@samsung.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | */ | |
15 | ||
16 | #include <linux/init.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/delay.h> | |
20 | #include <linux/clk.h> | |
21 | #include <linux/dma-mapping.h> | |
22 | #include <linux/dmaengine.h> | |
23 | #include <linux/platform_device.h> | |
24 | #include <linux/pm_runtime.h> | |
25 | #include <linux/spi/spi.h> | |
26 | #include <linux/gpio.h> | |
27 | #include <linux/of.h> | |
28 | #include <linux/of_gpio.h> | |
29 | ||
30 | #include <linux/platform_data/spi-s3c64xx.h> | |
31 | ||
32 | #define MAX_SPI_PORTS 6 | |
33 | #define S3C64XX_SPI_QUIRK_POLL (1 << 0) | |
34 | #define S3C64XX_SPI_QUIRK_CS_AUTO (1 << 1) | |
35 | #define AUTOSUSPEND_TIMEOUT 2000 | |
36 | ||
37 | /* Registers and bit-fields */ | |
38 | ||
39 | #define S3C64XX_SPI_CH_CFG 0x00 | |
40 | #define S3C64XX_SPI_CLK_CFG 0x04 | |
41 | #define S3C64XX_SPI_MODE_CFG 0x08 | |
42 | #define S3C64XX_SPI_SLAVE_SEL 0x0C | |
43 | #define S3C64XX_SPI_INT_EN 0x10 | |
44 | #define S3C64XX_SPI_STATUS 0x14 | |
45 | #define S3C64XX_SPI_TX_DATA 0x18 | |
46 | #define S3C64XX_SPI_RX_DATA 0x1C | |
47 | #define S3C64XX_SPI_PACKET_CNT 0x20 | |
48 | #define S3C64XX_SPI_PENDING_CLR 0x24 | |
49 | #define S3C64XX_SPI_SWAP_CFG 0x28 | |
50 | #define S3C64XX_SPI_FB_CLK 0x2C | |
51 | ||
52 | #define S3C64XX_SPI_CH_HS_EN (1<<6) /* High Speed Enable */ | |
53 | #define S3C64XX_SPI_CH_SW_RST (1<<5) | |
54 | #define S3C64XX_SPI_CH_SLAVE (1<<4) | |
55 | #define S3C64XX_SPI_CPOL_L (1<<3) | |
56 | #define S3C64XX_SPI_CPHA_B (1<<2) | |
57 | #define S3C64XX_SPI_CH_RXCH_ON (1<<1) | |
58 | #define S3C64XX_SPI_CH_TXCH_ON (1<<0) | |
59 | ||
60 | #define S3C64XX_SPI_CLKSEL_SRCMSK (3<<9) | |
61 | #define S3C64XX_SPI_CLKSEL_SRCSHFT 9 | |
62 | #define S3C64XX_SPI_ENCLK_ENABLE (1<<8) | |
63 | #define S3C64XX_SPI_PSR_MASK 0xff | |
64 | ||
65 | #define S3C64XX_SPI_MODE_CH_TSZ_BYTE (0<<29) | |
66 | #define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD (1<<29) | |
67 | #define S3C64XX_SPI_MODE_CH_TSZ_WORD (2<<29) | |
68 | #define S3C64XX_SPI_MODE_CH_TSZ_MASK (3<<29) | |
69 | #define S3C64XX_SPI_MODE_BUS_TSZ_BYTE (0<<17) | |
70 | #define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD (1<<17) | |
71 | #define S3C64XX_SPI_MODE_BUS_TSZ_WORD (2<<17) | |
72 | #define S3C64XX_SPI_MODE_BUS_TSZ_MASK (3<<17) | |
73 | #define S3C64XX_SPI_MODE_RXDMA_ON (1<<2) | |
74 | #define S3C64XX_SPI_MODE_TXDMA_ON (1<<1) | |
75 | #define S3C64XX_SPI_MODE_4BURST (1<<0) | |
76 | ||
77 | #define S3C64XX_SPI_SLAVE_AUTO (1<<1) | |
78 | #define S3C64XX_SPI_SLAVE_SIG_INACT (1<<0) | |
79 | #define S3C64XX_SPI_SLAVE_NSC_CNT_2 (2<<4) | |
80 | ||
81 | #define S3C64XX_SPI_INT_TRAILING_EN (1<<6) | |
82 | #define S3C64XX_SPI_INT_RX_OVERRUN_EN (1<<5) | |
83 | #define S3C64XX_SPI_INT_RX_UNDERRUN_EN (1<<4) | |
84 | #define S3C64XX_SPI_INT_TX_OVERRUN_EN (1<<3) | |
85 | #define S3C64XX_SPI_INT_TX_UNDERRUN_EN (1<<2) | |
86 | #define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1) | |
87 | #define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0) | |
88 | ||
89 | #define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5) | |
90 | #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4) | |
91 | #define S3C64XX_SPI_ST_TX_OVERRUN_ERR (1<<3) | |
92 | #define S3C64XX_SPI_ST_TX_UNDERRUN_ERR (1<<2) | |
93 | #define S3C64XX_SPI_ST_RX_FIFORDY (1<<1) | |
94 | #define S3C64XX_SPI_ST_TX_FIFORDY (1<<0) | |
95 | ||
96 | #define S3C64XX_SPI_PACKET_CNT_EN (1<<16) | |
97 | ||
98 | #define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4) | |
99 | #define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3) | |
100 | #define S3C64XX_SPI_PND_RX_UNDERRUN_CLR (1<<2) | |
101 | #define S3C64XX_SPI_PND_RX_OVERRUN_CLR (1<<1) | |
102 | #define S3C64XX_SPI_PND_TRAILING_CLR (1<<0) | |
103 | ||
104 | #define S3C64XX_SPI_SWAP_RX_HALF_WORD (1<<7) | |
105 | #define S3C64XX_SPI_SWAP_RX_BYTE (1<<6) | |
106 | #define S3C64XX_SPI_SWAP_RX_BIT (1<<5) | |
107 | #define S3C64XX_SPI_SWAP_RX_EN (1<<4) | |
108 | #define S3C64XX_SPI_SWAP_TX_HALF_WORD (1<<3) | |
109 | #define S3C64XX_SPI_SWAP_TX_BYTE (1<<2) | |
110 | #define S3C64XX_SPI_SWAP_TX_BIT (1<<1) | |
111 | #define S3C64XX_SPI_SWAP_TX_EN (1<<0) | |
112 | ||
113 | #define S3C64XX_SPI_FBCLK_MSK (3<<0) | |
114 | ||
115 | #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id]) | |
116 | #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \ | |
117 | (1 << (i)->port_conf->tx_st_done)) ? 1 : 0) | |
118 | #define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i)) | |
119 | #define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \ | |
120 | FIFO_LVL_MASK(i)) | |
121 | ||
122 | #define S3C64XX_SPI_MAX_TRAILCNT 0x3ff | |
123 | #define S3C64XX_SPI_TRAILCNT_OFF 19 | |
124 | ||
125 | #define S3C64XX_SPI_TRAILCNT S3C64XX_SPI_MAX_TRAILCNT | |
126 | ||
127 | #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) | |
128 | #define is_polling(x) (x->port_conf->quirks & S3C64XX_SPI_QUIRK_POLL) | |
129 | ||
130 | #define RXBUSY (1<<2) | |
131 | #define TXBUSY (1<<3) | |
132 | ||
133 | struct s3c64xx_spi_dma_data { | |
134 | struct dma_chan *ch; | |
135 | enum dma_transfer_direction direction; | |
136 | }; | |
137 | ||
138 | /** | |
139 | * struct s3c64xx_spi_info - SPI Controller hardware info | |
140 | * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register. | |
141 | * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter. | |
142 | * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter. | |
143 | * @high_speed: True, if the controller supports HIGH_SPEED_EN bit. | |
144 | * @clk_from_cmu: True, if the controller does not include a clock mux and | |
145 | * prescaler unit. | |
146 | * | |
147 | * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but | |
148 | * differ in some aspects such as the size of the fifo and spi bus clock | |
149 | * setup. Such differences are specified to the driver using this structure | |
150 | * which is provided as driver data to the driver. | |
151 | */ | |
152 | struct s3c64xx_spi_port_config { | |
153 | int fifo_lvl_mask[MAX_SPI_PORTS]; | |
154 | int rx_lvl_offset; | |
155 | int tx_st_done; | |
156 | int quirks; | |
157 | bool high_speed; | |
158 | bool clk_from_cmu; | |
159 | }; | |
160 | ||
161 | /** | |
162 | * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver. | |
163 | * @clk: Pointer to the spi clock. | |
164 | * @src_clk: Pointer to the clock used to generate SPI signals. | |
165 | * @master: Pointer to the SPI Protocol master. | |
166 | * @cntrlr_info: Platform specific data for the controller this driver manages. | |
167 | * @tgl_spi: Pointer to the last CS left untoggled by the cs_change hint. | |
168 | * @lock: Controller specific lock. | |
169 | * @state: Set of FLAGS to indicate status. | |
170 | * @rx_dmach: Controller's DMA channel for Rx. | |
171 | * @tx_dmach: Controller's DMA channel for Tx. | |
172 | * @sfr_start: BUS address of SPI controller regs. | |
173 | * @regs: Pointer to ioremap'ed controller registers. | |
174 | * @irq: interrupt | |
175 | * @xfer_completion: To indicate completion of xfer task. | |
176 | * @cur_mode: Stores the active configuration of the controller. | |
177 | * @cur_bpw: Stores the active bits per word settings. | |
178 | * @cur_speed: Stores the active xfer clock speed. | |
179 | */ | |
180 | struct s3c64xx_spi_driver_data { | |
181 | void __iomem *regs; | |
182 | struct clk *clk; | |
183 | struct clk *src_clk; | |
184 | struct platform_device *pdev; | |
185 | struct spi_master *master; | |
186 | struct s3c64xx_spi_info *cntrlr_info; | |
187 | struct spi_device *tgl_spi; | |
188 | spinlock_t lock; | |
189 | unsigned long sfr_start; | |
190 | struct completion xfer_completion; | |
191 | unsigned state; | |
192 | unsigned cur_mode, cur_bpw; | |
193 | unsigned cur_speed; | |
194 | struct s3c64xx_spi_dma_data rx_dma; | |
195 | struct s3c64xx_spi_dma_data tx_dma; | |
196 | struct s3c64xx_spi_port_config *port_conf; | |
197 | unsigned int port_id; | |
198 | }; | |
199 | ||
200 | static void flush_fifo(struct s3c64xx_spi_driver_data *sdd) | |
201 | { | |
202 | void __iomem *regs = sdd->regs; | |
203 | unsigned long loops; | |
204 | u32 val; | |
205 | ||
206 | writel(0, regs + S3C64XX_SPI_PACKET_CNT); | |
207 | ||
208 | val = readl(regs + S3C64XX_SPI_CH_CFG); | |
209 | val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON); | |
210 | writel(val, regs + S3C64XX_SPI_CH_CFG); | |
211 | ||
212 | val = readl(regs + S3C64XX_SPI_CH_CFG); | |
213 | val |= S3C64XX_SPI_CH_SW_RST; | |
214 | val &= ~S3C64XX_SPI_CH_HS_EN; | |
215 | writel(val, regs + S3C64XX_SPI_CH_CFG); | |
216 | ||
217 | /* Flush TxFIFO*/ | |
218 | loops = msecs_to_loops(1); | |
219 | do { | |
220 | val = readl(regs + S3C64XX_SPI_STATUS); | |
221 | } while (TX_FIFO_LVL(val, sdd) && loops--); | |
222 | ||
223 | if (loops == 0) | |
224 | dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n"); | |
225 | ||
226 | /* Flush RxFIFO*/ | |
227 | loops = msecs_to_loops(1); | |
228 | do { | |
229 | val = readl(regs + S3C64XX_SPI_STATUS); | |
230 | if (RX_FIFO_LVL(val, sdd)) | |
231 | readl(regs + S3C64XX_SPI_RX_DATA); | |
232 | else | |
233 | break; | |
234 | } while (loops--); | |
235 | ||
236 | if (loops == 0) | |
237 | dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n"); | |
238 | ||
239 | val = readl(regs + S3C64XX_SPI_CH_CFG); | |
240 | val &= ~S3C64XX_SPI_CH_SW_RST; | |
241 | writel(val, regs + S3C64XX_SPI_CH_CFG); | |
242 | ||
243 | val = readl(regs + S3C64XX_SPI_MODE_CFG); | |
244 | val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON); | |
245 | writel(val, regs + S3C64XX_SPI_MODE_CFG); | |
246 | } | |
247 | ||
248 | static void s3c64xx_spi_dmacb(void *data) | |
249 | { | |
250 | struct s3c64xx_spi_driver_data *sdd; | |
251 | struct s3c64xx_spi_dma_data *dma = data; | |
252 | unsigned long flags; | |
253 | ||
254 | if (dma->direction == DMA_DEV_TO_MEM) | |
255 | sdd = container_of(data, | |
256 | struct s3c64xx_spi_driver_data, rx_dma); | |
257 | else | |
258 | sdd = container_of(data, | |
259 | struct s3c64xx_spi_driver_data, tx_dma); | |
260 | ||
261 | spin_lock_irqsave(&sdd->lock, flags); | |
262 | ||
263 | if (dma->direction == DMA_DEV_TO_MEM) { | |
264 | sdd->state &= ~RXBUSY; | |
265 | if (!(sdd->state & TXBUSY)) | |
266 | complete(&sdd->xfer_completion); | |
267 | } else { | |
268 | sdd->state &= ~TXBUSY; | |
269 | if (!(sdd->state & RXBUSY)) | |
270 | complete(&sdd->xfer_completion); | |
271 | } | |
272 | ||
273 | spin_unlock_irqrestore(&sdd->lock, flags); | |
274 | } | |
275 | ||
276 | static void prepare_dma(struct s3c64xx_spi_dma_data *dma, | |
277 | struct sg_table *sgt) | |
278 | { | |
279 | struct s3c64xx_spi_driver_data *sdd; | |
280 | struct dma_slave_config config; | |
281 | struct dma_async_tx_descriptor *desc; | |
282 | ||
283 | memset(&config, 0, sizeof(config)); | |
284 | ||
285 | if (dma->direction == DMA_DEV_TO_MEM) { | |
286 | sdd = container_of((void *)dma, | |
287 | struct s3c64xx_spi_driver_data, rx_dma); | |
288 | config.direction = dma->direction; | |
289 | config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA; | |
290 | config.src_addr_width = sdd->cur_bpw / 8; | |
291 | config.src_maxburst = 1; | |
292 | dmaengine_slave_config(dma->ch, &config); | |
293 | } else { | |
294 | sdd = container_of((void *)dma, | |
295 | struct s3c64xx_spi_driver_data, tx_dma); | |
296 | config.direction = dma->direction; | |
297 | config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA; | |
298 | config.dst_addr_width = sdd->cur_bpw / 8; | |
299 | config.dst_maxburst = 1; | |
300 | dmaengine_slave_config(dma->ch, &config); | |
301 | } | |
302 | ||
303 | desc = dmaengine_prep_slave_sg(dma->ch, sgt->sgl, sgt->nents, | |
304 | dma->direction, DMA_PREP_INTERRUPT); | |
305 | ||
306 | desc->callback = s3c64xx_spi_dmacb; | |
307 | desc->callback_param = dma; | |
308 | ||
309 | dmaengine_submit(desc); | |
310 | dma_async_issue_pending(dma->ch); | |
311 | } | |
312 | ||
313 | static void s3c64xx_spi_set_cs(struct spi_device *spi, bool enable) | |
314 | { | |
315 | struct s3c64xx_spi_driver_data *sdd = | |
316 | spi_master_get_devdata(spi->master); | |
317 | ||
318 | if (sdd->cntrlr_info->no_cs) | |
319 | return; | |
320 | ||
321 | if (enable) { | |
322 | if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) { | |
323 | writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL); | |
324 | } else { | |
325 | u32 ssel = readl(sdd->regs + S3C64XX_SPI_SLAVE_SEL); | |
326 | ||
327 | ssel |= (S3C64XX_SPI_SLAVE_AUTO | | |
328 | S3C64XX_SPI_SLAVE_NSC_CNT_2); | |
329 | writel(ssel, sdd->regs + S3C64XX_SPI_SLAVE_SEL); | |
330 | } | |
331 | } else { | |
332 | if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) | |
333 | writel(S3C64XX_SPI_SLAVE_SIG_INACT, | |
334 | sdd->regs + S3C64XX_SPI_SLAVE_SEL); | |
335 | } | |
336 | } | |
337 | ||
338 | static int s3c64xx_spi_prepare_transfer(struct spi_master *spi) | |
339 | { | |
340 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi); | |
341 | dma_filter_fn filter = sdd->cntrlr_info->filter; | |
342 | struct device *dev = &sdd->pdev->dev; | |
343 | dma_cap_mask_t mask; | |
344 | int ret; | |
345 | ||
346 | if (!is_polling(sdd)) { | |
347 | dma_cap_zero(mask); | |
348 | dma_cap_set(DMA_SLAVE, mask); | |
349 | ||
350 | /* Acquire DMA channels */ | |
351 | sdd->rx_dma.ch = dma_request_slave_channel_compat(mask, filter, | |
352 | sdd->cntrlr_info->dma_rx, dev, "rx"); | |
353 | if (!sdd->rx_dma.ch) { | |
354 | dev_err(dev, "Failed to get RX DMA channel\n"); | |
355 | ret = -EBUSY; | |
356 | goto out; | |
357 | } | |
358 | spi->dma_rx = sdd->rx_dma.ch; | |
359 | ||
360 | sdd->tx_dma.ch = dma_request_slave_channel_compat(mask, filter, | |
361 | sdd->cntrlr_info->dma_tx, dev, "tx"); | |
362 | if (!sdd->tx_dma.ch) { | |
363 | dev_err(dev, "Failed to get TX DMA channel\n"); | |
364 | ret = -EBUSY; | |
365 | goto out_rx; | |
366 | } | |
367 | spi->dma_tx = sdd->tx_dma.ch; | |
368 | } | |
369 | ||
370 | return 0; | |
371 | ||
372 | out_rx: | |
373 | dma_release_channel(sdd->rx_dma.ch); | |
374 | out: | |
375 | return ret; | |
376 | } | |
377 | ||
378 | static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi) | |
379 | { | |
380 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi); | |
381 | ||
382 | /* Free DMA channels */ | |
383 | if (!is_polling(sdd)) { | |
384 | dma_release_channel(sdd->rx_dma.ch); | |
385 | dma_release_channel(sdd->tx_dma.ch); | |
386 | } | |
387 | ||
388 | return 0; | |
389 | } | |
390 | ||
391 | static bool s3c64xx_spi_can_dma(struct spi_master *master, | |
392 | struct spi_device *spi, | |
393 | struct spi_transfer *xfer) | |
394 | { | |
395 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); | |
396 | ||
397 | return xfer->len > (FIFO_LVL_MASK(sdd) >> 1) + 1; | |
398 | } | |
399 | ||
400 | static void enable_datapath(struct s3c64xx_spi_driver_data *sdd, | |
401 | struct spi_device *spi, | |
402 | struct spi_transfer *xfer, int dma_mode) | |
403 | { | |
404 | void __iomem *regs = sdd->regs; | |
405 | u32 modecfg, chcfg; | |
406 | ||
407 | modecfg = readl(regs + S3C64XX_SPI_MODE_CFG); | |
408 | modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON); | |
409 | ||
410 | chcfg = readl(regs + S3C64XX_SPI_CH_CFG); | |
411 | chcfg &= ~S3C64XX_SPI_CH_TXCH_ON; | |
412 | ||
413 | if (dma_mode) { | |
414 | chcfg &= ~S3C64XX_SPI_CH_RXCH_ON; | |
415 | } else { | |
416 | /* Always shift in data in FIFO, even if xfer is Tx only, | |
417 | * this helps setting PCKT_CNT value for generating clocks | |
418 | * as exactly needed. | |
419 | */ | |
420 | chcfg |= S3C64XX_SPI_CH_RXCH_ON; | |
421 | writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff) | |
422 | | S3C64XX_SPI_PACKET_CNT_EN, | |
423 | regs + S3C64XX_SPI_PACKET_CNT); | |
424 | } | |
425 | ||
426 | if (xfer->tx_buf != NULL) { | |
427 | sdd->state |= TXBUSY; | |
428 | chcfg |= S3C64XX_SPI_CH_TXCH_ON; | |
429 | if (dma_mode) { | |
430 | modecfg |= S3C64XX_SPI_MODE_TXDMA_ON; | |
431 | prepare_dma(&sdd->tx_dma, &xfer->tx_sg); | |
432 | } else { | |
433 | switch (sdd->cur_bpw) { | |
434 | case 32: | |
435 | iowrite32_rep(regs + S3C64XX_SPI_TX_DATA, | |
436 | xfer->tx_buf, xfer->len / 4); | |
437 | break; | |
438 | case 16: | |
439 | iowrite16_rep(regs + S3C64XX_SPI_TX_DATA, | |
440 | xfer->tx_buf, xfer->len / 2); | |
441 | break; | |
442 | default: | |
443 | iowrite8_rep(regs + S3C64XX_SPI_TX_DATA, | |
444 | xfer->tx_buf, xfer->len); | |
445 | break; | |
446 | } | |
447 | } | |
448 | } | |
449 | ||
450 | if (xfer->rx_buf != NULL) { | |
451 | sdd->state |= RXBUSY; | |
452 | ||
453 | if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL | |
454 | && !(sdd->cur_mode & SPI_CPHA)) | |
455 | chcfg |= S3C64XX_SPI_CH_HS_EN; | |
456 | ||
457 | if (dma_mode) { | |
458 | modecfg |= S3C64XX_SPI_MODE_RXDMA_ON; | |
459 | chcfg |= S3C64XX_SPI_CH_RXCH_ON; | |
460 | writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff) | |
461 | | S3C64XX_SPI_PACKET_CNT_EN, | |
462 | regs + S3C64XX_SPI_PACKET_CNT); | |
463 | prepare_dma(&sdd->rx_dma, &xfer->rx_sg); | |
464 | } | |
465 | } | |
466 | ||
467 | writel(modecfg, regs + S3C64XX_SPI_MODE_CFG); | |
468 | writel(chcfg, regs + S3C64XX_SPI_CH_CFG); | |
469 | } | |
470 | ||
471 | static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd, | |
472 | int timeout_ms) | |
473 | { | |
474 | void __iomem *regs = sdd->regs; | |
475 | unsigned long val = 1; | |
476 | u32 status; | |
477 | ||
478 | /* max fifo depth available */ | |
479 | u32 max_fifo = (FIFO_LVL_MASK(sdd) >> 1) + 1; | |
480 | ||
481 | if (timeout_ms) | |
482 | val = msecs_to_loops(timeout_ms); | |
483 | ||
484 | do { | |
485 | status = readl(regs + S3C64XX_SPI_STATUS); | |
486 | } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val); | |
487 | ||
488 | /* return the actual received data length */ | |
489 | return RX_FIFO_LVL(status, sdd); | |
490 | } | |
491 | ||
492 | static int wait_for_dma(struct s3c64xx_spi_driver_data *sdd, | |
493 | struct spi_transfer *xfer) | |
494 | { | |
495 | void __iomem *regs = sdd->regs; | |
496 | unsigned long val; | |
497 | u32 status; | |
498 | int ms; | |
499 | ||
500 | /* millisecs to xfer 'len' bytes @ 'cur_speed' */ | |
501 | ms = xfer->len * 8 * 1000 / sdd->cur_speed; | |
502 | ms += 10; /* some tolerance */ | |
503 | ||
504 | val = msecs_to_jiffies(ms) + 10; | |
505 | val = wait_for_completion_timeout(&sdd->xfer_completion, val); | |
506 | ||
507 | /* | |
508 | * If the previous xfer was completed within timeout, then | |
509 | * proceed further else return -EIO. | |
510 | * DmaTx returns after simply writing data in the FIFO, | |
511 | * w/o waiting for real transmission on the bus to finish. | |
512 | * DmaRx returns only after Dma read data from FIFO which | |
513 | * needs bus transmission to finish, so we don't worry if | |
514 | * Xfer involved Rx(with or without Tx). | |
515 | */ | |
516 | if (val && !xfer->rx_buf) { | |
517 | val = msecs_to_loops(10); | |
518 | status = readl(regs + S3C64XX_SPI_STATUS); | |
519 | while ((TX_FIFO_LVL(status, sdd) | |
520 | || !S3C64XX_SPI_ST_TX_DONE(status, sdd)) | |
521 | && --val) { | |
522 | cpu_relax(); | |
523 | status = readl(regs + S3C64XX_SPI_STATUS); | |
524 | } | |
525 | ||
526 | } | |
527 | ||
528 | /* If timed out while checking rx/tx status return error */ | |
529 | if (!val) | |
530 | return -EIO; | |
531 | ||
532 | return 0; | |
533 | } | |
534 | ||
535 | static int wait_for_pio(struct s3c64xx_spi_driver_data *sdd, | |
536 | struct spi_transfer *xfer) | |
537 | { | |
538 | void __iomem *regs = sdd->regs; | |
539 | unsigned long val; | |
540 | u32 status; | |
541 | int loops; | |
542 | u32 cpy_len; | |
543 | u8 *buf; | |
544 | int ms; | |
545 | ||
546 | /* millisecs to xfer 'len' bytes @ 'cur_speed' */ | |
547 | ms = xfer->len * 8 * 1000 / sdd->cur_speed; | |
548 | ms += 10; /* some tolerance */ | |
549 | ||
550 | val = msecs_to_loops(ms); | |
551 | do { | |
552 | status = readl(regs + S3C64XX_SPI_STATUS); | |
553 | } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val); | |
554 | ||
555 | ||
556 | /* If it was only Tx */ | |
557 | if (!xfer->rx_buf) { | |
558 | sdd->state &= ~TXBUSY; | |
559 | return 0; | |
560 | } | |
561 | ||
562 | /* | |
563 | * If the receive length is bigger than the controller fifo | |
564 | * size, calculate the loops and read the fifo as many times. | |
565 | * loops = length / max fifo size (calculated by using the | |
566 | * fifo mask). | |
567 | * For any size less than the fifo size the below code is | |
568 | * executed atleast once. | |
569 | */ | |
570 | loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1); | |
571 | buf = xfer->rx_buf; | |
572 | do { | |
573 | /* wait for data to be received in the fifo */ | |
574 | cpy_len = s3c64xx_spi_wait_for_timeout(sdd, | |
575 | (loops ? ms : 0)); | |
576 | ||
577 | switch (sdd->cur_bpw) { | |
578 | case 32: | |
579 | ioread32_rep(regs + S3C64XX_SPI_RX_DATA, | |
580 | buf, cpy_len / 4); | |
581 | break; | |
582 | case 16: | |
583 | ioread16_rep(regs + S3C64XX_SPI_RX_DATA, | |
584 | buf, cpy_len / 2); | |
585 | break; | |
586 | default: | |
587 | ioread8_rep(regs + S3C64XX_SPI_RX_DATA, | |
588 | buf, cpy_len); | |
589 | break; | |
590 | } | |
591 | ||
592 | buf = buf + cpy_len; | |
593 | } while (loops--); | |
594 | sdd->state &= ~RXBUSY; | |
595 | ||
596 | return 0; | |
597 | } | |
598 | ||
599 | static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) | |
600 | { | |
601 | void __iomem *regs = sdd->regs; | |
602 | u32 val; | |
603 | ||
604 | /* Disable Clock */ | |
605 | if (sdd->port_conf->clk_from_cmu) { | |
606 | clk_disable_unprepare(sdd->src_clk); | |
607 | } else { | |
608 | val = readl(regs + S3C64XX_SPI_CLK_CFG); | |
609 | val &= ~S3C64XX_SPI_ENCLK_ENABLE; | |
610 | writel(val, regs + S3C64XX_SPI_CLK_CFG); | |
611 | } | |
612 | ||
613 | /* Set Polarity and Phase */ | |
614 | val = readl(regs + S3C64XX_SPI_CH_CFG); | |
615 | val &= ~(S3C64XX_SPI_CH_SLAVE | | |
616 | S3C64XX_SPI_CPOL_L | | |
617 | S3C64XX_SPI_CPHA_B); | |
618 | ||
619 | if (sdd->cur_mode & SPI_CPOL) | |
620 | val |= S3C64XX_SPI_CPOL_L; | |
621 | ||
622 | if (sdd->cur_mode & SPI_CPHA) | |
623 | val |= S3C64XX_SPI_CPHA_B; | |
624 | ||
625 | writel(val, regs + S3C64XX_SPI_CH_CFG); | |
626 | ||
627 | /* Set Channel & DMA Mode */ | |
628 | val = readl(regs + S3C64XX_SPI_MODE_CFG); | |
629 | val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK | |
630 | | S3C64XX_SPI_MODE_CH_TSZ_MASK); | |
631 | ||
632 | switch (sdd->cur_bpw) { | |
633 | case 32: | |
634 | val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD; | |
635 | val |= S3C64XX_SPI_MODE_CH_TSZ_WORD; | |
636 | break; | |
637 | case 16: | |
638 | val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD; | |
639 | val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD; | |
640 | break; | |
641 | default: | |
642 | val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE; | |
643 | val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE; | |
644 | break; | |
645 | } | |
646 | ||
647 | writel(val, regs + S3C64XX_SPI_MODE_CFG); | |
648 | ||
649 | if (sdd->port_conf->clk_from_cmu) { | |
650 | /* Configure Clock */ | |
651 | /* There is half-multiplier before the SPI */ | |
652 | clk_set_rate(sdd->src_clk, sdd->cur_speed * 2); | |
653 | /* Enable Clock */ | |
654 | clk_prepare_enable(sdd->src_clk); | |
655 | } else { | |
656 | /* Configure Clock */ | |
657 | val = readl(regs + S3C64XX_SPI_CLK_CFG); | |
658 | val &= ~S3C64XX_SPI_PSR_MASK; | |
659 | val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1) | |
660 | & S3C64XX_SPI_PSR_MASK); | |
661 | writel(val, regs + S3C64XX_SPI_CLK_CFG); | |
662 | ||
663 | /* Enable Clock */ | |
664 | val = readl(regs + S3C64XX_SPI_CLK_CFG); | |
665 | val |= S3C64XX_SPI_ENCLK_ENABLE; | |
666 | writel(val, regs + S3C64XX_SPI_CLK_CFG); | |
667 | } | |
668 | } | |
669 | ||
670 | #define XFER_DMAADDR_INVALID DMA_BIT_MASK(32) | |
671 | ||
672 | static int s3c64xx_spi_prepare_message(struct spi_master *master, | |
673 | struct spi_message *msg) | |
674 | { | |
675 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); | |
676 | struct spi_device *spi = msg->spi; | |
677 | struct s3c64xx_spi_csinfo *cs = spi->controller_data; | |
678 | ||
679 | /* If Master's(controller) state differs from that needed by Slave */ | |
680 | if (sdd->cur_speed != spi->max_speed_hz | |
681 | || sdd->cur_mode != spi->mode | |
682 | || sdd->cur_bpw != spi->bits_per_word) { | |
683 | sdd->cur_bpw = spi->bits_per_word; | |
684 | sdd->cur_speed = spi->max_speed_hz; | |
685 | sdd->cur_mode = spi->mode; | |
686 | s3c64xx_spi_config(sdd); | |
687 | } | |
688 | ||
689 | /* Configure feedback delay */ | |
690 | writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK); | |
691 | ||
692 | return 0; | |
693 | } | |
694 | ||
695 | static int s3c64xx_spi_transfer_one(struct spi_master *master, | |
696 | struct spi_device *spi, | |
697 | struct spi_transfer *xfer) | |
698 | { | |
699 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); | |
700 | int status; | |
701 | u32 speed; | |
702 | u8 bpw; | |
703 | unsigned long flags; | |
704 | int use_dma; | |
705 | ||
706 | reinit_completion(&sdd->xfer_completion); | |
707 | ||
708 | /* Only BPW and Speed may change across transfers */ | |
709 | bpw = xfer->bits_per_word; | |
710 | speed = xfer->speed_hz; | |
711 | ||
712 | if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) { | |
713 | sdd->cur_bpw = bpw; | |
714 | sdd->cur_speed = speed; | |
715 | s3c64xx_spi_config(sdd); | |
716 | } | |
717 | ||
718 | /* Polling method for xfers not bigger than FIFO capacity */ | |
719 | use_dma = 0; | |
720 | if (!is_polling(sdd) && | |
721 | (sdd->rx_dma.ch && sdd->tx_dma.ch && | |
722 | (xfer->len > ((FIFO_LVL_MASK(sdd) >> 1) + 1)))) | |
723 | use_dma = 1; | |
724 | ||
725 | spin_lock_irqsave(&sdd->lock, flags); | |
726 | ||
727 | /* Pending only which is to be done */ | |
728 | sdd->state &= ~RXBUSY; | |
729 | sdd->state &= ~TXBUSY; | |
730 | ||
731 | enable_datapath(sdd, spi, xfer, use_dma); | |
732 | ||
733 | /* Start the signals */ | |
734 | s3c64xx_spi_set_cs(spi, true); | |
735 | ||
736 | spin_unlock_irqrestore(&sdd->lock, flags); | |
737 | ||
738 | if (use_dma) | |
739 | status = wait_for_dma(sdd, xfer); | |
740 | else | |
741 | status = wait_for_pio(sdd, xfer); | |
742 | ||
743 | if (status) { | |
744 | dev_err(&spi->dev, "I/O Error: rx-%d tx-%d res:rx-%c tx-%c len-%d\n", | |
745 | xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0, | |
746 | (sdd->state & RXBUSY) ? 'f' : 'p', | |
747 | (sdd->state & TXBUSY) ? 'f' : 'p', | |
748 | xfer->len); | |
749 | ||
750 | if (use_dma) { | |
751 | if (xfer->tx_buf != NULL | |
752 | && (sdd->state & TXBUSY)) | |
753 | dmaengine_terminate_all(sdd->tx_dma.ch); | |
754 | if (xfer->rx_buf != NULL | |
755 | && (sdd->state & RXBUSY)) | |
756 | dmaengine_terminate_all(sdd->rx_dma.ch); | |
757 | } | |
758 | } else { | |
759 | flush_fifo(sdd); | |
760 | } | |
761 | ||
762 | return status; | |
763 | } | |
764 | ||
765 | static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata( | |
766 | struct spi_device *spi) | |
767 | { | |
768 | struct s3c64xx_spi_csinfo *cs; | |
769 | struct device_node *slave_np, *data_np = NULL; | |
770 | u32 fb_delay = 0; | |
771 | ||
772 | slave_np = spi->dev.of_node; | |
773 | if (!slave_np) { | |
774 | dev_err(&spi->dev, "device node not found\n"); | |
775 | return ERR_PTR(-EINVAL); | |
776 | } | |
777 | ||
778 | data_np = of_get_child_by_name(slave_np, "controller-data"); | |
779 | if (!data_np) { | |
780 | dev_err(&spi->dev, "child node 'controller-data' not found\n"); | |
781 | return ERR_PTR(-EINVAL); | |
782 | } | |
783 | ||
784 | cs = kzalloc(sizeof(*cs), GFP_KERNEL); | |
785 | if (!cs) { | |
786 | of_node_put(data_np); | |
787 | return ERR_PTR(-ENOMEM); | |
788 | } | |
789 | ||
790 | of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay); | |
791 | cs->fb_delay = fb_delay; | |
792 | of_node_put(data_np); | |
793 | return cs; | |
794 | } | |
795 | ||
796 | /* | |
797 | * Here we only check the validity of requested configuration | |
798 | * and save the configuration in a local data-structure. | |
799 | * The controller is actually configured only just before we | |
800 | * get a message to transfer. | |
801 | */ | |
802 | static int s3c64xx_spi_setup(struct spi_device *spi) | |
803 | { | |
804 | struct s3c64xx_spi_csinfo *cs = spi->controller_data; | |
805 | struct s3c64xx_spi_driver_data *sdd; | |
806 | struct s3c64xx_spi_info *sci; | |
807 | int err; | |
808 | ||
809 | sdd = spi_master_get_devdata(spi->master); | |
810 | if (spi->dev.of_node) { | |
811 | cs = s3c64xx_get_slave_ctrldata(spi); | |
812 | spi->controller_data = cs; | |
813 | } else if (cs) { | |
814 | /* On non-DT platforms the SPI core will set spi->cs_gpio | |
815 | * to -ENOENT. The GPIO pin used to drive the chip select | |
816 | * is defined by using platform data so spi->cs_gpio value | |
817 | * has to be override to have the proper GPIO pin number. | |
818 | */ | |
819 | spi->cs_gpio = cs->line; | |
820 | } | |
821 | ||
822 | if (IS_ERR_OR_NULL(cs)) { | |
823 | dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select); | |
824 | return -ENODEV; | |
825 | } | |
826 | ||
827 | if (!spi_get_ctldata(spi)) { | |
828 | if (gpio_is_valid(spi->cs_gpio)) { | |
829 | err = gpio_request_one(spi->cs_gpio, GPIOF_OUT_INIT_HIGH, | |
830 | dev_name(&spi->dev)); | |
831 | if (err) { | |
832 | dev_err(&spi->dev, | |
833 | "Failed to get /CS gpio [%d]: %d\n", | |
834 | spi->cs_gpio, err); | |
835 | goto err_gpio_req; | |
836 | } | |
837 | } | |
838 | ||
839 | spi_set_ctldata(spi, cs); | |
840 | } | |
841 | ||
842 | sci = sdd->cntrlr_info; | |
843 | ||
844 | pm_runtime_get_sync(&sdd->pdev->dev); | |
845 | ||
846 | /* Check if we can provide the requested rate */ | |
847 | if (!sdd->port_conf->clk_from_cmu) { | |
848 | u32 psr, speed; | |
849 | ||
850 | /* Max possible */ | |
851 | speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1); | |
852 | ||
853 | if (spi->max_speed_hz > speed) | |
854 | spi->max_speed_hz = speed; | |
855 | ||
856 | psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1; | |
857 | psr &= S3C64XX_SPI_PSR_MASK; | |
858 | if (psr == S3C64XX_SPI_PSR_MASK) | |
859 | psr--; | |
860 | ||
861 | speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1); | |
862 | if (spi->max_speed_hz < speed) { | |
863 | if (psr+1 < S3C64XX_SPI_PSR_MASK) { | |
864 | psr++; | |
865 | } else { | |
866 | err = -EINVAL; | |
867 | goto setup_exit; | |
868 | } | |
869 | } | |
870 | ||
871 | speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1); | |
872 | if (spi->max_speed_hz >= speed) { | |
873 | spi->max_speed_hz = speed; | |
874 | } else { | |
875 | dev_err(&spi->dev, "Can't set %dHz transfer speed\n", | |
876 | spi->max_speed_hz); | |
877 | err = -EINVAL; | |
878 | goto setup_exit; | |
879 | } | |
880 | } | |
881 | ||
882 | pm_runtime_mark_last_busy(&sdd->pdev->dev); | |
883 | pm_runtime_put_autosuspend(&sdd->pdev->dev); | |
884 | s3c64xx_spi_set_cs(spi, false); | |
885 | ||
886 | return 0; | |
887 | ||
888 | setup_exit: | |
889 | pm_runtime_mark_last_busy(&sdd->pdev->dev); | |
890 | pm_runtime_put_autosuspend(&sdd->pdev->dev); | |
891 | /* setup() returns with device de-selected */ | |
892 | s3c64xx_spi_set_cs(spi, false); | |
893 | ||
894 | if (gpio_is_valid(spi->cs_gpio)) | |
895 | gpio_free(spi->cs_gpio); | |
896 | spi_set_ctldata(spi, NULL); | |
897 | ||
898 | err_gpio_req: | |
899 | if (spi->dev.of_node) | |
900 | kfree(cs); | |
901 | ||
902 | return err; | |
903 | } | |
904 | ||
905 | static void s3c64xx_spi_cleanup(struct spi_device *spi) | |
906 | { | |
907 | struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi); | |
908 | ||
909 | if (gpio_is_valid(spi->cs_gpio)) { | |
910 | gpio_free(spi->cs_gpio); | |
911 | if (spi->dev.of_node) | |
912 | kfree(cs); | |
913 | else { | |
914 | /* On non-DT platforms, the SPI core sets | |
915 | * spi->cs_gpio to -ENOENT and .setup() | |
916 | * overrides it with the GPIO pin value | |
917 | * passed using platform data. | |
918 | */ | |
919 | spi->cs_gpio = -ENOENT; | |
920 | } | |
921 | } | |
922 | ||
923 | spi_set_ctldata(spi, NULL); | |
924 | } | |
925 | ||
926 | static irqreturn_t s3c64xx_spi_irq(int irq, void *data) | |
927 | { | |
928 | struct s3c64xx_spi_driver_data *sdd = data; | |
929 | struct spi_master *spi = sdd->master; | |
930 | unsigned int val, clr = 0; | |
931 | ||
932 | val = readl(sdd->regs + S3C64XX_SPI_STATUS); | |
933 | ||
934 | if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) { | |
935 | clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR; | |
936 | dev_err(&spi->dev, "RX overrun\n"); | |
937 | } | |
938 | if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) { | |
939 | clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR; | |
940 | dev_err(&spi->dev, "RX underrun\n"); | |
941 | } | |
942 | if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) { | |
943 | clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR; | |
944 | dev_err(&spi->dev, "TX overrun\n"); | |
945 | } | |
946 | if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) { | |
947 | clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR; | |
948 | dev_err(&spi->dev, "TX underrun\n"); | |
949 | } | |
950 | ||
951 | /* Clear the pending irq by setting and then clearing it */ | |
952 | writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR); | |
953 | writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR); | |
954 | ||
955 | return IRQ_HANDLED; | |
956 | } | |
957 | ||
958 | static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel) | |
959 | { | |
960 | struct s3c64xx_spi_info *sci = sdd->cntrlr_info; | |
961 | void __iomem *regs = sdd->regs; | |
962 | unsigned int val; | |
963 | ||
964 | sdd->cur_speed = 0; | |
965 | ||
966 | if (sci->no_cs) | |
967 | writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL); | |
968 | else if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) | |
969 | writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL); | |
970 | ||
971 | /* Disable Interrupts - we use Polling if not DMA mode */ | |
972 | writel(0, regs + S3C64XX_SPI_INT_EN); | |
973 | ||
974 | if (!sdd->port_conf->clk_from_cmu) | |
975 | writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT, | |
976 | regs + S3C64XX_SPI_CLK_CFG); | |
977 | writel(0, regs + S3C64XX_SPI_MODE_CFG); | |
978 | writel(0, regs + S3C64XX_SPI_PACKET_CNT); | |
979 | ||
980 | /* Clear any irq pending bits, should set and clear the bits */ | |
981 | val = S3C64XX_SPI_PND_RX_OVERRUN_CLR | | |
982 | S3C64XX_SPI_PND_RX_UNDERRUN_CLR | | |
983 | S3C64XX_SPI_PND_TX_OVERRUN_CLR | | |
984 | S3C64XX_SPI_PND_TX_UNDERRUN_CLR; | |
985 | writel(val, regs + S3C64XX_SPI_PENDING_CLR); | |
986 | writel(0, regs + S3C64XX_SPI_PENDING_CLR); | |
987 | ||
988 | writel(0, regs + S3C64XX_SPI_SWAP_CFG); | |
989 | ||
990 | val = readl(regs + S3C64XX_SPI_MODE_CFG); | |
991 | val &= ~S3C64XX_SPI_MODE_4BURST; | |
992 | val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF); | |
993 | val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF); | |
994 | writel(val, regs + S3C64XX_SPI_MODE_CFG); | |
995 | ||
996 | flush_fifo(sdd); | |
997 | } | |
998 | ||
999 | #ifdef CONFIG_OF | |
1000 | static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev) | |
1001 | { | |
1002 | struct s3c64xx_spi_info *sci; | |
1003 | u32 temp; | |
1004 | ||
1005 | sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL); | |
1006 | if (!sci) | |
1007 | return ERR_PTR(-ENOMEM); | |
1008 | ||
1009 | if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) { | |
1010 | dev_warn(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n"); | |
1011 | sci->src_clk_nr = 0; | |
1012 | } else { | |
1013 | sci->src_clk_nr = temp; | |
1014 | } | |
1015 | ||
1016 | if (of_property_read_u32(dev->of_node, "num-cs", &temp)) { | |
1017 | dev_warn(dev, "number of chip select lines not specified, assuming 1 chip select line\n"); | |
1018 | sci->num_cs = 1; | |
1019 | } else { | |
1020 | sci->num_cs = temp; | |
1021 | } | |
1022 | ||
1023 | sci->no_cs = of_property_read_bool(dev->of_node, "broken-cs"); | |
1024 | ||
1025 | return sci; | |
1026 | } | |
1027 | #else | |
1028 | static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev) | |
1029 | { | |
1030 | return dev_get_platdata(dev); | |
1031 | } | |
1032 | #endif | |
1033 | ||
1034 | static const struct of_device_id s3c64xx_spi_dt_match[]; | |
1035 | ||
1036 | static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config( | |
1037 | struct platform_device *pdev) | |
1038 | { | |
1039 | #ifdef CONFIG_OF | |
1040 | if (pdev->dev.of_node) { | |
1041 | const struct of_device_id *match; | |
1042 | match = of_match_node(s3c64xx_spi_dt_match, pdev->dev.of_node); | |
1043 | return (struct s3c64xx_spi_port_config *)match->data; | |
1044 | } | |
1045 | #endif | |
1046 | return (struct s3c64xx_spi_port_config *) | |
1047 | platform_get_device_id(pdev)->driver_data; | |
1048 | } | |
1049 | ||
1050 | static int s3c64xx_spi_probe(struct platform_device *pdev) | |
1051 | { | |
1052 | struct resource *mem_res; | |
1053 | struct s3c64xx_spi_driver_data *sdd; | |
1054 | struct s3c64xx_spi_info *sci = dev_get_platdata(&pdev->dev); | |
1055 | struct spi_master *master; | |
1056 | int ret, irq; | |
1057 | char clk_name[16]; | |
1058 | ||
1059 | if (!sci && pdev->dev.of_node) { | |
1060 | sci = s3c64xx_spi_parse_dt(&pdev->dev); | |
1061 | if (IS_ERR(sci)) | |
1062 | return PTR_ERR(sci); | |
1063 | } | |
1064 | ||
1065 | if (!sci) { | |
1066 | dev_err(&pdev->dev, "platform_data missing!\n"); | |
1067 | return -ENODEV; | |
1068 | } | |
1069 | ||
1070 | mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1071 | if (mem_res == NULL) { | |
1072 | dev_err(&pdev->dev, "Unable to get SPI MEM resource\n"); | |
1073 | return -ENXIO; | |
1074 | } | |
1075 | ||
1076 | irq = platform_get_irq(pdev, 0); | |
1077 | if (irq < 0) { | |
1078 | dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq); | |
1079 | return irq; | |
1080 | } | |
1081 | ||
1082 | master = spi_alloc_master(&pdev->dev, | |
1083 | sizeof(struct s3c64xx_spi_driver_data)); | |
1084 | if (master == NULL) { | |
1085 | dev_err(&pdev->dev, "Unable to allocate SPI Master\n"); | |
1086 | return -ENOMEM; | |
1087 | } | |
1088 | ||
1089 | platform_set_drvdata(pdev, master); | |
1090 | ||
1091 | sdd = spi_master_get_devdata(master); | |
1092 | sdd->port_conf = s3c64xx_spi_get_port_config(pdev); | |
1093 | sdd->master = master; | |
1094 | sdd->cntrlr_info = sci; | |
1095 | sdd->pdev = pdev; | |
1096 | sdd->sfr_start = mem_res->start; | |
1097 | if (pdev->dev.of_node) { | |
1098 | ret = of_alias_get_id(pdev->dev.of_node, "spi"); | |
1099 | if (ret < 0) { | |
1100 | dev_err(&pdev->dev, "failed to get alias id, errno %d\n", | |
1101 | ret); | |
1102 | goto err0; | |
1103 | } | |
1104 | sdd->port_id = ret; | |
1105 | } else { | |
1106 | sdd->port_id = pdev->id; | |
1107 | } | |
1108 | ||
1109 | sdd->cur_bpw = 8; | |
1110 | ||
1111 | if (!sdd->pdev->dev.of_node && (!sci->dma_tx || !sci->dma_rx)) { | |
1112 | dev_warn(&pdev->dev, "Unable to get SPI tx/rx DMA data. Switching to poll mode\n"); | |
1113 | sdd->port_conf->quirks = S3C64XX_SPI_QUIRK_POLL; | |
1114 | } | |
1115 | ||
1116 | sdd->tx_dma.direction = DMA_MEM_TO_DEV; | |
1117 | sdd->rx_dma.direction = DMA_DEV_TO_MEM; | |
1118 | ||
1119 | master->dev.of_node = pdev->dev.of_node; | |
1120 | master->bus_num = sdd->port_id; | |
1121 | master->setup = s3c64xx_spi_setup; | |
1122 | master->cleanup = s3c64xx_spi_cleanup; | |
1123 | master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer; | |
1124 | master->prepare_message = s3c64xx_spi_prepare_message; | |
1125 | master->transfer_one = s3c64xx_spi_transfer_one; | |
1126 | master->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer; | |
1127 | master->num_chipselect = sci->num_cs; | |
1128 | master->dma_alignment = 8; | |
1129 | master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) | | |
1130 | SPI_BPW_MASK(8); | |
1131 | /* the spi->mode bits understood by this driver: */ | |
1132 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; | |
1133 | master->auto_runtime_pm = true; | |
1134 | if (!is_polling(sdd)) | |
1135 | master->can_dma = s3c64xx_spi_can_dma; | |
1136 | ||
1137 | sdd->regs = devm_ioremap_resource(&pdev->dev, mem_res); | |
1138 | if (IS_ERR(sdd->regs)) { | |
1139 | ret = PTR_ERR(sdd->regs); | |
1140 | goto err0; | |
1141 | } | |
1142 | ||
1143 | if (sci->cfg_gpio && sci->cfg_gpio()) { | |
1144 | dev_err(&pdev->dev, "Unable to config gpio\n"); | |
1145 | ret = -EBUSY; | |
1146 | goto err0; | |
1147 | } | |
1148 | ||
1149 | /* Setup clocks */ | |
1150 | sdd->clk = devm_clk_get(&pdev->dev, "spi"); | |
1151 | if (IS_ERR(sdd->clk)) { | |
1152 | dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n"); | |
1153 | ret = PTR_ERR(sdd->clk); | |
1154 | goto err0; | |
1155 | } | |
1156 | ||
1157 | if (clk_prepare_enable(sdd->clk)) { | |
1158 | dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n"); | |
1159 | ret = -EBUSY; | |
1160 | goto err0; | |
1161 | } | |
1162 | ||
1163 | sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr); | |
1164 | sdd->src_clk = devm_clk_get(&pdev->dev, clk_name); | |
1165 | if (IS_ERR(sdd->src_clk)) { | |
1166 | dev_err(&pdev->dev, | |
1167 | "Unable to acquire clock '%s'\n", clk_name); | |
1168 | ret = PTR_ERR(sdd->src_clk); | |
1169 | goto err2; | |
1170 | } | |
1171 | ||
1172 | if (clk_prepare_enable(sdd->src_clk)) { | |
1173 | dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name); | |
1174 | ret = -EBUSY; | |
1175 | goto err2; | |
1176 | } | |
1177 | ||
1178 | pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT); | |
1179 | pm_runtime_use_autosuspend(&pdev->dev); | |
1180 | pm_runtime_set_active(&pdev->dev); | |
1181 | pm_runtime_enable(&pdev->dev); | |
1182 | pm_runtime_get_sync(&pdev->dev); | |
1183 | ||
1184 | /* Setup Deufult Mode */ | |
1185 | s3c64xx_spi_hwinit(sdd, sdd->port_id); | |
1186 | ||
1187 | spin_lock_init(&sdd->lock); | |
1188 | init_completion(&sdd->xfer_completion); | |
1189 | ||
1190 | ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0, | |
1191 | "spi-s3c64xx", sdd); | |
1192 | if (ret != 0) { | |
1193 | dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n", | |
1194 | irq, ret); | |
1195 | goto err3; | |
1196 | } | |
1197 | ||
1198 | writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN | | |
1199 | S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN, | |
1200 | sdd->regs + S3C64XX_SPI_INT_EN); | |
1201 | ||
1202 | ret = devm_spi_register_master(&pdev->dev, master); | |
1203 | if (ret != 0) { | |
1204 | dev_err(&pdev->dev, "cannot register SPI master: %d\n", ret); | |
1205 | goto err3; | |
1206 | } | |
1207 | ||
1208 | dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n", | |
1209 | sdd->port_id, master->num_chipselect); | |
1210 | dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tFIFO %dbytes\tDMA=[Rx-%p, Tx-%p]\n", | |
1211 | mem_res, (FIFO_LVL_MASK(sdd) >> 1) + 1, | |
1212 | sci->dma_rx, sci->dma_tx); | |
1213 | ||
1214 | pm_runtime_mark_last_busy(&pdev->dev); | |
1215 | pm_runtime_put_autosuspend(&pdev->dev); | |
1216 | ||
1217 | return 0; | |
1218 | ||
1219 | err3: | |
1220 | pm_runtime_put_noidle(&pdev->dev); | |
1221 | pm_runtime_disable(&pdev->dev); | |
1222 | pm_runtime_set_suspended(&pdev->dev); | |
1223 | ||
1224 | clk_disable_unprepare(sdd->src_clk); | |
1225 | err2: | |
1226 | clk_disable_unprepare(sdd->clk); | |
1227 | err0: | |
1228 | spi_master_put(master); | |
1229 | ||
1230 | return ret; | |
1231 | } | |
1232 | ||
1233 | static int s3c64xx_spi_remove(struct platform_device *pdev) | |
1234 | { | |
1235 | struct spi_master *master = spi_master_get(platform_get_drvdata(pdev)); | |
1236 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); | |
1237 | ||
1238 | pm_runtime_get_sync(&pdev->dev); | |
1239 | ||
1240 | writel(0, sdd->regs + S3C64XX_SPI_INT_EN); | |
1241 | ||
1242 | clk_disable_unprepare(sdd->src_clk); | |
1243 | ||
1244 | clk_disable_unprepare(sdd->clk); | |
1245 | ||
1246 | pm_runtime_put_noidle(&pdev->dev); | |
1247 | pm_runtime_disable(&pdev->dev); | |
1248 | pm_runtime_set_suspended(&pdev->dev); | |
1249 | ||
1250 | return 0; | |
1251 | } | |
1252 | ||
1253 | #ifdef CONFIG_PM_SLEEP | |
1254 | static int s3c64xx_spi_suspend(struct device *dev) | |
1255 | { | |
1256 | struct spi_master *master = dev_get_drvdata(dev); | |
1257 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); | |
1258 | ||
1259 | int ret = spi_master_suspend(master); | |
1260 | if (ret) | |
1261 | return ret; | |
1262 | ||
1263 | ret = pm_runtime_force_suspend(dev); | |
1264 | if (ret < 0) | |
1265 | return ret; | |
1266 | ||
1267 | sdd->cur_speed = 0; /* Output Clock is stopped */ | |
1268 | ||
1269 | return 0; | |
1270 | } | |
1271 | ||
1272 | static int s3c64xx_spi_resume(struct device *dev) | |
1273 | { | |
1274 | struct spi_master *master = dev_get_drvdata(dev); | |
1275 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); | |
1276 | struct s3c64xx_spi_info *sci = sdd->cntrlr_info; | |
1277 | int ret; | |
1278 | ||
1279 | if (sci->cfg_gpio) | |
1280 | sci->cfg_gpio(); | |
1281 | ||
1282 | ret = pm_runtime_force_resume(dev); | |
1283 | if (ret < 0) | |
1284 | return ret; | |
1285 | ||
1286 | s3c64xx_spi_hwinit(sdd, sdd->port_id); | |
1287 | ||
1288 | return spi_master_resume(master); | |
1289 | } | |
1290 | #endif /* CONFIG_PM_SLEEP */ | |
1291 | ||
1292 | #ifdef CONFIG_PM | |
1293 | static int s3c64xx_spi_runtime_suspend(struct device *dev) | |
1294 | { | |
1295 | struct spi_master *master = dev_get_drvdata(dev); | |
1296 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); | |
1297 | ||
1298 | clk_disable_unprepare(sdd->clk); | |
1299 | clk_disable_unprepare(sdd->src_clk); | |
1300 | ||
1301 | return 0; | |
1302 | } | |
1303 | ||
1304 | static int s3c64xx_spi_runtime_resume(struct device *dev) | |
1305 | { | |
1306 | struct spi_master *master = dev_get_drvdata(dev); | |
1307 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); | |
1308 | int ret; | |
1309 | ||
1310 | ret = clk_prepare_enable(sdd->src_clk); | |
1311 | if (ret != 0) | |
1312 | return ret; | |
1313 | ||
1314 | ret = clk_prepare_enable(sdd->clk); | |
1315 | if (ret != 0) { | |
1316 | clk_disable_unprepare(sdd->src_clk); | |
1317 | return ret; | |
1318 | } | |
1319 | ||
1320 | return 0; | |
1321 | } | |
1322 | #endif /* CONFIG_PM */ | |
1323 | ||
1324 | static const struct dev_pm_ops s3c64xx_spi_pm = { | |
1325 | SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume) | |
1326 | SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend, | |
1327 | s3c64xx_spi_runtime_resume, NULL) | |
1328 | }; | |
1329 | ||
1330 | static struct s3c64xx_spi_port_config s3c2443_spi_port_config = { | |
1331 | .fifo_lvl_mask = { 0x7f }, | |
1332 | .rx_lvl_offset = 13, | |
1333 | .tx_st_done = 21, | |
1334 | .high_speed = true, | |
1335 | }; | |
1336 | ||
1337 | static struct s3c64xx_spi_port_config s3c6410_spi_port_config = { | |
1338 | .fifo_lvl_mask = { 0x7f, 0x7F }, | |
1339 | .rx_lvl_offset = 13, | |
1340 | .tx_st_done = 21, | |
1341 | }; | |
1342 | ||
1343 | static struct s3c64xx_spi_port_config s5pv210_spi_port_config = { | |
1344 | .fifo_lvl_mask = { 0x1ff, 0x7F }, | |
1345 | .rx_lvl_offset = 15, | |
1346 | .tx_st_done = 25, | |
1347 | .high_speed = true, | |
1348 | }; | |
1349 | ||
1350 | static struct s3c64xx_spi_port_config exynos4_spi_port_config = { | |
1351 | .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F }, | |
1352 | .rx_lvl_offset = 15, | |
1353 | .tx_st_done = 25, | |
1354 | .high_speed = true, | |
1355 | .clk_from_cmu = true, | |
1356 | }; | |
1357 | ||
1358 | static struct s3c64xx_spi_port_config exynos5440_spi_port_config = { | |
1359 | .fifo_lvl_mask = { 0x1ff }, | |
1360 | .rx_lvl_offset = 15, | |
1361 | .tx_st_done = 25, | |
1362 | .high_speed = true, | |
1363 | .clk_from_cmu = true, | |
1364 | .quirks = S3C64XX_SPI_QUIRK_POLL, | |
1365 | }; | |
1366 | ||
1367 | static struct s3c64xx_spi_port_config exynos7_spi_port_config = { | |
1368 | .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F, 0x7F, 0x7F, 0x1ff}, | |
1369 | .rx_lvl_offset = 15, | |
1370 | .tx_st_done = 25, | |
1371 | .high_speed = true, | |
1372 | .clk_from_cmu = true, | |
1373 | .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, | |
1374 | }; | |
1375 | ||
1376 | static const struct platform_device_id s3c64xx_spi_driver_ids[] = { | |
1377 | { | |
1378 | .name = "s3c2443-spi", | |
1379 | .driver_data = (kernel_ulong_t)&s3c2443_spi_port_config, | |
1380 | }, { | |
1381 | .name = "s3c6410-spi", | |
1382 | .driver_data = (kernel_ulong_t)&s3c6410_spi_port_config, | |
1383 | }, | |
1384 | { }, | |
1385 | }; | |
1386 | ||
1387 | static const struct of_device_id s3c64xx_spi_dt_match[] = { | |
1388 | { .compatible = "samsung,s3c2443-spi", | |
1389 | .data = (void *)&s3c2443_spi_port_config, | |
1390 | }, | |
1391 | { .compatible = "samsung,s3c6410-spi", | |
1392 | .data = (void *)&s3c6410_spi_port_config, | |
1393 | }, | |
1394 | { .compatible = "samsung,s5pv210-spi", | |
1395 | .data = (void *)&s5pv210_spi_port_config, | |
1396 | }, | |
1397 | { .compatible = "samsung,exynos4210-spi", | |
1398 | .data = (void *)&exynos4_spi_port_config, | |
1399 | }, | |
1400 | { .compatible = "samsung,exynos5440-spi", | |
1401 | .data = (void *)&exynos5440_spi_port_config, | |
1402 | }, | |
1403 | { .compatible = "samsung,exynos7-spi", | |
1404 | .data = (void *)&exynos7_spi_port_config, | |
1405 | }, | |
1406 | { }, | |
1407 | }; | |
1408 | MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match); | |
1409 | ||
1410 | static struct platform_driver s3c64xx_spi_driver = { | |
1411 | .driver = { | |
1412 | .name = "s3c64xx-spi", | |
1413 | .pm = &s3c64xx_spi_pm, | |
1414 | .of_match_table = of_match_ptr(s3c64xx_spi_dt_match), | |
1415 | }, | |
1416 | .probe = s3c64xx_spi_probe, | |
1417 | .remove = s3c64xx_spi_remove, | |
1418 | .id_table = s3c64xx_spi_driver_ids, | |
1419 | }; | |
1420 | MODULE_ALIAS("platform:s3c64xx-spi"); | |
1421 | ||
1422 | module_platform_driver(s3c64xx_spi_driver); | |
1423 | ||
1424 | MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>"); | |
1425 | MODULE_DESCRIPTION("S3C64XX SPI Controller Driver"); | |
1426 | MODULE_LICENSE("GPL"); |