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Blackfin SPI Driver: Add GPIO controlled SPI Slave Select support
[mirror_ubuntu-artful-kernel.git] / drivers / spi / spi_bfin5xx.c
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1/*
2 * Blackfin On-Chip SPI Driver
3 *
4 * Copyright 2004-2007 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 */
10
11#include <linux/init.h>
12#include <linux/module.h>
13#include <linux/delay.h>
14#include <linux/device.h>
15#include <linux/io.h>
16#include <linux/ioport.h>
17#include <linux/irq.h>
18#include <linux/errno.h>
19#include <linux/interrupt.h>
20#include <linux/platform_device.h>
21#include <linux/dma-mapping.h>
22#include <linux/spi/spi.h>
23#include <linux/workqueue.h>
24
25#include <asm/dma.h>
26#include <asm/portmux.h>
27#include <asm/bfin5xx_spi.h>
28#include <asm/cacheflush.h>
29
30#define DRV_NAME "bfin-spi"
31#define DRV_AUTHOR "Bryan Wu, Luke Yang"
32#define DRV_DESC "Blackfin on-chip SPI Controller Driver"
33#define DRV_VERSION "1.0"
34
35MODULE_AUTHOR(DRV_AUTHOR);
36MODULE_DESCRIPTION(DRV_DESC);
37MODULE_LICENSE("GPL");
38
39#define IS_DMA_ALIGNED(x) (((u32)(x)&0x07) == 0)
40
41#define START_STATE ((void *)0)
42#define RUNNING_STATE ((void *)1)
43#define DONE_STATE ((void *)2)
44#define ERROR_STATE ((void *)-1)
45#define QUEUE_RUNNING 0
46#define QUEUE_STOPPED 1
47
48struct driver_data {
49 /* Driver model hookup */
50 struct platform_device *pdev;
51
52 /* SPI framework hookup */
53 struct spi_master *master;
54
55 /* Regs base of SPI controller */
56 void __iomem *regs_base;
57
58 /* Pin request list */
59 u16 *pin_req;
60
61 /* BFIN hookup */
62 struct bfin5xx_spi_master *master_info;
63
64 /* Driver message queue */
65 struct workqueue_struct *workqueue;
66 struct work_struct pump_messages;
67 spinlock_t lock;
68 struct list_head queue;
69 int busy;
70 int run;
71
72 /* Message Transfer pump */
73 struct tasklet_struct pump_transfers;
74
75 /* Current message transfer state info */
76 struct spi_message *cur_msg;
77 struct spi_transfer *cur_transfer;
78 struct chip_data *cur_chip;
79 size_t len_in_bytes;
80 size_t len;
81 void *tx;
82 void *tx_end;
83 void *rx;
84 void *rx_end;
85
86 /* DMA stuffs */
87 int dma_channel;
88 int dma_mapped;
89 int dma_requested;
90 dma_addr_t rx_dma;
91 dma_addr_t tx_dma;
92
93 size_t rx_map_len;
94 size_t tx_map_len;
95 u8 n_bytes;
96 int cs_change;
97 void (*write) (struct driver_data *);
98 void (*read) (struct driver_data *);
99 void (*duplex) (struct driver_data *);
100};
101
102struct chip_data {
103 u16 ctl_reg;
104 u16 baud;
105 u16 flag;
106
107 u8 chip_select_num;
108 u8 n_bytes;
109 u8 width; /* 0 or 1 */
110 u8 enable_dma;
111 u8 bits_per_word; /* 8 or 16 */
112 u8 cs_change_per_word;
113 u16 cs_chg_udelay; /* Some devices require > 255usec delay */
114 u32 cs_gpio;
115 void (*write) (struct driver_data *);
116 void (*read) (struct driver_data *);
117 void (*duplex) (struct driver_data *);
118};
119
120#define DEFINE_SPI_REG(reg, off) \
121static inline u16 read_##reg(struct driver_data *drv_data) \
122 { return bfin_read16(drv_data->regs_base + off); } \
123static inline void write_##reg(struct driver_data *drv_data, u16 v) \
124 { bfin_write16(drv_data->regs_base + off, v); }
125
126DEFINE_SPI_REG(CTRL, 0x00)
127DEFINE_SPI_REG(FLAG, 0x04)
128DEFINE_SPI_REG(STAT, 0x08)
129DEFINE_SPI_REG(TDBR, 0x0C)
130DEFINE_SPI_REG(RDBR, 0x10)
131DEFINE_SPI_REG(BAUD, 0x14)
132DEFINE_SPI_REG(SHAW, 0x18)
133
134static void bfin_spi_enable(struct driver_data *drv_data)
135{
136 u16 cr;
137
138 cr = read_CTRL(drv_data);
139 write_CTRL(drv_data, (cr | BIT_CTL_ENABLE));
140}
141
142static void bfin_spi_disable(struct driver_data *drv_data)
143{
144 u16 cr;
145
146 cr = read_CTRL(drv_data);
147 write_CTRL(drv_data, (cr & (~BIT_CTL_ENABLE)));
148}
149
150/* Caculate the SPI_BAUD register value based on input HZ */
151static u16 hz_to_spi_baud(u32 speed_hz)
152{
153 u_long sclk = get_sclk();
154 u16 spi_baud = (sclk / (2 * speed_hz));
155
156 if ((sclk % (2 * speed_hz)) > 0)
157 spi_baud++;
158
159 if (spi_baud < MIN_SPI_BAUD_VAL)
160 spi_baud = MIN_SPI_BAUD_VAL;
161
162 return spi_baud;
163}
164
165static int bfin_spi_flush(struct driver_data *drv_data)
166{
167 unsigned long limit = loops_per_jiffy << 1;
168
169 /* wait for stop and clear stat */
170 while (!(read_STAT(drv_data) & BIT_STAT_SPIF) && limit--)
171 cpu_relax();
172
173 write_STAT(drv_data, BIT_STAT_CLR);
174
175 return limit;
176}
177
178/* Chip select operation functions for cs_change flag */
179static void bfin_spi_cs_active(struct driver_data *drv_data, struct chip_data *chip)
180{
181 if (likely(chip->chip_select_num)) {
182 u16 flag = read_FLAG(drv_data);
183
184 flag |= chip->flag;
185 flag &= ~(chip->flag << 8);
186
187 write_FLAG(drv_data, flag);
188 } else {
189 gpio_set_value(chip->cs_gpio, 0);
190 }
191}
192
193static void bfin_spi_cs_deactive(struct driver_data *drv_data, struct chip_data *chip)
194{
195 if (likely(chip->chip_select_num)) {
196 u16 flag = read_FLAG(drv_data);
197
198 flag &= ~chip->flag;
199 flag |= (chip->flag << 8);
200
201 write_FLAG(drv_data, flag);
202 } else {
203 gpio_set_value(chip->cs_gpio, 1);
204 }
205
206 /* Move delay here for consistency */
207 if (chip->cs_chg_udelay)
208 udelay(chip->cs_chg_udelay);
209}
210
211/* stop controller and re-config current chip*/
212static void bfin_spi_restore_state(struct driver_data *drv_data)
213{
214 struct chip_data *chip = drv_data->cur_chip;
215
216 /* Clear status and disable clock */
217 write_STAT(drv_data, BIT_STAT_CLR);
218 bfin_spi_disable(drv_data);
219 dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n");
220
221 /* Load the registers */
222 write_CTRL(drv_data, chip->ctl_reg);
223 write_BAUD(drv_data, chip->baud);
224
225 bfin_spi_enable(drv_data);
226 bfin_spi_cs_active(drv_data, chip);
227}
228
229/* used to kick off transfer in rx mode */
230static unsigned short bfin_spi_dummy_read(struct driver_data *drv_data)
231{
232 unsigned short tmp;
233 tmp = read_RDBR(drv_data);
234 return tmp;
235}
236
237static void bfin_spi_null_writer(struct driver_data *drv_data)
238{
239 u8 n_bytes = drv_data->n_bytes;
240
241 while (drv_data->tx < drv_data->tx_end) {
242 write_TDBR(drv_data, 0);
243 while ((read_STAT(drv_data) & BIT_STAT_TXS))
244 cpu_relax();
245 drv_data->tx += n_bytes;
246 }
247}
248
249static void bfin_spi_null_reader(struct driver_data *drv_data)
250{
251 u8 n_bytes = drv_data->n_bytes;
252 bfin_spi_dummy_read(drv_data);
253
254 while (drv_data->rx < drv_data->rx_end) {
255 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
256 cpu_relax();
257 bfin_spi_dummy_read(drv_data);
258 drv_data->rx += n_bytes;
259 }
260}
261
262static void bfin_spi_u8_writer(struct driver_data *drv_data)
263{
264 dev_dbg(&drv_data->pdev->dev,
265 "cr8-s is 0x%x\n", read_STAT(drv_data));
266
267 while (drv_data->tx < drv_data->tx_end) {
268 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
269 while (read_STAT(drv_data) & BIT_STAT_TXS)
270 cpu_relax();
271 ++drv_data->tx;
272 }
273
274 /* poll for SPI completion before return */
275 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
276 cpu_relax();
277}
278
279static void bfin_spi_u8_cs_chg_writer(struct driver_data *drv_data)
280{
281 struct chip_data *chip = drv_data->cur_chip;
282
283 while (drv_data->tx < drv_data->tx_end) {
284 bfin_spi_cs_active(drv_data, chip);
285
286 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
287 while (read_STAT(drv_data) & BIT_STAT_TXS)
288 cpu_relax();
289 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
290 cpu_relax();
291
292 bfin_spi_cs_deactive(drv_data, chip);
293
294 ++drv_data->tx;
295 }
296}
297
298static void bfin_spi_u8_reader(struct driver_data *drv_data)
299{
300 dev_dbg(&drv_data->pdev->dev,
301 "cr-8 is 0x%x\n", read_STAT(drv_data));
302
303 /* poll for SPI completion before start */
304 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
305 cpu_relax();
306
307 /* clear TDBR buffer before read(else it will be shifted out) */
308 write_TDBR(drv_data, 0xFFFF);
309
310 bfin_spi_dummy_read(drv_data);
311
312 while (drv_data->rx < drv_data->rx_end - 1) {
313 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
314 cpu_relax();
315 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
316 ++drv_data->rx;
317 }
318
319 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
320 cpu_relax();
321 *(u8 *) (drv_data->rx) = read_SHAW(drv_data);
322 ++drv_data->rx;
323}
324
325static void bfin_spi_u8_cs_chg_reader(struct driver_data *drv_data)
326{
327 struct chip_data *chip = drv_data->cur_chip;
328
329 while (drv_data->rx < drv_data->rx_end) {
330 bfin_spi_cs_active(drv_data, chip);
331 read_RDBR(drv_data); /* kick off */
332
333 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
334 cpu_relax();
335 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
336 cpu_relax();
337
338 *(u8 *) (drv_data->rx) = read_SHAW(drv_data);
339 bfin_spi_cs_deactive(drv_data, chip);
340
341 ++drv_data->rx;
342 }
343}
344
345static void bfin_spi_u8_duplex(struct driver_data *drv_data)
346{
347 /* in duplex mode, clk is triggered by writing of TDBR */
348 while (drv_data->rx < drv_data->rx_end) {
349 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
350 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
351 cpu_relax();
352 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
353 cpu_relax();
354 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
355 ++drv_data->rx;
356 ++drv_data->tx;
357 }
358}
359
360static void bfin_spi_u8_cs_chg_duplex(struct driver_data *drv_data)
361{
362 struct chip_data *chip = drv_data->cur_chip;
363
364 while (drv_data->rx < drv_data->rx_end) {
365 bfin_spi_cs_active(drv_data, chip);
366
367 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
368
369 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
370 cpu_relax();
371 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
372 cpu_relax();
373 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
374
375 bfin_spi_cs_deactive(drv_data, chip);
376
377 ++drv_data->rx;
378 ++drv_data->tx;
379 }
380}
381
382static void bfin_spi_u16_writer(struct driver_data *drv_data)
383{
384 dev_dbg(&drv_data->pdev->dev,
385 "cr16 is 0x%x\n", read_STAT(drv_data));
386
387 while (drv_data->tx < drv_data->tx_end) {
388 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
389 while ((read_STAT(drv_data) & BIT_STAT_TXS))
390 cpu_relax();
391 drv_data->tx += 2;
392 }
393
394 /* poll for SPI completion before return */
395 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
396 cpu_relax();
397}
398
399static void bfin_spi_u16_cs_chg_writer(struct driver_data *drv_data)
400{
401 struct chip_data *chip = drv_data->cur_chip;
402
403 while (drv_data->tx < drv_data->tx_end) {
404 bfin_spi_cs_active(drv_data, chip);
405
406 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
407 while ((read_STAT(drv_data) & BIT_STAT_TXS))
408 cpu_relax();
409 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
410 cpu_relax();
411
412 bfin_spi_cs_deactive(drv_data, chip);
413
414 drv_data->tx += 2;
415 }
416}
417
418static void bfin_spi_u16_reader(struct driver_data *drv_data)
419{
420 dev_dbg(&drv_data->pdev->dev,
421 "cr-16 is 0x%x\n", read_STAT(drv_data));
422
423 /* poll for SPI completion before start */
424 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
425 cpu_relax();
426
427 /* clear TDBR buffer before read(else it will be shifted out) */
428 write_TDBR(drv_data, 0xFFFF);
429
430 bfin_spi_dummy_read(drv_data);
431
432 while (drv_data->rx < (drv_data->rx_end - 2)) {
433 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
434 cpu_relax();
435 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
436 drv_data->rx += 2;
437 }
438
439 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
440 cpu_relax();
441 *(u16 *) (drv_data->rx) = read_SHAW(drv_data);
442 drv_data->rx += 2;
443}
444
445static void bfin_spi_u16_cs_chg_reader(struct driver_data *drv_data)
446{
447 struct chip_data *chip = drv_data->cur_chip;
448
449 /* poll for SPI completion before start */
450 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
451 cpu_relax();
452
453 /* clear TDBR buffer before read(else it will be shifted out) */
454 write_TDBR(drv_data, 0xFFFF);
455
456 bfin_spi_cs_active(drv_data, chip);
457 bfin_spi_dummy_read(drv_data);
458
459 while (drv_data->rx < drv_data->rx_end - 2) {
460 bfin_spi_cs_deactive(drv_data, chip);
461
462 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
463 cpu_relax();
464 bfin_spi_cs_active(drv_data, chip);
465 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
466 drv_data->rx += 2;
467 }
468 bfin_spi_cs_deactive(drv_data, chip);
469
470 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
471 cpu_relax();
472 *(u16 *) (drv_data->rx) = read_SHAW(drv_data);
473 drv_data->rx += 2;
474}
475
476static void bfin_spi_u16_duplex(struct driver_data *drv_data)
477{
478 /* in duplex mode, clk is triggered by writing of TDBR */
479 while (drv_data->tx < drv_data->tx_end) {
480 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
481 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
482 cpu_relax();
483 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
484 cpu_relax();
485 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
486 drv_data->rx += 2;
487 drv_data->tx += 2;
488 }
489}
490
491static void bfin_spi_u16_cs_chg_duplex(struct driver_data *drv_data)
492{
493 struct chip_data *chip = drv_data->cur_chip;
494
495 while (drv_data->tx < drv_data->tx_end) {
496 bfin_spi_cs_active(drv_data, chip);
497
498 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
499 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
500 cpu_relax();
501 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
502 cpu_relax();
503 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
504
505 bfin_spi_cs_deactive(drv_data, chip);
506
507 drv_data->rx += 2;
508 drv_data->tx += 2;
509 }
510}
511
512/* test if ther is more transfer to be done */
513static void *bfin_spi_next_transfer(struct driver_data *drv_data)
514{
515 struct spi_message *msg = drv_data->cur_msg;
516 struct spi_transfer *trans = drv_data->cur_transfer;
517
518 /* Move to next transfer */
519 if (trans->transfer_list.next != &msg->transfers) {
520 drv_data->cur_transfer =
521 list_entry(trans->transfer_list.next,
522 struct spi_transfer, transfer_list);
523 return RUNNING_STATE;
524 } else
525 return DONE_STATE;
526}
527
528/*
529 * caller already set message->status;
530 * dma and pio irqs are blocked give finished message back
531 */
532static void bfin_spi_giveback(struct driver_data *drv_data)
533{
534 struct chip_data *chip = drv_data->cur_chip;
535 struct spi_transfer *last_transfer;
536 unsigned long flags;
537 struct spi_message *msg;
538
539 spin_lock_irqsave(&drv_data->lock, flags);
540 msg = drv_data->cur_msg;
541 drv_data->cur_msg = NULL;
542 drv_data->cur_transfer = NULL;
543 drv_data->cur_chip = NULL;
544 queue_work(drv_data->workqueue, &drv_data->pump_messages);
545 spin_unlock_irqrestore(&drv_data->lock, flags);
546
547 last_transfer = list_entry(msg->transfers.prev,
548 struct spi_transfer, transfer_list);
549
550 msg->state = NULL;
551
552 if (!drv_data->cs_change)
553 bfin_spi_cs_deactive(drv_data, chip);
554
555 /* Not stop spi in autobuffer mode */
556 if (drv_data->tx_dma != 0xFFFF)
557 bfin_spi_disable(drv_data);
558
559 if (msg->complete)
560 msg->complete(msg->context);
561}
562
563static irqreturn_t bfin_spi_dma_irq_handler(int irq, void *dev_id)
564{
565 struct driver_data *drv_data = dev_id;
566 struct chip_data *chip = drv_data->cur_chip;
567 struct spi_message *msg = drv_data->cur_msg;
568 unsigned long timeout;
569 unsigned short dmastat = get_dma_curr_irqstat(drv_data->dma_channel);
570 u16 spistat = read_STAT(drv_data);
571
572 dev_dbg(&drv_data->pdev->dev,
573 "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
574 dmastat, spistat);
575
576 clear_dma_irqstat(drv_data->dma_channel);
577
578 /* Wait for DMA to complete */
579 while (get_dma_curr_irqstat(drv_data->dma_channel) & DMA_RUN)
580 cpu_relax();
581
582 /*
583 * wait for the last transaction shifted out. HRM states:
584 * at this point there may still be data in the SPI DMA FIFO waiting
585 * to be transmitted ... software needs to poll TXS in the SPI_STAT
586 * register until it goes low for 2 successive reads
587 */
588 if (drv_data->tx != NULL) {
589 while ((read_STAT(drv_data) & TXS) ||
590 (read_STAT(drv_data) & TXS))
591 cpu_relax();
592 }
593
594 dev_dbg(&drv_data->pdev->dev,
595 "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
596 dmastat, read_STAT(drv_data));
597
598 timeout = jiffies + HZ;
599 while (!(read_STAT(drv_data) & SPIF))
600 if (!time_before(jiffies, timeout)) {
601 dev_warn(&drv_data->pdev->dev, "timeout waiting for SPIF");
602 break;
603 } else
604 cpu_relax();
605
606 if ((dmastat & DMA_ERR) && (spistat & RBSY)) {
607 msg->state = ERROR_STATE;
608 dev_err(&drv_data->pdev->dev, "dma receive: fifo/buffer overflow\n");
609 } else {
610 msg->actual_length += drv_data->len_in_bytes;
611
612 if (drv_data->cs_change)
613 bfin_spi_cs_deactive(drv_data, chip);
614
615 /* Move to next transfer */
616 msg->state = bfin_spi_next_transfer(drv_data);
617 }
618
619 /* Schedule transfer tasklet */
620 tasklet_schedule(&drv_data->pump_transfers);
621
622 /* free the irq handler before next transfer */
623 dev_dbg(&drv_data->pdev->dev,
624 "disable dma channel irq%d\n",
625 drv_data->dma_channel);
626 dma_disable_irq(drv_data->dma_channel);
627
628 return IRQ_HANDLED;
629}
630
631static void bfin_spi_pump_transfers(unsigned long data)
632{
633 struct driver_data *drv_data = (struct driver_data *)data;
634 struct spi_message *message = NULL;
635 struct spi_transfer *transfer = NULL;
636 struct spi_transfer *previous = NULL;
637 struct chip_data *chip = NULL;
638 u8 width;
639 u16 cr, dma_width, dma_config;
640 u32 tranf_success = 1;
641 u8 full_duplex = 0;
642
643 /* Get current state information */
644 message = drv_data->cur_msg;
645 transfer = drv_data->cur_transfer;
646 chip = drv_data->cur_chip;
647
648 /*
649 * if msg is error or done, report it back using complete() callback
650 */
651
652 /* Handle for abort */
653 if (message->state == ERROR_STATE) {
654 dev_dbg(&drv_data->pdev->dev, "transfer: we've hit an error\n");
655 message->status = -EIO;
656 bfin_spi_giveback(drv_data);
657 return;
658 }
659
660 /* Handle end of message */
661 if (message->state == DONE_STATE) {
662 dev_dbg(&drv_data->pdev->dev, "transfer: all done!\n");
663 message->status = 0;
664 bfin_spi_giveback(drv_data);
665 return;
666 }
667
668 /* Delay if requested at end of transfer */
669 if (message->state == RUNNING_STATE) {
670 dev_dbg(&drv_data->pdev->dev, "transfer: still running ...\n");
671 previous = list_entry(transfer->transfer_list.prev,
672 struct spi_transfer, transfer_list);
673 if (previous->delay_usecs)
674 udelay(previous->delay_usecs);
675 }
676
677 /* Setup the transfer state based on the type of transfer */
678 if (bfin_spi_flush(drv_data) == 0) {
679 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
680 message->status = -EIO;
681 bfin_spi_giveback(drv_data);
682 return;
683 }
684
685 if (transfer->tx_buf != NULL) {
686 drv_data->tx = (void *)transfer->tx_buf;
687 drv_data->tx_end = drv_data->tx + transfer->len;
688 dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n",
689 transfer->tx_buf, drv_data->tx_end);
690 } else {
691 drv_data->tx = NULL;
692 }
693
694 if (transfer->rx_buf != NULL) {
695 full_duplex = transfer->tx_buf != NULL;
696 drv_data->rx = transfer->rx_buf;
697 drv_data->rx_end = drv_data->rx + transfer->len;
698 dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n",
699 transfer->rx_buf, drv_data->rx_end);
700 } else {
701 drv_data->rx = NULL;
702 }
703
704 drv_data->rx_dma = transfer->rx_dma;
705 drv_data->tx_dma = transfer->tx_dma;
706 drv_data->len_in_bytes = transfer->len;
707 drv_data->cs_change = transfer->cs_change;
708
709 /* Bits per word setup */
710 switch (transfer->bits_per_word) {
711 case 8:
712 drv_data->n_bytes = 1;
713 width = CFG_SPI_WORDSIZE8;
714 drv_data->read = chip->cs_change_per_word ?
715 bfin_spi_u8_cs_chg_reader : bfin_spi_u8_reader;
716 drv_data->write = chip->cs_change_per_word ?
717 bfin_spi_u8_cs_chg_writer : bfin_spi_u8_writer;
718 drv_data->duplex = chip->cs_change_per_word ?
719 bfin_spi_u8_cs_chg_duplex : bfin_spi_u8_duplex;
720 break;
721
722 case 16:
723 drv_data->n_bytes = 2;
724 width = CFG_SPI_WORDSIZE16;
725 drv_data->read = chip->cs_change_per_word ?
726 bfin_spi_u16_cs_chg_reader : bfin_spi_u16_reader;
727 drv_data->write = chip->cs_change_per_word ?
728 bfin_spi_u16_cs_chg_writer : bfin_spi_u16_writer;
729 drv_data->duplex = chip->cs_change_per_word ?
730 bfin_spi_u16_cs_chg_duplex : bfin_spi_u16_duplex;
731 break;
732
733 default:
734 /* No change, the same as default setting */
735 drv_data->n_bytes = chip->n_bytes;
736 width = chip->width;
737 drv_data->write = drv_data->tx ? chip->write : bfin_spi_null_writer;
738 drv_data->read = drv_data->rx ? chip->read : bfin_spi_null_reader;
739 drv_data->duplex = chip->duplex ? chip->duplex : bfin_spi_null_writer;
740 break;
741 }
742 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
743 cr |= (width << 8);
744 write_CTRL(drv_data, cr);
745
746 if (width == CFG_SPI_WORDSIZE16) {
747 drv_data->len = (transfer->len) >> 1;
748 } else {
749 drv_data->len = transfer->len;
750 }
751 dev_dbg(&drv_data->pdev->dev,
752 "transfer: drv_data->write is %p, chip->write is %p, null_wr is %p\n",
753 drv_data->write, chip->write, bfin_spi_null_writer);
754
755 /* speed and width has been set on per message */
756 message->state = RUNNING_STATE;
757 dma_config = 0;
758
759 /* Speed setup (surely valid because already checked) */
760 if (transfer->speed_hz)
761 write_BAUD(drv_data, hz_to_spi_baud(transfer->speed_hz));
762 else
763 write_BAUD(drv_data, chip->baud);
764
765 write_STAT(drv_data, BIT_STAT_CLR);
766 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
767 if (drv_data->cs_change)
768 bfin_spi_cs_active(drv_data, chip);
769
770 dev_dbg(&drv_data->pdev->dev,
771 "now pumping a transfer: width is %d, len is %d\n",
772 width, transfer->len);
773
774 /*
775 * Try to map dma buffer and do a dma transfer. If successful use,
776 * different way to r/w according to the enable_dma settings and if
777 * we are not doing a full duplex transfer (since the hardware does
778 * not support full duplex DMA transfers).
779 */
780 if (!full_duplex && drv_data->cur_chip->enable_dma
781 && drv_data->len > 6) {
782
783 unsigned long dma_start_addr, flags;
784
785 disable_dma(drv_data->dma_channel);
786 clear_dma_irqstat(drv_data->dma_channel);
787
788 /* config dma channel */
789 dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n");
790 set_dma_x_count(drv_data->dma_channel, drv_data->len);
791 if (width == CFG_SPI_WORDSIZE16) {
792 set_dma_x_modify(drv_data->dma_channel, 2);
793 dma_width = WDSIZE_16;
794 } else {
795 set_dma_x_modify(drv_data->dma_channel, 1);
796 dma_width = WDSIZE_8;
797 }
798
799 /* poll for SPI completion before start */
800 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
801 cpu_relax();
802
803 /* dirty hack for autobuffer DMA mode */
804 if (drv_data->tx_dma == 0xFFFF) {
805 dev_dbg(&drv_data->pdev->dev,
806 "doing autobuffer DMA out.\n");
807
808 /* no irq in autobuffer mode */
809 dma_config =
810 (DMAFLOW_AUTO | RESTART | dma_width | DI_EN);
811 set_dma_config(drv_data->dma_channel, dma_config);
812 set_dma_start_addr(drv_data->dma_channel,
813 (unsigned long)drv_data->tx);
814 enable_dma(drv_data->dma_channel);
815
816 /* start SPI transfer */
817 write_CTRL(drv_data, cr | BIT_CTL_TIMOD_DMA_TX);
818
819 /* just return here, there can only be one transfer
820 * in this mode
821 */
822 message->status = 0;
823 bfin_spi_giveback(drv_data);
824 return;
825 }
826
827 /* In dma mode, rx or tx must be NULL in one transfer */
828 dma_config = (RESTART | dma_width | DI_EN);
829 if (drv_data->rx != NULL) {
830 /* set transfer mode, and enable SPI */
831 dev_dbg(&drv_data->pdev->dev, "doing DMA in to %p (size %zx)\n",
832 drv_data->rx, drv_data->len_in_bytes);
833
834 /* invalidate caches, if needed */
835 if (bfin_addr_dcachable((unsigned long) drv_data->rx))
836 invalidate_dcache_range((unsigned long) drv_data->rx,
837 (unsigned long) (drv_data->rx +
838 drv_data->len_in_bytes));
839
840 /* clear tx reg soformer data is not shifted out */
841 write_TDBR(drv_data, 0xFFFF);
842
843 dma_config |= WNR;
844 dma_start_addr = (unsigned long)drv_data->rx;
845 cr |= BIT_CTL_TIMOD_DMA_RX | BIT_CTL_SENDOPT;
846
847 } else if (drv_data->tx != NULL) {
848 dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n");
849
850 /* flush caches, if needed */
851 if (bfin_addr_dcachable((unsigned long) drv_data->tx))
852 flush_dcache_range((unsigned long) drv_data->tx,
853 (unsigned long) (drv_data->tx +
854 drv_data->len_in_bytes));
855
856 dma_start_addr = (unsigned long)drv_data->tx;
857 cr |= BIT_CTL_TIMOD_DMA_TX;
858
859 } else
860 BUG();
861
862 /* oh man, here there be monsters ... and i dont mean the
863 * fluffy cute ones from pixar, i mean the kind that'll eat
864 * your data, kick your dog, and love it all. do *not* try
865 * and change these lines unless you (1) heavily test DMA
866 * with SPI flashes on a loaded system (e.g. ping floods),
867 * (2) know just how broken the DMA engine interaction with
868 * the SPI peripheral is, and (3) have someone else to blame
869 * when you screw it all up anyways.
870 */
871 set_dma_start_addr(drv_data->dma_channel, dma_start_addr);
872 set_dma_config(drv_data->dma_channel, dma_config);
873 local_irq_save(flags);
874 SSYNC();
875 write_CTRL(drv_data, cr);
876 enable_dma(drv_data->dma_channel);
877 dma_enable_irq(drv_data->dma_channel);
878 local_irq_restore(flags);
879
880 } else {
881 /* IO mode write then read */
882 dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n");
883
884 if (full_duplex) {
885 /* full duplex mode */
886 BUG_ON((drv_data->tx_end - drv_data->tx) !=
887 (drv_data->rx_end - drv_data->rx));
888 dev_dbg(&drv_data->pdev->dev,
889 "IO duplex: cr is 0x%x\n", cr);
890
891 /* set SPI transfer mode */
892 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
893
894 drv_data->duplex(drv_data);
895
896 if (drv_data->tx != drv_data->tx_end)
897 tranf_success = 0;
898 } else if (drv_data->tx != NULL) {
899 /* write only half duplex */
900 dev_dbg(&drv_data->pdev->dev,
901 "IO write: cr is 0x%x\n", cr);
902
903 /* set SPI transfer mode */
904 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
905
906 drv_data->write(drv_data);
907
908 if (drv_data->tx != drv_data->tx_end)
909 tranf_success = 0;
910 } else if (drv_data->rx != NULL) {
911 /* read only half duplex */
912 dev_dbg(&drv_data->pdev->dev,
913 "IO read: cr is 0x%x\n", cr);
914
915 /* set SPI transfer mode */
916 write_CTRL(drv_data, (cr | CFG_SPI_READ));
917
918 drv_data->read(drv_data);
919 if (drv_data->rx != drv_data->rx_end)
920 tranf_success = 0;
921 }
922
923 if (!tranf_success) {
924 dev_dbg(&drv_data->pdev->dev,
925 "IO write error!\n");
926 message->state = ERROR_STATE;
927 } else {
928 /* Update total byte transfered */
929 message->actual_length += drv_data->len_in_bytes;
930 /* Move to next transfer of this msg */
931 message->state = bfin_spi_next_transfer(drv_data);
932 if (drv_data->cs_change)
933 bfin_spi_cs_deactive(drv_data, chip);
934 }
935 /* Schedule next transfer tasklet */
936 tasklet_schedule(&drv_data->pump_transfers);
937
938 }
939}
940
941/* pop a msg from queue and kick off real transfer */
942static void bfin_spi_pump_messages(struct work_struct *work)
943{
944 struct driver_data *drv_data;
945 unsigned long flags;
946
947 drv_data = container_of(work, struct driver_data, pump_messages);
948
949 /* Lock queue and check for queue work */
950 spin_lock_irqsave(&drv_data->lock, flags);
951 if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
952 /* pumper kicked off but no work to do */
953 drv_data->busy = 0;
954 spin_unlock_irqrestore(&drv_data->lock, flags);
955 return;
956 }
957
958 /* Make sure we are not already running a message */
959 if (drv_data->cur_msg) {
960 spin_unlock_irqrestore(&drv_data->lock, flags);
961 return;
962 }
963
964 /* Extract head of queue */
965 drv_data->cur_msg = list_entry(drv_data->queue.next,
966 struct spi_message, queue);
967
968 /* Setup the SSP using the per chip configuration */
969 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
970 bfin_spi_restore_state(drv_data);
971
972 list_del_init(&drv_data->cur_msg->queue);
973
974 /* Initial message state */
975 drv_data->cur_msg->state = START_STATE;
976 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
977 struct spi_transfer, transfer_list);
978
979 dev_dbg(&drv_data->pdev->dev, "got a message to pump, "
980 "state is set to: baud %d, flag 0x%x, ctl 0x%x\n",
981 drv_data->cur_chip->baud, drv_data->cur_chip->flag,
982 drv_data->cur_chip->ctl_reg);
983
984 dev_dbg(&drv_data->pdev->dev,
985 "the first transfer len is %d\n",
986 drv_data->cur_transfer->len);
987
988 /* Mark as busy and launch transfers */
989 tasklet_schedule(&drv_data->pump_transfers);
990
991 drv_data->busy = 1;
992 spin_unlock_irqrestore(&drv_data->lock, flags);
993}
994
995/*
996 * got a msg to transfer, queue it in drv_data->queue.
997 * And kick off message pumper
998 */
999static int bfin_spi_transfer(struct spi_device *spi, struct spi_message *msg)
1000{
1001 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1002 unsigned long flags;
1003
1004 spin_lock_irqsave(&drv_data->lock, flags);
1005
1006 if (drv_data->run == QUEUE_STOPPED) {
1007 spin_unlock_irqrestore(&drv_data->lock, flags);
1008 return -ESHUTDOWN;
1009 }
1010
1011 msg->actual_length = 0;
1012 msg->status = -EINPROGRESS;
1013 msg->state = START_STATE;
1014
1015 dev_dbg(&spi->dev, "adding an msg in transfer() \n");
1016 list_add_tail(&msg->queue, &drv_data->queue);
1017
1018 if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
1019 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1020
1021 spin_unlock_irqrestore(&drv_data->lock, flags);
1022
1023 return 0;
1024}
1025
1026#define MAX_SPI_SSEL 7
1027
1028static u16 ssel[][MAX_SPI_SSEL] = {
1029 {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3,
1030 P_SPI0_SSEL4, P_SPI0_SSEL5,
1031 P_SPI0_SSEL6, P_SPI0_SSEL7},
1032
1033 {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3,
1034 P_SPI1_SSEL4, P_SPI1_SSEL5,
1035 P_SPI1_SSEL6, P_SPI1_SSEL7},
1036
1037 {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3,
1038 P_SPI2_SSEL4, P_SPI2_SSEL5,
1039 P_SPI2_SSEL6, P_SPI2_SSEL7},
1040};
1041
1042/* first setup for new devices */
1043static int bfin_spi_setup(struct spi_device *spi)
1044{
1045 struct bfin5xx_spi_chip *chip_info = NULL;
1046 struct chip_data *chip;
1047 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1048 int ret;
1049
1050 /* Abort device setup if requested features are not supported */
1051 if (spi->mode & ~(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST)) {
1052 dev_err(&spi->dev, "requested mode not fully supported\n");
1053 return -EINVAL;
1054 }
1055
1056 /* Zero (the default) here means 8 bits */
1057 if (!spi->bits_per_word)
1058 spi->bits_per_word = 8;
1059
1060 if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
1061 return -EINVAL;
1062
1063 /* Only alloc (or use chip_info) on first setup */
1064 chip = spi_get_ctldata(spi);
1065 if (chip == NULL) {
1066 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1067 if (!chip)
1068 return -ENOMEM;
1069
1070 chip->enable_dma = 0;
1071 chip_info = spi->controller_data;
1072 }
1073
1074 /* chip_info isn't always needed */
1075 if (chip_info) {
1076 /* Make sure people stop trying to set fields via ctl_reg
1077 * when they should actually be using common SPI framework.
1078 * Currently we let through: WOM EMISO PSSE GM SZ TIMOD.
1079 * Not sure if a user actually needs/uses any of these,
1080 * but let's assume (for now) they do.
1081 */
1082 if (chip_info->ctl_reg & (SPE|MSTR|CPOL|CPHA|LSBF|SIZE)) {
1083 dev_err(&spi->dev, "do not set bits in ctl_reg "
1084 "that the SPI framework manages\n");
1085 return -EINVAL;
1086 }
1087
1088 chip->enable_dma = chip_info->enable_dma != 0
1089 && drv_data->master_info->enable_dma;
1090 chip->ctl_reg = chip_info->ctl_reg;
1091 chip->bits_per_word = chip_info->bits_per_word;
1092 chip->cs_change_per_word = chip_info->cs_change_per_word;
1093 chip->cs_chg_udelay = chip_info->cs_chg_udelay;
1094 chip->cs_gpio = chip_info->cs_gpio;
1095 }
1096
1097 /* translate common spi framework into our register */
1098 if (spi->mode & SPI_CPOL)
1099 chip->ctl_reg |= CPOL;
1100 if (spi->mode & SPI_CPHA)
1101 chip->ctl_reg |= CPHA;
1102 if (spi->mode & SPI_LSB_FIRST)
1103 chip->ctl_reg |= LSBF;
1104 /* we dont support running in slave mode (yet?) */
1105 chip->ctl_reg |= MSTR;
1106
1107 /*
1108 * if any one SPI chip is registered and wants DMA, request the
1109 * DMA channel for it
1110 */
1111 if (chip->enable_dma && !drv_data->dma_requested) {
1112 /* register dma irq handler */
1113 if (request_dma(drv_data->dma_channel, "BFIN_SPI_DMA") < 0) {
1114 dev_dbg(&spi->dev,
1115 "Unable to request BlackFin SPI DMA channel\n");
1116 return -ENODEV;
1117 }
1118 if (set_dma_callback(drv_data->dma_channel,
1119 bfin_spi_dma_irq_handler, drv_data) < 0) {
1120 dev_dbg(&spi->dev, "Unable to set dma callback\n");
1121 return -EPERM;
1122 }
1123 dma_disable_irq(drv_data->dma_channel);
1124 drv_data->dma_requested = 1;
1125 }
1126
1127 /*
1128 * Notice: for blackfin, the speed_hz is the value of register
1129 * SPI_BAUD, not the real baudrate
1130 */
1131 chip->baud = hz_to_spi_baud(spi->max_speed_hz);
1132 chip->flag = 1 << (spi->chip_select);
1133 chip->chip_select_num = spi->chip_select;
1134
1135 if (chip->chip_select_num == 0) {
1136 ret = gpio_request(chip->cs_gpio, spi->modalias);
1137 if (ret) {
1138 if (drv_data->dma_requested)
1139 free_dma(drv_data->dma_channel);
1140 return ret;
1141 }
1142 gpio_direction_output(chip->cs_gpio, 1);
1143 }
1144
1145 switch (chip->bits_per_word) {
1146 case 8:
1147 chip->n_bytes = 1;
1148 chip->width = CFG_SPI_WORDSIZE8;
1149 chip->read = chip->cs_change_per_word ?
1150 bfin_spi_u8_cs_chg_reader : bfin_spi_u8_reader;
1151 chip->write = chip->cs_change_per_word ?
1152 bfin_spi_u8_cs_chg_writer : bfin_spi_u8_writer;
1153 chip->duplex = chip->cs_change_per_word ?
1154 bfin_spi_u8_cs_chg_duplex : bfin_spi_u8_duplex;
1155 break;
1156
1157 case 16:
1158 chip->n_bytes = 2;
1159 chip->width = CFG_SPI_WORDSIZE16;
1160 chip->read = chip->cs_change_per_word ?
1161 bfin_spi_u16_cs_chg_reader : bfin_spi_u16_reader;
1162 chip->write = chip->cs_change_per_word ?
1163 bfin_spi_u16_cs_chg_writer : bfin_spi_u16_writer;
1164 chip->duplex = chip->cs_change_per_word ?
1165 bfin_spi_u16_cs_chg_duplex : bfin_spi_u16_duplex;
1166 break;
1167
1168 default:
1169 dev_err(&spi->dev, "%d bits_per_word is not supported\n",
1170 chip->bits_per_word);
1171 if (chip_info)
1172 kfree(chip);
1173 return -ENODEV;
1174 }
1175
1176 dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n",
1177 spi->modalias, chip->width, chip->enable_dma);
1178 dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n",
1179 chip->ctl_reg, chip->flag);
1180
1181 spi_set_ctldata(spi, chip);
1182
1183 dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num);
1184 if ((chip->chip_select_num > 0)
1185 && (chip->chip_select_num <= spi->master->num_chipselect))
1186 peripheral_request(ssel[spi->master->bus_num]
1187 [chip->chip_select_num-1], spi->modalias);
1188
1189 bfin_spi_cs_deactive(drv_data, chip);
1190
1191 return 0;
1192}
1193
1194/*
1195 * callback for spi framework.
1196 * clean driver specific data
1197 */
1198static void bfin_spi_cleanup(struct spi_device *spi)
1199{
1200 struct chip_data *chip = spi_get_ctldata(spi);
1201
1202 if (!chip)
1203 return;
1204
1205 if ((chip->chip_select_num > 0)
1206 && (chip->chip_select_num <= spi->master->num_chipselect))
1207 peripheral_free(ssel[spi->master->bus_num]
1208 [chip->chip_select_num-1]);
1209
1210 if (chip->chip_select_num == 0)
1211 gpio_free(chip->cs_gpio);
1212
1213 kfree(chip);
1214}
1215
1216static inline int bfin_spi_init_queue(struct driver_data *drv_data)
1217{
1218 INIT_LIST_HEAD(&drv_data->queue);
1219 spin_lock_init(&drv_data->lock);
1220
1221 drv_data->run = QUEUE_STOPPED;
1222 drv_data->busy = 0;
1223
1224 /* init transfer tasklet */
1225 tasklet_init(&drv_data->pump_transfers,
1226 bfin_spi_pump_transfers, (unsigned long)drv_data);
1227
1228 /* init messages workqueue */
1229 INIT_WORK(&drv_data->pump_messages, bfin_spi_pump_messages);
1230 drv_data->workqueue = create_singlethread_workqueue(
1231 dev_name(drv_data->master->dev.parent));
1232 if (drv_data->workqueue == NULL)
1233 return -EBUSY;
1234
1235 return 0;
1236}
1237
1238static inline int bfin_spi_start_queue(struct driver_data *drv_data)
1239{
1240 unsigned long flags;
1241
1242 spin_lock_irqsave(&drv_data->lock, flags);
1243
1244 if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1245 spin_unlock_irqrestore(&drv_data->lock, flags);
1246 return -EBUSY;
1247 }
1248
1249 drv_data->run = QUEUE_RUNNING;
1250 drv_data->cur_msg = NULL;
1251 drv_data->cur_transfer = NULL;
1252 drv_data->cur_chip = NULL;
1253 spin_unlock_irqrestore(&drv_data->lock, flags);
1254
1255 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1256
1257 return 0;
1258}
1259
1260static inline int bfin_spi_stop_queue(struct driver_data *drv_data)
1261{
1262 unsigned long flags;
1263 unsigned limit = 500;
1264 int status = 0;
1265
1266 spin_lock_irqsave(&drv_data->lock, flags);
1267
1268 /*
1269 * This is a bit lame, but is optimized for the common execution path.
1270 * A wait_queue on the drv_data->busy could be used, but then the common
1271 * execution path (pump_messages) would be required to call wake_up or
1272 * friends on every SPI message. Do this instead
1273 */
1274 drv_data->run = QUEUE_STOPPED;
1275 while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1276 spin_unlock_irqrestore(&drv_data->lock, flags);
1277 msleep(10);
1278 spin_lock_irqsave(&drv_data->lock, flags);
1279 }
1280
1281 if (!list_empty(&drv_data->queue) || drv_data->busy)
1282 status = -EBUSY;
1283
1284 spin_unlock_irqrestore(&drv_data->lock, flags);
1285
1286 return status;
1287}
1288
1289static inline int bfin_spi_destroy_queue(struct driver_data *drv_data)
1290{
1291 int status;
1292
1293 status = bfin_spi_stop_queue(drv_data);
1294 if (status != 0)
1295 return status;
1296
1297 destroy_workqueue(drv_data->workqueue);
1298
1299 return 0;
1300}
1301
1302static int __init bfin_spi_probe(struct platform_device *pdev)
1303{
1304 struct device *dev = &pdev->dev;
1305 struct bfin5xx_spi_master *platform_info;
1306 struct spi_master *master;
1307 struct driver_data *drv_data = 0;
1308 struct resource *res;
1309 int status = 0;
1310
1311 platform_info = dev->platform_data;
1312
1313 /* Allocate master with space for drv_data */
1314 master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1315 if (!master) {
1316 dev_err(&pdev->dev, "can not alloc spi_master\n");
1317 return -ENOMEM;
1318 }
1319
1320 drv_data = spi_master_get_devdata(master);
1321 drv_data->master = master;
1322 drv_data->master_info = platform_info;
1323 drv_data->pdev = pdev;
1324 drv_data->pin_req = platform_info->pin_req;
1325
1326 master->bus_num = pdev->id;
1327 master->num_chipselect = platform_info->num_chipselect;
1328 master->cleanup = bfin_spi_cleanup;
1329 master->setup = bfin_spi_setup;
1330 master->transfer = bfin_spi_transfer;
1331
1332 /* Find and map our resources */
1333 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1334 if (res == NULL) {
1335 dev_err(dev, "Cannot get IORESOURCE_MEM\n");
1336 status = -ENOENT;
1337 goto out_error_get_res;
1338 }
1339
1340 drv_data->regs_base = ioremap(res->start, (res->end - res->start + 1));
1341 if (drv_data->regs_base == NULL) {
1342 dev_err(dev, "Cannot map IO\n");
1343 status = -ENXIO;
1344 goto out_error_ioremap;
1345 }
1346
1347 drv_data->dma_channel = platform_get_irq(pdev, 0);
1348 if (drv_data->dma_channel < 0) {
1349 dev_err(dev, "No DMA channel specified\n");
1350 status = -ENOENT;
1351 goto out_error_no_dma_ch;
1352 }
1353
1354 /* Initial and start queue */
1355 status = bfin_spi_init_queue(drv_data);
1356 if (status != 0) {
1357 dev_err(dev, "problem initializing queue\n");
1358 goto out_error_queue_alloc;
1359 }
1360
1361 status = bfin_spi_start_queue(drv_data);
1362 if (status != 0) {
1363 dev_err(dev, "problem starting queue\n");
1364 goto out_error_queue_alloc;
1365 }
1366
1367 status = peripheral_request_list(drv_data->pin_req, DRV_NAME);
1368 if (status != 0) {
1369 dev_err(&pdev->dev, ": Requesting Peripherals failed\n");
1370 goto out_error_queue_alloc;
1371 }
1372
1373 /* Register with the SPI framework */
1374 platform_set_drvdata(pdev, drv_data);
1375 status = spi_register_master(master);
1376 if (status != 0) {
1377 dev_err(dev, "problem registering spi master\n");
1378 goto out_error_queue_alloc;
1379 }
1380
1381 dev_info(dev, "%s, Version %s, regs_base@%p, dma channel@%d\n",
1382 DRV_DESC, DRV_VERSION, drv_data->regs_base,
1383 drv_data->dma_channel);
1384 return status;
1385
1386out_error_queue_alloc:
1387 bfin_spi_destroy_queue(drv_data);
1388out_error_no_dma_ch:
1389 iounmap((void *) drv_data->regs_base);
1390out_error_ioremap:
1391out_error_get_res:
1392 spi_master_put(master);
1393
1394 return status;
1395}
1396
1397/* stop hardware and remove the driver */
1398static int __devexit bfin_spi_remove(struct platform_device *pdev)
1399{
1400 struct driver_data *drv_data = platform_get_drvdata(pdev);
1401 int status = 0;
1402
1403 if (!drv_data)
1404 return 0;
1405
1406 /* Remove the queue */
1407 status = bfin_spi_destroy_queue(drv_data);
1408 if (status != 0)
1409 return status;
1410
1411 /* Disable the SSP at the peripheral and SOC level */
1412 bfin_spi_disable(drv_data);
1413
1414 /* Release DMA */
1415 if (drv_data->master_info->enable_dma) {
1416 if (dma_channel_active(drv_data->dma_channel))
1417 free_dma(drv_data->dma_channel);
1418 }
1419
1420 /* Disconnect from the SPI framework */
1421 spi_unregister_master(drv_data->master);
1422
1423 peripheral_free_list(drv_data->pin_req);
1424
1425 /* Prevent double remove */
1426 platform_set_drvdata(pdev, NULL);
1427
1428 return 0;
1429}
1430
1431#ifdef CONFIG_PM
1432static int bfin_spi_suspend(struct platform_device *pdev, pm_message_t state)
1433{
1434 struct driver_data *drv_data = platform_get_drvdata(pdev);
1435 int status = 0;
1436
1437 status = bfin_spi_stop_queue(drv_data);
1438 if (status != 0)
1439 return status;
1440
1441 /* stop hardware */
1442 bfin_spi_disable(drv_data);
1443
1444 return 0;
1445}
1446
1447static int bfin_spi_resume(struct platform_device *pdev)
1448{
1449 struct driver_data *drv_data = platform_get_drvdata(pdev);
1450 int status = 0;
1451
1452 /* Enable the SPI interface */
1453 bfin_spi_enable(drv_data);
1454
1455 /* Start the queue running */
1456 status = bfin_spi_start_queue(drv_data);
1457 if (status != 0) {
1458 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1459 return status;
1460 }
1461
1462 return 0;
1463}
1464#else
1465#define bfin_spi_suspend NULL
1466#define bfin_spi_resume NULL
1467#endif /* CONFIG_PM */
1468
1469MODULE_ALIAS("platform:bfin-spi");
1470static struct platform_driver bfin_spi_driver = {
1471 .driver = {
1472 .name = DRV_NAME,
1473 .owner = THIS_MODULE,
1474 },
1475 .suspend = bfin_spi_suspend,
1476 .resume = bfin_spi_resume,
1477 .remove = __devexit_p(bfin_spi_remove),
1478};
1479
1480static int __init bfin_spi_init(void)
1481{
1482 return platform_driver_probe(&bfin_spi_driver, bfin_spi_probe);
1483}
1484module_init(bfin_spi_init);
1485
1486static void __exit bfin_spi_exit(void)
1487{
1488 platform_driver_unregister(&bfin_spi_driver);
1489}
1490module_exit(bfin_spi_exit);
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