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1 | /** | |
2 | * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link | |
3 | * | |
4 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com | |
5 | * | |
6 | * Authors: Felipe Balbi <balbi@ti.com>, | |
7 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
8 | * | |
9 | * This program is free software: you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 of | |
11 | * the License as published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | */ | |
18 | ||
19 | #include <linux/kernel.h> | |
20 | #include <linux/delay.h> | |
21 | #include <linux/slab.h> | |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/platform_device.h> | |
24 | #include <linux/pm_runtime.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/io.h> | |
27 | #include <linux/list.h> | |
28 | #include <linux/dma-mapping.h> | |
29 | ||
30 | #include <linux/usb/ch9.h> | |
31 | #include <linux/usb/gadget.h> | |
32 | ||
33 | #include "debug.h" | |
34 | #include "core.h" | |
35 | #include "gadget.h" | |
36 | #include "io.h" | |
37 | ||
38 | /** | |
39 | * dwc3_gadget_set_test_mode - Enables USB2 Test Modes | |
40 | * @dwc: pointer to our context structure | |
41 | * @mode: the mode to set (J, K SE0 NAK, Force Enable) | |
42 | * | |
43 | * Caller should take care of locking. This function will | |
44 | * return 0 on success or -EINVAL if wrong Test Selector | |
45 | * is passed | |
46 | */ | |
47 | int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) | |
48 | { | |
49 | u32 reg; | |
50 | ||
51 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
52 | reg &= ~DWC3_DCTL_TSTCTRL_MASK; | |
53 | ||
54 | switch (mode) { | |
55 | case TEST_J: | |
56 | case TEST_K: | |
57 | case TEST_SE0_NAK: | |
58 | case TEST_PACKET: | |
59 | case TEST_FORCE_EN: | |
60 | reg |= mode << 1; | |
61 | break; | |
62 | default: | |
63 | return -EINVAL; | |
64 | } | |
65 | ||
66 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
67 | ||
68 | return 0; | |
69 | } | |
70 | ||
71 | /** | |
72 | * dwc3_gadget_get_link_state - Gets current state of USB Link | |
73 | * @dwc: pointer to our context structure | |
74 | * | |
75 | * Caller should take care of locking. This function will | |
76 | * return the link state on success (>= 0) or -ETIMEDOUT. | |
77 | */ | |
78 | int dwc3_gadget_get_link_state(struct dwc3 *dwc) | |
79 | { | |
80 | u32 reg; | |
81 | ||
82 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
83 | ||
84 | return DWC3_DSTS_USBLNKST(reg); | |
85 | } | |
86 | ||
87 | /** | |
88 | * dwc3_gadget_set_link_state - Sets USB Link to a particular State | |
89 | * @dwc: pointer to our context structure | |
90 | * @state: the state to put link into | |
91 | * | |
92 | * Caller should take care of locking. This function will | |
93 | * return 0 on success or -ETIMEDOUT. | |
94 | */ | |
95 | int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state) | |
96 | { | |
97 | int retries = 10000; | |
98 | u32 reg; | |
99 | ||
100 | /* | |
101 | * Wait until device controller is ready. Only applies to 1.94a and | |
102 | * later RTL. | |
103 | */ | |
104 | if (dwc->revision >= DWC3_REVISION_194A) { | |
105 | while (--retries) { | |
106 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
107 | if (reg & DWC3_DSTS_DCNRD) | |
108 | udelay(5); | |
109 | else | |
110 | break; | |
111 | } | |
112 | ||
113 | if (retries <= 0) | |
114 | return -ETIMEDOUT; | |
115 | } | |
116 | ||
117 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
118 | reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; | |
119 | ||
120 | /* set requested state */ | |
121 | reg |= DWC3_DCTL_ULSTCHNGREQ(state); | |
122 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
123 | ||
124 | /* | |
125 | * The following code is racy when called from dwc3_gadget_wakeup, | |
126 | * and is not needed, at least on newer versions | |
127 | */ | |
128 | if (dwc->revision >= DWC3_REVISION_194A) | |
129 | return 0; | |
130 | ||
131 | /* wait for a change in DSTS */ | |
132 | retries = 10000; | |
133 | while (--retries) { | |
134 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
135 | ||
136 | if (DWC3_DSTS_USBLNKST(reg) == state) | |
137 | return 0; | |
138 | ||
139 | udelay(5); | |
140 | } | |
141 | ||
142 | dwc3_trace(trace_dwc3_gadget, | |
143 | "link state change request timed out"); | |
144 | ||
145 | return -ETIMEDOUT; | |
146 | } | |
147 | ||
148 | /** | |
149 | * dwc3_ep_inc_trb() - Increment a TRB index. | |
150 | * @index - Pointer to the TRB index to increment. | |
151 | * | |
152 | * The index should never point to the link TRB. After incrementing, | |
153 | * if it is point to the link TRB, wrap around to the beginning. The | |
154 | * link TRB is always at the last TRB entry. | |
155 | */ | |
156 | static void dwc3_ep_inc_trb(u8 *index) | |
157 | { | |
158 | (*index)++; | |
159 | if (*index == (DWC3_TRB_NUM - 1)) | |
160 | *index = 0; | |
161 | } | |
162 | ||
163 | static void dwc3_ep_inc_enq(struct dwc3_ep *dep) | |
164 | { | |
165 | dwc3_ep_inc_trb(&dep->trb_enqueue); | |
166 | } | |
167 | ||
168 | static void dwc3_ep_inc_deq(struct dwc3_ep *dep) | |
169 | { | |
170 | dwc3_ep_inc_trb(&dep->trb_dequeue); | |
171 | } | |
172 | ||
173 | void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req, | |
174 | int status) | |
175 | { | |
176 | struct dwc3 *dwc = dep->dwc; | |
177 | ||
178 | req->started = false; | |
179 | list_del(&req->list); | |
180 | req->trb = NULL; | |
181 | ||
182 | if (req->request.status == -EINPROGRESS) | |
183 | req->request.status = status; | |
184 | ||
185 | if (dwc->ep0_bounced && dep->number == 0) | |
186 | dwc->ep0_bounced = false; | |
187 | else | |
188 | usb_gadget_unmap_request(&dwc->gadget, &req->request, | |
189 | req->direction); | |
190 | ||
191 | trace_dwc3_gadget_giveback(req); | |
192 | ||
193 | spin_unlock(&dwc->lock); | |
194 | usb_gadget_giveback_request(&dep->endpoint, &req->request); | |
195 | spin_lock(&dwc->lock); | |
196 | ||
197 | if (dep->number > 1) | |
198 | pm_runtime_put(dwc->dev); | |
199 | } | |
200 | ||
201 | int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param) | |
202 | { | |
203 | u32 timeout = 500; | |
204 | int status = 0; | |
205 | int ret = 0; | |
206 | u32 reg; | |
207 | ||
208 | dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param); | |
209 | dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT); | |
210 | ||
211 | do { | |
212 | reg = dwc3_readl(dwc->regs, DWC3_DGCMD); | |
213 | if (!(reg & DWC3_DGCMD_CMDACT)) { | |
214 | status = DWC3_DGCMD_STATUS(reg); | |
215 | if (status) | |
216 | ret = -EINVAL; | |
217 | break; | |
218 | } | |
219 | } while (timeout--); | |
220 | ||
221 | if (!timeout) { | |
222 | ret = -ETIMEDOUT; | |
223 | status = -ETIMEDOUT; | |
224 | } | |
225 | ||
226 | trace_dwc3_gadget_generic_cmd(cmd, param, status); | |
227 | ||
228 | return ret; | |
229 | } | |
230 | ||
231 | static int __dwc3_gadget_wakeup(struct dwc3 *dwc); | |
232 | ||
233 | int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd, | |
234 | struct dwc3_gadget_ep_cmd_params *params) | |
235 | { | |
236 | struct dwc3 *dwc = dep->dwc; | |
237 | u32 timeout = 500; | |
238 | u32 reg; | |
239 | ||
240 | int cmd_status = 0; | |
241 | int susphy = false; | |
242 | int ret = -EINVAL; | |
243 | ||
244 | /* | |
245 | * Synopsys Databook 2.60a states, on section 6.3.2.5.[1-8], that if | |
246 | * we're issuing an endpoint command, we must check if | |
247 | * GUSB2PHYCFG.SUSPHY bit is set. If it is, then we need to clear it. | |
248 | * | |
249 | * We will also set SUSPHY bit to what it was before returning as stated | |
250 | * by the same section on Synopsys databook. | |
251 | */ | |
252 | if (dwc->gadget.speed <= USB_SPEED_HIGH) { | |
253 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); | |
254 | if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) { | |
255 | susphy = true; | |
256 | reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; | |
257 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); | |
258 | } | |
259 | } | |
260 | ||
261 | if (cmd == DWC3_DEPCMD_STARTTRANSFER) { | |
262 | int needs_wakeup; | |
263 | ||
264 | needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 || | |
265 | dwc->link_state == DWC3_LINK_STATE_U2 || | |
266 | dwc->link_state == DWC3_LINK_STATE_U3); | |
267 | ||
268 | if (unlikely(needs_wakeup)) { | |
269 | ret = __dwc3_gadget_wakeup(dwc); | |
270 | dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n", | |
271 | ret); | |
272 | } | |
273 | } | |
274 | ||
275 | dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0); | |
276 | dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1); | |
277 | dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2); | |
278 | ||
279 | dwc3_writel(dep->regs, DWC3_DEPCMD, cmd | DWC3_DEPCMD_CMDACT); | |
280 | do { | |
281 | reg = dwc3_readl(dep->regs, DWC3_DEPCMD); | |
282 | if (!(reg & DWC3_DEPCMD_CMDACT)) { | |
283 | cmd_status = DWC3_DEPCMD_STATUS(reg); | |
284 | ||
285 | switch (cmd_status) { | |
286 | case 0: | |
287 | ret = 0; | |
288 | break; | |
289 | case DEPEVT_TRANSFER_NO_RESOURCE: | |
290 | ret = -EINVAL; | |
291 | break; | |
292 | case DEPEVT_TRANSFER_BUS_EXPIRY: | |
293 | /* | |
294 | * SW issues START TRANSFER command to | |
295 | * isochronous ep with future frame interval. If | |
296 | * future interval time has already passed when | |
297 | * core receives the command, it will respond | |
298 | * with an error status of 'Bus Expiry'. | |
299 | * | |
300 | * Instead of always returning -EINVAL, let's | |
301 | * give a hint to the gadget driver that this is | |
302 | * the case by returning -EAGAIN. | |
303 | */ | |
304 | ret = -EAGAIN; | |
305 | break; | |
306 | default: | |
307 | dev_WARN(dwc->dev, "UNKNOWN cmd status\n"); | |
308 | } | |
309 | ||
310 | break; | |
311 | } | |
312 | } while (--timeout); | |
313 | ||
314 | if (timeout == 0) { | |
315 | ret = -ETIMEDOUT; | |
316 | cmd_status = -ETIMEDOUT; | |
317 | } | |
318 | ||
319 | trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status); | |
320 | ||
321 | if (unlikely(susphy)) { | |
322 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); | |
323 | reg |= DWC3_GUSB2PHYCFG_SUSPHY; | |
324 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); | |
325 | } | |
326 | ||
327 | return ret; | |
328 | } | |
329 | ||
330 | static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep) | |
331 | { | |
332 | struct dwc3 *dwc = dep->dwc; | |
333 | struct dwc3_gadget_ep_cmd_params params; | |
334 | u32 cmd = DWC3_DEPCMD_CLEARSTALL; | |
335 | ||
336 | /* | |
337 | * As of core revision 2.60a the recommended programming model | |
338 | * is to set the ClearPendIN bit when issuing a Clear Stall EP | |
339 | * command for IN endpoints. This is to prevent an issue where | |
340 | * some (non-compliant) hosts may not send ACK TPs for pending | |
341 | * IN transfers due to a mishandled error condition. Synopsys | |
342 | * STAR 9000614252. | |
343 | */ | |
344 | if (dep->direction && (dwc->revision >= DWC3_REVISION_260A)) | |
345 | cmd |= DWC3_DEPCMD_CLEARPENDIN; | |
346 | ||
347 | memset(¶ms, 0, sizeof(params)); | |
348 | ||
349 | return dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); | |
350 | } | |
351 | ||
352 | static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep, | |
353 | struct dwc3_trb *trb) | |
354 | { | |
355 | u32 offset = (char *) trb - (char *) dep->trb_pool; | |
356 | ||
357 | return dep->trb_pool_dma + offset; | |
358 | } | |
359 | ||
360 | static int dwc3_alloc_trb_pool(struct dwc3_ep *dep) | |
361 | { | |
362 | struct dwc3 *dwc = dep->dwc; | |
363 | ||
364 | if (dep->trb_pool) | |
365 | return 0; | |
366 | ||
367 | dep->trb_pool = dma_alloc_coherent(dwc->dev, | |
368 | sizeof(struct dwc3_trb) * DWC3_TRB_NUM, | |
369 | &dep->trb_pool_dma, GFP_KERNEL); | |
370 | if (!dep->trb_pool) { | |
371 | dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n", | |
372 | dep->name); | |
373 | return -ENOMEM; | |
374 | } | |
375 | ||
376 | return 0; | |
377 | } | |
378 | ||
379 | static void dwc3_free_trb_pool(struct dwc3_ep *dep) | |
380 | { | |
381 | struct dwc3 *dwc = dep->dwc; | |
382 | ||
383 | dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM, | |
384 | dep->trb_pool, dep->trb_pool_dma); | |
385 | ||
386 | dep->trb_pool = NULL; | |
387 | dep->trb_pool_dma = 0; | |
388 | } | |
389 | ||
390 | static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep); | |
391 | ||
392 | /** | |
393 | * dwc3_gadget_start_config - Configure EP resources | |
394 | * @dwc: pointer to our controller context structure | |
395 | * @dep: endpoint that is being enabled | |
396 | * | |
397 | * The assignment of transfer resources cannot perfectly follow the | |
398 | * data book due to the fact that the controller driver does not have | |
399 | * all knowledge of the configuration in advance. It is given this | |
400 | * information piecemeal by the composite gadget framework after every | |
401 | * SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook | |
402 | * programming model in this scenario can cause errors. For two | |
403 | * reasons: | |
404 | * | |
405 | * 1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION | |
406 | * and SET_INTERFACE (8.1.5). This is incorrect in the scenario of | |
407 | * multiple interfaces. | |
408 | * | |
409 | * 2) The databook does not mention doing more DEPXFERCFG for new | |
410 | * endpoint on alt setting (8.1.6). | |
411 | * | |
412 | * The following simplified method is used instead: | |
413 | * | |
414 | * All hardware endpoints can be assigned a transfer resource and this | |
415 | * setting will stay persistent until either a core reset or | |
416 | * hibernation. So whenever we do a DEPSTARTCFG(0) we can go ahead and | |
417 | * do DEPXFERCFG for every hardware endpoint as well. We are | |
418 | * guaranteed that there are as many transfer resources as endpoints. | |
419 | * | |
420 | * This function is called for each endpoint when it is being enabled | |
421 | * but is triggered only when called for EP0-out, which always happens | |
422 | * first, and which should only happen in one of the above conditions. | |
423 | */ | |
424 | static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep) | |
425 | { | |
426 | struct dwc3_gadget_ep_cmd_params params; | |
427 | u32 cmd; | |
428 | int i; | |
429 | int ret; | |
430 | ||
431 | if (dep->number) | |
432 | return 0; | |
433 | ||
434 | memset(¶ms, 0x00, sizeof(params)); | |
435 | cmd = DWC3_DEPCMD_DEPSTARTCFG; | |
436 | ||
437 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); | |
438 | if (ret) | |
439 | return ret; | |
440 | ||
441 | for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) { | |
442 | struct dwc3_ep *dep = dwc->eps[i]; | |
443 | ||
444 | if (!dep) | |
445 | continue; | |
446 | ||
447 | ret = dwc3_gadget_set_xfer_resource(dwc, dep); | |
448 | if (ret) | |
449 | return ret; | |
450 | } | |
451 | ||
452 | return 0; | |
453 | } | |
454 | ||
455 | static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep, | |
456 | const struct usb_endpoint_descriptor *desc, | |
457 | const struct usb_ss_ep_comp_descriptor *comp_desc, | |
458 | bool modify, bool restore) | |
459 | { | |
460 | struct dwc3_gadget_ep_cmd_params params; | |
461 | ||
462 | if (dev_WARN_ONCE(dwc->dev, modify && restore, | |
463 | "Can't modify and restore\n")) | |
464 | return -EINVAL; | |
465 | ||
466 | memset(¶ms, 0x00, sizeof(params)); | |
467 | ||
468 | params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc)) | |
469 | | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc)); | |
470 | ||
471 | /* Burst size is only needed in SuperSpeed mode */ | |
472 | if (dwc->gadget.speed >= USB_SPEED_SUPER) { | |
473 | u32 burst = dep->endpoint.maxburst; | |
474 | params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1); | |
475 | } | |
476 | ||
477 | if (modify) { | |
478 | params.param0 |= DWC3_DEPCFG_ACTION_MODIFY; | |
479 | } else if (restore) { | |
480 | params.param0 |= DWC3_DEPCFG_ACTION_RESTORE; | |
481 | params.param2 |= dep->saved_state; | |
482 | } else { | |
483 | params.param0 |= DWC3_DEPCFG_ACTION_INIT; | |
484 | } | |
485 | ||
486 | if (usb_endpoint_xfer_control(desc)) | |
487 | params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN; | |
488 | ||
489 | if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc)) | |
490 | params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN; | |
491 | ||
492 | if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) { | |
493 | params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE | |
494 | | DWC3_DEPCFG_STREAM_EVENT_EN; | |
495 | dep->stream_capable = true; | |
496 | } | |
497 | ||
498 | if (!usb_endpoint_xfer_control(desc)) | |
499 | params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN; | |
500 | ||
501 | /* | |
502 | * We are doing 1:1 mapping for endpoints, meaning | |
503 | * Physical Endpoints 2 maps to Logical Endpoint 2 and | |
504 | * so on. We consider the direction bit as part of the physical | |
505 | * endpoint number. So USB endpoint 0x81 is 0x03. | |
506 | */ | |
507 | params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number); | |
508 | ||
509 | /* | |
510 | * We must use the lower 16 TX FIFOs even though | |
511 | * HW might have more | |
512 | */ | |
513 | if (dep->direction) | |
514 | params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1); | |
515 | ||
516 | if (desc->bInterval) { | |
517 | params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1); | |
518 | dep->interval = 1 << (desc->bInterval - 1); | |
519 | } | |
520 | ||
521 | return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, ¶ms); | |
522 | } | |
523 | ||
524 | static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep) | |
525 | { | |
526 | struct dwc3_gadget_ep_cmd_params params; | |
527 | ||
528 | memset(¶ms, 0x00, sizeof(params)); | |
529 | ||
530 | params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1); | |
531 | ||
532 | return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE, | |
533 | ¶ms); | |
534 | } | |
535 | ||
536 | /** | |
537 | * __dwc3_gadget_ep_enable - Initializes a HW endpoint | |
538 | * @dep: endpoint to be initialized | |
539 | * @desc: USB Endpoint Descriptor | |
540 | * | |
541 | * Caller should take care of locking | |
542 | */ | |
543 | static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, | |
544 | const struct usb_endpoint_descriptor *desc, | |
545 | const struct usb_ss_ep_comp_descriptor *comp_desc, | |
546 | bool modify, bool restore) | |
547 | { | |
548 | struct dwc3 *dwc = dep->dwc; | |
549 | u32 reg; | |
550 | int ret; | |
551 | ||
552 | dwc3_trace(trace_dwc3_gadget, "Enabling %s", dep->name); | |
553 | ||
554 | if (!(dep->flags & DWC3_EP_ENABLED)) { | |
555 | ret = dwc3_gadget_start_config(dwc, dep); | |
556 | if (ret) | |
557 | return ret; | |
558 | } | |
559 | ||
560 | ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, modify, | |
561 | restore); | |
562 | if (ret) | |
563 | return ret; | |
564 | ||
565 | if (!(dep->flags & DWC3_EP_ENABLED)) { | |
566 | struct dwc3_trb *trb_st_hw; | |
567 | struct dwc3_trb *trb_link; | |
568 | ||
569 | dep->endpoint.desc = desc; | |
570 | dep->comp_desc = comp_desc; | |
571 | dep->type = usb_endpoint_type(desc); | |
572 | dep->flags |= DWC3_EP_ENABLED; | |
573 | ||
574 | reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); | |
575 | reg |= DWC3_DALEPENA_EP(dep->number); | |
576 | dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); | |
577 | ||
578 | if (usb_endpoint_xfer_control(desc)) | |
579 | return 0; | |
580 | ||
581 | /* Initialize the TRB ring */ | |
582 | dep->trb_dequeue = 0; | |
583 | dep->trb_enqueue = 0; | |
584 | memset(dep->trb_pool, 0, | |
585 | sizeof(struct dwc3_trb) * DWC3_TRB_NUM); | |
586 | ||
587 | /* Link TRB. The HWO bit is never reset */ | |
588 | trb_st_hw = &dep->trb_pool[0]; | |
589 | ||
590 | trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1]; | |
591 | trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); | |
592 | trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); | |
593 | trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB; | |
594 | trb_link->ctrl |= DWC3_TRB_CTRL_HWO; | |
595 | } | |
596 | ||
597 | return 0; | |
598 | } | |
599 | ||
600 | static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force); | |
601 | static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep) | |
602 | { | |
603 | struct dwc3_request *req; | |
604 | ||
605 | dwc3_stop_active_transfer(dwc, dep->number, true); | |
606 | ||
607 | /* - giveback all requests to gadget driver */ | |
608 | while (!list_empty(&dep->started_list)) { | |
609 | req = next_request(&dep->started_list); | |
610 | ||
611 | dwc3_gadget_giveback(dep, req, -ESHUTDOWN); | |
612 | } | |
613 | ||
614 | while (!list_empty(&dep->pending_list)) { | |
615 | req = next_request(&dep->pending_list); | |
616 | ||
617 | dwc3_gadget_giveback(dep, req, -ESHUTDOWN); | |
618 | } | |
619 | } | |
620 | ||
621 | /** | |
622 | * __dwc3_gadget_ep_disable - Disables a HW endpoint | |
623 | * @dep: the endpoint to disable | |
624 | * | |
625 | * This function also removes requests which are currently processed ny the | |
626 | * hardware and those which are not yet scheduled. | |
627 | * Caller should take care of locking. | |
628 | */ | |
629 | static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep) | |
630 | { | |
631 | struct dwc3 *dwc = dep->dwc; | |
632 | u32 reg; | |
633 | ||
634 | dwc3_trace(trace_dwc3_gadget, "Disabling %s", dep->name); | |
635 | ||
636 | dwc3_remove_requests(dwc, dep); | |
637 | ||
638 | /* make sure HW endpoint isn't stalled */ | |
639 | if (dep->flags & DWC3_EP_STALL) | |
640 | __dwc3_gadget_ep_set_halt(dep, 0, false); | |
641 | ||
642 | reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); | |
643 | reg &= ~DWC3_DALEPENA_EP(dep->number); | |
644 | dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); | |
645 | ||
646 | dep->stream_capable = false; | |
647 | dep->endpoint.desc = NULL; | |
648 | dep->comp_desc = NULL; | |
649 | dep->type = 0; | |
650 | dep->flags = 0; | |
651 | ||
652 | return 0; | |
653 | } | |
654 | ||
655 | /* -------------------------------------------------------------------------- */ | |
656 | ||
657 | static int dwc3_gadget_ep0_enable(struct usb_ep *ep, | |
658 | const struct usb_endpoint_descriptor *desc) | |
659 | { | |
660 | return -EINVAL; | |
661 | } | |
662 | ||
663 | static int dwc3_gadget_ep0_disable(struct usb_ep *ep) | |
664 | { | |
665 | return -EINVAL; | |
666 | } | |
667 | ||
668 | /* -------------------------------------------------------------------------- */ | |
669 | ||
670 | static int dwc3_gadget_ep_enable(struct usb_ep *ep, | |
671 | const struct usb_endpoint_descriptor *desc) | |
672 | { | |
673 | struct dwc3_ep *dep; | |
674 | struct dwc3 *dwc; | |
675 | unsigned long flags; | |
676 | int ret; | |
677 | ||
678 | if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) { | |
679 | pr_debug("dwc3: invalid parameters\n"); | |
680 | return -EINVAL; | |
681 | } | |
682 | ||
683 | if (!desc->wMaxPacketSize) { | |
684 | pr_debug("dwc3: missing wMaxPacketSize\n"); | |
685 | return -EINVAL; | |
686 | } | |
687 | ||
688 | dep = to_dwc3_ep(ep); | |
689 | dwc = dep->dwc; | |
690 | ||
691 | if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED, | |
692 | "%s is already enabled\n", | |
693 | dep->name)) | |
694 | return 0; | |
695 | ||
696 | spin_lock_irqsave(&dwc->lock, flags); | |
697 | ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false); | |
698 | spin_unlock_irqrestore(&dwc->lock, flags); | |
699 | ||
700 | return ret; | |
701 | } | |
702 | ||
703 | static int dwc3_gadget_ep_disable(struct usb_ep *ep) | |
704 | { | |
705 | struct dwc3_ep *dep; | |
706 | struct dwc3 *dwc; | |
707 | unsigned long flags; | |
708 | int ret; | |
709 | ||
710 | if (!ep) { | |
711 | pr_debug("dwc3: invalid parameters\n"); | |
712 | return -EINVAL; | |
713 | } | |
714 | ||
715 | dep = to_dwc3_ep(ep); | |
716 | dwc = dep->dwc; | |
717 | ||
718 | if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED), | |
719 | "%s is already disabled\n", | |
720 | dep->name)) | |
721 | return 0; | |
722 | ||
723 | spin_lock_irqsave(&dwc->lock, flags); | |
724 | ret = __dwc3_gadget_ep_disable(dep); | |
725 | spin_unlock_irqrestore(&dwc->lock, flags); | |
726 | ||
727 | return ret; | |
728 | } | |
729 | ||
730 | static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep, | |
731 | gfp_t gfp_flags) | |
732 | { | |
733 | struct dwc3_request *req; | |
734 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
735 | ||
736 | req = kzalloc(sizeof(*req), gfp_flags); | |
737 | if (!req) | |
738 | return NULL; | |
739 | ||
740 | req->epnum = dep->number; | |
741 | req->dep = dep; | |
742 | ||
743 | dep->allocated_requests++; | |
744 | ||
745 | trace_dwc3_alloc_request(req); | |
746 | ||
747 | return &req->request; | |
748 | } | |
749 | ||
750 | static void dwc3_gadget_ep_free_request(struct usb_ep *ep, | |
751 | struct usb_request *request) | |
752 | { | |
753 | struct dwc3_request *req = to_dwc3_request(request); | |
754 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
755 | ||
756 | dep->allocated_requests--; | |
757 | trace_dwc3_free_request(req); | |
758 | kfree(req); | |
759 | } | |
760 | ||
761 | static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep); | |
762 | ||
763 | /** | |
764 | * dwc3_prepare_one_trb - setup one TRB from one request | |
765 | * @dep: endpoint for which this request is prepared | |
766 | * @req: dwc3_request pointer | |
767 | */ | |
768 | static void dwc3_prepare_one_trb(struct dwc3_ep *dep, | |
769 | struct dwc3_request *req, dma_addr_t dma, | |
770 | unsigned length, unsigned chain, unsigned node) | |
771 | { | |
772 | struct dwc3_trb *trb; | |
773 | ||
774 | dwc3_trace(trace_dwc3_gadget, "%s: req %p dma %08llx length %d%s", | |
775 | dep->name, req, (unsigned long long) dma, | |
776 | length, chain ? " chain" : ""); | |
777 | ||
778 | trb = &dep->trb_pool[dep->trb_enqueue]; | |
779 | ||
780 | if (!req->trb) { | |
781 | dwc3_gadget_move_started_request(req); | |
782 | req->trb = trb; | |
783 | req->trb_dma = dwc3_trb_dma_offset(dep, trb); | |
784 | req->first_trb_index = dep->trb_enqueue; | |
785 | } | |
786 | ||
787 | dwc3_ep_inc_enq(dep); | |
788 | ||
789 | trb->size = DWC3_TRB_SIZE_LENGTH(length); | |
790 | trb->bpl = lower_32_bits(dma); | |
791 | trb->bph = upper_32_bits(dma); | |
792 | ||
793 | switch (usb_endpoint_type(dep->endpoint.desc)) { | |
794 | case USB_ENDPOINT_XFER_CONTROL: | |
795 | trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP; | |
796 | break; | |
797 | ||
798 | case USB_ENDPOINT_XFER_ISOC: | |
799 | if (!node) | |
800 | trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST; | |
801 | else | |
802 | trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS; | |
803 | ||
804 | /* always enable Interrupt on Missed ISOC */ | |
805 | trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI; | |
806 | break; | |
807 | ||
808 | case USB_ENDPOINT_XFER_BULK: | |
809 | case USB_ENDPOINT_XFER_INT: | |
810 | trb->ctrl = DWC3_TRBCTL_NORMAL; | |
811 | break; | |
812 | default: | |
813 | /* | |
814 | * This is only possible with faulty memory because we | |
815 | * checked it already :) | |
816 | */ | |
817 | BUG(); | |
818 | } | |
819 | ||
820 | /* always enable Continue on Short Packet */ | |
821 | trb->ctrl |= DWC3_TRB_CTRL_CSP; | |
822 | ||
823 | if ((!req->request.no_interrupt && !chain) || | |
824 | (dwc3_calc_trbs_left(dep) == 0)) | |
825 | trb->ctrl |= DWC3_TRB_CTRL_IOC | DWC3_TRB_CTRL_ISP_IMI; | |
826 | ||
827 | if (chain) | |
828 | trb->ctrl |= DWC3_TRB_CTRL_CHN; | |
829 | ||
830 | if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable) | |
831 | trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id); | |
832 | ||
833 | trb->ctrl |= DWC3_TRB_CTRL_HWO; | |
834 | ||
835 | dep->queued_requests++; | |
836 | ||
837 | trace_dwc3_prepare_trb(dep, trb); | |
838 | } | |
839 | ||
840 | /** | |
841 | * dwc3_ep_prev_trb() - Returns the previous TRB in the ring | |
842 | * @dep: The endpoint with the TRB ring | |
843 | * @index: The index of the current TRB in the ring | |
844 | * | |
845 | * Returns the TRB prior to the one pointed to by the index. If the | |
846 | * index is 0, we will wrap backwards, skip the link TRB, and return | |
847 | * the one just before that. | |
848 | */ | |
849 | static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index) | |
850 | { | |
851 | u8 tmp = index; | |
852 | ||
853 | if (!tmp) | |
854 | tmp = DWC3_TRB_NUM - 1; | |
855 | ||
856 | return &dep->trb_pool[tmp - 1]; | |
857 | } | |
858 | ||
859 | static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep) | |
860 | { | |
861 | struct dwc3_trb *tmp; | |
862 | u8 trbs_left; | |
863 | ||
864 | /* | |
865 | * If enqueue & dequeue are equal than it is either full or empty. | |
866 | * | |
867 | * One way to know for sure is if the TRB right before us has HWO bit | |
868 | * set or not. If it has, then we're definitely full and can't fit any | |
869 | * more transfers in our ring. | |
870 | */ | |
871 | if (dep->trb_enqueue == dep->trb_dequeue) { | |
872 | tmp = dwc3_ep_prev_trb(dep, dep->trb_enqueue); | |
873 | if (tmp->ctrl & DWC3_TRB_CTRL_HWO) | |
874 | return 0; | |
875 | ||
876 | return DWC3_TRB_NUM - 1; | |
877 | } | |
878 | ||
879 | trbs_left = dep->trb_dequeue - dep->trb_enqueue; | |
880 | trbs_left &= (DWC3_TRB_NUM - 1); | |
881 | ||
882 | if (dep->trb_dequeue < dep->trb_enqueue) | |
883 | trbs_left--; | |
884 | ||
885 | return trbs_left; | |
886 | } | |
887 | ||
888 | static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep, | |
889 | struct dwc3_request *req, unsigned int trbs_left) | |
890 | { | |
891 | struct scatterlist *sg = req->sg; | |
892 | struct scatterlist *s; | |
893 | unsigned int length; | |
894 | dma_addr_t dma; | |
895 | int i; | |
896 | ||
897 | for_each_sg(sg, s, req->num_pending_sgs, i) { | |
898 | unsigned chain = true; | |
899 | ||
900 | length = sg_dma_len(s); | |
901 | dma = sg_dma_address(s); | |
902 | ||
903 | if (sg_is_last(s)) | |
904 | chain = false; | |
905 | ||
906 | dwc3_prepare_one_trb(dep, req, dma, length, | |
907 | chain, i); | |
908 | ||
909 | if (!trbs_left--) | |
910 | break; | |
911 | } | |
912 | } | |
913 | ||
914 | static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep, | |
915 | struct dwc3_request *req, unsigned int trbs_left) | |
916 | { | |
917 | unsigned int length; | |
918 | dma_addr_t dma; | |
919 | ||
920 | dma = req->request.dma; | |
921 | length = req->request.length; | |
922 | ||
923 | dwc3_prepare_one_trb(dep, req, dma, length, | |
924 | false, 0); | |
925 | } | |
926 | ||
927 | /* | |
928 | * dwc3_prepare_trbs - setup TRBs from requests | |
929 | * @dep: endpoint for which requests are being prepared | |
930 | * | |
931 | * The function goes through the requests list and sets up TRBs for the | |
932 | * transfers. The function returns once there are no more TRBs available or | |
933 | * it runs out of requests. | |
934 | */ | |
935 | static void dwc3_prepare_trbs(struct dwc3_ep *dep) | |
936 | { | |
937 | struct dwc3_request *req, *n; | |
938 | u32 trbs_left; | |
939 | ||
940 | BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM); | |
941 | ||
942 | trbs_left = dwc3_calc_trbs_left(dep); | |
943 | if (!trbs_left) | |
944 | return; | |
945 | ||
946 | list_for_each_entry_safe(req, n, &dep->pending_list, list) { | |
947 | if (req->num_pending_sgs > 0) | |
948 | dwc3_prepare_one_trb_sg(dep, req, trbs_left--); | |
949 | else | |
950 | dwc3_prepare_one_trb_linear(dep, req, trbs_left--); | |
951 | ||
952 | if (!trbs_left) | |
953 | return; | |
954 | } | |
955 | } | |
956 | ||
957 | static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param) | |
958 | { | |
959 | struct dwc3_gadget_ep_cmd_params params; | |
960 | struct dwc3_request *req; | |
961 | struct dwc3 *dwc = dep->dwc; | |
962 | int starting; | |
963 | int ret; | |
964 | u32 cmd; | |
965 | ||
966 | starting = !(dep->flags & DWC3_EP_BUSY); | |
967 | ||
968 | dwc3_prepare_trbs(dep); | |
969 | req = next_request(&dep->started_list); | |
970 | if (!req) { | |
971 | dep->flags |= DWC3_EP_PENDING_REQUEST; | |
972 | return 0; | |
973 | } | |
974 | ||
975 | memset(¶ms, 0, sizeof(params)); | |
976 | ||
977 | if (starting) { | |
978 | params.param0 = upper_32_bits(req->trb_dma); | |
979 | params.param1 = lower_32_bits(req->trb_dma); | |
980 | cmd = DWC3_DEPCMD_STARTTRANSFER | | |
981 | DWC3_DEPCMD_PARAM(cmd_param); | |
982 | } else { | |
983 | cmd = DWC3_DEPCMD_UPDATETRANSFER | | |
984 | DWC3_DEPCMD_PARAM(dep->resource_index); | |
985 | } | |
986 | ||
987 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); | |
988 | if (ret < 0) { | |
989 | /* | |
990 | * FIXME we need to iterate over the list of requests | |
991 | * here and stop, unmap, free and del each of the linked | |
992 | * requests instead of what we do now. | |
993 | */ | |
994 | usb_gadget_unmap_request(&dwc->gadget, &req->request, | |
995 | req->direction); | |
996 | list_del(&req->list); | |
997 | return ret; | |
998 | } | |
999 | ||
1000 | dep->flags |= DWC3_EP_BUSY; | |
1001 | ||
1002 | if (starting) { | |
1003 | dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep); | |
1004 | WARN_ON_ONCE(!dep->resource_index); | |
1005 | } | |
1006 | ||
1007 | return 0; | |
1008 | } | |
1009 | ||
1010 | static void __dwc3_gadget_start_isoc(struct dwc3 *dwc, | |
1011 | struct dwc3_ep *dep, u32 cur_uf) | |
1012 | { | |
1013 | u32 uf; | |
1014 | ||
1015 | if (list_empty(&dep->pending_list)) { | |
1016 | dwc3_trace(trace_dwc3_gadget, | |
1017 | "ISOC ep %s run out for requests", | |
1018 | dep->name); | |
1019 | dep->flags |= DWC3_EP_PENDING_REQUEST; | |
1020 | return; | |
1021 | } | |
1022 | ||
1023 | /* 4 micro frames in the future */ | |
1024 | uf = cur_uf + dep->interval * 4; | |
1025 | ||
1026 | __dwc3_gadget_kick_transfer(dep, uf); | |
1027 | } | |
1028 | ||
1029 | static void dwc3_gadget_start_isoc(struct dwc3 *dwc, | |
1030 | struct dwc3_ep *dep, const struct dwc3_event_depevt *event) | |
1031 | { | |
1032 | u32 cur_uf, mask; | |
1033 | ||
1034 | mask = ~(dep->interval - 1); | |
1035 | cur_uf = event->parameters & mask; | |
1036 | ||
1037 | __dwc3_gadget_start_isoc(dwc, dep, cur_uf); | |
1038 | } | |
1039 | ||
1040 | static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req) | |
1041 | { | |
1042 | struct dwc3 *dwc = dep->dwc; | |
1043 | int ret; | |
1044 | ||
1045 | if (!dep->endpoint.desc) { | |
1046 | dwc3_trace(trace_dwc3_gadget, | |
1047 | "trying to queue request %p to disabled %s", | |
1048 | &req->request, dep->endpoint.name); | |
1049 | return -ESHUTDOWN; | |
1050 | } | |
1051 | ||
1052 | if (WARN(req->dep != dep, "request %p belongs to '%s'\n", | |
1053 | &req->request, req->dep->name)) { | |
1054 | dwc3_trace(trace_dwc3_gadget, "request %p belongs to '%s'", | |
1055 | &req->request, req->dep->name); | |
1056 | return -EINVAL; | |
1057 | } | |
1058 | ||
1059 | pm_runtime_get(dwc->dev); | |
1060 | ||
1061 | req->request.actual = 0; | |
1062 | req->request.status = -EINPROGRESS; | |
1063 | req->direction = dep->direction; | |
1064 | req->epnum = dep->number; | |
1065 | ||
1066 | trace_dwc3_ep_queue(req); | |
1067 | ||
1068 | ret = usb_gadget_map_request(&dwc->gadget, &req->request, | |
1069 | dep->direction); | |
1070 | if (ret) | |
1071 | return ret; | |
1072 | ||
1073 | req->sg = req->request.sg; | |
1074 | req->num_pending_sgs = req->request.num_mapped_sgs; | |
1075 | ||
1076 | list_add_tail(&req->list, &dep->pending_list); | |
1077 | ||
1078 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && | |
1079 | dep->flags & DWC3_EP_PENDING_REQUEST) { | |
1080 | if (list_empty(&dep->started_list)) { | |
1081 | dwc3_stop_active_transfer(dwc, dep->number, true); | |
1082 | dep->flags = DWC3_EP_ENABLED; | |
1083 | } | |
1084 | return 0; | |
1085 | } | |
1086 | ||
1087 | ret = __dwc3_gadget_kick_transfer(dep, 0); | |
1088 | if (ret && ret != -EBUSY) | |
1089 | dwc3_trace(trace_dwc3_gadget, | |
1090 | "%s: failed to kick transfers", | |
1091 | dep->name); | |
1092 | if (ret == -EBUSY) | |
1093 | ret = 0; | |
1094 | ||
1095 | return ret; | |
1096 | } | |
1097 | ||
1098 | static void __dwc3_gadget_ep_zlp_complete(struct usb_ep *ep, | |
1099 | struct usb_request *request) | |
1100 | { | |
1101 | dwc3_gadget_ep_free_request(ep, request); | |
1102 | } | |
1103 | ||
1104 | static int __dwc3_gadget_ep_queue_zlp(struct dwc3 *dwc, struct dwc3_ep *dep) | |
1105 | { | |
1106 | struct dwc3_request *req; | |
1107 | struct usb_request *request; | |
1108 | struct usb_ep *ep = &dep->endpoint; | |
1109 | ||
1110 | dwc3_trace(trace_dwc3_gadget, "queueing ZLP"); | |
1111 | request = dwc3_gadget_ep_alloc_request(ep, GFP_ATOMIC); | |
1112 | if (!request) | |
1113 | return -ENOMEM; | |
1114 | ||
1115 | request->length = 0; | |
1116 | request->buf = dwc->zlp_buf; | |
1117 | request->complete = __dwc3_gadget_ep_zlp_complete; | |
1118 | ||
1119 | req = to_dwc3_request(request); | |
1120 | ||
1121 | return __dwc3_gadget_ep_queue(dep, req); | |
1122 | } | |
1123 | ||
1124 | static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request, | |
1125 | gfp_t gfp_flags) | |
1126 | { | |
1127 | struct dwc3_request *req = to_dwc3_request(request); | |
1128 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1129 | struct dwc3 *dwc = dep->dwc; | |
1130 | ||
1131 | unsigned long flags; | |
1132 | ||
1133 | int ret; | |
1134 | ||
1135 | spin_lock_irqsave(&dwc->lock, flags); | |
1136 | ret = __dwc3_gadget_ep_queue(dep, req); | |
1137 | ||
1138 | /* | |
1139 | * Okay, here's the thing, if gadget driver has requested for a ZLP by | |
1140 | * setting request->zero, instead of doing magic, we will just queue an | |
1141 | * extra usb_request ourselves so that it gets handled the same way as | |
1142 | * any other request. | |
1143 | */ | |
1144 | if (ret == 0 && request->zero && request->length && | |
1145 | (request->length % ep->maxpacket == 0)) | |
1146 | ret = __dwc3_gadget_ep_queue_zlp(dwc, dep); | |
1147 | ||
1148 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1149 | ||
1150 | return ret; | |
1151 | } | |
1152 | ||
1153 | static int dwc3_gadget_ep_dequeue(struct usb_ep *ep, | |
1154 | struct usb_request *request) | |
1155 | { | |
1156 | struct dwc3_request *req = to_dwc3_request(request); | |
1157 | struct dwc3_request *r = NULL; | |
1158 | ||
1159 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1160 | struct dwc3 *dwc = dep->dwc; | |
1161 | ||
1162 | unsigned long flags; | |
1163 | int ret = 0; | |
1164 | ||
1165 | trace_dwc3_ep_dequeue(req); | |
1166 | ||
1167 | spin_lock_irqsave(&dwc->lock, flags); | |
1168 | ||
1169 | list_for_each_entry(r, &dep->pending_list, list) { | |
1170 | if (r == req) | |
1171 | break; | |
1172 | } | |
1173 | ||
1174 | if (r != req) { | |
1175 | list_for_each_entry(r, &dep->started_list, list) { | |
1176 | if (r == req) | |
1177 | break; | |
1178 | } | |
1179 | if (r == req) { | |
1180 | /* wait until it is processed */ | |
1181 | dwc3_stop_active_transfer(dwc, dep->number, true); | |
1182 | goto out1; | |
1183 | } | |
1184 | dev_err(dwc->dev, "request %p was not queued to %s\n", | |
1185 | request, ep->name); | |
1186 | ret = -EINVAL; | |
1187 | goto out0; | |
1188 | } | |
1189 | ||
1190 | out1: | |
1191 | /* giveback the request */ | |
1192 | dwc3_gadget_giveback(dep, req, -ECONNRESET); | |
1193 | ||
1194 | out0: | |
1195 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1196 | ||
1197 | return ret; | |
1198 | } | |
1199 | ||
1200 | int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol) | |
1201 | { | |
1202 | struct dwc3_gadget_ep_cmd_params params; | |
1203 | struct dwc3 *dwc = dep->dwc; | |
1204 | int ret; | |
1205 | ||
1206 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { | |
1207 | dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name); | |
1208 | return -EINVAL; | |
1209 | } | |
1210 | ||
1211 | memset(¶ms, 0x00, sizeof(params)); | |
1212 | ||
1213 | if (value) { | |
1214 | struct dwc3_trb *trb; | |
1215 | ||
1216 | unsigned transfer_in_flight; | |
1217 | unsigned started; | |
1218 | ||
1219 | if (dep->number > 1) | |
1220 | trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue); | |
1221 | else | |
1222 | trb = &dwc->ep0_trb[dep->trb_enqueue]; | |
1223 | ||
1224 | transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO; | |
1225 | started = !list_empty(&dep->started_list); | |
1226 | ||
1227 | if (!protocol && ((dep->direction && transfer_in_flight) || | |
1228 | (!dep->direction && started))) { | |
1229 | dwc3_trace(trace_dwc3_gadget, | |
1230 | "%s: pending request, cannot halt", | |
1231 | dep->name); | |
1232 | return -EAGAIN; | |
1233 | } | |
1234 | ||
1235 | ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL, | |
1236 | ¶ms); | |
1237 | if (ret) | |
1238 | dev_err(dwc->dev, "failed to set STALL on %s\n", | |
1239 | dep->name); | |
1240 | else | |
1241 | dep->flags |= DWC3_EP_STALL; | |
1242 | } else { | |
1243 | ||
1244 | ret = dwc3_send_clear_stall_ep_cmd(dep); | |
1245 | if (ret) | |
1246 | dev_err(dwc->dev, "failed to clear STALL on %s\n", | |
1247 | dep->name); | |
1248 | else | |
1249 | dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE); | |
1250 | } | |
1251 | ||
1252 | return ret; | |
1253 | } | |
1254 | ||
1255 | static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value) | |
1256 | { | |
1257 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1258 | struct dwc3 *dwc = dep->dwc; | |
1259 | ||
1260 | unsigned long flags; | |
1261 | ||
1262 | int ret; | |
1263 | ||
1264 | spin_lock_irqsave(&dwc->lock, flags); | |
1265 | ret = __dwc3_gadget_ep_set_halt(dep, value, false); | |
1266 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1267 | ||
1268 | return ret; | |
1269 | } | |
1270 | ||
1271 | static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep) | |
1272 | { | |
1273 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1274 | struct dwc3 *dwc = dep->dwc; | |
1275 | unsigned long flags; | |
1276 | int ret; | |
1277 | ||
1278 | spin_lock_irqsave(&dwc->lock, flags); | |
1279 | dep->flags |= DWC3_EP_WEDGE; | |
1280 | ||
1281 | if (dep->number == 0 || dep->number == 1) | |
1282 | ret = __dwc3_gadget_ep0_set_halt(ep, 1); | |
1283 | else | |
1284 | ret = __dwc3_gadget_ep_set_halt(dep, 1, false); | |
1285 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1286 | ||
1287 | return ret; | |
1288 | } | |
1289 | ||
1290 | /* -------------------------------------------------------------------------- */ | |
1291 | ||
1292 | static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = { | |
1293 | .bLength = USB_DT_ENDPOINT_SIZE, | |
1294 | .bDescriptorType = USB_DT_ENDPOINT, | |
1295 | .bmAttributes = USB_ENDPOINT_XFER_CONTROL, | |
1296 | }; | |
1297 | ||
1298 | static const struct usb_ep_ops dwc3_gadget_ep0_ops = { | |
1299 | .enable = dwc3_gadget_ep0_enable, | |
1300 | .disable = dwc3_gadget_ep0_disable, | |
1301 | .alloc_request = dwc3_gadget_ep_alloc_request, | |
1302 | .free_request = dwc3_gadget_ep_free_request, | |
1303 | .queue = dwc3_gadget_ep0_queue, | |
1304 | .dequeue = dwc3_gadget_ep_dequeue, | |
1305 | .set_halt = dwc3_gadget_ep0_set_halt, | |
1306 | .set_wedge = dwc3_gadget_ep_set_wedge, | |
1307 | }; | |
1308 | ||
1309 | static const struct usb_ep_ops dwc3_gadget_ep_ops = { | |
1310 | .enable = dwc3_gadget_ep_enable, | |
1311 | .disable = dwc3_gadget_ep_disable, | |
1312 | .alloc_request = dwc3_gadget_ep_alloc_request, | |
1313 | .free_request = dwc3_gadget_ep_free_request, | |
1314 | .queue = dwc3_gadget_ep_queue, | |
1315 | .dequeue = dwc3_gadget_ep_dequeue, | |
1316 | .set_halt = dwc3_gadget_ep_set_halt, | |
1317 | .set_wedge = dwc3_gadget_ep_set_wedge, | |
1318 | }; | |
1319 | ||
1320 | /* -------------------------------------------------------------------------- */ | |
1321 | ||
1322 | static int dwc3_gadget_get_frame(struct usb_gadget *g) | |
1323 | { | |
1324 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1325 | u32 reg; | |
1326 | ||
1327 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
1328 | return DWC3_DSTS_SOFFN(reg); | |
1329 | } | |
1330 | ||
1331 | static int __dwc3_gadget_wakeup(struct dwc3 *dwc) | |
1332 | { | |
1333 | unsigned long timeout; | |
1334 | ||
1335 | int ret; | |
1336 | u32 reg; | |
1337 | ||
1338 | u8 link_state; | |
1339 | u8 speed; | |
1340 | ||
1341 | /* | |
1342 | * According to the Databook Remote wakeup request should | |
1343 | * be issued only when the device is in early suspend state. | |
1344 | * | |
1345 | * We can check that via USB Link State bits in DSTS register. | |
1346 | */ | |
1347 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
1348 | ||
1349 | speed = reg & DWC3_DSTS_CONNECTSPD; | |
1350 | if ((speed == DWC3_DSTS_SUPERSPEED) || | |
1351 | (speed == DWC3_DSTS_SUPERSPEED_PLUS)) { | |
1352 | dwc3_trace(trace_dwc3_gadget, "no wakeup on SuperSpeed"); | |
1353 | return 0; | |
1354 | } | |
1355 | ||
1356 | link_state = DWC3_DSTS_USBLNKST(reg); | |
1357 | ||
1358 | switch (link_state) { | |
1359 | case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */ | |
1360 | case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */ | |
1361 | break; | |
1362 | default: | |
1363 | dwc3_trace(trace_dwc3_gadget, | |
1364 | "can't wakeup from '%s'", | |
1365 | dwc3_gadget_link_string(link_state)); | |
1366 | return -EINVAL; | |
1367 | } | |
1368 | ||
1369 | ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV); | |
1370 | if (ret < 0) { | |
1371 | dev_err(dwc->dev, "failed to put link in Recovery\n"); | |
1372 | return ret; | |
1373 | } | |
1374 | ||
1375 | /* Recent versions do this automatically */ | |
1376 | if (dwc->revision < DWC3_REVISION_194A) { | |
1377 | /* write zeroes to Link Change Request */ | |
1378 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
1379 | reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; | |
1380 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
1381 | } | |
1382 | ||
1383 | /* poll until Link State changes to ON */ | |
1384 | timeout = jiffies + msecs_to_jiffies(100); | |
1385 | ||
1386 | while (!time_after(jiffies, timeout)) { | |
1387 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
1388 | ||
1389 | /* in HS, means ON */ | |
1390 | if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0) | |
1391 | break; | |
1392 | } | |
1393 | ||
1394 | if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) { | |
1395 | dev_err(dwc->dev, "failed to send remote wakeup\n"); | |
1396 | return -EINVAL; | |
1397 | } | |
1398 | ||
1399 | return 0; | |
1400 | } | |
1401 | ||
1402 | static int dwc3_gadget_wakeup(struct usb_gadget *g) | |
1403 | { | |
1404 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1405 | unsigned long flags; | |
1406 | int ret; | |
1407 | ||
1408 | spin_lock_irqsave(&dwc->lock, flags); | |
1409 | ret = __dwc3_gadget_wakeup(dwc); | |
1410 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1411 | ||
1412 | return ret; | |
1413 | } | |
1414 | ||
1415 | static int dwc3_gadget_set_selfpowered(struct usb_gadget *g, | |
1416 | int is_selfpowered) | |
1417 | { | |
1418 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1419 | unsigned long flags; | |
1420 | ||
1421 | spin_lock_irqsave(&dwc->lock, flags); | |
1422 | g->is_selfpowered = !!is_selfpowered; | |
1423 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1424 | ||
1425 | return 0; | |
1426 | } | |
1427 | ||
1428 | static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend) | |
1429 | { | |
1430 | u32 reg; | |
1431 | u32 timeout = 500; | |
1432 | ||
1433 | if (pm_runtime_suspended(dwc->dev)) | |
1434 | return 0; | |
1435 | ||
1436 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
1437 | if (is_on) { | |
1438 | if (dwc->revision <= DWC3_REVISION_187A) { | |
1439 | reg &= ~DWC3_DCTL_TRGTULST_MASK; | |
1440 | reg |= DWC3_DCTL_TRGTULST_RX_DET; | |
1441 | } | |
1442 | ||
1443 | if (dwc->revision >= DWC3_REVISION_194A) | |
1444 | reg &= ~DWC3_DCTL_KEEP_CONNECT; | |
1445 | reg |= DWC3_DCTL_RUN_STOP; | |
1446 | ||
1447 | if (dwc->has_hibernation) | |
1448 | reg |= DWC3_DCTL_KEEP_CONNECT; | |
1449 | ||
1450 | dwc->pullups_connected = true; | |
1451 | } else { | |
1452 | reg &= ~DWC3_DCTL_RUN_STOP; | |
1453 | ||
1454 | if (dwc->has_hibernation && !suspend) | |
1455 | reg &= ~DWC3_DCTL_KEEP_CONNECT; | |
1456 | ||
1457 | dwc->pullups_connected = false; | |
1458 | } | |
1459 | ||
1460 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
1461 | ||
1462 | do { | |
1463 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
1464 | reg &= DWC3_DSTS_DEVCTRLHLT; | |
1465 | } while (--timeout && !(!is_on ^ !reg)); | |
1466 | ||
1467 | if (!timeout) | |
1468 | return -ETIMEDOUT; | |
1469 | ||
1470 | dwc3_trace(trace_dwc3_gadget, "gadget %s data soft-%s", | |
1471 | dwc->gadget_driver | |
1472 | ? dwc->gadget_driver->function : "no-function", | |
1473 | is_on ? "connect" : "disconnect"); | |
1474 | ||
1475 | return 0; | |
1476 | } | |
1477 | ||
1478 | static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on) | |
1479 | { | |
1480 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1481 | unsigned long flags; | |
1482 | int ret; | |
1483 | ||
1484 | is_on = !!is_on; | |
1485 | ||
1486 | spin_lock_irqsave(&dwc->lock, flags); | |
1487 | ret = dwc3_gadget_run_stop(dwc, is_on, false); | |
1488 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1489 | ||
1490 | return ret; | |
1491 | } | |
1492 | ||
1493 | static void dwc3_gadget_enable_irq(struct dwc3 *dwc) | |
1494 | { | |
1495 | u32 reg; | |
1496 | ||
1497 | /* Enable all but Start and End of Frame IRQs */ | |
1498 | reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN | | |
1499 | DWC3_DEVTEN_EVNTOVERFLOWEN | | |
1500 | DWC3_DEVTEN_CMDCMPLTEN | | |
1501 | DWC3_DEVTEN_ERRTICERREN | | |
1502 | DWC3_DEVTEN_WKUPEVTEN | | |
1503 | DWC3_DEVTEN_ULSTCNGEN | | |
1504 | DWC3_DEVTEN_CONNECTDONEEN | | |
1505 | DWC3_DEVTEN_USBRSTEN | | |
1506 | DWC3_DEVTEN_DISCONNEVTEN); | |
1507 | ||
1508 | dwc3_writel(dwc->regs, DWC3_DEVTEN, reg); | |
1509 | } | |
1510 | ||
1511 | static void dwc3_gadget_disable_irq(struct dwc3 *dwc) | |
1512 | { | |
1513 | /* mask all interrupts */ | |
1514 | dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00); | |
1515 | } | |
1516 | ||
1517 | static irqreturn_t dwc3_interrupt(int irq, void *_dwc); | |
1518 | static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc); | |
1519 | ||
1520 | /** | |
1521 | * dwc3_gadget_setup_nump - Calculate and initialize NUMP field of DCFG | |
1522 | * dwc: pointer to our context structure | |
1523 | * | |
1524 | * The following looks like complex but it's actually very simple. In order to | |
1525 | * calculate the number of packets we can burst at once on OUT transfers, we're | |
1526 | * gonna use RxFIFO size. | |
1527 | * | |
1528 | * To calculate RxFIFO size we need two numbers: | |
1529 | * MDWIDTH = size, in bits, of the internal memory bus | |
1530 | * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits) | |
1531 | * | |
1532 | * Given these two numbers, the formula is simple: | |
1533 | * | |
1534 | * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16; | |
1535 | * | |
1536 | * 24 bytes is for 3x SETUP packets | |
1537 | * 16 bytes is a clock domain crossing tolerance | |
1538 | * | |
1539 | * Given RxFIFO Size, NUMP = RxFIFOSize / 1024; | |
1540 | */ | |
1541 | static void dwc3_gadget_setup_nump(struct dwc3 *dwc) | |
1542 | { | |
1543 | u32 ram2_depth; | |
1544 | u32 mdwidth; | |
1545 | u32 nump; | |
1546 | u32 reg; | |
1547 | ||
1548 | ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7); | |
1549 | mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0); | |
1550 | ||
1551 | nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024; | |
1552 | nump = min_t(u32, nump, 16); | |
1553 | ||
1554 | /* update NumP */ | |
1555 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
1556 | reg &= ~DWC3_DCFG_NUMP_MASK; | |
1557 | reg |= nump << DWC3_DCFG_NUMP_SHIFT; | |
1558 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
1559 | } | |
1560 | ||
1561 | static int __dwc3_gadget_start(struct dwc3 *dwc) | |
1562 | { | |
1563 | struct dwc3_ep *dep; | |
1564 | int ret = 0; | |
1565 | u32 reg; | |
1566 | ||
1567 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
1568 | reg &= ~(DWC3_DCFG_SPEED_MASK); | |
1569 | ||
1570 | /** | |
1571 | * WORKAROUND: DWC3 revision < 2.20a have an issue | |
1572 | * which would cause metastability state on Run/Stop | |
1573 | * bit if we try to force the IP to USB2-only mode. | |
1574 | * | |
1575 | * Because of that, we cannot configure the IP to any | |
1576 | * speed other than the SuperSpeed | |
1577 | * | |
1578 | * Refers to: | |
1579 | * | |
1580 | * STAR#9000525659: Clock Domain Crossing on DCTL in | |
1581 | * USB 2.0 Mode | |
1582 | */ | |
1583 | if (dwc->revision < DWC3_REVISION_220A) { | |
1584 | reg |= DWC3_DCFG_SUPERSPEED; | |
1585 | } else { | |
1586 | switch (dwc->maximum_speed) { | |
1587 | case USB_SPEED_LOW: | |
1588 | reg |= DWC3_DCFG_LOWSPEED; | |
1589 | break; | |
1590 | case USB_SPEED_FULL: | |
1591 | reg |= DWC3_DCFG_FULLSPEED1; | |
1592 | break; | |
1593 | case USB_SPEED_HIGH: | |
1594 | reg |= DWC3_DCFG_HIGHSPEED; | |
1595 | break; | |
1596 | case USB_SPEED_SUPER_PLUS: | |
1597 | reg |= DWC3_DCFG_SUPERSPEED_PLUS; | |
1598 | break; | |
1599 | default: | |
1600 | dev_err(dwc->dev, "invalid dwc->maximum_speed (%d)\n", | |
1601 | dwc->maximum_speed); | |
1602 | /* fall through */ | |
1603 | case USB_SPEED_SUPER: | |
1604 | reg |= DWC3_DCFG_SUPERSPEED; | |
1605 | break; | |
1606 | } | |
1607 | } | |
1608 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
1609 | ||
1610 | /* | |
1611 | * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP | |
1612 | * field instead of letting dwc3 itself calculate that automatically. | |
1613 | * | |
1614 | * This way, we maximize the chances that we'll be able to get several | |
1615 | * bursts of data without going through any sort of endpoint throttling. | |
1616 | */ | |
1617 | reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); | |
1618 | reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL; | |
1619 | dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); | |
1620 | ||
1621 | dwc3_gadget_setup_nump(dwc); | |
1622 | ||
1623 | /* Start with SuperSpeed Default */ | |
1624 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); | |
1625 | ||
1626 | dep = dwc->eps[0]; | |
1627 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false, | |
1628 | false); | |
1629 | if (ret) { | |
1630 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
1631 | goto err0; | |
1632 | } | |
1633 | ||
1634 | dep = dwc->eps[1]; | |
1635 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false, | |
1636 | false); | |
1637 | if (ret) { | |
1638 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
1639 | goto err1; | |
1640 | } | |
1641 | ||
1642 | /* begin to receive SETUP packets */ | |
1643 | dwc->ep0state = EP0_SETUP_PHASE; | |
1644 | dwc3_ep0_out_start(dwc); | |
1645 | ||
1646 | dwc3_gadget_enable_irq(dwc); | |
1647 | ||
1648 | return 0; | |
1649 | ||
1650 | err1: | |
1651 | __dwc3_gadget_ep_disable(dwc->eps[0]); | |
1652 | ||
1653 | err0: | |
1654 | return ret; | |
1655 | } | |
1656 | ||
1657 | static int dwc3_gadget_start(struct usb_gadget *g, | |
1658 | struct usb_gadget_driver *driver) | |
1659 | { | |
1660 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1661 | unsigned long flags; | |
1662 | int ret = 0; | |
1663 | int irq; | |
1664 | ||
1665 | irq = dwc->irq_gadget; | |
1666 | ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt, | |
1667 | IRQF_SHARED, "dwc3", dwc->ev_buf); | |
1668 | if (ret) { | |
1669 | dev_err(dwc->dev, "failed to request irq #%d --> %d\n", | |
1670 | irq, ret); | |
1671 | goto err0; | |
1672 | } | |
1673 | ||
1674 | spin_lock_irqsave(&dwc->lock, flags); | |
1675 | if (dwc->gadget_driver) { | |
1676 | dev_err(dwc->dev, "%s is already bound to %s\n", | |
1677 | dwc->gadget.name, | |
1678 | dwc->gadget_driver->driver.name); | |
1679 | ret = -EBUSY; | |
1680 | goto err1; | |
1681 | } | |
1682 | ||
1683 | dwc->gadget_driver = driver; | |
1684 | ||
1685 | if (pm_runtime_active(dwc->dev)) | |
1686 | __dwc3_gadget_start(dwc); | |
1687 | ||
1688 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1689 | ||
1690 | return 0; | |
1691 | ||
1692 | err1: | |
1693 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1694 | free_irq(irq, dwc); | |
1695 | ||
1696 | err0: | |
1697 | return ret; | |
1698 | } | |
1699 | ||
1700 | static void __dwc3_gadget_stop(struct dwc3 *dwc) | |
1701 | { | |
1702 | if (pm_runtime_suspended(dwc->dev)) | |
1703 | return; | |
1704 | ||
1705 | dwc3_gadget_disable_irq(dwc); | |
1706 | __dwc3_gadget_ep_disable(dwc->eps[0]); | |
1707 | __dwc3_gadget_ep_disable(dwc->eps[1]); | |
1708 | } | |
1709 | ||
1710 | static int dwc3_gadget_stop(struct usb_gadget *g) | |
1711 | { | |
1712 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1713 | unsigned long flags; | |
1714 | ||
1715 | spin_lock_irqsave(&dwc->lock, flags); | |
1716 | __dwc3_gadget_stop(dwc); | |
1717 | dwc->gadget_driver = NULL; | |
1718 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1719 | ||
1720 | free_irq(dwc->irq_gadget, dwc->ev_buf); | |
1721 | ||
1722 | return 0; | |
1723 | } | |
1724 | ||
1725 | static const struct usb_gadget_ops dwc3_gadget_ops = { | |
1726 | .get_frame = dwc3_gadget_get_frame, | |
1727 | .wakeup = dwc3_gadget_wakeup, | |
1728 | .set_selfpowered = dwc3_gadget_set_selfpowered, | |
1729 | .pullup = dwc3_gadget_pullup, | |
1730 | .udc_start = dwc3_gadget_start, | |
1731 | .udc_stop = dwc3_gadget_stop, | |
1732 | }; | |
1733 | ||
1734 | /* -------------------------------------------------------------------------- */ | |
1735 | ||
1736 | static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc, | |
1737 | u8 num, u32 direction) | |
1738 | { | |
1739 | struct dwc3_ep *dep; | |
1740 | u8 i; | |
1741 | ||
1742 | for (i = 0; i < num; i++) { | |
1743 | u8 epnum = (i << 1) | (direction ? 1 : 0); | |
1744 | ||
1745 | dep = kzalloc(sizeof(*dep), GFP_KERNEL); | |
1746 | if (!dep) | |
1747 | return -ENOMEM; | |
1748 | ||
1749 | dep->dwc = dwc; | |
1750 | dep->number = epnum; | |
1751 | dep->direction = !!direction; | |
1752 | dep->regs = dwc->regs + DWC3_DEP_BASE(epnum); | |
1753 | dwc->eps[epnum] = dep; | |
1754 | ||
1755 | snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1, | |
1756 | (epnum & 1) ? "in" : "out"); | |
1757 | ||
1758 | dep->endpoint.name = dep->name; | |
1759 | spin_lock_init(&dep->lock); | |
1760 | ||
1761 | dwc3_trace(trace_dwc3_gadget, "initializing %s", dep->name); | |
1762 | ||
1763 | if (epnum == 0 || epnum == 1) { | |
1764 | usb_ep_set_maxpacket_limit(&dep->endpoint, 512); | |
1765 | dep->endpoint.maxburst = 1; | |
1766 | dep->endpoint.ops = &dwc3_gadget_ep0_ops; | |
1767 | if (!epnum) | |
1768 | dwc->gadget.ep0 = &dep->endpoint; | |
1769 | } else { | |
1770 | int ret; | |
1771 | ||
1772 | usb_ep_set_maxpacket_limit(&dep->endpoint, 1024); | |
1773 | dep->endpoint.max_streams = 15; | |
1774 | dep->endpoint.ops = &dwc3_gadget_ep_ops; | |
1775 | list_add_tail(&dep->endpoint.ep_list, | |
1776 | &dwc->gadget.ep_list); | |
1777 | ||
1778 | ret = dwc3_alloc_trb_pool(dep); | |
1779 | if (ret) | |
1780 | return ret; | |
1781 | } | |
1782 | ||
1783 | if (epnum == 0 || epnum == 1) { | |
1784 | dep->endpoint.caps.type_control = true; | |
1785 | } else { | |
1786 | dep->endpoint.caps.type_iso = true; | |
1787 | dep->endpoint.caps.type_bulk = true; | |
1788 | dep->endpoint.caps.type_int = true; | |
1789 | } | |
1790 | ||
1791 | dep->endpoint.caps.dir_in = !!direction; | |
1792 | dep->endpoint.caps.dir_out = !direction; | |
1793 | ||
1794 | INIT_LIST_HEAD(&dep->pending_list); | |
1795 | INIT_LIST_HEAD(&dep->started_list); | |
1796 | } | |
1797 | ||
1798 | return 0; | |
1799 | } | |
1800 | ||
1801 | static int dwc3_gadget_init_endpoints(struct dwc3 *dwc) | |
1802 | { | |
1803 | int ret; | |
1804 | ||
1805 | INIT_LIST_HEAD(&dwc->gadget.ep_list); | |
1806 | ||
1807 | ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0); | |
1808 | if (ret < 0) { | |
1809 | dwc3_trace(trace_dwc3_gadget, | |
1810 | "failed to allocate OUT endpoints"); | |
1811 | return ret; | |
1812 | } | |
1813 | ||
1814 | ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1); | |
1815 | if (ret < 0) { | |
1816 | dwc3_trace(trace_dwc3_gadget, | |
1817 | "failed to allocate IN endpoints"); | |
1818 | return ret; | |
1819 | } | |
1820 | ||
1821 | return 0; | |
1822 | } | |
1823 | ||
1824 | static void dwc3_gadget_free_endpoints(struct dwc3 *dwc) | |
1825 | { | |
1826 | struct dwc3_ep *dep; | |
1827 | u8 epnum; | |
1828 | ||
1829 | for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
1830 | dep = dwc->eps[epnum]; | |
1831 | if (!dep) | |
1832 | continue; | |
1833 | /* | |
1834 | * Physical endpoints 0 and 1 are special; they form the | |
1835 | * bi-directional USB endpoint 0. | |
1836 | * | |
1837 | * For those two physical endpoints, we don't allocate a TRB | |
1838 | * pool nor do we add them the endpoints list. Due to that, we | |
1839 | * shouldn't do these two operations otherwise we would end up | |
1840 | * with all sorts of bugs when removing dwc3.ko. | |
1841 | */ | |
1842 | if (epnum != 0 && epnum != 1) { | |
1843 | dwc3_free_trb_pool(dep); | |
1844 | list_del(&dep->endpoint.ep_list); | |
1845 | } | |
1846 | ||
1847 | kfree(dep); | |
1848 | } | |
1849 | } | |
1850 | ||
1851 | /* -------------------------------------------------------------------------- */ | |
1852 | ||
1853 | static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep, | |
1854 | struct dwc3_request *req, struct dwc3_trb *trb, | |
1855 | const struct dwc3_event_depevt *event, int status, | |
1856 | int chain) | |
1857 | { | |
1858 | unsigned int count; | |
1859 | unsigned int s_pkt = 0; | |
1860 | unsigned int trb_status; | |
1861 | ||
1862 | dep->queued_requests--; | |
1863 | trace_dwc3_complete_trb(dep, trb); | |
1864 | ||
1865 | /* | |
1866 | * If we're in the middle of series of chained TRBs and we | |
1867 | * receive a short transfer along the way, DWC3 will skip | |
1868 | * through all TRBs including the last TRB in the chain (the | |
1869 | * where CHN bit is zero. DWC3 will also avoid clearing HWO | |
1870 | * bit and SW has to do it manually. | |
1871 | * | |
1872 | * We're going to do that here to avoid problems of HW trying | |
1873 | * to use bogus TRBs for transfers. | |
1874 | */ | |
1875 | if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO)) | |
1876 | trb->ctrl &= ~DWC3_TRB_CTRL_HWO; | |
1877 | ||
1878 | if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN) | |
1879 | return 1; | |
1880 | ||
1881 | count = trb->size & DWC3_TRB_SIZE_MASK; | |
1882 | ||
1883 | if (dep->direction) { | |
1884 | if (count) { | |
1885 | trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size); | |
1886 | if (trb_status == DWC3_TRBSTS_MISSED_ISOC) { | |
1887 | dwc3_trace(trace_dwc3_gadget, | |
1888 | "%s: incomplete IN transfer", | |
1889 | dep->name); | |
1890 | /* | |
1891 | * If missed isoc occurred and there is | |
1892 | * no request queued then issue END | |
1893 | * TRANSFER, so that core generates | |
1894 | * next xfernotready and we will issue | |
1895 | * a fresh START TRANSFER. | |
1896 | * If there are still queued request | |
1897 | * then wait, do not issue either END | |
1898 | * or UPDATE TRANSFER, just attach next | |
1899 | * request in pending_list during | |
1900 | * giveback.If any future queued request | |
1901 | * is successfully transferred then we | |
1902 | * will issue UPDATE TRANSFER for all | |
1903 | * request in the pending_list. | |
1904 | */ | |
1905 | dep->flags |= DWC3_EP_MISSED_ISOC; | |
1906 | } else { | |
1907 | dev_err(dwc->dev, "incomplete IN transfer %s\n", | |
1908 | dep->name); | |
1909 | status = -ECONNRESET; | |
1910 | } | |
1911 | } else { | |
1912 | dep->flags &= ~DWC3_EP_MISSED_ISOC; | |
1913 | } | |
1914 | } else { | |
1915 | if (count && (event->status & DEPEVT_STATUS_SHORT)) | |
1916 | s_pkt = 1; | |
1917 | } | |
1918 | ||
1919 | if (s_pkt && !chain) | |
1920 | return 1; | |
1921 | if ((event->status & DEPEVT_STATUS_LST) && | |
1922 | (trb->ctrl & (DWC3_TRB_CTRL_LST | | |
1923 | DWC3_TRB_CTRL_HWO))) | |
1924 | return 1; | |
1925 | if ((event->status & DEPEVT_STATUS_IOC) && | |
1926 | (trb->ctrl & DWC3_TRB_CTRL_IOC)) | |
1927 | return 1; | |
1928 | return 0; | |
1929 | } | |
1930 | ||
1931 | static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep, | |
1932 | const struct dwc3_event_depevt *event, int status) | |
1933 | { | |
1934 | struct dwc3_request *req, *n; | |
1935 | struct dwc3_trb *trb; | |
1936 | int count = 0; | |
1937 | int ret; | |
1938 | ||
1939 | list_for_each_entry_safe(req, n, &dep->started_list, list) { | |
1940 | unsigned length; | |
1941 | unsigned actual; | |
1942 | int chain; | |
1943 | ||
1944 | length = req->request.length; | |
1945 | chain = req->num_pending_sgs > 0; | |
1946 | if (chain) { | |
1947 | struct scatterlist *sg = req->sg; | |
1948 | struct scatterlist *s; | |
1949 | unsigned int pending = req->num_pending_sgs; | |
1950 | unsigned int i; | |
1951 | ||
1952 | for_each_sg(sg, s, pending, i) { | |
1953 | trb = &dep->trb_pool[dep->trb_dequeue]; | |
1954 | count += trb->size & DWC3_TRB_SIZE_MASK; | |
1955 | dwc3_ep_inc_deq(dep); | |
1956 | ||
1957 | req->sg = sg_next(s); | |
1958 | req->num_pending_sgs--; | |
1959 | ||
1960 | ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb, | |
1961 | event, status, chain); | |
1962 | if (ret) | |
1963 | break; | |
1964 | } | |
1965 | } else { | |
1966 | trb = &dep->trb_pool[dep->trb_dequeue]; | |
1967 | count += trb->size & DWC3_TRB_SIZE_MASK; | |
1968 | dwc3_ep_inc_deq(dep); | |
1969 | ||
1970 | ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb, | |
1971 | event, status, chain); | |
1972 | } | |
1973 | ||
1974 | /* | |
1975 | * We assume here we will always receive the entire data block | |
1976 | * which we should receive. Meaning, if we program RX to | |
1977 | * receive 4K but we receive only 2K, we assume that's all we | |
1978 | * should receive and we simply bounce the request back to the | |
1979 | * gadget driver for further processing. | |
1980 | */ | |
1981 | actual = length - req->request.actual; | |
1982 | req->request.actual = actual; | |
1983 | ||
1984 | if (ret && chain && (actual < length) && req->num_pending_sgs) | |
1985 | return __dwc3_gadget_kick_transfer(dep, 0); | |
1986 | ||
1987 | dwc3_gadget_giveback(dep, req, status); | |
1988 | ||
1989 | if (ret) | |
1990 | break; | |
1991 | } | |
1992 | ||
1993 | /* | |
1994 | * Our endpoint might get disabled by another thread during | |
1995 | * dwc3_gadget_giveback(). If that happens, we're just gonna return 1 | |
1996 | * early on so DWC3_EP_BUSY flag gets cleared | |
1997 | */ | |
1998 | if (!dep->endpoint.desc) | |
1999 | return 1; | |
2000 | ||
2001 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && | |
2002 | list_empty(&dep->started_list)) { | |
2003 | if (list_empty(&dep->pending_list)) { | |
2004 | /* | |
2005 | * If there is no entry in request list then do | |
2006 | * not issue END TRANSFER now. Just set PENDING | |
2007 | * flag, so that END TRANSFER is issued when an | |
2008 | * entry is added into request list. | |
2009 | */ | |
2010 | dep->flags = DWC3_EP_PENDING_REQUEST; | |
2011 | } else { | |
2012 | dwc3_stop_active_transfer(dwc, dep->number, true); | |
2013 | dep->flags = DWC3_EP_ENABLED; | |
2014 | } | |
2015 | return 1; | |
2016 | } | |
2017 | ||
2018 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) | |
2019 | if ((event->status & DEPEVT_STATUS_IOC) && | |
2020 | (trb->ctrl & DWC3_TRB_CTRL_IOC)) | |
2021 | return 0; | |
2022 | return 1; | |
2023 | } | |
2024 | ||
2025 | static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc, | |
2026 | struct dwc3_ep *dep, const struct dwc3_event_depevt *event) | |
2027 | { | |
2028 | unsigned status = 0; | |
2029 | int clean_busy; | |
2030 | u32 is_xfer_complete; | |
2031 | ||
2032 | is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE); | |
2033 | ||
2034 | if (event->status & DEPEVT_STATUS_BUSERR) | |
2035 | status = -ECONNRESET; | |
2036 | ||
2037 | clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status); | |
2038 | if (clean_busy && (!dep->endpoint.desc || is_xfer_complete || | |
2039 | usb_endpoint_xfer_isoc(dep->endpoint.desc))) | |
2040 | dep->flags &= ~DWC3_EP_BUSY; | |
2041 | ||
2042 | /* | |
2043 | * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround. | |
2044 | * See dwc3_gadget_linksts_change_interrupt() for 1st half. | |
2045 | */ | |
2046 | if (dwc->revision < DWC3_REVISION_183A) { | |
2047 | u32 reg; | |
2048 | int i; | |
2049 | ||
2050 | for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) { | |
2051 | dep = dwc->eps[i]; | |
2052 | ||
2053 | if (!(dep->flags & DWC3_EP_ENABLED)) | |
2054 | continue; | |
2055 | ||
2056 | if (!list_empty(&dep->started_list)) | |
2057 | return; | |
2058 | } | |
2059 | ||
2060 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2061 | reg |= dwc->u1u2; | |
2062 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
2063 | ||
2064 | dwc->u1u2 = 0; | |
2065 | } | |
2066 | ||
2067 | /* | |
2068 | * Our endpoint might get disabled by another thread during | |
2069 | * dwc3_gadget_giveback(). If that happens, we're just gonna return 1 | |
2070 | * early on so DWC3_EP_BUSY flag gets cleared | |
2071 | */ | |
2072 | if (!dep->endpoint.desc) | |
2073 | return; | |
2074 | ||
2075 | if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) { | |
2076 | int ret; | |
2077 | ||
2078 | ret = __dwc3_gadget_kick_transfer(dep, 0); | |
2079 | if (!ret || ret == -EBUSY) | |
2080 | return; | |
2081 | } | |
2082 | } | |
2083 | ||
2084 | static void dwc3_endpoint_interrupt(struct dwc3 *dwc, | |
2085 | const struct dwc3_event_depevt *event) | |
2086 | { | |
2087 | struct dwc3_ep *dep; | |
2088 | u8 epnum = event->endpoint_number; | |
2089 | ||
2090 | dep = dwc->eps[epnum]; | |
2091 | ||
2092 | if (!(dep->flags & DWC3_EP_ENABLED)) | |
2093 | return; | |
2094 | ||
2095 | if (epnum == 0 || epnum == 1) { | |
2096 | dwc3_ep0_interrupt(dwc, event); | |
2097 | return; | |
2098 | } | |
2099 | ||
2100 | switch (event->endpoint_event) { | |
2101 | case DWC3_DEPEVT_XFERCOMPLETE: | |
2102 | dep->resource_index = 0; | |
2103 | ||
2104 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { | |
2105 | dwc3_trace(trace_dwc3_gadget, | |
2106 | "%s is an Isochronous endpoint", | |
2107 | dep->name); | |
2108 | return; | |
2109 | } | |
2110 | ||
2111 | dwc3_endpoint_transfer_complete(dwc, dep, event); | |
2112 | break; | |
2113 | case DWC3_DEPEVT_XFERINPROGRESS: | |
2114 | dwc3_endpoint_transfer_complete(dwc, dep, event); | |
2115 | break; | |
2116 | case DWC3_DEPEVT_XFERNOTREADY: | |
2117 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { | |
2118 | dwc3_gadget_start_isoc(dwc, dep, event); | |
2119 | } else { | |
2120 | int active; | |
2121 | int ret; | |
2122 | ||
2123 | active = event->status & DEPEVT_STATUS_TRANSFER_ACTIVE; | |
2124 | ||
2125 | dwc3_trace(trace_dwc3_gadget, "%s: reason %s", | |
2126 | dep->name, active ? "Transfer Active" | |
2127 | : "Transfer Not Active"); | |
2128 | ||
2129 | ret = __dwc3_gadget_kick_transfer(dep, 0); | |
2130 | if (!ret || ret == -EBUSY) | |
2131 | return; | |
2132 | ||
2133 | dwc3_trace(trace_dwc3_gadget, | |
2134 | "%s: failed to kick transfers", | |
2135 | dep->name); | |
2136 | } | |
2137 | ||
2138 | break; | |
2139 | case DWC3_DEPEVT_STREAMEVT: | |
2140 | if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) { | |
2141 | dev_err(dwc->dev, "Stream event for non-Bulk %s\n", | |
2142 | dep->name); | |
2143 | return; | |
2144 | } | |
2145 | ||
2146 | switch (event->status) { | |
2147 | case DEPEVT_STREAMEVT_FOUND: | |
2148 | dwc3_trace(trace_dwc3_gadget, | |
2149 | "Stream %d found and started", | |
2150 | event->parameters); | |
2151 | ||
2152 | break; | |
2153 | case DEPEVT_STREAMEVT_NOTFOUND: | |
2154 | /* FALLTHROUGH */ | |
2155 | default: | |
2156 | dwc3_trace(trace_dwc3_gadget, | |
2157 | "unable to find suitable stream"); | |
2158 | } | |
2159 | break; | |
2160 | case DWC3_DEPEVT_RXTXFIFOEVT: | |
2161 | dwc3_trace(trace_dwc3_gadget, "%s FIFO Overrun", dep->name); | |
2162 | break; | |
2163 | case DWC3_DEPEVT_EPCMDCMPLT: | |
2164 | dwc3_trace(trace_dwc3_gadget, "Endpoint Command Complete"); | |
2165 | break; | |
2166 | } | |
2167 | } | |
2168 | ||
2169 | static void dwc3_disconnect_gadget(struct dwc3 *dwc) | |
2170 | { | |
2171 | if (dwc->gadget_driver && dwc->gadget_driver->disconnect) { | |
2172 | spin_unlock(&dwc->lock); | |
2173 | dwc->gadget_driver->disconnect(&dwc->gadget); | |
2174 | spin_lock(&dwc->lock); | |
2175 | } | |
2176 | } | |
2177 | ||
2178 | static void dwc3_suspend_gadget(struct dwc3 *dwc) | |
2179 | { | |
2180 | if (dwc->gadget_driver && dwc->gadget_driver->suspend) { | |
2181 | spin_unlock(&dwc->lock); | |
2182 | dwc->gadget_driver->suspend(&dwc->gadget); | |
2183 | spin_lock(&dwc->lock); | |
2184 | } | |
2185 | } | |
2186 | ||
2187 | static void dwc3_resume_gadget(struct dwc3 *dwc) | |
2188 | { | |
2189 | if (dwc->gadget_driver && dwc->gadget_driver->resume) { | |
2190 | spin_unlock(&dwc->lock); | |
2191 | dwc->gadget_driver->resume(&dwc->gadget); | |
2192 | spin_lock(&dwc->lock); | |
2193 | } | |
2194 | } | |
2195 | ||
2196 | static void dwc3_reset_gadget(struct dwc3 *dwc) | |
2197 | { | |
2198 | if (!dwc->gadget_driver) | |
2199 | return; | |
2200 | ||
2201 | if (dwc->gadget.speed != USB_SPEED_UNKNOWN) { | |
2202 | spin_unlock(&dwc->lock); | |
2203 | usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver); | |
2204 | spin_lock(&dwc->lock); | |
2205 | } | |
2206 | } | |
2207 | ||
2208 | static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force) | |
2209 | { | |
2210 | struct dwc3_ep *dep; | |
2211 | struct dwc3_gadget_ep_cmd_params params; | |
2212 | u32 cmd; | |
2213 | int ret; | |
2214 | ||
2215 | dep = dwc->eps[epnum]; | |
2216 | ||
2217 | if (!dep->resource_index) | |
2218 | return; | |
2219 | ||
2220 | /* | |
2221 | * NOTICE: We are violating what the Databook says about the | |
2222 | * EndTransfer command. Ideally we would _always_ wait for the | |
2223 | * EndTransfer Command Completion IRQ, but that's causing too | |
2224 | * much trouble synchronizing between us and gadget driver. | |
2225 | * | |
2226 | * We have discussed this with the IP Provider and it was | |
2227 | * suggested to giveback all requests here, but give HW some | |
2228 | * extra time to synchronize with the interconnect. We're using | |
2229 | * an arbitrary 100us delay for that. | |
2230 | * | |
2231 | * Note also that a similar handling was tested by Synopsys | |
2232 | * (thanks a lot Paul) and nothing bad has come out of it. | |
2233 | * In short, what we're doing is: | |
2234 | * | |
2235 | * - Issue EndTransfer WITH CMDIOC bit set | |
2236 | * - Wait 100us | |
2237 | */ | |
2238 | ||
2239 | cmd = DWC3_DEPCMD_ENDTRANSFER; | |
2240 | cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0; | |
2241 | cmd |= DWC3_DEPCMD_CMDIOC; | |
2242 | cmd |= DWC3_DEPCMD_PARAM(dep->resource_index); | |
2243 | memset(¶ms, 0, sizeof(params)); | |
2244 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); | |
2245 | WARN_ON_ONCE(ret); | |
2246 | dep->resource_index = 0; | |
2247 | dep->flags &= ~DWC3_EP_BUSY; | |
2248 | udelay(100); | |
2249 | } | |
2250 | ||
2251 | static void dwc3_stop_active_transfers(struct dwc3 *dwc) | |
2252 | { | |
2253 | u32 epnum; | |
2254 | ||
2255 | for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
2256 | struct dwc3_ep *dep; | |
2257 | ||
2258 | dep = dwc->eps[epnum]; | |
2259 | if (!dep) | |
2260 | continue; | |
2261 | ||
2262 | if (!(dep->flags & DWC3_EP_ENABLED)) | |
2263 | continue; | |
2264 | ||
2265 | dwc3_remove_requests(dwc, dep); | |
2266 | } | |
2267 | } | |
2268 | ||
2269 | static void dwc3_clear_stall_all_ep(struct dwc3 *dwc) | |
2270 | { | |
2271 | u32 epnum; | |
2272 | ||
2273 | for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
2274 | struct dwc3_ep *dep; | |
2275 | int ret; | |
2276 | ||
2277 | dep = dwc->eps[epnum]; | |
2278 | if (!dep) | |
2279 | continue; | |
2280 | ||
2281 | if (!(dep->flags & DWC3_EP_STALL)) | |
2282 | continue; | |
2283 | ||
2284 | dep->flags &= ~DWC3_EP_STALL; | |
2285 | ||
2286 | ret = dwc3_send_clear_stall_ep_cmd(dep); | |
2287 | WARN_ON_ONCE(ret); | |
2288 | } | |
2289 | } | |
2290 | ||
2291 | static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc) | |
2292 | { | |
2293 | int reg; | |
2294 | ||
2295 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2296 | reg &= ~DWC3_DCTL_INITU1ENA; | |
2297 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
2298 | ||
2299 | reg &= ~DWC3_DCTL_INITU2ENA; | |
2300 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
2301 | ||
2302 | dwc3_disconnect_gadget(dwc); | |
2303 | ||
2304 | dwc->gadget.speed = USB_SPEED_UNKNOWN; | |
2305 | dwc->setup_packet_pending = false; | |
2306 | usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED); | |
2307 | ||
2308 | dwc->connected = false; | |
2309 | } | |
2310 | ||
2311 | static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc) | |
2312 | { | |
2313 | u32 reg; | |
2314 | ||
2315 | dwc->connected = true; | |
2316 | ||
2317 | /* | |
2318 | * WORKAROUND: DWC3 revisions <1.88a have an issue which | |
2319 | * would cause a missing Disconnect Event if there's a | |
2320 | * pending Setup Packet in the FIFO. | |
2321 | * | |
2322 | * There's no suggested workaround on the official Bug | |
2323 | * report, which states that "unless the driver/application | |
2324 | * is doing any special handling of a disconnect event, | |
2325 | * there is no functional issue". | |
2326 | * | |
2327 | * Unfortunately, it turns out that we _do_ some special | |
2328 | * handling of a disconnect event, namely complete all | |
2329 | * pending transfers, notify gadget driver of the | |
2330 | * disconnection, and so on. | |
2331 | * | |
2332 | * Our suggested workaround is to follow the Disconnect | |
2333 | * Event steps here, instead, based on a setup_packet_pending | |
2334 | * flag. Such flag gets set whenever we have a SETUP_PENDING | |
2335 | * status for EP0 TRBs and gets cleared on XferComplete for the | |
2336 | * same endpoint. | |
2337 | * | |
2338 | * Refers to: | |
2339 | * | |
2340 | * STAR#9000466709: RTL: Device : Disconnect event not | |
2341 | * generated if setup packet pending in FIFO | |
2342 | */ | |
2343 | if (dwc->revision < DWC3_REVISION_188A) { | |
2344 | if (dwc->setup_packet_pending) | |
2345 | dwc3_gadget_disconnect_interrupt(dwc); | |
2346 | } | |
2347 | ||
2348 | dwc3_reset_gadget(dwc); | |
2349 | ||
2350 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2351 | reg &= ~DWC3_DCTL_TSTCTRL_MASK; | |
2352 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
2353 | dwc->test_mode = false; | |
2354 | ||
2355 | dwc3_stop_active_transfers(dwc); | |
2356 | dwc3_clear_stall_all_ep(dwc); | |
2357 | ||
2358 | /* Reset device address to zero */ | |
2359 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
2360 | reg &= ~(DWC3_DCFG_DEVADDR_MASK); | |
2361 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
2362 | } | |
2363 | ||
2364 | static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed) | |
2365 | { | |
2366 | u32 reg; | |
2367 | u32 usb30_clock = DWC3_GCTL_CLK_BUS; | |
2368 | ||
2369 | /* | |
2370 | * We change the clock only at SS but I dunno why I would want to do | |
2371 | * this. Maybe it becomes part of the power saving plan. | |
2372 | */ | |
2373 | ||
2374 | if ((speed != DWC3_DSTS_SUPERSPEED) && | |
2375 | (speed != DWC3_DSTS_SUPERSPEED_PLUS)) | |
2376 | return; | |
2377 | ||
2378 | /* | |
2379 | * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed | |
2380 | * each time on Connect Done. | |
2381 | */ | |
2382 | if (!usb30_clock) | |
2383 | return; | |
2384 | ||
2385 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); | |
2386 | reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock); | |
2387 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); | |
2388 | } | |
2389 | ||
2390 | static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc) | |
2391 | { | |
2392 | struct dwc3_ep *dep; | |
2393 | int ret; | |
2394 | u32 reg; | |
2395 | u8 speed; | |
2396 | ||
2397 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
2398 | speed = reg & DWC3_DSTS_CONNECTSPD; | |
2399 | dwc->speed = speed; | |
2400 | ||
2401 | dwc3_update_ram_clk_sel(dwc, speed); | |
2402 | ||
2403 | switch (speed) { | |
2404 | case DWC3_DSTS_SUPERSPEED_PLUS: | |
2405 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); | |
2406 | dwc->gadget.ep0->maxpacket = 512; | |
2407 | dwc->gadget.speed = USB_SPEED_SUPER_PLUS; | |
2408 | break; | |
2409 | case DWC3_DSTS_SUPERSPEED: | |
2410 | /* | |
2411 | * WORKAROUND: DWC3 revisions <1.90a have an issue which | |
2412 | * would cause a missing USB3 Reset event. | |
2413 | * | |
2414 | * In such situations, we should force a USB3 Reset | |
2415 | * event by calling our dwc3_gadget_reset_interrupt() | |
2416 | * routine. | |
2417 | * | |
2418 | * Refers to: | |
2419 | * | |
2420 | * STAR#9000483510: RTL: SS : USB3 reset event may | |
2421 | * not be generated always when the link enters poll | |
2422 | */ | |
2423 | if (dwc->revision < DWC3_REVISION_190A) | |
2424 | dwc3_gadget_reset_interrupt(dwc); | |
2425 | ||
2426 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); | |
2427 | dwc->gadget.ep0->maxpacket = 512; | |
2428 | dwc->gadget.speed = USB_SPEED_SUPER; | |
2429 | break; | |
2430 | case DWC3_DSTS_HIGHSPEED: | |
2431 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); | |
2432 | dwc->gadget.ep0->maxpacket = 64; | |
2433 | dwc->gadget.speed = USB_SPEED_HIGH; | |
2434 | break; | |
2435 | case DWC3_DSTS_FULLSPEED2: | |
2436 | case DWC3_DSTS_FULLSPEED1: | |
2437 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); | |
2438 | dwc->gadget.ep0->maxpacket = 64; | |
2439 | dwc->gadget.speed = USB_SPEED_FULL; | |
2440 | break; | |
2441 | case DWC3_DSTS_LOWSPEED: | |
2442 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8); | |
2443 | dwc->gadget.ep0->maxpacket = 8; | |
2444 | dwc->gadget.speed = USB_SPEED_LOW; | |
2445 | break; | |
2446 | } | |
2447 | ||
2448 | /* Enable USB2 LPM Capability */ | |
2449 | ||
2450 | if ((dwc->revision > DWC3_REVISION_194A) && | |
2451 | (speed != DWC3_DSTS_SUPERSPEED) && | |
2452 | (speed != DWC3_DSTS_SUPERSPEED_PLUS)) { | |
2453 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
2454 | reg |= DWC3_DCFG_LPM_CAP; | |
2455 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
2456 | ||
2457 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2458 | reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN); | |
2459 | ||
2460 | reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold); | |
2461 | ||
2462 | /* | |
2463 | * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and | |
2464 | * DCFG.LPMCap is set, core responses with an ACK and the | |
2465 | * BESL value in the LPM token is less than or equal to LPM | |
2466 | * NYET threshold. | |
2467 | */ | |
2468 | WARN_ONCE(dwc->revision < DWC3_REVISION_240A | |
2469 | && dwc->has_lpm_erratum, | |
2470 | "LPM Erratum not available on dwc3 revisisions < 2.40a\n"); | |
2471 | ||
2472 | if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A) | |
2473 | reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold); | |
2474 | ||
2475 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
2476 | } else { | |
2477 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2478 | reg &= ~DWC3_DCTL_HIRD_THRES_MASK; | |
2479 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
2480 | } | |
2481 | ||
2482 | dep = dwc->eps[0]; | |
2483 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true, | |
2484 | false); | |
2485 | if (ret) { | |
2486 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
2487 | return; | |
2488 | } | |
2489 | ||
2490 | dep = dwc->eps[1]; | |
2491 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true, | |
2492 | false); | |
2493 | if (ret) { | |
2494 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
2495 | return; | |
2496 | } | |
2497 | ||
2498 | /* | |
2499 | * Configure PHY via GUSB3PIPECTLn if required. | |
2500 | * | |
2501 | * Update GTXFIFOSIZn | |
2502 | * | |
2503 | * In both cases reset values should be sufficient. | |
2504 | */ | |
2505 | } | |
2506 | ||
2507 | static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc) | |
2508 | { | |
2509 | /* | |
2510 | * TODO take core out of low power mode when that's | |
2511 | * implemented. | |
2512 | */ | |
2513 | ||
2514 | if (dwc->gadget_driver && dwc->gadget_driver->resume) { | |
2515 | spin_unlock(&dwc->lock); | |
2516 | dwc->gadget_driver->resume(&dwc->gadget); | |
2517 | spin_lock(&dwc->lock); | |
2518 | } | |
2519 | } | |
2520 | ||
2521 | static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc, | |
2522 | unsigned int evtinfo) | |
2523 | { | |
2524 | enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK; | |
2525 | unsigned int pwropt; | |
2526 | ||
2527 | /* | |
2528 | * WORKAROUND: DWC3 < 2.50a have an issue when configured without | |
2529 | * Hibernation mode enabled which would show up when device detects | |
2530 | * host-initiated U3 exit. | |
2531 | * | |
2532 | * In that case, device will generate a Link State Change Interrupt | |
2533 | * from U3 to RESUME which is only necessary if Hibernation is | |
2534 | * configured in. | |
2535 | * | |
2536 | * There are no functional changes due to such spurious event and we | |
2537 | * just need to ignore it. | |
2538 | * | |
2539 | * Refers to: | |
2540 | * | |
2541 | * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation | |
2542 | * operational mode | |
2543 | */ | |
2544 | pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1); | |
2545 | if ((dwc->revision < DWC3_REVISION_250A) && | |
2546 | (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) { | |
2547 | if ((dwc->link_state == DWC3_LINK_STATE_U3) && | |
2548 | (next == DWC3_LINK_STATE_RESUME)) { | |
2549 | dwc3_trace(trace_dwc3_gadget, | |
2550 | "ignoring transition U3 -> Resume"); | |
2551 | return; | |
2552 | } | |
2553 | } | |
2554 | ||
2555 | /* | |
2556 | * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending | |
2557 | * on the link partner, the USB session might do multiple entry/exit | |
2558 | * of low power states before a transfer takes place. | |
2559 | * | |
2560 | * Due to this problem, we might experience lower throughput. The | |
2561 | * suggested workaround is to disable DCTL[12:9] bits if we're | |
2562 | * transitioning from U1/U2 to U0 and enable those bits again | |
2563 | * after a transfer completes and there are no pending transfers | |
2564 | * on any of the enabled endpoints. | |
2565 | * | |
2566 | * This is the first half of that workaround. | |
2567 | * | |
2568 | * Refers to: | |
2569 | * | |
2570 | * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us | |
2571 | * core send LGO_Ux entering U0 | |
2572 | */ | |
2573 | if (dwc->revision < DWC3_REVISION_183A) { | |
2574 | if (next == DWC3_LINK_STATE_U0) { | |
2575 | u32 u1u2; | |
2576 | u32 reg; | |
2577 | ||
2578 | switch (dwc->link_state) { | |
2579 | case DWC3_LINK_STATE_U1: | |
2580 | case DWC3_LINK_STATE_U2: | |
2581 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2582 | u1u2 = reg & (DWC3_DCTL_INITU2ENA | |
2583 | | DWC3_DCTL_ACCEPTU2ENA | |
2584 | | DWC3_DCTL_INITU1ENA | |
2585 | | DWC3_DCTL_ACCEPTU1ENA); | |
2586 | ||
2587 | if (!dwc->u1u2) | |
2588 | dwc->u1u2 = reg & u1u2; | |
2589 | ||
2590 | reg &= ~u1u2; | |
2591 | ||
2592 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
2593 | break; | |
2594 | default: | |
2595 | /* do nothing */ | |
2596 | break; | |
2597 | } | |
2598 | } | |
2599 | } | |
2600 | ||
2601 | switch (next) { | |
2602 | case DWC3_LINK_STATE_U1: | |
2603 | if (dwc->speed == USB_SPEED_SUPER) | |
2604 | dwc3_suspend_gadget(dwc); | |
2605 | break; | |
2606 | case DWC3_LINK_STATE_U2: | |
2607 | case DWC3_LINK_STATE_U3: | |
2608 | dwc3_suspend_gadget(dwc); | |
2609 | break; | |
2610 | case DWC3_LINK_STATE_RESUME: | |
2611 | dwc3_resume_gadget(dwc); | |
2612 | break; | |
2613 | default: | |
2614 | /* do nothing */ | |
2615 | break; | |
2616 | } | |
2617 | ||
2618 | dwc->link_state = next; | |
2619 | } | |
2620 | ||
2621 | static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc, | |
2622 | unsigned int evtinfo) | |
2623 | { | |
2624 | enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK; | |
2625 | ||
2626 | if (dwc->link_state != next && next == DWC3_LINK_STATE_U3) | |
2627 | dwc3_suspend_gadget(dwc); | |
2628 | ||
2629 | dwc->link_state = next; | |
2630 | } | |
2631 | ||
2632 | static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc, | |
2633 | unsigned int evtinfo) | |
2634 | { | |
2635 | unsigned int is_ss = evtinfo & BIT(4); | |
2636 | ||
2637 | /** | |
2638 | * WORKAROUND: DWC3 revison 2.20a with hibernation support | |
2639 | * have a known issue which can cause USB CV TD.9.23 to fail | |
2640 | * randomly. | |
2641 | * | |
2642 | * Because of this issue, core could generate bogus hibernation | |
2643 | * events which SW needs to ignore. | |
2644 | * | |
2645 | * Refers to: | |
2646 | * | |
2647 | * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0 | |
2648 | * Device Fallback from SuperSpeed | |
2649 | */ | |
2650 | if (is_ss ^ (dwc->speed == USB_SPEED_SUPER)) | |
2651 | return; | |
2652 | ||
2653 | /* enter hibernation here */ | |
2654 | } | |
2655 | ||
2656 | static void dwc3_gadget_interrupt(struct dwc3 *dwc, | |
2657 | const struct dwc3_event_devt *event) | |
2658 | { | |
2659 | switch (event->type) { | |
2660 | case DWC3_DEVICE_EVENT_DISCONNECT: | |
2661 | dwc3_gadget_disconnect_interrupt(dwc); | |
2662 | break; | |
2663 | case DWC3_DEVICE_EVENT_RESET: | |
2664 | dwc3_gadget_reset_interrupt(dwc); | |
2665 | break; | |
2666 | case DWC3_DEVICE_EVENT_CONNECT_DONE: | |
2667 | dwc3_gadget_conndone_interrupt(dwc); | |
2668 | break; | |
2669 | case DWC3_DEVICE_EVENT_WAKEUP: | |
2670 | dwc3_gadget_wakeup_interrupt(dwc); | |
2671 | break; | |
2672 | case DWC3_DEVICE_EVENT_HIBER_REQ: | |
2673 | if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation, | |
2674 | "unexpected hibernation event\n")) | |
2675 | break; | |
2676 | ||
2677 | dwc3_gadget_hibernation_interrupt(dwc, event->event_info); | |
2678 | break; | |
2679 | case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE: | |
2680 | dwc3_gadget_linksts_change_interrupt(dwc, event->event_info); | |
2681 | break; | |
2682 | case DWC3_DEVICE_EVENT_EOPF: | |
2683 | /* It changed to be suspend event for version 2.30a and above */ | |
2684 | if (dwc->revision < DWC3_REVISION_230A) { | |
2685 | dwc3_trace(trace_dwc3_gadget, "End of Periodic Frame"); | |
2686 | } else { | |
2687 | dwc3_trace(trace_dwc3_gadget, "U3/L1-L2 Suspend Event"); | |
2688 | ||
2689 | /* | |
2690 | * Ignore suspend event until the gadget enters into | |
2691 | * USB_STATE_CONFIGURED state. | |
2692 | */ | |
2693 | if (dwc->gadget.state >= USB_STATE_CONFIGURED) | |
2694 | dwc3_gadget_suspend_interrupt(dwc, | |
2695 | event->event_info); | |
2696 | } | |
2697 | break; | |
2698 | case DWC3_DEVICE_EVENT_SOF: | |
2699 | dwc3_trace(trace_dwc3_gadget, "Start of Periodic Frame"); | |
2700 | break; | |
2701 | case DWC3_DEVICE_EVENT_ERRATIC_ERROR: | |
2702 | dwc3_trace(trace_dwc3_gadget, "Erratic Error"); | |
2703 | break; | |
2704 | case DWC3_DEVICE_EVENT_CMD_CMPL: | |
2705 | dwc3_trace(trace_dwc3_gadget, "Command Complete"); | |
2706 | break; | |
2707 | case DWC3_DEVICE_EVENT_OVERFLOW: | |
2708 | dwc3_trace(trace_dwc3_gadget, "Overflow"); | |
2709 | break; | |
2710 | default: | |
2711 | dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type); | |
2712 | } | |
2713 | } | |
2714 | ||
2715 | static void dwc3_process_event_entry(struct dwc3 *dwc, | |
2716 | const union dwc3_event *event) | |
2717 | { | |
2718 | trace_dwc3_event(event->raw); | |
2719 | ||
2720 | /* Endpoint IRQ, handle it and return early */ | |
2721 | if (event->type.is_devspec == 0) { | |
2722 | /* depevt */ | |
2723 | return dwc3_endpoint_interrupt(dwc, &event->depevt); | |
2724 | } | |
2725 | ||
2726 | switch (event->type.type) { | |
2727 | case DWC3_EVENT_TYPE_DEV: | |
2728 | dwc3_gadget_interrupt(dwc, &event->devt); | |
2729 | break; | |
2730 | /* REVISIT what to do with Carkit and I2C events ? */ | |
2731 | default: | |
2732 | dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw); | |
2733 | } | |
2734 | } | |
2735 | ||
2736 | static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt) | |
2737 | { | |
2738 | struct dwc3 *dwc = evt->dwc; | |
2739 | irqreturn_t ret = IRQ_NONE; | |
2740 | int left; | |
2741 | u32 reg; | |
2742 | ||
2743 | left = evt->count; | |
2744 | ||
2745 | if (!(evt->flags & DWC3_EVENT_PENDING)) | |
2746 | return IRQ_NONE; | |
2747 | ||
2748 | while (left > 0) { | |
2749 | union dwc3_event event; | |
2750 | ||
2751 | event.raw = *(u32 *) (evt->buf + evt->lpos); | |
2752 | ||
2753 | dwc3_process_event_entry(dwc, &event); | |
2754 | ||
2755 | /* | |
2756 | * FIXME we wrap around correctly to the next entry as | |
2757 | * almost all entries are 4 bytes in size. There is one | |
2758 | * entry which has 12 bytes which is a regular entry | |
2759 | * followed by 8 bytes data. ATM I don't know how | |
2760 | * things are organized if we get next to the a | |
2761 | * boundary so I worry about that once we try to handle | |
2762 | * that. | |
2763 | */ | |
2764 | evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE; | |
2765 | left -= 4; | |
2766 | ||
2767 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 4); | |
2768 | } | |
2769 | ||
2770 | evt->count = 0; | |
2771 | evt->flags &= ~DWC3_EVENT_PENDING; | |
2772 | ret = IRQ_HANDLED; | |
2773 | ||
2774 | /* Unmask interrupt */ | |
2775 | reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0)); | |
2776 | reg &= ~DWC3_GEVNTSIZ_INTMASK; | |
2777 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg); | |
2778 | ||
2779 | return ret; | |
2780 | } | |
2781 | ||
2782 | static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt) | |
2783 | { | |
2784 | struct dwc3_event_buffer *evt = _evt; | |
2785 | struct dwc3 *dwc = evt->dwc; | |
2786 | unsigned long flags; | |
2787 | irqreturn_t ret = IRQ_NONE; | |
2788 | ||
2789 | spin_lock_irqsave(&dwc->lock, flags); | |
2790 | ret = dwc3_process_event_buf(evt); | |
2791 | spin_unlock_irqrestore(&dwc->lock, flags); | |
2792 | ||
2793 | return ret; | |
2794 | } | |
2795 | ||
2796 | static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt) | |
2797 | { | |
2798 | struct dwc3 *dwc = evt->dwc; | |
2799 | u32 count; | |
2800 | u32 reg; | |
2801 | ||
2802 | if (pm_runtime_suspended(dwc->dev)) { | |
2803 | pm_runtime_get(dwc->dev); | |
2804 | disable_irq_nosync(dwc->irq_gadget); | |
2805 | dwc->pending_events = true; | |
2806 | return IRQ_HANDLED; | |
2807 | } | |
2808 | ||
2809 | count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0)); | |
2810 | count &= DWC3_GEVNTCOUNT_MASK; | |
2811 | if (!count) | |
2812 | return IRQ_NONE; | |
2813 | ||
2814 | evt->count = count; | |
2815 | evt->flags |= DWC3_EVENT_PENDING; | |
2816 | ||
2817 | /* Mask interrupt */ | |
2818 | reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0)); | |
2819 | reg |= DWC3_GEVNTSIZ_INTMASK; | |
2820 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg); | |
2821 | ||
2822 | return IRQ_WAKE_THREAD; | |
2823 | } | |
2824 | ||
2825 | static irqreturn_t dwc3_interrupt(int irq, void *_evt) | |
2826 | { | |
2827 | struct dwc3_event_buffer *evt = _evt; | |
2828 | ||
2829 | return dwc3_check_event_buf(evt); | |
2830 | } | |
2831 | ||
2832 | /** | |
2833 | * dwc3_gadget_init - Initializes gadget related registers | |
2834 | * @dwc: pointer to our controller context structure | |
2835 | * | |
2836 | * Returns 0 on success otherwise negative errno. | |
2837 | */ | |
2838 | int dwc3_gadget_init(struct dwc3 *dwc) | |
2839 | { | |
2840 | int ret, irq; | |
2841 | struct platform_device *dwc3_pdev = to_platform_device(dwc->dev); | |
2842 | ||
2843 | irq = platform_get_irq_byname(dwc3_pdev, "peripheral"); | |
2844 | if (irq == -EPROBE_DEFER) | |
2845 | return irq; | |
2846 | ||
2847 | if (irq <= 0) { | |
2848 | irq = platform_get_irq_byname(dwc3_pdev, "dwc_usb3"); | |
2849 | if (irq == -EPROBE_DEFER) | |
2850 | return irq; | |
2851 | ||
2852 | if (irq <= 0) { | |
2853 | irq = platform_get_irq(dwc3_pdev, 0); | |
2854 | if (irq <= 0) { | |
2855 | if (irq != -EPROBE_DEFER) { | |
2856 | dev_err(dwc->dev, | |
2857 | "missing peripheral IRQ\n"); | |
2858 | } | |
2859 | if (!irq) | |
2860 | irq = -EINVAL; | |
2861 | return irq; | |
2862 | } | |
2863 | } | |
2864 | } | |
2865 | ||
2866 | dwc->irq_gadget = irq; | |
2867 | ||
2868 | dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req), | |
2869 | &dwc->ctrl_req_addr, GFP_KERNEL); | |
2870 | if (!dwc->ctrl_req) { | |
2871 | dev_err(dwc->dev, "failed to allocate ctrl request\n"); | |
2872 | ret = -ENOMEM; | |
2873 | goto err0; | |
2874 | } | |
2875 | ||
2876 | dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2, | |
2877 | &dwc->ep0_trb_addr, GFP_KERNEL); | |
2878 | if (!dwc->ep0_trb) { | |
2879 | dev_err(dwc->dev, "failed to allocate ep0 trb\n"); | |
2880 | ret = -ENOMEM; | |
2881 | goto err1; | |
2882 | } | |
2883 | ||
2884 | dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL); | |
2885 | if (!dwc->setup_buf) { | |
2886 | ret = -ENOMEM; | |
2887 | goto err2; | |
2888 | } | |
2889 | ||
2890 | dwc->ep0_bounce = dma_alloc_coherent(dwc->dev, | |
2891 | DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr, | |
2892 | GFP_KERNEL); | |
2893 | if (!dwc->ep0_bounce) { | |
2894 | dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n"); | |
2895 | ret = -ENOMEM; | |
2896 | goto err3; | |
2897 | } | |
2898 | ||
2899 | dwc->zlp_buf = kzalloc(DWC3_ZLP_BUF_SIZE, GFP_KERNEL); | |
2900 | if (!dwc->zlp_buf) { | |
2901 | ret = -ENOMEM; | |
2902 | goto err4; | |
2903 | } | |
2904 | ||
2905 | dwc->gadget.ops = &dwc3_gadget_ops; | |
2906 | dwc->gadget.speed = USB_SPEED_UNKNOWN; | |
2907 | dwc->gadget.sg_supported = true; | |
2908 | dwc->gadget.name = "dwc3-gadget"; | |
2909 | dwc->gadget.is_otg = dwc->dr_mode == USB_DR_MODE_OTG; | |
2910 | ||
2911 | /* | |
2912 | * FIXME We might be setting max_speed to <SUPER, however versions | |
2913 | * <2.20a of dwc3 have an issue with metastability (documented | |
2914 | * elsewhere in this driver) which tells us we can't set max speed to | |
2915 | * anything lower than SUPER. | |
2916 | * | |
2917 | * Because gadget.max_speed is only used by composite.c and function | |
2918 | * drivers (i.e. it won't go into dwc3's registers) we are allowing this | |
2919 | * to happen so we avoid sending SuperSpeed Capability descriptor | |
2920 | * together with our BOS descriptor as that could confuse host into | |
2921 | * thinking we can handle super speed. | |
2922 | * | |
2923 | * Note that, in fact, we won't even support GetBOS requests when speed | |
2924 | * is less than super speed because we don't have means, yet, to tell | |
2925 | * composite.c that we are USB 2.0 + LPM ECN. | |
2926 | */ | |
2927 | if (dwc->revision < DWC3_REVISION_220A) | |
2928 | dwc3_trace(trace_dwc3_gadget, | |
2929 | "Changing max_speed on rev %08x", | |
2930 | dwc->revision); | |
2931 | ||
2932 | dwc->gadget.max_speed = dwc->maximum_speed; | |
2933 | ||
2934 | /* | |
2935 | * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize | |
2936 | * on ep out. | |
2937 | */ | |
2938 | dwc->gadget.quirk_ep_out_aligned_size = true; | |
2939 | ||
2940 | /* | |
2941 | * REVISIT: Here we should clear all pending IRQs to be | |
2942 | * sure we're starting from a well known location. | |
2943 | */ | |
2944 | ||
2945 | ret = dwc3_gadget_init_endpoints(dwc); | |
2946 | if (ret) | |
2947 | goto err5; | |
2948 | ||
2949 | ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget); | |
2950 | if (ret) { | |
2951 | dev_err(dwc->dev, "failed to register udc\n"); | |
2952 | goto err5; | |
2953 | } | |
2954 | ||
2955 | return 0; | |
2956 | ||
2957 | err5: | |
2958 | kfree(dwc->zlp_buf); | |
2959 | ||
2960 | err4: | |
2961 | dwc3_gadget_free_endpoints(dwc); | |
2962 | dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE, | |
2963 | dwc->ep0_bounce, dwc->ep0_bounce_addr); | |
2964 | ||
2965 | err3: | |
2966 | kfree(dwc->setup_buf); | |
2967 | ||
2968 | err2: | |
2969 | dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb), | |
2970 | dwc->ep0_trb, dwc->ep0_trb_addr); | |
2971 | ||
2972 | err1: | |
2973 | dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req), | |
2974 | dwc->ctrl_req, dwc->ctrl_req_addr); | |
2975 | ||
2976 | err0: | |
2977 | return ret; | |
2978 | } | |
2979 | ||
2980 | /* -------------------------------------------------------------------------- */ | |
2981 | ||
2982 | void dwc3_gadget_exit(struct dwc3 *dwc) | |
2983 | { | |
2984 | usb_del_gadget_udc(&dwc->gadget); | |
2985 | ||
2986 | dwc3_gadget_free_endpoints(dwc); | |
2987 | ||
2988 | dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE, | |
2989 | dwc->ep0_bounce, dwc->ep0_bounce_addr); | |
2990 | ||
2991 | kfree(dwc->setup_buf); | |
2992 | kfree(dwc->zlp_buf); | |
2993 | ||
2994 | dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb), | |
2995 | dwc->ep0_trb, dwc->ep0_trb_addr); | |
2996 | ||
2997 | dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req), | |
2998 | dwc->ctrl_req, dwc->ctrl_req_addr); | |
2999 | } | |
3000 | ||
3001 | int dwc3_gadget_suspend(struct dwc3 *dwc) | |
3002 | { | |
3003 | int ret; | |
3004 | ||
3005 | if (!dwc->gadget_driver) | |
3006 | return 0; | |
3007 | ||
3008 | ret = dwc3_gadget_run_stop(dwc, false, false); | |
3009 | if (ret < 0) | |
3010 | return ret; | |
3011 | ||
3012 | dwc3_disconnect_gadget(dwc); | |
3013 | __dwc3_gadget_stop(dwc); | |
3014 | ||
3015 | return 0; | |
3016 | } | |
3017 | ||
3018 | int dwc3_gadget_resume(struct dwc3 *dwc) | |
3019 | { | |
3020 | int ret; | |
3021 | ||
3022 | if (!dwc->gadget_driver) | |
3023 | return 0; | |
3024 | ||
3025 | ret = __dwc3_gadget_start(dwc); | |
3026 | if (ret < 0) | |
3027 | goto err0; | |
3028 | ||
3029 | ret = dwc3_gadget_run_stop(dwc, true, false); | |
3030 | if (ret < 0) | |
3031 | goto err1; | |
3032 | ||
3033 | return 0; | |
3034 | ||
3035 | err1: | |
3036 | __dwc3_gadget_stop(dwc); | |
3037 | ||
3038 | err0: | |
3039 | return ret; | |
3040 | } | |
3041 | ||
3042 | void dwc3_gadget_process_pending_events(struct dwc3 *dwc) | |
3043 | { | |
3044 | if (dwc->pending_events) { | |
3045 | dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf); | |
3046 | dwc->pending_events = false; | |
3047 | enable_irq(dwc->irq_gadget); | |
3048 | } | |
3049 | } |