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1 | /* | |
2 | * MUSB OTG driver peripheral support | |
3 | * | |
4 | * Copyright 2005 Mentor Graphics Corporation | |
5 | * Copyright (C) 2005-2006 by Texas Instruments | |
6 | * Copyright (C) 2006-2007 Nokia Corporation | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License | |
10 | * version 2 as published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but | |
13 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
20 | * 02110-1301 USA | |
21 | * | |
22 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED | |
23 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
24 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
25 | * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, | |
26 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
27 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | |
28 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | |
29 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
30 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
31 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
32 | * | |
33 | */ | |
34 | ||
35 | #include <linux/kernel.h> | |
36 | #include <linux/list.h> | |
37 | #include <linux/timer.h> | |
38 | #include <linux/module.h> | |
39 | #include <linux/smp.h> | |
40 | #include <linux/spinlock.h> | |
41 | #include <linux/delay.h> | |
42 | #include <linux/moduleparam.h> | |
43 | #include <linux/stat.h> | |
44 | #include <linux/dma-mapping.h> | |
45 | ||
46 | #include "musb_core.h" | |
47 | ||
48 | ||
49 | /* MUSB PERIPHERAL status 3-mar-2006: | |
50 | * | |
51 | * - EP0 seems solid. It passes both USBCV and usbtest control cases. | |
52 | * Minor glitches: | |
53 | * | |
54 | * + remote wakeup to Linux hosts work, but saw USBCV failures; | |
55 | * in one test run (operator error?) | |
56 | * + endpoint halt tests -- in both usbtest and usbcv -- seem | |
57 | * to break when dma is enabled ... is something wrongly | |
58 | * clearing SENDSTALL? | |
59 | * | |
60 | * - Mass storage behaved ok when last tested. Network traffic patterns | |
61 | * (with lots of short transfers etc) need retesting; they turn up the | |
62 | * worst cases of the DMA, since short packets are typical but are not | |
63 | * required. | |
64 | * | |
65 | * - TX/IN | |
66 | * + both pio and dma behave in with network and g_zero tests | |
67 | * + no cppi throughput issues other than no-hw-queueing | |
68 | * + failed with FLAT_REG (DaVinci) | |
69 | * + seems to behave with double buffering, PIO -and- CPPI | |
70 | * + with gadgetfs + AIO, requests got lost? | |
71 | * | |
72 | * - RX/OUT | |
73 | * + both pio and dma behave in with network and g_zero tests | |
74 | * + dma is slow in typical case (short_not_ok is clear) | |
75 | * + double buffering ok with PIO | |
76 | * + double buffering *FAILS* with CPPI, wrong data bytes sometimes | |
77 | * + request lossage observed with gadgetfs | |
78 | * | |
79 | * - ISO not tested ... might work, but only weakly isochronous | |
80 | * | |
81 | * - Gadget driver disabling of softconnect during bind() is ignored; so | |
82 | * drivers can't hold off host requests until userspace is ready. | |
83 | * (Workaround: they can turn it off later.) | |
84 | * | |
85 | * - PORTABILITY (assumes PIO works): | |
86 | * + DaVinci, basically works with cppi dma | |
87 | * + OMAP 2430, ditto with mentor dma | |
88 | * + TUSB 6010, platform-specific dma in the works | |
89 | */ | |
90 | ||
91 | /* ----------------------------------------------------------------------- */ | |
92 | ||
93 | /* | |
94 | * Immediately complete a request. | |
95 | * | |
96 | * @param request the request to complete | |
97 | * @param status the status to complete the request with | |
98 | * Context: controller locked, IRQs blocked. | |
99 | */ | |
100 | void musb_g_giveback( | |
101 | struct musb_ep *ep, | |
102 | struct usb_request *request, | |
103 | int status) | |
104 | __releases(ep->musb->lock) | |
105 | __acquires(ep->musb->lock) | |
106 | { | |
107 | struct musb_request *req; | |
108 | struct musb *musb; | |
109 | int busy = ep->busy; | |
110 | ||
111 | req = to_musb_request(request); | |
112 | ||
113 | list_del(&request->list); | |
114 | if (req->request.status == -EINPROGRESS) | |
115 | req->request.status = status; | |
116 | musb = req->musb; | |
117 | ||
118 | ep->busy = 1; | |
119 | spin_unlock(&musb->lock); | |
120 | if (is_dma_capable()) { | |
121 | if (req->mapped) { | |
122 | dma_unmap_single(musb->controller, | |
123 | req->request.dma, | |
124 | req->request.length, | |
125 | req->tx | |
126 | ? DMA_TO_DEVICE | |
127 | : DMA_FROM_DEVICE); | |
128 | req->request.dma = DMA_ADDR_INVALID; | |
129 | req->mapped = 0; | |
130 | } else if (req->request.dma != DMA_ADDR_INVALID) | |
131 | dma_sync_single_for_cpu(musb->controller, | |
132 | req->request.dma, | |
133 | req->request.length, | |
134 | req->tx | |
135 | ? DMA_TO_DEVICE | |
136 | : DMA_FROM_DEVICE); | |
137 | } | |
138 | if (request->status == 0) | |
139 | DBG(5, "%s done request %p, %d/%d\n", | |
140 | ep->end_point.name, request, | |
141 | req->request.actual, req->request.length); | |
142 | else | |
143 | DBG(2, "%s request %p, %d/%d fault %d\n", | |
144 | ep->end_point.name, request, | |
145 | req->request.actual, req->request.length, | |
146 | request->status); | |
147 | req->request.complete(&req->ep->end_point, &req->request); | |
148 | spin_lock(&musb->lock); | |
149 | ep->busy = busy; | |
150 | } | |
151 | ||
152 | /* ----------------------------------------------------------------------- */ | |
153 | ||
154 | /* | |
155 | * Abort requests queued to an endpoint using the status. Synchronous. | |
156 | * caller locked controller and blocked irqs, and selected this ep. | |
157 | */ | |
158 | static void nuke(struct musb_ep *ep, const int status) | |
159 | { | |
160 | struct musb_request *req = NULL; | |
161 | void __iomem *epio = ep->musb->endpoints[ep->current_epnum].regs; | |
162 | ||
163 | ep->busy = 1; | |
164 | ||
165 | if (is_dma_capable() && ep->dma) { | |
166 | struct dma_controller *c = ep->musb->dma_controller; | |
167 | int value; | |
168 | ||
169 | if (ep->is_in) { | |
170 | /* | |
171 | * The programming guide says that we must not clear | |
172 | * the DMAMODE bit before DMAENAB, so we only | |
173 | * clear it in the second write... | |
174 | */ | |
175 | musb_writew(epio, MUSB_TXCSR, | |
176 | MUSB_TXCSR_DMAMODE | MUSB_TXCSR_FLUSHFIFO); | |
177 | musb_writew(epio, MUSB_TXCSR, | |
178 | 0 | MUSB_TXCSR_FLUSHFIFO); | |
179 | } else { | |
180 | musb_writew(epio, MUSB_RXCSR, | |
181 | 0 | MUSB_RXCSR_FLUSHFIFO); | |
182 | musb_writew(epio, MUSB_RXCSR, | |
183 | 0 | MUSB_RXCSR_FLUSHFIFO); | |
184 | } | |
185 | ||
186 | value = c->channel_abort(ep->dma); | |
187 | DBG(value ? 1 : 6, "%s: abort DMA --> %d\n", ep->name, value); | |
188 | c->channel_release(ep->dma); | |
189 | ep->dma = NULL; | |
190 | } | |
191 | ||
192 | while (!list_empty(&(ep->req_list))) { | |
193 | req = container_of(ep->req_list.next, struct musb_request, | |
194 | request.list); | |
195 | musb_g_giveback(ep, &req->request, status); | |
196 | } | |
197 | } | |
198 | ||
199 | /* ----------------------------------------------------------------------- */ | |
200 | ||
201 | /* Data transfers - pure PIO, pure DMA, or mixed mode */ | |
202 | ||
203 | /* | |
204 | * This assumes the separate CPPI engine is responding to DMA requests | |
205 | * from the usb core ... sequenced a bit differently from mentor dma. | |
206 | */ | |
207 | ||
208 | static inline int max_ep_writesize(struct musb *musb, struct musb_ep *ep) | |
209 | { | |
210 | if (can_bulk_split(musb, ep->type)) | |
211 | return ep->hw_ep->max_packet_sz_tx; | |
212 | else | |
213 | return ep->packet_sz; | |
214 | } | |
215 | ||
216 | ||
217 | #ifdef CONFIG_USB_INVENTRA_DMA | |
218 | ||
219 | /* Peripheral tx (IN) using Mentor DMA works as follows: | |
220 | Only mode 0 is used for transfers <= wPktSize, | |
221 | mode 1 is used for larger transfers, | |
222 | ||
223 | One of the following happens: | |
224 | - Host sends IN token which causes an endpoint interrupt | |
225 | -> TxAvail | |
226 | -> if DMA is currently busy, exit. | |
227 | -> if queue is non-empty, txstate(). | |
228 | ||
229 | - Request is queued by the gadget driver. | |
230 | -> if queue was previously empty, txstate() | |
231 | ||
232 | txstate() | |
233 | -> start | |
234 | /\ -> setup DMA | |
235 | | (data is transferred to the FIFO, then sent out when | |
236 | | IN token(s) are recd from Host. | |
237 | | -> DMA interrupt on completion | |
238 | | calls TxAvail. | |
239 | | -> stop DMA, ~DMAENAB, | |
240 | | -> set TxPktRdy for last short pkt or zlp | |
241 | | -> Complete Request | |
242 | | -> Continue next request (call txstate) | |
243 | |___________________________________| | |
244 | ||
245 | * Non-Mentor DMA engines can of course work differently, such as by | |
246 | * upleveling from irq-per-packet to irq-per-buffer. | |
247 | */ | |
248 | ||
249 | #endif | |
250 | ||
251 | /* | |
252 | * An endpoint is transmitting data. This can be called either from | |
253 | * the IRQ routine or from ep.queue() to kickstart a request on an | |
254 | * endpoint. | |
255 | * | |
256 | * Context: controller locked, IRQs blocked, endpoint selected | |
257 | */ | |
258 | static void txstate(struct musb *musb, struct musb_request *req) | |
259 | { | |
260 | u8 epnum = req->epnum; | |
261 | struct musb_ep *musb_ep; | |
262 | void __iomem *epio = musb->endpoints[epnum].regs; | |
263 | struct usb_request *request; | |
264 | u16 fifo_count = 0, csr; | |
265 | int use_dma = 0; | |
266 | ||
267 | musb_ep = req->ep; | |
268 | ||
269 | /* we shouldn't get here while DMA is active ... but we do ... */ | |
270 | if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) { | |
271 | DBG(4, "dma pending...\n"); | |
272 | return; | |
273 | } | |
274 | ||
275 | /* read TXCSR before */ | |
276 | csr = musb_readw(epio, MUSB_TXCSR); | |
277 | ||
278 | request = &req->request; | |
279 | fifo_count = min(max_ep_writesize(musb, musb_ep), | |
280 | (int)(request->length - request->actual)); | |
281 | ||
282 | if (csr & MUSB_TXCSR_TXPKTRDY) { | |
283 | DBG(5, "%s old packet still ready , txcsr %03x\n", | |
284 | musb_ep->end_point.name, csr); | |
285 | return; | |
286 | } | |
287 | ||
288 | if (csr & MUSB_TXCSR_P_SENDSTALL) { | |
289 | DBG(5, "%s stalling, txcsr %03x\n", | |
290 | musb_ep->end_point.name, csr); | |
291 | return; | |
292 | } | |
293 | ||
294 | DBG(4, "hw_ep%d, maxpacket %d, fifo count %d, txcsr %03x\n", | |
295 | epnum, musb_ep->packet_sz, fifo_count, | |
296 | csr); | |
297 | ||
298 | #ifndef CONFIG_MUSB_PIO_ONLY | |
299 | if (is_dma_capable() && musb_ep->dma) { | |
300 | struct dma_controller *c = musb->dma_controller; | |
301 | ||
302 | use_dma = (request->dma != DMA_ADDR_INVALID); | |
303 | ||
304 | /* MUSB_TXCSR_P_ISO is still set correctly */ | |
305 | ||
306 | #ifdef CONFIG_USB_INVENTRA_DMA | |
307 | { | |
308 | size_t request_size; | |
309 | ||
310 | /* setup DMA, then program endpoint CSR */ | |
311 | request_size = min(request->length, | |
312 | musb_ep->dma->max_len); | |
313 | if (request_size <= musb_ep->packet_sz) | |
314 | musb_ep->dma->desired_mode = 0; | |
315 | else | |
316 | musb_ep->dma->desired_mode = 1; | |
317 | ||
318 | use_dma = use_dma && c->channel_program( | |
319 | musb_ep->dma, musb_ep->packet_sz, | |
320 | musb_ep->dma->desired_mode, | |
321 | request->dma, request_size); | |
322 | if (use_dma) { | |
323 | if (musb_ep->dma->desired_mode == 0) { | |
324 | /* | |
325 | * We must not clear the DMAMODE bit | |
326 | * before the DMAENAB bit -- and the | |
327 | * latter doesn't always get cleared | |
328 | * before we get here... | |
329 | */ | |
330 | csr &= ~(MUSB_TXCSR_AUTOSET | |
331 | | MUSB_TXCSR_DMAENAB); | |
332 | musb_writew(epio, MUSB_TXCSR, csr | |
333 | | MUSB_TXCSR_P_WZC_BITS); | |
334 | csr &= ~MUSB_TXCSR_DMAMODE; | |
335 | csr |= (MUSB_TXCSR_DMAENAB | | |
336 | MUSB_TXCSR_MODE); | |
337 | /* against programming guide */ | |
338 | } else | |
339 | csr |= (MUSB_TXCSR_AUTOSET | |
340 | | MUSB_TXCSR_DMAENAB | |
341 | | MUSB_TXCSR_DMAMODE | |
342 | | MUSB_TXCSR_MODE); | |
343 | ||
344 | csr &= ~MUSB_TXCSR_P_UNDERRUN; | |
345 | musb_writew(epio, MUSB_TXCSR, csr); | |
346 | } | |
347 | } | |
348 | ||
349 | #elif defined(CONFIG_USB_TI_CPPI_DMA) | |
350 | /* program endpoint CSR first, then setup DMA */ | |
351 | csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY); | |
352 | csr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_DMAMODE | | |
353 | MUSB_TXCSR_MODE; | |
354 | musb_writew(epio, MUSB_TXCSR, | |
355 | (MUSB_TXCSR_P_WZC_BITS & ~MUSB_TXCSR_P_UNDERRUN) | |
356 | | csr); | |
357 | ||
358 | /* ensure writebuffer is empty */ | |
359 | csr = musb_readw(epio, MUSB_TXCSR); | |
360 | ||
361 | /* NOTE host side sets DMAENAB later than this; both are | |
362 | * OK since the transfer dma glue (between CPPI and Mentor | |
363 | * fifos) just tells CPPI it could start. Data only moves | |
364 | * to the USB TX fifo when both fifos are ready. | |
365 | */ | |
366 | ||
367 | /* "mode" is irrelevant here; handle terminating ZLPs like | |
368 | * PIO does, since the hardware RNDIS mode seems unreliable | |
369 | * except for the last-packet-is-already-short case. | |
370 | */ | |
371 | use_dma = use_dma && c->channel_program( | |
372 | musb_ep->dma, musb_ep->packet_sz, | |
373 | 0, | |
374 | request->dma, | |
375 | request->length); | |
376 | if (!use_dma) { | |
377 | c->channel_release(musb_ep->dma); | |
378 | musb_ep->dma = NULL; | |
379 | csr &= ~MUSB_TXCSR_DMAENAB; | |
380 | musb_writew(epio, MUSB_TXCSR, csr); | |
381 | /* invariant: prequest->buf is non-null */ | |
382 | } | |
383 | #elif defined(CONFIG_USB_TUSB_OMAP_DMA) | |
384 | use_dma = use_dma && c->channel_program( | |
385 | musb_ep->dma, musb_ep->packet_sz, | |
386 | request->zero, | |
387 | request->dma, | |
388 | request->length); | |
389 | #endif | |
390 | } | |
391 | #endif | |
392 | ||
393 | if (!use_dma) { | |
394 | musb_write_fifo(musb_ep->hw_ep, fifo_count, | |
395 | (u8 *) (request->buf + request->actual)); | |
396 | request->actual += fifo_count; | |
397 | csr |= MUSB_TXCSR_TXPKTRDY; | |
398 | csr &= ~MUSB_TXCSR_P_UNDERRUN; | |
399 | musb_writew(epio, MUSB_TXCSR, csr); | |
400 | } | |
401 | ||
402 | /* host may already have the data when this message shows... */ | |
403 | DBG(3, "%s TX/IN %s len %d/%d, txcsr %04x, fifo %d/%d\n", | |
404 | musb_ep->end_point.name, use_dma ? "dma" : "pio", | |
405 | request->actual, request->length, | |
406 | musb_readw(epio, MUSB_TXCSR), | |
407 | fifo_count, | |
408 | musb_readw(epio, MUSB_TXMAXP)); | |
409 | } | |
410 | ||
411 | /* | |
412 | * FIFO state update (e.g. data ready). | |
413 | * Called from IRQ, with controller locked. | |
414 | */ | |
415 | void musb_g_tx(struct musb *musb, u8 epnum) | |
416 | { | |
417 | u16 csr; | |
418 | struct usb_request *request; | |
419 | u8 __iomem *mbase = musb->mregs; | |
420 | struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_in; | |
421 | void __iomem *epio = musb->endpoints[epnum].regs; | |
422 | struct dma_channel *dma; | |
423 | ||
424 | musb_ep_select(mbase, epnum); | |
425 | request = next_request(musb_ep); | |
426 | ||
427 | csr = musb_readw(epio, MUSB_TXCSR); | |
428 | DBG(4, "<== %s, txcsr %04x\n", musb_ep->end_point.name, csr); | |
429 | ||
430 | dma = is_dma_capable() ? musb_ep->dma : NULL; | |
431 | do { | |
432 | /* REVISIT for high bandwidth, MUSB_TXCSR_P_INCOMPTX | |
433 | * probably rates reporting as a host error | |
434 | */ | |
435 | if (csr & MUSB_TXCSR_P_SENTSTALL) { | |
436 | csr |= MUSB_TXCSR_P_WZC_BITS; | |
437 | csr &= ~MUSB_TXCSR_P_SENTSTALL; | |
438 | musb_writew(epio, MUSB_TXCSR, csr); | |
439 | if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { | |
440 | dma->status = MUSB_DMA_STATUS_CORE_ABORT; | |
441 | musb->dma_controller->channel_abort(dma); | |
442 | } | |
443 | ||
444 | if (request) | |
445 | musb_g_giveback(musb_ep, request, -EPIPE); | |
446 | ||
447 | break; | |
448 | } | |
449 | ||
450 | if (csr & MUSB_TXCSR_P_UNDERRUN) { | |
451 | /* we NAKed, no big deal ... little reason to care */ | |
452 | csr |= MUSB_TXCSR_P_WZC_BITS; | |
453 | csr &= ~(MUSB_TXCSR_P_UNDERRUN | |
454 | | MUSB_TXCSR_TXPKTRDY); | |
455 | musb_writew(epio, MUSB_TXCSR, csr); | |
456 | DBG(20, "underrun on ep%d, req %p\n", epnum, request); | |
457 | } | |
458 | ||
459 | if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { | |
460 | /* SHOULD NOT HAPPEN ... has with cppi though, after | |
461 | * changing SENDSTALL (and other cases); harmless? | |
462 | */ | |
463 | DBG(5, "%s dma still busy?\n", musb_ep->end_point.name); | |
464 | break; | |
465 | } | |
466 | ||
467 | if (request) { | |
468 | u8 is_dma = 0; | |
469 | ||
470 | if (dma && (csr & MUSB_TXCSR_DMAENAB)) { | |
471 | is_dma = 1; | |
472 | csr |= MUSB_TXCSR_P_WZC_BITS; | |
473 | csr &= ~(MUSB_TXCSR_DMAENAB | |
474 | | MUSB_TXCSR_P_UNDERRUN | |
475 | | MUSB_TXCSR_TXPKTRDY); | |
476 | musb_writew(epio, MUSB_TXCSR, csr); | |
477 | /* ensure writebuffer is empty */ | |
478 | csr = musb_readw(epio, MUSB_TXCSR); | |
479 | request->actual += musb_ep->dma->actual_len; | |
480 | DBG(4, "TXCSR%d %04x, dma off, " | |
481 | "len %zu, req %p\n", | |
482 | epnum, csr, | |
483 | musb_ep->dma->actual_len, | |
484 | request); | |
485 | } | |
486 | ||
487 | if (is_dma || request->actual == request->length) { | |
488 | ||
489 | /* First, maybe a terminating short packet. | |
490 | * Some DMA engines might handle this by | |
491 | * themselves. | |
492 | */ | |
493 | if ((request->zero | |
494 | && request->length | |
495 | && (request->length | |
496 | % musb_ep->packet_sz) | |
497 | == 0) | |
498 | #ifdef CONFIG_USB_INVENTRA_DMA | |
499 | || (is_dma && | |
500 | ((!dma->desired_mode) || | |
501 | (request->actual & | |
502 | (musb_ep->packet_sz - 1)))) | |
503 | #endif | |
504 | ) { | |
505 | /* on dma completion, fifo may not | |
506 | * be available yet ... | |
507 | */ | |
508 | if (csr & MUSB_TXCSR_TXPKTRDY) | |
509 | break; | |
510 | ||
511 | DBG(4, "sending zero pkt\n"); | |
512 | musb_writew(epio, MUSB_TXCSR, | |
513 | MUSB_TXCSR_MODE | |
514 | | MUSB_TXCSR_TXPKTRDY); | |
515 | request->zero = 0; | |
516 | } | |
517 | ||
518 | /* ... or if not, then complete it */ | |
519 | musb_g_giveback(musb_ep, request, 0); | |
520 | ||
521 | /* kickstart next transfer if appropriate; | |
522 | * the packet that just completed might not | |
523 | * be transmitted for hours or days. | |
524 | * REVISIT for double buffering... | |
525 | * FIXME revisit for stalls too... | |
526 | */ | |
527 | musb_ep_select(mbase, epnum); | |
528 | csr = musb_readw(epio, MUSB_TXCSR); | |
529 | if (csr & MUSB_TXCSR_FIFONOTEMPTY) | |
530 | break; | |
531 | request = musb_ep->desc | |
532 | ? next_request(musb_ep) | |
533 | : NULL; | |
534 | if (!request) { | |
535 | DBG(4, "%s idle now\n", | |
536 | musb_ep->end_point.name); | |
537 | break; | |
538 | } | |
539 | } | |
540 | ||
541 | txstate(musb, to_musb_request(request)); | |
542 | } | |
543 | ||
544 | } while (0); | |
545 | } | |
546 | ||
547 | /* ------------------------------------------------------------ */ | |
548 | ||
549 | #ifdef CONFIG_USB_INVENTRA_DMA | |
550 | ||
551 | /* Peripheral rx (OUT) using Mentor DMA works as follows: | |
552 | - Only mode 0 is used. | |
553 | ||
554 | - Request is queued by the gadget class driver. | |
555 | -> if queue was previously empty, rxstate() | |
556 | ||
557 | - Host sends OUT token which causes an endpoint interrupt | |
558 | /\ -> RxReady | |
559 | | -> if request queued, call rxstate | |
560 | | /\ -> setup DMA | |
561 | | | -> DMA interrupt on completion | |
562 | | | -> RxReady | |
563 | | | -> stop DMA | |
564 | | | -> ack the read | |
565 | | | -> if data recd = max expected | |
566 | | | by the request, or host | |
567 | | | sent a short packet, | |
568 | | | complete the request, | |
569 | | | and start the next one. | |
570 | | |_____________________________________| | |
571 | | else just wait for the host | |
572 | | to send the next OUT token. | |
573 | |__________________________________________________| | |
574 | ||
575 | * Non-Mentor DMA engines can of course work differently. | |
576 | */ | |
577 | ||
578 | #endif | |
579 | ||
580 | /* | |
581 | * Context: controller locked, IRQs blocked, endpoint selected | |
582 | */ | |
583 | static void rxstate(struct musb *musb, struct musb_request *req) | |
584 | { | |
585 | u16 csr = 0; | |
586 | const u8 epnum = req->epnum; | |
587 | struct usb_request *request = &req->request; | |
588 | struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_out; | |
589 | void __iomem *epio = musb->endpoints[epnum].regs; | |
590 | unsigned fifo_count = 0; | |
591 | u16 len = musb_ep->packet_sz; | |
592 | ||
593 | csr = musb_readw(epio, MUSB_RXCSR); | |
594 | ||
595 | if (is_cppi_enabled() && musb_ep->dma) { | |
596 | struct dma_controller *c = musb->dma_controller; | |
597 | struct dma_channel *channel = musb_ep->dma; | |
598 | ||
599 | /* NOTE: CPPI won't actually stop advancing the DMA | |
600 | * queue after short packet transfers, so this is almost | |
601 | * always going to run as IRQ-per-packet DMA so that | |
602 | * faults will be handled correctly. | |
603 | */ | |
604 | if (c->channel_program(channel, | |
605 | musb_ep->packet_sz, | |
606 | !request->short_not_ok, | |
607 | request->dma + request->actual, | |
608 | request->length - request->actual)) { | |
609 | ||
610 | /* make sure that if an rxpkt arrived after the irq, | |
611 | * the cppi engine will be ready to take it as soon | |
612 | * as DMA is enabled | |
613 | */ | |
614 | csr &= ~(MUSB_RXCSR_AUTOCLEAR | |
615 | | MUSB_RXCSR_DMAMODE); | |
616 | csr |= MUSB_RXCSR_DMAENAB | MUSB_RXCSR_P_WZC_BITS; | |
617 | musb_writew(epio, MUSB_RXCSR, csr); | |
618 | return; | |
619 | } | |
620 | } | |
621 | ||
622 | if (csr & MUSB_RXCSR_RXPKTRDY) { | |
623 | len = musb_readw(epio, MUSB_RXCOUNT); | |
624 | if (request->actual < request->length) { | |
625 | #ifdef CONFIG_USB_INVENTRA_DMA | |
626 | if (is_dma_capable() && musb_ep->dma) { | |
627 | struct dma_controller *c; | |
628 | struct dma_channel *channel; | |
629 | int use_dma = 0; | |
630 | ||
631 | c = musb->dma_controller; | |
632 | channel = musb_ep->dma; | |
633 | ||
634 | /* We use DMA Req mode 0 in rx_csr, and DMA controller operates in | |
635 | * mode 0 only. So we do not get endpoint interrupts due to DMA | |
636 | * completion. We only get interrupts from DMA controller. | |
637 | * | |
638 | * We could operate in DMA mode 1 if we knew the size of the tranfer | |
639 | * in advance. For mass storage class, request->length = what the host | |
640 | * sends, so that'd work. But for pretty much everything else, | |
641 | * request->length is routinely more than what the host sends. For | |
642 | * most these gadgets, end of is signified either by a short packet, | |
643 | * or filling the last byte of the buffer. (Sending extra data in | |
644 | * that last pckate should trigger an overflow fault.) But in mode 1, | |
645 | * we don't get DMA completion interrrupt for short packets. | |
646 | * | |
647 | * Theoretically, we could enable DMAReq irq (MUSB_RXCSR_DMAMODE = 1), | |
648 | * to get endpoint interrupt on every DMA req, but that didn't seem | |
649 | * to work reliably. | |
650 | * | |
651 | * REVISIT an updated g_file_storage can set req->short_not_ok, which | |
652 | * then becomes usable as a runtime "use mode 1" hint... | |
653 | */ | |
654 | ||
655 | csr |= MUSB_RXCSR_DMAENAB; | |
656 | #ifdef USE_MODE1 | |
657 | csr |= MUSB_RXCSR_AUTOCLEAR; | |
658 | /* csr |= MUSB_RXCSR_DMAMODE; */ | |
659 | ||
660 | /* this special sequence (enabling and then | |
661 | * disabling MUSB_RXCSR_DMAMODE) is required | |
662 | * to get DMAReq to activate | |
663 | */ | |
664 | musb_writew(epio, MUSB_RXCSR, | |
665 | csr | MUSB_RXCSR_DMAMODE); | |
666 | #endif | |
667 | musb_writew(epio, MUSB_RXCSR, csr); | |
668 | ||
669 | if (request->actual < request->length) { | |
670 | int transfer_size = 0; | |
671 | #ifdef USE_MODE1 | |
672 | transfer_size = min(request->length, | |
673 | channel->max_len); | |
674 | #else | |
675 | transfer_size = len; | |
676 | #endif | |
677 | if (transfer_size <= musb_ep->packet_sz) | |
678 | musb_ep->dma->desired_mode = 0; | |
679 | else | |
680 | musb_ep->dma->desired_mode = 1; | |
681 | ||
682 | use_dma = c->channel_program( | |
683 | channel, | |
684 | musb_ep->packet_sz, | |
685 | channel->desired_mode, | |
686 | request->dma | |
687 | + request->actual, | |
688 | transfer_size); | |
689 | } | |
690 | ||
691 | if (use_dma) | |
692 | return; | |
693 | } | |
694 | #endif /* Mentor's DMA */ | |
695 | ||
696 | fifo_count = request->length - request->actual; | |
697 | DBG(3, "%s OUT/RX pio fifo %d/%d, maxpacket %d\n", | |
698 | musb_ep->end_point.name, | |
699 | len, fifo_count, | |
700 | musb_ep->packet_sz); | |
701 | ||
702 | fifo_count = min_t(unsigned, len, fifo_count); | |
703 | ||
704 | #ifdef CONFIG_USB_TUSB_OMAP_DMA | |
705 | if (tusb_dma_omap() && musb_ep->dma) { | |
706 | struct dma_controller *c = musb->dma_controller; | |
707 | struct dma_channel *channel = musb_ep->dma; | |
708 | u32 dma_addr = request->dma + request->actual; | |
709 | int ret; | |
710 | ||
711 | ret = c->channel_program(channel, | |
712 | musb_ep->packet_sz, | |
713 | channel->desired_mode, | |
714 | dma_addr, | |
715 | fifo_count); | |
716 | if (ret) | |
717 | return; | |
718 | } | |
719 | #endif | |
720 | ||
721 | musb_read_fifo(musb_ep->hw_ep, fifo_count, (u8 *) | |
722 | (request->buf + request->actual)); | |
723 | request->actual += fifo_count; | |
724 | ||
725 | /* REVISIT if we left anything in the fifo, flush | |
726 | * it and report -EOVERFLOW | |
727 | */ | |
728 | ||
729 | /* ack the read! */ | |
730 | csr |= MUSB_RXCSR_P_WZC_BITS; | |
731 | csr &= ~MUSB_RXCSR_RXPKTRDY; | |
732 | musb_writew(epio, MUSB_RXCSR, csr); | |
733 | } | |
734 | } | |
735 | ||
736 | /* reach the end or short packet detected */ | |
737 | if (request->actual == request->length || len < musb_ep->packet_sz) | |
738 | musb_g_giveback(musb_ep, request, 0); | |
739 | } | |
740 | ||
741 | /* | |
742 | * Data ready for a request; called from IRQ | |
743 | */ | |
744 | void musb_g_rx(struct musb *musb, u8 epnum) | |
745 | { | |
746 | u16 csr; | |
747 | struct usb_request *request; | |
748 | void __iomem *mbase = musb->mregs; | |
749 | struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_out; | |
750 | void __iomem *epio = musb->endpoints[epnum].regs; | |
751 | struct dma_channel *dma; | |
752 | ||
753 | musb_ep_select(mbase, epnum); | |
754 | ||
755 | request = next_request(musb_ep); | |
756 | ||
757 | csr = musb_readw(epio, MUSB_RXCSR); | |
758 | dma = is_dma_capable() ? musb_ep->dma : NULL; | |
759 | ||
760 | DBG(4, "<== %s, rxcsr %04x%s %p\n", musb_ep->end_point.name, | |
761 | csr, dma ? " (dma)" : "", request); | |
762 | ||
763 | if (csr & MUSB_RXCSR_P_SENTSTALL) { | |
764 | if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { | |
765 | dma->status = MUSB_DMA_STATUS_CORE_ABORT; | |
766 | (void) musb->dma_controller->channel_abort(dma); | |
767 | request->actual += musb_ep->dma->actual_len; | |
768 | } | |
769 | ||
770 | csr |= MUSB_RXCSR_P_WZC_BITS; | |
771 | csr &= ~MUSB_RXCSR_P_SENTSTALL; | |
772 | musb_writew(epio, MUSB_RXCSR, csr); | |
773 | ||
774 | if (request) | |
775 | musb_g_giveback(musb_ep, request, -EPIPE); | |
776 | goto done; | |
777 | } | |
778 | ||
779 | if (csr & MUSB_RXCSR_P_OVERRUN) { | |
780 | /* csr |= MUSB_RXCSR_P_WZC_BITS; */ | |
781 | csr &= ~MUSB_RXCSR_P_OVERRUN; | |
782 | musb_writew(epio, MUSB_RXCSR, csr); | |
783 | ||
784 | DBG(3, "%s iso overrun on %p\n", musb_ep->name, request); | |
785 | if (request && request->status == -EINPROGRESS) | |
786 | request->status = -EOVERFLOW; | |
787 | } | |
788 | if (csr & MUSB_RXCSR_INCOMPRX) { | |
789 | /* REVISIT not necessarily an error */ | |
790 | DBG(4, "%s, incomprx\n", musb_ep->end_point.name); | |
791 | } | |
792 | ||
793 | if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { | |
794 | /* "should not happen"; likely RXPKTRDY pending for DMA */ | |
795 | DBG((csr & MUSB_RXCSR_DMAENAB) ? 4 : 1, | |
796 | "%s busy, csr %04x\n", | |
797 | musb_ep->end_point.name, csr); | |
798 | goto done; | |
799 | } | |
800 | ||
801 | if (dma && (csr & MUSB_RXCSR_DMAENAB)) { | |
802 | csr &= ~(MUSB_RXCSR_AUTOCLEAR | |
803 | | MUSB_RXCSR_DMAENAB | |
804 | | MUSB_RXCSR_DMAMODE); | |
805 | musb_writew(epio, MUSB_RXCSR, | |
806 | MUSB_RXCSR_P_WZC_BITS | csr); | |
807 | ||
808 | request->actual += musb_ep->dma->actual_len; | |
809 | ||
810 | DBG(4, "RXCSR%d %04x, dma off, %04x, len %zu, req %p\n", | |
811 | epnum, csr, | |
812 | musb_readw(epio, MUSB_RXCSR), | |
813 | musb_ep->dma->actual_len, request); | |
814 | ||
815 | #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) | |
816 | /* Autoclear doesn't clear RxPktRdy for short packets */ | |
817 | if ((dma->desired_mode == 0) | |
818 | || (dma->actual_len | |
819 | & (musb_ep->packet_sz - 1))) { | |
820 | /* ack the read! */ | |
821 | csr &= ~MUSB_RXCSR_RXPKTRDY; | |
822 | musb_writew(epio, MUSB_RXCSR, csr); | |
823 | } | |
824 | ||
825 | /* incomplete, and not short? wait for next IN packet */ | |
826 | if ((request->actual < request->length) | |
827 | && (musb_ep->dma->actual_len | |
828 | == musb_ep->packet_sz)) | |
829 | goto done; | |
830 | #endif | |
831 | musb_g_giveback(musb_ep, request, 0); | |
832 | ||
833 | request = next_request(musb_ep); | |
834 | if (!request) | |
835 | goto done; | |
836 | ||
837 | /* don't start more i/o till the stall clears */ | |
838 | musb_ep_select(mbase, epnum); | |
839 | csr = musb_readw(epio, MUSB_RXCSR); | |
840 | if (csr & MUSB_RXCSR_P_SENDSTALL) | |
841 | goto done; | |
842 | } | |
843 | ||
844 | ||
845 | /* analyze request if the ep is hot */ | |
846 | if (request) | |
847 | rxstate(musb, to_musb_request(request)); | |
848 | else | |
849 | DBG(3, "packet waiting for %s%s request\n", | |
850 | musb_ep->desc ? "" : "inactive ", | |
851 | musb_ep->end_point.name); | |
852 | ||
853 | done: | |
854 | return; | |
855 | } | |
856 | ||
857 | /* ------------------------------------------------------------ */ | |
858 | ||
859 | static int musb_gadget_enable(struct usb_ep *ep, | |
860 | const struct usb_endpoint_descriptor *desc) | |
861 | { | |
862 | unsigned long flags; | |
863 | struct musb_ep *musb_ep; | |
864 | struct musb_hw_ep *hw_ep; | |
865 | void __iomem *regs; | |
866 | struct musb *musb; | |
867 | void __iomem *mbase; | |
868 | u8 epnum; | |
869 | u16 csr; | |
870 | unsigned tmp; | |
871 | int status = -EINVAL; | |
872 | ||
873 | if (!ep || !desc) | |
874 | return -EINVAL; | |
875 | ||
876 | musb_ep = to_musb_ep(ep); | |
877 | hw_ep = musb_ep->hw_ep; | |
878 | regs = hw_ep->regs; | |
879 | musb = musb_ep->musb; | |
880 | mbase = musb->mregs; | |
881 | epnum = musb_ep->current_epnum; | |
882 | ||
883 | spin_lock_irqsave(&musb->lock, flags); | |
884 | ||
885 | if (musb_ep->desc) { | |
886 | status = -EBUSY; | |
887 | goto fail; | |
888 | } | |
889 | musb_ep->type = usb_endpoint_type(desc); | |
890 | ||
891 | /* check direction and (later) maxpacket size against endpoint */ | |
892 | if (usb_endpoint_num(desc) != epnum) | |
893 | goto fail; | |
894 | ||
895 | /* REVISIT this rules out high bandwidth periodic transfers */ | |
896 | tmp = le16_to_cpu(desc->wMaxPacketSize); | |
897 | if (tmp & ~0x07ff) | |
898 | goto fail; | |
899 | musb_ep->packet_sz = tmp; | |
900 | ||
901 | /* enable the interrupts for the endpoint, set the endpoint | |
902 | * packet size (or fail), set the mode, clear the fifo | |
903 | */ | |
904 | musb_ep_select(mbase, epnum); | |
905 | if (usb_endpoint_dir_in(desc)) { | |
906 | u16 int_txe = musb_readw(mbase, MUSB_INTRTXE); | |
907 | ||
908 | if (hw_ep->is_shared_fifo) | |
909 | musb_ep->is_in = 1; | |
910 | if (!musb_ep->is_in) | |
911 | goto fail; | |
912 | if (tmp > hw_ep->max_packet_sz_tx) | |
913 | goto fail; | |
914 | ||
915 | int_txe |= (1 << epnum); | |
916 | musb_writew(mbase, MUSB_INTRTXE, int_txe); | |
917 | ||
918 | /* REVISIT if can_bulk_split(), use by updating "tmp"; | |
919 | * likewise high bandwidth periodic tx | |
920 | */ | |
921 | musb_writew(regs, MUSB_TXMAXP, tmp); | |
922 | ||
923 | csr = MUSB_TXCSR_MODE | MUSB_TXCSR_CLRDATATOG; | |
924 | if (musb_readw(regs, MUSB_TXCSR) | |
925 | & MUSB_TXCSR_FIFONOTEMPTY) | |
926 | csr |= MUSB_TXCSR_FLUSHFIFO; | |
927 | if (musb_ep->type == USB_ENDPOINT_XFER_ISOC) | |
928 | csr |= MUSB_TXCSR_P_ISO; | |
929 | ||
930 | /* set twice in case of double buffering */ | |
931 | musb_writew(regs, MUSB_TXCSR, csr); | |
932 | /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */ | |
933 | musb_writew(regs, MUSB_TXCSR, csr); | |
934 | ||
935 | } else { | |
936 | u16 int_rxe = musb_readw(mbase, MUSB_INTRRXE); | |
937 | ||
938 | if (hw_ep->is_shared_fifo) | |
939 | musb_ep->is_in = 0; | |
940 | if (musb_ep->is_in) | |
941 | goto fail; | |
942 | if (tmp > hw_ep->max_packet_sz_rx) | |
943 | goto fail; | |
944 | ||
945 | int_rxe |= (1 << epnum); | |
946 | musb_writew(mbase, MUSB_INTRRXE, int_rxe); | |
947 | ||
948 | /* REVISIT if can_bulk_combine() use by updating "tmp" | |
949 | * likewise high bandwidth periodic rx | |
950 | */ | |
951 | musb_writew(regs, MUSB_RXMAXP, tmp); | |
952 | ||
953 | /* force shared fifo to OUT-only mode */ | |
954 | if (hw_ep->is_shared_fifo) { | |
955 | csr = musb_readw(regs, MUSB_TXCSR); | |
956 | csr &= ~(MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY); | |
957 | musb_writew(regs, MUSB_TXCSR, csr); | |
958 | } | |
959 | ||
960 | csr = MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_CLRDATATOG; | |
961 | if (musb_ep->type == USB_ENDPOINT_XFER_ISOC) | |
962 | csr |= MUSB_RXCSR_P_ISO; | |
963 | else if (musb_ep->type == USB_ENDPOINT_XFER_INT) | |
964 | csr |= MUSB_RXCSR_DISNYET; | |
965 | ||
966 | /* set twice in case of double buffering */ | |
967 | musb_writew(regs, MUSB_RXCSR, csr); | |
968 | musb_writew(regs, MUSB_RXCSR, csr); | |
969 | } | |
970 | ||
971 | /* NOTE: all the I/O code _should_ work fine without DMA, in case | |
972 | * for some reason you run out of channels here. | |
973 | */ | |
974 | if (is_dma_capable() && musb->dma_controller) { | |
975 | struct dma_controller *c = musb->dma_controller; | |
976 | ||
977 | musb_ep->dma = c->channel_alloc(c, hw_ep, | |
978 | (desc->bEndpointAddress & USB_DIR_IN)); | |
979 | } else | |
980 | musb_ep->dma = NULL; | |
981 | ||
982 | musb_ep->desc = desc; | |
983 | musb_ep->busy = 0; | |
984 | status = 0; | |
985 | ||
986 | pr_debug("%s periph: enabled %s for %s %s, %smaxpacket %d\n", | |
987 | musb_driver_name, musb_ep->end_point.name, | |
988 | ({ char *s; switch (musb_ep->type) { | |
989 | case USB_ENDPOINT_XFER_BULK: s = "bulk"; break; | |
990 | case USB_ENDPOINT_XFER_INT: s = "int"; break; | |
991 | default: s = "iso"; break; | |
992 | }; s; }), | |
993 | musb_ep->is_in ? "IN" : "OUT", | |
994 | musb_ep->dma ? "dma, " : "", | |
995 | musb_ep->packet_sz); | |
996 | ||
997 | schedule_work(&musb->irq_work); | |
998 | ||
999 | fail: | |
1000 | spin_unlock_irqrestore(&musb->lock, flags); | |
1001 | return status; | |
1002 | } | |
1003 | ||
1004 | /* | |
1005 | * Disable an endpoint flushing all requests queued. | |
1006 | */ | |
1007 | static int musb_gadget_disable(struct usb_ep *ep) | |
1008 | { | |
1009 | unsigned long flags; | |
1010 | struct musb *musb; | |
1011 | u8 epnum; | |
1012 | struct musb_ep *musb_ep; | |
1013 | void __iomem *epio; | |
1014 | int status = 0; | |
1015 | ||
1016 | musb_ep = to_musb_ep(ep); | |
1017 | musb = musb_ep->musb; | |
1018 | epnum = musb_ep->current_epnum; | |
1019 | epio = musb->endpoints[epnum].regs; | |
1020 | ||
1021 | spin_lock_irqsave(&musb->lock, flags); | |
1022 | musb_ep_select(musb->mregs, epnum); | |
1023 | ||
1024 | /* zero the endpoint sizes */ | |
1025 | if (musb_ep->is_in) { | |
1026 | u16 int_txe = musb_readw(musb->mregs, MUSB_INTRTXE); | |
1027 | int_txe &= ~(1 << epnum); | |
1028 | musb_writew(musb->mregs, MUSB_INTRTXE, int_txe); | |
1029 | musb_writew(epio, MUSB_TXMAXP, 0); | |
1030 | } else { | |
1031 | u16 int_rxe = musb_readw(musb->mregs, MUSB_INTRRXE); | |
1032 | int_rxe &= ~(1 << epnum); | |
1033 | musb_writew(musb->mregs, MUSB_INTRRXE, int_rxe); | |
1034 | musb_writew(epio, MUSB_RXMAXP, 0); | |
1035 | } | |
1036 | ||
1037 | musb_ep->desc = NULL; | |
1038 | ||
1039 | /* abort all pending DMA and requests */ | |
1040 | nuke(musb_ep, -ESHUTDOWN); | |
1041 | ||
1042 | schedule_work(&musb->irq_work); | |
1043 | ||
1044 | spin_unlock_irqrestore(&(musb->lock), flags); | |
1045 | ||
1046 | DBG(2, "%s\n", musb_ep->end_point.name); | |
1047 | ||
1048 | return status; | |
1049 | } | |
1050 | ||
1051 | /* | |
1052 | * Allocate a request for an endpoint. | |
1053 | * Reused by ep0 code. | |
1054 | */ | |
1055 | struct usb_request *musb_alloc_request(struct usb_ep *ep, gfp_t gfp_flags) | |
1056 | { | |
1057 | struct musb_ep *musb_ep = to_musb_ep(ep); | |
1058 | struct musb_request *request = NULL; | |
1059 | ||
1060 | request = kzalloc(sizeof *request, gfp_flags); | |
1061 | if (request) { | |
1062 | INIT_LIST_HEAD(&request->request.list); | |
1063 | request->request.dma = DMA_ADDR_INVALID; | |
1064 | request->epnum = musb_ep->current_epnum; | |
1065 | request->ep = musb_ep; | |
1066 | } | |
1067 | ||
1068 | return &request->request; | |
1069 | } | |
1070 | ||
1071 | /* | |
1072 | * Free a request | |
1073 | * Reused by ep0 code. | |
1074 | */ | |
1075 | void musb_free_request(struct usb_ep *ep, struct usb_request *req) | |
1076 | { | |
1077 | kfree(to_musb_request(req)); | |
1078 | } | |
1079 | ||
1080 | static LIST_HEAD(buffers); | |
1081 | ||
1082 | struct free_record { | |
1083 | struct list_head list; | |
1084 | struct device *dev; | |
1085 | unsigned bytes; | |
1086 | dma_addr_t dma; | |
1087 | }; | |
1088 | ||
1089 | /* | |
1090 | * Context: controller locked, IRQs blocked. | |
1091 | */ | |
1092 | static void musb_ep_restart(struct musb *musb, struct musb_request *req) | |
1093 | { | |
1094 | DBG(3, "<== %s request %p len %u on hw_ep%d\n", | |
1095 | req->tx ? "TX/IN" : "RX/OUT", | |
1096 | &req->request, req->request.length, req->epnum); | |
1097 | ||
1098 | musb_ep_select(musb->mregs, req->epnum); | |
1099 | if (req->tx) | |
1100 | txstate(musb, req); | |
1101 | else | |
1102 | rxstate(musb, req); | |
1103 | } | |
1104 | ||
1105 | static int musb_gadget_queue(struct usb_ep *ep, struct usb_request *req, | |
1106 | gfp_t gfp_flags) | |
1107 | { | |
1108 | struct musb_ep *musb_ep; | |
1109 | struct musb_request *request; | |
1110 | struct musb *musb; | |
1111 | int status = 0; | |
1112 | unsigned long lockflags; | |
1113 | ||
1114 | if (!ep || !req) | |
1115 | return -EINVAL; | |
1116 | if (!req->buf) | |
1117 | return -ENODATA; | |
1118 | ||
1119 | musb_ep = to_musb_ep(ep); | |
1120 | musb = musb_ep->musb; | |
1121 | ||
1122 | request = to_musb_request(req); | |
1123 | request->musb = musb; | |
1124 | ||
1125 | if (request->ep != musb_ep) | |
1126 | return -EINVAL; | |
1127 | ||
1128 | DBG(4, "<== to %s request=%p\n", ep->name, req); | |
1129 | ||
1130 | /* request is mine now... */ | |
1131 | request->request.actual = 0; | |
1132 | request->request.status = -EINPROGRESS; | |
1133 | request->epnum = musb_ep->current_epnum; | |
1134 | request->tx = musb_ep->is_in; | |
1135 | ||
1136 | if (is_dma_capable() && musb_ep->dma) { | |
1137 | if (request->request.dma == DMA_ADDR_INVALID) { | |
1138 | request->request.dma = dma_map_single( | |
1139 | musb->controller, | |
1140 | request->request.buf, | |
1141 | request->request.length, | |
1142 | request->tx | |
1143 | ? DMA_TO_DEVICE | |
1144 | : DMA_FROM_DEVICE); | |
1145 | request->mapped = 1; | |
1146 | } else { | |
1147 | dma_sync_single_for_device(musb->controller, | |
1148 | request->request.dma, | |
1149 | request->request.length, | |
1150 | request->tx | |
1151 | ? DMA_TO_DEVICE | |
1152 | : DMA_FROM_DEVICE); | |
1153 | request->mapped = 0; | |
1154 | } | |
1155 | } else if (!req->buf) { | |
1156 | return -ENODATA; | |
1157 | } else | |
1158 | request->mapped = 0; | |
1159 | ||
1160 | spin_lock_irqsave(&musb->lock, lockflags); | |
1161 | ||
1162 | /* don't queue if the ep is down */ | |
1163 | if (!musb_ep->desc) { | |
1164 | DBG(4, "req %p queued to %s while ep %s\n", | |
1165 | req, ep->name, "disabled"); | |
1166 | status = -ESHUTDOWN; | |
1167 | goto cleanup; | |
1168 | } | |
1169 | ||
1170 | /* add request to the list */ | |
1171 | list_add_tail(&(request->request.list), &(musb_ep->req_list)); | |
1172 | ||
1173 | /* it this is the head of the queue, start i/o ... */ | |
1174 | if (!musb_ep->busy && &request->request.list == musb_ep->req_list.next) | |
1175 | musb_ep_restart(musb, request); | |
1176 | ||
1177 | cleanup: | |
1178 | spin_unlock_irqrestore(&musb->lock, lockflags); | |
1179 | return status; | |
1180 | } | |
1181 | ||
1182 | static int musb_gadget_dequeue(struct usb_ep *ep, struct usb_request *request) | |
1183 | { | |
1184 | struct musb_ep *musb_ep = to_musb_ep(ep); | |
1185 | struct usb_request *r; | |
1186 | unsigned long flags; | |
1187 | int status = 0; | |
1188 | struct musb *musb = musb_ep->musb; | |
1189 | ||
1190 | if (!ep || !request || to_musb_request(request)->ep != musb_ep) | |
1191 | return -EINVAL; | |
1192 | ||
1193 | spin_lock_irqsave(&musb->lock, flags); | |
1194 | ||
1195 | list_for_each_entry(r, &musb_ep->req_list, list) { | |
1196 | if (r == request) | |
1197 | break; | |
1198 | } | |
1199 | if (r != request) { | |
1200 | DBG(3, "request %p not queued to %s\n", request, ep->name); | |
1201 | status = -EINVAL; | |
1202 | goto done; | |
1203 | } | |
1204 | ||
1205 | /* if the hardware doesn't have the request, easy ... */ | |
1206 | if (musb_ep->req_list.next != &request->list || musb_ep->busy) | |
1207 | musb_g_giveback(musb_ep, request, -ECONNRESET); | |
1208 | ||
1209 | /* ... else abort the dma transfer ... */ | |
1210 | else if (is_dma_capable() && musb_ep->dma) { | |
1211 | struct dma_controller *c = musb->dma_controller; | |
1212 | ||
1213 | musb_ep_select(musb->mregs, musb_ep->current_epnum); | |
1214 | if (c->channel_abort) | |
1215 | status = c->channel_abort(musb_ep->dma); | |
1216 | else | |
1217 | status = -EBUSY; | |
1218 | if (status == 0) | |
1219 | musb_g_giveback(musb_ep, request, -ECONNRESET); | |
1220 | } else { | |
1221 | /* NOTE: by sticking to easily tested hardware/driver states, | |
1222 | * we leave counting of in-flight packets imprecise. | |
1223 | */ | |
1224 | musb_g_giveback(musb_ep, request, -ECONNRESET); | |
1225 | } | |
1226 | ||
1227 | done: | |
1228 | spin_unlock_irqrestore(&musb->lock, flags); | |
1229 | return status; | |
1230 | } | |
1231 | ||
1232 | /* | |
1233 | * Set or clear the halt bit of an endpoint. A halted enpoint won't tx/rx any | |
1234 | * data but will queue requests. | |
1235 | * | |
1236 | * exported to ep0 code | |
1237 | */ | |
1238 | int musb_gadget_set_halt(struct usb_ep *ep, int value) | |
1239 | { | |
1240 | struct musb_ep *musb_ep = to_musb_ep(ep); | |
1241 | u8 epnum = musb_ep->current_epnum; | |
1242 | struct musb *musb = musb_ep->musb; | |
1243 | void __iomem *epio = musb->endpoints[epnum].regs; | |
1244 | void __iomem *mbase; | |
1245 | unsigned long flags; | |
1246 | u16 csr; | |
1247 | struct musb_request *request = NULL; | |
1248 | int status = 0; | |
1249 | ||
1250 | if (!ep) | |
1251 | return -EINVAL; | |
1252 | mbase = musb->mregs; | |
1253 | ||
1254 | spin_lock_irqsave(&musb->lock, flags); | |
1255 | ||
1256 | if ((USB_ENDPOINT_XFER_ISOC == musb_ep->type)) { | |
1257 | status = -EINVAL; | |
1258 | goto done; | |
1259 | } | |
1260 | ||
1261 | musb_ep_select(mbase, epnum); | |
1262 | ||
1263 | /* cannot portably stall with non-empty FIFO */ | |
1264 | request = to_musb_request(next_request(musb_ep)); | |
1265 | if (value && musb_ep->is_in) { | |
1266 | csr = musb_readw(epio, MUSB_TXCSR); | |
1267 | if (csr & MUSB_TXCSR_FIFONOTEMPTY) { | |
1268 | DBG(3, "%s fifo busy, cannot halt\n", ep->name); | |
1269 | spin_unlock_irqrestore(&musb->lock, flags); | |
1270 | return -EAGAIN; | |
1271 | } | |
1272 | ||
1273 | } | |
1274 | ||
1275 | /* set/clear the stall and toggle bits */ | |
1276 | DBG(2, "%s: %s stall\n", ep->name, value ? "set" : "clear"); | |
1277 | if (musb_ep->is_in) { | |
1278 | csr = musb_readw(epio, MUSB_TXCSR); | |
1279 | if (csr & MUSB_TXCSR_FIFONOTEMPTY) | |
1280 | csr |= MUSB_TXCSR_FLUSHFIFO; | |
1281 | csr |= MUSB_TXCSR_P_WZC_BITS | |
1282 | | MUSB_TXCSR_CLRDATATOG; | |
1283 | if (value) | |
1284 | csr |= MUSB_TXCSR_P_SENDSTALL; | |
1285 | else | |
1286 | csr &= ~(MUSB_TXCSR_P_SENDSTALL | |
1287 | | MUSB_TXCSR_P_SENTSTALL); | |
1288 | csr &= ~MUSB_TXCSR_TXPKTRDY; | |
1289 | musb_writew(epio, MUSB_TXCSR, csr); | |
1290 | } else { | |
1291 | csr = musb_readw(epio, MUSB_RXCSR); | |
1292 | csr |= MUSB_RXCSR_P_WZC_BITS | |
1293 | | MUSB_RXCSR_FLUSHFIFO | |
1294 | | MUSB_RXCSR_CLRDATATOG; | |
1295 | if (value) | |
1296 | csr |= MUSB_RXCSR_P_SENDSTALL; | |
1297 | else | |
1298 | csr &= ~(MUSB_RXCSR_P_SENDSTALL | |
1299 | | MUSB_RXCSR_P_SENTSTALL); | |
1300 | musb_writew(epio, MUSB_RXCSR, csr); | |
1301 | } | |
1302 | ||
1303 | done: | |
1304 | ||
1305 | /* maybe start the first request in the queue */ | |
1306 | if (!musb_ep->busy && !value && request) { | |
1307 | DBG(3, "restarting the request\n"); | |
1308 | musb_ep_restart(musb, request); | |
1309 | } | |
1310 | ||
1311 | spin_unlock_irqrestore(&musb->lock, flags); | |
1312 | return status; | |
1313 | } | |
1314 | ||
1315 | static int musb_gadget_fifo_status(struct usb_ep *ep) | |
1316 | { | |
1317 | struct musb_ep *musb_ep = to_musb_ep(ep); | |
1318 | void __iomem *epio = musb_ep->hw_ep->regs; | |
1319 | int retval = -EINVAL; | |
1320 | ||
1321 | if (musb_ep->desc && !musb_ep->is_in) { | |
1322 | struct musb *musb = musb_ep->musb; | |
1323 | int epnum = musb_ep->current_epnum; | |
1324 | void __iomem *mbase = musb->mregs; | |
1325 | unsigned long flags; | |
1326 | ||
1327 | spin_lock_irqsave(&musb->lock, flags); | |
1328 | ||
1329 | musb_ep_select(mbase, epnum); | |
1330 | /* FIXME return zero unless RXPKTRDY is set */ | |
1331 | retval = musb_readw(epio, MUSB_RXCOUNT); | |
1332 | ||
1333 | spin_unlock_irqrestore(&musb->lock, flags); | |
1334 | } | |
1335 | return retval; | |
1336 | } | |
1337 | ||
1338 | static void musb_gadget_fifo_flush(struct usb_ep *ep) | |
1339 | { | |
1340 | struct musb_ep *musb_ep = to_musb_ep(ep); | |
1341 | struct musb *musb = musb_ep->musb; | |
1342 | u8 epnum = musb_ep->current_epnum; | |
1343 | void __iomem *epio = musb->endpoints[epnum].regs; | |
1344 | void __iomem *mbase; | |
1345 | unsigned long flags; | |
1346 | u16 csr, int_txe; | |
1347 | ||
1348 | mbase = musb->mregs; | |
1349 | ||
1350 | spin_lock_irqsave(&musb->lock, flags); | |
1351 | musb_ep_select(mbase, (u8) epnum); | |
1352 | ||
1353 | /* disable interrupts */ | |
1354 | int_txe = musb_readw(mbase, MUSB_INTRTXE); | |
1355 | musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum)); | |
1356 | ||
1357 | if (musb_ep->is_in) { | |
1358 | csr = musb_readw(epio, MUSB_TXCSR); | |
1359 | if (csr & MUSB_TXCSR_FIFONOTEMPTY) { | |
1360 | csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_P_WZC_BITS; | |
1361 | musb_writew(epio, MUSB_TXCSR, csr); | |
1362 | /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */ | |
1363 | musb_writew(epio, MUSB_TXCSR, csr); | |
1364 | } | |
1365 | } else { | |
1366 | csr = musb_readw(epio, MUSB_RXCSR); | |
1367 | csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_P_WZC_BITS; | |
1368 | musb_writew(epio, MUSB_RXCSR, csr); | |
1369 | musb_writew(epio, MUSB_RXCSR, csr); | |
1370 | } | |
1371 | ||
1372 | /* re-enable interrupt */ | |
1373 | musb_writew(mbase, MUSB_INTRTXE, int_txe); | |
1374 | spin_unlock_irqrestore(&musb->lock, flags); | |
1375 | } | |
1376 | ||
1377 | static const struct usb_ep_ops musb_ep_ops = { | |
1378 | .enable = musb_gadget_enable, | |
1379 | .disable = musb_gadget_disable, | |
1380 | .alloc_request = musb_alloc_request, | |
1381 | .free_request = musb_free_request, | |
1382 | .queue = musb_gadget_queue, | |
1383 | .dequeue = musb_gadget_dequeue, | |
1384 | .set_halt = musb_gadget_set_halt, | |
1385 | .fifo_status = musb_gadget_fifo_status, | |
1386 | .fifo_flush = musb_gadget_fifo_flush | |
1387 | }; | |
1388 | ||
1389 | /* ----------------------------------------------------------------------- */ | |
1390 | ||
1391 | static int musb_gadget_get_frame(struct usb_gadget *gadget) | |
1392 | { | |
1393 | struct musb *musb = gadget_to_musb(gadget); | |
1394 | ||
1395 | return (int)musb_readw(musb->mregs, MUSB_FRAME); | |
1396 | } | |
1397 | ||
1398 | static int musb_gadget_wakeup(struct usb_gadget *gadget) | |
1399 | { | |
1400 | struct musb *musb = gadget_to_musb(gadget); | |
1401 | void __iomem *mregs = musb->mregs; | |
1402 | unsigned long flags; | |
1403 | int status = -EINVAL; | |
1404 | u8 power, devctl; | |
1405 | int retries; | |
1406 | ||
1407 | spin_lock_irqsave(&musb->lock, flags); | |
1408 | ||
1409 | switch (musb->xceiv->state) { | |
1410 | case OTG_STATE_B_PERIPHERAL: | |
1411 | /* NOTE: OTG state machine doesn't include B_SUSPENDED; | |
1412 | * that's part of the standard usb 1.1 state machine, and | |
1413 | * doesn't affect OTG transitions. | |
1414 | */ | |
1415 | if (musb->may_wakeup && musb->is_suspended) | |
1416 | break; | |
1417 | goto done; | |
1418 | case OTG_STATE_B_IDLE: | |
1419 | /* Start SRP ... OTG not required. */ | |
1420 | devctl = musb_readb(mregs, MUSB_DEVCTL); | |
1421 | DBG(2, "Sending SRP: devctl: %02x\n", devctl); | |
1422 | devctl |= MUSB_DEVCTL_SESSION; | |
1423 | musb_writeb(mregs, MUSB_DEVCTL, devctl); | |
1424 | devctl = musb_readb(mregs, MUSB_DEVCTL); | |
1425 | retries = 100; | |
1426 | while (!(devctl & MUSB_DEVCTL_SESSION)) { | |
1427 | devctl = musb_readb(mregs, MUSB_DEVCTL); | |
1428 | if (retries-- < 1) | |
1429 | break; | |
1430 | } | |
1431 | retries = 10000; | |
1432 | while (devctl & MUSB_DEVCTL_SESSION) { | |
1433 | devctl = musb_readb(mregs, MUSB_DEVCTL); | |
1434 | if (retries-- < 1) | |
1435 | break; | |
1436 | } | |
1437 | ||
1438 | /* Block idling for at least 1s */ | |
1439 | musb_platform_try_idle(musb, | |
1440 | jiffies + msecs_to_jiffies(1 * HZ)); | |
1441 | ||
1442 | status = 0; | |
1443 | goto done; | |
1444 | default: | |
1445 | DBG(2, "Unhandled wake: %s\n", otg_state_string(musb)); | |
1446 | goto done; | |
1447 | } | |
1448 | ||
1449 | status = 0; | |
1450 | ||
1451 | power = musb_readb(mregs, MUSB_POWER); | |
1452 | power |= MUSB_POWER_RESUME; | |
1453 | musb_writeb(mregs, MUSB_POWER, power); | |
1454 | DBG(2, "issue wakeup\n"); | |
1455 | ||
1456 | /* FIXME do this next chunk in a timer callback, no udelay */ | |
1457 | mdelay(2); | |
1458 | ||
1459 | power = musb_readb(mregs, MUSB_POWER); | |
1460 | power &= ~MUSB_POWER_RESUME; | |
1461 | musb_writeb(mregs, MUSB_POWER, power); | |
1462 | done: | |
1463 | spin_unlock_irqrestore(&musb->lock, flags); | |
1464 | return status; | |
1465 | } | |
1466 | ||
1467 | static int | |
1468 | musb_gadget_set_self_powered(struct usb_gadget *gadget, int is_selfpowered) | |
1469 | { | |
1470 | struct musb *musb = gadget_to_musb(gadget); | |
1471 | ||
1472 | musb->is_self_powered = !!is_selfpowered; | |
1473 | return 0; | |
1474 | } | |
1475 | ||
1476 | static void musb_pullup(struct musb *musb, int is_on) | |
1477 | { | |
1478 | u8 power; | |
1479 | ||
1480 | power = musb_readb(musb->mregs, MUSB_POWER); | |
1481 | if (is_on) | |
1482 | power |= MUSB_POWER_SOFTCONN; | |
1483 | else | |
1484 | power &= ~MUSB_POWER_SOFTCONN; | |
1485 | ||
1486 | /* FIXME if on, HdrcStart; if off, HdrcStop */ | |
1487 | ||
1488 | DBG(3, "gadget %s D+ pullup %s\n", | |
1489 | musb->gadget_driver->function, is_on ? "on" : "off"); | |
1490 | musb_writeb(musb->mregs, MUSB_POWER, power); | |
1491 | } | |
1492 | ||
1493 | #if 0 | |
1494 | static int musb_gadget_vbus_session(struct usb_gadget *gadget, int is_active) | |
1495 | { | |
1496 | DBG(2, "<= %s =>\n", __func__); | |
1497 | ||
1498 | /* | |
1499 | * FIXME iff driver's softconnect flag is set (as it is during probe, | |
1500 | * though that can clear it), just musb_pullup(). | |
1501 | */ | |
1502 | ||
1503 | return -EINVAL; | |
1504 | } | |
1505 | #endif | |
1506 | ||
1507 | static int musb_gadget_vbus_draw(struct usb_gadget *gadget, unsigned mA) | |
1508 | { | |
1509 | struct musb *musb = gadget_to_musb(gadget); | |
1510 | ||
1511 | if (!musb->xceiv->set_power) | |
1512 | return -EOPNOTSUPP; | |
1513 | return otg_set_power(musb->xceiv, mA); | |
1514 | } | |
1515 | ||
1516 | static int musb_gadget_pullup(struct usb_gadget *gadget, int is_on) | |
1517 | { | |
1518 | struct musb *musb = gadget_to_musb(gadget); | |
1519 | unsigned long flags; | |
1520 | ||
1521 | is_on = !!is_on; | |
1522 | ||
1523 | /* NOTE: this assumes we are sensing vbus; we'd rather | |
1524 | * not pullup unless the B-session is active. | |
1525 | */ | |
1526 | spin_lock_irqsave(&musb->lock, flags); | |
1527 | if (is_on != musb->softconnect) { | |
1528 | musb->softconnect = is_on; | |
1529 | musb_pullup(musb, is_on); | |
1530 | } | |
1531 | spin_unlock_irqrestore(&musb->lock, flags); | |
1532 | return 0; | |
1533 | } | |
1534 | ||
1535 | static const struct usb_gadget_ops musb_gadget_operations = { | |
1536 | .get_frame = musb_gadget_get_frame, | |
1537 | .wakeup = musb_gadget_wakeup, | |
1538 | .set_selfpowered = musb_gadget_set_self_powered, | |
1539 | /* .vbus_session = musb_gadget_vbus_session, */ | |
1540 | .vbus_draw = musb_gadget_vbus_draw, | |
1541 | .pullup = musb_gadget_pullup, | |
1542 | }; | |
1543 | ||
1544 | /* ----------------------------------------------------------------------- */ | |
1545 | ||
1546 | /* Registration */ | |
1547 | ||
1548 | /* Only this registration code "knows" the rule (from USB standards) | |
1549 | * about there being only one external upstream port. It assumes | |
1550 | * all peripheral ports are external... | |
1551 | */ | |
1552 | static struct musb *the_gadget; | |
1553 | ||
1554 | static void musb_gadget_release(struct device *dev) | |
1555 | { | |
1556 | /* kref_put(WHAT) */ | |
1557 | dev_dbg(dev, "%s\n", __func__); | |
1558 | } | |
1559 | ||
1560 | ||
1561 | static void __init | |
1562 | init_peripheral_ep(struct musb *musb, struct musb_ep *ep, u8 epnum, int is_in) | |
1563 | { | |
1564 | struct musb_hw_ep *hw_ep = musb->endpoints + epnum; | |
1565 | ||
1566 | memset(ep, 0, sizeof *ep); | |
1567 | ||
1568 | ep->current_epnum = epnum; | |
1569 | ep->musb = musb; | |
1570 | ep->hw_ep = hw_ep; | |
1571 | ep->is_in = is_in; | |
1572 | ||
1573 | INIT_LIST_HEAD(&ep->req_list); | |
1574 | ||
1575 | sprintf(ep->name, "ep%d%s", epnum, | |
1576 | (!epnum || hw_ep->is_shared_fifo) ? "" : ( | |
1577 | is_in ? "in" : "out")); | |
1578 | ep->end_point.name = ep->name; | |
1579 | INIT_LIST_HEAD(&ep->end_point.ep_list); | |
1580 | if (!epnum) { | |
1581 | ep->end_point.maxpacket = 64; | |
1582 | ep->end_point.ops = &musb_g_ep0_ops; | |
1583 | musb->g.ep0 = &ep->end_point; | |
1584 | } else { | |
1585 | if (is_in) | |
1586 | ep->end_point.maxpacket = hw_ep->max_packet_sz_tx; | |
1587 | else | |
1588 | ep->end_point.maxpacket = hw_ep->max_packet_sz_rx; | |
1589 | ep->end_point.ops = &musb_ep_ops; | |
1590 | list_add_tail(&ep->end_point.ep_list, &musb->g.ep_list); | |
1591 | } | |
1592 | } | |
1593 | ||
1594 | /* | |
1595 | * Initialize the endpoints exposed to peripheral drivers, with backlinks | |
1596 | * to the rest of the driver state. | |
1597 | */ | |
1598 | static inline void __init musb_g_init_endpoints(struct musb *musb) | |
1599 | { | |
1600 | u8 epnum; | |
1601 | struct musb_hw_ep *hw_ep; | |
1602 | unsigned count = 0; | |
1603 | ||
1604 | /* intialize endpoint list just once */ | |
1605 | INIT_LIST_HEAD(&(musb->g.ep_list)); | |
1606 | ||
1607 | for (epnum = 0, hw_ep = musb->endpoints; | |
1608 | epnum < musb->nr_endpoints; | |
1609 | epnum++, hw_ep++) { | |
1610 | if (hw_ep->is_shared_fifo /* || !epnum */) { | |
1611 | init_peripheral_ep(musb, &hw_ep->ep_in, epnum, 0); | |
1612 | count++; | |
1613 | } else { | |
1614 | if (hw_ep->max_packet_sz_tx) { | |
1615 | init_peripheral_ep(musb, &hw_ep->ep_in, | |
1616 | epnum, 1); | |
1617 | count++; | |
1618 | } | |
1619 | if (hw_ep->max_packet_sz_rx) { | |
1620 | init_peripheral_ep(musb, &hw_ep->ep_out, | |
1621 | epnum, 0); | |
1622 | count++; | |
1623 | } | |
1624 | } | |
1625 | } | |
1626 | } | |
1627 | ||
1628 | /* called once during driver setup to initialize and link into | |
1629 | * the driver model; memory is zeroed. | |
1630 | */ | |
1631 | int __init musb_gadget_setup(struct musb *musb) | |
1632 | { | |
1633 | int status; | |
1634 | ||
1635 | /* REVISIT minor race: if (erroneously) setting up two | |
1636 | * musb peripherals at the same time, only the bus lock | |
1637 | * is probably held. | |
1638 | */ | |
1639 | if (the_gadget) | |
1640 | return -EBUSY; | |
1641 | the_gadget = musb; | |
1642 | ||
1643 | musb->g.ops = &musb_gadget_operations; | |
1644 | musb->g.is_dualspeed = 1; | |
1645 | musb->g.speed = USB_SPEED_UNKNOWN; | |
1646 | ||
1647 | /* this "gadget" abstracts/virtualizes the controller */ | |
1648 | dev_set_name(&musb->g.dev, "gadget"); | |
1649 | musb->g.dev.parent = musb->controller; | |
1650 | musb->g.dev.dma_mask = musb->controller->dma_mask; | |
1651 | musb->g.dev.release = musb_gadget_release; | |
1652 | musb->g.name = musb_driver_name; | |
1653 | ||
1654 | if (is_otg_enabled(musb)) | |
1655 | musb->g.is_otg = 1; | |
1656 | ||
1657 | musb_g_init_endpoints(musb); | |
1658 | ||
1659 | musb->is_active = 0; | |
1660 | musb_platform_try_idle(musb, 0); | |
1661 | ||
1662 | status = device_register(&musb->g.dev); | |
1663 | if (status != 0) | |
1664 | the_gadget = NULL; | |
1665 | return status; | |
1666 | } | |
1667 | ||
1668 | void musb_gadget_cleanup(struct musb *musb) | |
1669 | { | |
1670 | if (musb != the_gadget) | |
1671 | return; | |
1672 | ||
1673 | device_unregister(&musb->g.dev); | |
1674 | the_gadget = NULL; | |
1675 | } | |
1676 | ||
1677 | /* | |
1678 | * Register the gadget driver. Used by gadget drivers when | |
1679 | * registering themselves with the controller. | |
1680 | * | |
1681 | * -EINVAL something went wrong (not driver) | |
1682 | * -EBUSY another gadget is already using the controller | |
1683 | * -ENOMEM no memeory to perform the operation | |
1684 | * | |
1685 | * @param driver the gadget driver | |
1686 | * @return <0 if error, 0 if everything is fine | |
1687 | */ | |
1688 | int usb_gadget_register_driver(struct usb_gadget_driver *driver) | |
1689 | { | |
1690 | int retval; | |
1691 | unsigned long flags; | |
1692 | struct musb *musb = the_gadget; | |
1693 | ||
1694 | if (!driver | |
1695 | || driver->speed != USB_SPEED_HIGH | |
1696 | || !driver->bind | |
1697 | || !driver->setup) | |
1698 | return -EINVAL; | |
1699 | ||
1700 | /* driver must be initialized to support peripheral mode */ | |
1701 | if (!musb || !(musb->board_mode == MUSB_OTG | |
1702 | || musb->board_mode != MUSB_OTG)) { | |
1703 | DBG(1, "%s, no dev??\n", __func__); | |
1704 | return -ENODEV; | |
1705 | } | |
1706 | ||
1707 | DBG(3, "registering driver %s\n", driver->function); | |
1708 | spin_lock_irqsave(&musb->lock, flags); | |
1709 | ||
1710 | if (musb->gadget_driver) { | |
1711 | DBG(1, "%s is already bound to %s\n", | |
1712 | musb_driver_name, | |
1713 | musb->gadget_driver->driver.name); | |
1714 | retval = -EBUSY; | |
1715 | } else { | |
1716 | musb->gadget_driver = driver; | |
1717 | musb->g.dev.driver = &driver->driver; | |
1718 | driver->driver.bus = NULL; | |
1719 | musb->softconnect = 1; | |
1720 | retval = 0; | |
1721 | } | |
1722 | ||
1723 | spin_unlock_irqrestore(&musb->lock, flags); | |
1724 | ||
1725 | if (retval == 0) { | |
1726 | retval = driver->bind(&musb->g); | |
1727 | if (retval != 0) { | |
1728 | DBG(3, "bind to driver %s failed --> %d\n", | |
1729 | driver->driver.name, retval); | |
1730 | musb->gadget_driver = NULL; | |
1731 | musb->g.dev.driver = NULL; | |
1732 | } | |
1733 | ||
1734 | spin_lock_irqsave(&musb->lock, flags); | |
1735 | ||
1736 | otg_set_peripheral(musb->xceiv, &musb->g); | |
1737 | musb->is_active = 1; | |
1738 | ||
1739 | /* FIXME this ignores the softconnect flag. Drivers are | |
1740 | * allowed hold the peripheral inactive until for example | |
1741 | * userspace hooks up printer hardware or DSP codecs, so | |
1742 | * hosts only see fully functional devices. | |
1743 | */ | |
1744 | ||
1745 | if (!is_otg_enabled(musb)) | |
1746 | musb_start(musb); | |
1747 | ||
1748 | otg_set_peripheral(musb->xceiv, &musb->g); | |
1749 | ||
1750 | spin_unlock_irqrestore(&musb->lock, flags); | |
1751 | ||
1752 | if (is_otg_enabled(musb)) { | |
1753 | DBG(3, "OTG startup...\n"); | |
1754 | ||
1755 | /* REVISIT: funcall to other code, which also | |
1756 | * handles power budgeting ... this way also | |
1757 | * ensures HdrcStart is indirectly called. | |
1758 | */ | |
1759 | retval = usb_add_hcd(musb_to_hcd(musb), -1, 0); | |
1760 | if (retval < 0) { | |
1761 | DBG(1, "add_hcd failed, %d\n", retval); | |
1762 | spin_lock_irqsave(&musb->lock, flags); | |
1763 | otg_set_peripheral(musb->xceiv, NULL); | |
1764 | musb->gadget_driver = NULL; | |
1765 | musb->g.dev.driver = NULL; | |
1766 | spin_unlock_irqrestore(&musb->lock, flags); | |
1767 | } | |
1768 | } | |
1769 | } | |
1770 | ||
1771 | return retval; | |
1772 | } | |
1773 | EXPORT_SYMBOL(usb_gadget_register_driver); | |
1774 | ||
1775 | static void stop_activity(struct musb *musb, struct usb_gadget_driver *driver) | |
1776 | { | |
1777 | int i; | |
1778 | struct musb_hw_ep *hw_ep; | |
1779 | ||
1780 | /* don't disconnect if it's not connected */ | |
1781 | if (musb->g.speed == USB_SPEED_UNKNOWN) | |
1782 | driver = NULL; | |
1783 | else | |
1784 | musb->g.speed = USB_SPEED_UNKNOWN; | |
1785 | ||
1786 | /* deactivate the hardware */ | |
1787 | if (musb->softconnect) { | |
1788 | musb->softconnect = 0; | |
1789 | musb_pullup(musb, 0); | |
1790 | } | |
1791 | musb_stop(musb); | |
1792 | ||
1793 | /* killing any outstanding requests will quiesce the driver; | |
1794 | * then report disconnect | |
1795 | */ | |
1796 | if (driver) { | |
1797 | for (i = 0, hw_ep = musb->endpoints; | |
1798 | i < musb->nr_endpoints; | |
1799 | i++, hw_ep++) { | |
1800 | musb_ep_select(musb->mregs, i); | |
1801 | if (hw_ep->is_shared_fifo /* || !epnum */) { | |
1802 | nuke(&hw_ep->ep_in, -ESHUTDOWN); | |
1803 | } else { | |
1804 | if (hw_ep->max_packet_sz_tx) | |
1805 | nuke(&hw_ep->ep_in, -ESHUTDOWN); | |
1806 | if (hw_ep->max_packet_sz_rx) | |
1807 | nuke(&hw_ep->ep_out, -ESHUTDOWN); | |
1808 | } | |
1809 | } | |
1810 | ||
1811 | spin_unlock(&musb->lock); | |
1812 | driver->disconnect(&musb->g); | |
1813 | spin_lock(&musb->lock); | |
1814 | } | |
1815 | } | |
1816 | ||
1817 | /* | |
1818 | * Unregister the gadget driver. Used by gadget drivers when | |
1819 | * unregistering themselves from the controller. | |
1820 | * | |
1821 | * @param driver the gadget driver to unregister | |
1822 | */ | |
1823 | int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) | |
1824 | { | |
1825 | unsigned long flags; | |
1826 | int retval = 0; | |
1827 | struct musb *musb = the_gadget; | |
1828 | ||
1829 | if (!driver || !driver->unbind || !musb) | |
1830 | return -EINVAL; | |
1831 | ||
1832 | /* REVISIT always use otg_set_peripheral() here too; | |
1833 | * this needs to shut down the OTG engine. | |
1834 | */ | |
1835 | ||
1836 | spin_lock_irqsave(&musb->lock, flags); | |
1837 | ||
1838 | #ifdef CONFIG_USB_MUSB_OTG | |
1839 | musb_hnp_stop(musb); | |
1840 | #endif | |
1841 | ||
1842 | if (musb->gadget_driver == driver) { | |
1843 | ||
1844 | (void) musb_gadget_vbus_draw(&musb->g, 0); | |
1845 | ||
1846 | musb->xceiv->state = OTG_STATE_UNDEFINED; | |
1847 | stop_activity(musb, driver); | |
1848 | otg_set_peripheral(musb->xceiv, NULL); | |
1849 | ||
1850 | DBG(3, "unregistering driver %s\n", driver->function); | |
1851 | spin_unlock_irqrestore(&musb->lock, flags); | |
1852 | driver->unbind(&musb->g); | |
1853 | spin_lock_irqsave(&musb->lock, flags); | |
1854 | ||
1855 | musb->gadget_driver = NULL; | |
1856 | musb->g.dev.driver = NULL; | |
1857 | ||
1858 | musb->is_active = 0; | |
1859 | musb_platform_try_idle(musb, 0); | |
1860 | } else | |
1861 | retval = -EINVAL; | |
1862 | spin_unlock_irqrestore(&musb->lock, flags); | |
1863 | ||
1864 | if (is_otg_enabled(musb) && retval == 0) { | |
1865 | usb_remove_hcd(musb_to_hcd(musb)); | |
1866 | /* FIXME we need to be able to register another | |
1867 | * gadget driver here and have everything work; | |
1868 | * that currently misbehaves. | |
1869 | */ | |
1870 | } | |
1871 | ||
1872 | return retval; | |
1873 | } | |
1874 | EXPORT_SYMBOL(usb_gadget_unregister_driver); | |
1875 | ||
1876 | ||
1877 | /* ----------------------------------------------------------------------- */ | |
1878 | ||
1879 | /* lifecycle operations called through plat_uds.c */ | |
1880 | ||
1881 | void musb_g_resume(struct musb *musb) | |
1882 | { | |
1883 | musb->is_suspended = 0; | |
1884 | switch (musb->xceiv->state) { | |
1885 | case OTG_STATE_B_IDLE: | |
1886 | break; | |
1887 | case OTG_STATE_B_WAIT_ACON: | |
1888 | case OTG_STATE_B_PERIPHERAL: | |
1889 | musb->is_active = 1; | |
1890 | if (musb->gadget_driver && musb->gadget_driver->resume) { | |
1891 | spin_unlock(&musb->lock); | |
1892 | musb->gadget_driver->resume(&musb->g); | |
1893 | spin_lock(&musb->lock); | |
1894 | } | |
1895 | break; | |
1896 | default: | |
1897 | WARNING("unhandled RESUME transition (%s)\n", | |
1898 | otg_state_string(musb)); | |
1899 | } | |
1900 | } | |
1901 | ||
1902 | /* called when SOF packets stop for 3+ msec */ | |
1903 | void musb_g_suspend(struct musb *musb) | |
1904 | { | |
1905 | u8 devctl; | |
1906 | ||
1907 | devctl = musb_readb(musb->mregs, MUSB_DEVCTL); | |
1908 | DBG(3, "devctl %02x\n", devctl); | |
1909 | ||
1910 | switch (musb->xceiv->state) { | |
1911 | case OTG_STATE_B_IDLE: | |
1912 | if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) | |
1913 | musb->xceiv->state = OTG_STATE_B_PERIPHERAL; | |
1914 | break; | |
1915 | case OTG_STATE_B_PERIPHERAL: | |
1916 | musb->is_suspended = 1; | |
1917 | if (musb->gadget_driver && musb->gadget_driver->suspend) { | |
1918 | spin_unlock(&musb->lock); | |
1919 | musb->gadget_driver->suspend(&musb->g); | |
1920 | spin_lock(&musb->lock); | |
1921 | } | |
1922 | break; | |
1923 | default: | |
1924 | /* REVISIT if B_HOST, clear DEVCTL.HOSTREQ; | |
1925 | * A_PERIPHERAL may need care too | |
1926 | */ | |
1927 | WARNING("unhandled SUSPEND transition (%s)\n", | |
1928 | otg_state_string(musb)); | |
1929 | } | |
1930 | } | |
1931 | ||
1932 | /* Called during SRP */ | |
1933 | void musb_g_wakeup(struct musb *musb) | |
1934 | { | |
1935 | musb_gadget_wakeup(&musb->g); | |
1936 | } | |
1937 | ||
1938 | /* called when VBUS drops below session threshold, and in other cases */ | |
1939 | void musb_g_disconnect(struct musb *musb) | |
1940 | { | |
1941 | void __iomem *mregs = musb->mregs; | |
1942 | u8 devctl = musb_readb(mregs, MUSB_DEVCTL); | |
1943 | ||
1944 | DBG(3, "devctl %02x\n", devctl); | |
1945 | ||
1946 | /* clear HR */ | |
1947 | musb_writeb(mregs, MUSB_DEVCTL, devctl & MUSB_DEVCTL_SESSION); | |
1948 | ||
1949 | /* don't draw vbus until new b-default session */ | |
1950 | (void) musb_gadget_vbus_draw(&musb->g, 0); | |
1951 | ||
1952 | musb->g.speed = USB_SPEED_UNKNOWN; | |
1953 | if (musb->gadget_driver && musb->gadget_driver->disconnect) { | |
1954 | spin_unlock(&musb->lock); | |
1955 | musb->gadget_driver->disconnect(&musb->g); | |
1956 | spin_lock(&musb->lock); | |
1957 | } | |
1958 | ||
1959 | switch (musb->xceiv->state) { | |
1960 | default: | |
1961 | #ifdef CONFIG_USB_MUSB_OTG | |
1962 | DBG(2, "Unhandled disconnect %s, setting a_idle\n", | |
1963 | otg_state_string(musb)); | |
1964 | musb->xceiv->state = OTG_STATE_A_IDLE; | |
1965 | MUSB_HST_MODE(musb); | |
1966 | break; | |
1967 | case OTG_STATE_A_PERIPHERAL: | |
1968 | musb->xceiv->state = OTG_STATE_A_WAIT_BCON; | |
1969 | MUSB_HST_MODE(musb); | |
1970 | break; | |
1971 | case OTG_STATE_B_WAIT_ACON: | |
1972 | case OTG_STATE_B_HOST: | |
1973 | #endif | |
1974 | case OTG_STATE_B_PERIPHERAL: | |
1975 | case OTG_STATE_B_IDLE: | |
1976 | musb->xceiv->state = OTG_STATE_B_IDLE; | |
1977 | break; | |
1978 | case OTG_STATE_B_SRP_INIT: | |
1979 | break; | |
1980 | } | |
1981 | ||
1982 | musb->is_active = 0; | |
1983 | } | |
1984 | ||
1985 | void musb_g_reset(struct musb *musb) | |
1986 | __releases(musb->lock) | |
1987 | __acquires(musb->lock) | |
1988 | { | |
1989 | void __iomem *mbase = musb->mregs; | |
1990 | u8 devctl = musb_readb(mbase, MUSB_DEVCTL); | |
1991 | u8 power; | |
1992 | ||
1993 | DBG(3, "<== %s addr=%x driver '%s'\n", | |
1994 | (devctl & MUSB_DEVCTL_BDEVICE) | |
1995 | ? "B-Device" : "A-Device", | |
1996 | musb_readb(mbase, MUSB_FADDR), | |
1997 | musb->gadget_driver | |
1998 | ? musb->gadget_driver->driver.name | |
1999 | : NULL | |
2000 | ); | |
2001 | ||
2002 | /* report disconnect, if we didn't already (flushing EP state) */ | |
2003 | if (musb->g.speed != USB_SPEED_UNKNOWN) | |
2004 | musb_g_disconnect(musb); | |
2005 | ||
2006 | /* clear HR */ | |
2007 | else if (devctl & MUSB_DEVCTL_HR) | |
2008 | musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION); | |
2009 | ||
2010 | ||
2011 | /* what speed did we negotiate? */ | |
2012 | power = musb_readb(mbase, MUSB_POWER); | |
2013 | musb->g.speed = (power & MUSB_POWER_HSMODE) | |
2014 | ? USB_SPEED_HIGH : USB_SPEED_FULL; | |
2015 | ||
2016 | /* start in USB_STATE_DEFAULT */ | |
2017 | musb->is_active = 1; | |
2018 | musb->is_suspended = 0; | |
2019 | MUSB_DEV_MODE(musb); | |
2020 | musb->address = 0; | |
2021 | musb->ep0_state = MUSB_EP0_STAGE_SETUP; | |
2022 | ||
2023 | musb->may_wakeup = 0; | |
2024 | musb->g.b_hnp_enable = 0; | |
2025 | musb->g.a_alt_hnp_support = 0; | |
2026 | musb->g.a_hnp_support = 0; | |
2027 | ||
2028 | /* Normal reset, as B-Device; | |
2029 | * or else after HNP, as A-Device | |
2030 | */ | |
2031 | if (devctl & MUSB_DEVCTL_BDEVICE) { | |
2032 | musb->xceiv->state = OTG_STATE_B_PERIPHERAL; | |
2033 | musb->g.is_a_peripheral = 0; | |
2034 | } else if (is_otg_enabled(musb)) { | |
2035 | musb->xceiv->state = OTG_STATE_A_PERIPHERAL; | |
2036 | musb->g.is_a_peripheral = 1; | |
2037 | } else | |
2038 | WARN_ON(1); | |
2039 | ||
2040 | /* start with default limits on VBUS power draw */ | |
2041 | (void) musb_gadget_vbus_draw(&musb->g, | |
2042 | is_otg_enabled(musb) ? 8 : 100); | |
2043 | } |