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1 | /* | |
2 | * Frame buffer driver for Trident TGUI, Blade and Image series | |
3 | * | |
4 | * Copyright 2001, 2002 - Jani Monoses <jani@iv.ro> | |
5 | * | |
6 | * | |
7 | * CREDITS:(in order of appearance) | |
8 | * skeletonfb.c by Geert Uytterhoeven and other fb code in drivers/video | |
9 | * Special thanks ;) to Mattia Crivellini <tia@mclink.it> | |
10 | * much inspired by the XFree86 4.x Trident driver sources | |
11 | * by Alan Hourihane the FreeVGA project | |
12 | * Francesco Salvestrini <salvestrini@users.sf.net> XP support, | |
13 | * code, suggestions | |
14 | * TODO: | |
15 | * timing value tweaking so it looks good on every monitor in every mode | |
16 | */ | |
17 | ||
18 | #include <linux/module.h> | |
19 | #include <linux/fb.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/pci.h> | |
22 | ||
23 | #include <linux/delay.h> | |
24 | #include <video/vga.h> | |
25 | #include <video/trident.h> | |
26 | ||
27 | struct tridentfb_par { | |
28 | void __iomem *io_virt; /* iospace virtual memory address */ | |
29 | u32 pseudo_pal[16]; | |
30 | int chip_id; | |
31 | int flatpanel; | |
32 | void (*init_accel) (struct tridentfb_par *, int, int); | |
33 | void (*wait_engine) (struct tridentfb_par *); | |
34 | void (*fill_rect) | |
35 | (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32); | |
36 | void (*copy_rect) | |
37 | (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32); | |
38 | unsigned char eng_oper; /* engine operation... */ | |
39 | }; | |
40 | ||
41 | static struct fb_ops tridentfb_ops; | |
42 | ||
43 | static struct fb_fix_screeninfo tridentfb_fix = { | |
44 | .id = "Trident", | |
45 | .type = FB_TYPE_PACKED_PIXELS, | |
46 | .ypanstep = 1, | |
47 | .visual = FB_VISUAL_PSEUDOCOLOR, | |
48 | .accel = FB_ACCEL_NONE, | |
49 | }; | |
50 | ||
51 | /* defaults which are normally overriden by user values */ | |
52 | ||
53 | /* video mode */ | |
54 | static char *mode_option __devinitdata = "640x480-8@60"; | |
55 | static int bpp __devinitdata = 8; | |
56 | ||
57 | static int noaccel __devinitdata; | |
58 | ||
59 | static int center; | |
60 | static int stretch; | |
61 | ||
62 | static int fp __devinitdata; | |
63 | static int crt __devinitdata; | |
64 | ||
65 | static int memsize __devinitdata; | |
66 | static int memdiff __devinitdata; | |
67 | static int nativex; | |
68 | ||
69 | module_param(mode_option, charp, 0); | |
70 | MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'"); | |
71 | module_param_named(mode, mode_option, charp, 0); | |
72 | MODULE_PARM_DESC(mode, "Initial video mode e.g. '648x480-8@60' (deprecated)"); | |
73 | module_param(bpp, int, 0); | |
74 | module_param(center, int, 0); | |
75 | module_param(stretch, int, 0); | |
76 | module_param(noaccel, int, 0); | |
77 | module_param(memsize, int, 0); | |
78 | module_param(memdiff, int, 0); | |
79 | module_param(nativex, int, 0); | |
80 | module_param(fp, int, 0); | |
81 | MODULE_PARM_DESC(fp, "Define if flatpanel is connected"); | |
82 | module_param(crt, int, 0); | |
83 | MODULE_PARM_DESC(crt, "Define if CRT is connected"); | |
84 | ||
85 | static inline int is_oldclock(int id) | |
86 | { | |
87 | return (id == TGUI9440) || | |
88 | (id == TGUI9660) || | |
89 | (id == CYBER9320); | |
90 | } | |
91 | ||
92 | static inline int is_oldprotect(int id) | |
93 | { | |
94 | return is_oldclock(id) || | |
95 | (id == PROVIDIA9685) || | |
96 | (id == CYBER9382) || | |
97 | (id == CYBER9385); | |
98 | } | |
99 | ||
100 | static inline int is_blade(int id) | |
101 | { | |
102 | return (id == BLADE3D) || | |
103 | (id == CYBERBLADEE4) || | |
104 | (id == CYBERBLADEi7) || | |
105 | (id == CYBERBLADEi7D) || | |
106 | (id == CYBERBLADEi1) || | |
107 | (id == CYBERBLADEi1D) || | |
108 | (id == CYBERBLADEAi1) || | |
109 | (id == CYBERBLADEAi1D); | |
110 | } | |
111 | ||
112 | static inline int is_xp(int id) | |
113 | { | |
114 | return (id == CYBERBLADEXPAi1) || | |
115 | (id == CYBERBLADEXPm8) || | |
116 | (id == CYBERBLADEXPm16); | |
117 | } | |
118 | ||
119 | static inline int is3Dchip(int id) | |
120 | { | |
121 | return is_blade(id) || is_xp(id) || | |
122 | (id == CYBER9397) || (id == CYBER9397DVD) || | |
123 | (id == CYBER9520) || (id == CYBER9525DVD) || | |
124 | (id == IMAGE975) || (id == IMAGE985); | |
125 | } | |
126 | ||
127 | static inline int iscyber(int id) | |
128 | { | |
129 | switch (id) { | |
130 | case CYBER9388: | |
131 | case CYBER9382: | |
132 | case CYBER9385: | |
133 | case CYBER9397: | |
134 | case CYBER9397DVD: | |
135 | case CYBER9520: | |
136 | case CYBER9525DVD: | |
137 | case CYBERBLADEE4: | |
138 | case CYBERBLADEi7D: | |
139 | case CYBERBLADEi1: | |
140 | case CYBERBLADEi1D: | |
141 | case CYBERBLADEAi1: | |
142 | case CYBERBLADEAi1D: | |
143 | case CYBERBLADEXPAi1: | |
144 | return 1; | |
145 | ||
146 | case CYBER9320: | |
147 | case CYBERBLADEi7: /* VIA MPV4 integrated version */ | |
148 | default: | |
149 | /* case CYBERBLDAEXPm8: Strange */ | |
150 | /* case CYBERBLDAEXPm16: Strange */ | |
151 | return 0; | |
152 | } | |
153 | } | |
154 | ||
155 | static inline void t_outb(struct tridentfb_par *p, u8 val, u16 reg) | |
156 | { | |
157 | fb_writeb(val, p->io_virt + reg); | |
158 | } | |
159 | ||
160 | static inline u8 t_inb(struct tridentfb_par *p, u16 reg) | |
161 | { | |
162 | return fb_readb(p->io_virt + reg); | |
163 | } | |
164 | ||
165 | static inline void writemmr(struct tridentfb_par *par, u16 r, u32 v) | |
166 | { | |
167 | fb_writel(v, par->io_virt + r); | |
168 | } | |
169 | ||
170 | static inline u32 readmmr(struct tridentfb_par *par, u16 r) | |
171 | { | |
172 | return fb_readl(par->io_virt + r); | |
173 | } | |
174 | ||
175 | /* | |
176 | * Blade specific acceleration. | |
177 | */ | |
178 | ||
179 | #define point(x, y) ((y) << 16 | (x)) | |
180 | ||
181 | static void blade_init_accel(struct tridentfb_par *par, int pitch, int bpp) | |
182 | { | |
183 | int v1 = (pitch >> 3) << 20; | |
184 | int tmp = bpp == 24 ? 2 : (bpp >> 4); | |
185 | int v2 = v1 | (tmp << 29); | |
186 | ||
187 | writemmr(par, 0x21C0, v2); | |
188 | writemmr(par, 0x21C4, v2); | |
189 | writemmr(par, 0x21B8, v2); | |
190 | writemmr(par, 0x21BC, v2); | |
191 | writemmr(par, 0x21D0, v1); | |
192 | writemmr(par, 0x21D4, v1); | |
193 | writemmr(par, 0x21C8, v1); | |
194 | writemmr(par, 0x21CC, v1); | |
195 | writemmr(par, 0x216C, 0); | |
196 | } | |
197 | ||
198 | static void blade_wait_engine(struct tridentfb_par *par) | |
199 | { | |
200 | while (readmmr(par, STATUS) & 0xFA800000) | |
201 | cpu_relax(); | |
202 | } | |
203 | ||
204 | static void blade_fill_rect(struct tridentfb_par *par, | |
205 | u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop) | |
206 | { | |
207 | writemmr(par, COLOR, c); | |
208 | writemmr(par, ROP, rop ? ROP_X : ROP_S); | |
209 | writemmr(par, CMD, 0x20000000 | 1 << 19 | 1 << 4 | 2 << 2); | |
210 | ||
211 | writemmr(par, DST1, point(x, y)); | |
212 | writemmr(par, DST2, point(x + w - 1, y + h - 1)); | |
213 | } | |
214 | ||
215 | static void blade_copy_rect(struct tridentfb_par *par, | |
216 | u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h) | |
217 | { | |
218 | int direction = 2; | |
219 | u32 s1 = point(x1, y1); | |
220 | u32 s2 = point(x1 + w - 1, y1 + h - 1); | |
221 | u32 d1 = point(x2, y2); | |
222 | u32 d2 = point(x2 + w - 1, y2 + h - 1); | |
223 | ||
224 | if ((y1 > y2) || ((y1 == y2) && (x1 > x2))) | |
225 | direction = 0; | |
226 | ||
227 | writemmr(par, ROP, ROP_S); | |
228 | writemmr(par, CMD, 0xE0000000 | 1 << 19 | 1 << 4 | 1 << 2 | direction); | |
229 | ||
230 | writemmr(par, SRC1, direction ? s2 : s1); | |
231 | writemmr(par, SRC2, direction ? s1 : s2); | |
232 | writemmr(par, DST1, direction ? d2 : d1); | |
233 | writemmr(par, DST2, direction ? d1 : d2); | |
234 | } | |
235 | ||
236 | /* | |
237 | * BladeXP specific acceleration functions | |
238 | */ | |
239 | ||
240 | static void xp_init_accel(struct tridentfb_par *par, int pitch, int bpp) | |
241 | { | |
242 | unsigned char x = bpp == 24 ? 3 : (bpp >> 4); | |
243 | int v1 = pitch << (bpp == 24 ? 20 : (18 + x)); | |
244 | ||
245 | switch (pitch << (bpp >> 3)) { | |
246 | case 8192: | |
247 | case 512: | |
248 | x |= 0x00; | |
249 | break; | |
250 | case 1024: | |
251 | x |= 0x04; | |
252 | break; | |
253 | case 2048: | |
254 | x |= 0x08; | |
255 | break; | |
256 | case 4096: | |
257 | x |= 0x0C; | |
258 | break; | |
259 | } | |
260 | ||
261 | t_outb(par, x, 0x2125); | |
262 | ||
263 | par->eng_oper = x | 0x40; | |
264 | ||
265 | writemmr(par, 0x2154, v1); | |
266 | writemmr(par, 0x2150, v1); | |
267 | t_outb(par, 3, 0x2126); | |
268 | } | |
269 | ||
270 | static void xp_wait_engine(struct tridentfb_par *par) | |
271 | { | |
272 | int count = 0; | |
273 | int timeout = 0; | |
274 | ||
275 | while (t_inb(par, STATUS) & 0x80) { | |
276 | count++; | |
277 | if (count == 10000000) { | |
278 | /* Timeout */ | |
279 | count = 9990000; | |
280 | timeout++; | |
281 | if (timeout == 8) { | |
282 | /* Reset engine */ | |
283 | t_outb(par, 0x00, STATUS); | |
284 | return; | |
285 | } | |
286 | } | |
287 | cpu_relax(); | |
288 | } | |
289 | } | |
290 | ||
291 | static void xp_fill_rect(struct tridentfb_par *par, | |
292 | u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop) | |
293 | { | |
294 | writemmr(par, 0x2127, ROP_P); | |
295 | writemmr(par, 0x2158, c); | |
296 | writemmr(par, DRAWFL, 0x4000); | |
297 | writemmr(par, OLDDIM, point(h, w)); | |
298 | writemmr(par, OLDDST, point(y, x)); | |
299 | t_outb(par, 0x01, OLDCMD); | |
300 | t_outb(par, par->eng_oper, 0x2125); | |
301 | } | |
302 | ||
303 | static void xp_copy_rect(struct tridentfb_par *par, | |
304 | u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h) | |
305 | { | |
306 | u32 x1_tmp, x2_tmp, y1_tmp, y2_tmp; | |
307 | int direction = 0x0004; | |
308 | ||
309 | if ((x1 < x2) && (y1 == y2)) { | |
310 | direction |= 0x0200; | |
311 | x1_tmp = x1 + w - 1; | |
312 | x2_tmp = x2 + w - 1; | |
313 | } else { | |
314 | x1_tmp = x1; | |
315 | x2_tmp = x2; | |
316 | } | |
317 | ||
318 | if (y1 < y2) { | |
319 | direction |= 0x0100; | |
320 | y1_tmp = y1 + h - 1; | |
321 | y2_tmp = y2 + h - 1; | |
322 | } else { | |
323 | y1_tmp = y1; | |
324 | y2_tmp = y2; | |
325 | } | |
326 | ||
327 | writemmr(par, DRAWFL, direction); | |
328 | t_outb(par, ROP_S, 0x2127); | |
329 | writemmr(par, OLDSRC, point(y1_tmp, x1_tmp)); | |
330 | writemmr(par, OLDDST, point(y2_tmp, x2_tmp)); | |
331 | writemmr(par, OLDDIM, point(h, w)); | |
332 | t_outb(par, 0x01, OLDCMD); | |
333 | } | |
334 | ||
335 | /* | |
336 | * Image specific acceleration functions | |
337 | */ | |
338 | static void image_init_accel(struct tridentfb_par *par, int pitch, int bpp) | |
339 | { | |
340 | int tmp = bpp == 24 ? 2: (bpp >> 4); | |
341 | ||
342 | writemmr(par, 0x2120, 0xF0000000); | |
343 | writemmr(par, 0x2120, 0x40000000 | tmp); | |
344 | writemmr(par, 0x2120, 0x80000000); | |
345 | writemmr(par, 0x2144, 0x00000000); | |
346 | writemmr(par, 0x2148, 0x00000000); | |
347 | writemmr(par, 0x2150, 0x00000000); | |
348 | writemmr(par, 0x2154, 0x00000000); | |
349 | writemmr(par, 0x2120, 0x60000000 | (pitch << 16) | pitch); | |
350 | writemmr(par, 0x216C, 0x00000000); | |
351 | writemmr(par, 0x2170, 0x00000000); | |
352 | writemmr(par, 0x217C, 0x00000000); | |
353 | writemmr(par, 0x2120, 0x10000000); | |
354 | writemmr(par, 0x2130, (2047 << 16) | 2047); | |
355 | } | |
356 | ||
357 | static void image_wait_engine(struct tridentfb_par *par) | |
358 | { | |
359 | while (readmmr(par, 0x2164) & 0xF0000000) | |
360 | cpu_relax(); | |
361 | } | |
362 | ||
363 | static void image_fill_rect(struct tridentfb_par *par, | |
364 | u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop) | |
365 | { | |
366 | writemmr(par, 0x2120, 0x80000000); | |
367 | writemmr(par, 0x2120, 0x90000000 | ROP_S); | |
368 | ||
369 | writemmr(par, 0x2144, c); | |
370 | ||
371 | writemmr(par, DST1, point(x, y)); | |
372 | writemmr(par, DST2, point(x + w - 1, y + h - 1)); | |
373 | ||
374 | writemmr(par, 0x2124, 0x80000000 | 3 << 22 | 1 << 10 | 1 << 9); | |
375 | } | |
376 | ||
377 | static void image_copy_rect(struct tridentfb_par *par, | |
378 | u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h) | |
379 | { | |
380 | int direction = 0x4; | |
381 | u32 s1 = point(x1, y1); | |
382 | u32 s2 = point(x1 + w - 1, y1 + h - 1); | |
383 | u32 d1 = point(x2, y2); | |
384 | u32 d2 = point(x2 + w - 1, y2 + h - 1); | |
385 | ||
386 | if ((y1 > y2) || ((y1 == y2) && (x1 > x2))) | |
387 | direction = 0; | |
388 | ||
389 | writemmr(par, 0x2120, 0x80000000); | |
390 | writemmr(par, 0x2120, 0x90000000 | ROP_S); | |
391 | ||
392 | writemmr(par, SRC1, direction ? s2 : s1); | |
393 | writemmr(par, SRC2, direction ? s1 : s2); | |
394 | writemmr(par, DST1, direction ? d2 : d1); | |
395 | writemmr(par, DST2, direction ? d1 : d2); | |
396 | writemmr(par, 0x2124, | |
397 | 0x80000000 | 1 << 22 | 1 << 10 | 1 << 7 | direction); | |
398 | } | |
399 | ||
400 | /* | |
401 | * TGUI 9440/96XX acceleration | |
402 | */ | |
403 | ||
404 | static void tgui_init_accel(struct tridentfb_par *par, int pitch, int bpp) | |
405 | { | |
406 | unsigned char x = bpp == 24 ? 3 : (bpp >> 4); | |
407 | ||
408 | /* disable clipping */ | |
409 | writemmr(par, 0x2148, 0); | |
410 | writemmr(par, 0x214C, point(4095, 2047)); | |
411 | ||
412 | switch ((pitch * bpp) / 8) { | |
413 | case 8192: | |
414 | case 512: | |
415 | x |= 0x00; | |
416 | break; | |
417 | case 1024: | |
418 | x |= 0x04; | |
419 | break; | |
420 | case 2048: | |
421 | x |= 0x08; | |
422 | break; | |
423 | case 4096: | |
424 | x |= 0x0C; | |
425 | break; | |
426 | } | |
427 | ||
428 | fb_writew(x, par->io_virt + 0x2122); | |
429 | } | |
430 | ||
431 | static void tgui_fill_rect(struct tridentfb_par *par, | |
432 | u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop) | |
433 | { | |
434 | t_outb(par, ROP_P, 0x2127); | |
435 | writemmr(par, OLDCLR, c); | |
436 | writemmr(par, DRAWFL, 0x4020); | |
437 | writemmr(par, OLDDIM, point(w - 1, h - 1)); | |
438 | writemmr(par, OLDDST, point(x, y)); | |
439 | t_outb(par, 1, OLDCMD); | |
440 | } | |
441 | ||
442 | static void tgui_copy_rect(struct tridentfb_par *par, | |
443 | u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h) | |
444 | { | |
445 | int flags = 0; | |
446 | u16 x1_tmp, x2_tmp, y1_tmp, y2_tmp; | |
447 | ||
448 | if ((x1 < x2) && (y1 == y2)) { | |
449 | flags |= 0x0200; | |
450 | x1_tmp = x1 + w - 1; | |
451 | x2_tmp = x2 + w - 1; | |
452 | } else { | |
453 | x1_tmp = x1; | |
454 | x2_tmp = x2; | |
455 | } | |
456 | ||
457 | if (y1 < y2) { | |
458 | flags |= 0x0100; | |
459 | y1_tmp = y1 + h - 1; | |
460 | y2_tmp = y2 + h - 1; | |
461 | } else { | |
462 | y1_tmp = y1; | |
463 | y2_tmp = y2; | |
464 | } | |
465 | ||
466 | writemmr(par, DRAWFL, 0x4 | flags); | |
467 | t_outb(par, ROP_S, 0x2127); | |
468 | writemmr(par, OLDSRC, point(x1_tmp, y1_tmp)); | |
469 | writemmr(par, OLDDST, point(x2_tmp, y2_tmp)); | |
470 | writemmr(par, OLDDIM, point(w - 1, h - 1)); | |
471 | t_outb(par, 1, OLDCMD); | |
472 | } | |
473 | ||
474 | /* | |
475 | * Accel functions called by the upper layers | |
476 | */ | |
477 | #ifdef CONFIG_FB_TRIDENT_ACCEL | |
478 | static void tridentfb_fillrect(struct fb_info *info, | |
479 | const struct fb_fillrect *fr) | |
480 | { | |
481 | struct tridentfb_par *par = info->par; | |
482 | int col; | |
483 | ||
484 | if (info->flags & FBINFO_HWACCEL_DISABLED) { | |
485 | cfb_fillrect(info, fr); | |
486 | return; | |
487 | } | |
488 | if (info->var.bits_per_pixel == 8) { | |
489 | col = fr->color; | |
490 | col |= col << 8; | |
491 | col |= col << 16; | |
492 | } else | |
493 | col = ((u32 *)(info->pseudo_palette))[fr->color]; | |
494 | ||
495 | par->wait_engine(par); | |
496 | par->fill_rect(par, fr->dx, fr->dy, fr->width, | |
497 | fr->height, col, fr->rop); | |
498 | } | |
499 | ||
500 | static void tridentfb_copyarea(struct fb_info *info, | |
501 | const struct fb_copyarea *ca) | |
502 | { | |
503 | struct tridentfb_par *par = info->par; | |
504 | ||
505 | if (info->flags & FBINFO_HWACCEL_DISABLED) { | |
506 | cfb_copyarea(info, ca); | |
507 | return; | |
508 | } | |
509 | par->wait_engine(par); | |
510 | par->copy_rect(par, ca->sx, ca->sy, ca->dx, ca->dy, | |
511 | ca->width, ca->height); | |
512 | } | |
513 | ||
514 | static int tridentfb_sync(struct fb_info *info) | |
515 | { | |
516 | struct tridentfb_par *par = info->par; | |
517 | ||
518 | if (!(info->flags & FBINFO_HWACCEL_DISABLED)) | |
519 | par->wait_engine(par); | |
520 | return 0; | |
521 | } | |
522 | #else | |
523 | #define tridentfb_fillrect cfb_fillrect | |
524 | #define tridentfb_copyarea cfb_copyarea | |
525 | #endif /* CONFIG_FB_TRIDENT_ACCEL */ | |
526 | ||
527 | /* | |
528 | * Hardware access functions | |
529 | */ | |
530 | ||
531 | static inline unsigned char read3X4(struct tridentfb_par *par, int reg) | |
532 | { | |
533 | return vga_mm_rcrt(par->io_virt, reg); | |
534 | } | |
535 | ||
536 | static inline void write3X4(struct tridentfb_par *par, int reg, | |
537 | unsigned char val) | |
538 | { | |
539 | vga_mm_wcrt(par->io_virt, reg, val); | |
540 | } | |
541 | ||
542 | static inline unsigned char read3CE(struct tridentfb_par *par, | |
543 | unsigned char reg) | |
544 | { | |
545 | return vga_mm_rgfx(par->io_virt, reg); | |
546 | } | |
547 | ||
548 | static inline void writeAttr(struct tridentfb_par *par, int reg, | |
549 | unsigned char val) | |
550 | { | |
551 | fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */ | |
552 | vga_mm_wattr(par->io_virt, reg, val); | |
553 | } | |
554 | ||
555 | static inline void write3CE(struct tridentfb_par *par, int reg, | |
556 | unsigned char val) | |
557 | { | |
558 | vga_mm_wgfx(par->io_virt, reg, val); | |
559 | } | |
560 | ||
561 | static void enable_mmio(struct tridentfb_par *par) | |
562 | { | |
563 | /* Goto New Mode */ | |
564 | vga_io_rseq(0x0B); | |
565 | ||
566 | /* Unprotect registers */ | |
567 | vga_io_wseq(NewMode1, 0x80); | |
568 | if (!is_oldprotect(par->chip_id)) | |
569 | vga_io_wseq(Protection, 0x92); | |
570 | ||
571 | /* Enable MMIO */ | |
572 | outb(PCIReg, 0x3D4); | |
573 | outb(inb(0x3D5) | 0x01, 0x3D5); | |
574 | } | |
575 | ||
576 | static void disable_mmio(struct tridentfb_par *par) | |
577 | { | |
578 | /* Goto New Mode */ | |
579 | vga_mm_rseq(par->io_virt, 0x0B); | |
580 | ||
581 | /* Unprotect registers */ | |
582 | vga_mm_wseq(par->io_virt, NewMode1, 0x80); | |
583 | if (!is_oldprotect(par->chip_id)) | |
584 | vga_mm_wseq(par->io_virt, Protection, 0x92); | |
585 | ||
586 | /* Disable MMIO */ | |
587 | t_outb(par, PCIReg, 0x3D4); | |
588 | t_outb(par, t_inb(par, 0x3D5) & ~0x01, 0x3D5); | |
589 | } | |
590 | ||
591 | static inline void crtc_unlock(struct tridentfb_par *par) | |
592 | { | |
593 | write3X4(par, VGA_CRTC_V_SYNC_END, | |
594 | read3X4(par, VGA_CRTC_V_SYNC_END) & 0x7F); | |
595 | } | |
596 | ||
597 | /* Return flat panel's maximum x resolution */ | |
598 | static int __devinit get_nativex(struct tridentfb_par *par) | |
599 | { | |
600 | int x, y, tmp; | |
601 | ||
602 | if (nativex) | |
603 | return nativex; | |
604 | ||
605 | tmp = (read3CE(par, VertStretch) >> 4) & 3; | |
606 | ||
607 | switch (tmp) { | |
608 | case 0: | |
609 | x = 1280; y = 1024; | |
610 | break; | |
611 | case 2: | |
612 | x = 1024; y = 768; | |
613 | break; | |
614 | case 3: | |
615 | x = 800; y = 600; | |
616 | break; | |
617 | case 4: | |
618 | x = 1400; y = 1050; | |
619 | break; | |
620 | case 1: | |
621 | default: | |
622 | x = 640; y = 480; | |
623 | break; | |
624 | } | |
625 | ||
626 | output("%dx%d flat panel found\n", x, y); | |
627 | return x; | |
628 | } | |
629 | ||
630 | /* Set pitch */ | |
631 | static inline void set_lwidth(struct tridentfb_par *par, int width) | |
632 | { | |
633 | write3X4(par, VGA_CRTC_OFFSET, width & 0xFF); | |
634 | write3X4(par, AddColReg, | |
635 | (read3X4(par, AddColReg) & 0xCF) | ((width & 0x300) >> 4)); | |
636 | } | |
637 | ||
638 | /* For resolutions smaller than FP resolution stretch */ | |
639 | static void screen_stretch(struct tridentfb_par *par) | |
640 | { | |
641 | if (par->chip_id != CYBERBLADEXPAi1) | |
642 | write3CE(par, BiosReg, 0); | |
643 | else | |
644 | write3CE(par, BiosReg, 8); | |
645 | write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 1); | |
646 | write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 1); | |
647 | } | |
648 | ||
649 | /* For resolutions smaller than FP resolution center */ | |
650 | static inline void screen_center(struct tridentfb_par *par) | |
651 | { | |
652 | write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 0x80); | |
653 | write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 0x80); | |
654 | } | |
655 | ||
656 | /* Address of first shown pixel in display memory */ | |
657 | static void set_screen_start(struct tridentfb_par *par, int base) | |
658 | { | |
659 | u8 tmp; | |
660 | write3X4(par, VGA_CRTC_START_LO, base & 0xFF); | |
661 | write3X4(par, VGA_CRTC_START_HI, (base & 0xFF00) >> 8); | |
662 | tmp = read3X4(par, CRTCModuleTest) & 0xDF; | |
663 | write3X4(par, CRTCModuleTest, tmp | ((base & 0x10000) >> 11)); | |
664 | tmp = read3X4(par, CRTHiOrd) & 0xF8; | |
665 | write3X4(par, CRTHiOrd, tmp | ((base & 0xE0000) >> 17)); | |
666 | } | |
667 | ||
668 | /* Set dotclock frequency */ | |
669 | static void set_vclk(struct tridentfb_par *par, unsigned long freq) | |
670 | { | |
671 | int m, n, k; | |
672 | unsigned long fi, d, di; | |
673 | unsigned char best_m = 0, best_n = 0, best_k = 0; | |
674 | unsigned char hi, lo; | |
675 | ||
676 | d = 20000; | |
677 | for (k = 1; k >= 0; k--) | |
678 | for (m = 0; m < 32; m++) { | |
679 | n = 2 * (m + 2) - 8; | |
680 | for (n = (n < 0 ? 0 : n); n < 122; n++) { | |
681 | fi = ((14318l * (n + 8)) / (m + 2)) >> k; | |
682 | di = abs(fi - freq); | |
683 | if (di <= d) { | |
684 | d = di; | |
685 | best_n = n; | |
686 | best_m = m; | |
687 | best_k = k; | |
688 | } | |
689 | if (fi > freq) | |
690 | break; | |
691 | } | |
692 | } | |
693 | ||
694 | if (is_oldclock(par->chip_id)) { | |
695 | lo = best_n | (best_m << 7); | |
696 | hi = (best_m >> 1) | (best_k << 4); | |
697 | } else { | |
698 | lo = best_n; | |
699 | hi = best_m | (best_k << 6); | |
700 | } | |
701 | ||
702 | if (is3Dchip(par->chip_id)) { | |
703 | vga_mm_wseq(par->io_virt, ClockHigh, hi); | |
704 | vga_mm_wseq(par->io_virt, ClockLow, lo); | |
705 | } else { | |
706 | t_outb(par, lo, 0x43C8); | |
707 | t_outb(par, hi, 0x43C9); | |
708 | } | |
709 | debug("VCLK = %X %X\n", hi, lo); | |
710 | } | |
711 | ||
712 | /* Set number of lines for flat panels*/ | |
713 | static void set_number_of_lines(struct tridentfb_par *par, int lines) | |
714 | { | |
715 | int tmp = read3CE(par, CyberEnhance) & 0x8F; | |
716 | if (lines > 1024) | |
717 | tmp |= 0x50; | |
718 | else if (lines > 768) | |
719 | tmp |= 0x30; | |
720 | else if (lines > 600) | |
721 | tmp |= 0x20; | |
722 | else if (lines > 480) | |
723 | tmp |= 0x10; | |
724 | write3CE(par, CyberEnhance, tmp); | |
725 | } | |
726 | ||
727 | /* | |
728 | * If we see that FP is active we assume we have one. | |
729 | * Otherwise we have a CRT display. User can override. | |
730 | */ | |
731 | static int __devinit is_flatpanel(struct tridentfb_par *par) | |
732 | { | |
733 | if (fp) | |
734 | return 1; | |
735 | if (crt || !iscyber(par->chip_id)) | |
736 | return 0; | |
737 | return (read3CE(par, FPConfig) & 0x10) ? 1 : 0; | |
738 | } | |
739 | ||
740 | /* Try detecting the video memory size */ | |
741 | static unsigned int __devinit get_memsize(struct tridentfb_par *par) | |
742 | { | |
743 | unsigned char tmp, tmp2; | |
744 | unsigned int k; | |
745 | ||
746 | /* If memory size provided by user */ | |
747 | if (memsize) | |
748 | k = memsize * Kb; | |
749 | else | |
750 | switch (par->chip_id) { | |
751 | case CYBER9525DVD: | |
752 | k = 2560 * Kb; | |
753 | break; | |
754 | default: | |
755 | tmp = read3X4(par, SPR) & 0x0F; | |
756 | switch (tmp) { | |
757 | ||
758 | case 0x01: | |
759 | k = 512 * Kb; | |
760 | break; | |
761 | case 0x02: | |
762 | k = 6 * Mb; /* XP */ | |
763 | break; | |
764 | case 0x03: | |
765 | k = 1 * Mb; | |
766 | break; | |
767 | case 0x04: | |
768 | k = 8 * Mb; | |
769 | break; | |
770 | case 0x06: | |
771 | k = 10 * Mb; /* XP */ | |
772 | break; | |
773 | case 0x07: | |
774 | k = 2 * Mb; | |
775 | break; | |
776 | case 0x08: | |
777 | k = 12 * Mb; /* XP */ | |
778 | break; | |
779 | case 0x0A: | |
780 | k = 14 * Mb; /* XP */ | |
781 | break; | |
782 | case 0x0C: | |
783 | k = 16 * Mb; /* XP */ | |
784 | break; | |
785 | case 0x0E: /* XP */ | |
786 | ||
787 | tmp2 = vga_mm_rseq(par->io_virt, 0xC1); | |
788 | switch (tmp2) { | |
789 | case 0x00: | |
790 | k = 20 * Mb; | |
791 | break; | |
792 | case 0x01: | |
793 | k = 24 * Mb; | |
794 | break; | |
795 | case 0x10: | |
796 | k = 28 * Mb; | |
797 | break; | |
798 | case 0x11: | |
799 | k = 32 * Mb; | |
800 | break; | |
801 | default: | |
802 | k = 1 * Mb; | |
803 | break; | |
804 | } | |
805 | break; | |
806 | ||
807 | case 0x0F: | |
808 | k = 4 * Mb; | |
809 | break; | |
810 | default: | |
811 | k = 1 * Mb; | |
812 | break; | |
813 | } | |
814 | } | |
815 | ||
816 | k -= memdiff * Kb; | |
817 | output("framebuffer size = %d Kb\n", k / Kb); | |
818 | return k; | |
819 | } | |
820 | ||
821 | /* See if we can handle the video mode described in var */ | |
822 | static int tridentfb_check_var(struct fb_var_screeninfo *var, | |
823 | struct fb_info *info) | |
824 | { | |
825 | struct tridentfb_par *par = info->par; | |
826 | int bpp = var->bits_per_pixel; | |
827 | int line_length; | |
828 | int ramdac = 230000; /* 230MHz for most 3D chips */ | |
829 | debug("enter\n"); | |
830 | ||
831 | /* check color depth */ | |
832 | if (bpp == 24) | |
833 | bpp = var->bits_per_pixel = 32; | |
834 | if (bpp != 8 && bpp != 16 && bpp != 32) | |
835 | return -EINVAL; | |
836 | if (par->chip_id == TGUI9440 && bpp == 32) | |
837 | return -EINVAL; | |
838 | /* check whether resolution fits on panel and in memory */ | |
839 | if (par->flatpanel && nativex && var->xres > nativex) | |
840 | return -EINVAL; | |
841 | /* various resolution checks */ | |
842 | var->xres = (var->xres + 7) & ~0x7; | |
843 | if (var->xres > var->xres_virtual) | |
844 | var->xres_virtual = var->xres; | |
845 | if (var->yres > var->yres_virtual) | |
846 | var->yres_virtual = var->yres; | |
847 | if (var->xres_virtual > 4095 || var->yres > 2048) | |
848 | return -EINVAL; | |
849 | /* prevent from position overflow for acceleration */ | |
850 | if (var->yres_virtual > 0xffff) | |
851 | return -EINVAL; | |
852 | line_length = var->xres_virtual * bpp / 8; | |
853 | ||
854 | if (!is3Dchip(par->chip_id) && | |
855 | !(info->flags & FBINFO_HWACCEL_DISABLED)) { | |
856 | /* acceleration requires line length to be power of 2 */ | |
857 | if (line_length <= 512) | |
858 | var->xres_virtual = 512 * 8 / bpp; | |
859 | else if (line_length <= 1024) | |
860 | var->xres_virtual = 1024 * 8 / bpp; | |
861 | else if (line_length <= 2048) | |
862 | var->xres_virtual = 2048 * 8 / bpp; | |
863 | else if (line_length <= 4096) | |
864 | var->xres_virtual = 4096 * 8 / bpp; | |
865 | else if (line_length <= 8192) | |
866 | var->xres_virtual = 8192 * 8 / bpp; | |
867 | else | |
868 | return -EINVAL; | |
869 | ||
870 | line_length = var->xres_virtual * bpp / 8; | |
871 | } | |
872 | ||
873 | /* datasheet specifies how to set panning only up to 4 MB */ | |
874 | if (line_length * (var->yres_virtual - var->yres) > (4 << 20)) | |
875 | var->yres_virtual = ((4 << 20) / line_length) + var->yres; | |
876 | ||
877 | if (line_length * var->yres_virtual > info->fix.smem_len) | |
878 | return -EINVAL; | |
879 | ||
880 | switch (bpp) { | |
881 | case 8: | |
882 | var->red.offset = 0; | |
883 | var->red.length = 8; | |
884 | var->green = var->red; | |
885 | var->blue = var->red; | |
886 | break; | |
887 | case 16: | |
888 | var->red.offset = 11; | |
889 | var->green.offset = 5; | |
890 | var->blue.offset = 0; | |
891 | var->red.length = 5; | |
892 | var->green.length = 6; | |
893 | var->blue.length = 5; | |
894 | break; | |
895 | case 32: | |
896 | var->red.offset = 16; | |
897 | var->green.offset = 8; | |
898 | var->blue.offset = 0; | |
899 | var->red.length = 8; | |
900 | var->green.length = 8; | |
901 | var->blue.length = 8; | |
902 | break; | |
903 | default: | |
904 | return -EINVAL; | |
905 | } | |
906 | ||
907 | if (is_xp(par->chip_id)) | |
908 | ramdac = 350000; | |
909 | ||
910 | switch (par->chip_id) { | |
911 | case TGUI9440: | |
912 | ramdac = (bpp >= 16) ? 45000 : 90000; | |
913 | break; | |
914 | case CYBER9320: | |
915 | case TGUI9660: | |
916 | ramdac = 135000; | |
917 | break; | |
918 | case PROVIDIA9685: | |
919 | case CYBER9388: | |
920 | case CYBER9382: | |
921 | case CYBER9385: | |
922 | ramdac = 170000; | |
923 | break; | |
924 | } | |
925 | ||
926 | /* The clock is doubled for 32 bpp */ | |
927 | if (bpp == 32) | |
928 | ramdac /= 2; | |
929 | ||
930 | if (PICOS2KHZ(var->pixclock) > ramdac) | |
931 | return -EINVAL; | |
932 | ||
933 | debug("exit\n"); | |
934 | ||
935 | return 0; | |
936 | ||
937 | } | |
938 | ||
939 | /* Pan the display */ | |
940 | static int tridentfb_pan_display(struct fb_var_screeninfo *var, | |
941 | struct fb_info *info) | |
942 | { | |
943 | struct tridentfb_par *par = info->par; | |
944 | unsigned int offset; | |
945 | ||
946 | debug("enter\n"); | |
947 | offset = (var->xoffset + (var->yoffset * var->xres_virtual)) | |
948 | * var->bits_per_pixel / 32; | |
949 | set_screen_start(par, offset); | |
950 | debug("exit\n"); | |
951 | return 0; | |
952 | } | |
953 | ||
954 | static inline void shadowmode_on(struct tridentfb_par *par) | |
955 | { | |
956 | write3CE(par, CyberControl, read3CE(par, CyberControl) | 0x81); | |
957 | } | |
958 | ||
959 | static inline void shadowmode_off(struct tridentfb_par *par) | |
960 | { | |
961 | write3CE(par, CyberControl, read3CE(par, CyberControl) & 0x7E); | |
962 | } | |
963 | ||
964 | /* Set the hardware to the requested video mode */ | |
965 | static int tridentfb_set_par(struct fb_info *info) | |
966 | { | |
967 | struct tridentfb_par *par = info->par; | |
968 | u32 htotal, hdispend, hsyncstart, hsyncend, hblankstart, hblankend; | |
969 | u32 vtotal, vdispend, vsyncstart, vsyncend, vblankstart, vblankend; | |
970 | struct fb_var_screeninfo *var = &info->var; | |
971 | int bpp = var->bits_per_pixel; | |
972 | unsigned char tmp; | |
973 | unsigned long vclk; | |
974 | ||
975 | debug("enter\n"); | |
976 | hdispend = var->xres / 8 - 1; | |
977 | hsyncstart = (var->xres + var->right_margin) / 8; | |
978 | hsyncend = (var->xres + var->right_margin + var->hsync_len) / 8; | |
979 | htotal = (var->xres + var->left_margin + var->right_margin + | |
980 | var->hsync_len) / 8 - 5; | |
981 | hblankstart = hdispend + 1; | |
982 | hblankend = htotal + 3; | |
983 | ||
984 | vdispend = var->yres - 1; | |
985 | vsyncstart = var->yres + var->lower_margin; | |
986 | vsyncend = vsyncstart + var->vsync_len; | |
987 | vtotal = var->upper_margin + vsyncend - 2; | |
988 | vblankstart = vdispend + 1; | |
989 | vblankend = vtotal; | |
990 | ||
991 | if (info->var.vmode & FB_VMODE_INTERLACED) { | |
992 | vtotal /= 2; | |
993 | vdispend /= 2; | |
994 | vsyncstart /= 2; | |
995 | vsyncend /= 2; | |
996 | vblankstart /= 2; | |
997 | vblankend /= 2; | |
998 | } | |
999 | ||
1000 | enable_mmio(par); | |
1001 | crtc_unlock(par); | |
1002 | write3CE(par, CyberControl, 8); | |
1003 | tmp = 0xEB; | |
1004 | if (var->sync & FB_SYNC_HOR_HIGH_ACT) | |
1005 | tmp &= ~0x40; | |
1006 | if (var->sync & FB_SYNC_VERT_HIGH_ACT) | |
1007 | tmp &= ~0x80; | |
1008 | ||
1009 | if (par->flatpanel && var->xres < nativex) { | |
1010 | /* | |
1011 | * on flat panels with native size larger | |
1012 | * than requested resolution decide whether | |
1013 | * we stretch or center | |
1014 | */ | |
1015 | t_outb(par, tmp | 0xC0, VGA_MIS_W); | |
1016 | ||
1017 | shadowmode_on(par); | |
1018 | ||
1019 | if (center) | |
1020 | screen_center(par); | |
1021 | else if (stretch) | |
1022 | screen_stretch(par); | |
1023 | ||
1024 | } else { | |
1025 | t_outb(par, tmp, VGA_MIS_W); | |
1026 | write3CE(par, CyberControl, 8); | |
1027 | } | |
1028 | ||
1029 | /* vertical timing values */ | |
1030 | write3X4(par, VGA_CRTC_V_TOTAL, vtotal & 0xFF); | |
1031 | write3X4(par, VGA_CRTC_V_DISP_END, vdispend & 0xFF); | |
1032 | write3X4(par, VGA_CRTC_V_SYNC_START, vsyncstart & 0xFF); | |
1033 | write3X4(par, VGA_CRTC_V_SYNC_END, (vsyncend & 0x0F)); | |
1034 | write3X4(par, VGA_CRTC_V_BLANK_START, vblankstart & 0xFF); | |
1035 | write3X4(par, VGA_CRTC_V_BLANK_END, vblankend & 0xFF); | |
1036 | ||
1037 | /* horizontal timing values */ | |
1038 | write3X4(par, VGA_CRTC_H_TOTAL, htotal & 0xFF); | |
1039 | write3X4(par, VGA_CRTC_H_DISP, hdispend & 0xFF); | |
1040 | write3X4(par, VGA_CRTC_H_SYNC_START, hsyncstart & 0xFF); | |
1041 | write3X4(par, VGA_CRTC_H_SYNC_END, | |
1042 | (hsyncend & 0x1F) | ((hblankend & 0x20) << 2)); | |
1043 | write3X4(par, VGA_CRTC_H_BLANK_START, hblankstart & 0xFF); | |
1044 | write3X4(par, VGA_CRTC_H_BLANK_END, hblankend & 0x1F); | |
1045 | ||
1046 | /* higher bits of vertical timing values */ | |
1047 | tmp = 0x10; | |
1048 | if (vtotal & 0x100) tmp |= 0x01; | |
1049 | if (vdispend & 0x100) tmp |= 0x02; | |
1050 | if (vsyncstart & 0x100) tmp |= 0x04; | |
1051 | if (vblankstart & 0x100) tmp |= 0x08; | |
1052 | ||
1053 | if (vtotal & 0x200) tmp |= 0x20; | |
1054 | if (vdispend & 0x200) tmp |= 0x40; | |
1055 | if (vsyncstart & 0x200) tmp |= 0x80; | |
1056 | write3X4(par, VGA_CRTC_OVERFLOW, tmp); | |
1057 | ||
1058 | tmp = read3X4(par, CRTHiOrd) & 0x07; | |
1059 | tmp |= 0x08; /* line compare bit 10 */ | |
1060 | if (vtotal & 0x400) tmp |= 0x80; | |
1061 | if (vblankstart & 0x400) tmp |= 0x40; | |
1062 | if (vsyncstart & 0x400) tmp |= 0x20; | |
1063 | if (vdispend & 0x400) tmp |= 0x10; | |
1064 | write3X4(par, CRTHiOrd, tmp); | |
1065 | ||
1066 | tmp = (htotal >> 8) & 0x01; | |
1067 | tmp |= (hdispend >> 7) & 0x02; | |
1068 | tmp |= (hsyncstart >> 5) & 0x08; | |
1069 | tmp |= (hblankstart >> 4) & 0x10; | |
1070 | write3X4(par, HorizOverflow, tmp); | |
1071 | ||
1072 | tmp = 0x40; | |
1073 | if (vblankstart & 0x200) tmp |= 0x20; | |
1074 | //FIXME if (info->var.vmode & FB_VMODE_DOUBLE) tmp |= 0x80; /* double scan for 200 line modes */ | |
1075 | write3X4(par, VGA_CRTC_MAX_SCAN, tmp); | |
1076 | ||
1077 | write3X4(par, VGA_CRTC_LINE_COMPARE, 0xFF); | |
1078 | write3X4(par, VGA_CRTC_PRESET_ROW, 0); | |
1079 | write3X4(par, VGA_CRTC_MODE, 0xC3); | |
1080 | ||
1081 | write3X4(par, LinearAddReg, 0x20); /* enable linear addressing */ | |
1082 | ||
1083 | tmp = (info->var.vmode & FB_VMODE_INTERLACED) ? 0x84 : 0x80; | |
1084 | /* enable access extended memory */ | |
1085 | write3X4(par, CRTCModuleTest, tmp); | |
1086 | tmp = read3CE(par, MiscIntContReg) & ~0x4; | |
1087 | if (info->var.vmode & FB_VMODE_INTERLACED) | |
1088 | tmp |= 0x4; | |
1089 | write3CE(par, MiscIntContReg, tmp); | |
1090 | ||
1091 | /* enable GE for text acceleration */ | |
1092 | write3X4(par, GraphEngReg, 0x80); | |
1093 | ||
1094 | switch (bpp) { | |
1095 | case 8: | |
1096 | tmp = 0x00; | |
1097 | break; | |
1098 | case 16: | |
1099 | tmp = 0x05; | |
1100 | break; | |
1101 | case 24: | |
1102 | tmp = 0x29; | |
1103 | break; | |
1104 | case 32: | |
1105 | tmp = 0x09; | |
1106 | break; | |
1107 | } | |
1108 | ||
1109 | write3X4(par, PixelBusReg, tmp); | |
1110 | ||
1111 | tmp = read3X4(par, DRAMControl); | |
1112 | if (!is_oldprotect(par->chip_id)) | |
1113 | tmp |= 0x10; | |
1114 | if (iscyber(par->chip_id)) | |
1115 | tmp |= 0x20; | |
1116 | write3X4(par, DRAMControl, tmp); /* both IO, linear enable */ | |
1117 | ||
1118 | write3X4(par, InterfaceSel, read3X4(par, InterfaceSel) | 0x40); | |
1119 | if (!is_xp(par->chip_id)) | |
1120 | write3X4(par, Performance, read3X4(par, Performance) | 0x10); | |
1121 | /* MMIO & PCI read and write burst enable */ | |
1122 | if (par->chip_id != TGUI9440 && par->chip_id != IMAGE975) | |
1123 | write3X4(par, PCIReg, read3X4(par, PCIReg) | 0x06); | |
1124 | ||
1125 | vga_mm_wseq(par->io_virt, 0, 3); | |
1126 | vga_mm_wseq(par->io_virt, 1, 1); /* set char clock 8 dots wide */ | |
1127 | /* enable 4 maps because needed in chain4 mode */ | |
1128 | vga_mm_wseq(par->io_virt, 2, 0x0F); | |
1129 | vga_mm_wseq(par->io_virt, 3, 0); | |
1130 | vga_mm_wseq(par->io_virt, 4, 0x0E); /* memory mode enable bitmaps ?? */ | |
1131 | ||
1132 | /* convert from picoseconds to kHz */ | |
1133 | vclk = PICOS2KHZ(info->var.pixclock); | |
1134 | ||
1135 | /* divide clock by 2 if 32bpp chain4 mode display and CPU path */ | |
1136 | tmp = read3CE(par, MiscExtFunc) & 0xF0; | |
1137 | if (bpp == 32 || (par->chip_id == TGUI9440 && bpp == 16)) { | |
1138 | tmp |= 8; | |
1139 | vclk *= 2; | |
1140 | } | |
1141 | set_vclk(par, vclk); | |
1142 | write3CE(par, MiscExtFunc, tmp | 0x12); | |
1143 | write3CE(par, 0x5, 0x40); /* no CGA compat, allow 256 col */ | |
1144 | write3CE(par, 0x6, 0x05); /* graphics mode */ | |
1145 | write3CE(par, 0x7, 0x0F); /* planes? */ | |
1146 | ||
1147 | /* graphics mode and support 256 color modes */ | |
1148 | writeAttr(par, 0x10, 0x41); | |
1149 | writeAttr(par, 0x12, 0x0F); /* planes */ | |
1150 | writeAttr(par, 0x13, 0); /* horizontal pel panning */ | |
1151 | ||
1152 | /* colors */ | |
1153 | for (tmp = 0; tmp < 0x10; tmp++) | |
1154 | writeAttr(par, tmp, tmp); | |
1155 | fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */ | |
1156 | t_outb(par, 0x20, VGA_ATT_W); /* enable attr */ | |
1157 | ||
1158 | switch (bpp) { | |
1159 | case 8: | |
1160 | tmp = 0; | |
1161 | break; | |
1162 | case 16: | |
1163 | tmp = 0x30; | |
1164 | break; | |
1165 | case 24: | |
1166 | case 32: | |
1167 | tmp = 0xD0; | |
1168 | break; | |
1169 | } | |
1170 | ||
1171 | t_inb(par, VGA_PEL_IW); | |
1172 | t_inb(par, VGA_PEL_MSK); | |
1173 | t_inb(par, VGA_PEL_MSK); | |
1174 | t_inb(par, VGA_PEL_MSK); | |
1175 | t_inb(par, VGA_PEL_MSK); | |
1176 | t_outb(par, tmp, VGA_PEL_MSK); | |
1177 | t_inb(par, VGA_PEL_IW); | |
1178 | ||
1179 | if (par->flatpanel) | |
1180 | set_number_of_lines(par, info->var.yres); | |
1181 | info->fix.line_length = info->var.xres_virtual * bpp / 8; | |
1182 | set_lwidth(par, info->fix.line_length / 8); | |
1183 | ||
1184 | if (!(info->flags & FBINFO_HWACCEL_DISABLED)) | |
1185 | par->init_accel(par, info->var.xres_virtual, bpp); | |
1186 | ||
1187 | info->fix.visual = (bpp == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR; | |
1188 | info->cmap.len = (bpp == 8) ? 256 : 16; | |
1189 | debug("exit\n"); | |
1190 | return 0; | |
1191 | } | |
1192 | ||
1193 | /* Set one color register */ | |
1194 | static int tridentfb_setcolreg(unsigned regno, unsigned red, unsigned green, | |
1195 | unsigned blue, unsigned transp, | |
1196 | struct fb_info *info) | |
1197 | { | |
1198 | int bpp = info->var.bits_per_pixel; | |
1199 | struct tridentfb_par *par = info->par; | |
1200 | ||
1201 | if (regno >= info->cmap.len) | |
1202 | return 1; | |
1203 | ||
1204 | if (bpp == 8) { | |
1205 | t_outb(par, 0xFF, VGA_PEL_MSK); | |
1206 | t_outb(par, regno, VGA_PEL_IW); | |
1207 | ||
1208 | t_outb(par, red >> 10, VGA_PEL_D); | |
1209 | t_outb(par, green >> 10, VGA_PEL_D); | |
1210 | t_outb(par, blue >> 10, VGA_PEL_D); | |
1211 | ||
1212 | } else if (regno < 16) { | |
1213 | if (bpp == 16) { /* RGB 565 */ | |
1214 | u32 col; | |
1215 | ||
1216 | col = (red & 0xF800) | ((green & 0xFC00) >> 5) | | |
1217 | ((blue & 0xF800) >> 11); | |
1218 | col |= col << 16; | |
1219 | ((u32 *)(info->pseudo_palette))[regno] = col; | |
1220 | } else if (bpp == 32) /* ARGB 8888 */ | |
1221 | ((u32 *)info->pseudo_palette)[regno] = | |
1222 | ((transp & 0xFF00) << 16) | | |
1223 | ((red & 0xFF00) << 8) | | |
1224 | ((green & 0xFF00)) | | |
1225 | ((blue & 0xFF00) >> 8); | |
1226 | } | |
1227 | ||
1228 | return 0; | |
1229 | } | |
1230 | ||
1231 | /* Try blanking the screen. For flat panels it does nothing */ | |
1232 | static int tridentfb_blank(int blank_mode, struct fb_info *info) | |
1233 | { | |
1234 | unsigned char PMCont, DPMSCont; | |
1235 | struct tridentfb_par *par = info->par; | |
1236 | ||
1237 | debug("enter\n"); | |
1238 | if (par->flatpanel) | |
1239 | return 0; | |
1240 | t_outb(par, 0x04, 0x83C8); /* Read DPMS Control */ | |
1241 | PMCont = t_inb(par, 0x83C6) & 0xFC; | |
1242 | DPMSCont = read3CE(par, PowerStatus) & 0xFC; | |
1243 | switch (blank_mode) { | |
1244 | case FB_BLANK_UNBLANK: | |
1245 | /* Screen: On, HSync: On, VSync: On */ | |
1246 | case FB_BLANK_NORMAL: | |
1247 | /* Screen: Off, HSync: On, VSync: On */ | |
1248 | PMCont |= 0x03; | |
1249 | DPMSCont |= 0x00; | |
1250 | break; | |
1251 | case FB_BLANK_HSYNC_SUSPEND: | |
1252 | /* Screen: Off, HSync: Off, VSync: On */ | |
1253 | PMCont |= 0x02; | |
1254 | DPMSCont |= 0x01; | |
1255 | break; | |
1256 | case FB_BLANK_VSYNC_SUSPEND: | |
1257 | /* Screen: Off, HSync: On, VSync: Off */ | |
1258 | PMCont |= 0x02; | |
1259 | DPMSCont |= 0x02; | |
1260 | break; | |
1261 | case FB_BLANK_POWERDOWN: | |
1262 | /* Screen: Off, HSync: Off, VSync: Off */ | |
1263 | PMCont |= 0x00; | |
1264 | DPMSCont |= 0x03; | |
1265 | break; | |
1266 | } | |
1267 | ||
1268 | write3CE(par, PowerStatus, DPMSCont); | |
1269 | t_outb(par, 4, 0x83C8); | |
1270 | t_outb(par, PMCont, 0x83C6); | |
1271 | ||
1272 | debug("exit\n"); | |
1273 | ||
1274 | /* let fbcon do a softblank for us */ | |
1275 | return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0; | |
1276 | } | |
1277 | ||
1278 | static struct fb_ops tridentfb_ops = { | |
1279 | .owner = THIS_MODULE, | |
1280 | .fb_setcolreg = tridentfb_setcolreg, | |
1281 | .fb_pan_display = tridentfb_pan_display, | |
1282 | .fb_blank = tridentfb_blank, | |
1283 | .fb_check_var = tridentfb_check_var, | |
1284 | .fb_set_par = tridentfb_set_par, | |
1285 | .fb_fillrect = tridentfb_fillrect, | |
1286 | .fb_copyarea = tridentfb_copyarea, | |
1287 | .fb_imageblit = cfb_imageblit, | |
1288 | #ifdef CONFIG_FB_TRIDENT_ACCEL | |
1289 | .fb_sync = tridentfb_sync, | |
1290 | #endif | |
1291 | }; | |
1292 | ||
1293 | static int __devinit trident_pci_probe(struct pci_dev *dev, | |
1294 | const struct pci_device_id *id) | |
1295 | { | |
1296 | int err; | |
1297 | unsigned char revision; | |
1298 | struct fb_info *info; | |
1299 | struct tridentfb_par *default_par; | |
1300 | int chip3D; | |
1301 | int chip_id; | |
1302 | ||
1303 | err = pci_enable_device(dev); | |
1304 | if (err) | |
1305 | return err; | |
1306 | ||
1307 | info = framebuffer_alloc(sizeof(struct tridentfb_par), &dev->dev); | |
1308 | if (!info) | |
1309 | return -ENOMEM; | |
1310 | default_par = info->par; | |
1311 | ||
1312 | chip_id = id->device; | |
1313 | ||
1314 | if (chip_id == CYBERBLADEi1) | |
1315 | output("*** Please do use cyblafb, Cyberblade/i1 support " | |
1316 | "will soon be removed from tridentfb!\n"); | |
1317 | ||
1318 | #ifndef CONFIG_FB_TRIDENT_ACCEL | |
1319 | noaccel = 1; | |
1320 | #endif | |
1321 | ||
1322 | /* If PCI id is 0x9660 then further detect chip type */ | |
1323 | ||
1324 | if (chip_id == TGUI9660) { | |
1325 | revision = vga_io_rseq(RevisionID); | |
1326 | ||
1327 | switch (revision) { | |
1328 | case 0x21: | |
1329 | chip_id = PROVIDIA9685; | |
1330 | break; | |
1331 | case 0x22: | |
1332 | case 0x23: | |
1333 | chip_id = CYBER9397; | |
1334 | break; | |
1335 | case 0x2A: | |
1336 | chip_id = CYBER9397DVD; | |
1337 | break; | |
1338 | case 0x30: | |
1339 | case 0x33: | |
1340 | case 0x34: | |
1341 | case 0x35: | |
1342 | case 0x38: | |
1343 | case 0x3A: | |
1344 | case 0xB3: | |
1345 | chip_id = CYBER9385; | |
1346 | break; | |
1347 | case 0x40 ... 0x43: | |
1348 | chip_id = CYBER9382; | |
1349 | break; | |
1350 | case 0x4A: | |
1351 | chip_id = CYBER9388; | |
1352 | break; | |
1353 | default: | |
1354 | break; | |
1355 | } | |
1356 | } | |
1357 | ||
1358 | chip3D = is3Dchip(chip_id); | |
1359 | ||
1360 | if (is_xp(chip_id)) { | |
1361 | default_par->init_accel = xp_init_accel; | |
1362 | default_par->wait_engine = xp_wait_engine; | |
1363 | default_par->fill_rect = xp_fill_rect; | |
1364 | default_par->copy_rect = xp_copy_rect; | |
1365 | tridentfb_fix.accel = FB_ACCEL_TRIDENT_BLADEXP; | |
1366 | } else if (is_blade(chip_id)) { | |
1367 | default_par->init_accel = blade_init_accel; | |
1368 | default_par->wait_engine = blade_wait_engine; | |
1369 | default_par->fill_rect = blade_fill_rect; | |
1370 | default_par->copy_rect = blade_copy_rect; | |
1371 | tridentfb_fix.accel = FB_ACCEL_TRIDENT_BLADE3D; | |
1372 | } else if (chip3D) { /* 3DImage family left */ | |
1373 | default_par->init_accel = image_init_accel; | |
1374 | default_par->wait_engine = image_wait_engine; | |
1375 | default_par->fill_rect = image_fill_rect; | |
1376 | default_par->copy_rect = image_copy_rect; | |
1377 | tridentfb_fix.accel = FB_ACCEL_TRIDENT_3DIMAGE; | |
1378 | } else { /* TGUI 9440/96XX family */ | |
1379 | default_par->init_accel = tgui_init_accel; | |
1380 | default_par->wait_engine = xp_wait_engine; | |
1381 | default_par->fill_rect = tgui_fill_rect; | |
1382 | default_par->copy_rect = tgui_copy_rect; | |
1383 | tridentfb_fix.accel = FB_ACCEL_TRIDENT_TGUI; | |
1384 | } | |
1385 | ||
1386 | default_par->chip_id = chip_id; | |
1387 | ||
1388 | /* setup MMIO region */ | |
1389 | tridentfb_fix.mmio_start = pci_resource_start(dev, 1); | |
1390 | tridentfb_fix.mmio_len = pci_resource_len(dev, 1); | |
1391 | ||
1392 | if (!request_mem_region(tridentfb_fix.mmio_start, | |
1393 | tridentfb_fix.mmio_len, "tridentfb")) { | |
1394 | debug("request_region failed!\n"); | |
1395 | framebuffer_release(info); | |
1396 | return -1; | |
1397 | } | |
1398 | ||
1399 | default_par->io_virt = ioremap_nocache(tridentfb_fix.mmio_start, | |
1400 | tridentfb_fix.mmio_len); | |
1401 | ||
1402 | if (!default_par->io_virt) { | |
1403 | debug("ioremap failed\n"); | |
1404 | err = -1; | |
1405 | goto out_unmap1; | |
1406 | } | |
1407 | ||
1408 | enable_mmio(default_par); | |
1409 | ||
1410 | /* setup framebuffer memory */ | |
1411 | tridentfb_fix.smem_start = pci_resource_start(dev, 0); | |
1412 | tridentfb_fix.smem_len = get_memsize(default_par); | |
1413 | ||
1414 | if (!request_mem_region(tridentfb_fix.smem_start, | |
1415 | tridentfb_fix.smem_len, "tridentfb")) { | |
1416 | debug("request_mem_region failed!\n"); | |
1417 | disable_mmio(info->par); | |
1418 | err = -1; | |
1419 | goto out_unmap1; | |
1420 | } | |
1421 | ||
1422 | info->screen_base = ioremap_nocache(tridentfb_fix.smem_start, | |
1423 | tridentfb_fix.smem_len); | |
1424 | ||
1425 | if (!info->screen_base) { | |
1426 | debug("ioremap failed\n"); | |
1427 | err = -1; | |
1428 | goto out_unmap2; | |
1429 | } | |
1430 | ||
1431 | default_par->flatpanel = is_flatpanel(default_par); | |
1432 | ||
1433 | if (default_par->flatpanel) | |
1434 | nativex = get_nativex(default_par); | |
1435 | ||
1436 | info->fix = tridentfb_fix; | |
1437 | info->fbops = &tridentfb_ops; | |
1438 | info->pseudo_palette = default_par->pseudo_pal; | |
1439 | ||
1440 | info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN; | |
1441 | if (!noaccel && default_par->init_accel) { | |
1442 | info->flags &= ~FBINFO_HWACCEL_DISABLED; | |
1443 | info->flags |= FBINFO_HWACCEL_COPYAREA; | |
1444 | info->flags |= FBINFO_HWACCEL_FILLRECT; | |
1445 | } else | |
1446 | info->flags |= FBINFO_HWACCEL_DISABLED; | |
1447 | ||
1448 | if (!fb_find_mode(&info->var, info, | |
1449 | mode_option, NULL, 0, NULL, bpp)) { | |
1450 | err = -EINVAL; | |
1451 | goto out_unmap2; | |
1452 | } | |
1453 | err = fb_alloc_cmap(&info->cmap, 256, 0); | |
1454 | if (err < 0) | |
1455 | goto out_unmap2; | |
1456 | ||
1457 | info->var.activate |= FB_ACTIVATE_NOW; | |
1458 | info->device = &dev->dev; | |
1459 | if (register_framebuffer(info) < 0) { | |
1460 | printk(KERN_ERR "tridentfb: could not register framebuffer\n"); | |
1461 | fb_dealloc_cmap(&info->cmap); | |
1462 | err = -EINVAL; | |
1463 | goto out_unmap2; | |
1464 | } | |
1465 | output("fb%d: %s frame buffer device %dx%d-%dbpp\n", | |
1466 | info->node, info->fix.id, info->var.xres, | |
1467 | info->var.yres, info->var.bits_per_pixel); | |
1468 | ||
1469 | pci_set_drvdata(dev, info); | |
1470 | return 0; | |
1471 | ||
1472 | out_unmap2: | |
1473 | if (info->screen_base) | |
1474 | iounmap(info->screen_base); | |
1475 | release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len); | |
1476 | disable_mmio(info->par); | |
1477 | out_unmap1: | |
1478 | if (default_par->io_virt) | |
1479 | iounmap(default_par->io_virt); | |
1480 | release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len); | |
1481 | framebuffer_release(info); | |
1482 | return err; | |
1483 | } | |
1484 | ||
1485 | static void __devexit trident_pci_remove(struct pci_dev *dev) | |
1486 | { | |
1487 | struct fb_info *info = pci_get_drvdata(dev); | |
1488 | struct tridentfb_par *par = info->par; | |
1489 | ||
1490 | unregister_framebuffer(info); | |
1491 | iounmap(par->io_virt); | |
1492 | iounmap(info->screen_base); | |
1493 | release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len); | |
1494 | release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len); | |
1495 | pci_set_drvdata(dev, NULL); | |
1496 | framebuffer_release(info); | |
1497 | } | |
1498 | ||
1499 | /* List of boards that we are trying to support */ | |
1500 | static struct pci_device_id trident_devices[] = { | |
1501 | {PCI_VENDOR_ID_TRIDENT, BLADE3D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1502 | {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1503 | {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1504 | {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1505 | {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1506 | {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1507 | {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1508 | {PCI_VENDOR_ID_TRIDENT, CYBERBLADEE4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1509 | {PCI_VENDOR_ID_TRIDENT, TGUI9440, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1510 | {PCI_VENDOR_ID_TRIDENT, TGUI9660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1511 | {PCI_VENDOR_ID_TRIDENT, IMAGE975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1512 | {PCI_VENDOR_ID_TRIDENT, IMAGE985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1513 | {PCI_VENDOR_ID_TRIDENT, CYBER9320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1514 | {PCI_VENDOR_ID_TRIDENT, CYBER9388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1515 | {PCI_VENDOR_ID_TRIDENT, CYBER9520, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1516 | {PCI_VENDOR_ID_TRIDENT, CYBER9525DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1517 | {PCI_VENDOR_ID_TRIDENT, CYBER9397, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1518 | {PCI_VENDOR_ID_TRIDENT, CYBER9397DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1519 | {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1520 | {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1521 | {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm16, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1522 | {0,} | |
1523 | }; | |
1524 | ||
1525 | MODULE_DEVICE_TABLE(pci, trident_devices); | |
1526 | ||
1527 | static struct pci_driver tridentfb_pci_driver = { | |
1528 | .name = "tridentfb", | |
1529 | .id_table = trident_devices, | |
1530 | .probe = trident_pci_probe, | |
1531 | .remove = __devexit_p(trident_pci_remove) | |
1532 | }; | |
1533 | ||
1534 | /* | |
1535 | * Parse user specified options (`video=trident:') | |
1536 | * example: | |
1537 | * video=trident:800x600,bpp=16,noaccel | |
1538 | */ | |
1539 | #ifndef MODULE | |
1540 | static int __init tridentfb_setup(char *options) | |
1541 | { | |
1542 | char *opt; | |
1543 | if (!options || !*options) | |
1544 | return 0; | |
1545 | while ((opt = strsep(&options, ",")) != NULL) { | |
1546 | if (!*opt) | |
1547 | continue; | |
1548 | if (!strncmp(opt, "noaccel", 7)) | |
1549 | noaccel = 1; | |
1550 | else if (!strncmp(opt, "fp", 2)) | |
1551 | fp = 1; | |
1552 | else if (!strncmp(opt, "crt", 3)) | |
1553 | fp = 0; | |
1554 | else if (!strncmp(opt, "bpp=", 4)) | |
1555 | bpp = simple_strtoul(opt + 4, NULL, 0); | |
1556 | else if (!strncmp(opt, "center", 6)) | |
1557 | center = 1; | |
1558 | else if (!strncmp(opt, "stretch", 7)) | |
1559 | stretch = 1; | |
1560 | else if (!strncmp(opt, "memsize=", 8)) | |
1561 | memsize = simple_strtoul(opt + 8, NULL, 0); | |
1562 | else if (!strncmp(opt, "memdiff=", 8)) | |
1563 | memdiff = simple_strtoul(opt + 8, NULL, 0); | |
1564 | else if (!strncmp(opt, "nativex=", 8)) | |
1565 | nativex = simple_strtoul(opt + 8, NULL, 0); | |
1566 | else | |
1567 | mode_option = opt; | |
1568 | } | |
1569 | return 0; | |
1570 | } | |
1571 | #endif | |
1572 | ||
1573 | static int __init tridentfb_init(void) | |
1574 | { | |
1575 | #ifndef MODULE | |
1576 | char *option = NULL; | |
1577 | ||
1578 | if (fb_get_options("tridentfb", &option)) | |
1579 | return -ENODEV; | |
1580 | tridentfb_setup(option); | |
1581 | #endif | |
1582 | return pci_register_driver(&tridentfb_pci_driver); | |
1583 | } | |
1584 | ||
1585 | static void __exit tridentfb_exit(void) | |
1586 | { | |
1587 | pci_unregister_driver(&tridentfb_pci_driver); | |
1588 | } | |
1589 | ||
1590 | module_init(tridentfb_init); | |
1591 | module_exit(tridentfb_exit); | |
1592 | ||
1593 | MODULE_AUTHOR("Jani Monoses <jani@iv.ro>"); | |
1594 | MODULE_DESCRIPTION("Framebuffer driver for Trident cards"); | |
1595 | MODULE_LICENSE("GPL"); | |
1596 |