]>
Commit | Line | Data |
---|---|---|
1 | /* | |
2 | * Octeon Watchdog driver | |
3 | * | |
4 | * Copyright (C) 2007, 2008, 2009, 2010 Cavium Networks | |
5 | * | |
6 | * Converted to use WATCHDOG_CORE by Aaro Koskinen <aaro.koskinen@iki.fi>. | |
7 | * | |
8 | * Some parts derived from wdt.c | |
9 | * | |
10 | * (c) Copyright 1996-1997 Alan Cox <alan@lxorguk.ukuu.org.uk>, | |
11 | * All Rights Reserved. | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or | |
14 | * modify it under the terms of the GNU General Public License | |
15 | * as published by the Free Software Foundation; either version | |
16 | * 2 of the License, or (at your option) any later version. | |
17 | * | |
18 | * Neither Alan Cox nor CymruNet Ltd. admit liability nor provide | |
19 | * warranty for any of this software. This material is provided | |
20 | * "AS-IS" and at no charge. | |
21 | * | |
22 | * (c) Copyright 1995 Alan Cox <alan@lxorguk.ukuu.org.uk> | |
23 | * | |
24 | * This file is subject to the terms and conditions of the GNU General Public | |
25 | * License. See the file "COPYING" in the main directory of this archive | |
26 | * for more details. | |
27 | * | |
28 | * | |
29 | * The OCTEON watchdog has a maximum timeout of 2^32 * io_clock. | |
30 | * For most systems this is less than 10 seconds, so to allow for | |
31 | * software to request longer watchdog heartbeats, we maintain software | |
32 | * counters to count multiples of the base rate. If the system locks | |
33 | * up in such a manner that we can not run the software counters, the | |
34 | * only result is a watchdog reset sooner than was requested. But | |
35 | * that is OK, because in this case userspace would likely not be able | |
36 | * to do anything anyhow. | |
37 | * | |
38 | * The hardware watchdog interval we call the period. The OCTEON | |
39 | * watchdog goes through several stages, after the first period an | |
40 | * irq is asserted, then if it is not reset, after the next period NMI | |
41 | * is asserted, then after an additional period a chip wide soft reset. | |
42 | * So for the software counters, we reset watchdog after each period | |
43 | * and decrement the counter. But for the last two periods we need to | |
44 | * let the watchdog progress to the NMI stage so we disable the irq | |
45 | * and let it proceed. Once in the NMI, we print the register state | |
46 | * to the serial port and then wait for the reset. | |
47 | * | |
48 | * A watchdog is maintained for each CPU in the system, that way if | |
49 | * one CPU suffers a lockup, we also get a register dump and reset. | |
50 | * The userspace ping resets the watchdog on all CPUs. | |
51 | * | |
52 | * Before userspace opens the watchdog device, we still run the | |
53 | * watchdogs to catch any lockups that may be kernel related. | |
54 | * | |
55 | */ | |
56 | ||
57 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
58 | ||
59 | #include <linux/interrupt.h> | |
60 | #include <linux/watchdog.h> | |
61 | #include <linux/cpumask.h> | |
62 | #include <linux/bitops.h> | |
63 | #include <linux/kernel.h> | |
64 | #include <linux/module.h> | |
65 | #include <linux/string.h> | |
66 | #include <linux/delay.h> | |
67 | #include <linux/cpu.h> | |
68 | #include <linux/smp.h> | |
69 | #include <linux/fs.h> | |
70 | #include <linux/irq.h> | |
71 | ||
72 | #include <asm/mipsregs.h> | |
73 | #include <asm/uasm.h> | |
74 | ||
75 | #include <asm/octeon/octeon.h> | |
76 | ||
77 | /* The count needed to achieve timeout_sec. */ | |
78 | static unsigned int timeout_cnt; | |
79 | ||
80 | /* The maximum period supported. */ | |
81 | static unsigned int max_timeout_sec; | |
82 | ||
83 | /* The current period. */ | |
84 | static unsigned int timeout_sec; | |
85 | ||
86 | /* Set to non-zero when userspace countdown mode active */ | |
87 | static int do_coundown; | |
88 | static unsigned int countdown_reset; | |
89 | static unsigned int per_cpu_countdown[NR_CPUS]; | |
90 | ||
91 | static cpumask_t irq_enabled_cpus; | |
92 | ||
93 | #define WD_TIMO 60 /* Default heartbeat = 60 seconds */ | |
94 | ||
95 | static int heartbeat = WD_TIMO; | |
96 | module_param(heartbeat, int, S_IRUGO); | |
97 | MODULE_PARM_DESC(heartbeat, | |
98 | "Watchdog heartbeat in seconds. (0 < heartbeat, default=" | |
99 | __MODULE_STRING(WD_TIMO) ")"); | |
100 | ||
101 | static bool nowayout = WATCHDOG_NOWAYOUT; | |
102 | module_param(nowayout, bool, S_IRUGO); | |
103 | MODULE_PARM_DESC(nowayout, | |
104 | "Watchdog cannot be stopped once started (default=" | |
105 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | |
106 | ||
107 | static u32 nmi_stage1_insns[64] __initdata; | |
108 | /* We need one branch and therefore one relocation per target label. */ | |
109 | static struct uasm_label labels[5] __initdata; | |
110 | static struct uasm_reloc relocs[5] __initdata; | |
111 | ||
112 | enum lable_id { | |
113 | label_enter_bootloader = 1 | |
114 | }; | |
115 | ||
116 | /* Some CP0 registers */ | |
117 | #define K0 26 | |
118 | #define C0_CVMMEMCTL 11, 7 | |
119 | #define C0_STATUS 12, 0 | |
120 | #define C0_EBASE 15, 1 | |
121 | #define C0_DESAVE 31, 0 | |
122 | ||
123 | void octeon_wdt_nmi_stage2(void); | |
124 | ||
125 | static void __init octeon_wdt_build_stage1(void) | |
126 | { | |
127 | int i; | |
128 | int len; | |
129 | u32 *p = nmi_stage1_insns; | |
130 | #ifdef CONFIG_HOTPLUG_CPU | |
131 | struct uasm_label *l = labels; | |
132 | struct uasm_reloc *r = relocs; | |
133 | #endif | |
134 | ||
135 | /* | |
136 | * For the next few instructions running the debugger may | |
137 | * cause corruption of k0 in the saved registers. Since we're | |
138 | * about to crash, nobody probably cares. | |
139 | * | |
140 | * Save K0 into the debug scratch register | |
141 | */ | |
142 | uasm_i_dmtc0(&p, K0, C0_DESAVE); | |
143 | ||
144 | uasm_i_mfc0(&p, K0, C0_STATUS); | |
145 | #ifdef CONFIG_HOTPLUG_CPU | |
146 | if (octeon_bootloader_entry_addr) | |
147 | uasm_il_bbit0(&p, &r, K0, ilog2(ST0_NMI), | |
148 | label_enter_bootloader); | |
149 | #endif | |
150 | /* Force 64-bit addressing enabled */ | |
151 | uasm_i_ori(&p, K0, K0, ST0_UX | ST0_SX | ST0_KX); | |
152 | uasm_i_mtc0(&p, K0, C0_STATUS); | |
153 | ||
154 | #ifdef CONFIG_HOTPLUG_CPU | |
155 | if (octeon_bootloader_entry_addr) { | |
156 | uasm_i_mfc0(&p, K0, C0_EBASE); | |
157 | /* Coreid number in K0 */ | |
158 | uasm_i_andi(&p, K0, K0, 0xf); | |
159 | /* 8 * coreid in bits 16-31 */ | |
160 | uasm_i_dsll_safe(&p, K0, K0, 3 + 16); | |
161 | uasm_i_ori(&p, K0, K0, 0x8001); | |
162 | uasm_i_dsll_safe(&p, K0, K0, 16); | |
163 | uasm_i_ori(&p, K0, K0, 0x0700); | |
164 | uasm_i_drotr_safe(&p, K0, K0, 32); | |
165 | /* | |
166 | * Should result in: 0x8001,0700,0000,8*coreid which is | |
167 | * CVMX_CIU_WDOGX(coreid) - 0x0500 | |
168 | * | |
169 | * Now ld K0, CVMX_CIU_WDOGX(coreid) | |
170 | */ | |
171 | uasm_i_ld(&p, K0, 0x500, K0); | |
172 | /* | |
173 | * If bit one set handle the NMI as a watchdog event. | |
174 | * otherwise transfer control to bootloader. | |
175 | */ | |
176 | uasm_il_bbit0(&p, &r, K0, 1, label_enter_bootloader); | |
177 | uasm_i_nop(&p); | |
178 | } | |
179 | #endif | |
180 | ||
181 | /* Clear Dcache so cvmseg works right. */ | |
182 | uasm_i_cache(&p, 1, 0, 0); | |
183 | ||
184 | /* Use K0 to do a read/modify/write of CVMMEMCTL */ | |
185 | uasm_i_dmfc0(&p, K0, C0_CVMMEMCTL); | |
186 | /* Clear out the size of CVMSEG */ | |
187 | uasm_i_dins(&p, K0, 0, 0, 6); | |
188 | /* Set CVMSEG to its largest value */ | |
189 | uasm_i_ori(&p, K0, K0, 0x1c0 | 54); | |
190 | /* Store the CVMMEMCTL value */ | |
191 | uasm_i_dmtc0(&p, K0, C0_CVMMEMCTL); | |
192 | ||
193 | /* Load the address of the second stage handler */ | |
194 | UASM_i_LA(&p, K0, (long)octeon_wdt_nmi_stage2); | |
195 | uasm_i_jr(&p, K0); | |
196 | uasm_i_dmfc0(&p, K0, C0_DESAVE); | |
197 | ||
198 | #ifdef CONFIG_HOTPLUG_CPU | |
199 | if (octeon_bootloader_entry_addr) { | |
200 | uasm_build_label(&l, p, label_enter_bootloader); | |
201 | /* Jump to the bootloader and restore K0 */ | |
202 | UASM_i_LA(&p, K0, (long)octeon_bootloader_entry_addr); | |
203 | uasm_i_jr(&p, K0); | |
204 | uasm_i_dmfc0(&p, K0, C0_DESAVE); | |
205 | } | |
206 | #endif | |
207 | uasm_resolve_relocs(relocs, labels); | |
208 | ||
209 | len = (int)(p - nmi_stage1_insns); | |
210 | pr_debug("Synthesized NMI stage 1 handler (%d instructions)\n", len); | |
211 | ||
212 | pr_debug("\t.set push\n"); | |
213 | pr_debug("\t.set noreorder\n"); | |
214 | for (i = 0; i < len; i++) | |
215 | pr_debug("\t.word 0x%08x\n", nmi_stage1_insns[i]); | |
216 | pr_debug("\t.set pop\n"); | |
217 | ||
218 | if (len > 32) | |
219 | panic("NMI stage 1 handler exceeds 32 instructions, was %d\n", | |
220 | len); | |
221 | } | |
222 | ||
223 | static int cpu2core(int cpu) | |
224 | { | |
225 | #ifdef CONFIG_SMP | |
226 | return cpu_logical_map(cpu); | |
227 | #else | |
228 | return cvmx_get_core_num(); | |
229 | #endif | |
230 | } | |
231 | ||
232 | static int core2cpu(int coreid) | |
233 | { | |
234 | #ifdef CONFIG_SMP | |
235 | return cpu_number_map(coreid); | |
236 | #else | |
237 | return 0; | |
238 | #endif | |
239 | } | |
240 | ||
241 | /** | |
242 | * Poke the watchdog when an interrupt is received | |
243 | * | |
244 | * @cpl: | |
245 | * @dev_id: | |
246 | * | |
247 | * Returns | |
248 | */ | |
249 | static irqreturn_t octeon_wdt_poke_irq(int cpl, void *dev_id) | |
250 | { | |
251 | unsigned int core = cvmx_get_core_num(); | |
252 | int cpu = core2cpu(core); | |
253 | ||
254 | if (do_coundown) { | |
255 | if (per_cpu_countdown[cpu] > 0) { | |
256 | /* We're alive, poke the watchdog */ | |
257 | cvmx_write_csr(CVMX_CIU_PP_POKEX(core), 1); | |
258 | per_cpu_countdown[cpu]--; | |
259 | } else { | |
260 | /* Bad news, you are about to reboot. */ | |
261 | disable_irq_nosync(cpl); | |
262 | cpumask_clear_cpu(cpu, &irq_enabled_cpus); | |
263 | } | |
264 | } else { | |
265 | /* Not open, just ping away... */ | |
266 | cvmx_write_csr(CVMX_CIU_PP_POKEX(core), 1); | |
267 | } | |
268 | return IRQ_HANDLED; | |
269 | } | |
270 | ||
271 | /* From setup.c */ | |
272 | extern int prom_putchar(char c); | |
273 | ||
274 | /** | |
275 | * Write a string to the uart | |
276 | * | |
277 | * @str: String to write | |
278 | */ | |
279 | static void octeon_wdt_write_string(const char *str) | |
280 | { | |
281 | /* Just loop writing one byte at a time */ | |
282 | while (*str) | |
283 | prom_putchar(*str++); | |
284 | } | |
285 | ||
286 | /** | |
287 | * Write a hex number out of the uart | |
288 | * | |
289 | * @value: Number to display | |
290 | * @digits: Number of digits to print (1 to 16) | |
291 | */ | |
292 | static void octeon_wdt_write_hex(u64 value, int digits) | |
293 | { | |
294 | int d; | |
295 | int v; | |
296 | ||
297 | for (d = 0; d < digits; d++) { | |
298 | v = (value >> ((digits - d - 1) * 4)) & 0xf; | |
299 | if (v >= 10) | |
300 | prom_putchar('a' + v - 10); | |
301 | else | |
302 | prom_putchar('0' + v); | |
303 | } | |
304 | } | |
305 | ||
306 | static const char reg_name[][3] = { | |
307 | "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
308 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", | |
309 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
310 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
311 | }; | |
312 | ||
313 | /** | |
314 | * NMI stage 3 handler. NMIs are handled in the following manner: | |
315 | * 1) The first NMI handler enables CVMSEG and transfers from | |
316 | * the bootbus region into normal memory. It is careful to not | |
317 | * destroy any registers. | |
318 | * 2) The second stage handler uses CVMSEG to save the registers | |
319 | * and create a stack for C code. It then calls the third level | |
320 | * handler with one argument, a pointer to the register values. | |
321 | * 3) The third, and final, level handler is the following C | |
322 | * function that prints out some useful infomration. | |
323 | * | |
324 | * @reg: Pointer to register state before the NMI | |
325 | */ | |
326 | void octeon_wdt_nmi_stage3(u64 reg[32]) | |
327 | { | |
328 | u64 i; | |
329 | ||
330 | unsigned int coreid = cvmx_get_core_num(); | |
331 | /* | |
332 | * Save status and cause early to get them before any changes | |
333 | * might happen. | |
334 | */ | |
335 | u64 cp0_cause = read_c0_cause(); | |
336 | u64 cp0_status = read_c0_status(); | |
337 | u64 cp0_error_epc = read_c0_errorepc(); | |
338 | u64 cp0_epc = read_c0_epc(); | |
339 | ||
340 | /* Delay so output from all cores output is not jumbled together. */ | |
341 | __delay(100000000ull * coreid); | |
342 | ||
343 | octeon_wdt_write_string("\r\n*** NMI Watchdog interrupt on Core 0x"); | |
344 | octeon_wdt_write_hex(coreid, 1); | |
345 | octeon_wdt_write_string(" ***\r\n"); | |
346 | for (i = 0; i < 32; i++) { | |
347 | octeon_wdt_write_string("\t"); | |
348 | octeon_wdt_write_string(reg_name[i]); | |
349 | octeon_wdt_write_string("\t0x"); | |
350 | octeon_wdt_write_hex(reg[i], 16); | |
351 | if (i & 1) | |
352 | octeon_wdt_write_string("\r\n"); | |
353 | } | |
354 | octeon_wdt_write_string("\terr_epc\t0x"); | |
355 | octeon_wdt_write_hex(cp0_error_epc, 16); | |
356 | ||
357 | octeon_wdt_write_string("\tepc\t0x"); | |
358 | octeon_wdt_write_hex(cp0_epc, 16); | |
359 | octeon_wdt_write_string("\r\n"); | |
360 | ||
361 | octeon_wdt_write_string("\tstatus\t0x"); | |
362 | octeon_wdt_write_hex(cp0_status, 16); | |
363 | octeon_wdt_write_string("\tcause\t0x"); | |
364 | octeon_wdt_write_hex(cp0_cause, 16); | |
365 | octeon_wdt_write_string("\r\n"); | |
366 | ||
367 | octeon_wdt_write_string("\tsum0\t0x"); | |
368 | octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU_INTX_SUM0(coreid * 2)), 16); | |
369 | octeon_wdt_write_string("\ten0\t0x"); | |
370 | octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)), 16); | |
371 | octeon_wdt_write_string("\r\n"); | |
372 | ||
373 | octeon_wdt_write_string("*** Chip soft reset soon ***\r\n"); | |
374 | } | |
375 | ||
376 | static int octeon_wdt_cpu_pre_down(unsigned int cpu) | |
377 | { | |
378 | unsigned int core; | |
379 | unsigned int irq; | |
380 | union cvmx_ciu_wdogx ciu_wdog; | |
381 | ||
382 | core = cpu2core(cpu); | |
383 | ||
384 | irq = OCTEON_IRQ_WDOG0 + core; | |
385 | ||
386 | /* Poke the watchdog to clear out its state */ | |
387 | cvmx_write_csr(CVMX_CIU_PP_POKEX(core), 1); | |
388 | ||
389 | /* Disable the hardware. */ | |
390 | ciu_wdog.u64 = 0; | |
391 | cvmx_write_csr(CVMX_CIU_WDOGX(core), ciu_wdog.u64); | |
392 | ||
393 | free_irq(irq, octeon_wdt_poke_irq); | |
394 | return 0; | |
395 | } | |
396 | ||
397 | static int octeon_wdt_cpu_online(unsigned int cpu) | |
398 | { | |
399 | unsigned int core; | |
400 | unsigned int irq; | |
401 | union cvmx_ciu_wdogx ciu_wdog; | |
402 | ||
403 | core = cpu2core(cpu); | |
404 | ||
405 | /* Disable it before doing anything with the interrupts. */ | |
406 | ciu_wdog.u64 = 0; | |
407 | cvmx_write_csr(CVMX_CIU_WDOGX(core), ciu_wdog.u64); | |
408 | ||
409 | per_cpu_countdown[cpu] = countdown_reset; | |
410 | ||
411 | irq = OCTEON_IRQ_WDOG0 + core; | |
412 | ||
413 | if (request_irq(irq, octeon_wdt_poke_irq, | |
414 | IRQF_NO_THREAD, "octeon_wdt", octeon_wdt_poke_irq)) | |
415 | panic("octeon_wdt: Couldn't obtain irq %d", irq); | |
416 | ||
417 | cpumask_set_cpu(cpu, &irq_enabled_cpus); | |
418 | ||
419 | /* Poke the watchdog to clear out its state */ | |
420 | cvmx_write_csr(CVMX_CIU_PP_POKEX(core), 1); | |
421 | ||
422 | /* Finally enable the watchdog now that all handlers are installed */ | |
423 | ciu_wdog.u64 = 0; | |
424 | ciu_wdog.s.len = timeout_cnt; | |
425 | ciu_wdog.s.mode = 3; /* 3 = Interrupt + NMI + Soft-Reset */ | |
426 | cvmx_write_csr(CVMX_CIU_WDOGX(core), ciu_wdog.u64); | |
427 | ||
428 | return 0; | |
429 | } | |
430 | ||
431 | static int octeon_wdt_ping(struct watchdog_device __always_unused *wdog) | |
432 | { | |
433 | int cpu; | |
434 | int coreid; | |
435 | ||
436 | for_each_online_cpu(cpu) { | |
437 | coreid = cpu2core(cpu); | |
438 | cvmx_write_csr(CVMX_CIU_PP_POKEX(coreid), 1); | |
439 | per_cpu_countdown[cpu] = countdown_reset; | |
440 | if ((countdown_reset || !do_coundown) && | |
441 | !cpumask_test_cpu(cpu, &irq_enabled_cpus)) { | |
442 | /* We have to enable the irq */ | |
443 | int irq = OCTEON_IRQ_WDOG0 + coreid; | |
444 | ||
445 | enable_irq(irq); | |
446 | cpumask_set_cpu(cpu, &irq_enabled_cpus); | |
447 | } | |
448 | } | |
449 | return 0; | |
450 | } | |
451 | ||
452 | static void octeon_wdt_calc_parameters(int t) | |
453 | { | |
454 | unsigned int periods; | |
455 | ||
456 | timeout_sec = max_timeout_sec; | |
457 | ||
458 | ||
459 | /* | |
460 | * Find the largest interrupt period, that can evenly divide | |
461 | * the requested heartbeat time. | |
462 | */ | |
463 | while ((t % timeout_sec) != 0) | |
464 | timeout_sec--; | |
465 | ||
466 | periods = t / timeout_sec; | |
467 | ||
468 | /* | |
469 | * The last two periods are after the irq is disabled, and | |
470 | * then to the nmi, so we subtract them off. | |
471 | */ | |
472 | ||
473 | countdown_reset = periods > 2 ? periods - 2 : 0; | |
474 | heartbeat = t; | |
475 | timeout_cnt = ((octeon_get_io_clock_rate() >> 8) * timeout_sec) >> 8; | |
476 | } | |
477 | ||
478 | static int octeon_wdt_set_timeout(struct watchdog_device *wdog, | |
479 | unsigned int t) | |
480 | { | |
481 | int cpu; | |
482 | int coreid; | |
483 | union cvmx_ciu_wdogx ciu_wdog; | |
484 | ||
485 | if (t <= 0) | |
486 | return -1; | |
487 | ||
488 | octeon_wdt_calc_parameters(t); | |
489 | ||
490 | for_each_online_cpu(cpu) { | |
491 | coreid = cpu2core(cpu); | |
492 | cvmx_write_csr(CVMX_CIU_PP_POKEX(coreid), 1); | |
493 | ciu_wdog.u64 = 0; | |
494 | ciu_wdog.s.len = timeout_cnt; | |
495 | ciu_wdog.s.mode = 3; /* 3 = Interrupt + NMI + Soft-Reset */ | |
496 | cvmx_write_csr(CVMX_CIU_WDOGX(coreid), ciu_wdog.u64); | |
497 | cvmx_write_csr(CVMX_CIU_PP_POKEX(coreid), 1); | |
498 | } | |
499 | octeon_wdt_ping(wdog); /* Get the irqs back on. */ | |
500 | return 0; | |
501 | } | |
502 | ||
503 | static int octeon_wdt_start(struct watchdog_device *wdog) | |
504 | { | |
505 | octeon_wdt_ping(wdog); | |
506 | do_coundown = 1; | |
507 | return 0; | |
508 | } | |
509 | ||
510 | static int octeon_wdt_stop(struct watchdog_device *wdog) | |
511 | { | |
512 | do_coundown = 0; | |
513 | octeon_wdt_ping(wdog); | |
514 | return 0; | |
515 | } | |
516 | ||
517 | static const struct watchdog_info octeon_wdt_info = { | |
518 | .options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING, | |
519 | .identity = "OCTEON", | |
520 | }; | |
521 | ||
522 | static const struct watchdog_ops octeon_wdt_ops = { | |
523 | .owner = THIS_MODULE, | |
524 | .start = octeon_wdt_start, | |
525 | .stop = octeon_wdt_stop, | |
526 | .ping = octeon_wdt_ping, | |
527 | .set_timeout = octeon_wdt_set_timeout, | |
528 | }; | |
529 | ||
530 | static struct watchdog_device octeon_wdt = { | |
531 | .info = &octeon_wdt_info, | |
532 | .ops = &octeon_wdt_ops, | |
533 | }; | |
534 | ||
535 | static enum cpuhp_state octeon_wdt_online; | |
536 | /** | |
537 | * Module/ driver initialization. | |
538 | * | |
539 | * Returns Zero on success | |
540 | */ | |
541 | static int __init octeon_wdt_init(void) | |
542 | { | |
543 | int i; | |
544 | int ret; | |
545 | u64 *ptr; | |
546 | ||
547 | /* | |
548 | * Watchdog time expiration length = The 16 bits of LEN | |
549 | * represent the most significant bits of a 24 bit decrementer | |
550 | * that decrements every 256 cycles. | |
551 | * | |
552 | * Try for a timeout of 5 sec, if that fails a smaller number | |
553 | * of even seconds, | |
554 | */ | |
555 | max_timeout_sec = 6; | |
556 | do { | |
557 | max_timeout_sec--; | |
558 | timeout_cnt = ((octeon_get_io_clock_rate() >> 8) * | |
559 | max_timeout_sec) >> 8; | |
560 | } while (timeout_cnt > 65535); | |
561 | ||
562 | BUG_ON(timeout_cnt == 0); | |
563 | ||
564 | octeon_wdt_calc_parameters(heartbeat); | |
565 | ||
566 | pr_info("Initial granularity %d Sec\n", timeout_sec); | |
567 | ||
568 | octeon_wdt.timeout = timeout_sec; | |
569 | octeon_wdt.max_timeout = UINT_MAX; | |
570 | ||
571 | watchdog_set_nowayout(&octeon_wdt, nowayout); | |
572 | ||
573 | ret = watchdog_register_device(&octeon_wdt); | |
574 | if (ret) { | |
575 | pr_err("watchdog_register_device() failed: %d\n", ret); | |
576 | return ret; | |
577 | } | |
578 | ||
579 | /* Build the NMI handler ... */ | |
580 | octeon_wdt_build_stage1(); | |
581 | ||
582 | /* ... and install it. */ | |
583 | ptr = (u64 *) nmi_stage1_insns; | |
584 | for (i = 0; i < 16; i++) { | |
585 | cvmx_write_csr(CVMX_MIO_BOOT_LOC_ADR, i * 8); | |
586 | cvmx_write_csr(CVMX_MIO_BOOT_LOC_DAT, ptr[i]); | |
587 | } | |
588 | cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0x81fc0000); | |
589 | ||
590 | cpumask_clear(&irq_enabled_cpus); | |
591 | ||
592 | ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "watchdog/octeon:online", | |
593 | octeon_wdt_cpu_online, octeon_wdt_cpu_pre_down); | |
594 | if (ret < 0) | |
595 | goto err; | |
596 | octeon_wdt_online = ret; | |
597 | return 0; | |
598 | err: | |
599 | cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0); | |
600 | watchdog_unregister_device(&octeon_wdt); | |
601 | return ret; | |
602 | } | |
603 | ||
604 | /** | |
605 | * Module / driver shutdown | |
606 | */ | |
607 | static void __exit octeon_wdt_cleanup(void) | |
608 | { | |
609 | watchdog_unregister_device(&octeon_wdt); | |
610 | cpuhp_remove_state(octeon_wdt_online); | |
611 | ||
612 | /* | |
613 | * Disable the boot-bus memory, the code it points to is soon | |
614 | * to go missing. | |
615 | */ | |
616 | cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0); | |
617 | } | |
618 | ||
619 | MODULE_LICENSE("GPL"); | |
620 | MODULE_AUTHOR("Cavium Networks <support@caviumnetworks.com>"); | |
621 | MODULE_DESCRIPTION("Cavium Networks Octeon Watchdog driver."); | |
622 | module_init(octeon_wdt_init); | |
623 | module_exit(octeon_wdt_cleanup); |