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1 | /* | |
2 | * Virtual page mapping | |
3 | * | |
4 | * Copyright (c) 2003 Fabrice Bellard | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | #include "qemu/osdep.h" | |
20 | #include "qapi/error.h" | |
21 | ||
22 | #include "qemu/cutils.h" | |
23 | #include "cpu.h" | |
24 | #include "exec/exec-all.h" | |
25 | #include "exec/target_page.h" | |
26 | #include "tcg.h" | |
27 | #include "hw/qdev-core.h" | |
28 | #include "hw/qdev-properties.h" | |
29 | #if !defined(CONFIG_USER_ONLY) | |
30 | #include "hw/boards.h" | |
31 | #include "hw/xen/xen.h" | |
32 | #endif | |
33 | #include "sysemu/kvm.h" | |
34 | #include "sysemu/sysemu.h" | |
35 | #include "qemu/timer.h" | |
36 | #include "qemu/config-file.h" | |
37 | #include "qemu/error-report.h" | |
38 | #if defined(CONFIG_USER_ONLY) | |
39 | #include "qemu.h" | |
40 | #else /* !CONFIG_USER_ONLY */ | |
41 | #include "hw/hw.h" | |
42 | #include "exec/memory.h" | |
43 | #include "exec/ioport.h" | |
44 | #include "sysemu/dma.h" | |
45 | #include "sysemu/numa.h" | |
46 | #include "sysemu/hw_accel.h" | |
47 | #include "exec/address-spaces.h" | |
48 | #include "sysemu/xen-mapcache.h" | |
49 | #include "trace-root.h" | |
50 | ||
51 | #ifdef CONFIG_FALLOCATE_PUNCH_HOLE | |
52 | #include <linux/falloc.h> | |
53 | #endif | |
54 | ||
55 | #endif | |
56 | #include "qemu/rcu_queue.h" | |
57 | #include "qemu/main-loop.h" | |
58 | #include "translate-all.h" | |
59 | #include "sysemu/replay.h" | |
60 | ||
61 | #include "exec/memory-internal.h" | |
62 | #include "exec/ram_addr.h" | |
63 | #include "exec/log.h" | |
64 | ||
65 | #include "migration/vmstate.h" | |
66 | ||
67 | #include "qemu/range.h" | |
68 | #ifndef _WIN32 | |
69 | #include "qemu/mmap-alloc.h" | |
70 | #endif | |
71 | ||
72 | #include "monitor/monitor.h" | |
73 | ||
74 | //#define DEBUG_SUBPAGE | |
75 | ||
76 | #if !defined(CONFIG_USER_ONLY) | |
77 | /* ram_list is read under rcu_read_lock()/rcu_read_unlock(). Writes | |
78 | * are protected by the ramlist lock. | |
79 | */ | |
80 | RAMList ram_list = { .blocks = QLIST_HEAD_INITIALIZER(ram_list.blocks) }; | |
81 | ||
82 | static MemoryRegion *system_memory; | |
83 | static MemoryRegion *system_io; | |
84 | ||
85 | AddressSpace address_space_io; | |
86 | AddressSpace address_space_memory; | |
87 | ||
88 | MemoryRegion io_mem_rom, io_mem_notdirty; | |
89 | static MemoryRegion io_mem_unassigned; | |
90 | #endif | |
91 | ||
92 | #ifdef TARGET_PAGE_BITS_VARY | |
93 | int target_page_bits; | |
94 | bool target_page_bits_decided; | |
95 | #endif | |
96 | ||
97 | struct CPUTailQ cpus = QTAILQ_HEAD_INITIALIZER(cpus); | |
98 | /* current CPU in the current thread. It is only valid inside | |
99 | cpu_exec() */ | |
100 | __thread CPUState *current_cpu; | |
101 | /* 0 = Do not count executed instructions. | |
102 | 1 = Precise instruction counting. | |
103 | 2 = Adaptive rate instruction counting. */ | |
104 | int use_icount; | |
105 | ||
106 | uintptr_t qemu_host_page_size; | |
107 | intptr_t qemu_host_page_mask; | |
108 | ||
109 | bool set_preferred_target_page_bits(int bits) | |
110 | { | |
111 | /* The target page size is the lowest common denominator for all | |
112 | * the CPUs in the system, so we can only make it smaller, never | |
113 | * larger. And we can't make it smaller once we've committed to | |
114 | * a particular size. | |
115 | */ | |
116 | #ifdef TARGET_PAGE_BITS_VARY | |
117 | assert(bits >= TARGET_PAGE_BITS_MIN); | |
118 | if (target_page_bits == 0 || target_page_bits > bits) { | |
119 | if (target_page_bits_decided) { | |
120 | return false; | |
121 | } | |
122 | target_page_bits = bits; | |
123 | } | |
124 | #endif | |
125 | return true; | |
126 | } | |
127 | ||
128 | #if !defined(CONFIG_USER_ONLY) | |
129 | ||
130 | static void finalize_target_page_bits(void) | |
131 | { | |
132 | #ifdef TARGET_PAGE_BITS_VARY | |
133 | if (target_page_bits == 0) { | |
134 | target_page_bits = TARGET_PAGE_BITS_MIN; | |
135 | } | |
136 | target_page_bits_decided = true; | |
137 | #endif | |
138 | } | |
139 | ||
140 | typedef struct PhysPageEntry PhysPageEntry; | |
141 | ||
142 | struct PhysPageEntry { | |
143 | /* How many bits skip to next level (in units of L2_SIZE). 0 for a leaf. */ | |
144 | uint32_t skip : 6; | |
145 | /* index into phys_sections (!skip) or phys_map_nodes (skip) */ | |
146 | uint32_t ptr : 26; | |
147 | }; | |
148 | ||
149 | #define PHYS_MAP_NODE_NIL (((uint32_t)~0) >> 6) | |
150 | ||
151 | /* Size of the L2 (and L3, etc) page tables. */ | |
152 | #define ADDR_SPACE_BITS 64 | |
153 | ||
154 | #define P_L2_BITS 9 | |
155 | #define P_L2_SIZE (1 << P_L2_BITS) | |
156 | ||
157 | #define P_L2_LEVELS (((ADDR_SPACE_BITS - TARGET_PAGE_BITS - 1) / P_L2_BITS) + 1) | |
158 | ||
159 | typedef PhysPageEntry Node[P_L2_SIZE]; | |
160 | ||
161 | typedef struct PhysPageMap { | |
162 | struct rcu_head rcu; | |
163 | ||
164 | unsigned sections_nb; | |
165 | unsigned sections_nb_alloc; | |
166 | unsigned nodes_nb; | |
167 | unsigned nodes_nb_alloc; | |
168 | Node *nodes; | |
169 | MemoryRegionSection *sections; | |
170 | } PhysPageMap; | |
171 | ||
172 | struct AddressSpaceDispatch { | |
173 | MemoryRegionSection *mru_section; | |
174 | /* This is a multi-level map on the physical address space. | |
175 | * The bottom level has pointers to MemoryRegionSections. | |
176 | */ | |
177 | PhysPageEntry phys_map; | |
178 | PhysPageMap map; | |
179 | }; | |
180 | ||
181 | #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK) | |
182 | typedef struct subpage_t { | |
183 | MemoryRegion iomem; | |
184 | FlatView *fv; | |
185 | hwaddr base; | |
186 | uint16_t sub_section[]; | |
187 | } subpage_t; | |
188 | ||
189 | #define PHYS_SECTION_UNASSIGNED 0 | |
190 | #define PHYS_SECTION_NOTDIRTY 1 | |
191 | #define PHYS_SECTION_ROM 2 | |
192 | #define PHYS_SECTION_WATCH 3 | |
193 | ||
194 | static void io_mem_init(void); | |
195 | static void memory_map_init(void); | |
196 | static void tcg_commit(MemoryListener *listener); | |
197 | ||
198 | static MemoryRegion io_mem_watch; | |
199 | ||
200 | /** | |
201 | * CPUAddressSpace: all the information a CPU needs about an AddressSpace | |
202 | * @cpu: the CPU whose AddressSpace this is | |
203 | * @as: the AddressSpace itself | |
204 | * @memory_dispatch: its dispatch pointer (cached, RCU protected) | |
205 | * @tcg_as_listener: listener for tracking changes to the AddressSpace | |
206 | */ | |
207 | struct CPUAddressSpace { | |
208 | CPUState *cpu; | |
209 | AddressSpace *as; | |
210 | struct AddressSpaceDispatch *memory_dispatch; | |
211 | MemoryListener tcg_as_listener; | |
212 | }; | |
213 | ||
214 | struct DirtyBitmapSnapshot { | |
215 | ram_addr_t start; | |
216 | ram_addr_t end; | |
217 | unsigned long dirty[]; | |
218 | }; | |
219 | ||
220 | #endif | |
221 | ||
222 | #if !defined(CONFIG_USER_ONLY) | |
223 | ||
224 | static void phys_map_node_reserve(PhysPageMap *map, unsigned nodes) | |
225 | { | |
226 | static unsigned alloc_hint = 16; | |
227 | if (map->nodes_nb + nodes > map->nodes_nb_alloc) { | |
228 | map->nodes_nb_alloc = MAX(map->nodes_nb_alloc, alloc_hint); | |
229 | map->nodes_nb_alloc = MAX(map->nodes_nb_alloc, map->nodes_nb + nodes); | |
230 | map->nodes = g_renew(Node, map->nodes, map->nodes_nb_alloc); | |
231 | alloc_hint = map->nodes_nb_alloc; | |
232 | } | |
233 | } | |
234 | ||
235 | static uint32_t phys_map_node_alloc(PhysPageMap *map, bool leaf) | |
236 | { | |
237 | unsigned i; | |
238 | uint32_t ret; | |
239 | PhysPageEntry e; | |
240 | PhysPageEntry *p; | |
241 | ||
242 | ret = map->nodes_nb++; | |
243 | p = map->nodes[ret]; | |
244 | assert(ret != PHYS_MAP_NODE_NIL); | |
245 | assert(ret != map->nodes_nb_alloc); | |
246 | ||
247 | e.skip = leaf ? 0 : 1; | |
248 | e.ptr = leaf ? PHYS_SECTION_UNASSIGNED : PHYS_MAP_NODE_NIL; | |
249 | for (i = 0; i < P_L2_SIZE; ++i) { | |
250 | memcpy(&p[i], &e, sizeof(e)); | |
251 | } | |
252 | return ret; | |
253 | } | |
254 | ||
255 | static void phys_page_set_level(PhysPageMap *map, PhysPageEntry *lp, | |
256 | hwaddr *index, hwaddr *nb, uint16_t leaf, | |
257 | int level) | |
258 | { | |
259 | PhysPageEntry *p; | |
260 | hwaddr step = (hwaddr)1 << (level * P_L2_BITS); | |
261 | ||
262 | if (lp->skip && lp->ptr == PHYS_MAP_NODE_NIL) { | |
263 | lp->ptr = phys_map_node_alloc(map, level == 0); | |
264 | } | |
265 | p = map->nodes[lp->ptr]; | |
266 | lp = &p[(*index >> (level * P_L2_BITS)) & (P_L2_SIZE - 1)]; | |
267 | ||
268 | while (*nb && lp < &p[P_L2_SIZE]) { | |
269 | if ((*index & (step - 1)) == 0 && *nb >= step) { | |
270 | lp->skip = 0; | |
271 | lp->ptr = leaf; | |
272 | *index += step; | |
273 | *nb -= step; | |
274 | } else { | |
275 | phys_page_set_level(map, lp, index, nb, leaf, level - 1); | |
276 | } | |
277 | ++lp; | |
278 | } | |
279 | } | |
280 | ||
281 | static void phys_page_set(AddressSpaceDispatch *d, | |
282 | hwaddr index, hwaddr nb, | |
283 | uint16_t leaf) | |
284 | { | |
285 | /* Wildly overreserve - it doesn't matter much. */ | |
286 | phys_map_node_reserve(&d->map, 3 * P_L2_LEVELS); | |
287 | ||
288 | phys_page_set_level(&d->map, &d->phys_map, &index, &nb, leaf, P_L2_LEVELS - 1); | |
289 | } | |
290 | ||
291 | /* Compact a non leaf page entry. Simply detect that the entry has a single child, | |
292 | * and update our entry so we can skip it and go directly to the destination. | |
293 | */ | |
294 | static void phys_page_compact(PhysPageEntry *lp, Node *nodes) | |
295 | { | |
296 | unsigned valid_ptr = P_L2_SIZE; | |
297 | int valid = 0; | |
298 | PhysPageEntry *p; | |
299 | int i; | |
300 | ||
301 | if (lp->ptr == PHYS_MAP_NODE_NIL) { | |
302 | return; | |
303 | } | |
304 | ||
305 | p = nodes[lp->ptr]; | |
306 | for (i = 0; i < P_L2_SIZE; i++) { | |
307 | if (p[i].ptr == PHYS_MAP_NODE_NIL) { | |
308 | continue; | |
309 | } | |
310 | ||
311 | valid_ptr = i; | |
312 | valid++; | |
313 | if (p[i].skip) { | |
314 | phys_page_compact(&p[i], nodes); | |
315 | } | |
316 | } | |
317 | ||
318 | /* We can only compress if there's only one child. */ | |
319 | if (valid != 1) { | |
320 | return; | |
321 | } | |
322 | ||
323 | assert(valid_ptr < P_L2_SIZE); | |
324 | ||
325 | /* Don't compress if it won't fit in the # of bits we have. */ | |
326 | if (lp->skip + p[valid_ptr].skip >= (1 << 3)) { | |
327 | return; | |
328 | } | |
329 | ||
330 | lp->ptr = p[valid_ptr].ptr; | |
331 | if (!p[valid_ptr].skip) { | |
332 | /* If our only child is a leaf, make this a leaf. */ | |
333 | /* By design, we should have made this node a leaf to begin with so we | |
334 | * should never reach here. | |
335 | * But since it's so simple to handle this, let's do it just in case we | |
336 | * change this rule. | |
337 | */ | |
338 | lp->skip = 0; | |
339 | } else { | |
340 | lp->skip += p[valid_ptr].skip; | |
341 | } | |
342 | } | |
343 | ||
344 | void address_space_dispatch_compact(AddressSpaceDispatch *d) | |
345 | { | |
346 | if (d->phys_map.skip) { | |
347 | phys_page_compact(&d->phys_map, d->map.nodes); | |
348 | } | |
349 | } | |
350 | ||
351 | static inline bool section_covers_addr(const MemoryRegionSection *section, | |
352 | hwaddr addr) | |
353 | { | |
354 | /* Memory topology clips a memory region to [0, 2^64); size.hi > 0 means | |
355 | * the section must cover the entire address space. | |
356 | */ | |
357 | return int128_gethi(section->size) || | |
358 | range_covers_byte(section->offset_within_address_space, | |
359 | int128_getlo(section->size), addr); | |
360 | } | |
361 | ||
362 | static MemoryRegionSection *phys_page_find(AddressSpaceDispatch *d, hwaddr addr) | |
363 | { | |
364 | PhysPageEntry lp = d->phys_map, *p; | |
365 | Node *nodes = d->map.nodes; | |
366 | MemoryRegionSection *sections = d->map.sections; | |
367 | hwaddr index = addr >> TARGET_PAGE_BITS; | |
368 | int i; | |
369 | ||
370 | for (i = P_L2_LEVELS; lp.skip && (i -= lp.skip) >= 0;) { | |
371 | if (lp.ptr == PHYS_MAP_NODE_NIL) { | |
372 | return §ions[PHYS_SECTION_UNASSIGNED]; | |
373 | } | |
374 | p = nodes[lp.ptr]; | |
375 | lp = p[(index >> (i * P_L2_BITS)) & (P_L2_SIZE - 1)]; | |
376 | } | |
377 | ||
378 | if (section_covers_addr(§ions[lp.ptr], addr)) { | |
379 | return §ions[lp.ptr]; | |
380 | } else { | |
381 | return §ions[PHYS_SECTION_UNASSIGNED]; | |
382 | } | |
383 | } | |
384 | ||
385 | /* Called from RCU critical section */ | |
386 | static MemoryRegionSection *address_space_lookup_region(AddressSpaceDispatch *d, | |
387 | hwaddr addr, | |
388 | bool resolve_subpage) | |
389 | { | |
390 | MemoryRegionSection *section = atomic_read(&d->mru_section); | |
391 | subpage_t *subpage; | |
392 | ||
393 | if (!section || section == &d->map.sections[PHYS_SECTION_UNASSIGNED] || | |
394 | !section_covers_addr(section, addr)) { | |
395 | section = phys_page_find(d, addr); | |
396 | atomic_set(&d->mru_section, section); | |
397 | } | |
398 | if (resolve_subpage && section->mr->subpage) { | |
399 | subpage = container_of(section->mr, subpage_t, iomem); | |
400 | section = &d->map.sections[subpage->sub_section[SUBPAGE_IDX(addr)]]; | |
401 | } | |
402 | return section; | |
403 | } | |
404 | ||
405 | /* Called from RCU critical section */ | |
406 | static MemoryRegionSection * | |
407 | address_space_translate_internal(AddressSpaceDispatch *d, hwaddr addr, hwaddr *xlat, | |
408 | hwaddr *plen, bool resolve_subpage) | |
409 | { | |
410 | MemoryRegionSection *section; | |
411 | MemoryRegion *mr; | |
412 | Int128 diff; | |
413 | ||
414 | section = address_space_lookup_region(d, addr, resolve_subpage); | |
415 | /* Compute offset within MemoryRegionSection */ | |
416 | addr -= section->offset_within_address_space; | |
417 | ||
418 | /* Compute offset within MemoryRegion */ | |
419 | *xlat = addr + section->offset_within_region; | |
420 | ||
421 | mr = section->mr; | |
422 | ||
423 | /* MMIO registers can be expected to perform full-width accesses based only | |
424 | * on their address, without considering adjacent registers that could | |
425 | * decode to completely different MemoryRegions. When such registers | |
426 | * exist (e.g. I/O ports 0xcf8 and 0xcf9 on most PC chipsets), MMIO | |
427 | * regions overlap wildly. For this reason we cannot clamp the accesses | |
428 | * here. | |
429 | * | |
430 | * If the length is small (as is the case for address_space_ldl/stl), | |
431 | * everything works fine. If the incoming length is large, however, | |
432 | * the caller really has to do the clamping through memory_access_size. | |
433 | */ | |
434 | if (memory_region_is_ram(mr)) { | |
435 | diff = int128_sub(section->size, int128_make64(addr)); | |
436 | *plen = int128_get64(int128_min(diff, int128_make64(*plen))); | |
437 | } | |
438 | return section; | |
439 | } | |
440 | ||
441 | /** | |
442 | * address_space_translate_iommu - translate an address through an IOMMU | |
443 | * memory region and then through the target address space. | |
444 | * | |
445 | * @iommu_mr: the IOMMU memory region that we start the translation from | |
446 | * @addr: the address to be translated through the MMU | |
447 | * @xlat: the translated address offset within the destination memory region. | |
448 | * It cannot be %NULL. | |
449 | * @plen_out: valid read/write length of the translated address. It | |
450 | * cannot be %NULL. | |
451 | * @page_mask_out: page mask for the translated address. This | |
452 | * should only be meaningful for IOMMU translated | |
453 | * addresses, since there may be huge pages that this bit | |
454 | * would tell. It can be %NULL if we don't care about it. | |
455 | * @is_write: whether the translation operation is for write | |
456 | * @is_mmio: whether this can be MMIO, set true if it can | |
457 | * @target_as: the address space targeted by the IOMMU | |
458 | * @attrs: transaction attributes | |
459 | * | |
460 | * This function is called from RCU critical section. It is the common | |
461 | * part of flatview_do_translate and address_space_translate_cached. | |
462 | */ | |
463 | static MemoryRegionSection address_space_translate_iommu(IOMMUMemoryRegion *iommu_mr, | |
464 | hwaddr *xlat, | |
465 | hwaddr *plen_out, | |
466 | hwaddr *page_mask_out, | |
467 | bool is_write, | |
468 | bool is_mmio, | |
469 | AddressSpace **target_as, | |
470 | MemTxAttrs attrs) | |
471 | { | |
472 | MemoryRegionSection *section; | |
473 | hwaddr page_mask = (hwaddr)-1; | |
474 | ||
475 | do { | |
476 | hwaddr addr = *xlat; | |
477 | IOMMUMemoryRegionClass *imrc = memory_region_get_iommu_class_nocheck(iommu_mr); | |
478 | int iommu_idx = 0; | |
479 | IOMMUTLBEntry iotlb; | |
480 | ||
481 | if (imrc->attrs_to_index) { | |
482 | iommu_idx = imrc->attrs_to_index(iommu_mr, attrs); | |
483 | } | |
484 | ||
485 | iotlb = imrc->translate(iommu_mr, addr, is_write ? | |
486 | IOMMU_WO : IOMMU_RO, iommu_idx); | |
487 | ||
488 | if (!(iotlb.perm & (1 << is_write))) { | |
489 | goto unassigned; | |
490 | } | |
491 | ||
492 | addr = ((iotlb.translated_addr & ~iotlb.addr_mask) | |
493 | | (addr & iotlb.addr_mask)); | |
494 | page_mask &= iotlb.addr_mask; | |
495 | *plen_out = MIN(*plen_out, (addr | iotlb.addr_mask) - addr + 1); | |
496 | *target_as = iotlb.target_as; | |
497 | ||
498 | section = address_space_translate_internal( | |
499 | address_space_to_dispatch(iotlb.target_as), addr, xlat, | |
500 | plen_out, is_mmio); | |
501 | ||
502 | iommu_mr = memory_region_get_iommu(section->mr); | |
503 | } while (unlikely(iommu_mr)); | |
504 | ||
505 | if (page_mask_out) { | |
506 | *page_mask_out = page_mask; | |
507 | } | |
508 | return *section; | |
509 | ||
510 | unassigned: | |
511 | return (MemoryRegionSection) { .mr = &io_mem_unassigned }; | |
512 | } | |
513 | ||
514 | /** | |
515 | * flatview_do_translate - translate an address in FlatView | |
516 | * | |
517 | * @fv: the flat view that we want to translate on | |
518 | * @addr: the address to be translated in above address space | |
519 | * @xlat: the translated address offset within memory region. It | |
520 | * cannot be @NULL. | |
521 | * @plen_out: valid read/write length of the translated address. It | |
522 | * can be @NULL when we don't care about it. | |
523 | * @page_mask_out: page mask for the translated address. This | |
524 | * should only be meaningful for IOMMU translated | |
525 | * addresses, since there may be huge pages that this bit | |
526 | * would tell. It can be @NULL if we don't care about it. | |
527 | * @is_write: whether the translation operation is for write | |
528 | * @is_mmio: whether this can be MMIO, set true if it can | |
529 | * @target_as: the address space targeted by the IOMMU | |
530 | * @attrs: memory transaction attributes | |
531 | * | |
532 | * This function is called from RCU critical section | |
533 | */ | |
534 | static MemoryRegionSection flatview_do_translate(FlatView *fv, | |
535 | hwaddr addr, | |
536 | hwaddr *xlat, | |
537 | hwaddr *plen_out, | |
538 | hwaddr *page_mask_out, | |
539 | bool is_write, | |
540 | bool is_mmio, | |
541 | AddressSpace **target_as, | |
542 | MemTxAttrs attrs) | |
543 | { | |
544 | MemoryRegionSection *section; | |
545 | IOMMUMemoryRegion *iommu_mr; | |
546 | hwaddr plen = (hwaddr)(-1); | |
547 | ||
548 | if (!plen_out) { | |
549 | plen_out = &plen; | |
550 | } | |
551 | ||
552 | section = address_space_translate_internal( | |
553 | flatview_to_dispatch(fv), addr, xlat, | |
554 | plen_out, is_mmio); | |
555 | ||
556 | iommu_mr = memory_region_get_iommu(section->mr); | |
557 | if (unlikely(iommu_mr)) { | |
558 | return address_space_translate_iommu(iommu_mr, xlat, | |
559 | plen_out, page_mask_out, | |
560 | is_write, is_mmio, | |
561 | target_as, attrs); | |
562 | } | |
563 | if (page_mask_out) { | |
564 | /* Not behind an IOMMU, use default page size. */ | |
565 | *page_mask_out = ~TARGET_PAGE_MASK; | |
566 | } | |
567 | ||
568 | return *section; | |
569 | } | |
570 | ||
571 | /* Called from RCU critical section */ | |
572 | IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr, | |
573 | bool is_write, MemTxAttrs attrs) | |
574 | { | |
575 | MemoryRegionSection section; | |
576 | hwaddr xlat, page_mask; | |
577 | ||
578 | /* | |
579 | * This can never be MMIO, and we don't really care about plen, | |
580 | * but page mask. | |
581 | */ | |
582 | section = flatview_do_translate(address_space_to_flatview(as), addr, &xlat, | |
583 | NULL, &page_mask, is_write, false, &as, | |
584 | attrs); | |
585 | ||
586 | /* Illegal translation */ | |
587 | if (section.mr == &io_mem_unassigned) { | |
588 | goto iotlb_fail; | |
589 | } | |
590 | ||
591 | /* Convert memory region offset into address space offset */ | |
592 | xlat += section.offset_within_address_space - | |
593 | section.offset_within_region; | |
594 | ||
595 | return (IOMMUTLBEntry) { | |
596 | .target_as = as, | |
597 | .iova = addr & ~page_mask, | |
598 | .translated_addr = xlat & ~page_mask, | |
599 | .addr_mask = page_mask, | |
600 | /* IOTLBs are for DMAs, and DMA only allows on RAMs. */ | |
601 | .perm = IOMMU_RW, | |
602 | }; | |
603 | ||
604 | iotlb_fail: | |
605 | return (IOMMUTLBEntry) {0}; | |
606 | } | |
607 | ||
608 | /* Called from RCU critical section */ | |
609 | MemoryRegion *flatview_translate(FlatView *fv, hwaddr addr, hwaddr *xlat, | |
610 | hwaddr *plen, bool is_write, | |
611 | MemTxAttrs attrs) | |
612 | { | |
613 | MemoryRegion *mr; | |
614 | MemoryRegionSection section; | |
615 | AddressSpace *as = NULL; | |
616 | ||
617 | /* This can be MMIO, so setup MMIO bit. */ | |
618 | section = flatview_do_translate(fv, addr, xlat, plen, NULL, | |
619 | is_write, true, &as, attrs); | |
620 | mr = section.mr; | |
621 | ||
622 | if (xen_enabled() && memory_access_is_direct(mr, is_write)) { | |
623 | hwaddr page = ((addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE) - addr; | |
624 | *plen = MIN(page, *plen); | |
625 | } | |
626 | ||
627 | return mr; | |
628 | } | |
629 | ||
630 | typedef struct TCGIOMMUNotifier { | |
631 | IOMMUNotifier n; | |
632 | MemoryRegion *mr; | |
633 | CPUState *cpu; | |
634 | int iommu_idx; | |
635 | bool active; | |
636 | } TCGIOMMUNotifier; | |
637 | ||
638 | static void tcg_iommu_unmap_notify(IOMMUNotifier *n, IOMMUTLBEntry *iotlb) | |
639 | { | |
640 | TCGIOMMUNotifier *notifier = container_of(n, TCGIOMMUNotifier, n); | |
641 | ||
642 | if (!notifier->active) { | |
643 | return; | |
644 | } | |
645 | tlb_flush(notifier->cpu); | |
646 | notifier->active = false; | |
647 | /* We leave the notifier struct on the list to avoid reallocating it later. | |
648 | * Generally the number of IOMMUs a CPU deals with will be small. | |
649 | * In any case we can't unregister the iommu notifier from a notify | |
650 | * callback. | |
651 | */ | |
652 | } | |
653 | ||
654 | static void tcg_register_iommu_notifier(CPUState *cpu, | |
655 | IOMMUMemoryRegion *iommu_mr, | |
656 | int iommu_idx) | |
657 | { | |
658 | /* Make sure this CPU has an IOMMU notifier registered for this | |
659 | * IOMMU/IOMMU index combination, so that we can flush its TLB | |
660 | * when the IOMMU tells us the mappings we've cached have changed. | |
661 | */ | |
662 | MemoryRegion *mr = MEMORY_REGION(iommu_mr); | |
663 | TCGIOMMUNotifier *notifier; | |
664 | int i; | |
665 | ||
666 | for (i = 0; i < cpu->iommu_notifiers->len; i++) { | |
667 | notifier = &g_array_index(cpu->iommu_notifiers, TCGIOMMUNotifier, i); | |
668 | if (notifier->mr == mr && notifier->iommu_idx == iommu_idx) { | |
669 | break; | |
670 | } | |
671 | } | |
672 | if (i == cpu->iommu_notifiers->len) { | |
673 | /* Not found, add a new entry at the end of the array */ | |
674 | cpu->iommu_notifiers = g_array_set_size(cpu->iommu_notifiers, i + 1); | |
675 | notifier = &g_array_index(cpu->iommu_notifiers, TCGIOMMUNotifier, i); | |
676 | ||
677 | notifier->mr = mr; | |
678 | notifier->iommu_idx = iommu_idx; | |
679 | notifier->cpu = cpu; | |
680 | /* Rather than trying to register interest in the specific part | |
681 | * of the iommu's address space that we've accessed and then | |
682 | * expand it later as subsequent accesses touch more of it, we | |
683 | * just register interest in the whole thing, on the assumption | |
684 | * that iommu reconfiguration will be rare. | |
685 | */ | |
686 | iommu_notifier_init(¬ifier->n, | |
687 | tcg_iommu_unmap_notify, | |
688 | IOMMU_NOTIFIER_UNMAP, | |
689 | 0, | |
690 | HWADDR_MAX, | |
691 | iommu_idx); | |
692 | memory_region_register_iommu_notifier(notifier->mr, ¬ifier->n); | |
693 | } | |
694 | ||
695 | if (!notifier->active) { | |
696 | notifier->active = true; | |
697 | } | |
698 | } | |
699 | ||
700 | static void tcg_iommu_free_notifier_list(CPUState *cpu) | |
701 | { | |
702 | /* Destroy the CPU's notifier list */ | |
703 | int i; | |
704 | TCGIOMMUNotifier *notifier; | |
705 | ||
706 | for (i = 0; i < cpu->iommu_notifiers->len; i++) { | |
707 | notifier = &g_array_index(cpu->iommu_notifiers, TCGIOMMUNotifier, i); | |
708 | memory_region_unregister_iommu_notifier(notifier->mr, ¬ifier->n); | |
709 | } | |
710 | g_array_free(cpu->iommu_notifiers, true); | |
711 | } | |
712 | ||
713 | /* Called from RCU critical section */ | |
714 | MemoryRegionSection * | |
715 | address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr, | |
716 | hwaddr *xlat, hwaddr *plen, | |
717 | MemTxAttrs attrs, int *prot) | |
718 | { | |
719 | MemoryRegionSection *section; | |
720 | IOMMUMemoryRegion *iommu_mr; | |
721 | IOMMUMemoryRegionClass *imrc; | |
722 | IOMMUTLBEntry iotlb; | |
723 | int iommu_idx; | |
724 | AddressSpaceDispatch *d = atomic_rcu_read(&cpu->cpu_ases[asidx].memory_dispatch); | |
725 | ||
726 | for (;;) { | |
727 | section = address_space_translate_internal(d, addr, &addr, plen, false); | |
728 | ||
729 | iommu_mr = memory_region_get_iommu(section->mr); | |
730 | if (!iommu_mr) { | |
731 | break; | |
732 | } | |
733 | ||
734 | imrc = memory_region_get_iommu_class_nocheck(iommu_mr); | |
735 | ||
736 | iommu_idx = imrc->attrs_to_index(iommu_mr, attrs); | |
737 | tcg_register_iommu_notifier(cpu, iommu_mr, iommu_idx); | |
738 | /* We need all the permissions, so pass IOMMU_NONE so the IOMMU | |
739 | * doesn't short-cut its translation table walk. | |
740 | */ | |
741 | iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE, iommu_idx); | |
742 | addr = ((iotlb.translated_addr & ~iotlb.addr_mask) | |
743 | | (addr & iotlb.addr_mask)); | |
744 | /* Update the caller's prot bits to remove permissions the IOMMU | |
745 | * is giving us a failure response for. If we get down to no | |
746 | * permissions left at all we can give up now. | |
747 | */ | |
748 | if (!(iotlb.perm & IOMMU_RO)) { | |
749 | *prot &= ~(PAGE_READ | PAGE_EXEC); | |
750 | } | |
751 | if (!(iotlb.perm & IOMMU_WO)) { | |
752 | *prot &= ~PAGE_WRITE; | |
753 | } | |
754 | ||
755 | if (!*prot) { | |
756 | goto translate_fail; | |
757 | } | |
758 | ||
759 | d = flatview_to_dispatch(address_space_to_flatview(iotlb.target_as)); | |
760 | } | |
761 | ||
762 | assert(!memory_region_is_iommu(section->mr)); | |
763 | *xlat = addr; | |
764 | return section; | |
765 | ||
766 | translate_fail: | |
767 | return &d->map.sections[PHYS_SECTION_UNASSIGNED]; | |
768 | } | |
769 | #endif | |
770 | ||
771 | #if !defined(CONFIG_USER_ONLY) | |
772 | ||
773 | static int cpu_common_post_load(void *opaque, int version_id) | |
774 | { | |
775 | CPUState *cpu = opaque; | |
776 | ||
777 | /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the | |
778 | version_id is increased. */ | |
779 | cpu->interrupt_request &= ~0x01; | |
780 | tlb_flush(cpu); | |
781 | ||
782 | /* loadvm has just updated the content of RAM, bypassing the | |
783 | * usual mechanisms that ensure we flush TBs for writes to | |
784 | * memory we've translated code from. So we must flush all TBs, | |
785 | * which will now be stale. | |
786 | */ | |
787 | tb_flush(cpu); | |
788 | ||
789 | return 0; | |
790 | } | |
791 | ||
792 | static int cpu_common_pre_load(void *opaque) | |
793 | { | |
794 | CPUState *cpu = opaque; | |
795 | ||
796 | cpu->exception_index = -1; | |
797 | ||
798 | return 0; | |
799 | } | |
800 | ||
801 | static bool cpu_common_exception_index_needed(void *opaque) | |
802 | { | |
803 | CPUState *cpu = opaque; | |
804 | ||
805 | return tcg_enabled() && cpu->exception_index != -1; | |
806 | } | |
807 | ||
808 | static const VMStateDescription vmstate_cpu_common_exception_index = { | |
809 | .name = "cpu_common/exception_index", | |
810 | .version_id = 1, | |
811 | .minimum_version_id = 1, | |
812 | .needed = cpu_common_exception_index_needed, | |
813 | .fields = (VMStateField[]) { | |
814 | VMSTATE_INT32(exception_index, CPUState), | |
815 | VMSTATE_END_OF_LIST() | |
816 | } | |
817 | }; | |
818 | ||
819 | static bool cpu_common_crash_occurred_needed(void *opaque) | |
820 | { | |
821 | CPUState *cpu = opaque; | |
822 | ||
823 | return cpu->crash_occurred; | |
824 | } | |
825 | ||
826 | static const VMStateDescription vmstate_cpu_common_crash_occurred = { | |
827 | .name = "cpu_common/crash_occurred", | |
828 | .version_id = 1, | |
829 | .minimum_version_id = 1, | |
830 | .needed = cpu_common_crash_occurred_needed, | |
831 | .fields = (VMStateField[]) { | |
832 | VMSTATE_BOOL(crash_occurred, CPUState), | |
833 | VMSTATE_END_OF_LIST() | |
834 | } | |
835 | }; | |
836 | ||
837 | const VMStateDescription vmstate_cpu_common = { | |
838 | .name = "cpu_common", | |
839 | .version_id = 1, | |
840 | .minimum_version_id = 1, | |
841 | .pre_load = cpu_common_pre_load, | |
842 | .post_load = cpu_common_post_load, | |
843 | .fields = (VMStateField[]) { | |
844 | VMSTATE_UINT32(halted, CPUState), | |
845 | VMSTATE_UINT32(interrupt_request, CPUState), | |
846 | VMSTATE_END_OF_LIST() | |
847 | }, | |
848 | .subsections = (const VMStateDescription*[]) { | |
849 | &vmstate_cpu_common_exception_index, | |
850 | &vmstate_cpu_common_crash_occurred, | |
851 | NULL | |
852 | } | |
853 | }; | |
854 | ||
855 | #endif | |
856 | ||
857 | CPUState *qemu_get_cpu(int index) | |
858 | { | |
859 | CPUState *cpu; | |
860 | ||
861 | CPU_FOREACH(cpu) { | |
862 | if (cpu->cpu_index == index) { | |
863 | return cpu; | |
864 | } | |
865 | } | |
866 | ||
867 | return NULL; | |
868 | } | |
869 | ||
870 | #if !defined(CONFIG_USER_ONLY) | |
871 | void cpu_address_space_init(CPUState *cpu, int asidx, | |
872 | const char *prefix, MemoryRegion *mr) | |
873 | { | |
874 | CPUAddressSpace *newas; | |
875 | AddressSpace *as = g_new0(AddressSpace, 1); | |
876 | char *as_name; | |
877 | ||
878 | assert(mr); | |
879 | as_name = g_strdup_printf("%s-%d", prefix, cpu->cpu_index); | |
880 | address_space_init(as, mr, as_name); | |
881 | g_free(as_name); | |
882 | ||
883 | /* Target code should have set num_ases before calling us */ | |
884 | assert(asidx < cpu->num_ases); | |
885 | ||
886 | if (asidx == 0) { | |
887 | /* address space 0 gets the convenience alias */ | |
888 | cpu->as = as; | |
889 | } | |
890 | ||
891 | /* KVM cannot currently support multiple address spaces. */ | |
892 | assert(asidx == 0 || !kvm_enabled()); | |
893 | ||
894 | if (!cpu->cpu_ases) { | |
895 | cpu->cpu_ases = g_new0(CPUAddressSpace, cpu->num_ases); | |
896 | } | |
897 | ||
898 | newas = &cpu->cpu_ases[asidx]; | |
899 | newas->cpu = cpu; | |
900 | newas->as = as; | |
901 | if (tcg_enabled()) { | |
902 | newas->tcg_as_listener.commit = tcg_commit; | |
903 | memory_listener_register(&newas->tcg_as_listener, as); | |
904 | } | |
905 | } | |
906 | ||
907 | AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx) | |
908 | { | |
909 | /* Return the AddressSpace corresponding to the specified index */ | |
910 | return cpu->cpu_ases[asidx].as; | |
911 | } | |
912 | #endif | |
913 | ||
914 | void cpu_exec_unrealizefn(CPUState *cpu) | |
915 | { | |
916 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
917 | ||
918 | cpu_list_remove(cpu); | |
919 | ||
920 | if (cc->vmsd != NULL) { | |
921 | vmstate_unregister(NULL, cc->vmsd, cpu); | |
922 | } | |
923 | if (qdev_get_vmsd(DEVICE(cpu)) == NULL) { | |
924 | vmstate_unregister(NULL, &vmstate_cpu_common, cpu); | |
925 | } | |
926 | #ifndef CONFIG_USER_ONLY | |
927 | tcg_iommu_free_notifier_list(cpu); | |
928 | #endif | |
929 | } | |
930 | ||
931 | Property cpu_common_props[] = { | |
932 | #ifndef CONFIG_USER_ONLY | |
933 | /* Create a memory property for softmmu CPU object, | |
934 | * so users can wire up its memory. (This can't go in qom/cpu.c | |
935 | * because that file is compiled only once for both user-mode | |
936 | * and system builds.) The default if no link is set up is to use | |
937 | * the system address space. | |
938 | */ | |
939 | DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION, | |
940 | MemoryRegion *), | |
941 | #endif | |
942 | DEFINE_PROP_END_OF_LIST(), | |
943 | }; | |
944 | ||
945 | void cpu_exec_initfn(CPUState *cpu) | |
946 | { | |
947 | cpu->as = NULL; | |
948 | cpu->num_ases = 0; | |
949 | ||
950 | #ifndef CONFIG_USER_ONLY | |
951 | cpu->thread_id = qemu_get_thread_id(); | |
952 | cpu->memory = system_memory; | |
953 | object_ref(OBJECT(cpu->memory)); | |
954 | #endif | |
955 | } | |
956 | ||
957 | void cpu_exec_realizefn(CPUState *cpu, Error **errp) | |
958 | { | |
959 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
960 | static bool tcg_target_initialized; | |
961 | ||
962 | cpu_list_add(cpu); | |
963 | ||
964 | if (tcg_enabled() && !tcg_target_initialized) { | |
965 | tcg_target_initialized = true; | |
966 | cc->tcg_initialize(); | |
967 | } | |
968 | tlb_init(cpu); | |
969 | ||
970 | #ifndef CONFIG_USER_ONLY | |
971 | if (qdev_get_vmsd(DEVICE(cpu)) == NULL) { | |
972 | vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu); | |
973 | } | |
974 | if (cc->vmsd != NULL) { | |
975 | vmstate_register(NULL, cpu->cpu_index, cc->vmsd, cpu); | |
976 | } | |
977 | ||
978 | cpu->iommu_notifiers = g_array_new(false, true, sizeof(TCGIOMMUNotifier)); | |
979 | #endif | |
980 | } | |
981 | ||
982 | const char *parse_cpu_model(const char *cpu_model) | |
983 | { | |
984 | ObjectClass *oc; | |
985 | CPUClass *cc; | |
986 | gchar **model_pieces; | |
987 | const char *cpu_type; | |
988 | ||
989 | model_pieces = g_strsplit(cpu_model, ",", 2); | |
990 | ||
991 | oc = cpu_class_by_name(CPU_RESOLVING_TYPE, model_pieces[0]); | |
992 | if (oc == NULL) { | |
993 | error_report("unable to find CPU model '%s'", model_pieces[0]); | |
994 | g_strfreev(model_pieces); | |
995 | exit(EXIT_FAILURE); | |
996 | } | |
997 | ||
998 | cpu_type = object_class_get_name(oc); | |
999 | cc = CPU_CLASS(oc); | |
1000 | cc->parse_features(cpu_type, model_pieces[1], &error_fatal); | |
1001 | g_strfreev(model_pieces); | |
1002 | return cpu_type; | |
1003 | } | |
1004 | ||
1005 | #if defined(CONFIG_USER_ONLY) | |
1006 | void tb_invalidate_phys_addr(target_ulong addr) | |
1007 | { | |
1008 | mmap_lock(); | |
1009 | tb_invalidate_phys_page_range(addr, addr + 1, 0); | |
1010 | mmap_unlock(); | |
1011 | } | |
1012 | ||
1013 | static void breakpoint_invalidate(CPUState *cpu, target_ulong pc) | |
1014 | { | |
1015 | tb_invalidate_phys_addr(pc); | |
1016 | } | |
1017 | #else | |
1018 | void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs) | |
1019 | { | |
1020 | ram_addr_t ram_addr; | |
1021 | MemoryRegion *mr; | |
1022 | hwaddr l = 1; | |
1023 | ||
1024 | if (!tcg_enabled()) { | |
1025 | return; | |
1026 | } | |
1027 | ||
1028 | rcu_read_lock(); | |
1029 | mr = address_space_translate(as, addr, &addr, &l, false, attrs); | |
1030 | if (!(memory_region_is_ram(mr) | |
1031 | || memory_region_is_romd(mr))) { | |
1032 | rcu_read_unlock(); | |
1033 | return; | |
1034 | } | |
1035 | ram_addr = memory_region_get_ram_addr(mr) + addr; | |
1036 | tb_invalidate_phys_page_range(ram_addr, ram_addr + 1, 0); | |
1037 | rcu_read_unlock(); | |
1038 | } | |
1039 | ||
1040 | static void breakpoint_invalidate(CPUState *cpu, target_ulong pc) | |
1041 | { | |
1042 | MemTxAttrs attrs; | |
1043 | hwaddr phys = cpu_get_phys_page_attrs_debug(cpu, pc, &attrs); | |
1044 | int asidx = cpu_asidx_from_attrs(cpu, attrs); | |
1045 | if (phys != -1) { | |
1046 | /* Locks grabbed by tb_invalidate_phys_addr */ | |
1047 | tb_invalidate_phys_addr(cpu->cpu_ases[asidx].as, | |
1048 | phys | (pc & ~TARGET_PAGE_MASK), attrs); | |
1049 | } | |
1050 | } | |
1051 | #endif | |
1052 | ||
1053 | #if defined(CONFIG_USER_ONLY) | |
1054 | void cpu_watchpoint_remove_all(CPUState *cpu, int mask) | |
1055 | ||
1056 | { | |
1057 | } | |
1058 | ||
1059 | int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len, | |
1060 | int flags) | |
1061 | { | |
1062 | return -ENOSYS; | |
1063 | } | |
1064 | ||
1065 | void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint) | |
1066 | { | |
1067 | } | |
1068 | ||
1069 | int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, | |
1070 | int flags, CPUWatchpoint **watchpoint) | |
1071 | { | |
1072 | return -ENOSYS; | |
1073 | } | |
1074 | #else | |
1075 | /* Add a watchpoint. */ | |
1076 | int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, | |
1077 | int flags, CPUWatchpoint **watchpoint) | |
1078 | { | |
1079 | CPUWatchpoint *wp; | |
1080 | ||
1081 | /* forbid ranges which are empty or run off the end of the address space */ | |
1082 | if (len == 0 || (addr + len - 1) < addr) { | |
1083 | error_report("tried to set invalid watchpoint at %" | |
1084 | VADDR_PRIx ", len=%" VADDR_PRIu, addr, len); | |
1085 | return -EINVAL; | |
1086 | } | |
1087 | wp = g_malloc(sizeof(*wp)); | |
1088 | ||
1089 | wp->vaddr = addr; | |
1090 | wp->len = len; | |
1091 | wp->flags = flags; | |
1092 | ||
1093 | /* keep all GDB-injected watchpoints in front */ | |
1094 | if (flags & BP_GDB) { | |
1095 | QTAILQ_INSERT_HEAD(&cpu->watchpoints, wp, entry); | |
1096 | } else { | |
1097 | QTAILQ_INSERT_TAIL(&cpu->watchpoints, wp, entry); | |
1098 | } | |
1099 | ||
1100 | tlb_flush_page(cpu, addr); | |
1101 | ||
1102 | if (watchpoint) | |
1103 | *watchpoint = wp; | |
1104 | return 0; | |
1105 | } | |
1106 | ||
1107 | /* Remove a specific watchpoint. */ | |
1108 | int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len, | |
1109 | int flags) | |
1110 | { | |
1111 | CPUWatchpoint *wp; | |
1112 | ||
1113 | QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { | |
1114 | if (addr == wp->vaddr && len == wp->len | |
1115 | && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) { | |
1116 | cpu_watchpoint_remove_by_ref(cpu, wp); | |
1117 | return 0; | |
1118 | } | |
1119 | } | |
1120 | return -ENOENT; | |
1121 | } | |
1122 | ||
1123 | /* Remove a specific watchpoint by reference. */ | |
1124 | void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint) | |
1125 | { | |
1126 | QTAILQ_REMOVE(&cpu->watchpoints, watchpoint, entry); | |
1127 | ||
1128 | tlb_flush_page(cpu, watchpoint->vaddr); | |
1129 | ||
1130 | g_free(watchpoint); | |
1131 | } | |
1132 | ||
1133 | /* Remove all matching watchpoints. */ | |
1134 | void cpu_watchpoint_remove_all(CPUState *cpu, int mask) | |
1135 | { | |
1136 | CPUWatchpoint *wp, *next; | |
1137 | ||
1138 | QTAILQ_FOREACH_SAFE(wp, &cpu->watchpoints, entry, next) { | |
1139 | if (wp->flags & mask) { | |
1140 | cpu_watchpoint_remove_by_ref(cpu, wp); | |
1141 | } | |
1142 | } | |
1143 | } | |
1144 | ||
1145 | /* Return true if this watchpoint address matches the specified | |
1146 | * access (ie the address range covered by the watchpoint overlaps | |
1147 | * partially or completely with the address range covered by the | |
1148 | * access). | |
1149 | */ | |
1150 | static inline bool cpu_watchpoint_address_matches(CPUWatchpoint *wp, | |
1151 | vaddr addr, | |
1152 | vaddr len) | |
1153 | { | |
1154 | /* We know the lengths are non-zero, but a little caution is | |
1155 | * required to avoid errors in the case where the range ends | |
1156 | * exactly at the top of the address space and so addr + len | |
1157 | * wraps round to zero. | |
1158 | */ | |
1159 | vaddr wpend = wp->vaddr + wp->len - 1; | |
1160 | vaddr addrend = addr + len - 1; | |
1161 | ||
1162 | return !(addr > wpend || wp->vaddr > addrend); | |
1163 | } | |
1164 | ||
1165 | #endif | |
1166 | ||
1167 | /* Add a breakpoint. */ | |
1168 | int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags, | |
1169 | CPUBreakpoint **breakpoint) | |
1170 | { | |
1171 | CPUBreakpoint *bp; | |
1172 | ||
1173 | bp = g_malloc(sizeof(*bp)); | |
1174 | ||
1175 | bp->pc = pc; | |
1176 | bp->flags = flags; | |
1177 | ||
1178 | /* keep all GDB-injected breakpoints in front */ | |
1179 | if (flags & BP_GDB) { | |
1180 | QTAILQ_INSERT_HEAD(&cpu->breakpoints, bp, entry); | |
1181 | } else { | |
1182 | QTAILQ_INSERT_TAIL(&cpu->breakpoints, bp, entry); | |
1183 | } | |
1184 | ||
1185 | breakpoint_invalidate(cpu, pc); | |
1186 | ||
1187 | if (breakpoint) { | |
1188 | *breakpoint = bp; | |
1189 | } | |
1190 | return 0; | |
1191 | } | |
1192 | ||
1193 | /* Remove a specific breakpoint. */ | |
1194 | int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags) | |
1195 | { | |
1196 | CPUBreakpoint *bp; | |
1197 | ||
1198 | QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { | |
1199 | if (bp->pc == pc && bp->flags == flags) { | |
1200 | cpu_breakpoint_remove_by_ref(cpu, bp); | |
1201 | return 0; | |
1202 | } | |
1203 | } | |
1204 | return -ENOENT; | |
1205 | } | |
1206 | ||
1207 | /* Remove a specific breakpoint by reference. */ | |
1208 | void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint) | |
1209 | { | |
1210 | QTAILQ_REMOVE(&cpu->breakpoints, breakpoint, entry); | |
1211 | ||
1212 | breakpoint_invalidate(cpu, breakpoint->pc); | |
1213 | ||
1214 | g_free(breakpoint); | |
1215 | } | |
1216 | ||
1217 | /* Remove all matching breakpoints. */ | |
1218 | void cpu_breakpoint_remove_all(CPUState *cpu, int mask) | |
1219 | { | |
1220 | CPUBreakpoint *bp, *next; | |
1221 | ||
1222 | QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) { | |
1223 | if (bp->flags & mask) { | |
1224 | cpu_breakpoint_remove_by_ref(cpu, bp); | |
1225 | } | |
1226 | } | |
1227 | } | |
1228 | ||
1229 | /* enable or disable single step mode. EXCP_DEBUG is returned by the | |
1230 | CPU loop after each instruction */ | |
1231 | void cpu_single_step(CPUState *cpu, int enabled) | |
1232 | { | |
1233 | if (cpu->singlestep_enabled != enabled) { | |
1234 | cpu->singlestep_enabled = enabled; | |
1235 | if (kvm_enabled()) { | |
1236 | kvm_update_guest_debug(cpu, 0); | |
1237 | } else { | |
1238 | /* must flush all the translated code to avoid inconsistencies */ | |
1239 | /* XXX: only flush what is necessary */ | |
1240 | tb_flush(cpu); | |
1241 | } | |
1242 | } | |
1243 | } | |
1244 | ||
1245 | void cpu_abort(CPUState *cpu, const char *fmt, ...) | |
1246 | { | |
1247 | va_list ap; | |
1248 | va_list ap2; | |
1249 | ||
1250 | va_start(ap, fmt); | |
1251 | va_copy(ap2, ap); | |
1252 | fprintf(stderr, "qemu: fatal: "); | |
1253 | vfprintf(stderr, fmt, ap); | |
1254 | fprintf(stderr, "\n"); | |
1255 | cpu_dump_state(cpu, stderr, fprintf, CPU_DUMP_FPU | CPU_DUMP_CCOP); | |
1256 | if (qemu_log_separate()) { | |
1257 | qemu_log_lock(); | |
1258 | qemu_log("qemu: fatal: "); | |
1259 | qemu_log_vprintf(fmt, ap2); | |
1260 | qemu_log("\n"); | |
1261 | log_cpu_state(cpu, CPU_DUMP_FPU | CPU_DUMP_CCOP); | |
1262 | qemu_log_flush(); | |
1263 | qemu_log_unlock(); | |
1264 | qemu_log_close(); | |
1265 | } | |
1266 | va_end(ap2); | |
1267 | va_end(ap); | |
1268 | replay_finish(); | |
1269 | #if defined(CONFIG_USER_ONLY) | |
1270 | { | |
1271 | struct sigaction act; | |
1272 | sigfillset(&act.sa_mask); | |
1273 | act.sa_handler = SIG_DFL; | |
1274 | act.sa_flags = 0; | |
1275 | sigaction(SIGABRT, &act, NULL); | |
1276 | } | |
1277 | #endif | |
1278 | abort(); | |
1279 | } | |
1280 | ||
1281 | #if !defined(CONFIG_USER_ONLY) | |
1282 | /* Called from RCU critical section */ | |
1283 | static RAMBlock *qemu_get_ram_block(ram_addr_t addr) | |
1284 | { | |
1285 | RAMBlock *block; | |
1286 | ||
1287 | block = atomic_rcu_read(&ram_list.mru_block); | |
1288 | if (block && addr - block->offset < block->max_length) { | |
1289 | return block; | |
1290 | } | |
1291 | RAMBLOCK_FOREACH(block) { | |
1292 | if (addr - block->offset < block->max_length) { | |
1293 | goto found; | |
1294 | } | |
1295 | } | |
1296 | ||
1297 | fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr); | |
1298 | abort(); | |
1299 | ||
1300 | found: | |
1301 | /* It is safe to write mru_block outside the iothread lock. This | |
1302 | * is what happens: | |
1303 | * | |
1304 | * mru_block = xxx | |
1305 | * rcu_read_unlock() | |
1306 | * xxx removed from list | |
1307 | * rcu_read_lock() | |
1308 | * read mru_block | |
1309 | * mru_block = NULL; | |
1310 | * call_rcu(reclaim_ramblock, xxx); | |
1311 | * rcu_read_unlock() | |
1312 | * | |
1313 | * atomic_rcu_set is not needed here. The block was already published | |
1314 | * when it was placed into the list. Here we're just making an extra | |
1315 | * copy of the pointer. | |
1316 | */ | |
1317 | ram_list.mru_block = block; | |
1318 | return block; | |
1319 | } | |
1320 | ||
1321 | static void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length) | |
1322 | { | |
1323 | CPUState *cpu; | |
1324 | ram_addr_t start1; | |
1325 | RAMBlock *block; | |
1326 | ram_addr_t end; | |
1327 | ||
1328 | assert(tcg_enabled()); | |
1329 | end = TARGET_PAGE_ALIGN(start + length); | |
1330 | start &= TARGET_PAGE_MASK; | |
1331 | ||
1332 | rcu_read_lock(); | |
1333 | block = qemu_get_ram_block(start); | |
1334 | assert(block == qemu_get_ram_block(end - 1)); | |
1335 | start1 = (uintptr_t)ramblock_ptr(block, start - block->offset); | |
1336 | CPU_FOREACH(cpu) { | |
1337 | tlb_reset_dirty(cpu, start1, length); | |
1338 | } | |
1339 | rcu_read_unlock(); | |
1340 | } | |
1341 | ||
1342 | /* Note: start and end must be within the same ram block. */ | |
1343 | bool cpu_physical_memory_test_and_clear_dirty(ram_addr_t start, | |
1344 | ram_addr_t length, | |
1345 | unsigned client) | |
1346 | { | |
1347 | DirtyMemoryBlocks *blocks; | |
1348 | unsigned long end, page; | |
1349 | bool dirty = false; | |
1350 | ||
1351 | if (length == 0) { | |
1352 | return false; | |
1353 | } | |
1354 | ||
1355 | end = TARGET_PAGE_ALIGN(start + length) >> TARGET_PAGE_BITS; | |
1356 | page = start >> TARGET_PAGE_BITS; | |
1357 | ||
1358 | rcu_read_lock(); | |
1359 | ||
1360 | blocks = atomic_rcu_read(&ram_list.dirty_memory[client]); | |
1361 | ||
1362 | while (page < end) { | |
1363 | unsigned long idx = page / DIRTY_MEMORY_BLOCK_SIZE; | |
1364 | unsigned long offset = page % DIRTY_MEMORY_BLOCK_SIZE; | |
1365 | unsigned long num = MIN(end - page, DIRTY_MEMORY_BLOCK_SIZE - offset); | |
1366 | ||
1367 | dirty |= bitmap_test_and_clear_atomic(blocks->blocks[idx], | |
1368 | offset, num); | |
1369 | page += num; | |
1370 | } | |
1371 | ||
1372 | rcu_read_unlock(); | |
1373 | ||
1374 | if (dirty && tcg_enabled()) { | |
1375 | tlb_reset_dirty_range_all(start, length); | |
1376 | } | |
1377 | ||
1378 | return dirty; | |
1379 | } | |
1380 | ||
1381 | DirtyBitmapSnapshot *cpu_physical_memory_snapshot_and_clear_dirty | |
1382 | (ram_addr_t start, ram_addr_t length, unsigned client) | |
1383 | { | |
1384 | DirtyMemoryBlocks *blocks; | |
1385 | unsigned long align = 1UL << (TARGET_PAGE_BITS + BITS_PER_LEVEL); | |
1386 | ram_addr_t first = QEMU_ALIGN_DOWN(start, align); | |
1387 | ram_addr_t last = QEMU_ALIGN_UP(start + length, align); | |
1388 | DirtyBitmapSnapshot *snap; | |
1389 | unsigned long page, end, dest; | |
1390 | ||
1391 | snap = g_malloc0(sizeof(*snap) + | |
1392 | ((last - first) >> (TARGET_PAGE_BITS + 3))); | |
1393 | snap->start = first; | |
1394 | snap->end = last; | |
1395 | ||
1396 | page = first >> TARGET_PAGE_BITS; | |
1397 | end = last >> TARGET_PAGE_BITS; | |
1398 | dest = 0; | |
1399 | ||
1400 | rcu_read_lock(); | |
1401 | ||
1402 | blocks = atomic_rcu_read(&ram_list.dirty_memory[client]); | |
1403 | ||
1404 | while (page < end) { | |
1405 | unsigned long idx = page / DIRTY_MEMORY_BLOCK_SIZE; | |
1406 | unsigned long offset = page % DIRTY_MEMORY_BLOCK_SIZE; | |
1407 | unsigned long num = MIN(end - page, DIRTY_MEMORY_BLOCK_SIZE - offset); | |
1408 | ||
1409 | assert(QEMU_IS_ALIGNED(offset, (1 << BITS_PER_LEVEL))); | |
1410 | assert(QEMU_IS_ALIGNED(num, (1 << BITS_PER_LEVEL))); | |
1411 | offset >>= BITS_PER_LEVEL; | |
1412 | ||
1413 | bitmap_copy_and_clear_atomic(snap->dirty + dest, | |
1414 | blocks->blocks[idx] + offset, | |
1415 | num); | |
1416 | page += num; | |
1417 | dest += num >> BITS_PER_LEVEL; | |
1418 | } | |
1419 | ||
1420 | rcu_read_unlock(); | |
1421 | ||
1422 | if (tcg_enabled()) { | |
1423 | tlb_reset_dirty_range_all(start, length); | |
1424 | } | |
1425 | ||
1426 | return snap; | |
1427 | } | |
1428 | ||
1429 | bool cpu_physical_memory_snapshot_get_dirty(DirtyBitmapSnapshot *snap, | |
1430 | ram_addr_t start, | |
1431 | ram_addr_t length) | |
1432 | { | |
1433 | unsigned long page, end; | |
1434 | ||
1435 | assert(start >= snap->start); | |
1436 | assert(start + length <= snap->end); | |
1437 | ||
1438 | end = TARGET_PAGE_ALIGN(start + length - snap->start) >> TARGET_PAGE_BITS; | |
1439 | page = (start - snap->start) >> TARGET_PAGE_BITS; | |
1440 | ||
1441 | while (page < end) { | |
1442 | if (test_bit(page, snap->dirty)) { | |
1443 | return true; | |
1444 | } | |
1445 | page++; | |
1446 | } | |
1447 | return false; | |
1448 | } | |
1449 | ||
1450 | /* Called from RCU critical section */ | |
1451 | hwaddr memory_region_section_get_iotlb(CPUState *cpu, | |
1452 | MemoryRegionSection *section, | |
1453 | target_ulong vaddr, | |
1454 | hwaddr paddr, hwaddr xlat, | |
1455 | int prot, | |
1456 | target_ulong *address) | |
1457 | { | |
1458 | hwaddr iotlb; | |
1459 | CPUWatchpoint *wp; | |
1460 | ||
1461 | if (memory_region_is_ram(section->mr)) { | |
1462 | /* Normal RAM. */ | |
1463 | iotlb = memory_region_get_ram_addr(section->mr) + xlat; | |
1464 | if (!section->readonly) { | |
1465 | iotlb |= PHYS_SECTION_NOTDIRTY; | |
1466 | } else { | |
1467 | iotlb |= PHYS_SECTION_ROM; | |
1468 | } | |
1469 | } else { | |
1470 | AddressSpaceDispatch *d; | |
1471 | ||
1472 | d = flatview_to_dispatch(section->fv); | |
1473 | iotlb = section - d->map.sections; | |
1474 | iotlb += xlat; | |
1475 | } | |
1476 | ||
1477 | /* Make accesses to pages with watchpoints go via the | |
1478 | watchpoint trap routines. */ | |
1479 | QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { | |
1480 | if (cpu_watchpoint_address_matches(wp, vaddr, TARGET_PAGE_SIZE)) { | |
1481 | /* Avoid trapping reads of pages with a write breakpoint. */ | |
1482 | if ((prot & PAGE_WRITE) || (wp->flags & BP_MEM_READ)) { | |
1483 | iotlb = PHYS_SECTION_WATCH + paddr; | |
1484 | *address |= TLB_MMIO; | |
1485 | break; | |
1486 | } | |
1487 | } | |
1488 | } | |
1489 | ||
1490 | return iotlb; | |
1491 | } | |
1492 | #endif /* defined(CONFIG_USER_ONLY) */ | |
1493 | ||
1494 | #if !defined(CONFIG_USER_ONLY) | |
1495 | ||
1496 | static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, | |
1497 | uint16_t section); | |
1498 | static subpage_t *subpage_init(FlatView *fv, hwaddr base); | |
1499 | ||
1500 | static void *(*phys_mem_alloc)(size_t size, uint64_t *align, bool shared) = | |
1501 | qemu_anon_ram_alloc; | |
1502 | ||
1503 | /* | |
1504 | * Set a custom physical guest memory alloator. | |
1505 | * Accelerators with unusual needs may need this. Hopefully, we can | |
1506 | * get rid of it eventually. | |
1507 | */ | |
1508 | void phys_mem_set_alloc(void *(*alloc)(size_t, uint64_t *align, bool shared)) | |
1509 | { | |
1510 | phys_mem_alloc = alloc; | |
1511 | } | |
1512 | ||
1513 | static uint16_t phys_section_add(PhysPageMap *map, | |
1514 | MemoryRegionSection *section) | |
1515 | { | |
1516 | /* The physical section number is ORed with a page-aligned | |
1517 | * pointer to produce the iotlb entries. Thus it should | |
1518 | * never overflow into the page-aligned value. | |
1519 | */ | |
1520 | assert(map->sections_nb < TARGET_PAGE_SIZE); | |
1521 | ||
1522 | if (map->sections_nb == map->sections_nb_alloc) { | |
1523 | map->sections_nb_alloc = MAX(map->sections_nb_alloc * 2, 16); | |
1524 | map->sections = g_renew(MemoryRegionSection, map->sections, | |
1525 | map->sections_nb_alloc); | |
1526 | } | |
1527 | map->sections[map->sections_nb] = *section; | |
1528 | memory_region_ref(section->mr); | |
1529 | return map->sections_nb++; | |
1530 | } | |
1531 | ||
1532 | static void phys_section_destroy(MemoryRegion *mr) | |
1533 | { | |
1534 | bool have_sub_page = mr->subpage; | |
1535 | ||
1536 | memory_region_unref(mr); | |
1537 | ||
1538 | if (have_sub_page) { | |
1539 | subpage_t *subpage = container_of(mr, subpage_t, iomem); | |
1540 | object_unref(OBJECT(&subpage->iomem)); | |
1541 | g_free(subpage); | |
1542 | } | |
1543 | } | |
1544 | ||
1545 | static void phys_sections_free(PhysPageMap *map) | |
1546 | { | |
1547 | while (map->sections_nb > 0) { | |
1548 | MemoryRegionSection *section = &map->sections[--map->sections_nb]; | |
1549 | phys_section_destroy(section->mr); | |
1550 | } | |
1551 | g_free(map->sections); | |
1552 | g_free(map->nodes); | |
1553 | } | |
1554 | ||
1555 | static void register_subpage(FlatView *fv, MemoryRegionSection *section) | |
1556 | { | |
1557 | AddressSpaceDispatch *d = flatview_to_dispatch(fv); | |
1558 | subpage_t *subpage; | |
1559 | hwaddr base = section->offset_within_address_space | |
1560 | & TARGET_PAGE_MASK; | |
1561 | MemoryRegionSection *existing = phys_page_find(d, base); | |
1562 | MemoryRegionSection subsection = { | |
1563 | .offset_within_address_space = base, | |
1564 | .size = int128_make64(TARGET_PAGE_SIZE), | |
1565 | }; | |
1566 | hwaddr start, end; | |
1567 | ||
1568 | assert(existing->mr->subpage || existing->mr == &io_mem_unassigned); | |
1569 | ||
1570 | if (!(existing->mr->subpage)) { | |
1571 | subpage = subpage_init(fv, base); | |
1572 | subsection.fv = fv; | |
1573 | subsection.mr = &subpage->iomem; | |
1574 | phys_page_set(d, base >> TARGET_PAGE_BITS, 1, | |
1575 | phys_section_add(&d->map, &subsection)); | |
1576 | } else { | |
1577 | subpage = container_of(existing->mr, subpage_t, iomem); | |
1578 | } | |
1579 | start = section->offset_within_address_space & ~TARGET_PAGE_MASK; | |
1580 | end = start + int128_get64(section->size) - 1; | |
1581 | subpage_register(subpage, start, end, | |
1582 | phys_section_add(&d->map, section)); | |
1583 | } | |
1584 | ||
1585 | ||
1586 | static void register_multipage(FlatView *fv, | |
1587 | MemoryRegionSection *section) | |
1588 | { | |
1589 | AddressSpaceDispatch *d = flatview_to_dispatch(fv); | |
1590 | hwaddr start_addr = section->offset_within_address_space; | |
1591 | uint16_t section_index = phys_section_add(&d->map, section); | |
1592 | uint64_t num_pages = int128_get64(int128_rshift(section->size, | |
1593 | TARGET_PAGE_BITS)); | |
1594 | ||
1595 | assert(num_pages); | |
1596 | phys_page_set(d, start_addr >> TARGET_PAGE_BITS, num_pages, section_index); | |
1597 | } | |
1598 | ||
1599 | void flatview_add_to_dispatch(FlatView *fv, MemoryRegionSection *section) | |
1600 | { | |
1601 | MemoryRegionSection now = *section, remain = *section; | |
1602 | Int128 page_size = int128_make64(TARGET_PAGE_SIZE); | |
1603 | ||
1604 | if (now.offset_within_address_space & ~TARGET_PAGE_MASK) { | |
1605 | uint64_t left = TARGET_PAGE_ALIGN(now.offset_within_address_space) | |
1606 | - now.offset_within_address_space; | |
1607 | ||
1608 | now.size = int128_min(int128_make64(left), now.size); | |
1609 | register_subpage(fv, &now); | |
1610 | } else { | |
1611 | now.size = int128_zero(); | |
1612 | } | |
1613 | while (int128_ne(remain.size, now.size)) { | |
1614 | remain.size = int128_sub(remain.size, now.size); | |
1615 | remain.offset_within_address_space += int128_get64(now.size); | |
1616 | remain.offset_within_region += int128_get64(now.size); | |
1617 | now = remain; | |
1618 | if (int128_lt(remain.size, page_size)) { | |
1619 | register_subpage(fv, &now); | |
1620 | } else if (remain.offset_within_address_space & ~TARGET_PAGE_MASK) { | |
1621 | now.size = page_size; | |
1622 | register_subpage(fv, &now); | |
1623 | } else { | |
1624 | now.size = int128_and(now.size, int128_neg(page_size)); | |
1625 | register_multipage(fv, &now); | |
1626 | } | |
1627 | } | |
1628 | } | |
1629 | ||
1630 | void qemu_flush_coalesced_mmio_buffer(void) | |
1631 | { | |
1632 | if (kvm_enabled()) | |
1633 | kvm_flush_coalesced_mmio_buffer(); | |
1634 | } | |
1635 | ||
1636 | void qemu_mutex_lock_ramlist(void) | |
1637 | { | |
1638 | qemu_mutex_lock(&ram_list.mutex); | |
1639 | } | |
1640 | ||
1641 | void qemu_mutex_unlock_ramlist(void) | |
1642 | { | |
1643 | qemu_mutex_unlock(&ram_list.mutex); | |
1644 | } | |
1645 | ||
1646 | void ram_block_dump(Monitor *mon) | |
1647 | { | |
1648 | RAMBlock *block; | |
1649 | char *psize; | |
1650 | ||
1651 | rcu_read_lock(); | |
1652 | monitor_printf(mon, "%24s %8s %18s %18s %18s\n", | |
1653 | "Block Name", "PSize", "Offset", "Used", "Total"); | |
1654 | RAMBLOCK_FOREACH(block) { | |
1655 | psize = size_to_str(block->page_size); | |
1656 | monitor_printf(mon, "%24s %8s 0x%016" PRIx64 " 0x%016" PRIx64 | |
1657 | " 0x%016" PRIx64 "\n", block->idstr, psize, | |
1658 | (uint64_t)block->offset, | |
1659 | (uint64_t)block->used_length, | |
1660 | (uint64_t)block->max_length); | |
1661 | g_free(psize); | |
1662 | } | |
1663 | rcu_read_unlock(); | |
1664 | } | |
1665 | ||
1666 | #ifdef __linux__ | |
1667 | /* | |
1668 | * FIXME TOCTTOU: this iterates over memory backends' mem-path, which | |
1669 | * may or may not name the same files / on the same filesystem now as | |
1670 | * when we actually open and map them. Iterate over the file | |
1671 | * descriptors instead, and use qemu_fd_getpagesize(). | |
1672 | */ | |
1673 | static int find_max_supported_pagesize(Object *obj, void *opaque) | |
1674 | { | |
1675 | long *hpsize_min = opaque; | |
1676 | ||
1677 | if (object_dynamic_cast(obj, TYPE_MEMORY_BACKEND)) { | |
1678 | long hpsize = host_memory_backend_pagesize(MEMORY_BACKEND(obj)); | |
1679 | ||
1680 | if (hpsize < *hpsize_min) { | |
1681 | *hpsize_min = hpsize; | |
1682 | } | |
1683 | } | |
1684 | ||
1685 | return 0; | |
1686 | } | |
1687 | ||
1688 | long qemu_getrampagesize(void) | |
1689 | { | |
1690 | long hpsize = LONG_MAX; | |
1691 | long mainrampagesize; | |
1692 | Object *memdev_root; | |
1693 | ||
1694 | mainrampagesize = qemu_mempath_getpagesize(mem_path); | |
1695 | ||
1696 | /* it's possible we have memory-backend objects with | |
1697 | * hugepage-backed RAM. these may get mapped into system | |
1698 | * address space via -numa parameters or memory hotplug | |
1699 | * hooks. we want to take these into account, but we | |
1700 | * also want to make sure these supported hugepage | |
1701 | * sizes are applicable across the entire range of memory | |
1702 | * we may boot from, so we take the min across all | |
1703 | * backends, and assume normal pages in cases where a | |
1704 | * backend isn't backed by hugepages. | |
1705 | */ | |
1706 | memdev_root = object_resolve_path("/objects", NULL); | |
1707 | if (memdev_root) { | |
1708 | object_child_foreach(memdev_root, find_max_supported_pagesize, &hpsize); | |
1709 | } | |
1710 | if (hpsize == LONG_MAX) { | |
1711 | /* No additional memory regions found ==> Report main RAM page size */ | |
1712 | return mainrampagesize; | |
1713 | } | |
1714 | ||
1715 | /* If NUMA is disabled or the NUMA nodes are not backed with a | |
1716 | * memory-backend, then there is at least one node using "normal" RAM, | |
1717 | * so if its page size is smaller we have got to report that size instead. | |
1718 | */ | |
1719 | if (hpsize > mainrampagesize && | |
1720 | (nb_numa_nodes == 0 || numa_info[0].node_memdev == NULL)) { | |
1721 | static bool warned; | |
1722 | if (!warned) { | |
1723 | error_report("Huge page support disabled (n/a for main memory)."); | |
1724 | warned = true; | |
1725 | } | |
1726 | return mainrampagesize; | |
1727 | } | |
1728 | ||
1729 | return hpsize; | |
1730 | } | |
1731 | #else | |
1732 | long qemu_getrampagesize(void) | |
1733 | { | |
1734 | return getpagesize(); | |
1735 | } | |
1736 | #endif | |
1737 | ||
1738 | #ifdef CONFIG_POSIX | |
1739 | static int64_t get_file_size(int fd) | |
1740 | { | |
1741 | int64_t size = lseek(fd, 0, SEEK_END); | |
1742 | if (size < 0) { | |
1743 | return -errno; | |
1744 | } | |
1745 | return size; | |
1746 | } | |
1747 | ||
1748 | static int file_ram_open(const char *path, | |
1749 | const char *region_name, | |
1750 | bool *created, | |
1751 | Error **errp) | |
1752 | { | |
1753 | char *filename; | |
1754 | char *sanitized_name; | |
1755 | char *c; | |
1756 | int fd = -1; | |
1757 | ||
1758 | *created = false; | |
1759 | for (;;) { | |
1760 | fd = open(path, O_RDWR); | |
1761 | if (fd >= 0) { | |
1762 | /* @path names an existing file, use it */ | |
1763 | break; | |
1764 | } | |
1765 | if (errno == ENOENT) { | |
1766 | /* @path names a file that doesn't exist, create it */ | |
1767 | fd = open(path, O_RDWR | O_CREAT | O_EXCL, 0644); | |
1768 | if (fd >= 0) { | |
1769 | *created = true; | |
1770 | break; | |
1771 | } | |
1772 | } else if (errno == EISDIR) { | |
1773 | /* @path names a directory, create a file there */ | |
1774 | /* Make name safe to use with mkstemp by replacing '/' with '_'. */ | |
1775 | sanitized_name = g_strdup(region_name); | |
1776 | for (c = sanitized_name; *c != '\0'; c++) { | |
1777 | if (*c == '/') { | |
1778 | *c = '_'; | |
1779 | } | |
1780 | } | |
1781 | ||
1782 | filename = g_strdup_printf("%s/qemu_back_mem.%s.XXXXXX", path, | |
1783 | sanitized_name); | |
1784 | g_free(sanitized_name); | |
1785 | ||
1786 | fd = mkstemp(filename); | |
1787 | if (fd >= 0) { | |
1788 | unlink(filename); | |
1789 | g_free(filename); | |
1790 | break; | |
1791 | } | |
1792 | g_free(filename); | |
1793 | } | |
1794 | if (errno != EEXIST && errno != EINTR) { | |
1795 | error_setg_errno(errp, errno, | |
1796 | "can't open backing store %s for guest RAM", | |
1797 | path); | |
1798 | return -1; | |
1799 | } | |
1800 | /* | |
1801 | * Try again on EINTR and EEXIST. The latter happens when | |
1802 | * something else creates the file between our two open(). | |
1803 | */ | |
1804 | } | |
1805 | ||
1806 | return fd; | |
1807 | } | |
1808 | ||
1809 | static void *file_ram_alloc(RAMBlock *block, | |
1810 | ram_addr_t memory, | |
1811 | int fd, | |
1812 | bool truncate, | |
1813 | Error **errp) | |
1814 | { | |
1815 | void *area; | |
1816 | ||
1817 | block->page_size = qemu_fd_getpagesize(fd); | |
1818 | if (block->mr->align % block->page_size) { | |
1819 | error_setg(errp, "alignment 0x%" PRIx64 | |
1820 | " must be multiples of page size 0x%zx", | |
1821 | block->mr->align, block->page_size); | |
1822 | return NULL; | |
1823 | } else if (block->mr->align && !is_power_of_2(block->mr->align)) { | |
1824 | error_setg(errp, "alignment 0x%" PRIx64 | |
1825 | " must be a power of two", block->mr->align); | |
1826 | return NULL; | |
1827 | } | |
1828 | block->mr->align = MAX(block->page_size, block->mr->align); | |
1829 | #if defined(__s390x__) | |
1830 | if (kvm_enabled()) { | |
1831 | block->mr->align = MAX(block->mr->align, QEMU_VMALLOC_ALIGN); | |
1832 | } | |
1833 | #endif | |
1834 | ||
1835 | if (memory < block->page_size) { | |
1836 | error_setg(errp, "memory size 0x" RAM_ADDR_FMT " must be equal to " | |
1837 | "or larger than page size 0x%zx", | |
1838 | memory, block->page_size); | |
1839 | return NULL; | |
1840 | } | |
1841 | ||
1842 | memory = ROUND_UP(memory, block->page_size); | |
1843 | ||
1844 | /* | |
1845 | * ftruncate is not supported by hugetlbfs in older | |
1846 | * hosts, so don't bother bailing out on errors. | |
1847 | * If anything goes wrong with it under other filesystems, | |
1848 | * mmap will fail. | |
1849 | * | |
1850 | * Do not truncate the non-empty backend file to avoid corrupting | |
1851 | * the existing data in the file. Disabling shrinking is not | |
1852 | * enough. For example, the current vNVDIMM implementation stores | |
1853 | * the guest NVDIMM labels at the end of the backend file. If the | |
1854 | * backend file is later extended, QEMU will not be able to find | |
1855 | * those labels. Therefore, extending the non-empty backend file | |
1856 | * is disabled as well. | |
1857 | */ | |
1858 | if (truncate && ftruncate(fd, memory)) { | |
1859 | perror("ftruncate"); | |
1860 | } | |
1861 | ||
1862 | area = qemu_ram_mmap(fd, memory, block->mr->align, | |
1863 | block->flags & RAM_SHARED); | |
1864 | if (area == MAP_FAILED) { | |
1865 | error_setg_errno(errp, errno, | |
1866 | "unable to map backing store for guest RAM"); | |
1867 | return NULL; | |
1868 | } | |
1869 | ||
1870 | if (mem_prealloc) { | |
1871 | os_mem_prealloc(fd, area, memory, smp_cpus, errp); | |
1872 | if (errp && *errp) { | |
1873 | qemu_ram_munmap(area, memory); | |
1874 | return NULL; | |
1875 | } | |
1876 | } | |
1877 | ||
1878 | block->fd = fd; | |
1879 | return area; | |
1880 | } | |
1881 | #endif | |
1882 | ||
1883 | /* Allocate space within the ram_addr_t space that governs the | |
1884 | * dirty bitmaps. | |
1885 | * Called with the ramlist lock held. | |
1886 | */ | |
1887 | static ram_addr_t find_ram_offset(ram_addr_t size) | |
1888 | { | |
1889 | RAMBlock *block, *next_block; | |
1890 | ram_addr_t offset = RAM_ADDR_MAX, mingap = RAM_ADDR_MAX; | |
1891 | ||
1892 | assert(size != 0); /* it would hand out same offset multiple times */ | |
1893 | ||
1894 | if (QLIST_EMPTY_RCU(&ram_list.blocks)) { | |
1895 | return 0; | |
1896 | } | |
1897 | ||
1898 | RAMBLOCK_FOREACH(block) { | |
1899 | ram_addr_t candidate, next = RAM_ADDR_MAX; | |
1900 | ||
1901 | /* Align blocks to start on a 'long' in the bitmap | |
1902 | * which makes the bitmap sync'ing take the fast path. | |
1903 | */ | |
1904 | candidate = block->offset + block->max_length; | |
1905 | candidate = ROUND_UP(candidate, BITS_PER_LONG << TARGET_PAGE_BITS); | |
1906 | ||
1907 | /* Search for the closest following block | |
1908 | * and find the gap. | |
1909 | */ | |
1910 | RAMBLOCK_FOREACH(next_block) { | |
1911 | if (next_block->offset >= candidate) { | |
1912 | next = MIN(next, next_block->offset); | |
1913 | } | |
1914 | } | |
1915 | ||
1916 | /* If it fits remember our place and remember the size | |
1917 | * of gap, but keep going so that we might find a smaller | |
1918 | * gap to fill so avoiding fragmentation. | |
1919 | */ | |
1920 | if (next - candidate >= size && next - candidate < mingap) { | |
1921 | offset = candidate; | |
1922 | mingap = next - candidate; | |
1923 | } | |
1924 | ||
1925 | trace_find_ram_offset_loop(size, candidate, offset, next, mingap); | |
1926 | } | |
1927 | ||
1928 | if (offset == RAM_ADDR_MAX) { | |
1929 | fprintf(stderr, "Failed to find gap of requested size: %" PRIu64 "\n", | |
1930 | (uint64_t)size); | |
1931 | abort(); | |
1932 | } | |
1933 | ||
1934 | trace_find_ram_offset(size, offset); | |
1935 | ||
1936 | return offset; | |
1937 | } | |
1938 | ||
1939 | static unsigned long last_ram_page(void) | |
1940 | { | |
1941 | RAMBlock *block; | |
1942 | ram_addr_t last = 0; | |
1943 | ||
1944 | rcu_read_lock(); | |
1945 | RAMBLOCK_FOREACH(block) { | |
1946 | last = MAX(last, block->offset + block->max_length); | |
1947 | } | |
1948 | rcu_read_unlock(); | |
1949 | return last >> TARGET_PAGE_BITS; | |
1950 | } | |
1951 | ||
1952 | static void qemu_ram_setup_dump(void *addr, ram_addr_t size) | |
1953 | { | |
1954 | int ret; | |
1955 | ||
1956 | /* Use MADV_DONTDUMP, if user doesn't want the guest memory in the core */ | |
1957 | if (!machine_dump_guest_core(current_machine)) { | |
1958 | ret = qemu_madvise(addr, size, QEMU_MADV_DONTDUMP); | |
1959 | if (ret) { | |
1960 | perror("qemu_madvise"); | |
1961 | fprintf(stderr, "madvise doesn't support MADV_DONTDUMP, " | |
1962 | "but dump_guest_core=off specified\n"); | |
1963 | } | |
1964 | } | |
1965 | } | |
1966 | ||
1967 | const char *qemu_ram_get_idstr(RAMBlock *rb) | |
1968 | { | |
1969 | return rb->idstr; | |
1970 | } | |
1971 | ||
1972 | bool qemu_ram_is_shared(RAMBlock *rb) | |
1973 | { | |
1974 | return rb->flags & RAM_SHARED; | |
1975 | } | |
1976 | ||
1977 | /* Note: Only set at the start of postcopy */ | |
1978 | bool qemu_ram_is_uf_zeroable(RAMBlock *rb) | |
1979 | { | |
1980 | return rb->flags & RAM_UF_ZEROPAGE; | |
1981 | } | |
1982 | ||
1983 | void qemu_ram_set_uf_zeroable(RAMBlock *rb) | |
1984 | { | |
1985 | rb->flags |= RAM_UF_ZEROPAGE; | |
1986 | } | |
1987 | ||
1988 | bool qemu_ram_is_migratable(RAMBlock *rb) | |
1989 | { | |
1990 | return rb->flags & RAM_MIGRATABLE; | |
1991 | } | |
1992 | ||
1993 | void qemu_ram_set_migratable(RAMBlock *rb) | |
1994 | { | |
1995 | rb->flags |= RAM_MIGRATABLE; | |
1996 | } | |
1997 | ||
1998 | void qemu_ram_unset_migratable(RAMBlock *rb) | |
1999 | { | |
2000 | rb->flags &= ~RAM_MIGRATABLE; | |
2001 | } | |
2002 | ||
2003 | /* Called with iothread lock held. */ | |
2004 | void qemu_ram_set_idstr(RAMBlock *new_block, const char *name, DeviceState *dev) | |
2005 | { | |
2006 | RAMBlock *block; | |
2007 | ||
2008 | assert(new_block); | |
2009 | assert(!new_block->idstr[0]); | |
2010 | ||
2011 | if (dev) { | |
2012 | char *id = qdev_get_dev_path(dev); | |
2013 | if (id) { | |
2014 | snprintf(new_block->idstr, sizeof(new_block->idstr), "%s/", id); | |
2015 | g_free(id); | |
2016 | } | |
2017 | } | |
2018 | pstrcat(new_block->idstr, sizeof(new_block->idstr), name); | |
2019 | ||
2020 | rcu_read_lock(); | |
2021 | RAMBLOCK_FOREACH(block) { | |
2022 | if (block != new_block && | |
2023 | !strcmp(block->idstr, new_block->idstr)) { | |
2024 | fprintf(stderr, "RAMBlock \"%s\" already registered, abort!\n", | |
2025 | new_block->idstr); | |
2026 | abort(); | |
2027 | } | |
2028 | } | |
2029 | rcu_read_unlock(); | |
2030 | } | |
2031 | ||
2032 | /* Called with iothread lock held. */ | |
2033 | void qemu_ram_unset_idstr(RAMBlock *block) | |
2034 | { | |
2035 | /* FIXME: arch_init.c assumes that this is not called throughout | |
2036 | * migration. Ignore the problem since hot-unplug during migration | |
2037 | * does not work anyway. | |
2038 | */ | |
2039 | if (block) { | |
2040 | memset(block->idstr, 0, sizeof(block->idstr)); | |
2041 | } | |
2042 | } | |
2043 | ||
2044 | size_t qemu_ram_pagesize(RAMBlock *rb) | |
2045 | { | |
2046 | return rb->page_size; | |
2047 | } | |
2048 | ||
2049 | /* Returns the largest size of page in use */ | |
2050 | size_t qemu_ram_pagesize_largest(void) | |
2051 | { | |
2052 | RAMBlock *block; | |
2053 | size_t largest = 0; | |
2054 | ||
2055 | RAMBLOCK_FOREACH(block) { | |
2056 | largest = MAX(largest, qemu_ram_pagesize(block)); | |
2057 | } | |
2058 | ||
2059 | return largest; | |
2060 | } | |
2061 | ||
2062 | static int memory_try_enable_merging(void *addr, size_t len) | |
2063 | { | |
2064 | if (!machine_mem_merge(current_machine)) { | |
2065 | /* disabled by the user */ | |
2066 | return 0; | |
2067 | } | |
2068 | ||
2069 | return qemu_madvise(addr, len, QEMU_MADV_MERGEABLE); | |
2070 | } | |
2071 | ||
2072 | /* Only legal before guest might have detected the memory size: e.g. on | |
2073 | * incoming migration, or right after reset. | |
2074 | * | |
2075 | * As memory core doesn't know how is memory accessed, it is up to | |
2076 | * resize callback to update device state and/or add assertions to detect | |
2077 | * misuse, if necessary. | |
2078 | */ | |
2079 | int qemu_ram_resize(RAMBlock *block, ram_addr_t newsize, Error **errp) | |
2080 | { | |
2081 | assert(block); | |
2082 | ||
2083 | newsize = HOST_PAGE_ALIGN(newsize); | |
2084 | ||
2085 | if (block->used_length == newsize) { | |
2086 | return 0; | |
2087 | } | |
2088 | ||
2089 | if (!(block->flags & RAM_RESIZEABLE)) { | |
2090 | error_setg_errno(errp, EINVAL, | |
2091 | "Length mismatch: %s: 0x" RAM_ADDR_FMT | |
2092 | " in != 0x" RAM_ADDR_FMT, block->idstr, | |
2093 | newsize, block->used_length); | |
2094 | return -EINVAL; | |
2095 | } | |
2096 | ||
2097 | if (block->max_length < newsize) { | |
2098 | error_setg_errno(errp, EINVAL, | |
2099 | "Length too large: %s: 0x" RAM_ADDR_FMT | |
2100 | " > 0x" RAM_ADDR_FMT, block->idstr, | |
2101 | newsize, block->max_length); | |
2102 | return -EINVAL; | |
2103 | } | |
2104 | ||
2105 | cpu_physical_memory_clear_dirty_range(block->offset, block->used_length); | |
2106 | block->used_length = newsize; | |
2107 | cpu_physical_memory_set_dirty_range(block->offset, block->used_length, | |
2108 | DIRTY_CLIENTS_ALL); | |
2109 | memory_region_set_size(block->mr, newsize); | |
2110 | if (block->resized) { | |
2111 | block->resized(block->idstr, newsize, block->host); | |
2112 | } | |
2113 | return 0; | |
2114 | } | |
2115 | ||
2116 | /* Called with ram_list.mutex held */ | |
2117 | static void dirty_memory_extend(ram_addr_t old_ram_size, | |
2118 | ram_addr_t new_ram_size) | |
2119 | { | |
2120 | ram_addr_t old_num_blocks = DIV_ROUND_UP(old_ram_size, | |
2121 | DIRTY_MEMORY_BLOCK_SIZE); | |
2122 | ram_addr_t new_num_blocks = DIV_ROUND_UP(new_ram_size, | |
2123 | DIRTY_MEMORY_BLOCK_SIZE); | |
2124 | int i; | |
2125 | ||
2126 | /* Only need to extend if block count increased */ | |
2127 | if (new_num_blocks <= old_num_blocks) { | |
2128 | return; | |
2129 | } | |
2130 | ||
2131 | for (i = 0; i < DIRTY_MEMORY_NUM; i++) { | |
2132 | DirtyMemoryBlocks *old_blocks; | |
2133 | DirtyMemoryBlocks *new_blocks; | |
2134 | int j; | |
2135 | ||
2136 | old_blocks = atomic_rcu_read(&ram_list.dirty_memory[i]); | |
2137 | new_blocks = g_malloc(sizeof(*new_blocks) + | |
2138 | sizeof(new_blocks->blocks[0]) * new_num_blocks); | |
2139 | ||
2140 | if (old_num_blocks) { | |
2141 | memcpy(new_blocks->blocks, old_blocks->blocks, | |
2142 | old_num_blocks * sizeof(old_blocks->blocks[0])); | |
2143 | } | |
2144 | ||
2145 | for (j = old_num_blocks; j < new_num_blocks; j++) { | |
2146 | new_blocks->blocks[j] = bitmap_new(DIRTY_MEMORY_BLOCK_SIZE); | |
2147 | } | |
2148 | ||
2149 | atomic_rcu_set(&ram_list.dirty_memory[i], new_blocks); | |
2150 | ||
2151 | if (old_blocks) { | |
2152 | g_free_rcu(old_blocks, rcu); | |
2153 | } | |
2154 | } | |
2155 | } | |
2156 | ||
2157 | static void ram_block_add(RAMBlock *new_block, Error **errp, bool shared) | |
2158 | { | |
2159 | RAMBlock *block; | |
2160 | RAMBlock *last_block = NULL; | |
2161 | ram_addr_t old_ram_size, new_ram_size; | |
2162 | Error *err = NULL; | |
2163 | ||
2164 | old_ram_size = last_ram_page(); | |
2165 | ||
2166 | qemu_mutex_lock_ramlist(); | |
2167 | new_block->offset = find_ram_offset(new_block->max_length); | |
2168 | ||
2169 | if (!new_block->host) { | |
2170 | if (xen_enabled()) { | |
2171 | xen_ram_alloc(new_block->offset, new_block->max_length, | |
2172 | new_block->mr, &err); | |
2173 | if (err) { | |
2174 | error_propagate(errp, err); | |
2175 | qemu_mutex_unlock_ramlist(); | |
2176 | return; | |
2177 | } | |
2178 | } else { | |
2179 | new_block->host = phys_mem_alloc(new_block->max_length, | |
2180 | &new_block->mr->align, shared); | |
2181 | if (!new_block->host) { | |
2182 | error_setg_errno(errp, errno, | |
2183 | "cannot set up guest memory '%s'", | |
2184 | memory_region_name(new_block->mr)); | |
2185 | qemu_mutex_unlock_ramlist(); | |
2186 | return; | |
2187 | } | |
2188 | memory_try_enable_merging(new_block->host, new_block->max_length); | |
2189 | } | |
2190 | } | |
2191 | ||
2192 | new_ram_size = MAX(old_ram_size, | |
2193 | (new_block->offset + new_block->max_length) >> TARGET_PAGE_BITS); | |
2194 | if (new_ram_size > old_ram_size) { | |
2195 | dirty_memory_extend(old_ram_size, new_ram_size); | |
2196 | } | |
2197 | /* Keep the list sorted from biggest to smallest block. Unlike QTAILQ, | |
2198 | * QLIST (which has an RCU-friendly variant) does not have insertion at | |
2199 | * tail, so save the last element in last_block. | |
2200 | */ | |
2201 | RAMBLOCK_FOREACH(block) { | |
2202 | last_block = block; | |
2203 | if (block->max_length < new_block->max_length) { | |
2204 | break; | |
2205 | } | |
2206 | } | |
2207 | if (block) { | |
2208 | QLIST_INSERT_BEFORE_RCU(block, new_block, next); | |
2209 | } else if (last_block) { | |
2210 | QLIST_INSERT_AFTER_RCU(last_block, new_block, next); | |
2211 | } else { /* list is empty */ | |
2212 | QLIST_INSERT_HEAD_RCU(&ram_list.blocks, new_block, next); | |
2213 | } | |
2214 | ram_list.mru_block = NULL; | |
2215 | ||
2216 | /* Write list before version */ | |
2217 | smp_wmb(); | |
2218 | ram_list.version++; | |
2219 | qemu_mutex_unlock_ramlist(); | |
2220 | ||
2221 | cpu_physical_memory_set_dirty_range(new_block->offset, | |
2222 | new_block->used_length, | |
2223 | DIRTY_CLIENTS_ALL); | |
2224 | ||
2225 | if (new_block->host) { | |
2226 | qemu_ram_setup_dump(new_block->host, new_block->max_length); | |
2227 | qemu_madvise(new_block->host, new_block->max_length, QEMU_MADV_HUGEPAGE); | |
2228 | /* MADV_DONTFORK is also needed by KVM in absence of synchronous MMU */ | |
2229 | qemu_madvise(new_block->host, new_block->max_length, QEMU_MADV_DONTFORK); | |
2230 | ram_block_notify_add(new_block->host, new_block->max_length); | |
2231 | } | |
2232 | } | |
2233 | ||
2234 | #ifdef CONFIG_POSIX | |
2235 | RAMBlock *qemu_ram_alloc_from_fd(ram_addr_t size, MemoryRegion *mr, | |
2236 | uint32_t ram_flags, int fd, | |
2237 | Error **errp) | |
2238 | { | |
2239 | RAMBlock *new_block; | |
2240 | Error *local_err = NULL; | |
2241 | int64_t file_size; | |
2242 | ||
2243 | /* Just support these ram flags by now. */ | |
2244 | assert((ram_flags & ~(RAM_SHARED | RAM_PMEM)) == 0); | |
2245 | ||
2246 | if (xen_enabled()) { | |
2247 | error_setg(errp, "-mem-path not supported with Xen"); | |
2248 | return NULL; | |
2249 | } | |
2250 | ||
2251 | if (kvm_enabled() && !kvm_has_sync_mmu()) { | |
2252 | error_setg(errp, | |
2253 | "host lacks kvm mmu notifiers, -mem-path unsupported"); | |
2254 | return NULL; | |
2255 | } | |
2256 | ||
2257 | if (phys_mem_alloc != qemu_anon_ram_alloc) { | |
2258 | /* | |
2259 | * file_ram_alloc() needs to allocate just like | |
2260 | * phys_mem_alloc, but we haven't bothered to provide | |
2261 | * a hook there. | |
2262 | */ | |
2263 | error_setg(errp, | |
2264 | "-mem-path not supported with this accelerator"); | |
2265 | return NULL; | |
2266 | } | |
2267 | ||
2268 | size = HOST_PAGE_ALIGN(size); | |
2269 | file_size = get_file_size(fd); | |
2270 | if (file_size > 0 && file_size < size) { | |
2271 | error_setg(errp, "backing store %s size 0x%" PRIx64 | |
2272 | " does not match 'size' option 0x" RAM_ADDR_FMT, | |
2273 | mem_path, file_size, size); | |
2274 | return NULL; | |
2275 | } | |
2276 | ||
2277 | new_block = g_malloc0(sizeof(*new_block)); | |
2278 | new_block->mr = mr; | |
2279 | new_block->used_length = size; | |
2280 | new_block->max_length = size; | |
2281 | new_block->flags = ram_flags; | |
2282 | new_block->host = file_ram_alloc(new_block, size, fd, !file_size, errp); | |
2283 | if (!new_block->host) { | |
2284 | g_free(new_block); | |
2285 | return NULL; | |
2286 | } | |
2287 | ||
2288 | ram_block_add(new_block, &local_err, ram_flags & RAM_SHARED); | |
2289 | if (local_err) { | |
2290 | g_free(new_block); | |
2291 | error_propagate(errp, local_err); | |
2292 | return NULL; | |
2293 | } | |
2294 | return new_block; | |
2295 | ||
2296 | } | |
2297 | ||
2298 | ||
2299 | RAMBlock *qemu_ram_alloc_from_file(ram_addr_t size, MemoryRegion *mr, | |
2300 | uint32_t ram_flags, const char *mem_path, | |
2301 | Error **errp) | |
2302 | { | |
2303 | int fd; | |
2304 | bool created; | |
2305 | RAMBlock *block; | |
2306 | ||
2307 | fd = file_ram_open(mem_path, memory_region_name(mr), &created, errp); | |
2308 | if (fd < 0) { | |
2309 | return NULL; | |
2310 | } | |
2311 | ||
2312 | block = qemu_ram_alloc_from_fd(size, mr, ram_flags, fd, errp); | |
2313 | if (!block) { | |
2314 | if (created) { | |
2315 | unlink(mem_path); | |
2316 | } | |
2317 | close(fd); | |
2318 | return NULL; | |
2319 | } | |
2320 | ||
2321 | return block; | |
2322 | } | |
2323 | #endif | |
2324 | ||
2325 | static | |
2326 | RAMBlock *qemu_ram_alloc_internal(ram_addr_t size, ram_addr_t max_size, | |
2327 | void (*resized)(const char*, | |
2328 | uint64_t length, | |
2329 | void *host), | |
2330 | void *host, bool resizeable, bool share, | |
2331 | MemoryRegion *mr, Error **errp) | |
2332 | { | |
2333 | RAMBlock *new_block; | |
2334 | Error *local_err = NULL; | |
2335 | ||
2336 | size = HOST_PAGE_ALIGN(size); | |
2337 | max_size = HOST_PAGE_ALIGN(max_size); | |
2338 | new_block = g_malloc0(sizeof(*new_block)); | |
2339 | new_block->mr = mr; | |
2340 | new_block->resized = resized; | |
2341 | new_block->used_length = size; | |
2342 | new_block->max_length = max_size; | |
2343 | assert(max_size >= size); | |
2344 | new_block->fd = -1; | |
2345 | new_block->page_size = getpagesize(); | |
2346 | new_block->host = host; | |
2347 | if (host) { | |
2348 | new_block->flags |= RAM_PREALLOC; | |
2349 | } | |
2350 | if (resizeable) { | |
2351 | new_block->flags |= RAM_RESIZEABLE; | |
2352 | } | |
2353 | ram_block_add(new_block, &local_err, share); | |
2354 | if (local_err) { | |
2355 | g_free(new_block); | |
2356 | error_propagate(errp, local_err); | |
2357 | return NULL; | |
2358 | } | |
2359 | return new_block; | |
2360 | } | |
2361 | ||
2362 | RAMBlock *qemu_ram_alloc_from_ptr(ram_addr_t size, void *host, | |
2363 | MemoryRegion *mr, Error **errp) | |
2364 | { | |
2365 | return qemu_ram_alloc_internal(size, size, NULL, host, false, | |
2366 | false, mr, errp); | |
2367 | } | |
2368 | ||
2369 | RAMBlock *qemu_ram_alloc(ram_addr_t size, bool share, | |
2370 | MemoryRegion *mr, Error **errp) | |
2371 | { | |
2372 | return qemu_ram_alloc_internal(size, size, NULL, NULL, false, | |
2373 | share, mr, errp); | |
2374 | } | |
2375 | ||
2376 | RAMBlock *qemu_ram_alloc_resizeable(ram_addr_t size, ram_addr_t maxsz, | |
2377 | void (*resized)(const char*, | |
2378 | uint64_t length, | |
2379 | void *host), | |
2380 | MemoryRegion *mr, Error **errp) | |
2381 | { | |
2382 | return qemu_ram_alloc_internal(size, maxsz, resized, NULL, true, | |
2383 | false, mr, errp); | |
2384 | } | |
2385 | ||
2386 | static void reclaim_ramblock(RAMBlock *block) | |
2387 | { | |
2388 | if (block->flags & RAM_PREALLOC) { | |
2389 | ; | |
2390 | } else if (xen_enabled()) { | |
2391 | xen_invalidate_map_cache_entry(block->host); | |
2392 | #ifndef _WIN32 | |
2393 | } else if (block->fd >= 0) { | |
2394 | qemu_ram_munmap(block->host, block->max_length); | |
2395 | close(block->fd); | |
2396 | #endif | |
2397 | } else { | |
2398 | qemu_anon_ram_free(block->host, block->max_length); | |
2399 | } | |
2400 | g_free(block); | |
2401 | } | |
2402 | ||
2403 | void qemu_ram_free(RAMBlock *block) | |
2404 | { | |
2405 | if (!block) { | |
2406 | return; | |
2407 | } | |
2408 | ||
2409 | if (block->host) { | |
2410 | ram_block_notify_remove(block->host, block->max_length); | |
2411 | } | |
2412 | ||
2413 | qemu_mutex_lock_ramlist(); | |
2414 | QLIST_REMOVE_RCU(block, next); | |
2415 | ram_list.mru_block = NULL; | |
2416 | /* Write list before version */ | |
2417 | smp_wmb(); | |
2418 | ram_list.version++; | |
2419 | call_rcu(block, reclaim_ramblock, rcu); | |
2420 | qemu_mutex_unlock_ramlist(); | |
2421 | } | |
2422 | ||
2423 | #ifndef _WIN32 | |
2424 | void qemu_ram_remap(ram_addr_t addr, ram_addr_t length) | |
2425 | { | |
2426 | RAMBlock *block; | |
2427 | ram_addr_t offset; | |
2428 | int flags; | |
2429 | void *area, *vaddr; | |
2430 | ||
2431 | RAMBLOCK_FOREACH(block) { | |
2432 | offset = addr - block->offset; | |
2433 | if (offset < block->max_length) { | |
2434 | vaddr = ramblock_ptr(block, offset); | |
2435 | if (block->flags & RAM_PREALLOC) { | |
2436 | ; | |
2437 | } else if (xen_enabled()) { | |
2438 | abort(); | |
2439 | } else { | |
2440 | flags = MAP_FIXED; | |
2441 | if (block->fd >= 0) { | |
2442 | flags |= (block->flags & RAM_SHARED ? | |
2443 | MAP_SHARED : MAP_PRIVATE); | |
2444 | area = mmap(vaddr, length, PROT_READ | PROT_WRITE, | |
2445 | flags, block->fd, offset); | |
2446 | } else { | |
2447 | /* | |
2448 | * Remap needs to match alloc. Accelerators that | |
2449 | * set phys_mem_alloc never remap. If they did, | |
2450 | * we'd need a remap hook here. | |
2451 | */ | |
2452 | assert(phys_mem_alloc == qemu_anon_ram_alloc); | |
2453 | ||
2454 | flags |= MAP_PRIVATE | MAP_ANONYMOUS; | |
2455 | area = mmap(vaddr, length, PROT_READ | PROT_WRITE, | |
2456 | flags, -1, 0); | |
2457 | } | |
2458 | if (area != vaddr) { | |
2459 | error_report("Could not remap addr: " | |
2460 | RAM_ADDR_FMT "@" RAM_ADDR_FMT "", | |
2461 | length, addr); | |
2462 | exit(1); | |
2463 | } | |
2464 | memory_try_enable_merging(vaddr, length); | |
2465 | qemu_ram_setup_dump(vaddr, length); | |
2466 | } | |
2467 | } | |
2468 | } | |
2469 | } | |
2470 | #endif /* !_WIN32 */ | |
2471 | ||
2472 | /* Return a host pointer to ram allocated with qemu_ram_alloc. | |
2473 | * This should not be used for general purpose DMA. Use address_space_map | |
2474 | * or address_space_rw instead. For local memory (e.g. video ram) that the | |
2475 | * device owns, use memory_region_get_ram_ptr. | |
2476 | * | |
2477 | * Called within RCU critical section. | |
2478 | */ | |
2479 | void *qemu_map_ram_ptr(RAMBlock *ram_block, ram_addr_t addr) | |
2480 | { | |
2481 | RAMBlock *block = ram_block; | |
2482 | ||
2483 | if (block == NULL) { | |
2484 | block = qemu_get_ram_block(addr); | |
2485 | addr -= block->offset; | |
2486 | } | |
2487 | ||
2488 | if (xen_enabled() && block->host == NULL) { | |
2489 | /* We need to check if the requested address is in the RAM | |
2490 | * because we don't want to map the entire memory in QEMU. | |
2491 | * In that case just map until the end of the page. | |
2492 | */ | |
2493 | if (block->offset == 0) { | |
2494 | return xen_map_cache(addr, 0, 0, false); | |
2495 | } | |
2496 | ||
2497 | block->host = xen_map_cache(block->offset, block->max_length, 1, false); | |
2498 | } | |
2499 | return ramblock_ptr(block, addr); | |
2500 | } | |
2501 | ||
2502 | /* Return a host pointer to guest's ram. Similar to qemu_map_ram_ptr | |
2503 | * but takes a size argument. | |
2504 | * | |
2505 | * Called within RCU critical section. | |
2506 | */ | |
2507 | static void *qemu_ram_ptr_length(RAMBlock *ram_block, ram_addr_t addr, | |
2508 | hwaddr *size, bool lock) | |
2509 | { | |
2510 | RAMBlock *block = ram_block; | |
2511 | if (*size == 0) { | |
2512 | return NULL; | |
2513 | } | |
2514 | ||
2515 | if (block == NULL) { | |
2516 | block = qemu_get_ram_block(addr); | |
2517 | addr -= block->offset; | |
2518 | } | |
2519 | *size = MIN(*size, block->max_length - addr); | |
2520 | ||
2521 | if (xen_enabled() && block->host == NULL) { | |
2522 | /* We need to check if the requested address is in the RAM | |
2523 | * because we don't want to map the entire memory in QEMU. | |
2524 | * In that case just map the requested area. | |
2525 | */ | |
2526 | if (block->offset == 0) { | |
2527 | return xen_map_cache(addr, *size, lock, lock); | |
2528 | } | |
2529 | ||
2530 | block->host = xen_map_cache(block->offset, block->max_length, 1, lock); | |
2531 | } | |
2532 | ||
2533 | return ramblock_ptr(block, addr); | |
2534 | } | |
2535 | ||
2536 | /* Return the offset of a hostpointer within a ramblock */ | |
2537 | ram_addr_t qemu_ram_block_host_offset(RAMBlock *rb, void *host) | |
2538 | { | |
2539 | ram_addr_t res = (uint8_t *)host - (uint8_t *)rb->host; | |
2540 | assert((uintptr_t)host >= (uintptr_t)rb->host); | |
2541 | assert(res < rb->max_length); | |
2542 | ||
2543 | return res; | |
2544 | } | |
2545 | ||
2546 | /* | |
2547 | * Translates a host ptr back to a RAMBlock, a ram_addr and an offset | |
2548 | * in that RAMBlock. | |
2549 | * | |
2550 | * ptr: Host pointer to look up | |
2551 | * round_offset: If true round the result offset down to a page boundary | |
2552 | * *ram_addr: set to result ram_addr | |
2553 | * *offset: set to result offset within the RAMBlock | |
2554 | * | |
2555 | * Returns: RAMBlock (or NULL if not found) | |
2556 | * | |
2557 | * By the time this function returns, the returned pointer is not protected | |
2558 | * by RCU anymore. If the caller is not within an RCU critical section and | |
2559 | * does not hold the iothread lock, it must have other means of protecting the | |
2560 | * pointer, such as a reference to the region that includes the incoming | |
2561 | * ram_addr_t. | |
2562 | */ | |
2563 | RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset, | |
2564 | ram_addr_t *offset) | |
2565 | { | |
2566 | RAMBlock *block; | |
2567 | uint8_t *host = ptr; | |
2568 | ||
2569 | if (xen_enabled()) { | |
2570 | ram_addr_t ram_addr; | |
2571 | rcu_read_lock(); | |
2572 | ram_addr = xen_ram_addr_from_mapcache(ptr); | |
2573 | block = qemu_get_ram_block(ram_addr); | |
2574 | if (block) { | |
2575 | *offset = ram_addr - block->offset; | |
2576 | } | |
2577 | rcu_read_unlock(); | |
2578 | return block; | |
2579 | } | |
2580 | ||
2581 | rcu_read_lock(); | |
2582 | block = atomic_rcu_read(&ram_list.mru_block); | |
2583 | if (block && block->host && host - block->host < block->max_length) { | |
2584 | goto found; | |
2585 | } | |
2586 | ||
2587 | RAMBLOCK_FOREACH(block) { | |
2588 | /* This case append when the block is not mapped. */ | |
2589 | if (block->host == NULL) { | |
2590 | continue; | |
2591 | } | |
2592 | if (host - block->host < block->max_length) { | |
2593 | goto found; | |
2594 | } | |
2595 | } | |
2596 | ||
2597 | rcu_read_unlock(); | |
2598 | return NULL; | |
2599 | ||
2600 | found: | |
2601 | *offset = (host - block->host); | |
2602 | if (round_offset) { | |
2603 | *offset &= TARGET_PAGE_MASK; | |
2604 | } | |
2605 | rcu_read_unlock(); | |
2606 | return block; | |
2607 | } | |
2608 | ||
2609 | /* | |
2610 | * Finds the named RAMBlock | |
2611 | * | |
2612 | * name: The name of RAMBlock to find | |
2613 | * | |
2614 | * Returns: RAMBlock (or NULL if not found) | |
2615 | */ | |
2616 | RAMBlock *qemu_ram_block_by_name(const char *name) | |
2617 | { | |
2618 | RAMBlock *block; | |
2619 | ||
2620 | RAMBLOCK_FOREACH(block) { | |
2621 | if (!strcmp(name, block->idstr)) { | |
2622 | return block; | |
2623 | } | |
2624 | } | |
2625 | ||
2626 | return NULL; | |
2627 | } | |
2628 | ||
2629 | /* Some of the softmmu routines need to translate from a host pointer | |
2630 | (typically a TLB entry) back to a ram offset. */ | |
2631 | ram_addr_t qemu_ram_addr_from_host(void *ptr) | |
2632 | { | |
2633 | RAMBlock *block; | |
2634 | ram_addr_t offset; | |
2635 | ||
2636 | block = qemu_ram_block_from_host(ptr, false, &offset); | |
2637 | if (!block) { | |
2638 | return RAM_ADDR_INVALID; | |
2639 | } | |
2640 | ||
2641 | return block->offset + offset; | |
2642 | } | |
2643 | ||
2644 | /* Called within RCU critical section. */ | |
2645 | void memory_notdirty_write_prepare(NotDirtyInfo *ndi, | |
2646 | CPUState *cpu, | |
2647 | vaddr mem_vaddr, | |
2648 | ram_addr_t ram_addr, | |
2649 | unsigned size) | |
2650 | { | |
2651 | ndi->cpu = cpu; | |
2652 | ndi->ram_addr = ram_addr; | |
2653 | ndi->mem_vaddr = mem_vaddr; | |
2654 | ndi->size = size; | |
2655 | ndi->pages = NULL; | |
2656 | ||
2657 | assert(tcg_enabled()); | |
2658 | if (!cpu_physical_memory_get_dirty_flag(ram_addr, DIRTY_MEMORY_CODE)) { | |
2659 | ndi->pages = page_collection_lock(ram_addr, ram_addr + size); | |
2660 | tb_invalidate_phys_page_fast(ndi->pages, ram_addr, size); | |
2661 | } | |
2662 | } | |
2663 | ||
2664 | /* Called within RCU critical section. */ | |
2665 | void memory_notdirty_write_complete(NotDirtyInfo *ndi) | |
2666 | { | |
2667 | if (ndi->pages) { | |
2668 | assert(tcg_enabled()); | |
2669 | page_collection_unlock(ndi->pages); | |
2670 | ndi->pages = NULL; | |
2671 | } | |
2672 | ||
2673 | /* Set both VGA and migration bits for simplicity and to remove | |
2674 | * the notdirty callback faster. | |
2675 | */ | |
2676 | cpu_physical_memory_set_dirty_range(ndi->ram_addr, ndi->size, | |
2677 | DIRTY_CLIENTS_NOCODE); | |
2678 | /* we remove the notdirty callback only if the code has been | |
2679 | flushed */ | |
2680 | if (!cpu_physical_memory_is_clean(ndi->ram_addr)) { | |
2681 | tlb_set_dirty(ndi->cpu, ndi->mem_vaddr); | |
2682 | } | |
2683 | } | |
2684 | ||
2685 | /* Called within RCU critical section. */ | |
2686 | static void notdirty_mem_write(void *opaque, hwaddr ram_addr, | |
2687 | uint64_t val, unsigned size) | |
2688 | { | |
2689 | NotDirtyInfo ndi; | |
2690 | ||
2691 | memory_notdirty_write_prepare(&ndi, current_cpu, current_cpu->mem_io_vaddr, | |
2692 | ram_addr, size); | |
2693 | ||
2694 | stn_p(qemu_map_ram_ptr(NULL, ram_addr), size, val); | |
2695 | memory_notdirty_write_complete(&ndi); | |
2696 | } | |
2697 | ||
2698 | static bool notdirty_mem_accepts(void *opaque, hwaddr addr, | |
2699 | unsigned size, bool is_write, | |
2700 | MemTxAttrs attrs) | |
2701 | { | |
2702 | return is_write; | |
2703 | } | |
2704 | ||
2705 | static const MemoryRegionOps notdirty_mem_ops = { | |
2706 | .write = notdirty_mem_write, | |
2707 | .valid.accepts = notdirty_mem_accepts, | |
2708 | .endianness = DEVICE_NATIVE_ENDIAN, | |
2709 | .valid = { | |
2710 | .min_access_size = 1, | |
2711 | .max_access_size = 8, | |
2712 | .unaligned = false, | |
2713 | }, | |
2714 | .impl = { | |
2715 | .min_access_size = 1, | |
2716 | .max_access_size = 8, | |
2717 | .unaligned = false, | |
2718 | }, | |
2719 | }; | |
2720 | ||
2721 | /* Generate a debug exception if a watchpoint has been hit. */ | |
2722 | static void check_watchpoint(int offset, int len, MemTxAttrs attrs, int flags) | |
2723 | { | |
2724 | CPUState *cpu = current_cpu; | |
2725 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
2726 | target_ulong vaddr; | |
2727 | CPUWatchpoint *wp; | |
2728 | ||
2729 | assert(tcg_enabled()); | |
2730 | if (cpu->watchpoint_hit) { | |
2731 | /* We re-entered the check after replacing the TB. Now raise | |
2732 | * the debug interrupt so that is will trigger after the | |
2733 | * current instruction. */ | |
2734 | cpu_interrupt(cpu, CPU_INTERRUPT_DEBUG); | |
2735 | return; | |
2736 | } | |
2737 | vaddr = (cpu->mem_io_vaddr & TARGET_PAGE_MASK) + offset; | |
2738 | vaddr = cc->adjust_watchpoint_address(cpu, vaddr, len); | |
2739 | QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { | |
2740 | if (cpu_watchpoint_address_matches(wp, vaddr, len) | |
2741 | && (wp->flags & flags)) { | |
2742 | if (flags == BP_MEM_READ) { | |
2743 | wp->flags |= BP_WATCHPOINT_HIT_READ; | |
2744 | } else { | |
2745 | wp->flags |= BP_WATCHPOINT_HIT_WRITE; | |
2746 | } | |
2747 | wp->hitaddr = vaddr; | |
2748 | wp->hitattrs = attrs; | |
2749 | if (!cpu->watchpoint_hit) { | |
2750 | if (wp->flags & BP_CPU && | |
2751 | !cc->debug_check_watchpoint(cpu, wp)) { | |
2752 | wp->flags &= ~BP_WATCHPOINT_HIT; | |
2753 | continue; | |
2754 | } | |
2755 | cpu->watchpoint_hit = wp; | |
2756 | ||
2757 | mmap_lock(); | |
2758 | tb_check_watchpoint(cpu); | |
2759 | if (wp->flags & BP_STOP_BEFORE_ACCESS) { | |
2760 | cpu->exception_index = EXCP_DEBUG; | |
2761 | mmap_unlock(); | |
2762 | cpu_loop_exit(cpu); | |
2763 | } else { | |
2764 | /* Force execution of one insn next time. */ | |
2765 | cpu->cflags_next_tb = 1 | curr_cflags(); | |
2766 | mmap_unlock(); | |
2767 | cpu_loop_exit_noexc(cpu); | |
2768 | } | |
2769 | } | |
2770 | } else { | |
2771 | wp->flags &= ~BP_WATCHPOINT_HIT; | |
2772 | } | |
2773 | } | |
2774 | } | |
2775 | ||
2776 | /* Watchpoint access routines. Watchpoints are inserted using TLB tricks, | |
2777 | so these check for a hit then pass through to the normal out-of-line | |
2778 | phys routines. */ | |
2779 | static MemTxResult watch_mem_read(void *opaque, hwaddr addr, uint64_t *pdata, | |
2780 | unsigned size, MemTxAttrs attrs) | |
2781 | { | |
2782 | MemTxResult res; | |
2783 | uint64_t data; | |
2784 | int asidx = cpu_asidx_from_attrs(current_cpu, attrs); | |
2785 | AddressSpace *as = current_cpu->cpu_ases[asidx].as; | |
2786 | ||
2787 | check_watchpoint(addr & ~TARGET_PAGE_MASK, size, attrs, BP_MEM_READ); | |
2788 | switch (size) { | |
2789 | case 1: | |
2790 | data = address_space_ldub(as, addr, attrs, &res); | |
2791 | break; | |
2792 | case 2: | |
2793 | data = address_space_lduw(as, addr, attrs, &res); | |
2794 | break; | |
2795 | case 4: | |
2796 | data = address_space_ldl(as, addr, attrs, &res); | |
2797 | break; | |
2798 | case 8: | |
2799 | data = address_space_ldq(as, addr, attrs, &res); | |
2800 | break; | |
2801 | default: abort(); | |
2802 | } | |
2803 | *pdata = data; | |
2804 | return res; | |
2805 | } | |
2806 | ||
2807 | static MemTxResult watch_mem_write(void *opaque, hwaddr addr, | |
2808 | uint64_t val, unsigned size, | |
2809 | MemTxAttrs attrs) | |
2810 | { | |
2811 | MemTxResult res; | |
2812 | int asidx = cpu_asidx_from_attrs(current_cpu, attrs); | |
2813 | AddressSpace *as = current_cpu->cpu_ases[asidx].as; | |
2814 | ||
2815 | check_watchpoint(addr & ~TARGET_PAGE_MASK, size, attrs, BP_MEM_WRITE); | |
2816 | switch (size) { | |
2817 | case 1: | |
2818 | address_space_stb(as, addr, val, attrs, &res); | |
2819 | break; | |
2820 | case 2: | |
2821 | address_space_stw(as, addr, val, attrs, &res); | |
2822 | break; | |
2823 | case 4: | |
2824 | address_space_stl(as, addr, val, attrs, &res); | |
2825 | break; | |
2826 | case 8: | |
2827 | address_space_stq(as, addr, val, attrs, &res); | |
2828 | break; | |
2829 | default: abort(); | |
2830 | } | |
2831 | return res; | |
2832 | } | |
2833 | ||
2834 | static const MemoryRegionOps watch_mem_ops = { | |
2835 | .read_with_attrs = watch_mem_read, | |
2836 | .write_with_attrs = watch_mem_write, | |
2837 | .endianness = DEVICE_NATIVE_ENDIAN, | |
2838 | .valid = { | |
2839 | .min_access_size = 1, | |
2840 | .max_access_size = 8, | |
2841 | .unaligned = false, | |
2842 | }, | |
2843 | .impl = { | |
2844 | .min_access_size = 1, | |
2845 | .max_access_size = 8, | |
2846 | .unaligned = false, | |
2847 | }, | |
2848 | }; | |
2849 | ||
2850 | static MemTxResult flatview_read(FlatView *fv, hwaddr addr, | |
2851 | MemTxAttrs attrs, uint8_t *buf, int len); | |
2852 | static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs, | |
2853 | const uint8_t *buf, int len); | |
2854 | static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len, | |
2855 | bool is_write, MemTxAttrs attrs); | |
2856 | ||
2857 | static MemTxResult subpage_read(void *opaque, hwaddr addr, uint64_t *data, | |
2858 | unsigned len, MemTxAttrs attrs) | |
2859 | { | |
2860 | subpage_t *subpage = opaque; | |
2861 | uint8_t buf[8]; | |
2862 | MemTxResult res; | |
2863 | ||
2864 | #if defined(DEBUG_SUBPAGE) | |
2865 | printf("%s: subpage %p len %u addr " TARGET_FMT_plx "\n", __func__, | |
2866 | subpage, len, addr); | |
2867 | #endif | |
2868 | res = flatview_read(subpage->fv, addr + subpage->base, attrs, buf, len); | |
2869 | if (res) { | |
2870 | return res; | |
2871 | } | |
2872 | *data = ldn_p(buf, len); | |
2873 | return MEMTX_OK; | |
2874 | } | |
2875 | ||
2876 | static MemTxResult subpage_write(void *opaque, hwaddr addr, | |
2877 | uint64_t value, unsigned len, MemTxAttrs attrs) | |
2878 | { | |
2879 | subpage_t *subpage = opaque; | |
2880 | uint8_t buf[8]; | |
2881 | ||
2882 | #if defined(DEBUG_SUBPAGE) | |
2883 | printf("%s: subpage %p len %u addr " TARGET_FMT_plx | |
2884 | " value %"PRIx64"\n", | |
2885 | __func__, subpage, len, addr, value); | |
2886 | #endif | |
2887 | stn_p(buf, len, value); | |
2888 | return flatview_write(subpage->fv, addr + subpage->base, attrs, buf, len); | |
2889 | } | |
2890 | ||
2891 | static bool subpage_accepts(void *opaque, hwaddr addr, | |
2892 | unsigned len, bool is_write, | |
2893 | MemTxAttrs attrs) | |
2894 | { | |
2895 | subpage_t *subpage = opaque; | |
2896 | #if defined(DEBUG_SUBPAGE) | |
2897 | printf("%s: subpage %p %c len %u addr " TARGET_FMT_plx "\n", | |
2898 | __func__, subpage, is_write ? 'w' : 'r', len, addr); | |
2899 | #endif | |
2900 | ||
2901 | return flatview_access_valid(subpage->fv, addr + subpage->base, | |
2902 | len, is_write, attrs); | |
2903 | } | |
2904 | ||
2905 | static const MemoryRegionOps subpage_ops = { | |
2906 | .read_with_attrs = subpage_read, | |
2907 | .write_with_attrs = subpage_write, | |
2908 | .impl.min_access_size = 1, | |
2909 | .impl.max_access_size = 8, | |
2910 | .valid.min_access_size = 1, | |
2911 | .valid.max_access_size = 8, | |
2912 | .valid.accepts = subpage_accepts, | |
2913 | .endianness = DEVICE_NATIVE_ENDIAN, | |
2914 | }; | |
2915 | ||
2916 | static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, | |
2917 | uint16_t section) | |
2918 | { | |
2919 | int idx, eidx; | |
2920 | ||
2921 | if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE) | |
2922 | return -1; | |
2923 | idx = SUBPAGE_IDX(start); | |
2924 | eidx = SUBPAGE_IDX(end); | |
2925 | #if defined(DEBUG_SUBPAGE) | |
2926 | printf("%s: %p start %08x end %08x idx %08x eidx %08x section %d\n", | |
2927 | __func__, mmio, start, end, idx, eidx, section); | |
2928 | #endif | |
2929 | for (; idx <= eidx; idx++) { | |
2930 | mmio->sub_section[idx] = section; | |
2931 | } | |
2932 | ||
2933 | return 0; | |
2934 | } | |
2935 | ||
2936 | static subpage_t *subpage_init(FlatView *fv, hwaddr base) | |
2937 | { | |
2938 | subpage_t *mmio; | |
2939 | ||
2940 | mmio = g_malloc0(sizeof(subpage_t) + TARGET_PAGE_SIZE * sizeof(uint16_t)); | |
2941 | mmio->fv = fv; | |
2942 | mmio->base = base; | |
2943 | memory_region_init_io(&mmio->iomem, NULL, &subpage_ops, mmio, | |
2944 | NULL, TARGET_PAGE_SIZE); | |
2945 | mmio->iomem.subpage = true; | |
2946 | #if defined(DEBUG_SUBPAGE) | |
2947 | printf("%s: %p base " TARGET_FMT_plx " len %08x\n", __func__, | |
2948 | mmio, base, TARGET_PAGE_SIZE); | |
2949 | #endif | |
2950 | subpage_register(mmio, 0, TARGET_PAGE_SIZE-1, PHYS_SECTION_UNASSIGNED); | |
2951 | ||
2952 | return mmio; | |
2953 | } | |
2954 | ||
2955 | static uint16_t dummy_section(PhysPageMap *map, FlatView *fv, MemoryRegion *mr) | |
2956 | { | |
2957 | assert(fv); | |
2958 | MemoryRegionSection section = { | |
2959 | .fv = fv, | |
2960 | .mr = mr, | |
2961 | .offset_within_address_space = 0, | |
2962 | .offset_within_region = 0, | |
2963 | .size = int128_2_64(), | |
2964 | }; | |
2965 | ||
2966 | return phys_section_add(map, §ion); | |
2967 | } | |
2968 | ||
2969 | static void readonly_mem_write(void *opaque, hwaddr addr, | |
2970 | uint64_t val, unsigned size) | |
2971 | { | |
2972 | /* Ignore any write to ROM. */ | |
2973 | } | |
2974 | ||
2975 | static bool readonly_mem_accepts(void *opaque, hwaddr addr, | |
2976 | unsigned size, bool is_write, | |
2977 | MemTxAttrs attrs) | |
2978 | { | |
2979 | return is_write; | |
2980 | } | |
2981 | ||
2982 | /* This will only be used for writes, because reads are special cased | |
2983 | * to directly access the underlying host ram. | |
2984 | */ | |
2985 | static const MemoryRegionOps readonly_mem_ops = { | |
2986 | .write = readonly_mem_write, | |
2987 | .valid.accepts = readonly_mem_accepts, | |
2988 | .endianness = DEVICE_NATIVE_ENDIAN, | |
2989 | .valid = { | |
2990 | .min_access_size = 1, | |
2991 | .max_access_size = 8, | |
2992 | .unaligned = false, | |
2993 | }, | |
2994 | .impl = { | |
2995 | .min_access_size = 1, | |
2996 | .max_access_size = 8, | |
2997 | .unaligned = false, | |
2998 | }, | |
2999 | }; | |
3000 | ||
3001 | MemoryRegionSection *iotlb_to_section(CPUState *cpu, | |
3002 | hwaddr index, MemTxAttrs attrs) | |
3003 | { | |
3004 | int asidx = cpu_asidx_from_attrs(cpu, attrs); | |
3005 | CPUAddressSpace *cpuas = &cpu->cpu_ases[asidx]; | |
3006 | AddressSpaceDispatch *d = atomic_rcu_read(&cpuas->memory_dispatch); | |
3007 | MemoryRegionSection *sections = d->map.sections; | |
3008 | ||
3009 | return §ions[index & ~TARGET_PAGE_MASK]; | |
3010 | } | |
3011 | ||
3012 | static void io_mem_init(void) | |
3013 | { | |
3014 | memory_region_init_io(&io_mem_rom, NULL, &readonly_mem_ops, | |
3015 | NULL, NULL, UINT64_MAX); | |
3016 | memory_region_init_io(&io_mem_unassigned, NULL, &unassigned_mem_ops, NULL, | |
3017 | NULL, UINT64_MAX); | |
3018 | ||
3019 | /* io_mem_notdirty calls tb_invalidate_phys_page_fast, | |
3020 | * which can be called without the iothread mutex. | |
3021 | */ | |
3022 | memory_region_init_io(&io_mem_notdirty, NULL, ¬dirty_mem_ops, NULL, | |
3023 | NULL, UINT64_MAX); | |
3024 | memory_region_clear_global_locking(&io_mem_notdirty); | |
3025 | ||
3026 | memory_region_init_io(&io_mem_watch, NULL, &watch_mem_ops, NULL, | |
3027 | NULL, UINT64_MAX); | |
3028 | } | |
3029 | ||
3030 | AddressSpaceDispatch *address_space_dispatch_new(FlatView *fv) | |
3031 | { | |
3032 | AddressSpaceDispatch *d = g_new0(AddressSpaceDispatch, 1); | |
3033 | uint16_t n; | |
3034 | ||
3035 | n = dummy_section(&d->map, fv, &io_mem_unassigned); | |
3036 | assert(n == PHYS_SECTION_UNASSIGNED); | |
3037 | n = dummy_section(&d->map, fv, &io_mem_notdirty); | |
3038 | assert(n == PHYS_SECTION_NOTDIRTY); | |
3039 | n = dummy_section(&d->map, fv, &io_mem_rom); | |
3040 | assert(n == PHYS_SECTION_ROM); | |
3041 | n = dummy_section(&d->map, fv, &io_mem_watch); | |
3042 | assert(n == PHYS_SECTION_WATCH); | |
3043 | ||
3044 | d->phys_map = (PhysPageEntry) { .ptr = PHYS_MAP_NODE_NIL, .skip = 1 }; | |
3045 | ||
3046 | return d; | |
3047 | } | |
3048 | ||
3049 | void address_space_dispatch_free(AddressSpaceDispatch *d) | |
3050 | { | |
3051 | phys_sections_free(&d->map); | |
3052 | g_free(d); | |
3053 | } | |
3054 | ||
3055 | static void tcg_commit(MemoryListener *listener) | |
3056 | { | |
3057 | CPUAddressSpace *cpuas; | |
3058 | AddressSpaceDispatch *d; | |
3059 | ||
3060 | assert(tcg_enabled()); | |
3061 | /* since each CPU stores ram addresses in its TLB cache, we must | |
3062 | reset the modified entries */ | |
3063 | cpuas = container_of(listener, CPUAddressSpace, tcg_as_listener); | |
3064 | cpu_reloading_memory_map(); | |
3065 | /* The CPU and TLB are protected by the iothread lock. | |
3066 | * We reload the dispatch pointer now because cpu_reloading_memory_map() | |
3067 | * may have split the RCU critical section. | |
3068 | */ | |
3069 | d = address_space_to_dispatch(cpuas->as); | |
3070 | atomic_rcu_set(&cpuas->memory_dispatch, d); | |
3071 | tlb_flush(cpuas->cpu); | |
3072 | } | |
3073 | ||
3074 | static void memory_map_init(void) | |
3075 | { | |
3076 | system_memory = g_malloc(sizeof(*system_memory)); | |
3077 | ||
3078 | memory_region_init(system_memory, NULL, "system", UINT64_MAX); | |
3079 | address_space_init(&address_space_memory, system_memory, "memory"); | |
3080 | ||
3081 | system_io = g_malloc(sizeof(*system_io)); | |
3082 | memory_region_init_io(system_io, NULL, &unassigned_io_ops, NULL, "io", | |
3083 | 65536); | |
3084 | address_space_init(&address_space_io, system_io, "I/O"); | |
3085 | } | |
3086 | ||
3087 | MemoryRegion *get_system_memory(void) | |
3088 | { | |
3089 | return system_memory; | |
3090 | } | |
3091 | ||
3092 | MemoryRegion *get_system_io(void) | |
3093 | { | |
3094 | return system_io; | |
3095 | } | |
3096 | ||
3097 | #endif /* !defined(CONFIG_USER_ONLY) */ | |
3098 | ||
3099 | /* physical memory access (slow version, mainly for debug) */ | |
3100 | #if defined(CONFIG_USER_ONLY) | |
3101 | int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, | |
3102 | uint8_t *buf, int len, int is_write) | |
3103 | { | |
3104 | int l, flags; | |
3105 | target_ulong page; | |
3106 | void * p; | |
3107 | ||
3108 | while (len > 0) { | |
3109 | page = addr & TARGET_PAGE_MASK; | |
3110 | l = (page + TARGET_PAGE_SIZE) - addr; | |
3111 | if (l > len) | |
3112 | l = len; | |
3113 | flags = page_get_flags(page); | |
3114 | if (!(flags & PAGE_VALID)) | |
3115 | return -1; | |
3116 | if (is_write) { | |
3117 | if (!(flags & PAGE_WRITE)) | |
3118 | return -1; | |
3119 | /* XXX: this code should not depend on lock_user */ | |
3120 | if (!(p = lock_user(VERIFY_WRITE, addr, l, 0))) | |
3121 | return -1; | |
3122 | memcpy(p, buf, l); | |
3123 | unlock_user(p, addr, l); | |
3124 | } else { | |
3125 | if (!(flags & PAGE_READ)) | |
3126 | return -1; | |
3127 | /* XXX: this code should not depend on lock_user */ | |
3128 | if (!(p = lock_user(VERIFY_READ, addr, l, 1))) | |
3129 | return -1; | |
3130 | memcpy(buf, p, l); | |
3131 | unlock_user(p, addr, 0); | |
3132 | } | |
3133 | len -= l; | |
3134 | buf += l; | |
3135 | addr += l; | |
3136 | } | |
3137 | return 0; | |
3138 | } | |
3139 | ||
3140 | #else | |
3141 | ||
3142 | static void invalidate_and_set_dirty(MemoryRegion *mr, hwaddr addr, | |
3143 | hwaddr length) | |
3144 | { | |
3145 | uint8_t dirty_log_mask = memory_region_get_dirty_log_mask(mr); | |
3146 | addr += memory_region_get_ram_addr(mr); | |
3147 | ||
3148 | /* No early return if dirty_log_mask is or becomes 0, because | |
3149 | * cpu_physical_memory_set_dirty_range will still call | |
3150 | * xen_modified_memory. | |
3151 | */ | |
3152 | if (dirty_log_mask) { | |
3153 | dirty_log_mask = | |
3154 | cpu_physical_memory_range_includes_clean(addr, length, dirty_log_mask); | |
3155 | } | |
3156 | if (dirty_log_mask & (1 << DIRTY_MEMORY_CODE)) { | |
3157 | assert(tcg_enabled()); | |
3158 | tb_invalidate_phys_range(addr, addr + length); | |
3159 | dirty_log_mask &= ~(1 << DIRTY_MEMORY_CODE); | |
3160 | } | |
3161 | cpu_physical_memory_set_dirty_range(addr, length, dirty_log_mask); | |
3162 | } | |
3163 | ||
3164 | static int memory_access_size(MemoryRegion *mr, unsigned l, hwaddr addr) | |
3165 | { | |
3166 | unsigned access_size_max = mr->ops->valid.max_access_size; | |
3167 | ||
3168 | /* Regions are assumed to support 1-4 byte accesses unless | |
3169 | otherwise specified. */ | |
3170 | if (access_size_max == 0) { | |
3171 | access_size_max = 4; | |
3172 | } | |
3173 | ||
3174 | /* Bound the maximum access by the alignment of the address. */ | |
3175 | if (!mr->ops->impl.unaligned) { | |
3176 | unsigned align_size_max = addr & -addr; | |
3177 | if (align_size_max != 0 && align_size_max < access_size_max) { | |
3178 | access_size_max = align_size_max; | |
3179 | } | |
3180 | } | |
3181 | ||
3182 | /* Don't attempt accesses larger than the maximum. */ | |
3183 | if (l > access_size_max) { | |
3184 | l = access_size_max; | |
3185 | } | |
3186 | l = pow2floor(l); | |
3187 | ||
3188 | return l; | |
3189 | } | |
3190 | ||
3191 | static bool prepare_mmio_access(MemoryRegion *mr) | |
3192 | { | |
3193 | bool unlocked = !qemu_mutex_iothread_locked(); | |
3194 | bool release_lock = false; | |
3195 | ||
3196 | if (unlocked && mr->global_locking) { | |
3197 | qemu_mutex_lock_iothread(); | |
3198 | unlocked = false; | |
3199 | release_lock = true; | |
3200 | } | |
3201 | if (mr->flush_coalesced_mmio) { | |
3202 | if (unlocked) { | |
3203 | qemu_mutex_lock_iothread(); | |
3204 | } | |
3205 | qemu_flush_coalesced_mmio_buffer(); | |
3206 | if (unlocked) { | |
3207 | qemu_mutex_unlock_iothread(); | |
3208 | } | |
3209 | } | |
3210 | ||
3211 | return release_lock; | |
3212 | } | |
3213 | ||
3214 | /* Called within RCU critical section. */ | |
3215 | static MemTxResult flatview_write_continue(FlatView *fv, hwaddr addr, | |
3216 | MemTxAttrs attrs, | |
3217 | const uint8_t *buf, | |
3218 | int len, hwaddr addr1, | |
3219 | hwaddr l, MemoryRegion *mr) | |
3220 | { | |
3221 | uint8_t *ptr; | |
3222 | uint64_t val; | |
3223 | MemTxResult result = MEMTX_OK; | |
3224 | bool release_lock = false; | |
3225 | ||
3226 | for (;;) { | |
3227 | if (!memory_access_is_direct(mr, true)) { | |
3228 | release_lock |= prepare_mmio_access(mr); | |
3229 | l = memory_access_size(mr, l, addr1); | |
3230 | /* XXX: could force current_cpu to NULL to avoid | |
3231 | potential bugs */ | |
3232 | val = ldn_p(buf, l); | |
3233 | result |= memory_region_dispatch_write(mr, addr1, val, l, attrs); | |
3234 | } else { | |
3235 | /* RAM case */ | |
3236 | ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false); | |
3237 | memcpy(ptr, buf, l); | |
3238 | invalidate_and_set_dirty(mr, addr1, l); | |
3239 | } | |
3240 | ||
3241 | if (release_lock) { | |
3242 | qemu_mutex_unlock_iothread(); | |
3243 | release_lock = false; | |
3244 | } | |
3245 | ||
3246 | len -= l; | |
3247 | buf += l; | |
3248 | addr += l; | |
3249 | ||
3250 | if (!len) { | |
3251 | break; | |
3252 | } | |
3253 | ||
3254 | l = len; | |
3255 | mr = flatview_translate(fv, addr, &addr1, &l, true, attrs); | |
3256 | } | |
3257 | ||
3258 | return result; | |
3259 | } | |
3260 | ||
3261 | /* Called from RCU critical section. */ | |
3262 | static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs, | |
3263 | const uint8_t *buf, int len) | |
3264 | { | |
3265 | hwaddr l; | |
3266 | hwaddr addr1; | |
3267 | MemoryRegion *mr; | |
3268 | MemTxResult result = MEMTX_OK; | |
3269 | ||
3270 | l = len; | |
3271 | mr = flatview_translate(fv, addr, &addr1, &l, true, attrs); | |
3272 | result = flatview_write_continue(fv, addr, attrs, buf, len, | |
3273 | addr1, l, mr); | |
3274 | ||
3275 | return result; | |
3276 | } | |
3277 | ||
3278 | /* Called within RCU critical section. */ | |
3279 | MemTxResult flatview_read_continue(FlatView *fv, hwaddr addr, | |
3280 | MemTxAttrs attrs, uint8_t *buf, | |
3281 | int len, hwaddr addr1, hwaddr l, | |
3282 | MemoryRegion *mr) | |
3283 | { | |
3284 | uint8_t *ptr; | |
3285 | uint64_t val; | |
3286 | MemTxResult result = MEMTX_OK; | |
3287 | bool release_lock = false; | |
3288 | ||
3289 | for (;;) { | |
3290 | if (!memory_access_is_direct(mr, false)) { | |
3291 | /* I/O case */ | |
3292 | release_lock |= prepare_mmio_access(mr); | |
3293 | l = memory_access_size(mr, l, addr1); | |
3294 | result |= memory_region_dispatch_read(mr, addr1, &val, l, attrs); | |
3295 | stn_p(buf, l, val); | |
3296 | } else { | |
3297 | /* RAM case */ | |
3298 | ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false); | |
3299 | memcpy(buf, ptr, l); | |
3300 | } | |
3301 | ||
3302 | if (release_lock) { | |
3303 | qemu_mutex_unlock_iothread(); | |
3304 | release_lock = false; | |
3305 | } | |
3306 | ||
3307 | len -= l; | |
3308 | buf += l; | |
3309 | addr += l; | |
3310 | ||
3311 | if (!len) { | |
3312 | break; | |
3313 | } | |
3314 | ||
3315 | l = len; | |
3316 | mr = flatview_translate(fv, addr, &addr1, &l, false, attrs); | |
3317 | } | |
3318 | ||
3319 | return result; | |
3320 | } | |
3321 | ||
3322 | /* Called from RCU critical section. */ | |
3323 | static MemTxResult flatview_read(FlatView *fv, hwaddr addr, | |
3324 | MemTxAttrs attrs, uint8_t *buf, int len) | |
3325 | { | |
3326 | hwaddr l; | |
3327 | hwaddr addr1; | |
3328 | MemoryRegion *mr; | |
3329 | ||
3330 | l = len; | |
3331 | mr = flatview_translate(fv, addr, &addr1, &l, false, attrs); | |
3332 | return flatview_read_continue(fv, addr, attrs, buf, len, | |
3333 | addr1, l, mr); | |
3334 | } | |
3335 | ||
3336 | MemTxResult address_space_read_full(AddressSpace *as, hwaddr addr, | |
3337 | MemTxAttrs attrs, uint8_t *buf, int len) | |
3338 | { | |
3339 | MemTxResult result = MEMTX_OK; | |
3340 | FlatView *fv; | |
3341 | ||
3342 | if (len > 0) { | |
3343 | rcu_read_lock(); | |
3344 | fv = address_space_to_flatview(as); | |
3345 | result = flatview_read(fv, addr, attrs, buf, len); | |
3346 | rcu_read_unlock(); | |
3347 | } | |
3348 | ||
3349 | return result; | |
3350 | } | |
3351 | ||
3352 | MemTxResult address_space_write(AddressSpace *as, hwaddr addr, | |
3353 | MemTxAttrs attrs, | |
3354 | const uint8_t *buf, int len) | |
3355 | { | |
3356 | MemTxResult result = MEMTX_OK; | |
3357 | FlatView *fv; | |
3358 | ||
3359 | if (len > 0) { | |
3360 | rcu_read_lock(); | |
3361 | fv = address_space_to_flatview(as); | |
3362 | result = flatview_write(fv, addr, attrs, buf, len); | |
3363 | rcu_read_unlock(); | |
3364 | } | |
3365 | ||
3366 | return result; | |
3367 | } | |
3368 | ||
3369 | MemTxResult address_space_rw(AddressSpace *as, hwaddr addr, MemTxAttrs attrs, | |
3370 | uint8_t *buf, int len, bool is_write) | |
3371 | { | |
3372 | if (is_write) { | |
3373 | return address_space_write(as, addr, attrs, buf, len); | |
3374 | } else { | |
3375 | return address_space_read_full(as, addr, attrs, buf, len); | |
3376 | } | |
3377 | } | |
3378 | ||
3379 | void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf, | |
3380 | int len, int is_write) | |
3381 | { | |
3382 | address_space_rw(&address_space_memory, addr, MEMTXATTRS_UNSPECIFIED, | |
3383 | buf, len, is_write); | |
3384 | } | |
3385 | ||
3386 | enum write_rom_type { | |
3387 | WRITE_DATA, | |
3388 | FLUSH_CACHE, | |
3389 | }; | |
3390 | ||
3391 | static inline void cpu_physical_memory_write_rom_internal(AddressSpace *as, | |
3392 | hwaddr addr, const uint8_t *buf, int len, enum write_rom_type type) | |
3393 | { | |
3394 | hwaddr l; | |
3395 | uint8_t *ptr; | |
3396 | hwaddr addr1; | |
3397 | MemoryRegion *mr; | |
3398 | ||
3399 | rcu_read_lock(); | |
3400 | while (len > 0) { | |
3401 | l = len; | |
3402 | mr = address_space_translate(as, addr, &addr1, &l, true, | |
3403 | MEMTXATTRS_UNSPECIFIED); | |
3404 | ||
3405 | if (!(memory_region_is_ram(mr) || | |
3406 | memory_region_is_romd(mr))) { | |
3407 | l = memory_access_size(mr, l, addr1); | |
3408 | } else { | |
3409 | /* ROM/RAM case */ | |
3410 | ptr = qemu_map_ram_ptr(mr->ram_block, addr1); | |
3411 | switch (type) { | |
3412 | case WRITE_DATA: | |
3413 | memcpy(ptr, buf, l); | |
3414 | invalidate_and_set_dirty(mr, addr1, l); | |
3415 | break; | |
3416 | case FLUSH_CACHE: | |
3417 | flush_icache_range((uintptr_t)ptr, (uintptr_t)ptr + l); | |
3418 | break; | |
3419 | } | |
3420 | } | |
3421 | len -= l; | |
3422 | buf += l; | |
3423 | addr += l; | |
3424 | } | |
3425 | rcu_read_unlock(); | |
3426 | } | |
3427 | ||
3428 | /* used for ROM loading : can write in RAM and ROM */ | |
3429 | void cpu_physical_memory_write_rom(AddressSpace *as, hwaddr addr, | |
3430 | const uint8_t *buf, int len) | |
3431 | { | |
3432 | cpu_physical_memory_write_rom_internal(as, addr, buf, len, WRITE_DATA); | |
3433 | } | |
3434 | ||
3435 | void cpu_flush_icache_range(hwaddr start, int len) | |
3436 | { | |
3437 | /* | |
3438 | * This function should do the same thing as an icache flush that was | |
3439 | * triggered from within the guest. For TCG we are always cache coherent, | |
3440 | * so there is no need to flush anything. For KVM / Xen we need to flush | |
3441 | * the host's instruction cache at least. | |
3442 | */ | |
3443 | if (tcg_enabled()) { | |
3444 | return; | |
3445 | } | |
3446 | ||
3447 | cpu_physical_memory_write_rom_internal(&address_space_memory, | |
3448 | start, NULL, len, FLUSH_CACHE); | |
3449 | } | |
3450 | ||
3451 | typedef struct { | |
3452 | MemoryRegion *mr; | |
3453 | void *buffer; | |
3454 | hwaddr addr; | |
3455 | hwaddr len; | |
3456 | bool in_use; | |
3457 | } BounceBuffer; | |
3458 | ||
3459 | static BounceBuffer bounce; | |
3460 | ||
3461 | typedef struct MapClient { | |
3462 | QEMUBH *bh; | |
3463 | QLIST_ENTRY(MapClient) link; | |
3464 | } MapClient; | |
3465 | ||
3466 | QemuMutex map_client_list_lock; | |
3467 | static QLIST_HEAD(map_client_list, MapClient) map_client_list | |
3468 | = QLIST_HEAD_INITIALIZER(map_client_list); | |
3469 | ||
3470 | static void cpu_unregister_map_client_do(MapClient *client) | |
3471 | { | |
3472 | QLIST_REMOVE(client, link); | |
3473 | g_free(client); | |
3474 | } | |
3475 | ||
3476 | static void cpu_notify_map_clients_locked(void) | |
3477 | { | |
3478 | MapClient *client; | |
3479 | ||
3480 | while (!QLIST_EMPTY(&map_client_list)) { | |
3481 | client = QLIST_FIRST(&map_client_list); | |
3482 | qemu_bh_schedule(client->bh); | |
3483 | cpu_unregister_map_client_do(client); | |
3484 | } | |
3485 | } | |
3486 | ||
3487 | void cpu_register_map_client(QEMUBH *bh) | |
3488 | { | |
3489 | MapClient *client = g_malloc(sizeof(*client)); | |
3490 | ||
3491 | qemu_mutex_lock(&map_client_list_lock); | |
3492 | client->bh = bh; | |
3493 | QLIST_INSERT_HEAD(&map_client_list, client, link); | |
3494 | if (!atomic_read(&bounce.in_use)) { | |
3495 | cpu_notify_map_clients_locked(); | |
3496 | } | |
3497 | qemu_mutex_unlock(&map_client_list_lock); | |
3498 | } | |
3499 | ||
3500 | void cpu_exec_init_all(void) | |
3501 | { | |
3502 | qemu_mutex_init(&ram_list.mutex); | |
3503 | /* The data structures we set up here depend on knowing the page size, | |
3504 | * so no more changes can be made after this point. | |
3505 | * In an ideal world, nothing we did before we had finished the | |
3506 | * machine setup would care about the target page size, and we could | |
3507 | * do this much later, rather than requiring board models to state | |
3508 | * up front what their requirements are. | |
3509 | */ | |
3510 | finalize_target_page_bits(); | |
3511 | io_mem_init(); | |
3512 | memory_map_init(); | |
3513 | qemu_mutex_init(&map_client_list_lock); | |
3514 | } | |
3515 | ||
3516 | void cpu_unregister_map_client(QEMUBH *bh) | |
3517 | { | |
3518 | MapClient *client; | |
3519 | ||
3520 | qemu_mutex_lock(&map_client_list_lock); | |
3521 | QLIST_FOREACH(client, &map_client_list, link) { | |
3522 | if (client->bh == bh) { | |
3523 | cpu_unregister_map_client_do(client); | |
3524 | break; | |
3525 | } | |
3526 | } | |
3527 | qemu_mutex_unlock(&map_client_list_lock); | |
3528 | } | |
3529 | ||
3530 | static void cpu_notify_map_clients(void) | |
3531 | { | |
3532 | qemu_mutex_lock(&map_client_list_lock); | |
3533 | cpu_notify_map_clients_locked(); | |
3534 | qemu_mutex_unlock(&map_client_list_lock); | |
3535 | } | |
3536 | ||
3537 | static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len, | |
3538 | bool is_write, MemTxAttrs attrs) | |
3539 | { | |
3540 | MemoryRegion *mr; | |
3541 | hwaddr l, xlat; | |
3542 | ||
3543 | while (len > 0) { | |
3544 | l = len; | |
3545 | mr = flatview_translate(fv, addr, &xlat, &l, is_write, attrs); | |
3546 | if (!memory_access_is_direct(mr, is_write)) { | |
3547 | l = memory_access_size(mr, l, addr); | |
3548 | if (!memory_region_access_valid(mr, xlat, l, is_write, attrs)) { | |
3549 | return false; | |
3550 | } | |
3551 | } | |
3552 | ||
3553 | len -= l; | |
3554 | addr += l; | |
3555 | } | |
3556 | return true; | |
3557 | } | |
3558 | ||
3559 | bool address_space_access_valid(AddressSpace *as, hwaddr addr, | |
3560 | int len, bool is_write, | |
3561 | MemTxAttrs attrs) | |
3562 | { | |
3563 | FlatView *fv; | |
3564 | bool result; | |
3565 | ||
3566 | rcu_read_lock(); | |
3567 | fv = address_space_to_flatview(as); | |
3568 | result = flatview_access_valid(fv, addr, len, is_write, attrs); | |
3569 | rcu_read_unlock(); | |
3570 | return result; | |
3571 | } | |
3572 | ||
3573 | static hwaddr | |
3574 | flatview_extend_translation(FlatView *fv, hwaddr addr, | |
3575 | hwaddr target_len, | |
3576 | MemoryRegion *mr, hwaddr base, hwaddr len, | |
3577 | bool is_write, MemTxAttrs attrs) | |
3578 | { | |
3579 | hwaddr done = 0; | |
3580 | hwaddr xlat; | |
3581 | MemoryRegion *this_mr; | |
3582 | ||
3583 | for (;;) { | |
3584 | target_len -= len; | |
3585 | addr += len; | |
3586 | done += len; | |
3587 | if (target_len == 0) { | |
3588 | return done; | |
3589 | } | |
3590 | ||
3591 | len = target_len; | |
3592 | this_mr = flatview_translate(fv, addr, &xlat, | |
3593 | &len, is_write, attrs); | |
3594 | if (this_mr != mr || xlat != base + done) { | |
3595 | return done; | |
3596 | } | |
3597 | } | |
3598 | } | |
3599 | ||
3600 | /* Map a physical memory region into a host virtual address. | |
3601 | * May map a subset of the requested range, given by and returned in *plen. | |
3602 | * May return NULL if resources needed to perform the mapping are exhausted. | |
3603 | * Use only for reads OR writes - not for read-modify-write operations. | |
3604 | * Use cpu_register_map_client() to know when retrying the map operation is | |
3605 | * likely to succeed. | |
3606 | */ | |
3607 | void *address_space_map(AddressSpace *as, | |
3608 | hwaddr addr, | |
3609 | hwaddr *plen, | |
3610 | bool is_write, | |
3611 | MemTxAttrs attrs) | |
3612 | { | |
3613 | hwaddr len = *plen; | |
3614 | hwaddr l, xlat; | |
3615 | MemoryRegion *mr; | |
3616 | void *ptr; | |
3617 | FlatView *fv; | |
3618 | ||
3619 | if (len == 0) { | |
3620 | return NULL; | |
3621 | } | |
3622 | ||
3623 | l = len; | |
3624 | rcu_read_lock(); | |
3625 | fv = address_space_to_flatview(as); | |
3626 | mr = flatview_translate(fv, addr, &xlat, &l, is_write, attrs); | |
3627 | ||
3628 | if (!memory_access_is_direct(mr, is_write)) { | |
3629 | if (atomic_xchg(&bounce.in_use, true)) { | |
3630 | rcu_read_unlock(); | |
3631 | return NULL; | |
3632 | } | |
3633 | /* Avoid unbounded allocations */ | |
3634 | l = MIN(l, TARGET_PAGE_SIZE); | |
3635 | bounce.buffer = qemu_memalign(TARGET_PAGE_SIZE, l); | |
3636 | bounce.addr = addr; | |
3637 | bounce.len = l; | |
3638 | ||
3639 | memory_region_ref(mr); | |
3640 | bounce.mr = mr; | |
3641 | if (!is_write) { | |
3642 | flatview_read(fv, addr, MEMTXATTRS_UNSPECIFIED, | |
3643 | bounce.buffer, l); | |
3644 | } | |
3645 | ||
3646 | rcu_read_unlock(); | |
3647 | *plen = l; | |
3648 | return bounce.buffer; | |
3649 | } | |
3650 | ||
3651 | ||
3652 | memory_region_ref(mr); | |
3653 | *plen = flatview_extend_translation(fv, addr, len, mr, xlat, | |
3654 | l, is_write, attrs); | |
3655 | ptr = qemu_ram_ptr_length(mr->ram_block, xlat, plen, true); | |
3656 | rcu_read_unlock(); | |
3657 | ||
3658 | return ptr; | |
3659 | } | |
3660 | ||
3661 | /* Unmaps a memory region previously mapped by address_space_map(). | |
3662 | * Will also mark the memory as dirty if is_write == 1. access_len gives | |
3663 | * the amount of memory that was actually read or written by the caller. | |
3664 | */ | |
3665 | void address_space_unmap(AddressSpace *as, void *buffer, hwaddr len, | |
3666 | int is_write, hwaddr access_len) | |
3667 | { | |
3668 | if (buffer != bounce.buffer) { | |
3669 | MemoryRegion *mr; | |
3670 | ram_addr_t addr1; | |
3671 | ||
3672 | mr = memory_region_from_host(buffer, &addr1); | |
3673 | assert(mr != NULL); | |
3674 | if (is_write) { | |
3675 | invalidate_and_set_dirty(mr, addr1, access_len); | |
3676 | } | |
3677 | if (xen_enabled()) { | |
3678 | xen_invalidate_map_cache_entry(buffer); | |
3679 | } | |
3680 | memory_region_unref(mr); | |
3681 | return; | |
3682 | } | |
3683 | if (is_write) { | |
3684 | address_space_write(as, bounce.addr, MEMTXATTRS_UNSPECIFIED, | |
3685 | bounce.buffer, access_len); | |
3686 | } | |
3687 | qemu_vfree(bounce.buffer); | |
3688 | bounce.buffer = NULL; | |
3689 | memory_region_unref(bounce.mr); | |
3690 | atomic_mb_set(&bounce.in_use, false); | |
3691 | cpu_notify_map_clients(); | |
3692 | } | |
3693 | ||
3694 | void *cpu_physical_memory_map(hwaddr addr, | |
3695 | hwaddr *plen, | |
3696 | int is_write) | |
3697 | { | |
3698 | return address_space_map(&address_space_memory, addr, plen, is_write, | |
3699 | MEMTXATTRS_UNSPECIFIED); | |
3700 | } | |
3701 | ||
3702 | void cpu_physical_memory_unmap(void *buffer, hwaddr len, | |
3703 | int is_write, hwaddr access_len) | |
3704 | { | |
3705 | return address_space_unmap(&address_space_memory, buffer, len, is_write, access_len); | |
3706 | } | |
3707 | ||
3708 | #define ARG1_DECL AddressSpace *as | |
3709 | #define ARG1 as | |
3710 | #define SUFFIX | |
3711 | #define TRANSLATE(...) address_space_translate(as, __VA_ARGS__) | |
3712 | #define RCU_READ_LOCK(...) rcu_read_lock() | |
3713 | #define RCU_READ_UNLOCK(...) rcu_read_unlock() | |
3714 | #include "memory_ldst.inc.c" | |
3715 | ||
3716 | int64_t address_space_cache_init(MemoryRegionCache *cache, | |
3717 | AddressSpace *as, | |
3718 | hwaddr addr, | |
3719 | hwaddr len, | |
3720 | bool is_write) | |
3721 | { | |
3722 | AddressSpaceDispatch *d; | |
3723 | hwaddr l; | |
3724 | MemoryRegion *mr; | |
3725 | ||
3726 | assert(len > 0); | |
3727 | ||
3728 | l = len; | |
3729 | cache->fv = address_space_get_flatview(as); | |
3730 | d = flatview_to_dispatch(cache->fv); | |
3731 | cache->mrs = *address_space_translate_internal(d, addr, &cache->xlat, &l, true); | |
3732 | ||
3733 | mr = cache->mrs.mr; | |
3734 | memory_region_ref(mr); | |
3735 | if (memory_access_is_direct(mr, is_write)) { | |
3736 | /* We don't care about the memory attributes here as we're only | |
3737 | * doing this if we found actual RAM, which behaves the same | |
3738 | * regardless of attributes; so UNSPECIFIED is fine. | |
3739 | */ | |
3740 | l = flatview_extend_translation(cache->fv, addr, len, mr, | |
3741 | cache->xlat, l, is_write, | |
3742 | MEMTXATTRS_UNSPECIFIED); | |
3743 | cache->ptr = qemu_ram_ptr_length(mr->ram_block, cache->xlat, &l, true); | |
3744 | } else { | |
3745 | cache->ptr = NULL; | |
3746 | } | |
3747 | ||
3748 | cache->len = l; | |
3749 | cache->is_write = is_write; | |
3750 | return l; | |
3751 | } | |
3752 | ||
3753 | void address_space_cache_invalidate(MemoryRegionCache *cache, | |
3754 | hwaddr addr, | |
3755 | hwaddr access_len) | |
3756 | { | |
3757 | assert(cache->is_write); | |
3758 | if (likely(cache->ptr)) { | |
3759 | invalidate_and_set_dirty(cache->mrs.mr, addr + cache->xlat, access_len); | |
3760 | } | |
3761 | } | |
3762 | ||
3763 | void address_space_cache_destroy(MemoryRegionCache *cache) | |
3764 | { | |
3765 | if (!cache->mrs.mr) { | |
3766 | return; | |
3767 | } | |
3768 | ||
3769 | if (xen_enabled()) { | |
3770 | xen_invalidate_map_cache_entry(cache->ptr); | |
3771 | } | |
3772 | memory_region_unref(cache->mrs.mr); | |
3773 | flatview_unref(cache->fv); | |
3774 | cache->mrs.mr = NULL; | |
3775 | cache->fv = NULL; | |
3776 | } | |
3777 | ||
3778 | /* Called from RCU critical section. This function has the same | |
3779 | * semantics as address_space_translate, but it only works on a | |
3780 | * predefined range of a MemoryRegion that was mapped with | |
3781 | * address_space_cache_init. | |
3782 | */ | |
3783 | static inline MemoryRegion *address_space_translate_cached( | |
3784 | MemoryRegionCache *cache, hwaddr addr, hwaddr *xlat, | |
3785 | hwaddr *plen, bool is_write, MemTxAttrs attrs) | |
3786 | { | |
3787 | MemoryRegionSection section; | |
3788 | MemoryRegion *mr; | |
3789 | IOMMUMemoryRegion *iommu_mr; | |
3790 | AddressSpace *target_as; | |
3791 | ||
3792 | assert(!cache->ptr); | |
3793 | *xlat = addr + cache->xlat; | |
3794 | ||
3795 | mr = cache->mrs.mr; | |
3796 | iommu_mr = memory_region_get_iommu(mr); | |
3797 | if (!iommu_mr) { | |
3798 | /* MMIO region. */ | |
3799 | return mr; | |
3800 | } | |
3801 | ||
3802 | section = address_space_translate_iommu(iommu_mr, xlat, plen, | |
3803 | NULL, is_write, true, | |
3804 | &target_as, attrs); | |
3805 | return section.mr; | |
3806 | } | |
3807 | ||
3808 | /* Called from RCU critical section. address_space_read_cached uses this | |
3809 | * out of line function when the target is an MMIO or IOMMU region. | |
3810 | */ | |
3811 | void | |
3812 | address_space_read_cached_slow(MemoryRegionCache *cache, hwaddr addr, | |
3813 | void *buf, int len) | |
3814 | { | |
3815 | hwaddr addr1, l; | |
3816 | MemoryRegion *mr; | |
3817 | ||
3818 | l = len; | |
3819 | mr = address_space_translate_cached(cache, addr, &addr1, &l, false, | |
3820 | MEMTXATTRS_UNSPECIFIED); | |
3821 | flatview_read_continue(cache->fv, | |
3822 | addr, MEMTXATTRS_UNSPECIFIED, buf, len, | |
3823 | addr1, l, mr); | |
3824 | } | |
3825 | ||
3826 | /* Called from RCU critical section. address_space_write_cached uses this | |
3827 | * out of line function when the target is an MMIO or IOMMU region. | |
3828 | */ | |
3829 | void | |
3830 | address_space_write_cached_slow(MemoryRegionCache *cache, hwaddr addr, | |
3831 | const void *buf, int len) | |
3832 | { | |
3833 | hwaddr addr1, l; | |
3834 | MemoryRegion *mr; | |
3835 | ||
3836 | l = len; | |
3837 | mr = address_space_translate_cached(cache, addr, &addr1, &l, true, | |
3838 | MEMTXATTRS_UNSPECIFIED); | |
3839 | flatview_write_continue(cache->fv, | |
3840 | addr, MEMTXATTRS_UNSPECIFIED, buf, len, | |
3841 | addr1, l, mr); | |
3842 | } | |
3843 | ||
3844 | #define ARG1_DECL MemoryRegionCache *cache | |
3845 | #define ARG1 cache | |
3846 | #define SUFFIX _cached_slow | |
3847 | #define TRANSLATE(...) address_space_translate_cached(cache, __VA_ARGS__) | |
3848 | #define RCU_READ_LOCK() ((void)0) | |
3849 | #define RCU_READ_UNLOCK() ((void)0) | |
3850 | #include "memory_ldst.inc.c" | |
3851 | ||
3852 | /* virtual memory access for debug (includes writing to ROM) */ | |
3853 | int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, | |
3854 | uint8_t *buf, int len, int is_write) | |
3855 | { | |
3856 | int l; | |
3857 | hwaddr phys_addr; | |
3858 | target_ulong page; | |
3859 | ||
3860 | cpu_synchronize_state(cpu); | |
3861 | while (len > 0) { | |
3862 | int asidx; | |
3863 | MemTxAttrs attrs; | |
3864 | ||
3865 | page = addr & TARGET_PAGE_MASK; | |
3866 | phys_addr = cpu_get_phys_page_attrs_debug(cpu, page, &attrs); | |
3867 | asidx = cpu_asidx_from_attrs(cpu, attrs); | |
3868 | /* if no physical page mapped, return an error */ | |
3869 | if (phys_addr == -1) | |
3870 | return -1; | |
3871 | l = (page + TARGET_PAGE_SIZE) - addr; | |
3872 | if (l > len) | |
3873 | l = len; | |
3874 | phys_addr += (addr & ~TARGET_PAGE_MASK); | |
3875 | if (is_write) { | |
3876 | cpu_physical_memory_write_rom(cpu->cpu_ases[asidx].as, | |
3877 | phys_addr, buf, l); | |
3878 | } else { | |
3879 | address_space_rw(cpu->cpu_ases[asidx].as, phys_addr, | |
3880 | MEMTXATTRS_UNSPECIFIED, | |
3881 | buf, l, 0); | |
3882 | } | |
3883 | len -= l; | |
3884 | buf += l; | |
3885 | addr += l; | |
3886 | } | |
3887 | return 0; | |
3888 | } | |
3889 | ||
3890 | /* | |
3891 | * Allows code that needs to deal with migration bitmaps etc to still be built | |
3892 | * target independent. | |
3893 | */ | |
3894 | size_t qemu_target_page_size(void) | |
3895 | { | |
3896 | return TARGET_PAGE_SIZE; | |
3897 | } | |
3898 | ||
3899 | int qemu_target_page_bits(void) | |
3900 | { | |
3901 | return TARGET_PAGE_BITS; | |
3902 | } | |
3903 | ||
3904 | int qemu_target_page_bits_min(void) | |
3905 | { | |
3906 | return TARGET_PAGE_BITS_MIN; | |
3907 | } | |
3908 | #endif | |
3909 | ||
3910 | bool target_words_bigendian(void) | |
3911 | { | |
3912 | #if defined(TARGET_WORDS_BIGENDIAN) | |
3913 | return true; | |
3914 | #else | |
3915 | return false; | |
3916 | #endif | |
3917 | } | |
3918 | ||
3919 | #ifndef CONFIG_USER_ONLY | |
3920 | bool cpu_physical_memory_is_io(hwaddr phys_addr) | |
3921 | { | |
3922 | MemoryRegion*mr; | |
3923 | hwaddr l = 1; | |
3924 | bool res; | |
3925 | ||
3926 | rcu_read_lock(); | |
3927 | mr = address_space_translate(&address_space_memory, | |
3928 | phys_addr, &phys_addr, &l, false, | |
3929 | MEMTXATTRS_UNSPECIFIED); | |
3930 | ||
3931 | res = !(memory_region_is_ram(mr) || memory_region_is_romd(mr)); | |
3932 | rcu_read_unlock(); | |
3933 | return res; | |
3934 | } | |
3935 | ||
3936 | int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque) | |
3937 | { | |
3938 | RAMBlock *block; | |
3939 | int ret = 0; | |
3940 | ||
3941 | rcu_read_lock(); | |
3942 | RAMBLOCK_FOREACH(block) { | |
3943 | ret = func(block->idstr, block->host, block->offset, | |
3944 | block->used_length, opaque); | |
3945 | if (ret) { | |
3946 | break; | |
3947 | } | |
3948 | } | |
3949 | rcu_read_unlock(); | |
3950 | return ret; | |
3951 | } | |
3952 | ||
3953 | int qemu_ram_foreach_migratable_block(RAMBlockIterFunc func, void *opaque) | |
3954 | { | |
3955 | RAMBlock *block; | |
3956 | int ret = 0; | |
3957 | ||
3958 | rcu_read_lock(); | |
3959 | RAMBLOCK_FOREACH(block) { | |
3960 | if (!qemu_ram_is_migratable(block)) { | |
3961 | continue; | |
3962 | } | |
3963 | ret = func(block->idstr, block->host, block->offset, | |
3964 | block->used_length, opaque); | |
3965 | if (ret) { | |
3966 | break; | |
3967 | } | |
3968 | } | |
3969 | rcu_read_unlock(); | |
3970 | return ret; | |
3971 | } | |
3972 | ||
3973 | /* | |
3974 | * Unmap pages of memory from start to start+length such that | |
3975 | * they a) read as 0, b) Trigger whatever fault mechanism | |
3976 | * the OS provides for postcopy. | |
3977 | * The pages must be unmapped by the end of the function. | |
3978 | * Returns: 0 on success, none-0 on failure | |
3979 | * | |
3980 | */ | |
3981 | int ram_block_discard_range(RAMBlock *rb, uint64_t start, size_t length) | |
3982 | { | |
3983 | int ret = -1; | |
3984 | ||
3985 | uint8_t *host_startaddr = rb->host + start; | |
3986 | ||
3987 | if ((uintptr_t)host_startaddr & (rb->page_size - 1)) { | |
3988 | error_report("ram_block_discard_range: Unaligned start address: %p", | |
3989 | host_startaddr); | |
3990 | goto err; | |
3991 | } | |
3992 | ||
3993 | if ((start + length) <= rb->used_length) { | |
3994 | bool need_madvise, need_fallocate; | |
3995 | uint8_t *host_endaddr = host_startaddr + length; | |
3996 | if ((uintptr_t)host_endaddr & (rb->page_size - 1)) { | |
3997 | error_report("ram_block_discard_range: Unaligned end address: %p", | |
3998 | host_endaddr); | |
3999 | goto err; | |
4000 | } | |
4001 | ||
4002 | errno = ENOTSUP; /* If we are missing MADVISE etc */ | |
4003 | ||
4004 | /* The logic here is messy; | |
4005 | * madvise DONTNEED fails for hugepages | |
4006 | * fallocate works on hugepages and shmem | |
4007 | */ | |
4008 | need_madvise = (rb->page_size == qemu_host_page_size); | |
4009 | need_fallocate = rb->fd != -1; | |
4010 | if (need_fallocate) { | |
4011 | /* For a file, this causes the area of the file to be zero'd | |
4012 | * if read, and for hugetlbfs also causes it to be unmapped | |
4013 | * so a userfault will trigger. | |
4014 | */ | |
4015 | #ifdef CONFIG_FALLOCATE_PUNCH_HOLE | |
4016 | ret = fallocate(rb->fd, FALLOC_FL_PUNCH_HOLE | FALLOC_FL_KEEP_SIZE, | |
4017 | start, length); | |
4018 | if (ret) { | |
4019 | ret = -errno; | |
4020 | error_report("ram_block_discard_range: Failed to fallocate " | |
4021 | "%s:%" PRIx64 " +%zx (%d)", | |
4022 | rb->idstr, start, length, ret); | |
4023 | goto err; | |
4024 | } | |
4025 | #else | |
4026 | ret = -ENOSYS; | |
4027 | error_report("ram_block_discard_range: fallocate not available/file" | |
4028 | "%s:%" PRIx64 " +%zx (%d)", | |
4029 | rb->idstr, start, length, ret); | |
4030 | goto err; | |
4031 | #endif | |
4032 | } | |
4033 | if (need_madvise) { | |
4034 | /* For normal RAM this causes it to be unmapped, | |
4035 | * for shared memory it causes the local mapping to disappear | |
4036 | * and to fall back on the file contents (which we just | |
4037 | * fallocate'd away). | |
4038 | */ | |
4039 | #if defined(CONFIG_MADVISE) | |
4040 | ret = madvise(host_startaddr, length, MADV_DONTNEED); | |
4041 | if (ret) { | |
4042 | ret = -errno; | |
4043 | error_report("ram_block_discard_range: Failed to discard range " | |
4044 | "%s:%" PRIx64 " +%zx (%d)", | |
4045 | rb->idstr, start, length, ret); | |
4046 | goto err; | |
4047 | } | |
4048 | #else | |
4049 | ret = -ENOSYS; | |
4050 | error_report("ram_block_discard_range: MADVISE not available" | |
4051 | "%s:%" PRIx64 " +%zx (%d)", | |
4052 | rb->idstr, start, length, ret); | |
4053 | goto err; | |
4054 | #endif | |
4055 | } | |
4056 | trace_ram_block_discard_range(rb->idstr, host_startaddr, length, | |
4057 | need_madvise, need_fallocate, ret); | |
4058 | } else { | |
4059 | error_report("ram_block_discard_range: Overrun block '%s' (%" PRIu64 | |
4060 | "/%zx/" RAM_ADDR_FMT")", | |
4061 | rb->idstr, start, length, rb->used_length); | |
4062 | } | |
4063 | ||
4064 | err: | |
4065 | return ret; | |
4066 | } | |
4067 | ||
4068 | bool ramblock_is_pmem(RAMBlock *rb) | |
4069 | { | |
4070 | return rb->flags & RAM_PMEM; | |
4071 | } | |
4072 | ||
4073 | #endif | |
4074 | ||
4075 | void page_size_init(void) | |
4076 | { | |
4077 | /* NOTE: we can always suppose that qemu_host_page_size >= | |
4078 | TARGET_PAGE_SIZE */ | |
4079 | if (qemu_host_page_size == 0) { | |
4080 | qemu_host_page_size = qemu_real_host_page_size; | |
4081 | } | |
4082 | if (qemu_host_page_size < TARGET_PAGE_SIZE) { | |
4083 | qemu_host_page_size = TARGET_PAGE_SIZE; | |
4084 | } | |
4085 | qemu_host_page_mask = -(intptr_t)qemu_host_page_size; | |
4086 | } | |
4087 | ||
4088 | #if !defined(CONFIG_USER_ONLY) | |
4089 | ||
4090 | static void mtree_print_phys_entries(fprintf_function mon, void *f, | |
4091 | int start, int end, int skip, int ptr) | |
4092 | { | |
4093 | if (start == end - 1) { | |
4094 | mon(f, "\t%3d ", start); | |
4095 | } else { | |
4096 | mon(f, "\t%3d..%-3d ", start, end - 1); | |
4097 | } | |
4098 | mon(f, " skip=%d ", skip); | |
4099 | if (ptr == PHYS_MAP_NODE_NIL) { | |
4100 | mon(f, " ptr=NIL"); | |
4101 | } else if (!skip) { | |
4102 | mon(f, " ptr=#%d", ptr); | |
4103 | } else { | |
4104 | mon(f, " ptr=[%d]", ptr); | |
4105 | } | |
4106 | mon(f, "\n"); | |
4107 | } | |
4108 | ||
4109 | #define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \ | |
4110 | int128_sub((size), int128_one())) : 0) | |
4111 | ||
4112 | void mtree_print_dispatch(fprintf_function mon, void *f, | |
4113 | AddressSpaceDispatch *d, MemoryRegion *root) | |
4114 | { | |
4115 | int i; | |
4116 | ||
4117 | mon(f, " Dispatch\n"); | |
4118 | mon(f, " Physical sections\n"); | |
4119 | ||
4120 | for (i = 0; i < d->map.sections_nb; ++i) { | |
4121 | MemoryRegionSection *s = d->map.sections + i; | |
4122 | const char *names[] = { " [unassigned]", " [not dirty]", | |
4123 | " [ROM]", " [watch]" }; | |
4124 | ||
4125 | mon(f, " #%d @" TARGET_FMT_plx ".." TARGET_FMT_plx " %s%s%s%s%s", | |
4126 | i, | |
4127 | s->offset_within_address_space, | |
4128 | s->offset_within_address_space + MR_SIZE(s->mr->size), | |
4129 | s->mr->name ? s->mr->name : "(noname)", | |
4130 | i < ARRAY_SIZE(names) ? names[i] : "", | |
4131 | s->mr == root ? " [ROOT]" : "", | |
4132 | s == d->mru_section ? " [MRU]" : "", | |
4133 | s->mr->is_iommu ? " [iommu]" : ""); | |
4134 | ||
4135 | if (s->mr->alias) { | |
4136 | mon(f, " alias=%s", s->mr->alias->name ? | |
4137 | s->mr->alias->name : "noname"); | |
4138 | } | |
4139 | mon(f, "\n"); | |
4140 | } | |
4141 | ||
4142 | mon(f, " Nodes (%d bits per level, %d levels) ptr=[%d] skip=%d\n", | |
4143 | P_L2_BITS, P_L2_LEVELS, d->phys_map.ptr, d->phys_map.skip); | |
4144 | for (i = 0; i < d->map.nodes_nb; ++i) { | |
4145 | int j, jprev; | |
4146 | PhysPageEntry prev; | |
4147 | Node *n = d->map.nodes + i; | |
4148 | ||
4149 | mon(f, " [%d]\n", i); | |
4150 | ||
4151 | for (j = 0, jprev = 0, prev = *n[0]; j < ARRAY_SIZE(*n); ++j) { | |
4152 | PhysPageEntry *pe = *n + j; | |
4153 | ||
4154 | if (pe->ptr == prev.ptr && pe->skip == prev.skip) { | |
4155 | continue; | |
4156 | } | |
4157 | ||
4158 | mtree_print_phys_entries(mon, f, jprev, j, prev.skip, prev.ptr); | |
4159 | ||
4160 | jprev = j; | |
4161 | prev = *pe; | |
4162 | } | |
4163 | ||
4164 | if (jprev != ARRAY_SIZE(*n)) { | |
4165 | mtree_print_phys_entries(mon, f, jprev, j, prev.skip, prev.ptr); | |
4166 | } | |
4167 | } | |
4168 | } | |
4169 | ||
4170 | #endif |