[mirror_qemu.git] / hw / arm / pxa2xx_gpio.c

/*
 * Intel XScale PXA255/270 GPIO controller emulation.
 *
 * Copyright (c) 2006 Openedhand Ltd.
 * Written by Andrzej Zaborowski <balrog@zabor.org>
 *
 * This code is licensed under the GPL.
 */

#include "qemu/osdep.h"
#include "cpu.h"
#include "hw/hw.h"
#include "hw/irq.h"
#include "hw/sysbus.h"
#include "migration/vmstate.h"
#include "hw/arm/pxa.h"
#include "qemu/log.h"
#include "qemu/module.h"

#define PXA2XX_GPIO_BANKS	4

#define TYPE_PXA2XX_GPIO "pxa2xx-gpio"
#define PXA2XX_GPIO(obj) \
    OBJECT_CHECK(PXA2xxGPIOInfo, (obj), TYPE_PXA2XX_GPIO)

typedef struct PXA2xxGPIOInfo PXA2xxGPIOInfo;
struct PXA2xxGPIOInfo {
    /*< private >*/
    SysBusDevice parent_obj;
    /*< public >*/

    MemoryRegion iomem;
    qemu_irq irq0, irq1, irqX;
    int lines;
    int ncpu;
    ARMCPU *cpu;

    /* XXX: GNU C vectors are more suitable */
    uint32_t ilevel[PXA2XX_GPIO_BANKS];
    uint32_t olevel[PXA2XX_GPIO_BANKS];
    uint32_t dir[PXA2XX_GPIO_BANKS];
    uint32_t rising[PXA2XX_GPIO_BANKS];
    uint32_t falling[PXA2XX_GPIO_BANKS];
    uint32_t status[PXA2XX_GPIO_BANKS];
    uint32_t gafr[PXA2XX_GPIO_BANKS * 2];

    uint32_t prev_level[PXA2XX_GPIO_BANKS];
    qemu_irq handler[PXA2XX_GPIO_BANKS * 32];
    qemu_irq read_notify;
};

static struct {
    enum {
        GPIO_NONE,
        GPLR,
        GPSR,
        GPCR,
        GPDR,
        GRER,
        GFER,
        GEDR,
        GAFR_L,
        GAFR_U,
    } reg;
    int bank;
} pxa2xx_gpio_regs[0x200] = {
    [0 ... 0x1ff] = { GPIO_NONE, 0 },
#define PXA2XX_REG(reg, a0, a1, a2, a3)	\
    [a0] = { reg, 0 }, [a1] = { reg, 1 }, [a2] = { reg, 2 }, [a3] = { reg, 3 },

    PXA2XX_REG(GPLR, 0x000, 0x004, 0x008, 0x100)
    PXA2XX_REG(GPSR, 0x018, 0x01c, 0x020, 0x118)
    PXA2XX_REG(GPCR, 0x024, 0x028, 0x02c, 0x124)
    PXA2XX_REG(GPDR, 0x00c, 0x010, 0x014, 0x10c)
    PXA2XX_REG(GRER, 0x030, 0x034, 0x038, 0x130)
    PXA2XX_REG(GFER, 0x03c, 0x040, 0x044, 0x13c)
    PXA2XX_REG(GEDR, 0x048, 0x04c, 0x050, 0x148)
    PXA2XX_REG(GAFR_L, 0x054, 0x05c, 0x064, 0x06c)
    PXA2XX_REG(GAFR_U, 0x058, 0x060, 0x068, 0x070)
};

static void pxa2xx_gpio_irq_update(PXA2xxGPIOInfo *s)
{
    if (s->status[0] & (1 << 0))
        qemu_irq_raise(s->irq0);
    else
        qemu_irq_lower(s->irq0);

    if (s->status[0] & (1 << 1))
        qemu_irq_raise(s->irq1);
    else
        qemu_irq_lower(s->irq1);

    if ((s->status[0] & ~3) | s->status[1] | s->status[2] | s->status[3])
        qemu_irq_raise(s->irqX);
    else
        qemu_irq_lower(s->irqX);
}

/* Bitmap of pins used as standby and sleep wake-up sources.  */
static const int pxa2xx_gpio_wake[PXA2XX_GPIO_BANKS] = {
    0x8003fe1b, 0x002001fc, 0xec080000, 0x0012007f,
};

static void pxa2xx_gpio_set(void *opaque, int line, int level)
{
    PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
    CPUState *cpu = CPU(s->cpu);
    int bank;
    uint32_t mask;

    if (line >= s->lines) {
        printf("%s: No GPIO pin %i\n", __func__, line);
        return;
    }

    bank = line >> 5;
    mask = 1U << (line & 31);

    if (level) {
        s->status[bank] |= s->rising[bank] & mask &
                ~s->ilevel[bank] & ~s->dir[bank];
        s->ilevel[bank] |= mask;
    } else {
        s->status[bank] |= s->falling[bank] & mask &
                s->ilevel[bank] & ~s->dir[bank];
        s->ilevel[bank] &= ~mask;
    }

    if (s->status[bank] & mask)
        pxa2xx_gpio_irq_update(s);

    /* Wake-up GPIOs */
    if (cpu->halted && (mask & ~s->dir[bank] & pxa2xx_gpio_wake[bank])) {
        cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB);
    }
}

static void pxa2xx_gpio_handler_update(PXA2xxGPIOInfo *s) {
    uint32_t level, diff;
    int i, bit, line;
    for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) {
        level = s->olevel[i] & s->dir[i];

        for (diff = s->prev_level[i] ^ level; diff; diff ^= 1 << bit) {
            bit = ctz32(diff);
            line = bit + 32 * i;
            qemu_set_irq(s->handler[line], (level >> bit) & 1);
        }

        s->prev_level[i] = level;
    }
}

static uint64_t pxa2xx_gpio_read(void *opaque, hwaddr offset,
                                 unsigned size)
{
    PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
    uint32_t ret;
    int bank;
    if (offset >= 0x200)
        return 0;

    bank = pxa2xx_gpio_regs[offset].bank;
    switch (pxa2xx_gpio_regs[offset].reg) {
    case GPDR:		/* GPIO Pin-Direction registers */
        return s->dir[bank];

    case GPSR:		/* GPIO Pin-Output Set registers */
        qemu_log_mask(LOG_GUEST_ERROR,
                      "pxa2xx GPIO: read from write only register GPSR\n");
        return 0;

    case GPCR:		/* GPIO Pin-Output Clear registers */
        qemu_log_mask(LOG_GUEST_ERROR,
                      "pxa2xx GPIO: read from write only register GPCR\n");
        return 0;

    case GRER:		/* GPIO Rising-Edge Detect Enable registers */
        return s->rising[bank];

    case GFER:		/* GPIO Falling-Edge Detect Enable registers */
        return s->falling[bank];

    case GAFR_L:	/* GPIO Alternate Function registers */
        return s->gafr[bank * 2];

    case GAFR_U:	/* GPIO Alternate Function registers */
        return s->gafr[bank * 2 + 1];

    case GPLR:		/* GPIO Pin-Level registers */
        ret = (s->olevel[bank] & s->dir[bank]) |
                (s->ilevel[bank] & ~s->dir[bank]);
        qemu_irq_raise(s->read_notify);
        return ret;

    case GEDR:		/* GPIO Edge Detect Status registers */
        return s->status[bank];

    default:
        hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset);
    }

    return 0;
}

static void pxa2xx_gpio_write(void *opaque, hwaddr offset,
                              uint64_t value, unsigned size)
{
    PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
    int bank;
    if (offset >= 0x200)
        return;

    bank = pxa2xx_gpio_regs[offset].bank;
    switch (pxa2xx_gpio_regs[offset].reg) {
    case GPDR:		/* GPIO Pin-Direction registers */
        s->dir[bank] = value;
        pxa2xx_gpio_handler_update(s);
        break;

    case GPSR:		/* GPIO Pin-Output Set registers */
        s->olevel[bank] |= value;
        pxa2xx_gpio_handler_update(s);
        break;

    case GPCR:		/* GPIO Pin-Output Clear registers */
        s->olevel[bank] &= ~value;
        pxa2xx_gpio_handler_update(s);
        break;

    case GRER:		/* GPIO Rising-Edge Detect Enable registers */
        s->rising[bank] = value;
        break;

    case GFER:		/* GPIO Falling-Edge Detect Enable registers */
        s->falling[bank] = value;
        break;

    case GAFR_L:	/* GPIO Alternate Function registers */
        s->gafr[bank * 2] = value;
        break;

    case GAFR_U:	/* GPIO Alternate Function registers */
        s->gafr[bank * 2 + 1] = value;
        break;

    case GEDR:		/* GPIO Edge Detect Status registers */
        s->status[bank] &= ~value;
        pxa2xx_gpio_irq_update(s);
        break;

    default:
        hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset);
    }
}

static const MemoryRegionOps pxa_gpio_ops = {
    .read = pxa2xx_gpio_read,
    .write = pxa2xx_gpio_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

DeviceState *pxa2xx_gpio_init(hwaddr base,
                              ARMCPU *cpu, DeviceState *pic, int lines)
{
    CPUState *cs = CPU(cpu);
    DeviceState *dev;

    dev = qdev_create(NULL, TYPE_PXA2XX_GPIO);
    qdev_prop_set_int32(dev, "lines", lines);
    qdev_prop_set_int32(dev, "ncpu", cs->cpu_index);
    qdev_init_nofail(dev);

    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
                    qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_0));
    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1,
                    qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_1));
    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2,
                    qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_X));

    return dev;
}

static void pxa2xx_gpio_initfn(Object *obj)
{
    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
    DeviceState *dev = DEVICE(sbd);
    PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);

    memory_region_init_io(&s->iomem, obj, &pxa_gpio_ops,
                          s, "pxa2xx-gpio", 0x1000);
    sysbus_init_mmio(sbd, &s->iomem);
    sysbus_init_irq(sbd, &s->irq0);
    sysbus_init_irq(sbd, &s->irq1);
    sysbus_init_irq(sbd, &s->irqX);
}

static void pxa2xx_gpio_realize(DeviceState *dev, Error **errp)
{
    PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);

    s->cpu = ARM_CPU(qemu_get_cpu(s->ncpu));

    qdev_init_gpio_in(dev, pxa2xx_gpio_set, s->lines);
    qdev_init_gpio_out(dev, s->handler, s->lines);
}

/*
 * Registers a callback to notify on GPLR reads.  This normally
 * shouldn't be needed but it is used for the hack on Spitz machines.
 */
void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler)
{
    PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);

    s->read_notify = handler;
}

static const VMStateDescription vmstate_pxa2xx_gpio_regs = {
    .name = "pxa2xx-gpio",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32_ARRAY(ilevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
        VMSTATE_UINT32_ARRAY(olevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
        VMSTATE_UINT32_ARRAY(dir, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
        VMSTATE_UINT32_ARRAY(rising, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
        VMSTATE_UINT32_ARRAY(falling, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
        VMSTATE_UINT32_ARRAY(status, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
        VMSTATE_UINT32_ARRAY(gafr, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS * 2),
        VMSTATE_UINT32_ARRAY(prev_level, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
        VMSTATE_END_OF_LIST(),
    },
};

static Property pxa2xx_gpio_properties[] = {
    DEFINE_PROP_INT32("lines", PXA2xxGPIOInfo, lines, 0),
    DEFINE_PROP_INT32("ncpu", PXA2xxGPIOInfo, ncpu, 0),
    DEFINE_PROP_END_OF_LIST(),
};

static void pxa2xx_gpio_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->desc = "PXA2xx GPIO controller";
    dc->props = pxa2xx_gpio_properties;
    dc->vmsd = &vmstate_pxa2xx_gpio_regs;
    dc->realize = pxa2xx_gpio_realize;
}

static const TypeInfo pxa2xx_gpio_info = {
    .name          = TYPE_PXA2XX_GPIO,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(PXA2xxGPIOInfo),
    .instance_init = pxa2xx_gpio_initfn,
    .class_init    = pxa2xx_gpio_class_init,
};

static void pxa2xx_gpio_register_types(void)
{
    type_register_static(&pxa2xx_gpio_info);
}

type_init(pxa2xx_gpio_register_types)
Commit	Line	Data
	1	/*
	2	* Intel XScale PXA255/270 GPIO controller emulation.
	3	*
	4	* Copyright (c) 2006 Openedhand Ltd.
	5	* Written by Andrzej Zaborowski <balrog@zabor.org>
	6	*
	7	* This code is licensed under the GPL.
	8	*/
	9
	10	#include "qemu/osdep.h"
	11	#include "cpu.h"
	12	#include "hw/hw.h"
	13	#include "hw/irq.h"
	14	#include "hw/sysbus.h"
	15	#include "migration/vmstate.h"
	16	#include "hw/arm/pxa.h"
	17	#include "qemu/log.h"
	18	#include "qemu/module.h"
	19
	20	#define PXA2XX_GPIO_BANKS 4
	21
	22	#define TYPE_PXA2XX_GPIO "pxa2xx-gpio"
	23	#define PXA2XX_GPIO(obj) \
	24	OBJECT_CHECK(PXA2xxGPIOInfo, (obj), TYPE_PXA2XX_GPIO)
	25
	26	typedef struct PXA2xxGPIOInfo PXA2xxGPIOInfo;
	27	struct PXA2xxGPIOInfo {
	28	/< private >/
	29	SysBusDevice parent_obj;
	30	/< public >/
	31
	32	MemoryRegion iomem;
	33	qemu_irq irq0, irq1, irqX;
	34	int lines;
	35	int ncpu;
	36	ARMCPU *cpu;
	37
	38	/* XXX: GNU C vectors are more suitable */
	39	uint32_t ilevel[PXA2XX_GPIO_BANKS];
	40	uint32_t olevel[PXA2XX_GPIO_BANKS];
	41	uint32_t dir[PXA2XX_GPIO_BANKS];
	42	uint32_t rising[PXA2XX_GPIO_BANKS];
	43	uint32_t falling[PXA2XX_GPIO_BANKS];
	44	uint32_t status[PXA2XX_GPIO_BANKS];
	45	uint32_t gafr[PXA2XX_GPIO_BANKS * 2];
	46
	47	uint32_t prev_level[PXA2XX_GPIO_BANKS];
	48	qemu_irq handler[PXA2XX_GPIO_BANKS * 32];
	49	qemu_irq read_notify;
	50	};
	51
	52	static struct {
	53	enum {
	54	GPIO_NONE,
	55	GPLR,
	56	GPSR,
	57	GPCR,
	58	GPDR,
	59	GRER,
	60	GFER,
	61	GEDR,
	62	GAFR_L,
	63	GAFR_U,
	64	} reg;
	65	int bank;
	66	} pxa2xx_gpio_regs[0x200] = {
	67	[0 ... 0x1ff] = { GPIO_NONE, 0 },
	68	#define PXA2XX_REG(reg, a0, a1, a2, a3) \
	69	[a0] = { reg, 0 }, [a1] = { reg, 1 }, [a2] = { reg, 2 }, [a3] = { reg, 3 },
	70
	71	PXA2XX_REG(GPLR, 0x000, 0x004, 0x008, 0x100)
	72	PXA2XX_REG(GPSR, 0x018, 0x01c, 0x020, 0x118)
	73	PXA2XX_REG(GPCR, 0x024, 0x028, 0x02c, 0x124)
	74	PXA2XX_REG(GPDR, 0x00c, 0x010, 0x014, 0x10c)
	75	PXA2XX_REG(GRER, 0x030, 0x034, 0x038, 0x130)
	76	PXA2XX_REG(GFER, 0x03c, 0x040, 0x044, 0x13c)
	77	PXA2XX_REG(GEDR, 0x048, 0x04c, 0x050, 0x148)
	78	PXA2XX_REG(GAFR_L, 0x054, 0x05c, 0x064, 0x06c)
	79	PXA2XX_REG(GAFR_U, 0x058, 0x060, 0x068, 0x070)
	80	};
	81
	82	static void pxa2xx_gpio_irq_update(PXA2xxGPIOInfo *s)
	83	{
	84	if (s->status[0] & (1 << 0))
	85	qemu_irq_raise(s->irq0);
	86	else
	87	qemu_irq_lower(s->irq0);
	88
	89	if (s->status[0] & (1 << 1))
	90	qemu_irq_raise(s->irq1);
	91	else
	92	qemu_irq_lower(s->irq1);
	93
	94	if ((s->status[0] & ~3) \| s->status[1] \| s->status[2] \| s->status[3])
	95	qemu_irq_raise(s->irqX);
	96	else
	97	qemu_irq_lower(s->irqX);
	98	}
	99
	100	/* Bitmap of pins used as standby and sleep wake-up sources. */
	101	static const int pxa2xx_gpio_wake[PXA2XX_GPIO_BANKS] = {
	102	0x8003fe1b, 0x002001fc, 0xec080000, 0x0012007f,
	103	};
	104
	105	static void pxa2xx_gpio_set(void *opaque, int line, int level)
	106	{
	107	PXA2xxGPIOInfo s = (PXA2xxGPIOInfo ) opaque;
	108	CPUState *cpu = CPU(s->cpu);
	109	int bank;
	110	uint32_t mask;
	111
	112	if (line >= s->lines) {
	113	printf("%s: No GPIO pin %i\n", __func__, line);
	114	return;
	115	}
	116
	117	bank = line >> 5;
	118	mask = 1U << (line & 31);
	119
	120	if (level) {
	121	s->status[bank] \|= s->rising[bank] & mask &
	122	~s->ilevel[bank] & ~s->dir[bank];
	123	s->ilevel[bank] \|= mask;
	124	} else {
	125	s->status[bank] \|= s->falling[bank] & mask &
	126	s->ilevel[bank] & ~s->dir[bank];
	127	s->ilevel[bank] &= ~mask;
	128	}
	129
	130	if (s->status[bank] & mask)
	131	pxa2xx_gpio_irq_update(s);
	132
	133	/* Wake-up GPIOs */
	134	if (cpu->halted && (mask & ~s->dir[bank] & pxa2xx_gpio_wake[bank])) {
	135	cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB);
	136	}
	137	}
	138
	139	static void pxa2xx_gpio_handler_update(PXA2xxGPIOInfo *s) {
	140	uint32_t level, diff;
	141	int i, bit, line;
	142	for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) {
	143	level = s->olevel[i] & s->dir[i];
	144
	145	for (diff = s->prev_level[i] ^ level; diff; diff ^= 1 << bit) {
	146	bit = ctz32(diff);
	147	line = bit + 32 * i;
	148	qemu_set_irq(s->handler[line], (level >> bit) & 1);
	149	}
	150
	151	s->prev_level[i] = level;
	152	}
	153	}
	154
	155	static uint64_t pxa2xx_gpio_read(void *opaque, hwaddr offset,
	156	unsigned size)
	157	{
	158	PXA2xxGPIOInfo s = (PXA2xxGPIOInfo ) opaque;
	159	uint32_t ret;
	160	int bank;
	161	if (offset >= 0x200)
	162	return 0;
	163
	164	bank = pxa2xx_gpio_regs[offset].bank;
	165	switch (pxa2xx_gpio_regs[offset].reg) {
	166	case GPDR: /* GPIO Pin-Direction registers */
	167	return s->dir[bank];
	168
	169	case GPSR: /* GPIO Pin-Output Set registers */
	170	qemu_log_mask(LOG_GUEST_ERROR,
	171	"pxa2xx GPIO: read from write only register GPSR\n");
	172	return 0;
	173
	174	case GPCR: /* GPIO Pin-Output Clear registers */
	175	qemu_log_mask(LOG_GUEST_ERROR,
	176	"pxa2xx GPIO: read from write only register GPCR\n");
	177	return 0;
	178
	179	case GRER: /* GPIO Rising-Edge Detect Enable registers */
	180	return s->rising[bank];
	181
	182	case GFER: /* GPIO Falling-Edge Detect Enable registers */
	183	return s->falling[bank];
	184
	185	case GAFR_L: /* GPIO Alternate Function registers */
	186	return s->gafr[bank * 2];
	187
	188	case GAFR_U: /* GPIO Alternate Function registers */
	189	return s->gafr[bank * 2 + 1];
	190
	191	case GPLR: /* GPIO Pin-Level registers */
	192	ret = (s->olevel[bank] & s->dir[bank]) \|
	193	(s->ilevel[bank] & ~s->dir[bank]);
	194	qemu_irq_raise(s->read_notify);
	195	return ret;
	196
	197	case GEDR: /* GPIO Edge Detect Status registers */
	198	return s->status[bank];
	199
	200	default:
	201	hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset);
	202	}
	203
	204	return 0;
	205	}
	206
	207	static void pxa2xx_gpio_write(void *opaque, hwaddr offset,
	208	uint64_t value, unsigned size)
	209	{
	210	PXA2xxGPIOInfo s = (PXA2xxGPIOInfo ) opaque;
	211	int bank;
	212	if (offset >= 0x200)
	213	return;
	214
	215	bank = pxa2xx_gpio_regs[offset].bank;
	216	switch (pxa2xx_gpio_regs[offset].reg) {
	217	case GPDR: /* GPIO Pin-Direction registers */
	218	s->dir[bank] = value;
	219	pxa2xx_gpio_handler_update(s);
	220	break;
	221
	222	case GPSR: /* GPIO Pin-Output Set registers */
	223	s->olevel[bank] \|= value;
	224	pxa2xx_gpio_handler_update(s);
	225	break;
	226
	227	case GPCR: /* GPIO Pin-Output Clear registers */
	228	s->olevel[bank] &= ~value;
	229	pxa2xx_gpio_handler_update(s);
	230	break;
	231
	232	case GRER: /* GPIO Rising-Edge Detect Enable registers */
	233	s->rising[bank] = value;
	234	break;
	235
	236	case GFER: /* GPIO Falling-Edge Detect Enable registers */
	237	s->falling[bank] = value;
	238	break;
	239
	240	case GAFR_L: /* GPIO Alternate Function registers */
	241	s->gafr[bank * 2] = value;
	242	break;
	243
	244	case GAFR_U: /* GPIO Alternate Function registers */
	245	s->gafr[bank * 2 + 1] = value;
	246	break;
	247
	248	case GEDR: /* GPIO Edge Detect Status registers */
	249	s->status[bank] &= ~value;
	250	pxa2xx_gpio_irq_update(s);
	251	break;
	252
	253	default:
	254	hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset);
	255	}
	256	}
	257
	258	static const MemoryRegionOps pxa_gpio_ops = {
	259	.read = pxa2xx_gpio_read,
	260	.write = pxa2xx_gpio_write,
	261	.endianness = DEVICE_NATIVE_ENDIAN,
	262	};
	263
	264	DeviceState *pxa2xx_gpio_init(hwaddr base,
	265	ARMCPU cpu, DeviceState pic, int lines)
	266	{
	267	CPUState *cs = CPU(cpu);
	268	DeviceState *dev;
	269
	270	dev = qdev_create(NULL, TYPE_PXA2XX_GPIO);
	271	qdev_prop_set_int32(dev, "lines", lines);
	272	qdev_prop_set_int32(dev, "ncpu", cs->cpu_index);
	273	qdev_init_nofail(dev);
	274
	275	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
	276	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
	277	qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_0));
	278	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1,
	279	qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_1));
	280	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2,
	281	qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_X));
	282
	283	return dev;
	284	}
	285
	286	static void pxa2xx_gpio_initfn(Object *obj)
	287	{
	288	SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
	289	DeviceState *dev = DEVICE(sbd);
	290	PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);
	291
	292	memory_region_init_io(&s->iomem, obj, &pxa_gpio_ops,
	293	s, "pxa2xx-gpio", 0x1000);
	294	sysbus_init_mmio(sbd, &s->iomem);
	295	sysbus_init_irq(sbd, &s->irq0);
	296	sysbus_init_irq(sbd, &s->irq1);
	297	sysbus_init_irq(sbd, &s->irqX);
	298	}
	299
	300	static void pxa2xx_gpio_realize(DeviceState dev, Error *errp)
	301	{
	302	PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);
	303
	304	s->cpu = ARM_CPU(qemu_get_cpu(s->ncpu));
	305
	306	qdev_init_gpio_in(dev, pxa2xx_gpio_set, s->lines);
	307	qdev_init_gpio_out(dev, s->handler, s->lines);
	308	}
	309
	310	/*
	311	* Registers a callback to notify on GPLR reads. This normally
	312	* shouldn't be needed but it is used for the hack on Spitz machines.
	313	*/
	314	void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler)
	315	{
	316	PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);
	317
	318	s->read_notify = handler;
	319	}
	320
	321	static const VMStateDescription vmstate_pxa2xx_gpio_regs = {
	322	.name = "pxa2xx-gpio",
	323	.version_id = 1,
	324	.minimum_version_id = 1,
	325	.fields = (VMStateField[]) {
	326	VMSTATE_UINT32_ARRAY(ilevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
	327	VMSTATE_UINT32_ARRAY(olevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
	328	VMSTATE_UINT32_ARRAY(dir, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
	329	VMSTATE_UINT32_ARRAY(rising, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
	330	VMSTATE_UINT32_ARRAY(falling, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
	331	VMSTATE_UINT32_ARRAY(status, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
	332	VMSTATE_UINT32_ARRAY(gafr, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS * 2),
	333	VMSTATE_UINT32_ARRAY(prev_level, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
	334	VMSTATE_END_OF_LIST(),
	335	},
	336	};
	337
	338	static Property pxa2xx_gpio_properties[] = {
	339	DEFINE_PROP_INT32("lines", PXA2xxGPIOInfo, lines, 0),
	340	DEFINE_PROP_INT32("ncpu", PXA2xxGPIOInfo, ncpu, 0),
	341	DEFINE_PROP_END_OF_LIST(),
	342	};
	343
	344	static void pxa2xx_gpio_class_init(ObjectClass klass, void data)
	345	{
	346	DeviceClass *dc = DEVICE_CLASS(klass);
	347
	348	dc->desc = "PXA2xx GPIO controller";
	349	dc->props = pxa2xx_gpio_properties;
	350	dc->vmsd = &vmstate_pxa2xx_gpio_regs;
	351	dc->realize = pxa2xx_gpio_realize;
	352	}
	353
	354	static const TypeInfo pxa2xx_gpio_info = {
	355	.name = TYPE_PXA2XX_GPIO,
	356	.parent = TYPE_SYS_BUS_DEVICE,
	357	.instance_size = sizeof(PXA2xxGPIOInfo),
	358	.instance_init = pxa2xx_gpio_initfn,
	359	.class_init = pxa2xx_gpio_class_init,
	360	};
	361
	362	static void pxa2xx_gpio_register_types(void)
	363	{
	364	type_register_static(&pxa2xx_gpio_info);
	365	}
	366
	367	type_init(pxa2xx_gpio_register_types)