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1 | /* Support for generating ACPI tables and passing them to Guests | |
2 | * | |
3 | * ARM virt ACPI generation | |
4 | * | |
5 | * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> | |
6 | * Copyright (C) 2006 Fabrice Bellard | |
7 | * Copyright (C) 2013 Red Hat Inc | |
8 | * | |
9 | * Author: Michael S. Tsirkin <mst@redhat.com> | |
10 | * | |
11 | * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD. | |
12 | * | |
13 | * Author: Shannon Zhao <zhaoshenglong@huawei.com> | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or modify | |
16 | * it under the terms of the GNU General Public License as published by | |
17 | * the Free Software Foundation; either version 2 of the License, or | |
18 | * (at your option) any later version. | |
19 | ||
20 | * This program is distributed in the hope that it will be useful, | |
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
23 | * GNU General Public License for more details. | |
24 | ||
25 | * You should have received a copy of the GNU General Public License along | |
26 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
27 | */ | |
28 | ||
29 | #include "qemu/osdep.h" | |
30 | #include "qapi/error.h" | |
31 | #include "qemu/bitmap.h" | |
32 | #include "qemu/error-report.h" | |
33 | #include "trace.h" | |
34 | #include "hw/core/cpu.h" | |
35 | #include "target/arm/cpu.h" | |
36 | #include "hw/acpi/acpi-defs.h" | |
37 | #include "hw/acpi/acpi.h" | |
38 | #include "hw/nvram/fw_cfg_acpi.h" | |
39 | #include "hw/acpi/bios-linker-loader.h" | |
40 | #include "hw/acpi/aml-build.h" | |
41 | #include "hw/acpi/utils.h" | |
42 | #include "hw/acpi/pci.h" | |
43 | #include "hw/acpi/memory_hotplug.h" | |
44 | #include "hw/acpi/generic_event_device.h" | |
45 | #include "hw/acpi/tpm.h" | |
46 | #include "hw/acpi/hmat.h" | |
47 | #include "hw/pci/pcie_host.h" | |
48 | #include "hw/pci/pci.h" | |
49 | #include "hw/pci/pci_bus.h" | |
50 | #include "hw/pci-host/gpex.h" | |
51 | #include "hw/arm/virt.h" | |
52 | #include "hw/intc/arm_gicv3_its_common.h" | |
53 | #include "hw/mem/nvdimm.h" | |
54 | #include "hw/platform-bus.h" | |
55 | #include "sysemu/numa.h" | |
56 | #include "sysemu/reset.h" | |
57 | #include "sysemu/tpm.h" | |
58 | #include "migration/vmstate.h" | |
59 | #include "hw/acpi/ghes.h" | |
60 | #include "hw/acpi/viot.h" | |
61 | #include "hw/virtio/virtio-acpi.h" | |
62 | ||
63 | #define ARM_SPI_BASE 32 | |
64 | ||
65 | #define ACPI_BUILD_TABLE_SIZE 0x20000 | |
66 | ||
67 | static void acpi_dsdt_add_cpus(Aml *scope, VirtMachineState *vms) | |
68 | { | |
69 | MachineState *ms = MACHINE(vms); | |
70 | uint16_t i; | |
71 | ||
72 | for (i = 0; i < ms->smp.cpus; i++) { | |
73 | Aml *dev = aml_device("C%.03X", i); | |
74 | aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007"))); | |
75 | aml_append(dev, aml_name_decl("_UID", aml_int(i))); | |
76 | aml_append(scope, dev); | |
77 | } | |
78 | } | |
79 | ||
80 | static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap, | |
81 | uint32_t uart_irq) | |
82 | { | |
83 | Aml *dev = aml_device("COM0"); | |
84 | aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0011"))); | |
85 | aml_append(dev, aml_name_decl("_UID", aml_int(0))); | |
86 | ||
87 | Aml *crs = aml_resource_template(); | |
88 | aml_append(crs, aml_memory32_fixed(uart_memmap->base, | |
89 | uart_memmap->size, AML_READ_WRITE)); | |
90 | aml_append(crs, | |
91 | aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, | |
92 | AML_EXCLUSIVE, &uart_irq, 1)); | |
93 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
94 | ||
95 | aml_append(scope, dev); | |
96 | } | |
97 | ||
98 | static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap) | |
99 | { | |
100 | Aml *dev, *crs; | |
101 | hwaddr base = flash_memmap->base; | |
102 | hwaddr size = flash_memmap->size / 2; | |
103 | ||
104 | dev = aml_device("FLS0"); | |
105 | aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015"))); | |
106 | aml_append(dev, aml_name_decl("_UID", aml_int(0))); | |
107 | ||
108 | crs = aml_resource_template(); | |
109 | aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE)); | |
110 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
111 | aml_append(scope, dev); | |
112 | ||
113 | dev = aml_device("FLS1"); | |
114 | aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015"))); | |
115 | aml_append(dev, aml_name_decl("_UID", aml_int(1))); | |
116 | crs = aml_resource_template(); | |
117 | aml_append(crs, aml_memory32_fixed(base + size, size, AML_READ_WRITE)); | |
118 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
119 | aml_append(scope, dev); | |
120 | } | |
121 | ||
122 | static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, | |
123 | uint32_t irq, VirtMachineState *vms) | |
124 | { | |
125 | int ecam_id = VIRT_ECAM_ID(vms->highmem_ecam); | |
126 | struct GPEXConfig cfg = { | |
127 | .mmio32 = memmap[VIRT_PCIE_MMIO], | |
128 | .pio = memmap[VIRT_PCIE_PIO], | |
129 | .ecam = memmap[ecam_id], | |
130 | .irq = irq, | |
131 | .bus = vms->bus, | |
132 | }; | |
133 | ||
134 | if (vms->highmem_mmio) { | |
135 | cfg.mmio64 = memmap[VIRT_HIGH_PCIE_MMIO]; | |
136 | } | |
137 | ||
138 | acpi_dsdt_add_gpex(scope, &cfg); | |
139 | } | |
140 | ||
141 | static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap, | |
142 | uint32_t gpio_irq) | |
143 | { | |
144 | Aml *dev = aml_device("GPO0"); | |
145 | aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0061"))); | |
146 | aml_append(dev, aml_name_decl("_UID", aml_int(0))); | |
147 | ||
148 | Aml *crs = aml_resource_template(); | |
149 | aml_append(crs, aml_memory32_fixed(gpio_memmap->base, gpio_memmap->size, | |
150 | AML_READ_WRITE)); | |
151 | aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, | |
152 | AML_EXCLUSIVE, &gpio_irq, 1)); | |
153 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
154 | ||
155 | Aml *aei = aml_resource_template(); | |
156 | /* Pin 3 for power button */ | |
157 | const uint32_t pin_list[1] = {3}; | |
158 | aml_append(aei, aml_gpio_int(AML_CONSUMER, AML_EDGE, AML_ACTIVE_HIGH, | |
159 | AML_EXCLUSIVE, AML_PULL_UP, 0, pin_list, 1, | |
160 | "GPO0", NULL, 0)); | |
161 | aml_append(dev, aml_name_decl("_AEI", aei)); | |
162 | ||
163 | /* _E03 is handle for power button */ | |
164 | Aml *method = aml_method("_E03", 0, AML_NOTSERIALIZED); | |
165 | aml_append(method, aml_notify(aml_name(ACPI_POWER_BUTTON_DEVICE), | |
166 | aml_int(0x80))); | |
167 | aml_append(dev, method); | |
168 | aml_append(scope, dev); | |
169 | } | |
170 | ||
171 | #ifdef CONFIG_TPM | |
172 | static void acpi_dsdt_add_tpm(Aml *scope, VirtMachineState *vms) | |
173 | { | |
174 | PlatformBusDevice *pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev); | |
175 | hwaddr pbus_base = vms->memmap[VIRT_PLATFORM_BUS].base; | |
176 | SysBusDevice *sbdev = SYS_BUS_DEVICE(tpm_find()); | |
177 | MemoryRegion *sbdev_mr; | |
178 | hwaddr tpm_base; | |
179 | ||
180 | if (!sbdev) { | |
181 | return; | |
182 | } | |
183 | ||
184 | tpm_base = platform_bus_get_mmio_addr(pbus, sbdev, 0); | |
185 | assert(tpm_base != -1); | |
186 | ||
187 | tpm_base += pbus_base; | |
188 | ||
189 | sbdev_mr = sysbus_mmio_get_region(sbdev, 0); | |
190 | ||
191 | Aml *dev = aml_device("TPM0"); | |
192 | aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); | |
193 | aml_append(dev, aml_name_decl("_STR", aml_string("TPM 2.0 Device"))); | |
194 | aml_append(dev, aml_name_decl("_UID", aml_int(0))); | |
195 | ||
196 | Aml *crs = aml_resource_template(); | |
197 | aml_append(crs, | |
198 | aml_memory32_fixed(tpm_base, | |
199 | (uint32_t)memory_region_size(sbdev_mr), | |
200 | AML_READ_WRITE)); | |
201 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
202 | aml_append(scope, dev); | |
203 | } | |
204 | #endif | |
205 | ||
206 | #define ID_MAPPING_ENTRY_SIZE 20 | |
207 | #define SMMU_V3_ENTRY_SIZE 68 | |
208 | #define ROOT_COMPLEX_ENTRY_SIZE 36 | |
209 | #define IORT_NODE_OFFSET 48 | |
210 | ||
211 | static void build_iort_id_mapping(GArray *table_data, uint32_t input_base, | |
212 | uint32_t id_count, uint32_t out_ref) | |
213 | { | |
214 | /* Table 4 ID mapping format */ | |
215 | build_append_int_noprefix(table_data, input_base, 4); /* Input base */ | |
216 | build_append_int_noprefix(table_data, id_count, 4); /* Number of IDs */ | |
217 | build_append_int_noprefix(table_data, input_base, 4); /* Output base */ | |
218 | build_append_int_noprefix(table_data, out_ref, 4); /* Output Reference */ | |
219 | /* Flags */ | |
220 | build_append_int_noprefix(table_data, 0 /* Single mapping (disabled) */, 4); | |
221 | } | |
222 | ||
223 | struct AcpiIortIdMapping { | |
224 | uint32_t input_base; | |
225 | uint32_t id_count; | |
226 | }; | |
227 | typedef struct AcpiIortIdMapping AcpiIortIdMapping; | |
228 | ||
229 | /* Build the iort ID mapping to SMMUv3 for a given PCI host bridge */ | |
230 | static int | |
231 | iort_host_bridges(Object *obj, void *opaque) | |
232 | { | |
233 | GArray *idmap_blob = opaque; | |
234 | ||
235 | if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { | |
236 | PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; | |
237 | ||
238 | if (bus && !pci_bus_bypass_iommu(bus)) { | |
239 | int min_bus, max_bus; | |
240 | ||
241 | pci_bus_range(bus, &min_bus, &max_bus); | |
242 | ||
243 | AcpiIortIdMapping idmap = { | |
244 | .input_base = min_bus << 8, | |
245 | .id_count = (max_bus - min_bus + 1) << 8, | |
246 | }; | |
247 | g_array_append_val(idmap_blob, idmap); | |
248 | } | |
249 | } | |
250 | ||
251 | return 0; | |
252 | } | |
253 | ||
254 | static int iort_idmap_compare(gconstpointer a, gconstpointer b) | |
255 | { | |
256 | AcpiIortIdMapping *idmap_a = (AcpiIortIdMapping *)a; | |
257 | AcpiIortIdMapping *idmap_b = (AcpiIortIdMapping *)b; | |
258 | ||
259 | return idmap_a->input_base - idmap_b->input_base; | |
260 | } | |
261 | ||
262 | /* | |
263 | * Input Output Remapping Table (IORT) | |
264 | * Conforms to "IO Remapping Table System Software on ARM Platforms", | |
265 | * Document number: ARM DEN 0049E.b, Feb 2021 | |
266 | */ | |
267 | static void | |
268 | build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) | |
269 | { | |
270 | int i, nb_nodes, rc_mapping_count; | |
271 | const uint32_t iort_node_offset = IORT_NODE_OFFSET; | |
272 | size_t node_size, smmu_offset = 0; | |
273 | AcpiIortIdMapping *idmap; | |
274 | uint32_t id = 0; | |
275 | GArray *smmu_idmaps = g_array_new(false, true, sizeof(AcpiIortIdMapping)); | |
276 | GArray *its_idmaps = g_array_new(false, true, sizeof(AcpiIortIdMapping)); | |
277 | ||
278 | AcpiTable table = { .sig = "IORT", .rev = 3, .oem_id = vms->oem_id, | |
279 | .oem_table_id = vms->oem_table_id }; | |
280 | /* Table 2 The IORT */ | |
281 | acpi_table_begin(&table, table_data); | |
282 | ||
283 | if (vms->iommu == VIRT_IOMMU_SMMUV3) { | |
284 | AcpiIortIdMapping next_range = {0}; | |
285 | ||
286 | object_child_foreach_recursive(object_get_root(), | |
287 | iort_host_bridges, smmu_idmaps); | |
288 | ||
289 | /* Sort the smmu idmap by input_base */ | |
290 | g_array_sort(smmu_idmaps, iort_idmap_compare); | |
291 | ||
292 | /* | |
293 | * Split the whole RIDs by mapping from RC to SMMU, | |
294 | * build the ID mapping from RC to ITS directly. | |
295 | */ | |
296 | for (i = 0; i < smmu_idmaps->len; i++) { | |
297 | idmap = &g_array_index(smmu_idmaps, AcpiIortIdMapping, i); | |
298 | ||
299 | if (next_range.input_base < idmap->input_base) { | |
300 | next_range.id_count = idmap->input_base - next_range.input_base; | |
301 | g_array_append_val(its_idmaps, next_range); | |
302 | } | |
303 | ||
304 | next_range.input_base = idmap->input_base + idmap->id_count; | |
305 | } | |
306 | ||
307 | /* Append the last RC -> ITS ID mapping */ | |
308 | if (next_range.input_base < 0xFFFF) { | |
309 | next_range.id_count = 0xFFFF - next_range.input_base; | |
310 | g_array_append_val(its_idmaps, next_range); | |
311 | } | |
312 | ||
313 | nb_nodes = 3; /* RC, ITS, SMMUv3 */ | |
314 | rc_mapping_count = smmu_idmaps->len + its_idmaps->len; | |
315 | } else { | |
316 | nb_nodes = 2; /* RC, ITS */ | |
317 | rc_mapping_count = 1; | |
318 | } | |
319 | /* Number of IORT Nodes */ | |
320 | build_append_int_noprefix(table_data, nb_nodes, 4); | |
321 | ||
322 | /* Offset to Array of IORT Nodes */ | |
323 | build_append_int_noprefix(table_data, IORT_NODE_OFFSET, 4); | |
324 | build_append_int_noprefix(table_data, 0, 4); /* Reserved */ | |
325 | ||
326 | /* Table 12 ITS Group Format */ | |
327 | build_append_int_noprefix(table_data, 0 /* ITS Group */, 1); /* Type */ | |
328 | node_size = 20 /* fixed header size */ + 4 /* 1 GIC ITS Identifier */; | |
329 | build_append_int_noprefix(table_data, node_size, 2); /* Length */ | |
330 | build_append_int_noprefix(table_data, 1, 1); /* Revision */ | |
331 | build_append_int_noprefix(table_data, id++, 4); /* Identifier */ | |
332 | build_append_int_noprefix(table_data, 0, 4); /* Number of ID mappings */ | |
333 | build_append_int_noprefix(table_data, 0, 4); /* Reference to ID Array */ | |
334 | build_append_int_noprefix(table_data, 1, 4); /* Number of ITSs */ | |
335 | /* GIC ITS Identifier Array */ | |
336 | build_append_int_noprefix(table_data, 0 /* MADT translation_id */, 4); | |
337 | ||
338 | if (vms->iommu == VIRT_IOMMU_SMMUV3) { | |
339 | int irq = vms->irqmap[VIRT_SMMU] + ARM_SPI_BASE; | |
340 | ||
341 | smmu_offset = table_data->len - table.table_offset; | |
342 | /* Table 9 SMMUv3 Format */ | |
343 | build_append_int_noprefix(table_data, 4 /* SMMUv3 */, 1); /* Type */ | |
344 | node_size = SMMU_V3_ENTRY_SIZE + ID_MAPPING_ENTRY_SIZE; | |
345 | build_append_int_noprefix(table_data, node_size, 2); /* Length */ | |
346 | build_append_int_noprefix(table_data, 4, 1); /* Revision */ | |
347 | build_append_int_noprefix(table_data, id++, 4); /* Identifier */ | |
348 | build_append_int_noprefix(table_data, 1, 4); /* Number of ID mappings */ | |
349 | /* Reference to ID Array */ | |
350 | build_append_int_noprefix(table_data, SMMU_V3_ENTRY_SIZE, 4); | |
351 | /* Base address */ | |
352 | build_append_int_noprefix(table_data, vms->memmap[VIRT_SMMU].base, 8); | |
353 | /* Flags */ | |
354 | build_append_int_noprefix(table_data, 1 /* COHACC Override */, 4); | |
355 | build_append_int_noprefix(table_data, 0, 4); /* Reserved */ | |
356 | build_append_int_noprefix(table_data, 0, 8); /* VATOS address */ | |
357 | /* Model */ | |
358 | build_append_int_noprefix(table_data, 0 /* Generic SMMU-v3 */, 4); | |
359 | build_append_int_noprefix(table_data, irq, 4); /* Event */ | |
360 | build_append_int_noprefix(table_data, irq + 1, 4); /* PRI */ | |
361 | build_append_int_noprefix(table_data, irq + 3, 4); /* GERR */ | |
362 | build_append_int_noprefix(table_data, irq + 2, 4); /* Sync */ | |
363 | build_append_int_noprefix(table_data, 0, 4); /* Proximity domain */ | |
364 | /* DeviceID mapping index (ignored since interrupts are GSIV based) */ | |
365 | build_append_int_noprefix(table_data, 0, 4); | |
366 | ||
367 | /* output IORT node is the ITS group node (the first node) */ | |
368 | build_iort_id_mapping(table_data, 0, 0xFFFF, IORT_NODE_OFFSET); | |
369 | } | |
370 | ||
371 | /* Table 17 Root Complex Node */ | |
372 | build_append_int_noprefix(table_data, 2 /* Root complex */, 1); /* Type */ | |
373 | node_size = ROOT_COMPLEX_ENTRY_SIZE + | |
374 | ID_MAPPING_ENTRY_SIZE * rc_mapping_count; | |
375 | build_append_int_noprefix(table_data, node_size, 2); /* Length */ | |
376 | build_append_int_noprefix(table_data, 3, 1); /* Revision */ | |
377 | build_append_int_noprefix(table_data, id++, 4); /* Identifier */ | |
378 | /* Number of ID mappings */ | |
379 | build_append_int_noprefix(table_data, rc_mapping_count, 4); | |
380 | /* Reference to ID Array */ | |
381 | build_append_int_noprefix(table_data, ROOT_COMPLEX_ENTRY_SIZE, 4); | |
382 | ||
383 | /* Table 14 Memory access properties */ | |
384 | /* CCA: Cache Coherent Attribute */ | |
385 | build_append_int_noprefix(table_data, 1 /* fully coherent */, 4); | |
386 | build_append_int_noprefix(table_data, 0, 1); /* AH: Note Allocation Hints */ | |
387 | build_append_int_noprefix(table_data, 0, 2); /* Reserved */ | |
388 | /* Table 15 Memory Access Flags */ | |
389 | build_append_int_noprefix(table_data, 0x3 /* CCA = CPM = DACS = 1 */, 1); | |
390 | ||
391 | build_append_int_noprefix(table_data, 0, 4); /* ATS Attribute */ | |
392 | /* MCFG pci_segment */ | |
393 | build_append_int_noprefix(table_data, 0, 4); /* PCI Segment number */ | |
394 | ||
395 | /* Memory address size limit */ | |
396 | build_append_int_noprefix(table_data, 64, 1); | |
397 | ||
398 | build_append_int_noprefix(table_data, 0, 3); /* Reserved */ | |
399 | ||
400 | /* Output Reference */ | |
401 | if (vms->iommu == VIRT_IOMMU_SMMUV3) { | |
402 | AcpiIortIdMapping *range; | |
403 | ||
404 | /* translated RIDs connect to SMMUv3 node: RC -> SMMUv3 -> ITS */ | |
405 | for (i = 0; i < smmu_idmaps->len; i++) { | |
406 | range = &g_array_index(smmu_idmaps, AcpiIortIdMapping, i); | |
407 | /* output IORT node is the smmuv3 node */ | |
408 | build_iort_id_mapping(table_data, range->input_base, | |
409 | range->id_count, smmu_offset); | |
410 | } | |
411 | ||
412 | /* bypassed RIDs connect to ITS group node directly: RC -> ITS */ | |
413 | for (i = 0; i < its_idmaps->len; i++) { | |
414 | range = &g_array_index(its_idmaps, AcpiIortIdMapping, i); | |
415 | /* output IORT node is the ITS group node (the first node) */ | |
416 | build_iort_id_mapping(table_data, range->input_base, | |
417 | range->id_count, iort_node_offset); | |
418 | } | |
419 | } else { | |
420 | /* output IORT node is the ITS group node (the first node) */ | |
421 | build_iort_id_mapping(table_data, 0, 0xFFFF, IORT_NODE_OFFSET); | |
422 | } | |
423 | ||
424 | acpi_table_end(linker, &table); | |
425 | g_array_free(smmu_idmaps, true); | |
426 | g_array_free(its_idmaps, true); | |
427 | } | |
428 | ||
429 | /* | |
430 | * Serial Port Console Redirection Table (SPCR) | |
431 | * Rev: 1.07 | |
432 | */ | |
433 | static void | |
434 | build_spcr(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) | |
435 | { | |
436 | AcpiTable table = { .sig = "SPCR", .rev = 2, .oem_id = vms->oem_id, | |
437 | .oem_table_id = vms->oem_table_id }; | |
438 | ||
439 | acpi_table_begin(&table, table_data); | |
440 | ||
441 | /* Interface Type */ | |
442 | build_append_int_noprefix(table_data, 3, 1); /* ARM PL011 UART */ | |
443 | build_append_int_noprefix(table_data, 0, 3); /* Reserved */ | |
444 | /* Base Address */ | |
445 | build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 32, 0, 3, | |
446 | vms->memmap[VIRT_UART].base); | |
447 | /* Interrupt Type */ | |
448 | build_append_int_noprefix(table_data, | |
449 | (1 << 3) /* Bit[3] ARMH GIC interrupt */, 1); | |
450 | build_append_int_noprefix(table_data, 0, 1); /* IRQ */ | |
451 | /* Global System Interrupt */ | |
452 | build_append_int_noprefix(table_data, | |
453 | vms->irqmap[VIRT_UART] + ARM_SPI_BASE, 4); | |
454 | build_append_int_noprefix(table_data, 3 /* 9600 */, 1); /* Baud Rate */ | |
455 | build_append_int_noprefix(table_data, 0 /* No Parity */, 1); /* Parity */ | |
456 | /* Stop Bits */ | |
457 | build_append_int_noprefix(table_data, 1 /* 1 Stop bit */, 1); | |
458 | /* Flow Control */ | |
459 | build_append_int_noprefix(table_data, | |
460 | (1 << 1) /* RTS/CTS hardware flow control */, 1); | |
461 | /* Terminal Type */ | |
462 | build_append_int_noprefix(table_data, 0 /* VT100 */, 1); | |
463 | build_append_int_noprefix(table_data, 0, 1); /* Language */ | |
464 | /* PCI Device ID */ | |
465 | build_append_int_noprefix(table_data, 0xffff /* not a PCI device*/, 2); | |
466 | /* PCI Vendor ID */ | |
467 | build_append_int_noprefix(table_data, 0xffff /* not a PCI device*/, 2); | |
468 | build_append_int_noprefix(table_data, 0, 1); /* PCI Bus Number */ | |
469 | build_append_int_noprefix(table_data, 0, 1); /* PCI Device Number */ | |
470 | build_append_int_noprefix(table_data, 0, 1); /* PCI Function Number */ | |
471 | build_append_int_noprefix(table_data, 0, 4); /* PCI Flags */ | |
472 | build_append_int_noprefix(table_data, 0, 1); /* PCI Segment */ | |
473 | build_append_int_noprefix(table_data, 0, 4); /* Reserved */ | |
474 | ||
475 | acpi_table_end(linker, &table); | |
476 | } | |
477 | ||
478 | /* | |
479 | * ACPI spec, Revision 5.1 | |
480 | * 5.2.16 System Resource Affinity Table (SRAT) | |
481 | */ | |
482 | static void | |
483 | build_srat(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) | |
484 | { | |
485 | int i; | |
486 | uint64_t mem_base; | |
487 | MachineClass *mc = MACHINE_GET_CLASS(vms); | |
488 | MachineState *ms = MACHINE(vms); | |
489 | const CPUArchIdList *cpu_list = mc->possible_cpu_arch_ids(ms); | |
490 | AcpiTable table = { .sig = "SRAT", .rev = 3, .oem_id = vms->oem_id, | |
491 | .oem_table_id = vms->oem_table_id }; | |
492 | ||
493 | acpi_table_begin(&table, table_data); | |
494 | build_append_int_noprefix(table_data, 1, 4); /* Reserved */ | |
495 | build_append_int_noprefix(table_data, 0, 8); /* Reserved */ | |
496 | ||
497 | for (i = 0; i < cpu_list->len; ++i) { | |
498 | uint32_t nodeid = cpu_list->cpus[i].props.node_id; | |
499 | /* | |
500 | * 5.2.16.4 GICC Affinity Structure | |
501 | */ | |
502 | build_append_int_noprefix(table_data, 3, 1); /* Type */ | |
503 | build_append_int_noprefix(table_data, 18, 1); /* Length */ | |
504 | build_append_int_noprefix(table_data, nodeid, 4); /* Proximity Domain */ | |
505 | build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */ | |
506 | /* Flags, Table 5-76 */ | |
507 | build_append_int_noprefix(table_data, 1 /* Enabled */, 4); | |
508 | build_append_int_noprefix(table_data, 0, 4); /* Clock Domain */ | |
509 | } | |
510 | ||
511 | mem_base = vms->memmap[VIRT_MEM].base; | |
512 | for (i = 0; i < ms->numa_state->num_nodes; ++i) { | |
513 | if (ms->numa_state->nodes[i].node_mem > 0) { | |
514 | build_srat_memory(table_data, mem_base, | |
515 | ms->numa_state->nodes[i].node_mem, i, | |
516 | MEM_AFFINITY_ENABLED); | |
517 | mem_base += ms->numa_state->nodes[i].node_mem; | |
518 | } | |
519 | } | |
520 | ||
521 | if (ms->nvdimms_state->is_enabled) { | |
522 | nvdimm_build_srat(table_data); | |
523 | } | |
524 | ||
525 | if (ms->device_memory) { | |
526 | build_srat_memory(table_data, ms->device_memory->base, | |
527 | memory_region_size(&ms->device_memory->mr), | |
528 | ms->numa_state->num_nodes - 1, | |
529 | MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED); | |
530 | } | |
531 | ||
532 | acpi_table_end(linker, &table); | |
533 | } | |
534 | ||
535 | /* | |
536 | * ACPI spec, Revision 5.1 | |
537 | * 5.2.24 Generic Timer Description Table (GTDT) | |
538 | */ | |
539 | static void | |
540 | build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) | |
541 | { | |
542 | VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); | |
543 | /* | |
544 | * Table 5-117 Flag Definitions | |
545 | * set only "Timer interrupt Mode" and assume "Timer Interrupt | |
546 | * polarity" bit as '0: Interrupt is Active high' | |
547 | */ | |
548 | uint32_t irqflags = vmc->claim_edge_triggered_timers ? | |
549 | 1 : /* Interrupt is Edge triggered */ | |
550 | 0; /* Interrupt is Level triggered */ | |
551 | AcpiTable table = { .sig = "GTDT", .rev = 2, .oem_id = vms->oem_id, | |
552 | .oem_table_id = vms->oem_table_id }; | |
553 | ||
554 | acpi_table_begin(&table, table_data); | |
555 | ||
556 | /* CntControlBase Physical Address */ | |
557 | build_append_int_noprefix(table_data, 0xFFFFFFFFFFFFFFFF, 8); | |
558 | build_append_int_noprefix(table_data, 0, 4); /* Reserved */ | |
559 | /* | |
560 | * FIXME: clarify comment: | |
561 | * The interrupt values are the same with the device tree when adding 16 | |
562 | */ | |
563 | /* Secure EL1 timer GSIV */ | |
564 | build_append_int_noprefix(table_data, ARCH_TIMER_S_EL1_IRQ, 4); | |
565 | /* Secure EL1 timer Flags */ | |
566 | build_append_int_noprefix(table_data, irqflags, 4); | |
567 | /* Non-Secure EL1 timer GSIV */ | |
568 | build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL1_IRQ, 4); | |
569 | /* Non-Secure EL1 timer Flags */ | |
570 | build_append_int_noprefix(table_data, irqflags | | |
571 | 1UL << 2, /* Always-on Capability */ | |
572 | 4); | |
573 | /* Virtual timer GSIV */ | |
574 | build_append_int_noprefix(table_data, ARCH_TIMER_VIRT_IRQ, 4); | |
575 | /* Virtual Timer Flags */ | |
576 | build_append_int_noprefix(table_data, irqflags, 4); | |
577 | /* Non-Secure EL2 timer GSIV */ | |
578 | build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL2_IRQ, 4); | |
579 | /* Non-Secure EL2 timer Flags */ | |
580 | build_append_int_noprefix(table_data, irqflags, 4); | |
581 | /* CntReadBase Physical address */ | |
582 | build_append_int_noprefix(table_data, 0xFFFFFFFFFFFFFFFF, 8); | |
583 | /* Platform Timer Count */ | |
584 | build_append_int_noprefix(table_data, 0, 4); | |
585 | /* Platform Timer Offset */ | |
586 | build_append_int_noprefix(table_data, 0, 4); | |
587 | ||
588 | acpi_table_end(linker, &table); | |
589 | } | |
590 | ||
591 | /* Debug Port Table 2 (DBG2) */ | |
592 | static void | |
593 | build_dbg2(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) | |
594 | { | |
595 | AcpiTable table = { .sig = "DBG2", .rev = 0, .oem_id = vms->oem_id, | |
596 | .oem_table_id = vms->oem_table_id }; | |
597 | int dbg2devicelength; | |
598 | const char name[] = "COM0"; | |
599 | const int namespace_length = sizeof(name); | |
600 | ||
601 | acpi_table_begin(&table, table_data); | |
602 | ||
603 | dbg2devicelength = 22 + /* BaseAddressRegister[] offset */ | |
604 | 12 + /* BaseAddressRegister[] */ | |
605 | 4 + /* AddressSize[] */ | |
606 | namespace_length /* NamespaceString[] */; | |
607 | ||
608 | /* OffsetDbgDeviceInfo */ | |
609 | build_append_int_noprefix(table_data, 44, 4); | |
610 | /* NumberDbgDeviceInfo */ | |
611 | build_append_int_noprefix(table_data, 1, 4); | |
612 | ||
613 | /* Table 2. Debug Device Information structure format */ | |
614 | build_append_int_noprefix(table_data, 0, 1); /* Revision */ | |
615 | build_append_int_noprefix(table_data, dbg2devicelength, 2); /* Length */ | |
616 | /* NumberofGenericAddressRegisters */ | |
617 | build_append_int_noprefix(table_data, 1, 1); | |
618 | /* NameSpaceStringLength */ | |
619 | build_append_int_noprefix(table_data, namespace_length, 2); | |
620 | build_append_int_noprefix(table_data, 38, 2); /* NameSpaceStringOffset */ | |
621 | build_append_int_noprefix(table_data, 0, 2); /* OemDataLength */ | |
622 | /* OemDataOffset (0 means no OEM data) */ | |
623 | build_append_int_noprefix(table_data, 0, 2); | |
624 | ||
625 | /* Port Type */ | |
626 | build_append_int_noprefix(table_data, 0x8000 /* Serial */, 2); | |
627 | /* Port Subtype */ | |
628 | build_append_int_noprefix(table_data, 0x3 /* ARM PL011 UART */, 2); | |
629 | build_append_int_noprefix(table_data, 0, 2); /* Reserved */ | |
630 | /* BaseAddressRegisterOffset */ | |
631 | build_append_int_noprefix(table_data, 22, 2); | |
632 | /* AddressSizeOffset */ | |
633 | build_append_int_noprefix(table_data, 34, 2); | |
634 | ||
635 | /* BaseAddressRegister[] */ | |
636 | build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 32, 0, 3, | |
637 | vms->memmap[VIRT_UART].base); | |
638 | ||
639 | /* AddressSize[] */ | |
640 | build_append_int_noprefix(table_data, | |
641 | vms->memmap[VIRT_UART].size, 4); | |
642 | ||
643 | /* NamespaceString[] */ | |
644 | g_array_append_vals(table_data, name, namespace_length); | |
645 | ||
646 | acpi_table_end(linker, &table); | |
647 | }; | |
648 | ||
649 | /* | |
650 | * ACPI spec, Revision 6.0 Errata A | |
651 | * 5.2.12 Multiple APIC Description Table (MADT) | |
652 | */ | |
653 | static void build_append_gicr(GArray *table_data, uint64_t base, uint32_t size) | |
654 | { | |
655 | build_append_int_noprefix(table_data, 0xE, 1); /* Type */ | |
656 | build_append_int_noprefix(table_data, 16, 1); /* Length */ | |
657 | build_append_int_noprefix(table_data, 0, 2); /* Reserved */ | |
658 | /* Discovery Range Base Address */ | |
659 | build_append_int_noprefix(table_data, base, 8); | |
660 | build_append_int_noprefix(table_data, size, 4); /* Discovery Range Length */ | |
661 | } | |
662 | ||
663 | static void | |
664 | build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) | |
665 | { | |
666 | int i; | |
667 | VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); | |
668 | const MemMapEntry *memmap = vms->memmap; | |
669 | AcpiTable table = { .sig = "APIC", .rev = 4, .oem_id = vms->oem_id, | |
670 | .oem_table_id = vms->oem_table_id }; | |
671 | ||
672 | acpi_table_begin(&table, table_data); | |
673 | /* Local Interrupt Controller Address */ | |
674 | build_append_int_noprefix(table_data, 0, 4); | |
675 | build_append_int_noprefix(table_data, 0, 4); /* Flags */ | |
676 | ||
677 | /* 5.2.12.15 GIC Distributor Structure */ | |
678 | build_append_int_noprefix(table_data, 0xC, 1); /* Type */ | |
679 | build_append_int_noprefix(table_data, 24, 1); /* Length */ | |
680 | build_append_int_noprefix(table_data, 0, 2); /* Reserved */ | |
681 | build_append_int_noprefix(table_data, 0, 4); /* GIC ID */ | |
682 | /* Physical Base Address */ | |
683 | build_append_int_noprefix(table_data, memmap[VIRT_GIC_DIST].base, 8); | |
684 | build_append_int_noprefix(table_data, 0, 4); /* System Vector Base */ | |
685 | /* GIC version */ | |
686 | build_append_int_noprefix(table_data, vms->gic_version, 1); | |
687 | build_append_int_noprefix(table_data, 0, 3); /* Reserved */ | |
688 | ||
689 | for (i = 0; i < MACHINE(vms)->smp.cpus; i++) { | |
690 | ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i)); | |
691 | uint64_t physical_base_address = 0, gich = 0, gicv = 0; | |
692 | uint32_t vgic_interrupt = vms->virt ? ARCH_GIC_MAINT_IRQ : 0; | |
693 | uint32_t pmu_interrupt = arm_feature(&armcpu->env, ARM_FEATURE_PMU) ? | |
694 | VIRTUAL_PMU_IRQ : 0; | |
695 | ||
696 | if (vms->gic_version == VIRT_GIC_VERSION_2) { | |
697 | physical_base_address = memmap[VIRT_GIC_CPU].base; | |
698 | gicv = memmap[VIRT_GIC_VCPU].base; | |
699 | gich = memmap[VIRT_GIC_HYP].base; | |
700 | } | |
701 | ||
702 | /* 5.2.12.14 GIC Structure */ | |
703 | build_append_int_noprefix(table_data, 0xB, 1); /* Type */ | |
704 | build_append_int_noprefix(table_data, 80, 1); /* Length */ | |
705 | build_append_int_noprefix(table_data, 0, 2); /* Reserved */ | |
706 | build_append_int_noprefix(table_data, i, 4); /* GIC ID */ | |
707 | build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */ | |
708 | /* Flags */ | |
709 | build_append_int_noprefix(table_data, 1, 4); /* Enabled */ | |
710 | /* Parking Protocol Version */ | |
711 | build_append_int_noprefix(table_data, 0, 4); | |
712 | /* Performance Interrupt GSIV */ | |
713 | build_append_int_noprefix(table_data, pmu_interrupt, 4); | |
714 | build_append_int_noprefix(table_data, 0, 8); /* Parked Address */ | |
715 | /* Physical Base Address */ | |
716 | build_append_int_noprefix(table_data, physical_base_address, 8); | |
717 | build_append_int_noprefix(table_data, gicv, 8); /* GICV */ | |
718 | build_append_int_noprefix(table_data, gich, 8); /* GICH */ | |
719 | /* VGIC Maintenance interrupt */ | |
720 | build_append_int_noprefix(table_data, vgic_interrupt, 4); | |
721 | build_append_int_noprefix(table_data, 0, 8); /* GICR Base Address*/ | |
722 | /* MPIDR */ | |
723 | build_append_int_noprefix(table_data, armcpu->mp_affinity, 8); | |
724 | /* Processor Power Efficiency Class */ | |
725 | build_append_int_noprefix(table_data, 0, 1); | |
726 | /* Reserved */ | |
727 | build_append_int_noprefix(table_data, 0, 3); | |
728 | } | |
729 | ||
730 | if (vms->gic_version != VIRT_GIC_VERSION_2) { | |
731 | build_append_gicr(table_data, memmap[VIRT_GIC_REDIST].base, | |
732 | memmap[VIRT_GIC_REDIST].size); | |
733 | if (virt_gicv3_redist_region_count(vms) == 2) { | |
734 | build_append_gicr(table_data, memmap[VIRT_HIGH_GIC_REDIST2].base, | |
735 | memmap[VIRT_HIGH_GIC_REDIST2].size); | |
736 | } | |
737 | ||
738 | if (its_class_name() && !vmc->no_its) { | |
739 | /* | |
740 | * ACPI spec, Revision 6.0 Errata A | |
741 | * (original 6.0 definition has invalid Length) | |
742 | * 5.2.12.18 GIC ITS Structure | |
743 | */ | |
744 | build_append_int_noprefix(table_data, 0xF, 1); /* Type */ | |
745 | build_append_int_noprefix(table_data, 20, 1); /* Length */ | |
746 | build_append_int_noprefix(table_data, 0, 2); /* Reserved */ | |
747 | build_append_int_noprefix(table_data, 0, 4); /* GIC ITS ID */ | |
748 | /* Physical Base Address */ | |
749 | build_append_int_noprefix(table_data, memmap[VIRT_GIC_ITS].base, 8); | |
750 | build_append_int_noprefix(table_data, 0, 4); /* Reserved */ | |
751 | } | |
752 | } else { | |
753 | const uint16_t spi_base = vms->irqmap[VIRT_GIC_V2M] + ARM_SPI_BASE; | |
754 | ||
755 | /* 5.2.12.16 GIC MSI Frame Structure */ | |
756 | build_append_int_noprefix(table_data, 0xD, 1); /* Type */ | |
757 | build_append_int_noprefix(table_data, 24, 1); /* Length */ | |
758 | build_append_int_noprefix(table_data, 0, 2); /* Reserved */ | |
759 | build_append_int_noprefix(table_data, 0, 4); /* GIC MSI Frame ID */ | |
760 | /* Physical Base Address */ | |
761 | build_append_int_noprefix(table_data, memmap[VIRT_GIC_V2M].base, 8); | |
762 | build_append_int_noprefix(table_data, 1, 4); /* Flags */ | |
763 | /* SPI Count */ | |
764 | build_append_int_noprefix(table_data, NUM_GICV2M_SPIS, 2); | |
765 | build_append_int_noprefix(table_data, spi_base, 2); /* SPI Base */ | |
766 | } | |
767 | acpi_table_end(linker, &table); | |
768 | } | |
769 | ||
770 | /* FADT */ | |
771 | static void build_fadt_rev6(GArray *table_data, BIOSLinker *linker, | |
772 | VirtMachineState *vms, unsigned dsdt_tbl_offset) | |
773 | { | |
774 | /* ACPI v6.0 */ | |
775 | AcpiFadtData fadt = { | |
776 | .rev = 6, | |
777 | .minor_ver = 0, | |
778 | .flags = 1 << ACPI_FADT_F_HW_REDUCED_ACPI, | |
779 | .xdsdt_tbl_offset = &dsdt_tbl_offset, | |
780 | }; | |
781 | ||
782 | switch (vms->psci_conduit) { | |
783 | case QEMU_PSCI_CONDUIT_DISABLED: | |
784 | fadt.arm_boot_arch = 0; | |
785 | break; | |
786 | case QEMU_PSCI_CONDUIT_HVC: | |
787 | fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT | | |
788 | ACPI_FADT_ARM_PSCI_USE_HVC; | |
789 | break; | |
790 | case QEMU_PSCI_CONDUIT_SMC: | |
791 | fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT; | |
792 | break; | |
793 | default: | |
794 | g_assert_not_reached(); | |
795 | } | |
796 | ||
797 | build_fadt(table_data, linker, &fadt, vms->oem_id, vms->oem_table_id); | |
798 | } | |
799 | ||
800 | /* DSDT */ | |
801 | static void | |
802 | build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) | |
803 | { | |
804 | VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); | |
805 | Aml *scope, *dsdt; | |
806 | MachineState *ms = MACHINE(vms); | |
807 | const MemMapEntry *memmap = vms->memmap; | |
808 | const int *irqmap = vms->irqmap; | |
809 | AcpiTable table = { .sig = "DSDT", .rev = 2, .oem_id = vms->oem_id, | |
810 | .oem_table_id = vms->oem_table_id }; | |
811 | ||
812 | acpi_table_begin(&table, table_data); | |
813 | dsdt = init_aml_allocator(); | |
814 | ||
815 | /* When booting the VM with UEFI, UEFI takes ownership of the RTC hardware. | |
816 | * While UEFI can use libfdt to disable the RTC device node in the DTB that | |
817 | * it passes to the OS, it cannot modify AML. Therefore, we won't generate | |
818 | * the RTC ACPI device at all when using UEFI. | |
819 | */ | |
820 | scope = aml_scope("\\_SB"); | |
821 | acpi_dsdt_add_cpus(scope, vms); | |
822 | acpi_dsdt_add_uart(scope, &memmap[VIRT_UART], | |
823 | (irqmap[VIRT_UART] + ARM_SPI_BASE)); | |
824 | if (vmc->acpi_expose_flash) { | |
825 | acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]); | |
826 | } | |
827 | fw_cfg_acpi_dsdt_add(scope, &memmap[VIRT_FW_CFG]); | |
828 | virtio_acpi_dsdt_add(scope, memmap[VIRT_MMIO].base, memmap[VIRT_MMIO].size, | |
829 | (irqmap[VIRT_MMIO] + ARM_SPI_BASE), | |
830 | 0, NUM_VIRTIO_TRANSPORTS); | |
831 | acpi_dsdt_add_pci(scope, memmap, irqmap[VIRT_PCIE] + ARM_SPI_BASE, vms); | |
832 | if (vms->acpi_dev) { | |
833 | build_ged_aml(scope, "\\_SB."GED_DEVICE, | |
834 | HOTPLUG_HANDLER(vms->acpi_dev), | |
835 | irqmap[VIRT_ACPI_GED] + ARM_SPI_BASE, AML_SYSTEM_MEMORY, | |
836 | memmap[VIRT_ACPI_GED].base); | |
837 | } else { | |
838 | acpi_dsdt_add_gpio(scope, &memmap[VIRT_GPIO], | |
839 | (irqmap[VIRT_GPIO] + ARM_SPI_BASE)); | |
840 | } | |
841 | ||
842 | if (vms->acpi_dev) { | |
843 | uint32_t event = object_property_get_uint(OBJECT(vms->acpi_dev), | |
844 | "ged-event", &error_abort); | |
845 | ||
846 | if (event & ACPI_GED_MEM_HOTPLUG_EVT) { | |
847 | build_memory_hotplug_aml(scope, ms->ram_slots, "\\_SB", NULL, | |
848 | AML_SYSTEM_MEMORY, | |
849 | memmap[VIRT_PCDIMM_ACPI].base); | |
850 | } | |
851 | } | |
852 | ||
853 | acpi_dsdt_add_power_button(scope); | |
854 | #ifdef CONFIG_TPM | |
855 | acpi_dsdt_add_tpm(scope, vms); | |
856 | #endif | |
857 | ||
858 | aml_append(dsdt, scope); | |
859 | ||
860 | /* copy AML table into ACPI tables blob */ | |
861 | g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); | |
862 | ||
863 | acpi_table_end(linker, &table); | |
864 | free_aml_allocator(); | |
865 | } | |
866 | ||
867 | typedef | |
868 | struct AcpiBuildState { | |
869 | /* Copy of table in RAM (for patching). */ | |
870 | MemoryRegion *table_mr; | |
871 | MemoryRegion *rsdp_mr; | |
872 | MemoryRegion *linker_mr; | |
873 | /* Is table patched? */ | |
874 | bool patched; | |
875 | } AcpiBuildState; | |
876 | ||
877 | static void acpi_align_size(GArray *blob, unsigned align) | |
878 | { | |
879 | /* | |
880 | * Align size to multiple of given size. This reduces the chance | |
881 | * we need to change size in the future (breaking cross version migration). | |
882 | */ | |
883 | g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); | |
884 | } | |
885 | ||
886 | static | |
887 | void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) | |
888 | { | |
889 | VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); | |
890 | GArray *table_offsets; | |
891 | unsigned dsdt, xsdt; | |
892 | GArray *tables_blob = tables->table_data; | |
893 | MachineState *ms = MACHINE(vms); | |
894 | ||
895 | table_offsets = g_array_new(false, true /* clear */, | |
896 | sizeof(uint32_t)); | |
897 | ||
898 | bios_linker_loader_alloc(tables->linker, | |
899 | ACPI_BUILD_TABLE_FILE, tables_blob, | |
900 | 64, false /* high memory */); | |
901 | ||
902 | /* DSDT is pointed to by FADT */ | |
903 | dsdt = tables_blob->len; | |
904 | build_dsdt(tables_blob, tables->linker, vms); | |
905 | ||
906 | /* FADT MADT PPTT GTDT MCFG SPCR DBG2 pointed to by RSDT */ | |
907 | acpi_add_table(table_offsets, tables_blob); | |
908 | build_fadt_rev6(tables_blob, tables->linker, vms, dsdt); | |
909 | ||
910 | acpi_add_table(table_offsets, tables_blob); | |
911 | build_madt(tables_blob, tables->linker, vms); | |
912 | ||
913 | if (!vmc->no_cpu_topology) { | |
914 | acpi_add_table(table_offsets, tables_blob); | |
915 | build_pptt(tables_blob, tables->linker, ms, | |
916 | vms->oem_id, vms->oem_table_id); | |
917 | } | |
918 | ||
919 | acpi_add_table(table_offsets, tables_blob); | |
920 | build_gtdt(tables_blob, tables->linker, vms); | |
921 | ||
922 | acpi_add_table(table_offsets, tables_blob); | |
923 | { | |
924 | AcpiMcfgInfo mcfg = { | |
925 | .base = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].base, | |
926 | .size = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].size, | |
927 | }; | |
928 | build_mcfg(tables_blob, tables->linker, &mcfg, vms->oem_id, | |
929 | vms->oem_table_id); | |
930 | } | |
931 | ||
932 | acpi_add_table(table_offsets, tables_blob); | |
933 | build_spcr(tables_blob, tables->linker, vms); | |
934 | ||
935 | acpi_add_table(table_offsets, tables_blob); | |
936 | build_dbg2(tables_blob, tables->linker, vms); | |
937 | ||
938 | if (vms->ras) { | |
939 | build_ghes_error_table(tables->hardware_errors, tables->linker); | |
940 | acpi_add_table(table_offsets, tables_blob); | |
941 | acpi_build_hest(tables_blob, tables->linker, vms->oem_id, | |
942 | vms->oem_table_id); | |
943 | } | |
944 | ||
945 | if (ms->numa_state->num_nodes > 0) { | |
946 | acpi_add_table(table_offsets, tables_blob); | |
947 | build_srat(tables_blob, tables->linker, vms); | |
948 | if (ms->numa_state->have_numa_distance) { | |
949 | acpi_add_table(table_offsets, tables_blob); | |
950 | build_slit(tables_blob, tables->linker, ms, vms->oem_id, | |
951 | vms->oem_table_id); | |
952 | } | |
953 | ||
954 | if (ms->numa_state->hmat_enabled) { | |
955 | acpi_add_table(table_offsets, tables_blob); | |
956 | build_hmat(tables_blob, tables->linker, ms->numa_state, | |
957 | vms->oem_id, vms->oem_table_id); | |
958 | } | |
959 | } | |
960 | ||
961 | if (ms->nvdimms_state->is_enabled) { | |
962 | nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, | |
963 | ms->nvdimms_state, ms->ram_slots, vms->oem_id, | |
964 | vms->oem_table_id); | |
965 | } | |
966 | ||
967 | if (its_class_name() && !vmc->no_its) { | |
968 | acpi_add_table(table_offsets, tables_blob); | |
969 | build_iort(tables_blob, tables->linker, vms); | |
970 | } | |
971 | ||
972 | #ifdef CONFIG_TPM | |
973 | if (tpm_get_version(tpm_find()) == TPM_VERSION_2_0) { | |
974 | acpi_add_table(table_offsets, tables_blob); | |
975 | build_tpm2(tables_blob, tables->linker, tables->tcpalog, vms->oem_id, | |
976 | vms->oem_table_id); | |
977 | } | |
978 | #endif | |
979 | ||
980 | if (vms->iommu == VIRT_IOMMU_VIRTIO) { | |
981 | acpi_add_table(table_offsets, tables_blob); | |
982 | build_viot(ms, tables_blob, tables->linker, vms->virtio_iommu_bdf, | |
983 | vms->oem_id, vms->oem_table_id); | |
984 | } | |
985 | ||
986 | /* XSDT is pointed to by RSDP */ | |
987 | xsdt = tables_blob->len; | |
988 | build_xsdt(tables_blob, tables->linker, table_offsets, vms->oem_id, | |
989 | vms->oem_table_id); | |
990 | ||
991 | /* RSDP is in FSEG memory, so allocate it separately */ | |
992 | { | |
993 | AcpiRsdpData rsdp_data = { | |
994 | .revision = 2, | |
995 | .oem_id = vms->oem_id, | |
996 | .xsdt_tbl_offset = &xsdt, | |
997 | .rsdt_tbl_offset = NULL, | |
998 | }; | |
999 | build_rsdp(tables->rsdp, tables->linker, &rsdp_data); | |
1000 | } | |
1001 | ||
1002 | /* | |
1003 | * The align size is 128, warn if 64k is not enough therefore | |
1004 | * the align size could be resized. | |
1005 | */ | |
1006 | if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { | |
1007 | warn_report("ACPI table size %u exceeds %d bytes," | |
1008 | " migration may not work", | |
1009 | tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2); | |
1010 | error_printf("Try removing CPUs, NUMA nodes, memory slots" | |
1011 | " or PCI bridges."); | |
1012 | } | |
1013 | acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); | |
1014 | ||
1015 | ||
1016 | /* Cleanup memory that's no longer used. */ | |
1017 | g_array_free(table_offsets, true); | |
1018 | } | |
1019 | ||
1020 | static void acpi_ram_update(MemoryRegion *mr, GArray *data) | |
1021 | { | |
1022 | uint32_t size = acpi_data_len(data); | |
1023 | ||
1024 | /* Make sure RAM size is correct - in case it got changed | |
1025 | * e.g. by migration */ | |
1026 | memory_region_ram_resize(mr, size, &error_abort); | |
1027 | ||
1028 | memcpy(memory_region_get_ram_ptr(mr), data->data, size); | |
1029 | memory_region_set_dirty(mr, 0, size); | |
1030 | } | |
1031 | ||
1032 | static void virt_acpi_build_update(void *build_opaque) | |
1033 | { | |
1034 | AcpiBuildState *build_state = build_opaque; | |
1035 | AcpiBuildTables tables; | |
1036 | ||
1037 | /* No state to update or already patched? Nothing to do. */ | |
1038 | if (!build_state || build_state->patched) { | |
1039 | return; | |
1040 | } | |
1041 | build_state->patched = true; | |
1042 | ||
1043 | acpi_build_tables_init(&tables); | |
1044 | ||
1045 | virt_acpi_build(VIRT_MACHINE(qdev_get_machine()), &tables); | |
1046 | ||
1047 | acpi_ram_update(build_state->table_mr, tables.table_data); | |
1048 | acpi_ram_update(build_state->rsdp_mr, tables.rsdp); | |
1049 | acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); | |
1050 | ||
1051 | acpi_build_tables_cleanup(&tables, true); | |
1052 | } | |
1053 | ||
1054 | static void virt_acpi_build_reset(void *build_opaque) | |
1055 | { | |
1056 | AcpiBuildState *build_state = build_opaque; | |
1057 | build_state->patched = false; | |
1058 | } | |
1059 | ||
1060 | static const VMStateDescription vmstate_virt_acpi_build = { | |
1061 | .name = "virt_acpi_build", | |
1062 | .version_id = 1, | |
1063 | .minimum_version_id = 1, | |
1064 | .fields = (const VMStateField[]) { | |
1065 | VMSTATE_BOOL(patched, AcpiBuildState), | |
1066 | VMSTATE_END_OF_LIST() | |
1067 | }, | |
1068 | }; | |
1069 | ||
1070 | void virt_acpi_setup(VirtMachineState *vms) | |
1071 | { | |
1072 | AcpiBuildTables tables; | |
1073 | AcpiBuildState *build_state; | |
1074 | AcpiGedState *acpi_ged_state; | |
1075 | ||
1076 | if (!vms->fw_cfg) { | |
1077 | trace_virt_acpi_setup(); | |
1078 | return; | |
1079 | } | |
1080 | ||
1081 | if (!virt_is_acpi_enabled(vms)) { | |
1082 | trace_virt_acpi_setup(); | |
1083 | return; | |
1084 | } | |
1085 | ||
1086 | build_state = g_malloc0(sizeof *build_state); | |
1087 | ||
1088 | acpi_build_tables_init(&tables); | |
1089 | virt_acpi_build(vms, &tables); | |
1090 | ||
1091 | /* Now expose it all to Guest */ | |
1092 | build_state->table_mr = acpi_add_rom_blob(virt_acpi_build_update, | |
1093 | build_state, tables.table_data, | |
1094 | ACPI_BUILD_TABLE_FILE); | |
1095 | assert(build_state->table_mr != NULL); | |
1096 | ||
1097 | build_state->linker_mr = acpi_add_rom_blob(virt_acpi_build_update, | |
1098 | build_state, | |
1099 | tables.linker->cmd_blob, | |
1100 | ACPI_BUILD_LOADER_FILE); | |
1101 | ||
1102 | fw_cfg_add_file(vms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, tables.tcpalog->data, | |
1103 | acpi_data_len(tables.tcpalog)); | |
1104 | ||
1105 | if (vms->ras) { | |
1106 | assert(vms->acpi_dev); | |
1107 | acpi_ged_state = ACPI_GED(vms->acpi_dev); | |
1108 | acpi_ghes_add_fw_cfg(&acpi_ged_state->ghes_state, | |
1109 | vms->fw_cfg, tables.hardware_errors); | |
1110 | } | |
1111 | ||
1112 | build_state->rsdp_mr = acpi_add_rom_blob(virt_acpi_build_update, | |
1113 | build_state, tables.rsdp, | |
1114 | ACPI_BUILD_RSDP_FILE); | |
1115 | ||
1116 | qemu_register_reset(virt_acpi_build_reset, build_state); | |
1117 | virt_acpi_build_reset(build_state); | |
1118 | vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state); | |
1119 | ||
1120 | /* Cleanup tables but don't free the memory: we track it | |
1121 | * in build_state. | |
1122 | */ | |
1123 | acpi_build_tables_cleanup(&tables, false); | |
1124 | } |