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1 | /* | |
2 | * Xilinx Zynq MPSoC emulation | |
3 | * | |
4 | * Copyright (C) 2015 Xilinx Inc | |
5 | * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License as published by the | |
9 | * Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | * for more details. | |
16 | */ | |
17 | ||
18 | #include "qemu/osdep.h" | |
19 | #include "qapi/error.h" | |
20 | #include "qemu/module.h" | |
21 | #include "cpu.h" | |
22 | #include "hw/arm/xlnx-zynqmp.h" | |
23 | #include "hw/intc/arm_gic_common.h" | |
24 | #include "hw/boards.h" | |
25 | #include "exec/address-spaces.h" | |
26 | #include "sysemu/kvm.h" | |
27 | #include "sysemu/sysemu.h" | |
28 | #include "kvm_arm.h" | |
29 | ||
30 | #define GIC_NUM_SPI_INTR 160 | |
31 | ||
32 | #define ARM_PHYS_TIMER_PPI 30 | |
33 | #define ARM_VIRT_TIMER_PPI 27 | |
34 | #define ARM_HYP_TIMER_PPI 26 | |
35 | #define ARM_SEC_TIMER_PPI 29 | |
36 | #define GIC_MAINTENANCE_PPI 25 | |
37 | ||
38 | #define GEM_REVISION 0x40070106 | |
39 | ||
40 | #define GIC_BASE_ADDR 0xf9000000 | |
41 | #define GIC_DIST_ADDR 0xf9010000 | |
42 | #define GIC_CPU_ADDR 0xf9020000 | |
43 | #define GIC_VIFACE_ADDR 0xf9040000 | |
44 | #define GIC_VCPU_ADDR 0xf9060000 | |
45 | ||
46 | #define SATA_INTR 133 | |
47 | #define SATA_ADDR 0xFD0C0000 | |
48 | #define SATA_NUM_PORTS 2 | |
49 | ||
50 | #define QSPI_ADDR 0xff0f0000 | |
51 | #define LQSPI_ADDR 0xc0000000 | |
52 | #define QSPI_IRQ 15 | |
53 | ||
54 | #define DP_ADDR 0xfd4a0000 | |
55 | #define DP_IRQ 113 | |
56 | ||
57 | #define DPDMA_ADDR 0xfd4c0000 | |
58 | #define DPDMA_IRQ 116 | |
59 | ||
60 | #define IPI_ADDR 0xFF300000 | |
61 | #define IPI_IRQ 64 | |
62 | ||
63 | #define RTC_ADDR 0xffa60000 | |
64 | #define RTC_IRQ 26 | |
65 | ||
66 | #define SDHCI_CAPABILITIES 0x280737ec6481 /* Datasheet: UG1085 (v1.7) */ | |
67 | ||
68 | static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = { | |
69 | 0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000, | |
70 | }; | |
71 | ||
72 | static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = { | |
73 | 57, 59, 61, 63, | |
74 | }; | |
75 | ||
76 | static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = { | |
77 | 0xFF000000, 0xFF010000, | |
78 | }; | |
79 | ||
80 | static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = { | |
81 | 21, 22, | |
82 | }; | |
83 | ||
84 | static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = { | |
85 | 0xFF160000, 0xFF170000, | |
86 | }; | |
87 | ||
88 | static const int sdhci_intr[XLNX_ZYNQMP_NUM_SDHCI] = { | |
89 | 48, 49, | |
90 | }; | |
91 | ||
92 | static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = { | |
93 | 0xFF040000, 0xFF050000, | |
94 | }; | |
95 | ||
96 | static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = { | |
97 | 19, 20, | |
98 | }; | |
99 | ||
100 | static const uint64_t gdma_ch_addr[XLNX_ZYNQMP_NUM_GDMA_CH] = { | |
101 | 0xFD500000, 0xFD510000, 0xFD520000, 0xFD530000, | |
102 | 0xFD540000, 0xFD550000, 0xFD560000, 0xFD570000 | |
103 | }; | |
104 | ||
105 | static const int gdma_ch_intr[XLNX_ZYNQMP_NUM_GDMA_CH] = { | |
106 | 124, 125, 126, 127, 128, 129, 130, 131 | |
107 | }; | |
108 | ||
109 | static const uint64_t adma_ch_addr[XLNX_ZYNQMP_NUM_ADMA_CH] = { | |
110 | 0xFFA80000, 0xFFA90000, 0xFFAA0000, 0xFFAB0000, | |
111 | 0xFFAC0000, 0xFFAD0000, 0xFFAE0000, 0xFFAF0000 | |
112 | }; | |
113 | ||
114 | static const int adma_ch_intr[XLNX_ZYNQMP_NUM_ADMA_CH] = { | |
115 | 77, 78, 79, 80, 81, 82, 83, 84 | |
116 | }; | |
117 | ||
118 | typedef struct XlnxZynqMPGICRegion { | |
119 | int region_index; | |
120 | uint32_t address; | |
121 | uint32_t offset; | |
122 | bool virt; | |
123 | } XlnxZynqMPGICRegion; | |
124 | ||
125 | static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = { | |
126 | /* Distributor */ | |
127 | { | |
128 | .region_index = 0, | |
129 | .address = GIC_DIST_ADDR, | |
130 | .offset = 0, | |
131 | .virt = false | |
132 | }, | |
133 | ||
134 | /* CPU interface */ | |
135 | { | |
136 | .region_index = 1, | |
137 | .address = GIC_CPU_ADDR, | |
138 | .offset = 0, | |
139 | .virt = false | |
140 | }, | |
141 | { | |
142 | .region_index = 1, | |
143 | .address = GIC_CPU_ADDR + 0x10000, | |
144 | .offset = 0x1000, | |
145 | .virt = false | |
146 | }, | |
147 | ||
148 | /* Virtual interface */ | |
149 | { | |
150 | .region_index = 2, | |
151 | .address = GIC_VIFACE_ADDR, | |
152 | .offset = 0, | |
153 | .virt = true | |
154 | }, | |
155 | ||
156 | /* Virtual CPU interface */ | |
157 | { | |
158 | .region_index = 3, | |
159 | .address = GIC_VCPU_ADDR, | |
160 | .offset = 0, | |
161 | .virt = true | |
162 | }, | |
163 | { | |
164 | .region_index = 3, | |
165 | .address = GIC_VCPU_ADDR + 0x10000, | |
166 | .offset = 0x1000, | |
167 | .virt = true | |
168 | }, | |
169 | }; | |
170 | ||
171 | static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index) | |
172 | { | |
173 | return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index; | |
174 | } | |
175 | ||
176 | static void xlnx_zynqmp_create_rpu(MachineState *ms, XlnxZynqMPState *s, | |
177 | const char *boot_cpu, Error **errp) | |
178 | { | |
179 | Error *err = NULL; | |
180 | int i; | |
181 | int num_rpus = MIN(ms->smp.cpus - XLNX_ZYNQMP_NUM_APU_CPUS, | |
182 | XLNX_ZYNQMP_NUM_RPU_CPUS); | |
183 | ||
184 | if (num_rpus <= 0) { | |
185 | /* Don't create rpu-cluster object if there's nothing to put in it */ | |
186 | return; | |
187 | } | |
188 | ||
189 | object_initialize_child(OBJECT(s), "rpu-cluster", &s->rpu_cluster, | |
190 | sizeof(s->rpu_cluster), TYPE_CPU_CLUSTER, | |
191 | &error_abort, NULL); | |
192 | qdev_prop_set_uint32(DEVICE(&s->rpu_cluster), "cluster-id", 1); | |
193 | ||
194 | for (i = 0; i < num_rpus; i++) { | |
195 | char *name; | |
196 | ||
197 | object_initialize_child(OBJECT(&s->rpu_cluster), "rpu-cpu[*]", | |
198 | &s->rpu_cpu[i], sizeof(s->rpu_cpu[i]), | |
199 | ARM_CPU_TYPE_NAME("cortex-r5f"), | |
200 | &error_abort, NULL); | |
201 | ||
202 | name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i])); | |
203 | if (strcmp(name, boot_cpu)) { | |
204 | /* Secondary CPUs start in PSCI powered-down state */ | |
205 | object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, | |
206 | "start-powered-off", &error_abort); | |
207 | } else { | |
208 | s->boot_cpu_ptr = &s->rpu_cpu[i]; | |
209 | } | |
210 | g_free(name); | |
211 | ||
212 | object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "reset-hivecs", | |
213 | &error_abort); | |
214 | object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "realized", | |
215 | &err); | |
216 | if (err) { | |
217 | error_propagate(errp, err); | |
218 | return; | |
219 | } | |
220 | } | |
221 | ||
222 | qdev_init_nofail(DEVICE(&s->rpu_cluster)); | |
223 | } | |
224 | ||
225 | static void xlnx_zynqmp_init(Object *obj) | |
226 | { | |
227 | MachineState *ms = MACHINE(qdev_get_machine()); | |
228 | XlnxZynqMPState *s = XLNX_ZYNQMP(obj); | |
229 | int i; | |
230 | int num_apus = MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS); | |
231 | ||
232 | object_initialize_child(obj, "apu-cluster", &s->apu_cluster, | |
233 | sizeof(s->apu_cluster), TYPE_CPU_CLUSTER, | |
234 | &error_abort, NULL); | |
235 | qdev_prop_set_uint32(DEVICE(&s->apu_cluster), "cluster-id", 0); | |
236 | ||
237 | for (i = 0; i < num_apus; i++) { | |
238 | object_initialize_child(OBJECT(&s->apu_cluster), "apu-cpu[*]", | |
239 | &s->apu_cpu[i], sizeof(s->apu_cpu[i]), | |
240 | ARM_CPU_TYPE_NAME("cortex-a53"), | |
241 | &error_abort, NULL); | |
242 | } | |
243 | ||
244 | sysbus_init_child_obj(obj, "gic", &s->gic, sizeof(s->gic), | |
245 | gic_class_name()); | |
246 | ||
247 | for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { | |
248 | sysbus_init_child_obj(obj, "gem[*]", &s->gem[i], sizeof(s->gem[i]), | |
249 | TYPE_CADENCE_GEM); | |
250 | } | |
251 | ||
252 | for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { | |
253 | sysbus_init_child_obj(obj, "uart[*]", &s->uart[i], sizeof(s->uart[i]), | |
254 | TYPE_CADENCE_UART); | |
255 | } | |
256 | ||
257 | sysbus_init_child_obj(obj, "sata", &s->sata, sizeof(s->sata), | |
258 | TYPE_SYSBUS_AHCI); | |
259 | ||
260 | for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { | |
261 | sysbus_init_child_obj(obj, "sdhci[*]", &s->sdhci[i], | |
262 | sizeof(s->sdhci[i]), TYPE_SYSBUS_SDHCI); | |
263 | } | |
264 | ||
265 | for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) { | |
266 | sysbus_init_child_obj(obj, "spi[*]", &s->spi[i], sizeof(s->spi[i]), | |
267 | TYPE_XILINX_SPIPS); | |
268 | } | |
269 | ||
270 | sysbus_init_child_obj(obj, "qspi", &s->qspi, sizeof(s->qspi), | |
271 | TYPE_XLNX_ZYNQMP_QSPIPS); | |
272 | ||
273 | sysbus_init_child_obj(obj, "xxxdp", &s->dp, sizeof(s->dp), TYPE_XLNX_DP); | |
274 | ||
275 | sysbus_init_child_obj(obj, "dp-dma", &s->dpdma, sizeof(s->dpdma), | |
276 | TYPE_XLNX_DPDMA); | |
277 | ||
278 | sysbus_init_child_obj(obj, "ipi", &s->ipi, sizeof(s->ipi), | |
279 | TYPE_XLNX_ZYNQMP_IPI); | |
280 | ||
281 | sysbus_init_child_obj(obj, "rtc", &s->rtc, sizeof(s->rtc), | |
282 | TYPE_XLNX_ZYNQMP_RTC); | |
283 | ||
284 | for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) { | |
285 | sysbus_init_child_obj(obj, "gdma[*]", &s->gdma[i], sizeof(s->gdma[i]), | |
286 | TYPE_XLNX_ZDMA); | |
287 | } | |
288 | ||
289 | for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) { | |
290 | sysbus_init_child_obj(obj, "adma[*]", &s->adma[i], sizeof(s->adma[i]), | |
291 | TYPE_XLNX_ZDMA); | |
292 | } | |
293 | } | |
294 | ||
295 | static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) | |
296 | { | |
297 | MachineState *ms = MACHINE(qdev_get_machine()); | |
298 | XlnxZynqMPState *s = XLNX_ZYNQMP(dev); | |
299 | MemoryRegion *system_memory = get_system_memory(); | |
300 | uint8_t i; | |
301 | uint64_t ram_size; | |
302 | int num_apus = MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS); | |
303 | const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]"; | |
304 | ram_addr_t ddr_low_size, ddr_high_size; | |
305 | qemu_irq gic_spi[GIC_NUM_SPI_INTR]; | |
306 | Error *err = NULL; | |
307 | ||
308 | ram_size = memory_region_size(s->ddr_ram); | |
309 | ||
310 | /* Create the DDR Memory Regions. User friendly checks should happen at | |
311 | * the board level | |
312 | */ | |
313 | if (ram_size > XLNX_ZYNQMP_MAX_LOW_RAM_SIZE) { | |
314 | /* The RAM size is above the maximum available for the low DDR. | |
315 | * Create the high DDR memory region as well. | |
316 | */ | |
317 | assert(ram_size <= XLNX_ZYNQMP_MAX_RAM_SIZE); | |
318 | ddr_low_size = XLNX_ZYNQMP_MAX_LOW_RAM_SIZE; | |
319 | ddr_high_size = ram_size - XLNX_ZYNQMP_MAX_LOW_RAM_SIZE; | |
320 | ||
321 | memory_region_init_alias(&s->ddr_ram_high, NULL, | |
322 | "ddr-ram-high", s->ddr_ram, | |
323 | ddr_low_size, ddr_high_size); | |
324 | memory_region_add_subregion(get_system_memory(), | |
325 | XLNX_ZYNQMP_HIGH_RAM_START, | |
326 | &s->ddr_ram_high); | |
327 | } else { | |
328 | /* RAM must be non-zero */ | |
329 | assert(ram_size); | |
330 | ddr_low_size = ram_size; | |
331 | } | |
332 | ||
333 | memory_region_init_alias(&s->ddr_ram_low, NULL, | |
334 | "ddr-ram-low", s->ddr_ram, | |
335 | 0, ddr_low_size); | |
336 | memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram_low); | |
337 | ||
338 | /* Create the four OCM banks */ | |
339 | for (i = 0; i < XLNX_ZYNQMP_NUM_OCM_BANKS; i++) { | |
340 | char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i); | |
341 | ||
342 | memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name, | |
343 | XLNX_ZYNQMP_OCM_RAM_SIZE, &error_fatal); | |
344 | memory_region_add_subregion(get_system_memory(), | |
345 | XLNX_ZYNQMP_OCM_RAM_0_ADDRESS + | |
346 | i * XLNX_ZYNQMP_OCM_RAM_SIZE, | |
347 | &s->ocm_ram[i]); | |
348 | ||
349 | g_free(ocm_name); | |
350 | } | |
351 | ||
352 | qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32); | |
353 | qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); | |
354 | qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", num_apus); | |
355 | qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", s->secure); | |
356 | qdev_prop_set_bit(DEVICE(&s->gic), | |
357 | "has-virtualization-extensions", s->virt); | |
358 | ||
359 | qdev_init_nofail(DEVICE(&s->apu_cluster)); | |
360 | ||
361 | /* Realize APUs before realizing the GIC. KVM requires this. */ | |
362 | for (i = 0; i < num_apus; i++) { | |
363 | char *name; | |
364 | ||
365 | object_property_set_int(OBJECT(&s->apu_cpu[i]), QEMU_PSCI_CONDUIT_SMC, | |
366 | "psci-conduit", &error_abort); | |
367 | ||
368 | name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i])); | |
369 | if (strcmp(name, boot_cpu)) { | |
370 | /* Secondary CPUs start in PSCI powered-down state */ | |
371 | object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, | |
372 | "start-powered-off", &error_abort); | |
373 | } else { | |
374 | s->boot_cpu_ptr = &s->apu_cpu[i]; | |
375 | } | |
376 | g_free(name); | |
377 | ||
378 | object_property_set_bool(OBJECT(&s->apu_cpu[i]), | |
379 | s->secure, "has_el3", NULL); | |
380 | object_property_set_bool(OBJECT(&s->apu_cpu[i]), | |
381 | s->virt, "has_el2", NULL); | |
382 | object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR, | |
383 | "reset-cbar", &error_abort); | |
384 | object_property_set_int(OBJECT(&s->apu_cpu[i]), num_apus, | |
385 | "core-count", &error_abort); | |
386 | object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "realized", | |
387 | &err); | |
388 | if (err) { | |
389 | error_propagate(errp, err); | |
390 | return; | |
391 | } | |
392 | } | |
393 | ||
394 | object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); | |
395 | if (err) { | |
396 | error_propagate(errp, err); | |
397 | return; | |
398 | } | |
399 | ||
400 | assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS); | |
401 | for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) { | |
402 | SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic); | |
403 | const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i]; | |
404 | MemoryRegion *mr; | |
405 | uint32_t addr = r->address; | |
406 | int j; | |
407 | ||
408 | if (r->virt && !s->virt) { | |
409 | continue; | |
410 | } | |
411 | ||
412 | mr = sysbus_mmio_get_region(gic, r->region_index); | |
413 | for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) { | |
414 | MemoryRegion *alias = &s->gic_mr[i][j]; | |
415 | ||
416 | memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr, | |
417 | r->offset, XLNX_ZYNQMP_GIC_REGION_SIZE); | |
418 | memory_region_add_subregion(system_memory, addr, alias); | |
419 | ||
420 | addr += XLNX_ZYNQMP_GIC_REGION_SIZE; | |
421 | } | |
422 | } | |
423 | ||
424 | for (i = 0; i < num_apus; i++) { | |
425 | qemu_irq irq; | |
426 | ||
427 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i, | |
428 | qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), | |
429 | ARM_CPU_IRQ)); | |
430 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus, | |
431 | qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), | |
432 | ARM_CPU_FIQ)); | |
433 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 2, | |
434 | qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), | |
435 | ARM_CPU_VIRQ)); | |
436 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 3, | |
437 | qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), | |
438 | ARM_CPU_VFIQ)); | |
439 | irq = qdev_get_gpio_in(DEVICE(&s->gic), | |
440 | arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI)); | |
441 | qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_PHYS, irq); | |
442 | irq = qdev_get_gpio_in(DEVICE(&s->gic), | |
443 | arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI)); | |
444 | qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_VIRT, irq); | |
445 | irq = qdev_get_gpio_in(DEVICE(&s->gic), | |
446 | arm_gic_ppi_index(i, ARM_HYP_TIMER_PPI)); | |
447 | qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_HYP, irq); | |
448 | irq = qdev_get_gpio_in(DEVICE(&s->gic), | |
449 | arm_gic_ppi_index(i, ARM_SEC_TIMER_PPI)); | |
450 | qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_SEC, irq); | |
451 | ||
452 | if (s->virt) { | |
453 | irq = qdev_get_gpio_in(DEVICE(&s->gic), | |
454 | arm_gic_ppi_index(i, GIC_MAINTENANCE_PPI)); | |
455 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 4, irq); | |
456 | } | |
457 | } | |
458 | ||
459 | if (s->has_rpu) { | |
460 | info_report("The 'has_rpu' property is no longer required, to use the " | |
461 | "RPUs just use -smp 6."); | |
462 | } | |
463 | ||
464 | xlnx_zynqmp_create_rpu(ms, s, boot_cpu, &err); | |
465 | if (err) { | |
466 | error_propagate(errp, err); | |
467 | return; | |
468 | } | |
469 | ||
470 | if (!s->boot_cpu_ptr) { | |
471 | error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu); | |
472 | return; | |
473 | } | |
474 | ||
475 | for (i = 0; i < GIC_NUM_SPI_INTR; i++) { | |
476 | gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i); | |
477 | } | |
478 | ||
479 | for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { | |
480 | NICInfo *nd = &nd_table[i]; | |
481 | ||
482 | if (nd->used) { | |
483 | qemu_check_nic_model(nd, TYPE_CADENCE_GEM); | |
484 | qdev_set_nic_properties(DEVICE(&s->gem[i]), nd); | |
485 | } | |
486 | object_property_set_int(OBJECT(&s->gem[i]), GEM_REVISION, "revision", | |
487 | &error_abort); | |
488 | object_property_set_int(OBJECT(&s->gem[i]), 2, "num-priority-queues", | |
489 | &error_abort); | |
490 | object_property_set_bool(OBJECT(&s->gem[i]), true, "realized", &err); | |
491 | if (err) { | |
492 | error_propagate(errp, err); | |
493 | return; | |
494 | } | |
495 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]); | |
496 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0, | |
497 | gic_spi[gem_intr[i]]); | |
498 | } | |
499 | ||
500 | for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { | |
501 | qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); | |
502 | object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err); | |
503 | if (err) { | |
504 | error_propagate(errp, err); | |
505 | return; | |
506 | } | |
507 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]); | |
508 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, | |
509 | gic_spi[uart_intr[i]]); | |
510 | } | |
511 | ||
512 | object_property_set_int(OBJECT(&s->sata), SATA_NUM_PORTS, "num-ports", | |
513 | &error_abort); | |
514 | object_property_set_bool(OBJECT(&s->sata), true, "realized", &err); | |
515 | if (err) { | |
516 | error_propagate(errp, err); | |
517 | return; | |
518 | } | |
519 | ||
520 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR); | |
521 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]); | |
522 | ||
523 | for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { | |
524 | char *bus_name = g_strdup_printf("sd-bus%d", i); | |
525 | SysBusDevice *sbd = SYS_BUS_DEVICE(&s->sdhci[i]); | |
526 | Object *sdhci = OBJECT(&s->sdhci[i]); | |
527 | ||
528 | /* Compatible with: | |
529 | * - SD Host Controller Specification Version 3.00 | |
530 | * - SDIO Specification Version 3.0 | |
531 | * - eMMC Specification Version 4.51 | |
532 | */ | |
533 | object_property_set_uint(sdhci, 3, "sd-spec-version", &err); | |
534 | object_property_set_uint(sdhci, SDHCI_CAPABILITIES, "capareg", &err); | |
535 | object_property_set_uint(sdhci, UHS_I, "uhs", &err); | |
536 | object_property_set_bool(sdhci, true, "realized", &err); | |
537 | if (err) { | |
538 | error_propagate(errp, err); | |
539 | return; | |
540 | } | |
541 | sysbus_mmio_map(sbd, 0, sdhci_addr[i]); | |
542 | sysbus_connect_irq(sbd, 0, gic_spi[sdhci_intr[i]]); | |
543 | ||
544 | /* Alias controller SD bus to the SoC itself */ | |
545 | object_property_add_alias(OBJECT(s), bus_name, sdhci, "sd-bus", | |
546 | &error_abort); | |
547 | g_free(bus_name); | |
548 | } | |
549 | ||
550 | for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) { | |
551 | gchar *bus_name; | |
552 | ||
553 | object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err); | |
554 | ||
555 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]); | |
556 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, | |
557 | gic_spi[spi_intr[i]]); | |
558 | ||
559 | /* Alias controller SPI bus to the SoC itself */ | |
560 | bus_name = g_strdup_printf("spi%d", i); | |
561 | object_property_add_alias(OBJECT(s), bus_name, | |
562 | OBJECT(&s->spi[i]), "spi0", | |
563 | &error_abort); | |
564 | g_free(bus_name); | |
565 | } | |
566 | ||
567 | object_property_set_bool(OBJECT(&s->qspi), true, "realized", &err); | |
568 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 0, QSPI_ADDR); | |
569 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 1, LQSPI_ADDR); | |
570 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi), 0, gic_spi[QSPI_IRQ]); | |
571 | ||
572 | for (i = 0; i < XLNX_ZYNQMP_NUM_QSPI_BUS; i++) { | |
573 | gchar *bus_name; | |
574 | gchar *target_bus; | |
575 | ||
576 | /* Alias controller SPI bus to the SoC itself */ | |
577 | bus_name = g_strdup_printf("qspi%d", i); | |
578 | target_bus = g_strdup_printf("spi%d", i); | |
579 | object_property_add_alias(OBJECT(s), bus_name, | |
580 | OBJECT(&s->qspi), target_bus, | |
581 | &error_abort); | |
582 | g_free(bus_name); | |
583 | g_free(target_bus); | |
584 | } | |
585 | ||
586 | object_property_set_bool(OBJECT(&s->dp), true, "realized", &err); | |
587 | if (err) { | |
588 | error_propagate(errp, err); | |
589 | return; | |
590 | } | |
591 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->dp), 0, DP_ADDR); | |
592 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->dp), 0, gic_spi[DP_IRQ]); | |
593 | ||
594 | object_property_set_bool(OBJECT(&s->dpdma), true, "realized", &err); | |
595 | if (err) { | |
596 | error_propagate(errp, err); | |
597 | return; | |
598 | } | |
599 | object_property_set_link(OBJECT(&s->dp), OBJECT(&s->dpdma), "dpdma", | |
600 | &error_abort); | |
601 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->dpdma), 0, DPDMA_ADDR); | |
602 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->dpdma), 0, gic_spi[DPDMA_IRQ]); | |
603 | ||
604 | object_property_set_bool(OBJECT(&s->ipi), true, "realized", &err); | |
605 | if (err) { | |
606 | error_propagate(errp, err); | |
607 | return; | |
608 | } | |
609 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->ipi), 0, IPI_ADDR); | |
610 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->ipi), 0, gic_spi[IPI_IRQ]); | |
611 | ||
612 | object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err); | |
613 | if (err) { | |
614 | error_propagate(errp, err); | |
615 | return; | |
616 | } | |
617 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, RTC_ADDR); | |
618 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, gic_spi[RTC_IRQ]); | |
619 | ||
620 | for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) { | |
621 | object_property_set_uint(OBJECT(&s->gdma[i]), 128, "bus-width", &err); | |
622 | object_property_set_bool(OBJECT(&s->gdma[i]), true, "realized", &err); | |
623 | if (err) { | |
624 | error_propagate(errp, err); | |
625 | return; | |
626 | } | |
627 | ||
628 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gdma[i]), 0, gdma_ch_addr[i]); | |
629 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gdma[i]), 0, | |
630 | gic_spi[gdma_ch_intr[i]]); | |
631 | } | |
632 | ||
633 | for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) { | |
634 | object_property_set_bool(OBJECT(&s->adma[i]), true, "realized", &err); | |
635 | if (err) { | |
636 | error_propagate(errp, err); | |
637 | return; | |
638 | } | |
639 | ||
640 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->adma[i]), 0, adma_ch_addr[i]); | |
641 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->adma[i]), 0, | |
642 | gic_spi[adma_ch_intr[i]]); | |
643 | } | |
644 | } | |
645 | ||
646 | static Property xlnx_zynqmp_props[] = { | |
647 | DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu), | |
648 | DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false), | |
649 | DEFINE_PROP_BOOL("virtualization", XlnxZynqMPState, virt, false), | |
650 | DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false), | |
651 | DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGION, | |
652 | MemoryRegion *), | |
653 | DEFINE_PROP_END_OF_LIST() | |
654 | }; | |
655 | ||
656 | static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data) | |
657 | { | |
658 | DeviceClass *dc = DEVICE_CLASS(oc); | |
659 | ||
660 | dc->props = xlnx_zynqmp_props; | |
661 | dc->realize = xlnx_zynqmp_realize; | |
662 | /* Reason: Uses serial_hds in realize function, thus can't be used twice */ | |
663 | dc->user_creatable = false; | |
664 | } | |
665 | ||
666 | static const TypeInfo xlnx_zynqmp_type_info = { | |
667 | .name = TYPE_XLNX_ZYNQMP, | |
668 | .parent = TYPE_DEVICE, | |
669 | .instance_size = sizeof(XlnxZynqMPState), | |
670 | .instance_init = xlnx_zynqmp_init, | |
671 | .class_init = xlnx_zynqmp_class_init, | |
672 | }; | |
673 | ||
674 | static void xlnx_zynqmp_register_types(void) | |
675 | { | |
676 | type_register_static(&xlnx_zynqmp_type_info); | |
677 | } | |
678 | ||
679 | type_init(xlnx_zynqmp_register_types) |