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1 | /* | |
2 | * QEMU ATI SVGA emulation | |
3 | * 2D engine functions | |
4 | * | |
5 | * Copyright (c) 2019 BALATON Zoltan | |
6 | * | |
7 | * This work is licensed under the GNU GPL license version 2 or later. | |
8 | */ | |
9 | ||
10 | #include "qemu/osdep.h" | |
11 | #include "ati_int.h" | |
12 | #include "ati_regs.h" | |
13 | #include "qemu/log.h" | |
14 | #include "ui/pixel_ops.h" | |
15 | #include "ui/console.h" | |
16 | ||
17 | /* | |
18 | * NOTE: | |
19 | * This is 2D _acceleration_ and supposed to be fast. Therefore, don't try to | |
20 | * reinvent the wheel (unlikely to get better with a naive implementation than | |
21 | * existing libraries) and avoid (poorly) reimplementing gfx primitives. | |
22 | * That is unnecessary and would become a performance problem. Instead, try to | |
23 | * map to and reuse existing optimised facilities (e.g. pixman) wherever | |
24 | * possible. | |
25 | */ | |
26 | ||
27 | static int ati_bpp_from_datatype(ATIVGAState *s) | |
28 | { | |
29 | switch (s->regs.dp_datatype & 0xf) { | |
30 | case 2: | |
31 | return 8; | |
32 | case 3: | |
33 | case 4: | |
34 | return 16; | |
35 | case 5: | |
36 | return 24; | |
37 | case 6: | |
38 | return 32; | |
39 | default: | |
40 | qemu_log_mask(LOG_UNIMP, "Unknown dst datatype %d\n", | |
41 | s->regs.dp_datatype & 0xf); | |
42 | return 0; | |
43 | } | |
44 | } | |
45 | ||
46 | #define DEFAULT_CNTL (s->regs.dp_gui_master_cntl & GMC_DST_PITCH_OFFSET_CNTL) | |
47 | ||
48 | void ati_2d_blt(ATIVGAState *s) | |
49 | { | |
50 | /* FIXME it is probably more complex than this and may need to be */ | |
51 | /* rewritten but for now as a start just to get some output: */ | |
52 | DisplaySurface *ds = qemu_console_surface(s->vga.con); | |
53 | DPRINTF("%p %u ds: %p %d %d rop: %x\n", s->vga.vram_ptr, | |
54 | s->vga.vbe_start_addr, surface_data(ds), surface_stride(ds), | |
55 | surface_bits_per_pixel(ds), | |
56 | (s->regs.dp_mix & GMC_ROP3_MASK) >> 16); | |
57 | unsigned dst_x = (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ? | |
58 | s->regs.dst_x : s->regs.dst_x + 1 - s->regs.dst_width); | |
59 | unsigned dst_y = (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ? | |
60 | s->regs.dst_y : s->regs.dst_y + 1 - s->regs.dst_height); | |
61 | int bpp = ati_bpp_from_datatype(s); | |
62 | if (!bpp) { | |
63 | qemu_log_mask(LOG_GUEST_ERROR, "Invalid bpp\n"); | |
64 | return; | |
65 | } | |
66 | int dst_stride = DEFAULT_CNTL ? s->regs.dst_pitch : s->regs.default_pitch; | |
67 | if (!dst_stride) { | |
68 | qemu_log_mask(LOG_GUEST_ERROR, "Zero dest pitch\n"); | |
69 | return; | |
70 | } | |
71 | uint8_t *dst_bits = s->vga.vram_ptr + (DEFAULT_CNTL ? | |
72 | s->regs.dst_offset : s->regs.default_offset); | |
73 | ||
74 | if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { | |
75 | dst_bits += s->regs.crtc_offset & 0x07ffffff; | |
76 | dst_stride *= bpp; | |
77 | } | |
78 | uint8_t *end = s->vga.vram_ptr + s->vga.vram_size; | |
79 | if (dst_x > 0x3fff || dst_y > 0x3fff || dst_bits >= end | |
80 | || dst_bits + dst_x | |
81 | + (dst_y + s->regs.dst_height) * dst_stride >= end) { | |
82 | qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n"); | |
83 | return; | |
84 | } | |
85 | DPRINTF("%d %d %d, %d %d %d, (%d,%d) -> (%d,%d) %dx%d %c %c\n", | |
86 | s->regs.src_offset, s->regs.dst_offset, s->regs.default_offset, | |
87 | s->regs.src_pitch, s->regs.dst_pitch, s->regs.default_pitch, | |
88 | s->regs.src_x, s->regs.src_y, dst_x, dst_y, | |
89 | s->regs.dst_width, s->regs.dst_height, | |
90 | (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ? '>' : '<'), | |
91 | (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ? 'v' : '^')); | |
92 | switch (s->regs.dp_mix & GMC_ROP3_MASK) { | |
93 | case ROP3_SRCCOPY: | |
94 | { | |
95 | bool fallback = false; | |
96 | unsigned src_x = (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ? | |
97 | s->regs.src_x : s->regs.src_x + 1 - s->regs.dst_width); | |
98 | unsigned src_y = (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ? | |
99 | s->regs.src_y : s->regs.src_y + 1 - s->regs.dst_height); | |
100 | int src_stride = DEFAULT_CNTL ? | |
101 | s->regs.src_pitch : s->regs.default_pitch; | |
102 | if (!src_stride) { | |
103 | qemu_log_mask(LOG_GUEST_ERROR, "Zero source pitch\n"); | |
104 | return; | |
105 | } | |
106 | uint8_t *src_bits = s->vga.vram_ptr + (DEFAULT_CNTL ? | |
107 | s->regs.src_offset : s->regs.default_offset); | |
108 | ||
109 | if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { | |
110 | src_bits += s->regs.crtc_offset & 0x07ffffff; | |
111 | src_stride *= bpp; | |
112 | } | |
113 | if (src_x > 0x3fff || src_y > 0x3fff || src_bits >= end | |
114 | || src_bits + src_x | |
115 | + (src_y + s->regs.dst_height) * src_stride >= end) { | |
116 | qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n"); | |
117 | return; | |
118 | } | |
119 | ||
120 | src_stride /= sizeof(uint32_t); | |
121 | dst_stride /= sizeof(uint32_t); | |
122 | DPRINTF("pixman_blt(%p, %p, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d)\n", | |
123 | src_bits, dst_bits, src_stride, dst_stride, bpp, bpp, | |
124 | src_x, src_y, dst_x, dst_y, | |
125 | s->regs.dst_width, s->regs.dst_height); | |
126 | #ifdef CONFIG_PIXMAN | |
127 | if ((s->use_pixman & BIT(1)) && | |
128 | s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT && | |
129 | s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM) { | |
130 | fallback = !pixman_blt((uint32_t *)src_bits, (uint32_t *)dst_bits, | |
131 | src_stride, dst_stride, bpp, bpp, | |
132 | src_x, src_y, dst_x, dst_y, | |
133 | s->regs.dst_width, s->regs.dst_height); | |
134 | } else if (s->use_pixman & BIT(1)) { | |
135 | /* FIXME: We only really need a temporary if src and dst overlap */ | |
136 | int llb = s->regs.dst_width * (bpp / 8); | |
137 | int tmp_stride = DIV_ROUND_UP(llb, sizeof(uint32_t)); | |
138 | uint32_t *tmp = g_malloc(tmp_stride * sizeof(uint32_t) * | |
139 | s->regs.dst_height); | |
140 | fallback = !pixman_blt((uint32_t *)src_bits, tmp, | |
141 | src_stride, tmp_stride, bpp, bpp, | |
142 | src_x, src_y, 0, 0, | |
143 | s->regs.dst_width, s->regs.dst_height); | |
144 | if (!fallback) { | |
145 | fallback = !pixman_blt(tmp, (uint32_t *)dst_bits, | |
146 | tmp_stride, dst_stride, bpp, bpp, | |
147 | 0, 0, dst_x, dst_y, | |
148 | s->regs.dst_width, s->regs.dst_height); | |
149 | } | |
150 | g_free(tmp); | |
151 | } else | |
152 | #endif | |
153 | { | |
154 | fallback = true; | |
155 | } | |
156 | if (fallback) { | |
157 | unsigned int y, i, j, bypp = bpp / 8; | |
158 | unsigned int src_pitch = src_stride * sizeof(uint32_t); | |
159 | unsigned int dst_pitch = dst_stride * sizeof(uint32_t); | |
160 | ||
161 | for (y = 0; y < s->regs.dst_height; y++) { | |
162 | i = dst_x * bypp; | |
163 | j = src_x * bypp; | |
164 | if (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM) { | |
165 | i += (dst_y + y) * dst_pitch; | |
166 | j += (src_y + y) * src_pitch; | |
167 | } else { | |
168 | i += (dst_y + s->regs.dst_height - 1 - y) * dst_pitch; | |
169 | j += (src_y + s->regs.dst_height - 1 - y) * src_pitch; | |
170 | } | |
171 | memmove(&dst_bits[i], &src_bits[j], s->regs.dst_width * bypp); | |
172 | } | |
173 | } | |
174 | if (dst_bits >= s->vga.vram_ptr + s->vga.vbe_start_addr && | |
175 | dst_bits < s->vga.vram_ptr + s->vga.vbe_start_addr + | |
176 | s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] * s->vga.vbe_line_offset) { | |
177 | memory_region_set_dirty(&s->vga.vram, s->vga.vbe_start_addr + | |
178 | s->regs.dst_offset + | |
179 | dst_y * surface_stride(ds), | |
180 | s->regs.dst_height * surface_stride(ds)); | |
181 | } | |
182 | s->regs.dst_x = (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ? | |
183 | dst_x + s->regs.dst_width : dst_x); | |
184 | s->regs.dst_y = (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ? | |
185 | dst_y + s->regs.dst_height : dst_y); | |
186 | break; | |
187 | } | |
188 | case ROP3_PATCOPY: | |
189 | case ROP3_BLACKNESS: | |
190 | case ROP3_WHITENESS: | |
191 | { | |
192 | uint32_t filler = 0; | |
193 | ||
194 | switch (s->regs.dp_mix & GMC_ROP3_MASK) { | |
195 | case ROP3_PATCOPY: | |
196 | filler = s->regs.dp_brush_frgd_clr; | |
197 | break; | |
198 | case ROP3_BLACKNESS: | |
199 | filler = 0xffUL << 24 | rgb_to_pixel32(s->vga.palette[0], | |
200 | s->vga.palette[1], s->vga.palette[2]); | |
201 | break; | |
202 | case ROP3_WHITENESS: | |
203 | filler = 0xffUL << 24 | rgb_to_pixel32(s->vga.palette[3], | |
204 | s->vga.palette[4], s->vga.palette[5]); | |
205 | break; | |
206 | } | |
207 | ||
208 | dst_stride /= sizeof(uint32_t); | |
209 | DPRINTF("pixman_fill(%p, %d, %d, %d, %d, %d, %d, %x)\n", | |
210 | dst_bits, dst_stride, bpp, dst_x, dst_y, | |
211 | s->regs.dst_width, s->regs.dst_height, filler); | |
212 | #ifdef CONFIG_PIXMAN | |
213 | if (!(s->use_pixman & BIT(0)) || | |
214 | !pixman_fill((uint32_t *)dst_bits, dst_stride, bpp, dst_x, dst_y, | |
215 | s->regs.dst_width, s->regs.dst_height, filler)) | |
216 | #endif | |
217 | { | |
218 | /* fallback when pixman failed or we don't want to call it */ | |
219 | unsigned int x, y, i, bypp = bpp / 8; | |
220 | unsigned int dst_pitch = dst_stride * sizeof(uint32_t); | |
221 | for (y = 0; y < s->regs.dst_height; y++) { | |
222 | i = dst_x * bypp + (dst_y + y) * dst_pitch; | |
223 | for (x = 0; x < s->regs.dst_width; x++, i += bypp) { | |
224 | stn_he_p(&dst_bits[i], bypp, filler); | |
225 | } | |
226 | } | |
227 | } | |
228 | if (dst_bits >= s->vga.vram_ptr + s->vga.vbe_start_addr && | |
229 | dst_bits < s->vga.vram_ptr + s->vga.vbe_start_addr + | |
230 | s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] * s->vga.vbe_line_offset) { | |
231 | memory_region_set_dirty(&s->vga.vram, s->vga.vbe_start_addr + | |
232 | s->regs.dst_offset + | |
233 | dst_y * surface_stride(ds), | |
234 | s->regs.dst_height * surface_stride(ds)); | |
235 | } | |
236 | s->regs.dst_y = (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ? | |
237 | dst_y + s->regs.dst_height : dst_y); | |
238 | break; | |
239 | } | |
240 | default: | |
241 | qemu_log_mask(LOG_UNIMP, "Unimplemented ati_2d blt op %x\n", | |
242 | (s->regs.dp_mix & GMC_ROP3_MASK) >> 16); | |
243 | } | |
244 | } |