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1 | /* | |
2 | * QEMU PC System Emulator | |
3 | * | |
4 | * Copyright (c) 2003-2004 Fabrice Bellard | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | #include "qemu/osdep.h" | |
25 | #include "hw/hw.h" | |
26 | #include "hw/i386/pc.h" | |
27 | #include "hw/char/serial.h" | |
28 | #include "hw/i386/apic.h" | |
29 | #include "hw/i386/topology.h" | |
30 | #include "sysemu/cpus.h" | |
31 | #include "hw/block/fdc.h" | |
32 | #include "hw/ide.h" | |
33 | #include "hw/pci/pci.h" | |
34 | #include "hw/pci/pci_bus.h" | |
35 | #include "hw/nvram/fw_cfg.h" | |
36 | #include "hw/timer/hpet.h" | |
37 | #include "hw/smbios/smbios.h" | |
38 | #include "hw/loader.h" | |
39 | #include "elf.h" | |
40 | #include "multiboot.h" | |
41 | #include "hw/timer/mc146818rtc.h" | |
42 | #include "hw/timer/i8254.h" | |
43 | #include "hw/audio/pcspk.h" | |
44 | #include "hw/pci/msi.h" | |
45 | #include "hw/sysbus.h" | |
46 | #include "sysemu/sysemu.h" | |
47 | #include "sysemu/numa.h" | |
48 | #include "sysemu/kvm.h" | |
49 | #include "sysemu/qtest.h" | |
50 | #include "kvm_i386.h" | |
51 | #include "hw/xen/xen.h" | |
52 | #include "sysemu/block-backend.h" | |
53 | #include "hw/block/block.h" | |
54 | #include "ui/qemu-spice.h" | |
55 | #include "exec/memory.h" | |
56 | #include "exec/address-spaces.h" | |
57 | #include "sysemu/arch_init.h" | |
58 | #include "qemu/bitmap.h" | |
59 | #include "qemu/config-file.h" | |
60 | #include "qemu/error-report.h" | |
61 | #include "hw/acpi/acpi.h" | |
62 | #include "hw/acpi/cpu_hotplug.h" | |
63 | #include "hw/boards.h" | |
64 | #include "hw/pci/pci_host.h" | |
65 | #include "acpi-build.h" | |
66 | #include "hw/mem/pc-dimm.h" | |
67 | #include "qapi/visitor.h" | |
68 | #include "qapi-visit.h" | |
69 | #include "qom/cpu.h" | |
70 | #include "hw/nmi.h" | |
71 | ||
72 | /* debug PC/ISA interrupts */ | |
73 | //#define DEBUG_IRQ | |
74 | ||
75 | #ifdef DEBUG_IRQ | |
76 | #define DPRINTF(fmt, ...) \ | |
77 | do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) | |
78 | #else | |
79 | #define DPRINTF(fmt, ...) | |
80 | #endif | |
81 | ||
82 | #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) | |
83 | #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) | |
84 | #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2) | |
85 | #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3) | |
86 | #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4) | |
87 | ||
88 | #define E820_NR_ENTRIES 16 | |
89 | ||
90 | struct e820_entry { | |
91 | uint64_t address; | |
92 | uint64_t length; | |
93 | uint32_t type; | |
94 | } QEMU_PACKED __attribute((__aligned__(4))); | |
95 | ||
96 | struct e820_table { | |
97 | uint32_t count; | |
98 | struct e820_entry entry[E820_NR_ENTRIES]; | |
99 | } QEMU_PACKED __attribute((__aligned__(4))); | |
100 | ||
101 | static struct e820_table e820_reserve; | |
102 | static struct e820_entry *e820_table; | |
103 | static unsigned e820_entries; | |
104 | struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; | |
105 | ||
106 | void gsi_handler(void *opaque, int n, int level) | |
107 | { | |
108 | GSIState *s = opaque; | |
109 | ||
110 | DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n); | |
111 | if (n < ISA_NUM_IRQS) { | |
112 | qemu_set_irq(s->i8259_irq[n], level); | |
113 | } | |
114 | qemu_set_irq(s->ioapic_irq[n], level); | |
115 | } | |
116 | ||
117 | static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, | |
118 | unsigned size) | |
119 | { | |
120 | } | |
121 | ||
122 | static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) | |
123 | { | |
124 | return 0xffffffffffffffffULL; | |
125 | } | |
126 | ||
127 | /* MSDOS compatibility mode FPU exception support */ | |
128 | static qemu_irq ferr_irq; | |
129 | ||
130 | void pc_register_ferr_irq(qemu_irq irq) | |
131 | { | |
132 | ferr_irq = irq; | |
133 | } | |
134 | ||
135 | /* XXX: add IGNNE support */ | |
136 | void cpu_set_ferr(CPUX86State *s) | |
137 | { | |
138 | qemu_irq_raise(ferr_irq); | |
139 | } | |
140 | ||
141 | static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, | |
142 | unsigned size) | |
143 | { | |
144 | qemu_irq_lower(ferr_irq); | |
145 | } | |
146 | ||
147 | static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) | |
148 | { | |
149 | return 0xffffffffffffffffULL; | |
150 | } | |
151 | ||
152 | /* TSC handling */ | |
153 | uint64_t cpu_get_tsc(CPUX86State *env) | |
154 | { | |
155 | return cpu_get_ticks(); | |
156 | } | |
157 | ||
158 | /* IRQ handling */ | |
159 | int cpu_get_pic_interrupt(CPUX86State *env) | |
160 | { | |
161 | X86CPU *cpu = x86_env_get_cpu(env); | |
162 | int intno; | |
163 | ||
164 | if (!kvm_irqchip_in_kernel()) { | |
165 | intno = apic_get_interrupt(cpu->apic_state); | |
166 | if (intno >= 0) { | |
167 | return intno; | |
168 | } | |
169 | /* read the irq from the PIC */ | |
170 | if (!apic_accept_pic_intr(cpu->apic_state)) { | |
171 | return -1; | |
172 | } | |
173 | } | |
174 | ||
175 | intno = pic_read_irq(isa_pic); | |
176 | return intno; | |
177 | } | |
178 | ||
179 | static void pic_irq_request(void *opaque, int irq, int level) | |
180 | { | |
181 | CPUState *cs = first_cpu; | |
182 | X86CPU *cpu = X86_CPU(cs); | |
183 | ||
184 | DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); | |
185 | if (cpu->apic_state && !kvm_irqchip_in_kernel()) { | |
186 | CPU_FOREACH(cs) { | |
187 | cpu = X86_CPU(cs); | |
188 | if (apic_accept_pic_intr(cpu->apic_state)) { | |
189 | apic_deliver_pic_intr(cpu->apic_state, level); | |
190 | } | |
191 | } | |
192 | } else { | |
193 | if (level) { | |
194 | cpu_interrupt(cs, CPU_INTERRUPT_HARD); | |
195 | } else { | |
196 | cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); | |
197 | } | |
198 | } | |
199 | } | |
200 | ||
201 | /* PC cmos mappings */ | |
202 | ||
203 | #define REG_EQUIPMENT_BYTE 0x14 | |
204 | ||
205 | int cmos_get_fd_drive_type(FloppyDriveType fd0) | |
206 | { | |
207 | int val; | |
208 | ||
209 | switch (fd0) { | |
210 | case FLOPPY_DRIVE_TYPE_144: | |
211 | /* 1.44 Mb 3"5 drive */ | |
212 | val = 4; | |
213 | break; | |
214 | case FLOPPY_DRIVE_TYPE_288: | |
215 | /* 2.88 Mb 3"5 drive */ | |
216 | val = 5; | |
217 | break; | |
218 | case FLOPPY_DRIVE_TYPE_120: | |
219 | /* 1.2 Mb 5"5 drive */ | |
220 | val = 2; | |
221 | break; | |
222 | case FLOPPY_DRIVE_TYPE_NONE: | |
223 | default: | |
224 | val = 0; | |
225 | break; | |
226 | } | |
227 | return val; | |
228 | } | |
229 | ||
230 | static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, | |
231 | int16_t cylinders, int8_t heads, int8_t sectors) | |
232 | { | |
233 | rtc_set_memory(s, type_ofs, 47); | |
234 | rtc_set_memory(s, info_ofs, cylinders); | |
235 | rtc_set_memory(s, info_ofs + 1, cylinders >> 8); | |
236 | rtc_set_memory(s, info_ofs + 2, heads); | |
237 | rtc_set_memory(s, info_ofs + 3, 0xff); | |
238 | rtc_set_memory(s, info_ofs + 4, 0xff); | |
239 | rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); | |
240 | rtc_set_memory(s, info_ofs + 6, cylinders); | |
241 | rtc_set_memory(s, info_ofs + 7, cylinders >> 8); | |
242 | rtc_set_memory(s, info_ofs + 8, sectors); | |
243 | } | |
244 | ||
245 | /* convert boot_device letter to something recognizable by the bios */ | |
246 | static int boot_device2nibble(char boot_device) | |
247 | { | |
248 | switch(boot_device) { | |
249 | case 'a': | |
250 | case 'b': | |
251 | return 0x01; /* floppy boot */ | |
252 | case 'c': | |
253 | return 0x02; /* hard drive boot */ | |
254 | case 'd': | |
255 | return 0x03; /* CD-ROM boot */ | |
256 | case 'n': | |
257 | return 0x04; /* Network boot */ | |
258 | } | |
259 | return 0; | |
260 | } | |
261 | ||
262 | static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) | |
263 | { | |
264 | #define PC_MAX_BOOT_DEVICES 3 | |
265 | int nbds, bds[3] = { 0, }; | |
266 | int i; | |
267 | ||
268 | nbds = strlen(boot_device); | |
269 | if (nbds > PC_MAX_BOOT_DEVICES) { | |
270 | error_setg(errp, "Too many boot devices for PC"); | |
271 | return; | |
272 | } | |
273 | for (i = 0; i < nbds; i++) { | |
274 | bds[i] = boot_device2nibble(boot_device[i]); | |
275 | if (bds[i] == 0) { | |
276 | error_setg(errp, "Invalid boot device for PC: '%c'", | |
277 | boot_device[i]); | |
278 | return; | |
279 | } | |
280 | } | |
281 | rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); | |
282 | rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); | |
283 | } | |
284 | ||
285 | static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) | |
286 | { | |
287 | set_boot_dev(opaque, boot_device, errp); | |
288 | } | |
289 | ||
290 | static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy) | |
291 | { | |
292 | int val, nb, i; | |
293 | FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, | |
294 | FLOPPY_DRIVE_TYPE_NONE }; | |
295 | ||
296 | /* floppy type */ | |
297 | if (floppy) { | |
298 | for (i = 0; i < 2; i++) { | |
299 | fd_type[i] = isa_fdc_get_drive_type(floppy, i); | |
300 | } | |
301 | } | |
302 | val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | | |
303 | cmos_get_fd_drive_type(fd_type[1]); | |
304 | rtc_set_memory(rtc_state, 0x10, val); | |
305 | ||
306 | val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE); | |
307 | nb = 0; | |
308 | if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { | |
309 | nb++; | |
310 | } | |
311 | if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { | |
312 | nb++; | |
313 | } | |
314 | switch (nb) { | |
315 | case 0: | |
316 | break; | |
317 | case 1: | |
318 | val |= 0x01; /* 1 drive, ready for boot */ | |
319 | break; | |
320 | case 2: | |
321 | val |= 0x41; /* 2 drives, ready for boot */ | |
322 | break; | |
323 | } | |
324 | rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val); | |
325 | } | |
326 | ||
327 | typedef struct pc_cmos_init_late_arg { | |
328 | ISADevice *rtc_state; | |
329 | BusState *idebus[2]; | |
330 | } pc_cmos_init_late_arg; | |
331 | ||
332 | typedef struct check_fdc_state { | |
333 | ISADevice *floppy; | |
334 | bool multiple; | |
335 | } CheckFdcState; | |
336 | ||
337 | static int check_fdc(Object *obj, void *opaque) | |
338 | { | |
339 | CheckFdcState *state = opaque; | |
340 | Object *fdc; | |
341 | uint32_t iobase; | |
342 | Error *local_err = NULL; | |
343 | ||
344 | fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); | |
345 | if (!fdc) { | |
346 | return 0; | |
347 | } | |
348 | ||
349 | iobase = object_property_get_int(obj, "iobase", &local_err); | |
350 | if (local_err || iobase != 0x3f0) { | |
351 | error_free(local_err); | |
352 | return 0; | |
353 | } | |
354 | ||
355 | if (state->floppy) { | |
356 | state->multiple = true; | |
357 | } else { | |
358 | state->floppy = ISA_DEVICE(obj); | |
359 | } | |
360 | return 0; | |
361 | } | |
362 | ||
363 | static const char * const fdc_container_path[] = { | |
364 | "/unattached", "/peripheral", "/peripheral-anon" | |
365 | }; | |
366 | ||
367 | /* | |
368 | * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers | |
369 | * and ACPI objects. | |
370 | */ | |
371 | ISADevice *pc_find_fdc0(void) | |
372 | { | |
373 | int i; | |
374 | Object *container; | |
375 | CheckFdcState state = { 0 }; | |
376 | ||
377 | for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { | |
378 | container = container_get(qdev_get_machine(), fdc_container_path[i]); | |
379 | object_child_foreach(container, check_fdc, &state); | |
380 | } | |
381 | ||
382 | if (state.multiple) { | |
383 | error_report("warning: multiple floppy disk controllers with " | |
384 | "iobase=0x3f0 have been found"); | |
385 | error_printf("the one being picked for CMOS setup might not reflect " | |
386 | "your intent\n"); | |
387 | } | |
388 | ||
389 | return state.floppy; | |
390 | } | |
391 | ||
392 | static void pc_cmos_init_late(void *opaque) | |
393 | { | |
394 | pc_cmos_init_late_arg *arg = opaque; | |
395 | ISADevice *s = arg->rtc_state; | |
396 | int16_t cylinders; | |
397 | int8_t heads, sectors; | |
398 | int val; | |
399 | int i, trans; | |
400 | ||
401 | val = 0; | |
402 | if (ide_get_geometry(arg->idebus[0], 0, | |
403 | &cylinders, &heads, §ors) >= 0) { | |
404 | cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); | |
405 | val |= 0xf0; | |
406 | } | |
407 | if (ide_get_geometry(arg->idebus[0], 1, | |
408 | &cylinders, &heads, §ors) >= 0) { | |
409 | cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); | |
410 | val |= 0x0f; | |
411 | } | |
412 | rtc_set_memory(s, 0x12, val); | |
413 | ||
414 | val = 0; | |
415 | for (i = 0; i < 4; i++) { | |
416 | /* NOTE: ide_get_geometry() returns the physical | |
417 | geometry. It is always such that: 1 <= sects <= 63, 1 | |
418 | <= heads <= 16, 1 <= cylinders <= 16383. The BIOS | |
419 | geometry can be different if a translation is done. */ | |
420 | if (ide_get_geometry(arg->idebus[i / 2], i % 2, | |
421 | &cylinders, &heads, §ors) >= 0) { | |
422 | trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; | |
423 | assert((trans & ~3) == 0); | |
424 | val |= trans << (i * 2); | |
425 | } | |
426 | } | |
427 | rtc_set_memory(s, 0x39, val); | |
428 | ||
429 | pc_cmos_init_floppy(s, pc_find_fdc0()); | |
430 | ||
431 | qemu_unregister_reset(pc_cmos_init_late, opaque); | |
432 | } | |
433 | ||
434 | void pc_cmos_init(PCMachineState *pcms, | |
435 | BusState *idebus0, BusState *idebus1, | |
436 | ISADevice *s) | |
437 | { | |
438 | int val; | |
439 | static pc_cmos_init_late_arg arg; | |
440 | ||
441 | /* various important CMOS locations needed by PC/Bochs bios */ | |
442 | ||
443 | /* memory size */ | |
444 | /* base memory (first MiB) */ | |
445 | val = MIN(pcms->below_4g_mem_size / 1024, 640); | |
446 | rtc_set_memory(s, 0x15, val); | |
447 | rtc_set_memory(s, 0x16, val >> 8); | |
448 | /* extended memory (next 64MiB) */ | |
449 | if (pcms->below_4g_mem_size > 1024 * 1024) { | |
450 | val = (pcms->below_4g_mem_size - 1024 * 1024) / 1024; | |
451 | } else { | |
452 | val = 0; | |
453 | } | |
454 | if (val > 65535) | |
455 | val = 65535; | |
456 | rtc_set_memory(s, 0x17, val); | |
457 | rtc_set_memory(s, 0x18, val >> 8); | |
458 | rtc_set_memory(s, 0x30, val); | |
459 | rtc_set_memory(s, 0x31, val >> 8); | |
460 | /* memory between 16MiB and 4GiB */ | |
461 | if (pcms->below_4g_mem_size > 16 * 1024 * 1024) { | |
462 | val = (pcms->below_4g_mem_size - 16 * 1024 * 1024) / 65536; | |
463 | } else { | |
464 | val = 0; | |
465 | } | |
466 | if (val > 65535) | |
467 | val = 65535; | |
468 | rtc_set_memory(s, 0x34, val); | |
469 | rtc_set_memory(s, 0x35, val >> 8); | |
470 | /* memory above 4GiB */ | |
471 | val = pcms->above_4g_mem_size / 65536; | |
472 | rtc_set_memory(s, 0x5b, val); | |
473 | rtc_set_memory(s, 0x5c, val >> 8); | |
474 | rtc_set_memory(s, 0x5d, val >> 16); | |
475 | ||
476 | object_property_add_link(OBJECT(pcms), "rtc_state", | |
477 | TYPE_ISA_DEVICE, | |
478 | (Object **)&pcms->rtc, | |
479 | object_property_allow_set_link, | |
480 | OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort); | |
481 | object_property_set_link(OBJECT(pcms), OBJECT(s), | |
482 | "rtc_state", &error_abort); | |
483 | ||
484 | set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal); | |
485 | ||
486 | val = 0; | |
487 | val |= 0x02; /* FPU is there */ | |
488 | val |= 0x04; /* PS/2 mouse installed */ | |
489 | rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); | |
490 | ||
491 | /* hard drives and FDC */ | |
492 | arg.rtc_state = s; | |
493 | arg.idebus[0] = idebus0; | |
494 | arg.idebus[1] = idebus1; | |
495 | qemu_register_reset(pc_cmos_init_late, &arg); | |
496 | } | |
497 | ||
498 | #define TYPE_PORT92 "port92" | |
499 | #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92) | |
500 | ||
501 | /* port 92 stuff: could be split off */ | |
502 | typedef struct Port92State { | |
503 | ISADevice parent_obj; | |
504 | ||
505 | MemoryRegion io; | |
506 | uint8_t outport; | |
507 | qemu_irq a20_out; | |
508 | } Port92State; | |
509 | ||
510 | static void port92_write(void *opaque, hwaddr addr, uint64_t val, | |
511 | unsigned size) | |
512 | { | |
513 | Port92State *s = opaque; | |
514 | int oldval = s->outport; | |
515 | ||
516 | DPRINTF("port92: write 0x%02" PRIx64 "\n", val); | |
517 | s->outport = val; | |
518 | qemu_set_irq(s->a20_out, (val >> 1) & 1); | |
519 | if ((val & 1) && !(oldval & 1)) { | |
520 | qemu_system_reset_request(); | |
521 | } | |
522 | } | |
523 | ||
524 | static uint64_t port92_read(void *opaque, hwaddr addr, | |
525 | unsigned size) | |
526 | { | |
527 | Port92State *s = opaque; | |
528 | uint32_t ret; | |
529 | ||
530 | ret = s->outport; | |
531 | DPRINTF("port92: read 0x%02x\n", ret); | |
532 | return ret; | |
533 | } | |
534 | ||
535 | static void port92_init(ISADevice *dev, qemu_irq a20_out) | |
536 | { | |
537 | qdev_connect_gpio_out_named(DEVICE(dev), PORT92_A20_LINE, 0, a20_out); | |
538 | } | |
539 | ||
540 | static const VMStateDescription vmstate_port92_isa = { | |
541 | .name = "port92", | |
542 | .version_id = 1, | |
543 | .minimum_version_id = 1, | |
544 | .fields = (VMStateField[]) { | |
545 | VMSTATE_UINT8(outport, Port92State), | |
546 | VMSTATE_END_OF_LIST() | |
547 | } | |
548 | }; | |
549 | ||
550 | static void port92_reset(DeviceState *d) | |
551 | { | |
552 | Port92State *s = PORT92(d); | |
553 | ||
554 | s->outport &= ~1; | |
555 | } | |
556 | ||
557 | static const MemoryRegionOps port92_ops = { | |
558 | .read = port92_read, | |
559 | .write = port92_write, | |
560 | .impl = { | |
561 | .min_access_size = 1, | |
562 | .max_access_size = 1, | |
563 | }, | |
564 | .endianness = DEVICE_LITTLE_ENDIAN, | |
565 | }; | |
566 | ||
567 | static void port92_initfn(Object *obj) | |
568 | { | |
569 | Port92State *s = PORT92(obj); | |
570 | ||
571 | memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1); | |
572 | ||
573 | s->outport = 0; | |
574 | ||
575 | qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, PORT92_A20_LINE, 1); | |
576 | } | |
577 | ||
578 | static void port92_realizefn(DeviceState *dev, Error **errp) | |
579 | { | |
580 | ISADevice *isadev = ISA_DEVICE(dev); | |
581 | Port92State *s = PORT92(dev); | |
582 | ||
583 | isa_register_ioport(isadev, &s->io, 0x92); | |
584 | } | |
585 | ||
586 | static void port92_class_initfn(ObjectClass *klass, void *data) | |
587 | { | |
588 | DeviceClass *dc = DEVICE_CLASS(klass); | |
589 | ||
590 | dc->realize = port92_realizefn; | |
591 | dc->reset = port92_reset; | |
592 | dc->vmsd = &vmstate_port92_isa; | |
593 | /* | |
594 | * Reason: unlike ordinary ISA devices, this one needs additional | |
595 | * wiring: its A20 output line needs to be wired up by | |
596 | * port92_init(). | |
597 | */ | |
598 | dc->cannot_instantiate_with_device_add_yet = true; | |
599 | } | |
600 | ||
601 | static const TypeInfo port92_info = { | |
602 | .name = TYPE_PORT92, | |
603 | .parent = TYPE_ISA_DEVICE, | |
604 | .instance_size = sizeof(Port92State), | |
605 | .instance_init = port92_initfn, | |
606 | .class_init = port92_class_initfn, | |
607 | }; | |
608 | ||
609 | static void port92_register_types(void) | |
610 | { | |
611 | type_register_static(&port92_info); | |
612 | } | |
613 | ||
614 | type_init(port92_register_types) | |
615 | ||
616 | static void handle_a20_line_change(void *opaque, int irq, int level) | |
617 | { | |
618 | X86CPU *cpu = opaque; | |
619 | ||
620 | /* XXX: send to all CPUs ? */ | |
621 | /* XXX: add logic to handle multiple A20 line sources */ | |
622 | x86_cpu_set_a20(cpu, level); | |
623 | } | |
624 | ||
625 | int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) | |
626 | { | |
627 | int index = le32_to_cpu(e820_reserve.count); | |
628 | struct e820_entry *entry; | |
629 | ||
630 | if (type != E820_RAM) { | |
631 | /* old FW_CFG_E820_TABLE entry -- reservations only */ | |
632 | if (index >= E820_NR_ENTRIES) { | |
633 | return -EBUSY; | |
634 | } | |
635 | entry = &e820_reserve.entry[index++]; | |
636 | ||
637 | entry->address = cpu_to_le64(address); | |
638 | entry->length = cpu_to_le64(length); | |
639 | entry->type = cpu_to_le32(type); | |
640 | ||
641 | e820_reserve.count = cpu_to_le32(index); | |
642 | } | |
643 | ||
644 | /* new "etc/e820" file -- include ram too */ | |
645 | e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1); | |
646 | e820_table[e820_entries].address = cpu_to_le64(address); | |
647 | e820_table[e820_entries].length = cpu_to_le64(length); | |
648 | e820_table[e820_entries].type = cpu_to_le32(type); | |
649 | e820_entries++; | |
650 | ||
651 | return e820_entries; | |
652 | } | |
653 | ||
654 | int e820_get_num_entries(void) | |
655 | { | |
656 | return e820_entries; | |
657 | } | |
658 | ||
659 | bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length) | |
660 | { | |
661 | if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) { | |
662 | *address = le64_to_cpu(e820_table[idx].address); | |
663 | *length = le64_to_cpu(e820_table[idx].length); | |
664 | return true; | |
665 | } | |
666 | return false; | |
667 | } | |
668 | ||
669 | /* Enables contiguous-apic-ID mode, for compatibility */ | |
670 | static bool compat_apic_id_mode; | |
671 | ||
672 | void enable_compat_apic_id_mode(void) | |
673 | { | |
674 | compat_apic_id_mode = true; | |
675 | } | |
676 | ||
677 | /* Calculates initial APIC ID for a specific CPU index | |
678 | * | |
679 | * Currently we need to be able to calculate the APIC ID from the CPU index | |
680 | * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have | |
681 | * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of | |
682 | * all CPUs up to max_cpus. | |
683 | */ | |
684 | static uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index) | |
685 | { | |
686 | uint32_t correct_id; | |
687 | static bool warned; | |
688 | ||
689 | correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index); | |
690 | if (compat_apic_id_mode) { | |
691 | if (cpu_index != correct_id && !warned && !qtest_enabled()) { | |
692 | error_report("APIC IDs set in compatibility mode, " | |
693 | "CPU topology won't match the configuration"); | |
694 | warned = true; | |
695 | } | |
696 | return cpu_index; | |
697 | } else { | |
698 | return correct_id; | |
699 | } | |
700 | } | |
701 | ||
702 | static void pc_build_smbios(FWCfgState *fw_cfg) | |
703 | { | |
704 | uint8_t *smbios_tables, *smbios_anchor; | |
705 | size_t smbios_tables_len, smbios_anchor_len; | |
706 | struct smbios_phys_mem_area *mem_array; | |
707 | unsigned i, array_count; | |
708 | ||
709 | smbios_tables = smbios_get_table_legacy(&smbios_tables_len); | |
710 | if (smbios_tables) { | |
711 | fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES, | |
712 | smbios_tables, smbios_tables_len); | |
713 | } | |
714 | ||
715 | /* build the array of physical mem area from e820 table */ | |
716 | mem_array = g_malloc0(sizeof(*mem_array) * e820_get_num_entries()); | |
717 | for (i = 0, array_count = 0; i < e820_get_num_entries(); i++) { | |
718 | uint64_t addr, len; | |
719 | ||
720 | if (e820_get_entry(i, E820_RAM, &addr, &len)) { | |
721 | mem_array[array_count].address = addr; | |
722 | mem_array[array_count].length = len; | |
723 | array_count++; | |
724 | } | |
725 | } | |
726 | smbios_get_tables(mem_array, array_count, | |
727 | &smbios_tables, &smbios_tables_len, | |
728 | &smbios_anchor, &smbios_anchor_len); | |
729 | g_free(mem_array); | |
730 | ||
731 | if (smbios_anchor) { | |
732 | fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-tables", | |
733 | smbios_tables, smbios_tables_len); | |
734 | fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-anchor", | |
735 | smbios_anchor, smbios_anchor_len); | |
736 | } | |
737 | } | |
738 | ||
739 | static FWCfgState *bochs_bios_init(AddressSpace *as, PCMachineState *pcms) | |
740 | { | |
741 | FWCfgState *fw_cfg; | |
742 | uint64_t *numa_fw_cfg; | |
743 | int i, j; | |
744 | ||
745 | fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, as); | |
746 | ||
747 | /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86: | |
748 | * | |
749 | * SeaBIOS needs FW_CFG_MAX_CPUS for CPU hotplug, but the CPU hotplug | |
750 | * QEMU<->SeaBIOS interface is not based on the "CPU index", but on the APIC | |
751 | * ID of hotplugged CPUs[1]. This means that FW_CFG_MAX_CPUS is not the | |
752 | * "maximum number of CPUs", but the "limit to the APIC ID values SeaBIOS | |
753 | * may see". | |
754 | * | |
755 | * So, this means we must not use max_cpus, here, but the maximum possible | |
756 | * APIC ID value, plus one. | |
757 | * | |
758 | * [1] The only kind of "CPU identifier" used between SeaBIOS and QEMU is | |
759 | * the APIC ID, not the "CPU index" | |
760 | */ | |
761 | fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)pcms->apic_id_limit); | |
762 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); | |
763 | fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, | |
764 | acpi_tables, acpi_tables_len); | |
765 | fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override()); | |
766 | ||
767 | fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, | |
768 | &e820_reserve, sizeof(e820_reserve)); | |
769 | fw_cfg_add_file(fw_cfg, "etc/e820", e820_table, | |
770 | sizeof(struct e820_entry) * e820_entries); | |
771 | ||
772 | fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg)); | |
773 | /* allocate memory for the NUMA channel: one (64bit) word for the number | |
774 | * of nodes, one word for each VCPU->node and one word for each node to | |
775 | * hold the amount of memory. | |
776 | */ | |
777 | numa_fw_cfg = g_new0(uint64_t, 1 + pcms->apic_id_limit + nb_numa_nodes); | |
778 | numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); | |
779 | for (i = 0; i < max_cpus; i++) { | |
780 | unsigned int apic_id = x86_cpu_apic_id_from_index(i); | |
781 | assert(apic_id < pcms->apic_id_limit); | |
782 | j = numa_get_node_for_cpu(i); | |
783 | if (j < nb_numa_nodes) { | |
784 | numa_fw_cfg[apic_id + 1] = cpu_to_le64(j); | |
785 | } | |
786 | } | |
787 | for (i = 0; i < nb_numa_nodes; i++) { | |
788 | numa_fw_cfg[pcms->apic_id_limit + 1 + i] = | |
789 | cpu_to_le64(numa_info[i].node_mem); | |
790 | } | |
791 | fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg, | |
792 | (1 + pcms->apic_id_limit + nb_numa_nodes) * | |
793 | sizeof(*numa_fw_cfg)); | |
794 | ||
795 | return fw_cfg; | |
796 | } | |
797 | ||
798 | static long get_file_size(FILE *f) | |
799 | { | |
800 | long where, size; | |
801 | ||
802 | /* XXX: on Unix systems, using fstat() probably makes more sense */ | |
803 | ||
804 | where = ftell(f); | |
805 | fseek(f, 0, SEEK_END); | |
806 | size = ftell(f); | |
807 | fseek(f, where, SEEK_SET); | |
808 | ||
809 | return size; | |
810 | } | |
811 | ||
812 | /* setup_data types */ | |
813 | #define SETUP_NONE 0 | |
814 | #define SETUP_E820_EXT 1 | |
815 | #define SETUP_DTB 2 | |
816 | #define SETUP_PCI 3 | |
817 | #define SETUP_EFI 4 | |
818 | ||
819 | struct setup_data { | |
820 | uint64_t next; | |
821 | uint32_t type; | |
822 | uint32_t len; | |
823 | uint8_t data[0]; | |
824 | } __attribute__((packed)); | |
825 | ||
826 | static void load_linux(PCMachineState *pcms, | |
827 | FWCfgState *fw_cfg) | |
828 | { | |
829 | uint16_t protocol; | |
830 | int setup_size, kernel_size, initrd_size = 0, cmdline_size; | |
831 | int dtb_size, setup_data_offset; | |
832 | uint32_t initrd_max; | |
833 | uint8_t header[8192], *setup, *kernel, *initrd_data; | |
834 | hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0; | |
835 | FILE *f; | |
836 | char *vmode; | |
837 | MachineState *machine = MACHINE(pcms); | |
838 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); | |
839 | struct setup_data *setup_data; | |
840 | const char *kernel_filename = machine->kernel_filename; | |
841 | const char *initrd_filename = machine->initrd_filename; | |
842 | const char *dtb_filename = machine->dtb; | |
843 | const char *kernel_cmdline = machine->kernel_cmdline; | |
844 | ||
845 | /* Align to 16 bytes as a paranoia measure */ | |
846 | cmdline_size = (strlen(kernel_cmdline)+16) & ~15; | |
847 | ||
848 | /* load the kernel header */ | |
849 | f = fopen(kernel_filename, "rb"); | |
850 | if (!f || !(kernel_size = get_file_size(f)) || | |
851 | fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != | |
852 | MIN(ARRAY_SIZE(header), kernel_size)) { | |
853 | fprintf(stderr, "qemu: could not load kernel '%s': %s\n", | |
854 | kernel_filename, strerror(errno)); | |
855 | exit(1); | |
856 | } | |
857 | ||
858 | /* kernel protocol version */ | |
859 | #if 0 | |
860 | fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); | |
861 | #endif | |
862 | if (ldl_p(header+0x202) == 0x53726448) { | |
863 | protocol = lduw_p(header+0x206); | |
864 | } else { | |
865 | /* This looks like a multiboot kernel. If it is, let's stop | |
866 | treating it like a Linux kernel. */ | |
867 | if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename, | |
868 | kernel_cmdline, kernel_size, header)) { | |
869 | return; | |
870 | } | |
871 | protocol = 0; | |
872 | } | |
873 | ||
874 | if (protocol < 0x200 || !(header[0x211] & 0x01)) { | |
875 | /* Low kernel */ | |
876 | real_addr = 0x90000; | |
877 | cmdline_addr = 0x9a000 - cmdline_size; | |
878 | prot_addr = 0x10000; | |
879 | } else if (protocol < 0x202) { | |
880 | /* High but ancient kernel */ | |
881 | real_addr = 0x90000; | |
882 | cmdline_addr = 0x9a000 - cmdline_size; | |
883 | prot_addr = 0x100000; | |
884 | } else { | |
885 | /* High and recent kernel */ | |
886 | real_addr = 0x10000; | |
887 | cmdline_addr = 0x20000; | |
888 | prot_addr = 0x100000; | |
889 | } | |
890 | ||
891 | #if 0 | |
892 | fprintf(stderr, | |
893 | "qemu: real_addr = 0x" TARGET_FMT_plx "\n" | |
894 | "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n" | |
895 | "qemu: prot_addr = 0x" TARGET_FMT_plx "\n", | |
896 | real_addr, | |
897 | cmdline_addr, | |
898 | prot_addr); | |
899 | #endif | |
900 | ||
901 | /* highest address for loading the initrd */ | |
902 | if (protocol >= 0x203) { | |
903 | initrd_max = ldl_p(header+0x22c); | |
904 | } else { | |
905 | initrd_max = 0x37ffffff; | |
906 | } | |
907 | ||
908 | if (initrd_max >= pcms->below_4g_mem_size - pcmc->acpi_data_size) { | |
909 | initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1; | |
910 | } | |
911 | ||
912 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); | |
913 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1); | |
914 | fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); | |
915 | ||
916 | if (protocol >= 0x202) { | |
917 | stl_p(header+0x228, cmdline_addr); | |
918 | } else { | |
919 | stw_p(header+0x20, 0xA33F); | |
920 | stw_p(header+0x22, cmdline_addr-real_addr); | |
921 | } | |
922 | ||
923 | /* handle vga= parameter */ | |
924 | vmode = strstr(kernel_cmdline, "vga="); | |
925 | if (vmode) { | |
926 | unsigned int video_mode; | |
927 | /* skip "vga=" */ | |
928 | vmode += 4; | |
929 | if (!strncmp(vmode, "normal", 6)) { | |
930 | video_mode = 0xffff; | |
931 | } else if (!strncmp(vmode, "ext", 3)) { | |
932 | video_mode = 0xfffe; | |
933 | } else if (!strncmp(vmode, "ask", 3)) { | |
934 | video_mode = 0xfffd; | |
935 | } else { | |
936 | video_mode = strtol(vmode, NULL, 0); | |
937 | } | |
938 | stw_p(header+0x1fa, video_mode); | |
939 | } | |
940 | ||
941 | /* loader type */ | |
942 | /* High nybble = B reserved for QEMU; low nybble is revision number. | |
943 | If this code is substantially changed, you may want to consider | |
944 | incrementing the revision. */ | |
945 | if (protocol >= 0x200) { | |
946 | header[0x210] = 0xB0; | |
947 | } | |
948 | /* heap */ | |
949 | if (protocol >= 0x201) { | |
950 | header[0x211] |= 0x80; /* CAN_USE_HEAP */ | |
951 | stw_p(header+0x224, cmdline_addr-real_addr-0x200); | |
952 | } | |
953 | ||
954 | /* load initrd */ | |
955 | if (initrd_filename) { | |
956 | if (protocol < 0x200) { | |
957 | fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); | |
958 | exit(1); | |
959 | } | |
960 | ||
961 | initrd_size = get_image_size(initrd_filename); | |
962 | if (initrd_size < 0) { | |
963 | fprintf(stderr, "qemu: error reading initrd %s: %s\n", | |
964 | initrd_filename, strerror(errno)); | |
965 | exit(1); | |
966 | } | |
967 | ||
968 | initrd_addr = (initrd_max-initrd_size) & ~4095; | |
969 | ||
970 | initrd_data = g_malloc(initrd_size); | |
971 | load_image(initrd_filename, initrd_data); | |
972 | ||
973 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); | |
974 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); | |
975 | fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); | |
976 | ||
977 | stl_p(header+0x218, initrd_addr); | |
978 | stl_p(header+0x21c, initrd_size); | |
979 | } | |
980 | ||
981 | /* load kernel and setup */ | |
982 | setup_size = header[0x1f1]; | |
983 | if (setup_size == 0) { | |
984 | setup_size = 4; | |
985 | } | |
986 | setup_size = (setup_size+1)*512; | |
987 | if (setup_size > kernel_size) { | |
988 | fprintf(stderr, "qemu: invalid kernel header\n"); | |
989 | exit(1); | |
990 | } | |
991 | kernel_size -= setup_size; | |
992 | ||
993 | setup = g_malloc(setup_size); | |
994 | kernel = g_malloc(kernel_size); | |
995 | fseek(f, 0, SEEK_SET); | |
996 | if (fread(setup, 1, setup_size, f) != setup_size) { | |
997 | fprintf(stderr, "fread() failed\n"); | |
998 | exit(1); | |
999 | } | |
1000 | if (fread(kernel, 1, kernel_size, f) != kernel_size) { | |
1001 | fprintf(stderr, "fread() failed\n"); | |
1002 | exit(1); | |
1003 | } | |
1004 | fclose(f); | |
1005 | ||
1006 | /* append dtb to kernel */ | |
1007 | if (dtb_filename) { | |
1008 | if (protocol < 0x209) { | |
1009 | fprintf(stderr, "qemu: Linux kernel too old to load a dtb\n"); | |
1010 | exit(1); | |
1011 | } | |
1012 | ||
1013 | dtb_size = get_image_size(dtb_filename); | |
1014 | if (dtb_size <= 0) { | |
1015 | fprintf(stderr, "qemu: error reading dtb %s: %s\n", | |
1016 | dtb_filename, strerror(errno)); | |
1017 | exit(1); | |
1018 | } | |
1019 | ||
1020 | setup_data_offset = QEMU_ALIGN_UP(kernel_size, 16); | |
1021 | kernel_size = setup_data_offset + sizeof(struct setup_data) + dtb_size; | |
1022 | kernel = g_realloc(kernel, kernel_size); | |
1023 | ||
1024 | stq_p(header+0x250, prot_addr + setup_data_offset); | |
1025 | ||
1026 | setup_data = (struct setup_data *)(kernel + setup_data_offset); | |
1027 | setup_data->next = 0; | |
1028 | setup_data->type = cpu_to_le32(SETUP_DTB); | |
1029 | setup_data->len = cpu_to_le32(dtb_size); | |
1030 | ||
1031 | load_image_size(dtb_filename, setup_data->data, dtb_size); | |
1032 | } | |
1033 | ||
1034 | memcpy(setup, header, MIN(sizeof(header), setup_size)); | |
1035 | ||
1036 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); | |
1037 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); | |
1038 | fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); | |
1039 | ||
1040 | fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); | |
1041 | fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); | |
1042 | fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); | |
1043 | ||
1044 | if (fw_cfg_dma_enabled(fw_cfg)) { | |
1045 | option_rom[nb_option_roms].name = "linuxboot_dma.bin"; | |
1046 | option_rom[nb_option_roms].bootindex = 0; | |
1047 | } else { | |
1048 | option_rom[nb_option_roms].name = "linuxboot.bin"; | |
1049 | option_rom[nb_option_roms].bootindex = 0; | |
1050 | } | |
1051 | nb_option_roms++; | |
1052 | } | |
1053 | ||
1054 | #define NE2000_NB_MAX 6 | |
1055 | ||
1056 | static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, | |
1057 | 0x280, 0x380 }; | |
1058 | static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; | |
1059 | ||
1060 | void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) | |
1061 | { | |
1062 | static int nb_ne2k = 0; | |
1063 | ||
1064 | if (nb_ne2k == NE2000_NB_MAX) | |
1065 | return; | |
1066 | isa_ne2000_init(bus, ne2000_io[nb_ne2k], | |
1067 | ne2000_irq[nb_ne2k], nd); | |
1068 | nb_ne2k++; | |
1069 | } | |
1070 | ||
1071 | DeviceState *cpu_get_current_apic(void) | |
1072 | { | |
1073 | if (current_cpu) { | |
1074 | X86CPU *cpu = X86_CPU(current_cpu); | |
1075 | return cpu->apic_state; | |
1076 | } else { | |
1077 | return NULL; | |
1078 | } | |
1079 | } | |
1080 | ||
1081 | void pc_acpi_smi_interrupt(void *opaque, int irq, int level) | |
1082 | { | |
1083 | X86CPU *cpu = opaque; | |
1084 | ||
1085 | if (level) { | |
1086 | cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); | |
1087 | } | |
1088 | } | |
1089 | ||
1090 | static int pc_present_cpus_count(PCMachineState *pcms) | |
1091 | { | |
1092 | int i, boot_cpus = 0; | |
1093 | for (i = 0; i < pcms->possible_cpus->len; i++) { | |
1094 | if (pcms->possible_cpus->cpus[i].cpu) { | |
1095 | boot_cpus++; | |
1096 | } | |
1097 | } | |
1098 | return boot_cpus; | |
1099 | } | |
1100 | ||
1101 | static X86CPU *pc_new_cpu(const char *typename, int64_t apic_id, | |
1102 | Error **errp) | |
1103 | { | |
1104 | X86CPU *cpu = NULL; | |
1105 | Error *local_err = NULL; | |
1106 | ||
1107 | cpu = X86_CPU(object_new(typename)); | |
1108 | ||
1109 | object_property_set_int(OBJECT(cpu), apic_id, "apic-id", &local_err); | |
1110 | object_property_set_bool(OBJECT(cpu), true, "realized", &local_err); | |
1111 | ||
1112 | if (local_err) { | |
1113 | error_propagate(errp, local_err); | |
1114 | object_unref(OBJECT(cpu)); | |
1115 | cpu = NULL; | |
1116 | } | |
1117 | return cpu; | |
1118 | } | |
1119 | ||
1120 | void pc_hot_add_cpu(const int64_t id, Error **errp) | |
1121 | { | |
1122 | X86CPU *cpu; | |
1123 | ObjectClass *oc; | |
1124 | PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); | |
1125 | int64_t apic_id = x86_cpu_apic_id_from_index(id); | |
1126 | Error *local_err = NULL; | |
1127 | ||
1128 | if (id < 0) { | |
1129 | error_setg(errp, "Invalid CPU id: %" PRIi64, id); | |
1130 | return; | |
1131 | } | |
1132 | ||
1133 | if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) { | |
1134 | error_setg(errp, "Unable to add CPU: %" PRIi64 | |
1135 | ", resulting APIC ID (%" PRIi64 ") is too large", | |
1136 | id, apic_id); | |
1137 | return; | |
1138 | } | |
1139 | ||
1140 | assert(pcms->possible_cpus->cpus[0].cpu); /* BSP is always present */ | |
1141 | oc = OBJECT_CLASS(CPU_GET_CLASS(pcms->possible_cpus->cpus[0].cpu)); | |
1142 | cpu = pc_new_cpu(object_class_get_name(oc), apic_id, &local_err); | |
1143 | if (local_err) { | |
1144 | error_propagate(errp, local_err); | |
1145 | return; | |
1146 | } | |
1147 | object_unref(OBJECT(cpu)); | |
1148 | } | |
1149 | ||
1150 | void pc_cpus_init(PCMachineState *pcms) | |
1151 | { | |
1152 | int i; | |
1153 | CPUClass *cc; | |
1154 | ObjectClass *oc; | |
1155 | const char *typename; | |
1156 | gchar **model_pieces; | |
1157 | X86CPU *cpu = NULL; | |
1158 | MachineState *machine = MACHINE(pcms); | |
1159 | ||
1160 | /* init CPUs */ | |
1161 | if (machine->cpu_model == NULL) { | |
1162 | #ifdef TARGET_X86_64 | |
1163 | machine->cpu_model = "qemu64"; | |
1164 | #else | |
1165 | machine->cpu_model = "qemu32"; | |
1166 | #endif | |
1167 | } | |
1168 | ||
1169 | model_pieces = g_strsplit(machine->cpu_model, ",", 2); | |
1170 | if (!model_pieces[0]) { | |
1171 | error_report("Invalid/empty CPU model name"); | |
1172 | exit(1); | |
1173 | } | |
1174 | ||
1175 | oc = cpu_class_by_name(TYPE_X86_CPU, model_pieces[0]); | |
1176 | if (oc == NULL) { | |
1177 | error_report("Unable to find CPU definition: %s", model_pieces[0]); | |
1178 | exit(1); | |
1179 | } | |
1180 | typename = object_class_get_name(oc); | |
1181 | cc = CPU_CLASS(oc); | |
1182 | cc->parse_features(typename, model_pieces[1], &error_fatal); | |
1183 | g_strfreev(model_pieces); | |
1184 | ||
1185 | /* Calculates the limit to CPU APIC ID values | |
1186 | * | |
1187 | * Limit for the APIC ID value, so that all | |
1188 | * CPU APIC IDs are < pcms->apic_id_limit. | |
1189 | * | |
1190 | * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init(). | |
1191 | */ | |
1192 | pcms->apic_id_limit = x86_cpu_apic_id_from_index(max_cpus - 1) + 1; | |
1193 | if (pcms->apic_id_limit > ACPI_CPU_HOTPLUG_ID_LIMIT) { | |
1194 | error_report("max_cpus is too large. APIC ID of last CPU is %u", | |
1195 | pcms->apic_id_limit - 1); | |
1196 | exit(1); | |
1197 | } | |
1198 | ||
1199 | pcms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + | |
1200 | sizeof(CPUArchId) * max_cpus); | |
1201 | for (i = 0; i < max_cpus; i++) { | |
1202 | pcms->possible_cpus->cpus[i].arch_id = x86_cpu_apic_id_from_index(i); | |
1203 | pcms->possible_cpus->len++; | |
1204 | if (i < smp_cpus) { | |
1205 | cpu = pc_new_cpu(typename, x86_cpu_apic_id_from_index(i), | |
1206 | &error_fatal); | |
1207 | object_unref(OBJECT(cpu)); | |
1208 | } | |
1209 | } | |
1210 | ||
1211 | /* tell smbios about cpuid version and features */ | |
1212 | smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]); | |
1213 | } | |
1214 | ||
1215 | static void pc_build_feature_control_file(PCMachineState *pcms) | |
1216 | { | |
1217 | X86CPU *cpu = X86_CPU(pcms->possible_cpus->cpus[0].cpu); | |
1218 | CPUX86State *env = &cpu->env; | |
1219 | uint32_t unused, ecx, edx; | |
1220 | uint64_t feature_control_bits = 0; | |
1221 | uint64_t *val; | |
1222 | ||
1223 | cpu_x86_cpuid(env, 1, 0, &unused, &unused, &ecx, &edx); | |
1224 | if (ecx & CPUID_EXT_VMX) { | |
1225 | feature_control_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; | |
1226 | } | |
1227 | ||
1228 | if ((edx & (CPUID_EXT2_MCE | CPUID_EXT2_MCA)) == | |
1229 | (CPUID_EXT2_MCE | CPUID_EXT2_MCA) && | |
1230 | (env->mcg_cap & MCG_LMCE_P)) { | |
1231 | feature_control_bits |= FEATURE_CONTROL_LMCE; | |
1232 | } | |
1233 | ||
1234 | if (!feature_control_bits) { | |
1235 | return; | |
1236 | } | |
1237 | ||
1238 | val = g_malloc(sizeof(*val)); | |
1239 | *val = cpu_to_le64(feature_control_bits | FEATURE_CONTROL_LOCKED); | |
1240 | fw_cfg_add_file(pcms->fw_cfg, "etc/msr_feature_control", val, sizeof(*val)); | |
1241 | } | |
1242 | ||
1243 | static | |
1244 | void pc_machine_done(Notifier *notifier, void *data) | |
1245 | { | |
1246 | PCMachineState *pcms = container_of(notifier, | |
1247 | PCMachineState, machine_done); | |
1248 | PCIBus *bus = pcms->bus; | |
1249 | ||
1250 | /* set the number of CPUs */ | |
1251 | rtc_set_memory(pcms->rtc, 0x5f, pc_present_cpus_count(pcms) - 1); | |
1252 | ||
1253 | if (bus) { | |
1254 | int extra_hosts = 0; | |
1255 | ||
1256 | QLIST_FOREACH(bus, &bus->child, sibling) { | |
1257 | /* look for expander root buses */ | |
1258 | if (pci_bus_is_root(bus)) { | |
1259 | extra_hosts++; | |
1260 | } | |
1261 | } | |
1262 | if (extra_hosts && pcms->fw_cfg) { | |
1263 | uint64_t *val = g_malloc(sizeof(*val)); | |
1264 | *val = cpu_to_le64(extra_hosts); | |
1265 | fw_cfg_add_file(pcms->fw_cfg, | |
1266 | "etc/extra-pci-roots", val, sizeof(*val)); | |
1267 | } | |
1268 | } | |
1269 | ||
1270 | acpi_setup(); | |
1271 | if (pcms->fw_cfg) { | |
1272 | pc_build_smbios(pcms->fw_cfg); | |
1273 | pc_build_feature_control_file(pcms); | |
1274 | } | |
1275 | } | |
1276 | ||
1277 | void pc_guest_info_init(PCMachineState *pcms) | |
1278 | { | |
1279 | int i; | |
1280 | ||
1281 | pcms->apic_xrupt_override = kvm_allows_irq0_override(); | |
1282 | pcms->numa_nodes = nb_numa_nodes; | |
1283 | pcms->node_mem = g_malloc0(pcms->numa_nodes * | |
1284 | sizeof *pcms->node_mem); | |
1285 | for (i = 0; i < nb_numa_nodes; i++) { | |
1286 | pcms->node_mem[i] = numa_info[i].node_mem; | |
1287 | } | |
1288 | ||
1289 | pcms->machine_done.notify = pc_machine_done; | |
1290 | qemu_add_machine_init_done_notifier(&pcms->machine_done); | |
1291 | } | |
1292 | ||
1293 | /* setup pci memory address space mapping into system address space */ | |
1294 | void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, | |
1295 | MemoryRegion *pci_address_space) | |
1296 | { | |
1297 | /* Set to lower priority than RAM */ | |
1298 | memory_region_add_subregion_overlap(system_memory, 0x0, | |
1299 | pci_address_space, -1); | |
1300 | } | |
1301 | ||
1302 | void pc_acpi_init(const char *default_dsdt) | |
1303 | { | |
1304 | char *filename; | |
1305 | ||
1306 | if (acpi_tables != NULL) { | |
1307 | /* manually set via -acpitable, leave it alone */ | |
1308 | return; | |
1309 | } | |
1310 | ||
1311 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt); | |
1312 | if (filename == NULL) { | |
1313 | fprintf(stderr, "WARNING: failed to find %s\n", default_dsdt); | |
1314 | } else { | |
1315 | QemuOpts *opts = qemu_opts_create(qemu_find_opts("acpi"), NULL, 0, | |
1316 | &error_abort); | |
1317 | Error *err = NULL; | |
1318 | ||
1319 | qemu_opt_set(opts, "file", filename, &error_abort); | |
1320 | ||
1321 | acpi_table_add_builtin(opts, &err); | |
1322 | if (err) { | |
1323 | error_reportf_err(err, "WARNING: failed to load %s: ", | |
1324 | filename); | |
1325 | } | |
1326 | g_free(filename); | |
1327 | } | |
1328 | } | |
1329 | ||
1330 | void xen_load_linux(PCMachineState *pcms) | |
1331 | { | |
1332 | int i; | |
1333 | FWCfgState *fw_cfg; | |
1334 | ||
1335 | assert(MACHINE(pcms)->kernel_filename != NULL); | |
1336 | ||
1337 | fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE); | |
1338 | rom_set_fw(fw_cfg); | |
1339 | ||
1340 | load_linux(pcms, fw_cfg); | |
1341 | for (i = 0; i < nb_option_roms; i++) { | |
1342 | assert(!strcmp(option_rom[i].name, "linuxboot.bin") || | |
1343 | !strcmp(option_rom[i].name, "linuxboot_dma.bin") || | |
1344 | !strcmp(option_rom[i].name, "multiboot.bin")); | |
1345 | rom_add_option(option_rom[i].name, option_rom[i].bootindex); | |
1346 | } | |
1347 | pcms->fw_cfg = fw_cfg; | |
1348 | } | |
1349 | ||
1350 | void pc_memory_init(PCMachineState *pcms, | |
1351 | MemoryRegion *system_memory, | |
1352 | MemoryRegion *rom_memory, | |
1353 | MemoryRegion **ram_memory) | |
1354 | { | |
1355 | int linux_boot, i; | |
1356 | MemoryRegion *ram, *option_rom_mr; | |
1357 | MemoryRegion *ram_below_4g, *ram_above_4g; | |
1358 | FWCfgState *fw_cfg; | |
1359 | MachineState *machine = MACHINE(pcms); | |
1360 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); | |
1361 | ||
1362 | assert(machine->ram_size == pcms->below_4g_mem_size + | |
1363 | pcms->above_4g_mem_size); | |
1364 | ||
1365 | linux_boot = (machine->kernel_filename != NULL); | |
1366 | ||
1367 | /* Allocate RAM. We allocate it as a single memory region and use | |
1368 | * aliases to address portions of it, mostly for backwards compatibility | |
1369 | * with older qemus that used qemu_ram_alloc(). | |
1370 | */ | |
1371 | ram = g_malloc(sizeof(*ram)); | |
1372 | memory_region_allocate_system_memory(ram, NULL, "pc.ram", | |
1373 | machine->ram_size); | |
1374 | *ram_memory = ram; | |
1375 | ram_below_4g = g_malloc(sizeof(*ram_below_4g)); | |
1376 | memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram, | |
1377 | 0, pcms->below_4g_mem_size); | |
1378 | memory_region_add_subregion(system_memory, 0, ram_below_4g); | |
1379 | e820_add_entry(0, pcms->below_4g_mem_size, E820_RAM); | |
1380 | if (pcms->above_4g_mem_size > 0) { | |
1381 | ram_above_4g = g_malloc(sizeof(*ram_above_4g)); | |
1382 | memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram, | |
1383 | pcms->below_4g_mem_size, | |
1384 | pcms->above_4g_mem_size); | |
1385 | memory_region_add_subregion(system_memory, 0x100000000ULL, | |
1386 | ram_above_4g); | |
1387 | e820_add_entry(0x100000000ULL, pcms->above_4g_mem_size, E820_RAM); | |
1388 | } | |
1389 | ||
1390 | if (!pcmc->has_reserved_memory && | |
1391 | (machine->ram_slots || | |
1392 | (machine->maxram_size > machine->ram_size))) { | |
1393 | MachineClass *mc = MACHINE_GET_CLASS(machine); | |
1394 | ||
1395 | error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", | |
1396 | mc->name); | |
1397 | exit(EXIT_FAILURE); | |
1398 | } | |
1399 | ||
1400 | /* initialize hotplug memory address space */ | |
1401 | if (pcmc->has_reserved_memory && | |
1402 | (machine->ram_size < machine->maxram_size)) { | |
1403 | ram_addr_t hotplug_mem_size = | |
1404 | machine->maxram_size - machine->ram_size; | |
1405 | ||
1406 | if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { | |
1407 | error_report("unsupported amount of memory slots: %"PRIu64, | |
1408 | machine->ram_slots); | |
1409 | exit(EXIT_FAILURE); | |
1410 | } | |
1411 | ||
1412 | if (QEMU_ALIGN_UP(machine->maxram_size, | |
1413 | TARGET_PAGE_SIZE) != machine->maxram_size) { | |
1414 | error_report("maximum memory size must by aligned to multiple of " | |
1415 | "%d bytes", TARGET_PAGE_SIZE); | |
1416 | exit(EXIT_FAILURE); | |
1417 | } | |
1418 | ||
1419 | pcms->hotplug_memory.base = | |
1420 | ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, 1ULL << 30); | |
1421 | ||
1422 | if (pcmc->enforce_aligned_dimm) { | |
1423 | /* size hotplug region assuming 1G page max alignment per slot */ | |
1424 | hotplug_mem_size += (1ULL << 30) * machine->ram_slots; | |
1425 | } | |
1426 | ||
1427 | if ((pcms->hotplug_memory.base + hotplug_mem_size) < | |
1428 | hotplug_mem_size) { | |
1429 | error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, | |
1430 | machine->maxram_size); | |
1431 | exit(EXIT_FAILURE); | |
1432 | } | |
1433 | ||
1434 | memory_region_init(&pcms->hotplug_memory.mr, OBJECT(pcms), | |
1435 | "hotplug-memory", hotplug_mem_size); | |
1436 | memory_region_add_subregion(system_memory, pcms->hotplug_memory.base, | |
1437 | &pcms->hotplug_memory.mr); | |
1438 | } | |
1439 | ||
1440 | /* Initialize PC system firmware */ | |
1441 | pc_system_firmware_init(rom_memory, !pcmc->pci_enabled); | |
1442 | ||
1443 | option_rom_mr = g_malloc(sizeof(*option_rom_mr)); | |
1444 | memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, | |
1445 | &error_fatal); | |
1446 | vmstate_register_ram_global(option_rom_mr); | |
1447 | memory_region_add_subregion_overlap(rom_memory, | |
1448 | PC_ROM_MIN_VGA, | |
1449 | option_rom_mr, | |
1450 | 1); | |
1451 | ||
1452 | fw_cfg = bochs_bios_init(&address_space_memory, pcms); | |
1453 | ||
1454 | rom_set_fw(fw_cfg); | |
1455 | ||
1456 | if (pcmc->has_reserved_memory && pcms->hotplug_memory.base) { | |
1457 | uint64_t *val = g_malloc(sizeof(*val)); | |
1458 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); | |
1459 | uint64_t res_mem_end = pcms->hotplug_memory.base; | |
1460 | ||
1461 | if (!pcmc->broken_reserved_end) { | |
1462 | res_mem_end += memory_region_size(&pcms->hotplug_memory.mr); | |
1463 | } | |
1464 | *val = cpu_to_le64(ROUND_UP(res_mem_end, 0x1ULL << 30)); | |
1465 | fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); | |
1466 | } | |
1467 | ||
1468 | if (linux_boot) { | |
1469 | load_linux(pcms, fw_cfg); | |
1470 | } | |
1471 | ||
1472 | for (i = 0; i < nb_option_roms; i++) { | |
1473 | rom_add_option(option_rom[i].name, option_rom[i].bootindex); | |
1474 | } | |
1475 | pcms->fw_cfg = fw_cfg; | |
1476 | ||
1477 | /* Init default IOAPIC address space */ | |
1478 | pcms->ioapic_as = &address_space_memory; | |
1479 | } | |
1480 | ||
1481 | qemu_irq pc_allocate_cpu_irq(void) | |
1482 | { | |
1483 | return qemu_allocate_irq(pic_irq_request, NULL, 0); | |
1484 | } | |
1485 | ||
1486 | DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) | |
1487 | { | |
1488 | DeviceState *dev = NULL; | |
1489 | ||
1490 | rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); | |
1491 | if (pci_bus) { | |
1492 | PCIDevice *pcidev = pci_vga_init(pci_bus); | |
1493 | dev = pcidev ? &pcidev->qdev : NULL; | |
1494 | } else if (isa_bus) { | |
1495 | ISADevice *isadev = isa_vga_init(isa_bus); | |
1496 | dev = isadev ? DEVICE(isadev) : NULL; | |
1497 | } | |
1498 | rom_reset_order_override(); | |
1499 | return dev; | |
1500 | } | |
1501 | ||
1502 | static const MemoryRegionOps ioport80_io_ops = { | |
1503 | .write = ioport80_write, | |
1504 | .read = ioport80_read, | |
1505 | .endianness = DEVICE_NATIVE_ENDIAN, | |
1506 | .impl = { | |
1507 | .min_access_size = 1, | |
1508 | .max_access_size = 1, | |
1509 | }, | |
1510 | }; | |
1511 | ||
1512 | static const MemoryRegionOps ioportF0_io_ops = { | |
1513 | .write = ioportF0_write, | |
1514 | .read = ioportF0_read, | |
1515 | .endianness = DEVICE_NATIVE_ENDIAN, | |
1516 | .impl = { | |
1517 | .min_access_size = 1, | |
1518 | .max_access_size = 1, | |
1519 | }, | |
1520 | }; | |
1521 | ||
1522 | void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, | |
1523 | ISADevice **rtc_state, | |
1524 | bool create_fdctrl, | |
1525 | bool no_vmport, | |
1526 | uint32_t hpet_irqs) | |
1527 | { | |
1528 | int i; | |
1529 | DriveInfo *fd[MAX_FD]; | |
1530 | DeviceState *hpet = NULL; | |
1531 | int pit_isa_irq = 0; | |
1532 | qemu_irq pit_alt_irq = NULL; | |
1533 | qemu_irq rtc_irq = NULL; | |
1534 | qemu_irq *a20_line; | |
1535 | ISADevice *i8042, *port92, *vmmouse, *pit = NULL; | |
1536 | MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); | |
1537 | MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); | |
1538 | ||
1539 | memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); | |
1540 | memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); | |
1541 | ||
1542 | memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); | |
1543 | memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); | |
1544 | ||
1545 | /* | |
1546 | * Check if an HPET shall be created. | |
1547 | * | |
1548 | * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT | |
1549 | * when the HPET wants to take over. Thus we have to disable the latter. | |
1550 | */ | |
1551 | if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) { | |
1552 | /* In order to set property, here not using sysbus_try_create_simple */ | |
1553 | hpet = qdev_try_create(NULL, TYPE_HPET); | |
1554 | if (hpet) { | |
1555 | /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 | |
1556 | * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, | |
1557 | * IRQ8 and IRQ2. | |
1558 | */ | |
1559 | uint8_t compat = object_property_get_int(OBJECT(hpet), | |
1560 | HPET_INTCAP, NULL); | |
1561 | if (!compat) { | |
1562 | qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); | |
1563 | } | |
1564 | qdev_init_nofail(hpet); | |
1565 | sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); | |
1566 | ||
1567 | for (i = 0; i < GSI_NUM_PINS; i++) { | |
1568 | sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); | |
1569 | } | |
1570 | pit_isa_irq = -1; | |
1571 | pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); | |
1572 | rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); | |
1573 | } | |
1574 | } | |
1575 | *rtc_state = rtc_init(isa_bus, 2000, rtc_irq); | |
1576 | ||
1577 | qemu_register_boot_set(pc_boot_set, *rtc_state); | |
1578 | ||
1579 | if (!xen_enabled()) { | |
1580 | if (kvm_pit_in_kernel()) { | |
1581 | pit = kvm_pit_init(isa_bus, 0x40); | |
1582 | } else { | |
1583 | pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); | |
1584 | } | |
1585 | if (hpet) { | |
1586 | /* connect PIT to output control line of the HPET */ | |
1587 | qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); | |
1588 | } | |
1589 | pcspk_init(isa_bus, pit); | |
1590 | } | |
1591 | ||
1592 | serial_hds_isa_init(isa_bus, MAX_SERIAL_PORTS); | |
1593 | parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); | |
1594 | ||
1595 | a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); | |
1596 | i8042 = isa_create_simple(isa_bus, "i8042"); | |
1597 | i8042_setup_a20_line(i8042, a20_line[0]); | |
1598 | if (!no_vmport) { | |
1599 | vmport_init(isa_bus); | |
1600 | vmmouse = isa_try_create(isa_bus, "vmmouse"); | |
1601 | } else { | |
1602 | vmmouse = NULL; | |
1603 | } | |
1604 | if (vmmouse) { | |
1605 | DeviceState *dev = DEVICE(vmmouse); | |
1606 | qdev_prop_set_ptr(dev, "ps2_mouse", i8042); | |
1607 | qdev_init_nofail(dev); | |
1608 | } | |
1609 | port92 = isa_create_simple(isa_bus, "port92"); | |
1610 | port92_init(port92, a20_line[1]); | |
1611 | g_free(a20_line); | |
1612 | ||
1613 | DMA_init(isa_bus, 0); | |
1614 | ||
1615 | for(i = 0; i < MAX_FD; i++) { | |
1616 | fd[i] = drive_get(IF_FLOPPY, 0, i); | |
1617 | create_fdctrl |= !!fd[i]; | |
1618 | } | |
1619 | if (create_fdctrl) { | |
1620 | fdctrl_init_isa(isa_bus, fd); | |
1621 | } | |
1622 | } | |
1623 | ||
1624 | void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus) | |
1625 | { | |
1626 | int i; | |
1627 | ||
1628 | rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); | |
1629 | for (i = 0; i < nb_nics; i++) { | |
1630 | NICInfo *nd = &nd_table[i]; | |
1631 | ||
1632 | if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) { | |
1633 | pc_init_ne2k_isa(isa_bus, nd); | |
1634 | } else { | |
1635 | pci_nic_init_nofail(nd, pci_bus, "e1000", NULL); | |
1636 | } | |
1637 | } | |
1638 | rom_reset_order_override(); | |
1639 | } | |
1640 | ||
1641 | void pc_pci_device_init(PCIBus *pci_bus) | |
1642 | { | |
1643 | int max_bus; | |
1644 | int bus; | |
1645 | ||
1646 | max_bus = drive_get_max_bus(IF_SCSI); | |
1647 | for (bus = 0; bus <= max_bus; bus++) { | |
1648 | pci_create_simple(pci_bus, -1, "lsi53c895a"); | |
1649 | } | |
1650 | } | |
1651 | ||
1652 | void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) | |
1653 | { | |
1654 | DeviceState *dev; | |
1655 | SysBusDevice *d; | |
1656 | unsigned int i; | |
1657 | ||
1658 | if (kvm_ioapic_in_kernel()) { | |
1659 | dev = qdev_create(NULL, "kvm-ioapic"); | |
1660 | } else { | |
1661 | dev = qdev_create(NULL, "ioapic"); | |
1662 | } | |
1663 | if (parent_name) { | |
1664 | object_property_add_child(object_resolve_path(parent_name, NULL), | |
1665 | "ioapic", OBJECT(dev), NULL); | |
1666 | } | |
1667 | qdev_init_nofail(dev); | |
1668 | d = SYS_BUS_DEVICE(dev); | |
1669 | sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); | |
1670 | ||
1671 | for (i = 0; i < IOAPIC_NUM_PINS; i++) { | |
1672 | gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); | |
1673 | } | |
1674 | } | |
1675 | ||
1676 | static void pc_dimm_plug(HotplugHandler *hotplug_dev, | |
1677 | DeviceState *dev, Error **errp) | |
1678 | { | |
1679 | HotplugHandlerClass *hhc; | |
1680 | Error *local_err = NULL; | |
1681 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
1682 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); | |
1683 | PCDIMMDevice *dimm = PC_DIMM(dev); | |
1684 | PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); | |
1685 | MemoryRegion *mr = ddc->get_memory_region(dimm); | |
1686 | uint64_t align = TARGET_PAGE_SIZE; | |
1687 | ||
1688 | if (memory_region_get_alignment(mr) && pcmc->enforce_aligned_dimm) { | |
1689 | align = memory_region_get_alignment(mr); | |
1690 | } | |
1691 | ||
1692 | if (!pcms->acpi_dev) { | |
1693 | error_setg(&local_err, | |
1694 | "memory hotplug is not enabled: missing acpi device"); | |
1695 | goto out; | |
1696 | } | |
1697 | ||
1698 | pc_dimm_memory_plug(dev, &pcms->hotplug_memory, mr, align, &local_err); | |
1699 | if (local_err) { | |
1700 | goto out; | |
1701 | } | |
1702 | ||
1703 | hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); | |
1704 | hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort); | |
1705 | out: | |
1706 | error_propagate(errp, local_err); | |
1707 | } | |
1708 | ||
1709 | static void pc_dimm_unplug_request(HotplugHandler *hotplug_dev, | |
1710 | DeviceState *dev, Error **errp) | |
1711 | { | |
1712 | HotplugHandlerClass *hhc; | |
1713 | Error *local_err = NULL; | |
1714 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
1715 | ||
1716 | if (!pcms->acpi_dev) { | |
1717 | error_setg(&local_err, | |
1718 | "memory hotplug is not enabled: missing acpi device"); | |
1719 | goto out; | |
1720 | } | |
1721 | ||
1722 | hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); | |
1723 | hhc->unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); | |
1724 | ||
1725 | out: | |
1726 | error_propagate(errp, local_err); | |
1727 | } | |
1728 | ||
1729 | static void pc_dimm_unplug(HotplugHandler *hotplug_dev, | |
1730 | DeviceState *dev, Error **errp) | |
1731 | { | |
1732 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
1733 | PCDIMMDevice *dimm = PC_DIMM(dev); | |
1734 | PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); | |
1735 | MemoryRegion *mr = ddc->get_memory_region(dimm); | |
1736 | HotplugHandlerClass *hhc; | |
1737 | Error *local_err = NULL; | |
1738 | ||
1739 | hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); | |
1740 | hhc->unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); | |
1741 | ||
1742 | if (local_err) { | |
1743 | goto out; | |
1744 | } | |
1745 | ||
1746 | pc_dimm_memory_unplug(dev, &pcms->hotplug_memory, mr); | |
1747 | object_unparent(OBJECT(dev)); | |
1748 | ||
1749 | out: | |
1750 | error_propagate(errp, local_err); | |
1751 | } | |
1752 | ||
1753 | static int pc_apic_cmp(const void *a, const void *b) | |
1754 | { | |
1755 | CPUArchId *apic_a = (CPUArchId *)a; | |
1756 | CPUArchId *apic_b = (CPUArchId *)b; | |
1757 | ||
1758 | return apic_a->arch_id - apic_b->arch_id; | |
1759 | } | |
1760 | ||
1761 | /* returns pointer to CPUArchId descriptor that matches CPU's apic_id | |
1762 | * in pcms->possible_cpus->cpus, if pcms->possible_cpus->cpus has no | |
1763 | * entry correponding to CPU's apic_id returns NULL. | |
1764 | */ | |
1765 | static CPUArchId *pc_find_cpu_slot(PCMachineState *pcms, CPUState *cpu, | |
1766 | int *idx) | |
1767 | { | |
1768 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
1769 | CPUArchId apic_id, *found_cpu; | |
1770 | ||
1771 | apic_id.arch_id = cc->get_arch_id(CPU(cpu)); | |
1772 | found_cpu = bsearch(&apic_id, pcms->possible_cpus->cpus, | |
1773 | pcms->possible_cpus->len, sizeof(*pcms->possible_cpus->cpus), | |
1774 | pc_apic_cmp); | |
1775 | if (found_cpu && idx) { | |
1776 | *idx = found_cpu - pcms->possible_cpus->cpus; | |
1777 | } | |
1778 | return found_cpu; | |
1779 | } | |
1780 | ||
1781 | static void pc_cpu_plug(HotplugHandler *hotplug_dev, | |
1782 | DeviceState *dev, Error **errp) | |
1783 | { | |
1784 | CPUArchId *found_cpu; | |
1785 | HotplugHandlerClass *hhc; | |
1786 | Error *local_err = NULL; | |
1787 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
1788 | ||
1789 | if (pcms->acpi_dev) { | |
1790 | hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); | |
1791 | hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); | |
1792 | if (local_err) { | |
1793 | goto out; | |
1794 | } | |
1795 | } | |
1796 | ||
1797 | if (dev->hotplugged) { | |
1798 | /* increment the number of CPUs */ | |
1799 | rtc_set_memory(pcms->rtc, 0x5f, rtc_get_memory(pcms->rtc, 0x5f) + 1); | |
1800 | } | |
1801 | ||
1802 | found_cpu = pc_find_cpu_slot(pcms, CPU(dev), NULL); | |
1803 | found_cpu->cpu = CPU(dev); | |
1804 | out: | |
1805 | error_propagate(errp, local_err); | |
1806 | } | |
1807 | static void pc_cpu_unplug_request_cb(HotplugHandler *hotplug_dev, | |
1808 | DeviceState *dev, Error **errp) | |
1809 | { | |
1810 | int idx = -1; | |
1811 | HotplugHandlerClass *hhc; | |
1812 | Error *local_err = NULL; | |
1813 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
1814 | ||
1815 | pc_find_cpu_slot(pcms, CPU(dev), &idx); | |
1816 | assert(idx != -1); | |
1817 | if (idx == 0) { | |
1818 | error_setg(&local_err, "Boot CPU is unpluggable"); | |
1819 | goto out; | |
1820 | } | |
1821 | ||
1822 | hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); | |
1823 | hhc->unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); | |
1824 | ||
1825 | if (local_err) { | |
1826 | goto out; | |
1827 | } | |
1828 | ||
1829 | out: | |
1830 | error_propagate(errp, local_err); | |
1831 | ||
1832 | } | |
1833 | ||
1834 | static void pc_cpu_unplug_cb(HotplugHandler *hotplug_dev, | |
1835 | DeviceState *dev, Error **errp) | |
1836 | { | |
1837 | CPUArchId *found_cpu; | |
1838 | HotplugHandlerClass *hhc; | |
1839 | Error *local_err = NULL; | |
1840 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
1841 | ||
1842 | hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); | |
1843 | hhc->unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); | |
1844 | ||
1845 | if (local_err) { | |
1846 | goto out; | |
1847 | } | |
1848 | ||
1849 | found_cpu = pc_find_cpu_slot(pcms, CPU(dev), NULL); | |
1850 | found_cpu->cpu = NULL; | |
1851 | object_unparent(OBJECT(dev)); | |
1852 | ||
1853 | rtc_set_memory(pcms->rtc, 0x5f, rtc_get_memory(pcms->rtc, 0x5f) - 1); | |
1854 | out: | |
1855 | error_propagate(errp, local_err); | |
1856 | } | |
1857 | ||
1858 | static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, | |
1859 | DeviceState *dev, Error **errp) | |
1860 | { | |
1861 | int idx; | |
1862 | CPUState *cs; | |
1863 | CPUArchId *cpu_slot; | |
1864 | X86CPUTopoInfo topo; | |
1865 | X86CPU *cpu = X86_CPU(dev); | |
1866 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
1867 | ||
1868 | /* if APIC ID is not set, set it based on socket/core/thread properties */ | |
1869 | if (cpu->apic_id == UNASSIGNED_APIC_ID) { | |
1870 | int max_socket = (max_cpus - 1) / smp_threads / smp_cores; | |
1871 | ||
1872 | if (cpu->socket_id < 0) { | |
1873 | error_setg(errp, "CPU socket-id is not set"); | |
1874 | return; | |
1875 | } else if (cpu->socket_id > max_socket) { | |
1876 | error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u", | |
1877 | cpu->socket_id, max_socket); | |
1878 | return; | |
1879 | } | |
1880 | if (cpu->core_id < 0) { | |
1881 | error_setg(errp, "CPU core-id is not set"); | |
1882 | return; | |
1883 | } else if (cpu->core_id > (smp_cores - 1)) { | |
1884 | error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u", | |
1885 | cpu->core_id, smp_cores - 1); | |
1886 | return; | |
1887 | } | |
1888 | if (cpu->thread_id < 0) { | |
1889 | error_setg(errp, "CPU thread-id is not set"); | |
1890 | return; | |
1891 | } else if (cpu->thread_id > (smp_threads - 1)) { | |
1892 | error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u", | |
1893 | cpu->thread_id, smp_threads - 1); | |
1894 | return; | |
1895 | } | |
1896 | ||
1897 | topo.pkg_id = cpu->socket_id; | |
1898 | topo.core_id = cpu->core_id; | |
1899 | topo.smt_id = cpu->thread_id; | |
1900 | cpu->apic_id = apicid_from_topo_ids(smp_cores, smp_threads, &topo); | |
1901 | } | |
1902 | ||
1903 | cpu_slot = pc_find_cpu_slot(pcms, CPU(dev), &idx); | |
1904 | if (!cpu_slot) { | |
1905 | x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo); | |
1906 | error_setg(errp, "Invalid CPU [socket: %u, core: %u, thread: %u] with" | |
1907 | " APIC ID %" PRIu32 ", valid index range 0:%d", | |
1908 | topo.pkg_id, topo.core_id, topo.smt_id, cpu->apic_id, | |
1909 | pcms->possible_cpus->len - 1); | |
1910 | return; | |
1911 | } | |
1912 | ||
1913 | if (cpu_slot->cpu) { | |
1914 | error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists", | |
1915 | idx, cpu->apic_id); | |
1916 | return; | |
1917 | } | |
1918 | ||
1919 | /* if 'address' properties socket-id/core-id/thread-id are not set, set them | |
1920 | * so that query_hotpluggable_cpus would show correct values | |
1921 | */ | |
1922 | /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn() | |
1923 | * once -smp refactoring is complete and there will be CPU private | |
1924 | * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */ | |
1925 | x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo); | |
1926 | if (cpu->socket_id != -1 && cpu->socket_id != topo.pkg_id) { | |
1927 | error_setg(errp, "property socket-id: %u doesn't match set apic-id:" | |
1928 | " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo.pkg_id); | |
1929 | return; | |
1930 | } | |
1931 | cpu->socket_id = topo.pkg_id; | |
1932 | ||
1933 | if (cpu->core_id != -1 && cpu->core_id != topo.core_id) { | |
1934 | error_setg(errp, "property core-id: %u doesn't match set apic-id:" | |
1935 | " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo.core_id); | |
1936 | return; | |
1937 | } | |
1938 | cpu->core_id = topo.core_id; | |
1939 | ||
1940 | if (cpu->thread_id != -1 && cpu->thread_id != topo.smt_id) { | |
1941 | error_setg(errp, "property thread-id: %u doesn't match set apic-id:" | |
1942 | " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, topo.smt_id); | |
1943 | return; | |
1944 | } | |
1945 | cpu->thread_id = topo.smt_id; | |
1946 | ||
1947 | cs = CPU(cpu); | |
1948 | cs->cpu_index = idx; | |
1949 | } | |
1950 | ||
1951 | static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, | |
1952 | DeviceState *dev, Error **errp) | |
1953 | { | |
1954 | if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { | |
1955 | pc_cpu_pre_plug(hotplug_dev, dev, errp); | |
1956 | } | |
1957 | } | |
1958 | ||
1959 | static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, | |
1960 | DeviceState *dev, Error **errp) | |
1961 | { | |
1962 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { | |
1963 | pc_dimm_plug(hotplug_dev, dev, errp); | |
1964 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { | |
1965 | pc_cpu_plug(hotplug_dev, dev, errp); | |
1966 | } | |
1967 | } | |
1968 | ||
1969 | static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, | |
1970 | DeviceState *dev, Error **errp) | |
1971 | { | |
1972 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { | |
1973 | pc_dimm_unplug_request(hotplug_dev, dev, errp); | |
1974 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { | |
1975 | pc_cpu_unplug_request_cb(hotplug_dev, dev, errp); | |
1976 | } else { | |
1977 | error_setg(errp, "acpi: device unplug request for not supported device" | |
1978 | " type: %s", object_get_typename(OBJECT(dev))); | |
1979 | } | |
1980 | } | |
1981 | ||
1982 | static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, | |
1983 | DeviceState *dev, Error **errp) | |
1984 | { | |
1985 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { | |
1986 | pc_dimm_unplug(hotplug_dev, dev, errp); | |
1987 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { | |
1988 | pc_cpu_unplug_cb(hotplug_dev, dev, errp); | |
1989 | } else { | |
1990 | error_setg(errp, "acpi: device unplug for not supported device" | |
1991 | " type: %s", object_get_typename(OBJECT(dev))); | |
1992 | } | |
1993 | } | |
1994 | ||
1995 | static HotplugHandler *pc_get_hotpug_handler(MachineState *machine, | |
1996 | DeviceState *dev) | |
1997 | { | |
1998 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); | |
1999 | ||
2000 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || | |
2001 | object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { | |
2002 | return HOTPLUG_HANDLER(machine); | |
2003 | } | |
2004 | ||
2005 | return pcmc->get_hotplug_handler ? | |
2006 | pcmc->get_hotplug_handler(machine, dev) : NULL; | |
2007 | } | |
2008 | ||
2009 | static void | |
2010 | pc_machine_get_hotplug_memory_region_size(Object *obj, Visitor *v, | |
2011 | const char *name, void *opaque, | |
2012 | Error **errp) | |
2013 | { | |
2014 | PCMachineState *pcms = PC_MACHINE(obj); | |
2015 | int64_t value = memory_region_size(&pcms->hotplug_memory.mr); | |
2016 | ||
2017 | visit_type_int(v, name, &value, errp); | |
2018 | } | |
2019 | ||
2020 | static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, | |
2021 | const char *name, void *opaque, | |
2022 | Error **errp) | |
2023 | { | |
2024 | PCMachineState *pcms = PC_MACHINE(obj); | |
2025 | uint64_t value = pcms->max_ram_below_4g; | |
2026 | ||
2027 | visit_type_size(v, name, &value, errp); | |
2028 | } | |
2029 | ||
2030 | static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, | |
2031 | const char *name, void *opaque, | |
2032 | Error **errp) | |
2033 | { | |
2034 | PCMachineState *pcms = PC_MACHINE(obj); | |
2035 | Error *error = NULL; | |
2036 | uint64_t value; | |
2037 | ||
2038 | visit_type_size(v, name, &value, &error); | |
2039 | if (error) { | |
2040 | error_propagate(errp, error); | |
2041 | return; | |
2042 | } | |
2043 | if (value > (1ULL << 32)) { | |
2044 | error_setg(&error, | |
2045 | "Machine option 'max-ram-below-4g=%"PRIu64 | |
2046 | "' expects size less than or equal to 4G", value); | |
2047 | error_propagate(errp, error); | |
2048 | return; | |
2049 | } | |
2050 | ||
2051 | if (value < (1ULL << 20)) { | |
2052 | error_report("Warning: small max_ram_below_4g(%"PRIu64 | |
2053 | ") less than 1M. BIOS may not work..", | |
2054 | value); | |
2055 | } | |
2056 | ||
2057 | pcms->max_ram_below_4g = value; | |
2058 | } | |
2059 | ||
2060 | static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, | |
2061 | void *opaque, Error **errp) | |
2062 | { | |
2063 | PCMachineState *pcms = PC_MACHINE(obj); | |
2064 | OnOffAuto vmport = pcms->vmport; | |
2065 | ||
2066 | visit_type_OnOffAuto(v, name, &vmport, errp); | |
2067 | } | |
2068 | ||
2069 | static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, | |
2070 | void *opaque, Error **errp) | |
2071 | { | |
2072 | PCMachineState *pcms = PC_MACHINE(obj); | |
2073 | ||
2074 | visit_type_OnOffAuto(v, name, &pcms->vmport, errp); | |
2075 | } | |
2076 | ||
2077 | bool pc_machine_is_smm_enabled(PCMachineState *pcms) | |
2078 | { | |
2079 | bool smm_available = false; | |
2080 | ||
2081 | if (pcms->smm == ON_OFF_AUTO_OFF) { | |
2082 | return false; | |
2083 | } | |
2084 | ||
2085 | if (tcg_enabled() || qtest_enabled()) { | |
2086 | smm_available = true; | |
2087 | } else if (kvm_enabled()) { | |
2088 | smm_available = kvm_has_smm(); | |
2089 | } | |
2090 | ||
2091 | if (smm_available) { | |
2092 | return true; | |
2093 | } | |
2094 | ||
2095 | if (pcms->smm == ON_OFF_AUTO_ON) { | |
2096 | error_report("System Management Mode not supported by this hypervisor."); | |
2097 | exit(1); | |
2098 | } | |
2099 | return false; | |
2100 | } | |
2101 | ||
2102 | static void pc_machine_get_smm(Object *obj, Visitor *v, const char *name, | |
2103 | void *opaque, Error **errp) | |
2104 | { | |
2105 | PCMachineState *pcms = PC_MACHINE(obj); | |
2106 | OnOffAuto smm = pcms->smm; | |
2107 | ||
2108 | visit_type_OnOffAuto(v, name, &smm, errp); | |
2109 | } | |
2110 | ||
2111 | static void pc_machine_set_smm(Object *obj, Visitor *v, const char *name, | |
2112 | void *opaque, Error **errp) | |
2113 | { | |
2114 | PCMachineState *pcms = PC_MACHINE(obj); | |
2115 | ||
2116 | visit_type_OnOffAuto(v, name, &pcms->smm, errp); | |
2117 | } | |
2118 | ||
2119 | static bool pc_machine_get_nvdimm(Object *obj, Error **errp) | |
2120 | { | |
2121 | PCMachineState *pcms = PC_MACHINE(obj); | |
2122 | ||
2123 | return pcms->acpi_nvdimm_state.is_enabled; | |
2124 | } | |
2125 | ||
2126 | static void pc_machine_set_nvdimm(Object *obj, bool value, Error **errp) | |
2127 | { | |
2128 | PCMachineState *pcms = PC_MACHINE(obj); | |
2129 | ||
2130 | pcms->acpi_nvdimm_state.is_enabled = value; | |
2131 | } | |
2132 | ||
2133 | static void pc_machine_initfn(Object *obj) | |
2134 | { | |
2135 | PCMachineState *pcms = PC_MACHINE(obj); | |
2136 | ||
2137 | object_property_add(obj, PC_MACHINE_MEMHP_REGION_SIZE, "int", | |
2138 | pc_machine_get_hotplug_memory_region_size, | |
2139 | NULL, NULL, NULL, &error_abort); | |
2140 | ||
2141 | pcms->max_ram_below_4g = 0; /* use default */ | |
2142 | object_property_add(obj, PC_MACHINE_MAX_RAM_BELOW_4G, "size", | |
2143 | pc_machine_get_max_ram_below_4g, | |
2144 | pc_machine_set_max_ram_below_4g, | |
2145 | NULL, NULL, &error_abort); | |
2146 | object_property_set_description(obj, PC_MACHINE_MAX_RAM_BELOW_4G, | |
2147 | "Maximum ram below the 4G boundary (32bit boundary)", | |
2148 | &error_abort); | |
2149 | ||
2150 | pcms->smm = ON_OFF_AUTO_AUTO; | |
2151 | object_property_add(obj, PC_MACHINE_SMM, "OnOffAuto", | |
2152 | pc_machine_get_smm, | |
2153 | pc_machine_set_smm, | |
2154 | NULL, NULL, &error_abort); | |
2155 | object_property_set_description(obj, PC_MACHINE_SMM, | |
2156 | "Enable SMM (pc & q35)", | |
2157 | &error_abort); | |
2158 | ||
2159 | pcms->vmport = ON_OFF_AUTO_AUTO; | |
2160 | object_property_add(obj, PC_MACHINE_VMPORT, "OnOffAuto", | |
2161 | pc_machine_get_vmport, | |
2162 | pc_machine_set_vmport, | |
2163 | NULL, NULL, &error_abort); | |
2164 | object_property_set_description(obj, PC_MACHINE_VMPORT, | |
2165 | "Enable vmport (pc & q35)", | |
2166 | &error_abort); | |
2167 | ||
2168 | /* nvdimm is disabled on default. */ | |
2169 | pcms->acpi_nvdimm_state.is_enabled = false; | |
2170 | object_property_add_bool(obj, PC_MACHINE_NVDIMM, pc_machine_get_nvdimm, | |
2171 | pc_machine_set_nvdimm, &error_abort); | |
2172 | } | |
2173 | ||
2174 | static void pc_machine_reset(void) | |
2175 | { | |
2176 | CPUState *cs; | |
2177 | X86CPU *cpu; | |
2178 | ||
2179 | qemu_devices_reset(); | |
2180 | ||
2181 | /* Reset APIC after devices have been reset to cancel | |
2182 | * any changes that qemu_devices_reset() might have done. | |
2183 | */ | |
2184 | CPU_FOREACH(cs) { | |
2185 | cpu = X86_CPU(cs); | |
2186 | ||
2187 | if (cpu->apic_state) { | |
2188 | device_reset(cpu->apic_state); | |
2189 | } | |
2190 | } | |
2191 | } | |
2192 | ||
2193 | static unsigned pc_cpu_index_to_socket_id(unsigned cpu_index) | |
2194 | { | |
2195 | X86CPUTopoInfo topo; | |
2196 | x86_topo_ids_from_idx(smp_cores, smp_threads, cpu_index, | |
2197 | &topo); | |
2198 | return topo.pkg_id; | |
2199 | } | |
2200 | ||
2201 | static CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *machine) | |
2202 | { | |
2203 | PCMachineState *pcms = PC_MACHINE(machine); | |
2204 | int len = sizeof(CPUArchIdList) + | |
2205 | sizeof(CPUArchId) * (pcms->possible_cpus->len); | |
2206 | CPUArchIdList *list = g_malloc(len); | |
2207 | ||
2208 | memcpy(list, pcms->possible_cpus, len); | |
2209 | return list; | |
2210 | } | |
2211 | ||
2212 | static HotpluggableCPUList *pc_query_hotpluggable_cpus(MachineState *machine) | |
2213 | { | |
2214 | int i; | |
2215 | CPUState *cpu; | |
2216 | HotpluggableCPUList *head = NULL; | |
2217 | PCMachineState *pcms = PC_MACHINE(machine); | |
2218 | const char *cpu_type; | |
2219 | ||
2220 | cpu = pcms->possible_cpus->cpus[0].cpu; | |
2221 | assert(cpu); /* BSP is always present */ | |
2222 | cpu_type = object_class_get_name(OBJECT_CLASS(CPU_GET_CLASS(cpu))); | |
2223 | ||
2224 | for (i = 0; i < pcms->possible_cpus->len; i++) { | |
2225 | X86CPUTopoInfo topo; | |
2226 | HotpluggableCPUList *list_item = g_new0(typeof(*list_item), 1); | |
2227 | HotpluggableCPU *cpu_item = g_new0(typeof(*cpu_item), 1); | |
2228 | CpuInstanceProperties *cpu_props = g_new0(typeof(*cpu_props), 1); | |
2229 | const uint32_t apic_id = pcms->possible_cpus->cpus[i].arch_id; | |
2230 | ||
2231 | x86_topo_ids_from_apicid(apic_id, smp_cores, smp_threads, &topo); | |
2232 | ||
2233 | cpu_item->type = g_strdup(cpu_type); | |
2234 | cpu_item->vcpus_count = 1; | |
2235 | cpu_props->has_socket_id = true; | |
2236 | cpu_props->socket_id = topo.pkg_id; | |
2237 | cpu_props->has_core_id = true; | |
2238 | cpu_props->core_id = topo.core_id; | |
2239 | cpu_props->has_thread_id = true; | |
2240 | cpu_props->thread_id = topo.smt_id; | |
2241 | cpu_item->props = cpu_props; | |
2242 | ||
2243 | cpu = pcms->possible_cpus->cpus[i].cpu; | |
2244 | if (cpu) { | |
2245 | cpu_item->has_qom_path = true; | |
2246 | cpu_item->qom_path = object_get_canonical_path(OBJECT(cpu)); | |
2247 | } | |
2248 | ||
2249 | list_item->value = cpu_item; | |
2250 | list_item->next = head; | |
2251 | head = list_item; | |
2252 | } | |
2253 | return head; | |
2254 | } | |
2255 | ||
2256 | static void x86_nmi(NMIState *n, int cpu_index, Error **errp) | |
2257 | { | |
2258 | /* cpu index isn't used */ | |
2259 | CPUState *cs; | |
2260 | ||
2261 | CPU_FOREACH(cs) { | |
2262 | X86CPU *cpu = X86_CPU(cs); | |
2263 | ||
2264 | if (!cpu->apic_state) { | |
2265 | cpu_interrupt(cs, CPU_INTERRUPT_NMI); | |
2266 | } else { | |
2267 | apic_deliver_nmi(cpu->apic_state); | |
2268 | } | |
2269 | } | |
2270 | } | |
2271 | ||
2272 | static void pc_machine_class_init(ObjectClass *oc, void *data) | |
2273 | { | |
2274 | MachineClass *mc = MACHINE_CLASS(oc); | |
2275 | PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); | |
2276 | HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); | |
2277 | NMIClass *nc = NMI_CLASS(oc); | |
2278 | ||
2279 | pcmc->get_hotplug_handler = mc->get_hotplug_handler; | |
2280 | pcmc->pci_enabled = true; | |
2281 | pcmc->has_acpi_build = true; | |
2282 | pcmc->rsdp_in_ram = true; | |
2283 | pcmc->smbios_defaults = true; | |
2284 | pcmc->smbios_uuid_encoded = true; | |
2285 | pcmc->gigabyte_align = true; | |
2286 | pcmc->has_reserved_memory = true; | |
2287 | pcmc->kvmclock_enabled = true; | |
2288 | pcmc->enforce_aligned_dimm = true; | |
2289 | /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported | |
2290 | * to be used at the moment, 32K should be enough for a while. */ | |
2291 | pcmc->acpi_data_size = 0x20000 + 0x8000; | |
2292 | pcmc->save_tsc_khz = true; | |
2293 | mc->get_hotplug_handler = pc_get_hotpug_handler; | |
2294 | mc->cpu_index_to_socket_id = pc_cpu_index_to_socket_id; | |
2295 | mc->possible_cpu_arch_ids = pc_possible_cpu_arch_ids; | |
2296 | mc->query_hotpluggable_cpus = pc_query_hotpluggable_cpus; | |
2297 | mc->default_boot_order = "cad"; | |
2298 | mc->hot_add_cpu = pc_hot_add_cpu; | |
2299 | mc->max_cpus = 255; | |
2300 | mc->reset = pc_machine_reset; | |
2301 | hc->pre_plug = pc_machine_device_pre_plug_cb; | |
2302 | hc->plug = pc_machine_device_plug_cb; | |
2303 | hc->unplug_request = pc_machine_device_unplug_request_cb; | |
2304 | hc->unplug = pc_machine_device_unplug_cb; | |
2305 | nc->nmi_monitor_handler = x86_nmi; | |
2306 | } | |
2307 | ||
2308 | static const TypeInfo pc_machine_info = { | |
2309 | .name = TYPE_PC_MACHINE, | |
2310 | .parent = TYPE_MACHINE, | |
2311 | .abstract = true, | |
2312 | .instance_size = sizeof(PCMachineState), | |
2313 | .instance_init = pc_machine_initfn, | |
2314 | .class_size = sizeof(PCMachineClass), | |
2315 | .class_init = pc_machine_class_init, | |
2316 | .interfaces = (InterfaceInfo[]) { | |
2317 | { TYPE_HOTPLUG_HANDLER }, | |
2318 | { TYPE_NMI }, | |
2319 | { } | |
2320 | }, | |
2321 | }; | |
2322 | ||
2323 | static void pc_machine_register_types(void) | |
2324 | { | |
2325 | type_register_static(&pc_machine_info); | |
2326 | } | |
2327 | ||
2328 | type_init(pc_machine_register_types) |