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1 | /* | |
2 | * QEMU PC System Emulator | |
3 | * | |
4 | * Copyright (c) 2003-2004 Fabrice Bellard | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
25 | #include "qemu/osdep.h" | |
26 | #include "qemu/units.h" | |
27 | #include "hw/i386/pc.h" | |
28 | #include "hw/char/serial.h" | |
29 | #include "hw/char/parallel.h" | |
30 | #include "hw/i386/apic.h" | |
31 | #include "hw/i386/topology.h" | |
32 | #include "hw/i386/fw_cfg.h" | |
33 | #include "sysemu/cpus.h" | |
34 | #include "hw/block/fdc.h" | |
35 | #include "hw/ide.h" | |
36 | #include "hw/pci/pci.h" | |
37 | #include "hw/pci/pci_bus.h" | |
38 | #include "hw/nvram/fw_cfg.h" | |
39 | #include "hw/timer/hpet.h" | |
40 | #include "hw/firmware/smbios.h" | |
41 | #include "hw/loader.h" | |
42 | #include "elf.h" | |
43 | #include "migration/vmstate.h" | |
44 | #include "multiboot.h" | |
45 | #include "hw/timer/mc146818rtc.h" | |
46 | #include "hw/dma/i8257.h" | |
47 | #include "hw/timer/i8254.h" | |
48 | #include "hw/input/i8042.h" | |
49 | #include "hw/irq.h" | |
50 | #include "hw/audio/pcspk.h" | |
51 | #include "hw/pci/msi.h" | |
52 | #include "hw/sysbus.h" | |
53 | #include "sysemu/sysemu.h" | |
54 | #include "sysemu/tcg.h" | |
55 | #include "sysemu/numa.h" | |
56 | #include "sysemu/kvm.h" | |
57 | #include "sysemu/qtest.h" | |
58 | #include "sysemu/reset.h" | |
59 | #include "sysemu/runstate.h" | |
60 | #include "kvm_i386.h" | |
61 | #include "hw/xen/xen.h" | |
62 | #include "hw/xen/start_info.h" | |
63 | #include "ui/qemu-spice.h" | |
64 | #include "exec/memory.h" | |
65 | #include "exec/address-spaces.h" | |
66 | #include "sysemu/arch_init.h" | |
67 | #include "qemu/bitmap.h" | |
68 | #include "qemu/config-file.h" | |
69 | #include "qemu/error-report.h" | |
70 | #include "qemu/option.h" | |
71 | #include "hw/acpi/acpi.h" | |
72 | #include "hw/acpi/cpu_hotplug.h" | |
73 | #include "hw/boards.h" | |
74 | #include "acpi-build.h" | |
75 | #include "hw/mem/pc-dimm.h" | |
76 | #include "qapi/error.h" | |
77 | #include "qapi/qapi-visit-common.h" | |
78 | #include "qapi/visitor.h" | |
79 | #include "hw/core/cpu.h" | |
80 | #include "hw/nmi.h" | |
81 | #include "hw/usb.h" | |
82 | #include "hw/i386/intel_iommu.h" | |
83 | #include "hw/net/ne2000-isa.h" | |
84 | #include "standard-headers/asm-x86/bootparam.h" | |
85 | #include "hw/virtio/virtio-pmem-pci.h" | |
86 | #include "hw/mem/memory-device.h" | |
87 | #include "sysemu/replay.h" | |
88 | #include "qapi/qmp/qerror.h" | |
89 | #include "config-devices.h" | |
90 | #include "e820_memory_layout.h" | |
91 | #include "fw_cfg.h" | |
92 | ||
93 | /* debug PC/ISA interrupts */ | |
94 | //#define DEBUG_IRQ | |
95 | ||
96 | #ifdef DEBUG_IRQ | |
97 | #define DPRINTF(fmt, ...) \ | |
98 | do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) | |
99 | #else | |
100 | #define DPRINTF(fmt, ...) | |
101 | #endif | |
102 | ||
103 | struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; | |
104 | ||
105 | /* Physical Address of PVH entry point read from kernel ELF NOTE */ | |
106 | static size_t pvh_start_addr; | |
107 | ||
108 | GlobalProperty pc_compat_4_1[] = {}; | |
109 | const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1); | |
110 | ||
111 | GlobalProperty pc_compat_4_0[] = {}; | |
112 | const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); | |
113 | ||
114 | GlobalProperty pc_compat_3_1[] = { | |
115 | { "intel-iommu", "dma-drain", "off" }, | |
116 | { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, | |
117 | { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, | |
118 | { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, | |
119 | { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, | |
120 | { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, | |
121 | { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, | |
122 | { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, | |
123 | { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, | |
124 | { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, | |
125 | { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, | |
126 | { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, | |
127 | { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, | |
128 | { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, | |
129 | { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, | |
130 | { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, | |
131 | { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, | |
132 | { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, | |
133 | { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, | |
134 | { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, | |
135 | { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, | |
136 | }; | |
137 | const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); | |
138 | ||
139 | GlobalProperty pc_compat_3_0[] = { | |
140 | { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, | |
141 | { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, | |
142 | { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, | |
143 | }; | |
144 | const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); | |
145 | ||
146 | GlobalProperty pc_compat_2_12[] = { | |
147 | { TYPE_X86_CPU, "legacy-cache", "on" }, | |
148 | { TYPE_X86_CPU, "topoext", "off" }, | |
149 | { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, | |
150 | { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, | |
151 | }; | |
152 | const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); | |
153 | ||
154 | GlobalProperty pc_compat_2_11[] = { | |
155 | { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, | |
156 | { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, | |
157 | }; | |
158 | const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); | |
159 | ||
160 | GlobalProperty pc_compat_2_10[] = { | |
161 | { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, | |
162 | { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, | |
163 | { "q35-pcihost", "x-pci-hole64-fix", "off" }, | |
164 | }; | |
165 | const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); | |
166 | ||
167 | GlobalProperty pc_compat_2_9[] = { | |
168 | { "mch", "extended-tseg-mbytes", "0" }, | |
169 | }; | |
170 | const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); | |
171 | ||
172 | GlobalProperty pc_compat_2_8[] = { | |
173 | { TYPE_X86_CPU, "tcg-cpuid", "off" }, | |
174 | { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, | |
175 | { "ICH9-LPC", "x-smi-broadcast", "off" }, | |
176 | { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, | |
177 | { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, | |
178 | }; | |
179 | const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); | |
180 | ||
181 | GlobalProperty pc_compat_2_7[] = { | |
182 | { TYPE_X86_CPU, "l3-cache", "off" }, | |
183 | { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, | |
184 | { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, | |
185 | { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, | |
186 | { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, | |
187 | { "isa-pcspk", "migrate", "off" }, | |
188 | }; | |
189 | const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); | |
190 | ||
191 | GlobalProperty pc_compat_2_6[] = { | |
192 | { TYPE_X86_CPU, "cpuid-0xb", "off" }, | |
193 | { "vmxnet3", "romfile", "" }, | |
194 | { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, | |
195 | { "apic-common", "legacy-instance-id", "on", } | |
196 | }; | |
197 | const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); | |
198 | ||
199 | GlobalProperty pc_compat_2_5[] = {}; | |
200 | const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5); | |
201 | ||
202 | GlobalProperty pc_compat_2_4[] = { | |
203 | PC_CPU_MODEL_IDS("2.4.0") | |
204 | { "Haswell-" TYPE_X86_CPU, "abm", "off" }, | |
205 | { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" }, | |
206 | { "Broadwell-" TYPE_X86_CPU, "abm", "off" }, | |
207 | { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" }, | |
208 | { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" }, | |
209 | { TYPE_X86_CPU, "check", "off" }, | |
210 | { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" }, | |
211 | { "qemu64" "-" TYPE_X86_CPU, "abm", "on" }, | |
212 | { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" }, | |
213 | { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" }, | |
214 | { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" }, | |
215 | { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" }, | |
216 | { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" }, | |
217 | { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", } | |
218 | }; | |
219 | const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4); | |
220 | ||
221 | GlobalProperty pc_compat_2_3[] = { | |
222 | PC_CPU_MODEL_IDS("2.3.0") | |
223 | { TYPE_X86_CPU, "arat", "off" }, | |
224 | { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" }, | |
225 | { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" }, | |
226 | { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" }, | |
227 | { "n270" "-" TYPE_X86_CPU, "min-level", "5" }, | |
228 | { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" }, | |
229 | { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" }, | |
230 | { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" }, | |
231 | { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
232 | { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
233 | { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
234 | { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
235 | { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
236 | { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
237 | { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
238 | { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
239 | { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
240 | { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
241 | { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
242 | { TYPE_X86_CPU, "kvm-no-smi-migration", "on" }, | |
243 | }; | |
244 | const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3); | |
245 | ||
246 | GlobalProperty pc_compat_2_2[] = { | |
247 | PC_CPU_MODEL_IDS("2.2.0") | |
248 | { "kvm64" "-" TYPE_X86_CPU, "vme", "off" }, | |
249 | { "kvm32" "-" TYPE_X86_CPU, "vme", "off" }, | |
250 | { "Conroe" "-" TYPE_X86_CPU, "vme", "off" }, | |
251 | { "Penryn" "-" TYPE_X86_CPU, "vme", "off" }, | |
252 | { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" }, | |
253 | { "Westmere" "-" TYPE_X86_CPU, "vme", "off" }, | |
254 | { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" }, | |
255 | { "Haswell" "-" TYPE_X86_CPU, "vme", "off" }, | |
256 | { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" }, | |
257 | { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" }, | |
258 | { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" }, | |
259 | { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" }, | |
260 | { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" }, | |
261 | { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" }, | |
262 | { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" }, | |
263 | { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" }, | |
264 | { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" }, | |
265 | { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" }, | |
266 | }; | |
267 | const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2); | |
268 | ||
269 | GlobalProperty pc_compat_2_1[] = { | |
270 | PC_CPU_MODEL_IDS("2.1.0") | |
271 | { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" }, | |
272 | { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" }, | |
273 | }; | |
274 | const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1); | |
275 | ||
276 | GlobalProperty pc_compat_2_0[] = { | |
277 | PC_CPU_MODEL_IDS("2.0.0") | |
278 | { "virtio-scsi-pci", "any_layout", "off" }, | |
279 | { "PIIX4_PM", "memory-hotplug-support", "off" }, | |
280 | { "apic", "version", "0x11" }, | |
281 | { "nec-usb-xhci", "superspeed-ports-first", "off" }, | |
282 | { "nec-usb-xhci", "force-pcie-endcap", "on" }, | |
283 | { "pci-serial", "prog_if", "0" }, | |
284 | { "pci-serial-2x", "prog_if", "0" }, | |
285 | { "pci-serial-4x", "prog_if", "0" }, | |
286 | { "virtio-net-pci", "guest_announce", "off" }, | |
287 | { "ICH9-LPC", "memory-hotplug-support", "off" }, | |
288 | { "xio3130-downstream", COMPAT_PROP_PCP, "off" }, | |
289 | { "ioh3420", COMPAT_PROP_PCP, "off" }, | |
290 | }; | |
291 | const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0); | |
292 | ||
293 | GlobalProperty pc_compat_1_7[] = { | |
294 | PC_CPU_MODEL_IDS("1.7.0") | |
295 | { TYPE_USB_DEVICE, "msos-desc", "no" }, | |
296 | { "PIIX4_PM", "acpi-pci-hotplug-with-bridge-support", "off" }, | |
297 | { "hpet", HPET_INTCAP, "4" }, | |
298 | }; | |
299 | const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7); | |
300 | ||
301 | GlobalProperty pc_compat_1_6[] = { | |
302 | PC_CPU_MODEL_IDS("1.6.0") | |
303 | { "e1000", "mitigation", "off" }, | |
304 | { "qemu64-" TYPE_X86_CPU, "model", "2" }, | |
305 | { "qemu32-" TYPE_X86_CPU, "model", "3" }, | |
306 | { "i440FX-pcihost", "short_root_bus", "1" }, | |
307 | { "q35-pcihost", "short_root_bus", "1" }, | |
308 | }; | |
309 | const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6); | |
310 | ||
311 | GlobalProperty pc_compat_1_5[] = { | |
312 | PC_CPU_MODEL_IDS("1.5.0") | |
313 | { "Conroe-" TYPE_X86_CPU, "model", "2" }, | |
314 | { "Conroe-" TYPE_X86_CPU, "min-level", "2" }, | |
315 | { "Penryn-" TYPE_X86_CPU, "model", "2" }, | |
316 | { "Penryn-" TYPE_X86_CPU, "min-level", "2" }, | |
317 | { "Nehalem-" TYPE_X86_CPU, "model", "2" }, | |
318 | { "Nehalem-" TYPE_X86_CPU, "min-level", "2" }, | |
319 | { "virtio-net-pci", "any_layout", "off" }, | |
320 | { TYPE_X86_CPU, "pmu", "on" }, | |
321 | { "i440FX-pcihost", "short_root_bus", "0" }, | |
322 | { "q35-pcihost", "short_root_bus", "0" }, | |
323 | }; | |
324 | const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5); | |
325 | ||
326 | GlobalProperty pc_compat_1_4[] = { | |
327 | PC_CPU_MODEL_IDS("1.4.0") | |
328 | { "scsi-hd", "discard_granularity", "0" }, | |
329 | { "scsi-cd", "discard_granularity", "0" }, | |
330 | { "scsi-disk", "discard_granularity", "0" }, | |
331 | { "ide-hd", "discard_granularity", "0" }, | |
332 | { "ide-cd", "discard_granularity", "0" }, | |
333 | { "ide-drive", "discard_granularity", "0" }, | |
334 | { "virtio-blk-pci", "discard_granularity", "0" }, | |
335 | /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */ | |
336 | { "virtio-serial-pci", "vectors", "0xFFFFFFFF" }, | |
337 | { "virtio-net-pci", "ctrl_guest_offloads", "off" }, | |
338 | { "e1000", "romfile", "pxe-e1000.rom" }, | |
339 | { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" }, | |
340 | { "pcnet", "romfile", "pxe-pcnet.rom" }, | |
341 | { "rtl8139", "romfile", "pxe-rtl8139.rom" }, | |
342 | { "virtio-net-pci", "romfile", "pxe-virtio.rom" }, | |
343 | { "486-" TYPE_X86_CPU, "model", "0" }, | |
344 | { "n270" "-" TYPE_X86_CPU, "movbe", "off" }, | |
345 | { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" }, | |
346 | }; | |
347 | const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4); | |
348 | ||
349 | void gsi_handler(void *opaque, int n, int level) | |
350 | { | |
351 | GSIState *s = opaque; | |
352 | ||
353 | DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n); | |
354 | if (n < ISA_NUM_IRQS) { | |
355 | qemu_set_irq(s->i8259_irq[n], level); | |
356 | } | |
357 | qemu_set_irq(s->ioapic_irq[n], level); | |
358 | } | |
359 | ||
360 | static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, | |
361 | unsigned size) | |
362 | { | |
363 | } | |
364 | ||
365 | static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) | |
366 | { | |
367 | return 0xffffffffffffffffULL; | |
368 | } | |
369 | ||
370 | /* MSDOS compatibility mode FPU exception support */ | |
371 | static qemu_irq ferr_irq; | |
372 | ||
373 | void pc_register_ferr_irq(qemu_irq irq) | |
374 | { | |
375 | ferr_irq = irq; | |
376 | } | |
377 | ||
378 | /* XXX: add IGNNE support */ | |
379 | void cpu_set_ferr(CPUX86State *s) | |
380 | { | |
381 | qemu_irq_raise(ferr_irq); | |
382 | } | |
383 | ||
384 | static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, | |
385 | unsigned size) | |
386 | { | |
387 | qemu_irq_lower(ferr_irq); | |
388 | } | |
389 | ||
390 | static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) | |
391 | { | |
392 | return 0xffffffffffffffffULL; | |
393 | } | |
394 | ||
395 | /* TSC handling */ | |
396 | uint64_t cpu_get_tsc(CPUX86State *env) | |
397 | { | |
398 | return cpu_get_ticks(); | |
399 | } | |
400 | ||
401 | /* IRQ handling */ | |
402 | int cpu_get_pic_interrupt(CPUX86State *env) | |
403 | { | |
404 | X86CPU *cpu = env_archcpu(env); | |
405 | int intno; | |
406 | ||
407 | if (!kvm_irqchip_in_kernel()) { | |
408 | intno = apic_get_interrupt(cpu->apic_state); | |
409 | if (intno >= 0) { | |
410 | return intno; | |
411 | } | |
412 | /* read the irq from the PIC */ | |
413 | if (!apic_accept_pic_intr(cpu->apic_state)) { | |
414 | return -1; | |
415 | } | |
416 | } | |
417 | ||
418 | intno = pic_read_irq(isa_pic); | |
419 | return intno; | |
420 | } | |
421 | ||
422 | static void pic_irq_request(void *opaque, int irq, int level) | |
423 | { | |
424 | CPUState *cs = first_cpu; | |
425 | X86CPU *cpu = X86_CPU(cs); | |
426 | ||
427 | DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); | |
428 | if (cpu->apic_state && !kvm_irqchip_in_kernel()) { | |
429 | CPU_FOREACH(cs) { | |
430 | cpu = X86_CPU(cs); | |
431 | if (apic_accept_pic_intr(cpu->apic_state)) { | |
432 | apic_deliver_pic_intr(cpu->apic_state, level); | |
433 | } | |
434 | } | |
435 | } else { | |
436 | if (level) { | |
437 | cpu_interrupt(cs, CPU_INTERRUPT_HARD); | |
438 | } else { | |
439 | cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); | |
440 | } | |
441 | } | |
442 | } | |
443 | ||
444 | /* PC cmos mappings */ | |
445 | ||
446 | #define REG_EQUIPMENT_BYTE 0x14 | |
447 | ||
448 | int cmos_get_fd_drive_type(FloppyDriveType fd0) | |
449 | { | |
450 | int val; | |
451 | ||
452 | switch (fd0) { | |
453 | case FLOPPY_DRIVE_TYPE_144: | |
454 | /* 1.44 Mb 3"5 drive */ | |
455 | val = 4; | |
456 | break; | |
457 | case FLOPPY_DRIVE_TYPE_288: | |
458 | /* 2.88 Mb 3"5 drive */ | |
459 | val = 5; | |
460 | break; | |
461 | case FLOPPY_DRIVE_TYPE_120: | |
462 | /* 1.2 Mb 5"5 drive */ | |
463 | val = 2; | |
464 | break; | |
465 | case FLOPPY_DRIVE_TYPE_NONE: | |
466 | default: | |
467 | val = 0; | |
468 | break; | |
469 | } | |
470 | return val; | |
471 | } | |
472 | ||
473 | static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, | |
474 | int16_t cylinders, int8_t heads, int8_t sectors) | |
475 | { | |
476 | rtc_set_memory(s, type_ofs, 47); | |
477 | rtc_set_memory(s, info_ofs, cylinders); | |
478 | rtc_set_memory(s, info_ofs + 1, cylinders >> 8); | |
479 | rtc_set_memory(s, info_ofs + 2, heads); | |
480 | rtc_set_memory(s, info_ofs + 3, 0xff); | |
481 | rtc_set_memory(s, info_ofs + 4, 0xff); | |
482 | rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); | |
483 | rtc_set_memory(s, info_ofs + 6, cylinders); | |
484 | rtc_set_memory(s, info_ofs + 7, cylinders >> 8); | |
485 | rtc_set_memory(s, info_ofs + 8, sectors); | |
486 | } | |
487 | ||
488 | /* convert boot_device letter to something recognizable by the bios */ | |
489 | static int boot_device2nibble(char boot_device) | |
490 | { | |
491 | switch(boot_device) { | |
492 | case 'a': | |
493 | case 'b': | |
494 | return 0x01; /* floppy boot */ | |
495 | case 'c': | |
496 | return 0x02; /* hard drive boot */ | |
497 | case 'd': | |
498 | return 0x03; /* CD-ROM boot */ | |
499 | case 'n': | |
500 | return 0x04; /* Network boot */ | |
501 | } | |
502 | return 0; | |
503 | } | |
504 | ||
505 | static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) | |
506 | { | |
507 | #define PC_MAX_BOOT_DEVICES 3 | |
508 | int nbds, bds[3] = { 0, }; | |
509 | int i; | |
510 | ||
511 | nbds = strlen(boot_device); | |
512 | if (nbds > PC_MAX_BOOT_DEVICES) { | |
513 | error_setg(errp, "Too many boot devices for PC"); | |
514 | return; | |
515 | } | |
516 | for (i = 0; i < nbds; i++) { | |
517 | bds[i] = boot_device2nibble(boot_device[i]); | |
518 | if (bds[i] == 0) { | |
519 | error_setg(errp, "Invalid boot device for PC: '%c'", | |
520 | boot_device[i]); | |
521 | return; | |
522 | } | |
523 | } | |
524 | rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); | |
525 | rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); | |
526 | } | |
527 | ||
528 | static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) | |
529 | { | |
530 | set_boot_dev(opaque, boot_device, errp); | |
531 | } | |
532 | ||
533 | static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy) | |
534 | { | |
535 | int val, nb, i; | |
536 | FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, | |
537 | FLOPPY_DRIVE_TYPE_NONE }; | |
538 | ||
539 | /* floppy type */ | |
540 | if (floppy) { | |
541 | for (i = 0; i < 2; i++) { | |
542 | fd_type[i] = isa_fdc_get_drive_type(floppy, i); | |
543 | } | |
544 | } | |
545 | val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | | |
546 | cmos_get_fd_drive_type(fd_type[1]); | |
547 | rtc_set_memory(rtc_state, 0x10, val); | |
548 | ||
549 | val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE); | |
550 | nb = 0; | |
551 | if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { | |
552 | nb++; | |
553 | } | |
554 | if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { | |
555 | nb++; | |
556 | } | |
557 | switch (nb) { | |
558 | case 0: | |
559 | break; | |
560 | case 1: | |
561 | val |= 0x01; /* 1 drive, ready for boot */ | |
562 | break; | |
563 | case 2: | |
564 | val |= 0x41; /* 2 drives, ready for boot */ | |
565 | break; | |
566 | } | |
567 | rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val); | |
568 | } | |
569 | ||
570 | typedef struct pc_cmos_init_late_arg { | |
571 | ISADevice *rtc_state; | |
572 | BusState *idebus[2]; | |
573 | } pc_cmos_init_late_arg; | |
574 | ||
575 | typedef struct check_fdc_state { | |
576 | ISADevice *floppy; | |
577 | bool multiple; | |
578 | } CheckFdcState; | |
579 | ||
580 | static int check_fdc(Object *obj, void *opaque) | |
581 | { | |
582 | CheckFdcState *state = opaque; | |
583 | Object *fdc; | |
584 | uint32_t iobase; | |
585 | Error *local_err = NULL; | |
586 | ||
587 | fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); | |
588 | if (!fdc) { | |
589 | return 0; | |
590 | } | |
591 | ||
592 | iobase = object_property_get_uint(obj, "iobase", &local_err); | |
593 | if (local_err || iobase != 0x3f0) { | |
594 | error_free(local_err); | |
595 | return 0; | |
596 | } | |
597 | ||
598 | if (state->floppy) { | |
599 | state->multiple = true; | |
600 | } else { | |
601 | state->floppy = ISA_DEVICE(obj); | |
602 | } | |
603 | return 0; | |
604 | } | |
605 | ||
606 | static const char * const fdc_container_path[] = { | |
607 | "/unattached", "/peripheral", "/peripheral-anon" | |
608 | }; | |
609 | ||
610 | /* | |
611 | * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers | |
612 | * and ACPI objects. | |
613 | */ | |
614 | ISADevice *pc_find_fdc0(void) | |
615 | { | |
616 | int i; | |
617 | Object *container; | |
618 | CheckFdcState state = { 0 }; | |
619 | ||
620 | for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { | |
621 | container = container_get(qdev_get_machine(), fdc_container_path[i]); | |
622 | object_child_foreach(container, check_fdc, &state); | |
623 | } | |
624 | ||
625 | if (state.multiple) { | |
626 | warn_report("multiple floppy disk controllers with " | |
627 | "iobase=0x3f0 have been found"); | |
628 | error_printf("the one being picked for CMOS setup might not reflect " | |
629 | "your intent"); | |
630 | } | |
631 | ||
632 | return state.floppy; | |
633 | } | |
634 | ||
635 | static void pc_cmos_init_late(void *opaque) | |
636 | { | |
637 | pc_cmos_init_late_arg *arg = opaque; | |
638 | ISADevice *s = arg->rtc_state; | |
639 | int16_t cylinders; | |
640 | int8_t heads, sectors; | |
641 | int val; | |
642 | int i, trans; | |
643 | ||
644 | val = 0; | |
645 | if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0, | |
646 | &cylinders, &heads, §ors) >= 0) { | |
647 | cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); | |
648 | val |= 0xf0; | |
649 | } | |
650 | if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1, | |
651 | &cylinders, &heads, §ors) >= 0) { | |
652 | cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); | |
653 | val |= 0x0f; | |
654 | } | |
655 | rtc_set_memory(s, 0x12, val); | |
656 | ||
657 | val = 0; | |
658 | for (i = 0; i < 4; i++) { | |
659 | /* NOTE: ide_get_geometry() returns the physical | |
660 | geometry. It is always such that: 1 <= sects <= 63, 1 | |
661 | <= heads <= 16, 1 <= cylinders <= 16383. The BIOS | |
662 | geometry can be different if a translation is done. */ | |
663 | if (arg->idebus[i / 2] && | |
664 | ide_get_geometry(arg->idebus[i / 2], i % 2, | |
665 | &cylinders, &heads, §ors) >= 0) { | |
666 | trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; | |
667 | assert((trans & ~3) == 0); | |
668 | val |= trans << (i * 2); | |
669 | } | |
670 | } | |
671 | rtc_set_memory(s, 0x39, val); | |
672 | ||
673 | pc_cmos_init_floppy(s, pc_find_fdc0()); | |
674 | ||
675 | qemu_unregister_reset(pc_cmos_init_late, opaque); | |
676 | } | |
677 | ||
678 | void pc_cmos_init(PCMachineState *pcms, | |
679 | BusState *idebus0, BusState *idebus1, | |
680 | ISADevice *s) | |
681 | { | |
682 | int val; | |
683 | static pc_cmos_init_late_arg arg; | |
684 | ||
685 | /* various important CMOS locations needed by PC/Bochs bios */ | |
686 | ||
687 | /* memory size */ | |
688 | /* base memory (first MiB) */ | |
689 | val = MIN(pcms->below_4g_mem_size / KiB, 640); | |
690 | rtc_set_memory(s, 0x15, val); | |
691 | rtc_set_memory(s, 0x16, val >> 8); | |
692 | /* extended memory (next 64MiB) */ | |
693 | if (pcms->below_4g_mem_size > 1 * MiB) { | |
694 | val = (pcms->below_4g_mem_size - 1 * MiB) / KiB; | |
695 | } else { | |
696 | val = 0; | |
697 | } | |
698 | if (val > 65535) | |
699 | val = 65535; | |
700 | rtc_set_memory(s, 0x17, val); | |
701 | rtc_set_memory(s, 0x18, val >> 8); | |
702 | rtc_set_memory(s, 0x30, val); | |
703 | rtc_set_memory(s, 0x31, val >> 8); | |
704 | /* memory between 16MiB and 4GiB */ | |
705 | if (pcms->below_4g_mem_size > 16 * MiB) { | |
706 | val = (pcms->below_4g_mem_size - 16 * MiB) / (64 * KiB); | |
707 | } else { | |
708 | val = 0; | |
709 | } | |
710 | if (val > 65535) | |
711 | val = 65535; | |
712 | rtc_set_memory(s, 0x34, val); | |
713 | rtc_set_memory(s, 0x35, val >> 8); | |
714 | /* memory above 4GiB */ | |
715 | val = pcms->above_4g_mem_size / 65536; | |
716 | rtc_set_memory(s, 0x5b, val); | |
717 | rtc_set_memory(s, 0x5c, val >> 8); | |
718 | rtc_set_memory(s, 0x5d, val >> 16); | |
719 | ||
720 | object_property_add_link(OBJECT(pcms), "rtc_state", | |
721 | TYPE_ISA_DEVICE, | |
722 | (Object **)&pcms->rtc, | |
723 | object_property_allow_set_link, | |
724 | OBJ_PROP_LINK_STRONG, &error_abort); | |
725 | object_property_set_link(OBJECT(pcms), OBJECT(s), | |
726 | "rtc_state", &error_abort); | |
727 | ||
728 | set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal); | |
729 | ||
730 | val = 0; | |
731 | val |= 0x02; /* FPU is there */ | |
732 | val |= 0x04; /* PS/2 mouse installed */ | |
733 | rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); | |
734 | ||
735 | /* hard drives and FDC */ | |
736 | arg.rtc_state = s; | |
737 | arg.idebus[0] = idebus0; | |
738 | arg.idebus[1] = idebus1; | |
739 | qemu_register_reset(pc_cmos_init_late, &arg); | |
740 | } | |
741 | ||
742 | #define TYPE_PORT92 "port92" | |
743 | #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92) | |
744 | ||
745 | /* port 92 stuff: could be split off */ | |
746 | typedef struct Port92State { | |
747 | ISADevice parent_obj; | |
748 | ||
749 | MemoryRegion io; | |
750 | uint8_t outport; | |
751 | qemu_irq a20_out; | |
752 | } Port92State; | |
753 | ||
754 | static void port92_write(void *opaque, hwaddr addr, uint64_t val, | |
755 | unsigned size) | |
756 | { | |
757 | Port92State *s = opaque; | |
758 | int oldval = s->outport; | |
759 | ||
760 | DPRINTF("port92: write 0x%02" PRIx64 "\n", val); | |
761 | s->outport = val; | |
762 | qemu_set_irq(s->a20_out, (val >> 1) & 1); | |
763 | if ((val & 1) && !(oldval & 1)) { | |
764 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); | |
765 | } | |
766 | } | |
767 | ||
768 | static uint64_t port92_read(void *opaque, hwaddr addr, | |
769 | unsigned size) | |
770 | { | |
771 | Port92State *s = opaque; | |
772 | uint32_t ret; | |
773 | ||
774 | ret = s->outport; | |
775 | DPRINTF("port92: read 0x%02x\n", ret); | |
776 | return ret; | |
777 | } | |
778 | ||
779 | static void port92_init(ISADevice *dev, qemu_irq a20_out) | |
780 | { | |
781 | qdev_connect_gpio_out_named(DEVICE(dev), PORT92_A20_LINE, 0, a20_out); | |
782 | } | |
783 | ||
784 | static const VMStateDescription vmstate_port92_isa = { | |
785 | .name = "port92", | |
786 | .version_id = 1, | |
787 | .minimum_version_id = 1, | |
788 | .fields = (VMStateField[]) { | |
789 | VMSTATE_UINT8(outport, Port92State), | |
790 | VMSTATE_END_OF_LIST() | |
791 | } | |
792 | }; | |
793 | ||
794 | static void port92_reset(DeviceState *d) | |
795 | { | |
796 | Port92State *s = PORT92(d); | |
797 | ||
798 | s->outport &= ~1; | |
799 | } | |
800 | ||
801 | static const MemoryRegionOps port92_ops = { | |
802 | .read = port92_read, | |
803 | .write = port92_write, | |
804 | .impl = { | |
805 | .min_access_size = 1, | |
806 | .max_access_size = 1, | |
807 | }, | |
808 | .endianness = DEVICE_LITTLE_ENDIAN, | |
809 | }; | |
810 | ||
811 | static void port92_initfn(Object *obj) | |
812 | { | |
813 | Port92State *s = PORT92(obj); | |
814 | ||
815 | memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1); | |
816 | ||
817 | s->outport = 0; | |
818 | ||
819 | qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, PORT92_A20_LINE, 1); | |
820 | } | |
821 | ||
822 | static void port92_realizefn(DeviceState *dev, Error **errp) | |
823 | { | |
824 | ISADevice *isadev = ISA_DEVICE(dev); | |
825 | Port92State *s = PORT92(dev); | |
826 | ||
827 | isa_register_ioport(isadev, &s->io, 0x92); | |
828 | } | |
829 | ||
830 | static void port92_class_initfn(ObjectClass *klass, void *data) | |
831 | { | |
832 | DeviceClass *dc = DEVICE_CLASS(klass); | |
833 | ||
834 | dc->realize = port92_realizefn; | |
835 | dc->reset = port92_reset; | |
836 | dc->vmsd = &vmstate_port92_isa; | |
837 | /* | |
838 | * Reason: unlike ordinary ISA devices, this one needs additional | |
839 | * wiring: its A20 output line needs to be wired up by | |
840 | * port92_init(). | |
841 | */ | |
842 | dc->user_creatable = false; | |
843 | } | |
844 | ||
845 | static const TypeInfo port92_info = { | |
846 | .name = TYPE_PORT92, | |
847 | .parent = TYPE_ISA_DEVICE, | |
848 | .instance_size = sizeof(Port92State), | |
849 | .instance_init = port92_initfn, | |
850 | .class_init = port92_class_initfn, | |
851 | }; | |
852 | ||
853 | static void port92_register_types(void) | |
854 | { | |
855 | type_register_static(&port92_info); | |
856 | } | |
857 | ||
858 | type_init(port92_register_types) | |
859 | ||
860 | static void handle_a20_line_change(void *opaque, int irq, int level) | |
861 | { | |
862 | X86CPU *cpu = opaque; | |
863 | ||
864 | /* XXX: send to all CPUs ? */ | |
865 | /* XXX: add logic to handle multiple A20 line sources */ | |
866 | x86_cpu_set_a20(cpu, level); | |
867 | } | |
868 | ||
869 | /* | |
870 | * Calculates initial APIC ID for a specific CPU index | |
871 | * | |
872 | * Currently we need to be able to calculate the APIC ID from the CPU index | |
873 | * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have | |
874 | * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of | |
875 | * all CPUs up to max_cpus. | |
876 | */ | |
877 | static uint32_t x86_cpu_apic_id_from_index(PCMachineState *pcms, | |
878 | unsigned int cpu_index) | |
879 | { | |
880 | MachineState *ms = MACHINE(pcms); | |
881 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); | |
882 | uint32_t correct_id; | |
883 | static bool warned; | |
884 | ||
885 | correct_id = x86_apicid_from_cpu_idx(pcms->smp_dies, ms->smp.cores, | |
886 | ms->smp.threads, cpu_index); | |
887 | if (pcmc->compat_apic_id_mode) { | |
888 | if (cpu_index != correct_id && !warned && !qtest_enabled()) { | |
889 | error_report("APIC IDs set in compatibility mode, " | |
890 | "CPU topology won't match the configuration"); | |
891 | warned = true; | |
892 | } | |
893 | return cpu_index; | |
894 | } else { | |
895 | return correct_id; | |
896 | } | |
897 | } | |
898 | ||
899 | static long get_file_size(FILE *f) | |
900 | { | |
901 | long where, size; | |
902 | ||
903 | /* XXX: on Unix systems, using fstat() probably makes more sense */ | |
904 | ||
905 | where = ftell(f); | |
906 | fseek(f, 0, SEEK_END); | |
907 | size = ftell(f); | |
908 | fseek(f, where, SEEK_SET); | |
909 | ||
910 | return size; | |
911 | } | |
912 | ||
913 | struct setup_data { | |
914 | uint64_t next; | |
915 | uint32_t type; | |
916 | uint32_t len; | |
917 | uint8_t data[0]; | |
918 | } __attribute__((packed)); | |
919 | ||
920 | ||
921 | /* | |
922 | * The entry point into the kernel for PVH boot is different from | |
923 | * the native entry point. The PVH entry is defined by the x86/HVM | |
924 | * direct boot ABI and is available in an ELFNOTE in the kernel binary. | |
925 | * | |
926 | * This function is passed to load_elf() when it is called from | |
927 | * load_elfboot() which then additionally checks for an ELF Note of | |
928 | * type XEN_ELFNOTE_PHYS32_ENTRY and passes it to this function to | |
929 | * parse the PVH entry address from the ELF Note. | |
930 | * | |
931 | * Due to trickery in elf_opts.h, load_elf() is actually available as | |
932 | * load_elf32() or load_elf64() and this routine needs to be able | |
933 | * to deal with being called as 32 or 64 bit. | |
934 | * | |
935 | * The address of the PVH entry point is saved to the 'pvh_start_addr' | |
936 | * global variable. (although the entry point is 32-bit, the kernel | |
937 | * binary can be either 32-bit or 64-bit). | |
938 | */ | |
939 | static uint64_t read_pvh_start_addr(void *arg1, void *arg2, bool is64) | |
940 | { | |
941 | size_t *elf_note_data_addr; | |
942 | ||
943 | /* Check if ELF Note header passed in is valid */ | |
944 | if (arg1 == NULL) { | |
945 | return 0; | |
946 | } | |
947 | ||
948 | if (is64) { | |
949 | struct elf64_note *nhdr64 = (struct elf64_note *)arg1; | |
950 | uint64_t nhdr_size64 = sizeof(struct elf64_note); | |
951 | uint64_t phdr_align = *(uint64_t *)arg2; | |
952 | uint64_t nhdr_namesz = nhdr64->n_namesz; | |
953 | ||
954 | elf_note_data_addr = | |
955 | ((void *)nhdr64) + nhdr_size64 + | |
956 | QEMU_ALIGN_UP(nhdr_namesz, phdr_align); | |
957 | } else { | |
958 | struct elf32_note *nhdr32 = (struct elf32_note *)arg1; | |
959 | uint32_t nhdr_size32 = sizeof(struct elf32_note); | |
960 | uint32_t phdr_align = *(uint32_t *)arg2; | |
961 | uint32_t nhdr_namesz = nhdr32->n_namesz; | |
962 | ||
963 | elf_note_data_addr = | |
964 | ((void *)nhdr32) + nhdr_size32 + | |
965 | QEMU_ALIGN_UP(nhdr_namesz, phdr_align); | |
966 | } | |
967 | ||
968 | pvh_start_addr = *elf_note_data_addr; | |
969 | ||
970 | return pvh_start_addr; | |
971 | } | |
972 | ||
973 | static bool load_elfboot(const char *kernel_filename, | |
974 | int kernel_file_size, | |
975 | uint8_t *header, | |
976 | size_t pvh_xen_start_addr, | |
977 | FWCfgState *fw_cfg) | |
978 | { | |
979 | uint32_t flags = 0; | |
980 | uint32_t mh_load_addr = 0; | |
981 | uint32_t elf_kernel_size = 0; | |
982 | uint64_t elf_entry; | |
983 | uint64_t elf_low, elf_high; | |
984 | int kernel_size; | |
985 | ||
986 | if (ldl_p(header) != 0x464c457f) { | |
987 | return false; /* no elfboot */ | |
988 | } | |
989 | ||
990 | bool elf_is64 = header[EI_CLASS] == ELFCLASS64; | |
991 | flags = elf_is64 ? | |
992 | ((Elf64_Ehdr *)header)->e_flags : ((Elf32_Ehdr *)header)->e_flags; | |
993 | ||
994 | if (flags & 0x00010004) { /* LOAD_ELF_HEADER_HAS_ADDR */ | |
995 | error_report("elfboot unsupported flags = %x", flags); | |
996 | exit(1); | |
997 | } | |
998 | ||
999 | uint64_t elf_note_type = XEN_ELFNOTE_PHYS32_ENTRY; | |
1000 | kernel_size = load_elf(kernel_filename, read_pvh_start_addr, | |
1001 | NULL, &elf_note_type, &elf_entry, | |
1002 | &elf_low, &elf_high, 0, I386_ELF_MACHINE, | |
1003 | 0, 0); | |
1004 | ||
1005 | if (kernel_size < 0) { | |
1006 | error_report("Error while loading elf kernel"); | |
1007 | exit(1); | |
1008 | } | |
1009 | mh_load_addr = elf_low; | |
1010 | elf_kernel_size = elf_high - elf_low; | |
1011 | ||
1012 | if (pvh_start_addr == 0) { | |
1013 | error_report("Error loading uncompressed kernel without PVH ELF Note"); | |
1014 | exit(1); | |
1015 | } | |
1016 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ENTRY, pvh_start_addr); | |
1017 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, mh_load_addr); | |
1018 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, elf_kernel_size); | |
1019 | ||
1020 | return true; | |
1021 | } | |
1022 | ||
1023 | static void x86_load_linux(PCMachineState *pcms, | |
1024 | FWCfgState *fw_cfg) | |
1025 | { | |
1026 | uint16_t protocol; | |
1027 | int setup_size, kernel_size, cmdline_size; | |
1028 | int dtb_size, setup_data_offset; | |
1029 | uint32_t initrd_max; | |
1030 | uint8_t header[8192], *setup, *kernel; | |
1031 | hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0; | |
1032 | FILE *f; | |
1033 | char *vmode; | |
1034 | MachineState *machine = MACHINE(pcms); | |
1035 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); | |
1036 | struct setup_data *setup_data; | |
1037 | const char *kernel_filename = machine->kernel_filename; | |
1038 | const char *initrd_filename = machine->initrd_filename; | |
1039 | const char *dtb_filename = machine->dtb; | |
1040 | const char *kernel_cmdline = machine->kernel_cmdline; | |
1041 | ||
1042 | /* Align to 16 bytes as a paranoia measure */ | |
1043 | cmdline_size = (strlen(kernel_cmdline) + 16) & ~15; | |
1044 | ||
1045 | /* load the kernel header */ | |
1046 | f = fopen(kernel_filename, "rb"); | |
1047 | if (!f || !(kernel_size = get_file_size(f)) || | |
1048 | fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != | |
1049 | MIN(ARRAY_SIZE(header), kernel_size)) { | |
1050 | fprintf(stderr, "qemu: could not load kernel '%s': %s\n", | |
1051 | kernel_filename, strerror(errno)); | |
1052 | exit(1); | |
1053 | } | |
1054 | ||
1055 | /* kernel protocol version */ | |
1056 | #if 0 | |
1057 | fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); | |
1058 | #endif | |
1059 | if (ldl_p(header + 0x202) == 0x53726448) { | |
1060 | protocol = lduw_p(header + 0x206); | |
1061 | } else { | |
1062 | /* | |
1063 | * This could be a multiboot kernel. If it is, let's stop treating it | |
1064 | * like a Linux kernel. | |
1065 | * Note: some multiboot images could be in the ELF format (the same of | |
1066 | * PVH), so we try multiboot first since we check the multiboot magic | |
1067 | * header before to load it. | |
1068 | */ | |
1069 | if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename, | |
1070 | kernel_cmdline, kernel_size, header)) { | |
1071 | return; | |
1072 | } | |
1073 | /* | |
1074 | * Check if the file is an uncompressed kernel file (ELF) and load it, | |
1075 | * saving the PVH entry point used by the x86/HVM direct boot ABI. | |
1076 | * If load_elfboot() is successful, populate the fw_cfg info. | |
1077 | */ | |
1078 | if (pcmc->pvh_enabled && | |
1079 | load_elfboot(kernel_filename, kernel_size, | |
1080 | header, pvh_start_addr, fw_cfg)) { | |
1081 | fclose(f); | |
1082 | ||
1083 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, | |
1084 | strlen(kernel_cmdline) + 1); | |
1085 | fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); | |
1086 | ||
1087 | fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, sizeof(header)); | |
1088 | fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, | |
1089 | header, sizeof(header)); | |
1090 | ||
1091 | /* load initrd */ | |
1092 | if (initrd_filename) { | |
1093 | GMappedFile *mapped_file; | |
1094 | gsize initrd_size; | |
1095 | gchar *initrd_data; | |
1096 | GError *gerr = NULL; | |
1097 | ||
1098 | mapped_file = g_mapped_file_new(initrd_filename, false, &gerr); | |
1099 | if (!mapped_file) { | |
1100 | fprintf(stderr, "qemu: error reading initrd %s: %s\n", | |
1101 | initrd_filename, gerr->message); | |
1102 | exit(1); | |
1103 | } | |
1104 | pcms->initrd_mapped_file = mapped_file; | |
1105 | ||
1106 | initrd_data = g_mapped_file_get_contents(mapped_file); | |
1107 | initrd_size = g_mapped_file_get_length(mapped_file); | |
1108 | initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1; | |
1109 | if (initrd_size >= initrd_max) { | |
1110 | fprintf(stderr, "qemu: initrd is too large, cannot support." | |
1111 | "(max: %"PRIu32", need %"PRId64")\n", | |
1112 | initrd_max, (uint64_t)initrd_size); | |
1113 | exit(1); | |
1114 | } | |
1115 | ||
1116 | initrd_addr = (initrd_max - initrd_size) & ~4095; | |
1117 | ||
1118 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); | |
1119 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); | |
1120 | fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, | |
1121 | initrd_size); | |
1122 | } | |
1123 | ||
1124 | option_rom[nb_option_roms].bootindex = 0; | |
1125 | option_rom[nb_option_roms].name = "pvh.bin"; | |
1126 | nb_option_roms++; | |
1127 | ||
1128 | return; | |
1129 | } | |
1130 | protocol = 0; | |
1131 | } | |
1132 | ||
1133 | if (protocol < 0x200 || !(header[0x211] & 0x01)) { | |
1134 | /* Low kernel */ | |
1135 | real_addr = 0x90000; | |
1136 | cmdline_addr = 0x9a000 - cmdline_size; | |
1137 | prot_addr = 0x10000; | |
1138 | } else if (protocol < 0x202) { | |
1139 | /* High but ancient kernel */ | |
1140 | real_addr = 0x90000; | |
1141 | cmdline_addr = 0x9a000 - cmdline_size; | |
1142 | prot_addr = 0x100000; | |
1143 | } else { | |
1144 | /* High and recent kernel */ | |
1145 | real_addr = 0x10000; | |
1146 | cmdline_addr = 0x20000; | |
1147 | prot_addr = 0x100000; | |
1148 | } | |
1149 | ||
1150 | #if 0 | |
1151 | fprintf(stderr, | |
1152 | "qemu: real_addr = 0x" TARGET_FMT_plx "\n" | |
1153 | "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n" | |
1154 | "qemu: prot_addr = 0x" TARGET_FMT_plx "\n", | |
1155 | real_addr, | |
1156 | cmdline_addr, | |
1157 | prot_addr); | |
1158 | #endif | |
1159 | ||
1160 | /* highest address for loading the initrd */ | |
1161 | if (protocol >= 0x20c && | |
1162 | lduw_p(header + 0x236) & XLF_CAN_BE_LOADED_ABOVE_4G) { | |
1163 | /* | |
1164 | * Linux has supported initrd up to 4 GB for a very long time (2007, | |
1165 | * long before XLF_CAN_BE_LOADED_ABOVE_4G which was added in 2013), | |
1166 | * though it only sets initrd_max to 2 GB to "work around bootloader | |
1167 | * bugs". Luckily, QEMU firmware(which does something like bootloader) | |
1168 | * has supported this. | |
1169 | * | |
1170 | * It's believed that if XLF_CAN_BE_LOADED_ABOVE_4G is set, initrd can | |
1171 | * be loaded into any address. | |
1172 | * | |
1173 | * In addition, initrd_max is uint32_t simply because QEMU doesn't | |
1174 | * support the 64-bit boot protocol (specifically the ext_ramdisk_image | |
1175 | * field). | |
1176 | * | |
1177 | * Therefore here just limit initrd_max to UINT32_MAX simply as well. | |
1178 | */ | |
1179 | initrd_max = UINT32_MAX; | |
1180 | } else if (protocol >= 0x203) { | |
1181 | initrd_max = ldl_p(header + 0x22c); | |
1182 | } else { | |
1183 | initrd_max = 0x37ffffff; | |
1184 | } | |
1185 | ||
1186 | if (initrd_max >= pcms->below_4g_mem_size - pcmc->acpi_data_size) { | |
1187 | initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1; | |
1188 | } | |
1189 | ||
1190 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); | |
1191 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline) + 1); | |
1192 | fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); | |
1193 | ||
1194 | if (protocol >= 0x202) { | |
1195 | stl_p(header + 0x228, cmdline_addr); | |
1196 | } else { | |
1197 | stw_p(header + 0x20, 0xA33F); | |
1198 | stw_p(header + 0x22, cmdline_addr - real_addr); | |
1199 | } | |
1200 | ||
1201 | /* handle vga= parameter */ | |
1202 | vmode = strstr(kernel_cmdline, "vga="); | |
1203 | if (vmode) { | |
1204 | unsigned int video_mode; | |
1205 | /* skip "vga=" */ | |
1206 | vmode += 4; | |
1207 | if (!strncmp(vmode, "normal", 6)) { | |
1208 | video_mode = 0xffff; | |
1209 | } else if (!strncmp(vmode, "ext", 3)) { | |
1210 | video_mode = 0xfffe; | |
1211 | } else if (!strncmp(vmode, "ask", 3)) { | |
1212 | video_mode = 0xfffd; | |
1213 | } else { | |
1214 | video_mode = strtol(vmode, NULL, 0); | |
1215 | } | |
1216 | stw_p(header + 0x1fa, video_mode); | |
1217 | } | |
1218 | ||
1219 | /* loader type */ | |
1220 | /* | |
1221 | * High nybble = B reserved for QEMU; low nybble is revision number. | |
1222 | * If this code is substantially changed, you may want to consider | |
1223 | * incrementing the revision. | |
1224 | */ | |
1225 | if (protocol >= 0x200) { | |
1226 | header[0x210] = 0xB0; | |
1227 | } | |
1228 | /* heap */ | |
1229 | if (protocol >= 0x201) { | |
1230 | header[0x211] |= 0x80; /* CAN_USE_HEAP */ | |
1231 | stw_p(header + 0x224, cmdline_addr - real_addr - 0x200); | |
1232 | } | |
1233 | ||
1234 | /* load initrd */ | |
1235 | if (initrd_filename) { | |
1236 | GMappedFile *mapped_file; | |
1237 | gsize initrd_size; | |
1238 | gchar *initrd_data; | |
1239 | GError *gerr = NULL; | |
1240 | ||
1241 | if (protocol < 0x200) { | |
1242 | fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); | |
1243 | exit(1); | |
1244 | } | |
1245 | ||
1246 | mapped_file = g_mapped_file_new(initrd_filename, false, &gerr); | |
1247 | if (!mapped_file) { | |
1248 | fprintf(stderr, "qemu: error reading initrd %s: %s\n", | |
1249 | initrd_filename, gerr->message); | |
1250 | exit(1); | |
1251 | } | |
1252 | pcms->initrd_mapped_file = mapped_file; | |
1253 | ||
1254 | initrd_data = g_mapped_file_get_contents(mapped_file); | |
1255 | initrd_size = g_mapped_file_get_length(mapped_file); | |
1256 | if (initrd_size >= initrd_max) { | |
1257 | fprintf(stderr, "qemu: initrd is too large, cannot support." | |
1258 | "(max: %"PRIu32", need %"PRId64")\n", | |
1259 | initrd_max, (uint64_t)initrd_size); | |
1260 | exit(1); | |
1261 | } | |
1262 | ||
1263 | initrd_addr = (initrd_max - initrd_size) & ~4095; | |
1264 | ||
1265 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); | |
1266 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); | |
1267 | fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); | |
1268 | ||
1269 | stl_p(header + 0x218, initrd_addr); | |
1270 | stl_p(header + 0x21c, initrd_size); | |
1271 | } | |
1272 | ||
1273 | /* load kernel and setup */ | |
1274 | setup_size = header[0x1f1]; | |
1275 | if (setup_size == 0) { | |
1276 | setup_size = 4; | |
1277 | } | |
1278 | setup_size = (setup_size + 1) * 512; | |
1279 | if (setup_size > kernel_size) { | |
1280 | fprintf(stderr, "qemu: invalid kernel header\n"); | |
1281 | exit(1); | |
1282 | } | |
1283 | kernel_size -= setup_size; | |
1284 | ||
1285 | setup = g_malloc(setup_size); | |
1286 | kernel = g_malloc(kernel_size); | |
1287 | fseek(f, 0, SEEK_SET); | |
1288 | if (fread(setup, 1, setup_size, f) != setup_size) { | |
1289 | fprintf(stderr, "fread() failed\n"); | |
1290 | exit(1); | |
1291 | } | |
1292 | if (fread(kernel, 1, kernel_size, f) != kernel_size) { | |
1293 | fprintf(stderr, "fread() failed\n"); | |
1294 | exit(1); | |
1295 | } | |
1296 | fclose(f); | |
1297 | ||
1298 | /* append dtb to kernel */ | |
1299 | if (dtb_filename) { | |
1300 | if (protocol < 0x209) { | |
1301 | fprintf(stderr, "qemu: Linux kernel too old to load a dtb\n"); | |
1302 | exit(1); | |
1303 | } | |
1304 | ||
1305 | dtb_size = get_image_size(dtb_filename); | |
1306 | if (dtb_size <= 0) { | |
1307 | fprintf(stderr, "qemu: error reading dtb %s: %s\n", | |
1308 | dtb_filename, strerror(errno)); | |
1309 | exit(1); | |
1310 | } | |
1311 | ||
1312 | setup_data_offset = QEMU_ALIGN_UP(kernel_size, 16); | |
1313 | kernel_size = setup_data_offset + sizeof(struct setup_data) + dtb_size; | |
1314 | kernel = g_realloc(kernel, kernel_size); | |
1315 | ||
1316 | stq_p(header + 0x250, prot_addr + setup_data_offset); | |
1317 | ||
1318 | setup_data = (struct setup_data *)(kernel + setup_data_offset); | |
1319 | setup_data->next = 0; | |
1320 | setup_data->type = cpu_to_le32(SETUP_DTB); | |
1321 | setup_data->len = cpu_to_le32(dtb_size); | |
1322 | ||
1323 | load_image_size(dtb_filename, setup_data->data, dtb_size); | |
1324 | } | |
1325 | ||
1326 | memcpy(setup, header, MIN(sizeof(header), setup_size)); | |
1327 | ||
1328 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); | |
1329 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); | |
1330 | fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); | |
1331 | ||
1332 | fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); | |
1333 | fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); | |
1334 | fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); | |
1335 | ||
1336 | option_rom[nb_option_roms].bootindex = 0; | |
1337 | option_rom[nb_option_roms].name = "linuxboot.bin"; | |
1338 | if (pcmc->linuxboot_dma_enabled && fw_cfg_dma_enabled(fw_cfg)) { | |
1339 | option_rom[nb_option_roms].name = "linuxboot_dma.bin"; | |
1340 | } | |
1341 | nb_option_roms++; | |
1342 | } | |
1343 | ||
1344 | #define NE2000_NB_MAX 6 | |
1345 | ||
1346 | static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, | |
1347 | 0x280, 0x380 }; | |
1348 | static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; | |
1349 | ||
1350 | void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) | |
1351 | { | |
1352 | static int nb_ne2k = 0; | |
1353 | ||
1354 | if (nb_ne2k == NE2000_NB_MAX) | |
1355 | return; | |
1356 | isa_ne2000_init(bus, ne2000_io[nb_ne2k], | |
1357 | ne2000_irq[nb_ne2k], nd); | |
1358 | nb_ne2k++; | |
1359 | } | |
1360 | ||
1361 | DeviceState *cpu_get_current_apic(void) | |
1362 | { | |
1363 | if (current_cpu) { | |
1364 | X86CPU *cpu = X86_CPU(current_cpu); | |
1365 | return cpu->apic_state; | |
1366 | } else { | |
1367 | return NULL; | |
1368 | } | |
1369 | } | |
1370 | ||
1371 | void pc_acpi_smi_interrupt(void *opaque, int irq, int level) | |
1372 | { | |
1373 | X86CPU *cpu = opaque; | |
1374 | ||
1375 | if (level) { | |
1376 | cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); | |
1377 | } | |
1378 | } | |
1379 | ||
1380 | static void x86_cpu_new(PCMachineState *pcms, int64_t apic_id, Error **errp) | |
1381 | { | |
1382 | Object *cpu = NULL; | |
1383 | Error *local_err = NULL; | |
1384 | CPUX86State *env = NULL; | |
1385 | ||
1386 | cpu = object_new(MACHINE(pcms)->cpu_type); | |
1387 | ||
1388 | env = &X86_CPU(cpu)->env; | |
1389 | env->nr_dies = pcms->smp_dies; | |
1390 | ||
1391 | object_property_set_uint(cpu, apic_id, "apic-id", &local_err); | |
1392 | object_property_set_bool(cpu, true, "realized", &local_err); | |
1393 | ||
1394 | object_unref(cpu); | |
1395 | error_propagate(errp, local_err); | |
1396 | } | |
1397 | ||
1398 | /* | |
1399 | * This function is very similar to smp_parse() | |
1400 | * in hw/core/machine.c but includes CPU die support. | |
1401 | */ | |
1402 | void pc_smp_parse(MachineState *ms, QemuOpts *opts) | |
1403 | { | |
1404 | PCMachineState *pcms = PC_MACHINE(ms); | |
1405 | ||
1406 | if (opts) { | |
1407 | unsigned cpus = qemu_opt_get_number(opts, "cpus", 0); | |
1408 | unsigned sockets = qemu_opt_get_number(opts, "sockets", 0); | |
1409 | unsigned dies = qemu_opt_get_number(opts, "dies", 1); | |
1410 | unsigned cores = qemu_opt_get_number(opts, "cores", 0); | |
1411 | unsigned threads = qemu_opt_get_number(opts, "threads", 0); | |
1412 | ||
1413 | /* compute missing values, prefer sockets over cores over threads */ | |
1414 | if (cpus == 0 || sockets == 0) { | |
1415 | cores = cores > 0 ? cores : 1; | |
1416 | threads = threads > 0 ? threads : 1; | |
1417 | if (cpus == 0) { | |
1418 | sockets = sockets > 0 ? sockets : 1; | |
1419 | cpus = cores * threads * dies * sockets; | |
1420 | } else { | |
1421 | ms->smp.max_cpus = | |
1422 | qemu_opt_get_number(opts, "maxcpus", cpus); | |
1423 | sockets = ms->smp.max_cpus / (cores * threads * dies); | |
1424 | } | |
1425 | } else if (cores == 0) { | |
1426 | threads = threads > 0 ? threads : 1; | |
1427 | cores = cpus / (sockets * dies * threads); | |
1428 | cores = cores > 0 ? cores : 1; | |
1429 | } else if (threads == 0) { | |
1430 | threads = cpus / (cores * dies * sockets); | |
1431 | threads = threads > 0 ? threads : 1; | |
1432 | } else if (sockets * dies * cores * threads < cpus) { | |
1433 | error_report("cpu topology: " | |
1434 | "sockets (%u) * dies (%u) * cores (%u) * threads (%u) < " | |
1435 | "smp_cpus (%u)", | |
1436 | sockets, dies, cores, threads, cpus); | |
1437 | exit(1); | |
1438 | } | |
1439 | ||
1440 | ms->smp.max_cpus = | |
1441 | qemu_opt_get_number(opts, "maxcpus", cpus); | |
1442 | ||
1443 | if (ms->smp.max_cpus < cpus) { | |
1444 | error_report("maxcpus must be equal to or greater than smp"); | |
1445 | exit(1); | |
1446 | } | |
1447 | ||
1448 | if (sockets * dies * cores * threads > ms->smp.max_cpus) { | |
1449 | error_report("cpu topology: " | |
1450 | "sockets (%u) * dies (%u) * cores (%u) * threads (%u) > " | |
1451 | "maxcpus (%u)", | |
1452 | sockets, dies, cores, threads, | |
1453 | ms->smp.max_cpus); | |
1454 | exit(1); | |
1455 | } | |
1456 | ||
1457 | if (sockets * dies * cores * threads != ms->smp.max_cpus) { | |
1458 | warn_report("Invalid CPU topology deprecated: " | |
1459 | "sockets (%u) * dies (%u) * cores (%u) * threads (%u) " | |
1460 | "!= maxcpus (%u)", | |
1461 | sockets, dies, cores, threads, | |
1462 | ms->smp.max_cpus); | |
1463 | } | |
1464 | ||
1465 | ms->smp.cpus = cpus; | |
1466 | ms->smp.cores = cores; | |
1467 | ms->smp.threads = threads; | |
1468 | pcms->smp_dies = dies; | |
1469 | } | |
1470 | ||
1471 | if (ms->smp.cpus > 1) { | |
1472 | Error *blocker = NULL; | |
1473 | error_setg(&blocker, QERR_REPLAY_NOT_SUPPORTED, "smp"); | |
1474 | replay_add_blocker(blocker); | |
1475 | } | |
1476 | } | |
1477 | ||
1478 | void pc_hot_add_cpu(MachineState *ms, const int64_t id, Error **errp) | |
1479 | { | |
1480 | PCMachineState *pcms = PC_MACHINE(ms); | |
1481 | int64_t apic_id = x86_cpu_apic_id_from_index(pcms, id); | |
1482 | Error *local_err = NULL; | |
1483 | ||
1484 | if (id < 0) { | |
1485 | error_setg(errp, "Invalid CPU id: %" PRIi64, id); | |
1486 | return; | |
1487 | } | |
1488 | ||
1489 | if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) { | |
1490 | error_setg(errp, "Unable to add CPU: %" PRIi64 | |
1491 | ", resulting APIC ID (%" PRIi64 ") is too large", | |
1492 | id, apic_id); | |
1493 | return; | |
1494 | } | |
1495 | ||
1496 | x86_cpu_new(PC_MACHINE(ms), apic_id, &local_err); | |
1497 | if (local_err) { | |
1498 | error_propagate(errp, local_err); | |
1499 | return; | |
1500 | } | |
1501 | } | |
1502 | ||
1503 | void x86_cpus_init(PCMachineState *pcms) | |
1504 | { | |
1505 | int i; | |
1506 | const CPUArchIdList *possible_cpus; | |
1507 | MachineState *ms = MACHINE(pcms); | |
1508 | MachineClass *mc = MACHINE_GET_CLASS(pcms); | |
1509 | PCMachineClass *pcmc = PC_MACHINE_CLASS(mc); | |
1510 | ||
1511 | x86_cpu_set_default_version(pcmc->default_cpu_version); | |
1512 | ||
1513 | /* | |
1514 | * Calculates the limit to CPU APIC ID values | |
1515 | * | |
1516 | * Limit for the APIC ID value, so that all | |
1517 | * CPU APIC IDs are < pcms->apic_id_limit. | |
1518 | * | |
1519 | * This is used for FW_CFG_MAX_CPUS. See comments on fw_cfg_arch_create(). | |
1520 | */ | |
1521 | pcms->apic_id_limit = x86_cpu_apic_id_from_index(pcms, | |
1522 | ms->smp.max_cpus - 1) + 1; | |
1523 | possible_cpus = mc->possible_cpu_arch_ids(ms); | |
1524 | for (i = 0; i < ms->smp.cpus; i++) { | |
1525 | x86_cpu_new(pcms, possible_cpus->cpus[i].arch_id, &error_fatal); | |
1526 | } | |
1527 | } | |
1528 | ||
1529 | static void rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count) | |
1530 | { | |
1531 | if (cpus_count > 0xff) { | |
1532 | /* If the number of CPUs can't be represented in 8 bits, the | |
1533 | * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just | |
1534 | * to make old BIOSes fail more predictably. | |
1535 | */ | |
1536 | rtc_set_memory(rtc, 0x5f, 0); | |
1537 | } else { | |
1538 | rtc_set_memory(rtc, 0x5f, cpus_count - 1); | |
1539 | } | |
1540 | } | |
1541 | ||
1542 | static | |
1543 | void pc_machine_done(Notifier *notifier, void *data) | |
1544 | { | |
1545 | PCMachineState *pcms = container_of(notifier, | |
1546 | PCMachineState, machine_done); | |
1547 | PCIBus *bus = pcms->bus; | |
1548 | ||
1549 | /* set the number of CPUs */ | |
1550 | rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus); | |
1551 | ||
1552 | if (bus) { | |
1553 | int extra_hosts = 0; | |
1554 | ||
1555 | QLIST_FOREACH(bus, &bus->child, sibling) { | |
1556 | /* look for expander root buses */ | |
1557 | if (pci_bus_is_root(bus)) { | |
1558 | extra_hosts++; | |
1559 | } | |
1560 | } | |
1561 | if (extra_hosts && pcms->fw_cfg) { | |
1562 | uint64_t *val = g_malloc(sizeof(*val)); | |
1563 | *val = cpu_to_le64(extra_hosts); | |
1564 | fw_cfg_add_file(pcms->fw_cfg, | |
1565 | "etc/extra-pci-roots", val, sizeof(*val)); | |
1566 | } | |
1567 | } | |
1568 | ||
1569 | acpi_setup(); | |
1570 | if (pcms->fw_cfg) { | |
1571 | fw_cfg_build_smbios(MACHINE(pcms), pcms->fw_cfg); | |
1572 | fw_cfg_build_feature_control(MACHINE(pcms), pcms->fw_cfg); | |
1573 | /* update FW_CFG_NB_CPUS to account for -device added CPUs */ | |
1574 | fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); | |
1575 | } | |
1576 | ||
1577 | if (pcms->apic_id_limit > 255 && !xen_enabled()) { | |
1578 | IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default()); | |
1579 | ||
1580 | if (!iommu || !x86_iommu_ir_supported(X86_IOMMU_DEVICE(iommu)) || | |
1581 | iommu->intr_eim != ON_OFF_AUTO_ON) { | |
1582 | error_report("current -smp configuration requires " | |
1583 | "Extended Interrupt Mode enabled. " | |
1584 | "You can add an IOMMU using: " | |
1585 | "-device intel-iommu,intremap=on,eim=on"); | |
1586 | exit(EXIT_FAILURE); | |
1587 | } | |
1588 | } | |
1589 | } | |
1590 | ||
1591 | void pc_guest_info_init(PCMachineState *pcms) | |
1592 | { | |
1593 | int i; | |
1594 | MachineState *ms = MACHINE(pcms); | |
1595 | ||
1596 | pcms->apic_xrupt_override = kvm_allows_irq0_override(); | |
1597 | pcms->numa_nodes = ms->numa_state->num_nodes; | |
1598 | pcms->node_mem = g_malloc0(pcms->numa_nodes * | |
1599 | sizeof *pcms->node_mem); | |
1600 | for (i = 0; i < ms->numa_state->num_nodes; i++) { | |
1601 | pcms->node_mem[i] = ms->numa_state->nodes[i].node_mem; | |
1602 | } | |
1603 | ||
1604 | pcms->machine_done.notify = pc_machine_done; | |
1605 | qemu_add_machine_init_done_notifier(&pcms->machine_done); | |
1606 | } | |
1607 | ||
1608 | /* setup pci memory address space mapping into system address space */ | |
1609 | void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, | |
1610 | MemoryRegion *pci_address_space) | |
1611 | { | |
1612 | /* Set to lower priority than RAM */ | |
1613 | memory_region_add_subregion_overlap(system_memory, 0x0, | |
1614 | pci_address_space, -1); | |
1615 | } | |
1616 | ||
1617 | void xen_load_linux(PCMachineState *pcms) | |
1618 | { | |
1619 | int i; | |
1620 | FWCfgState *fw_cfg; | |
1621 | ||
1622 | assert(MACHINE(pcms)->kernel_filename != NULL); | |
1623 | ||
1624 | fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE); | |
1625 | fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); | |
1626 | rom_set_fw(fw_cfg); | |
1627 | ||
1628 | x86_load_linux(pcms, fw_cfg); | |
1629 | for (i = 0; i < nb_option_roms; i++) { | |
1630 | assert(!strcmp(option_rom[i].name, "linuxboot.bin") || | |
1631 | !strcmp(option_rom[i].name, "linuxboot_dma.bin") || | |
1632 | !strcmp(option_rom[i].name, "pvh.bin") || | |
1633 | !strcmp(option_rom[i].name, "multiboot.bin")); | |
1634 | rom_add_option(option_rom[i].name, option_rom[i].bootindex); | |
1635 | } | |
1636 | pcms->fw_cfg = fw_cfg; | |
1637 | } | |
1638 | ||
1639 | void pc_memory_init(PCMachineState *pcms, | |
1640 | MemoryRegion *system_memory, | |
1641 | MemoryRegion *rom_memory, | |
1642 | MemoryRegion **ram_memory) | |
1643 | { | |
1644 | int linux_boot, i; | |
1645 | MemoryRegion *ram, *option_rom_mr; | |
1646 | MemoryRegion *ram_below_4g, *ram_above_4g; | |
1647 | FWCfgState *fw_cfg; | |
1648 | MachineState *machine = MACHINE(pcms); | |
1649 | MachineClass *mc = MACHINE_GET_CLASS(machine); | |
1650 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); | |
1651 | ||
1652 | assert(machine->ram_size == pcms->below_4g_mem_size + | |
1653 | pcms->above_4g_mem_size); | |
1654 | ||
1655 | linux_boot = (machine->kernel_filename != NULL); | |
1656 | ||
1657 | /* Allocate RAM. We allocate it as a single memory region and use | |
1658 | * aliases to address portions of it, mostly for backwards compatibility | |
1659 | * with older qemus that used qemu_ram_alloc(). | |
1660 | */ | |
1661 | ram = g_malloc(sizeof(*ram)); | |
1662 | memory_region_allocate_system_memory(ram, NULL, "pc.ram", | |
1663 | machine->ram_size); | |
1664 | *ram_memory = ram; | |
1665 | ram_below_4g = g_malloc(sizeof(*ram_below_4g)); | |
1666 | memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram, | |
1667 | 0, pcms->below_4g_mem_size); | |
1668 | memory_region_add_subregion(system_memory, 0, ram_below_4g); | |
1669 | e820_add_entry(0, pcms->below_4g_mem_size, E820_RAM); | |
1670 | if (pcms->above_4g_mem_size > 0) { | |
1671 | ram_above_4g = g_malloc(sizeof(*ram_above_4g)); | |
1672 | memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram, | |
1673 | pcms->below_4g_mem_size, | |
1674 | pcms->above_4g_mem_size); | |
1675 | memory_region_add_subregion(system_memory, 0x100000000ULL, | |
1676 | ram_above_4g); | |
1677 | e820_add_entry(0x100000000ULL, pcms->above_4g_mem_size, E820_RAM); | |
1678 | } | |
1679 | ||
1680 | if (!pcmc->has_reserved_memory && | |
1681 | (machine->ram_slots || | |
1682 | (machine->maxram_size > machine->ram_size))) { | |
1683 | ||
1684 | error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", | |
1685 | mc->name); | |
1686 | exit(EXIT_FAILURE); | |
1687 | } | |
1688 | ||
1689 | /* always allocate the device memory information */ | |
1690 | machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); | |
1691 | ||
1692 | /* initialize device memory address space */ | |
1693 | if (pcmc->has_reserved_memory && | |
1694 | (machine->ram_size < machine->maxram_size)) { | |
1695 | ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; | |
1696 | ||
1697 | if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { | |
1698 | error_report("unsupported amount of memory slots: %"PRIu64, | |
1699 | machine->ram_slots); | |
1700 | exit(EXIT_FAILURE); | |
1701 | } | |
1702 | ||
1703 | if (QEMU_ALIGN_UP(machine->maxram_size, | |
1704 | TARGET_PAGE_SIZE) != machine->maxram_size) { | |
1705 | error_report("maximum memory size must by aligned to multiple of " | |
1706 | "%d bytes", TARGET_PAGE_SIZE); | |
1707 | exit(EXIT_FAILURE); | |
1708 | } | |
1709 | ||
1710 | machine->device_memory->base = | |
1711 | ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, 1 * GiB); | |
1712 | ||
1713 | if (pcmc->enforce_aligned_dimm) { | |
1714 | /* size device region assuming 1G page max alignment per slot */ | |
1715 | device_mem_size += (1 * GiB) * machine->ram_slots; | |
1716 | } | |
1717 | ||
1718 | if ((machine->device_memory->base + device_mem_size) < | |
1719 | device_mem_size) { | |
1720 | error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, | |
1721 | machine->maxram_size); | |
1722 | exit(EXIT_FAILURE); | |
1723 | } | |
1724 | ||
1725 | memory_region_init(&machine->device_memory->mr, OBJECT(pcms), | |
1726 | "device-memory", device_mem_size); | |
1727 | memory_region_add_subregion(system_memory, machine->device_memory->base, | |
1728 | &machine->device_memory->mr); | |
1729 | } | |
1730 | ||
1731 | /* Initialize PC system firmware */ | |
1732 | pc_system_firmware_init(pcms, rom_memory); | |
1733 | ||
1734 | option_rom_mr = g_malloc(sizeof(*option_rom_mr)); | |
1735 | memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, | |
1736 | &error_fatal); | |
1737 | if (pcmc->pci_enabled) { | |
1738 | memory_region_set_readonly(option_rom_mr, true); | |
1739 | } | |
1740 | memory_region_add_subregion_overlap(rom_memory, | |
1741 | PC_ROM_MIN_VGA, | |
1742 | option_rom_mr, | |
1743 | 1); | |
1744 | ||
1745 | fw_cfg = fw_cfg_arch_create(machine, | |
1746 | pcms->boot_cpus, pcms->apic_id_limit); | |
1747 | ||
1748 | rom_set_fw(fw_cfg); | |
1749 | ||
1750 | if (pcmc->has_reserved_memory && machine->device_memory->base) { | |
1751 | uint64_t *val = g_malloc(sizeof(*val)); | |
1752 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); | |
1753 | uint64_t res_mem_end = machine->device_memory->base; | |
1754 | ||
1755 | if (!pcmc->broken_reserved_end) { | |
1756 | res_mem_end += memory_region_size(&machine->device_memory->mr); | |
1757 | } | |
1758 | *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); | |
1759 | fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); | |
1760 | } | |
1761 | ||
1762 | if (linux_boot) { | |
1763 | x86_load_linux(pcms, fw_cfg); | |
1764 | } | |
1765 | ||
1766 | for (i = 0; i < nb_option_roms; i++) { | |
1767 | rom_add_option(option_rom[i].name, option_rom[i].bootindex); | |
1768 | } | |
1769 | pcms->fw_cfg = fw_cfg; | |
1770 | ||
1771 | /* Init default IOAPIC address space */ | |
1772 | pcms->ioapic_as = &address_space_memory; | |
1773 | ||
1774 | /* Init ACPI memory hotplug IO base address */ | |
1775 | pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE; | |
1776 | } | |
1777 | ||
1778 | /* | |
1779 | * The 64bit pci hole starts after "above 4G RAM" and | |
1780 | * potentially the space reserved for memory hotplug. | |
1781 | */ | |
1782 | uint64_t pc_pci_hole64_start(void) | |
1783 | { | |
1784 | PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); | |
1785 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); | |
1786 | MachineState *ms = MACHINE(pcms); | |
1787 | uint64_t hole64_start = 0; | |
1788 | ||
1789 | if (pcmc->has_reserved_memory && ms->device_memory->base) { | |
1790 | hole64_start = ms->device_memory->base; | |
1791 | if (!pcmc->broken_reserved_end) { | |
1792 | hole64_start += memory_region_size(&ms->device_memory->mr); | |
1793 | } | |
1794 | } else { | |
1795 | hole64_start = 0x100000000ULL + pcms->above_4g_mem_size; | |
1796 | } | |
1797 | ||
1798 | return ROUND_UP(hole64_start, 1 * GiB); | |
1799 | } | |
1800 | ||
1801 | qemu_irq pc_allocate_cpu_irq(void) | |
1802 | { | |
1803 | return qemu_allocate_irq(pic_irq_request, NULL, 0); | |
1804 | } | |
1805 | ||
1806 | DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) | |
1807 | { | |
1808 | DeviceState *dev = NULL; | |
1809 | ||
1810 | rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); | |
1811 | if (pci_bus) { | |
1812 | PCIDevice *pcidev = pci_vga_init(pci_bus); | |
1813 | dev = pcidev ? &pcidev->qdev : NULL; | |
1814 | } else if (isa_bus) { | |
1815 | ISADevice *isadev = isa_vga_init(isa_bus); | |
1816 | dev = isadev ? DEVICE(isadev) : NULL; | |
1817 | } | |
1818 | rom_reset_order_override(); | |
1819 | return dev; | |
1820 | } | |
1821 | ||
1822 | static const MemoryRegionOps ioport80_io_ops = { | |
1823 | .write = ioport80_write, | |
1824 | .read = ioport80_read, | |
1825 | .endianness = DEVICE_NATIVE_ENDIAN, | |
1826 | .impl = { | |
1827 | .min_access_size = 1, | |
1828 | .max_access_size = 1, | |
1829 | }, | |
1830 | }; | |
1831 | ||
1832 | static const MemoryRegionOps ioportF0_io_ops = { | |
1833 | .write = ioportF0_write, | |
1834 | .read = ioportF0_read, | |
1835 | .endianness = DEVICE_NATIVE_ENDIAN, | |
1836 | .impl = { | |
1837 | .min_access_size = 1, | |
1838 | .max_access_size = 1, | |
1839 | }, | |
1840 | }; | |
1841 | ||
1842 | static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport) | |
1843 | { | |
1844 | int i; | |
1845 | DriveInfo *fd[MAX_FD]; | |
1846 | qemu_irq *a20_line; | |
1847 | ISADevice *i8042, *port92, *vmmouse; | |
1848 | ||
1849 | serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); | |
1850 | parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); | |
1851 | ||
1852 | for (i = 0; i < MAX_FD; i++) { | |
1853 | fd[i] = drive_get(IF_FLOPPY, 0, i); | |
1854 | create_fdctrl |= !!fd[i]; | |
1855 | } | |
1856 | if (create_fdctrl) { | |
1857 | fdctrl_init_isa(isa_bus, fd); | |
1858 | } | |
1859 | ||
1860 | i8042 = isa_create_simple(isa_bus, "i8042"); | |
1861 | if (!no_vmport) { | |
1862 | vmport_init(isa_bus); | |
1863 | vmmouse = isa_try_create(isa_bus, "vmmouse"); | |
1864 | } else { | |
1865 | vmmouse = NULL; | |
1866 | } | |
1867 | if (vmmouse) { | |
1868 | DeviceState *dev = DEVICE(vmmouse); | |
1869 | qdev_prop_set_ptr(dev, "ps2_mouse", i8042); | |
1870 | qdev_init_nofail(dev); | |
1871 | } | |
1872 | port92 = isa_create_simple(isa_bus, "port92"); | |
1873 | ||
1874 | a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); | |
1875 | i8042_setup_a20_line(i8042, a20_line[0]); | |
1876 | port92_init(port92, a20_line[1]); | |
1877 | g_free(a20_line); | |
1878 | } | |
1879 | ||
1880 | void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, | |
1881 | ISADevice **rtc_state, | |
1882 | bool create_fdctrl, | |
1883 | bool no_vmport, | |
1884 | bool has_pit, | |
1885 | uint32_t hpet_irqs) | |
1886 | { | |
1887 | int i; | |
1888 | DeviceState *hpet = NULL; | |
1889 | int pit_isa_irq = 0; | |
1890 | qemu_irq pit_alt_irq = NULL; | |
1891 | qemu_irq rtc_irq = NULL; | |
1892 | ISADevice *pit = NULL; | |
1893 | MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); | |
1894 | MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); | |
1895 | ||
1896 | memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); | |
1897 | memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); | |
1898 | ||
1899 | memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); | |
1900 | memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); | |
1901 | ||
1902 | /* | |
1903 | * Check if an HPET shall be created. | |
1904 | * | |
1905 | * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT | |
1906 | * when the HPET wants to take over. Thus we have to disable the latter. | |
1907 | */ | |
1908 | if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) { | |
1909 | /* In order to set property, here not using sysbus_try_create_simple */ | |
1910 | hpet = qdev_try_create(NULL, TYPE_HPET); | |
1911 | if (hpet) { | |
1912 | /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 | |
1913 | * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, | |
1914 | * IRQ8 and IRQ2. | |
1915 | */ | |
1916 | uint8_t compat = object_property_get_uint(OBJECT(hpet), | |
1917 | HPET_INTCAP, NULL); | |
1918 | if (!compat) { | |
1919 | qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); | |
1920 | } | |
1921 | qdev_init_nofail(hpet); | |
1922 | sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); | |
1923 | ||
1924 | for (i = 0; i < GSI_NUM_PINS; i++) { | |
1925 | sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); | |
1926 | } | |
1927 | pit_isa_irq = -1; | |
1928 | pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); | |
1929 | rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); | |
1930 | } | |
1931 | } | |
1932 | *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq); | |
1933 | ||
1934 | qemu_register_boot_set(pc_boot_set, *rtc_state); | |
1935 | ||
1936 | if (!xen_enabled() && has_pit) { | |
1937 | if (kvm_pit_in_kernel()) { | |
1938 | pit = kvm_pit_init(isa_bus, 0x40); | |
1939 | } else { | |
1940 | pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); | |
1941 | } | |
1942 | if (hpet) { | |
1943 | /* connect PIT to output control line of the HPET */ | |
1944 | qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); | |
1945 | } | |
1946 | pcspk_init(isa_bus, pit); | |
1947 | } | |
1948 | ||
1949 | i8257_dma_init(isa_bus, 0); | |
1950 | ||
1951 | /* Super I/O */ | |
1952 | pc_superio_init(isa_bus, create_fdctrl, no_vmport); | |
1953 | } | |
1954 | ||
1955 | void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) | |
1956 | { | |
1957 | int i; | |
1958 | ||
1959 | rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); | |
1960 | for (i = 0; i < nb_nics; i++) { | |
1961 | NICInfo *nd = &nd_table[i]; | |
1962 | const char *model = nd->model ? nd->model : pcmc->default_nic_model; | |
1963 | ||
1964 | if (g_str_equal(model, "ne2k_isa")) { | |
1965 | pc_init_ne2k_isa(isa_bus, nd); | |
1966 | } else { | |
1967 | pci_nic_init_nofail(nd, pci_bus, model, NULL); | |
1968 | } | |
1969 | } | |
1970 | rom_reset_order_override(); | |
1971 | } | |
1972 | ||
1973 | void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) | |
1974 | { | |
1975 | DeviceState *dev; | |
1976 | SysBusDevice *d; | |
1977 | unsigned int i; | |
1978 | ||
1979 | if (kvm_ioapic_in_kernel()) { | |
1980 | dev = qdev_create(NULL, TYPE_KVM_IOAPIC); | |
1981 | } else { | |
1982 | dev = qdev_create(NULL, TYPE_IOAPIC); | |
1983 | } | |
1984 | if (parent_name) { | |
1985 | object_property_add_child(object_resolve_path(parent_name, NULL), | |
1986 | "ioapic", OBJECT(dev), NULL); | |
1987 | } | |
1988 | qdev_init_nofail(dev); | |
1989 | d = SYS_BUS_DEVICE(dev); | |
1990 | sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); | |
1991 | ||
1992 | for (i = 0; i < IOAPIC_NUM_PINS; i++) { | |
1993 | gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); | |
1994 | } | |
1995 | } | |
1996 | ||
1997 | static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, | |
1998 | Error **errp) | |
1999 | { | |
2000 | const PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
2001 | const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); | |
2002 | const MachineState *ms = MACHINE(hotplug_dev); | |
2003 | const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); | |
2004 | const uint64_t legacy_align = TARGET_PAGE_SIZE; | |
2005 | Error *local_err = NULL; | |
2006 | ||
2007 | /* | |
2008 | * When -no-acpi is used with Q35 machine type, no ACPI is built, | |
2009 | * but pcms->acpi_dev is still created. Check !acpi_enabled in | |
2010 | * addition to cover this case. | |
2011 | */ | |
2012 | if (!pcms->acpi_dev || !acpi_enabled) { | |
2013 | error_setg(errp, | |
2014 | "memory hotplug is not enabled: missing acpi device or acpi disabled"); | |
2015 | return; | |
2016 | } | |
2017 | ||
2018 | if (is_nvdimm && !ms->nvdimms_state->is_enabled) { | |
2019 | error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); | |
2020 | return; | |
2021 | } | |
2022 | ||
2023 | hotplug_handler_pre_plug(pcms->acpi_dev, dev, &local_err); | |
2024 | if (local_err) { | |
2025 | error_propagate(errp, local_err); | |
2026 | return; | |
2027 | } | |
2028 | ||
2029 | pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), | |
2030 | pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp); | |
2031 | } | |
2032 | ||
2033 | static void pc_memory_plug(HotplugHandler *hotplug_dev, | |
2034 | DeviceState *dev, Error **errp) | |
2035 | { | |
2036 | Error *local_err = NULL; | |
2037 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
2038 | MachineState *ms = MACHINE(hotplug_dev); | |
2039 | bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); | |
2040 | ||
2041 | pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms), &local_err); | |
2042 | if (local_err) { | |
2043 | goto out; | |
2044 | } | |
2045 | ||
2046 | if (is_nvdimm) { | |
2047 | nvdimm_plug(ms->nvdimms_state); | |
2048 | } | |
2049 | ||
2050 | hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort); | |
2051 | out: | |
2052 | error_propagate(errp, local_err); | |
2053 | } | |
2054 | ||
2055 | static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, | |
2056 | DeviceState *dev, Error **errp) | |
2057 | { | |
2058 | Error *local_err = NULL; | |
2059 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
2060 | ||
2061 | /* | |
2062 | * When -no-acpi is used with Q35 machine type, no ACPI is built, | |
2063 | * but pcms->acpi_dev is still created. Check !acpi_enabled in | |
2064 | * addition to cover this case. | |
2065 | */ | |
2066 | if (!pcms->acpi_dev || !acpi_enabled) { | |
2067 | error_setg(&local_err, | |
2068 | "memory hotplug is not enabled: missing acpi device or acpi disabled"); | |
2069 | goto out; | |
2070 | } | |
2071 | ||
2072 | if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { | |
2073 | error_setg(&local_err, | |
2074 | "nvdimm device hot unplug is not supported yet."); | |
2075 | goto out; | |
2076 | } | |
2077 | ||
2078 | hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, | |
2079 | &local_err); | |
2080 | out: | |
2081 | error_propagate(errp, local_err); | |
2082 | } | |
2083 | ||
2084 | static void pc_memory_unplug(HotplugHandler *hotplug_dev, | |
2085 | DeviceState *dev, Error **errp) | |
2086 | { | |
2087 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
2088 | Error *local_err = NULL; | |
2089 | ||
2090 | hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); | |
2091 | if (local_err) { | |
2092 | goto out; | |
2093 | } | |
2094 | ||
2095 | pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); | |
2096 | object_property_set_bool(OBJECT(dev), false, "realized", NULL); | |
2097 | out: | |
2098 | error_propagate(errp, local_err); | |
2099 | } | |
2100 | ||
2101 | static int pc_apic_cmp(const void *a, const void *b) | |
2102 | { | |
2103 | CPUArchId *apic_a = (CPUArchId *)a; | |
2104 | CPUArchId *apic_b = (CPUArchId *)b; | |
2105 | ||
2106 | return apic_a->arch_id - apic_b->arch_id; | |
2107 | } | |
2108 | ||
2109 | /* returns pointer to CPUArchId descriptor that matches CPU's apic_id | |
2110 | * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no | |
2111 | * entry corresponding to CPU's apic_id returns NULL. | |
2112 | */ | |
2113 | static CPUArchId *pc_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) | |
2114 | { | |
2115 | CPUArchId apic_id, *found_cpu; | |
2116 | ||
2117 | apic_id.arch_id = id; | |
2118 | found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus, | |
2119 | ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus), | |
2120 | pc_apic_cmp); | |
2121 | if (found_cpu && idx) { | |
2122 | *idx = found_cpu - ms->possible_cpus->cpus; | |
2123 | } | |
2124 | return found_cpu; | |
2125 | } | |
2126 | ||
2127 | static void pc_cpu_plug(HotplugHandler *hotplug_dev, | |
2128 | DeviceState *dev, Error **errp) | |
2129 | { | |
2130 | CPUArchId *found_cpu; | |
2131 | Error *local_err = NULL; | |
2132 | X86CPU *cpu = X86_CPU(dev); | |
2133 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
2134 | ||
2135 | if (pcms->acpi_dev) { | |
2136 | hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); | |
2137 | if (local_err) { | |
2138 | goto out; | |
2139 | } | |
2140 | } | |
2141 | ||
2142 | /* increment the number of CPUs */ | |
2143 | pcms->boot_cpus++; | |
2144 | if (pcms->rtc) { | |
2145 | rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus); | |
2146 | } | |
2147 | if (pcms->fw_cfg) { | |
2148 | fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); | |
2149 | } | |
2150 | ||
2151 | found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL); | |
2152 | found_cpu->cpu = OBJECT(dev); | |
2153 | out: | |
2154 | error_propagate(errp, local_err); | |
2155 | } | |
2156 | static void pc_cpu_unplug_request_cb(HotplugHandler *hotplug_dev, | |
2157 | DeviceState *dev, Error **errp) | |
2158 | { | |
2159 | int idx = -1; | |
2160 | Error *local_err = NULL; | |
2161 | X86CPU *cpu = X86_CPU(dev); | |
2162 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
2163 | ||
2164 | if (!pcms->acpi_dev) { | |
2165 | error_setg(&local_err, "CPU hot unplug not supported without ACPI"); | |
2166 | goto out; | |
2167 | } | |
2168 | ||
2169 | pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx); | |
2170 | assert(idx != -1); | |
2171 | if (idx == 0) { | |
2172 | error_setg(&local_err, "Boot CPU is unpluggable"); | |
2173 | goto out; | |
2174 | } | |
2175 | ||
2176 | hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, | |
2177 | &local_err); | |
2178 | if (local_err) { | |
2179 | goto out; | |
2180 | } | |
2181 | ||
2182 | out: | |
2183 | error_propagate(errp, local_err); | |
2184 | ||
2185 | } | |
2186 | ||
2187 | static void pc_cpu_unplug_cb(HotplugHandler *hotplug_dev, | |
2188 | DeviceState *dev, Error **errp) | |
2189 | { | |
2190 | CPUArchId *found_cpu; | |
2191 | Error *local_err = NULL; | |
2192 | X86CPU *cpu = X86_CPU(dev); | |
2193 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
2194 | ||
2195 | hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); | |
2196 | if (local_err) { | |
2197 | goto out; | |
2198 | } | |
2199 | ||
2200 | found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL); | |
2201 | found_cpu->cpu = NULL; | |
2202 | object_property_set_bool(OBJECT(dev), false, "realized", NULL); | |
2203 | ||
2204 | /* decrement the number of CPUs */ | |
2205 | pcms->boot_cpus--; | |
2206 | /* Update the number of CPUs in CMOS */ | |
2207 | rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus); | |
2208 | fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); | |
2209 | out: | |
2210 | error_propagate(errp, local_err); | |
2211 | } | |
2212 | ||
2213 | static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, | |
2214 | DeviceState *dev, Error **errp) | |
2215 | { | |
2216 | int idx; | |
2217 | CPUState *cs; | |
2218 | CPUArchId *cpu_slot; | |
2219 | X86CPUTopoInfo topo; | |
2220 | X86CPU *cpu = X86_CPU(dev); | |
2221 | CPUX86State *env = &cpu->env; | |
2222 | MachineState *ms = MACHINE(hotplug_dev); | |
2223 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
2224 | unsigned int smp_cores = ms->smp.cores; | |
2225 | unsigned int smp_threads = ms->smp.threads; | |
2226 | ||
2227 | if(!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) { | |
2228 | error_setg(errp, "Invalid CPU type, expected cpu type: '%s'", | |
2229 | ms->cpu_type); | |
2230 | return; | |
2231 | } | |
2232 | ||
2233 | env->nr_dies = pcms->smp_dies; | |
2234 | ||
2235 | /* | |
2236 | * If APIC ID is not set, | |
2237 | * set it based on socket/die/core/thread properties. | |
2238 | */ | |
2239 | if (cpu->apic_id == UNASSIGNED_APIC_ID) { | |
2240 | int max_socket = (ms->smp.max_cpus - 1) / | |
2241 | smp_threads / smp_cores / pcms->smp_dies; | |
2242 | ||
2243 | /* | |
2244 | * die-id was optional in QEMU 4.0 and older, so keep it optional | |
2245 | * if there's only one die per socket. | |
2246 | */ | |
2247 | if (cpu->die_id < 0 && pcms->smp_dies == 1) { | |
2248 | cpu->die_id = 0; | |
2249 | } | |
2250 | ||
2251 | if (cpu->socket_id < 0) { | |
2252 | error_setg(errp, "CPU socket-id is not set"); | |
2253 | return; | |
2254 | } else if (cpu->socket_id > max_socket) { | |
2255 | error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u", | |
2256 | cpu->socket_id, max_socket); | |
2257 | return; | |
2258 | } | |
2259 | if (cpu->die_id < 0) { | |
2260 | error_setg(errp, "CPU die-id is not set"); | |
2261 | return; | |
2262 | } else if (cpu->die_id > pcms->smp_dies - 1) { | |
2263 | error_setg(errp, "Invalid CPU die-id: %u must be in range 0:%u", | |
2264 | cpu->die_id, pcms->smp_dies - 1); | |
2265 | return; | |
2266 | } | |
2267 | if (cpu->core_id < 0) { | |
2268 | error_setg(errp, "CPU core-id is not set"); | |
2269 | return; | |
2270 | } else if (cpu->core_id > (smp_cores - 1)) { | |
2271 | error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u", | |
2272 | cpu->core_id, smp_cores - 1); | |
2273 | return; | |
2274 | } | |
2275 | if (cpu->thread_id < 0) { | |
2276 | error_setg(errp, "CPU thread-id is not set"); | |
2277 | return; | |
2278 | } else if (cpu->thread_id > (smp_threads - 1)) { | |
2279 | error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u", | |
2280 | cpu->thread_id, smp_threads - 1); | |
2281 | return; | |
2282 | } | |
2283 | ||
2284 | topo.pkg_id = cpu->socket_id; | |
2285 | topo.die_id = cpu->die_id; | |
2286 | topo.core_id = cpu->core_id; | |
2287 | topo.smt_id = cpu->thread_id; | |
2288 | cpu->apic_id = apicid_from_topo_ids(pcms->smp_dies, smp_cores, | |
2289 | smp_threads, &topo); | |
2290 | } | |
2291 | ||
2292 | cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx); | |
2293 | if (!cpu_slot) { | |
2294 | MachineState *ms = MACHINE(pcms); | |
2295 | ||
2296 | x86_topo_ids_from_apicid(cpu->apic_id, pcms->smp_dies, | |
2297 | smp_cores, smp_threads, &topo); | |
2298 | error_setg(errp, | |
2299 | "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with" | |
2300 | " APIC ID %" PRIu32 ", valid index range 0:%d", | |
2301 | topo.pkg_id, topo.die_id, topo.core_id, topo.smt_id, | |
2302 | cpu->apic_id, ms->possible_cpus->len - 1); | |
2303 | return; | |
2304 | } | |
2305 | ||
2306 | if (cpu_slot->cpu) { | |
2307 | error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists", | |
2308 | idx, cpu->apic_id); | |
2309 | return; | |
2310 | } | |
2311 | ||
2312 | /* if 'address' properties socket-id/core-id/thread-id are not set, set them | |
2313 | * so that machine_query_hotpluggable_cpus would show correct values | |
2314 | */ | |
2315 | /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn() | |
2316 | * once -smp refactoring is complete and there will be CPU private | |
2317 | * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */ | |
2318 | x86_topo_ids_from_apicid(cpu->apic_id, pcms->smp_dies, | |
2319 | smp_cores, smp_threads, &topo); | |
2320 | if (cpu->socket_id != -1 && cpu->socket_id != topo.pkg_id) { | |
2321 | error_setg(errp, "property socket-id: %u doesn't match set apic-id:" | |
2322 | " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo.pkg_id); | |
2323 | return; | |
2324 | } | |
2325 | cpu->socket_id = topo.pkg_id; | |
2326 | ||
2327 | if (cpu->die_id != -1 && cpu->die_id != topo.die_id) { | |
2328 | error_setg(errp, "property die-id: %u doesn't match set apic-id:" | |
2329 | " 0x%x (die-id: %u)", cpu->die_id, cpu->apic_id, topo.die_id); | |
2330 | return; | |
2331 | } | |
2332 | cpu->die_id = topo.die_id; | |
2333 | ||
2334 | if (cpu->core_id != -1 && cpu->core_id != topo.core_id) { | |
2335 | error_setg(errp, "property core-id: %u doesn't match set apic-id:" | |
2336 | " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo.core_id); | |
2337 | return; | |
2338 | } | |
2339 | cpu->core_id = topo.core_id; | |
2340 | ||
2341 | if (cpu->thread_id != -1 && cpu->thread_id != topo.smt_id) { | |
2342 | error_setg(errp, "property thread-id: %u doesn't match set apic-id:" | |
2343 | " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, topo.smt_id); | |
2344 | return; | |
2345 | } | |
2346 | cpu->thread_id = topo.smt_id; | |
2347 | ||
2348 | if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && | |
2349 | !kvm_hv_vpindex_settable()) { | |
2350 | error_setg(errp, "kernel doesn't allow setting HyperV VP_INDEX"); | |
2351 | return; | |
2352 | } | |
2353 | ||
2354 | cs = CPU(cpu); | |
2355 | cs->cpu_index = idx; | |
2356 | ||
2357 | numa_cpu_pre_plug(cpu_slot, dev, errp); | |
2358 | } | |
2359 | ||
2360 | static void pc_virtio_pmem_pci_pre_plug(HotplugHandler *hotplug_dev, | |
2361 | DeviceState *dev, Error **errp) | |
2362 | { | |
2363 | HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); | |
2364 | Error *local_err = NULL; | |
2365 | ||
2366 | if (!hotplug_dev2) { | |
2367 | /* | |
2368 | * Without a bus hotplug handler, we cannot control the plug/unplug | |
2369 | * order. This should never be the case on x86, however better add | |
2370 | * a safety net. | |
2371 | */ | |
2372 | error_setg(errp, "virtio-pmem-pci not supported on this bus."); | |
2373 | return; | |
2374 | } | |
2375 | /* | |
2376 | * First, see if we can plug this memory device at all. If that | |
2377 | * succeeds, branch of to the actual hotplug handler. | |
2378 | */ | |
2379 | memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL, | |
2380 | &local_err); | |
2381 | if (!local_err) { | |
2382 | hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err); | |
2383 | } | |
2384 | error_propagate(errp, local_err); | |
2385 | } | |
2386 | ||
2387 | static void pc_virtio_pmem_pci_plug(HotplugHandler *hotplug_dev, | |
2388 | DeviceState *dev, Error **errp) | |
2389 | { | |
2390 | HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); | |
2391 | Error *local_err = NULL; | |
2392 | ||
2393 | /* | |
2394 | * Plug the memory device first and then branch off to the actual | |
2395 | * hotplug handler. If that one fails, we can easily undo the memory | |
2396 | * device bits. | |
2397 | */ | |
2398 | memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); | |
2399 | hotplug_handler_plug(hotplug_dev2, dev, &local_err); | |
2400 | if (local_err) { | |
2401 | memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); | |
2402 | } | |
2403 | error_propagate(errp, local_err); | |
2404 | } | |
2405 | ||
2406 | static void pc_virtio_pmem_pci_unplug_request(HotplugHandler *hotplug_dev, | |
2407 | DeviceState *dev, Error **errp) | |
2408 | { | |
2409 | /* We don't support virtio pmem hot unplug */ | |
2410 | error_setg(errp, "virtio pmem device unplug not supported."); | |
2411 | } | |
2412 | ||
2413 | static void pc_virtio_pmem_pci_unplug(HotplugHandler *hotplug_dev, | |
2414 | DeviceState *dev, Error **errp) | |
2415 | { | |
2416 | /* We don't support virtio pmem hot unplug */ | |
2417 | } | |
2418 | ||
2419 | static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, | |
2420 | DeviceState *dev, Error **errp) | |
2421 | { | |
2422 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { | |
2423 | pc_memory_pre_plug(hotplug_dev, dev, errp); | |
2424 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { | |
2425 | pc_cpu_pre_plug(hotplug_dev, dev, errp); | |
2426 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { | |
2427 | pc_virtio_pmem_pci_pre_plug(hotplug_dev, dev, errp); | |
2428 | } | |
2429 | } | |
2430 | ||
2431 | static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, | |
2432 | DeviceState *dev, Error **errp) | |
2433 | { | |
2434 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { | |
2435 | pc_memory_plug(hotplug_dev, dev, errp); | |
2436 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { | |
2437 | pc_cpu_plug(hotplug_dev, dev, errp); | |
2438 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { | |
2439 | pc_virtio_pmem_pci_plug(hotplug_dev, dev, errp); | |
2440 | } | |
2441 | } | |
2442 | ||
2443 | static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, | |
2444 | DeviceState *dev, Error **errp) | |
2445 | { | |
2446 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { | |
2447 | pc_memory_unplug_request(hotplug_dev, dev, errp); | |
2448 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { | |
2449 | pc_cpu_unplug_request_cb(hotplug_dev, dev, errp); | |
2450 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { | |
2451 | pc_virtio_pmem_pci_unplug_request(hotplug_dev, dev, errp); | |
2452 | } else { | |
2453 | error_setg(errp, "acpi: device unplug request for not supported device" | |
2454 | " type: %s", object_get_typename(OBJECT(dev))); | |
2455 | } | |
2456 | } | |
2457 | ||
2458 | static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, | |
2459 | DeviceState *dev, Error **errp) | |
2460 | { | |
2461 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { | |
2462 | pc_memory_unplug(hotplug_dev, dev, errp); | |
2463 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { | |
2464 | pc_cpu_unplug_cb(hotplug_dev, dev, errp); | |
2465 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { | |
2466 | pc_virtio_pmem_pci_unplug(hotplug_dev, dev, errp); | |
2467 | } else { | |
2468 | error_setg(errp, "acpi: device unplug for not supported device" | |
2469 | " type: %s", object_get_typename(OBJECT(dev))); | |
2470 | } | |
2471 | } | |
2472 | ||
2473 | static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, | |
2474 | DeviceState *dev) | |
2475 | { | |
2476 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || | |
2477 | object_dynamic_cast(OBJECT(dev), TYPE_CPU) || | |
2478 | object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { | |
2479 | return HOTPLUG_HANDLER(machine); | |
2480 | } | |
2481 | ||
2482 | return NULL; | |
2483 | } | |
2484 | ||
2485 | static void | |
2486 | pc_machine_get_device_memory_region_size(Object *obj, Visitor *v, | |
2487 | const char *name, void *opaque, | |
2488 | Error **errp) | |
2489 | { | |
2490 | MachineState *ms = MACHINE(obj); | |
2491 | int64_t value = 0; | |
2492 | ||
2493 | if (ms->device_memory) { | |
2494 | value = memory_region_size(&ms->device_memory->mr); | |
2495 | } | |
2496 | ||
2497 | visit_type_int(v, name, &value, errp); | |
2498 | } | |
2499 | ||
2500 | static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, | |
2501 | const char *name, void *opaque, | |
2502 | Error **errp) | |
2503 | { | |
2504 | PCMachineState *pcms = PC_MACHINE(obj); | |
2505 | uint64_t value = pcms->max_ram_below_4g; | |
2506 | ||
2507 | visit_type_size(v, name, &value, errp); | |
2508 | } | |
2509 | ||
2510 | static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, | |
2511 | const char *name, void *opaque, | |
2512 | Error **errp) | |
2513 | { | |
2514 | PCMachineState *pcms = PC_MACHINE(obj); | |
2515 | Error *error = NULL; | |
2516 | uint64_t value; | |
2517 | ||
2518 | visit_type_size(v, name, &value, &error); | |
2519 | if (error) { | |
2520 | error_propagate(errp, error); | |
2521 | return; | |
2522 | } | |
2523 | if (value > 4 * GiB) { | |
2524 | error_setg(&error, | |
2525 | "Machine option 'max-ram-below-4g=%"PRIu64 | |
2526 | "' expects size less than or equal to 4G", value); | |
2527 | error_propagate(errp, error); | |
2528 | return; | |
2529 | } | |
2530 | ||
2531 | if (value < 1 * MiB) { | |
2532 | warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," | |
2533 | "BIOS may not work with less than 1MiB", value); | |
2534 | } | |
2535 | ||
2536 | pcms->max_ram_below_4g = value; | |
2537 | } | |
2538 | ||
2539 | static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, | |
2540 | void *opaque, Error **errp) | |
2541 | { | |
2542 | PCMachineState *pcms = PC_MACHINE(obj); | |
2543 | OnOffAuto vmport = pcms->vmport; | |
2544 | ||
2545 | visit_type_OnOffAuto(v, name, &vmport, errp); | |
2546 | } | |
2547 | ||
2548 | static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, | |
2549 | void *opaque, Error **errp) | |
2550 | { | |
2551 | PCMachineState *pcms = PC_MACHINE(obj); | |
2552 | ||
2553 | visit_type_OnOffAuto(v, name, &pcms->vmport, errp); | |
2554 | } | |
2555 | ||
2556 | bool pc_machine_is_smm_enabled(PCMachineState *pcms) | |
2557 | { | |
2558 | bool smm_available = false; | |
2559 | ||
2560 | if (pcms->smm == ON_OFF_AUTO_OFF) { | |
2561 | return false; | |
2562 | } | |
2563 | ||
2564 | if (tcg_enabled() || qtest_enabled()) { | |
2565 | smm_available = true; | |
2566 | } else if (kvm_enabled()) { | |
2567 | smm_available = kvm_has_smm(); | |
2568 | } | |
2569 | ||
2570 | if (smm_available) { | |
2571 | return true; | |
2572 | } | |
2573 | ||
2574 | if (pcms->smm == ON_OFF_AUTO_ON) { | |
2575 | error_report("System Management Mode not supported by this hypervisor."); | |
2576 | exit(1); | |
2577 | } | |
2578 | return false; | |
2579 | } | |
2580 | ||
2581 | static void pc_machine_get_smm(Object *obj, Visitor *v, const char *name, | |
2582 | void *opaque, Error **errp) | |
2583 | { | |
2584 | PCMachineState *pcms = PC_MACHINE(obj); | |
2585 | OnOffAuto smm = pcms->smm; | |
2586 | ||
2587 | visit_type_OnOffAuto(v, name, &smm, errp); | |
2588 | } | |
2589 | ||
2590 | static void pc_machine_set_smm(Object *obj, Visitor *v, const char *name, | |
2591 | void *opaque, Error **errp) | |
2592 | { | |
2593 | PCMachineState *pcms = PC_MACHINE(obj); | |
2594 | ||
2595 | visit_type_OnOffAuto(v, name, &pcms->smm, errp); | |
2596 | } | |
2597 | ||
2598 | static bool pc_machine_get_smbus(Object *obj, Error **errp) | |
2599 | { | |
2600 | PCMachineState *pcms = PC_MACHINE(obj); | |
2601 | ||
2602 | return pcms->smbus_enabled; | |
2603 | } | |
2604 | ||
2605 | static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) | |
2606 | { | |
2607 | PCMachineState *pcms = PC_MACHINE(obj); | |
2608 | ||
2609 | pcms->smbus_enabled = value; | |
2610 | } | |
2611 | ||
2612 | static bool pc_machine_get_sata(Object *obj, Error **errp) | |
2613 | { | |
2614 | PCMachineState *pcms = PC_MACHINE(obj); | |
2615 | ||
2616 | return pcms->sata_enabled; | |
2617 | } | |
2618 | ||
2619 | static void pc_machine_set_sata(Object *obj, bool value, Error **errp) | |
2620 | { | |
2621 | PCMachineState *pcms = PC_MACHINE(obj); | |
2622 | ||
2623 | pcms->sata_enabled = value; | |
2624 | } | |
2625 | ||
2626 | static bool pc_machine_get_pit(Object *obj, Error **errp) | |
2627 | { | |
2628 | PCMachineState *pcms = PC_MACHINE(obj); | |
2629 | ||
2630 | return pcms->pit_enabled; | |
2631 | } | |
2632 | ||
2633 | static void pc_machine_set_pit(Object *obj, bool value, Error **errp) | |
2634 | { | |
2635 | PCMachineState *pcms = PC_MACHINE(obj); | |
2636 | ||
2637 | pcms->pit_enabled = value; | |
2638 | } | |
2639 | ||
2640 | static void pc_machine_initfn(Object *obj) | |
2641 | { | |
2642 | PCMachineState *pcms = PC_MACHINE(obj); | |
2643 | ||
2644 | pcms->max_ram_below_4g = 0; /* use default */ | |
2645 | pcms->smm = ON_OFF_AUTO_AUTO; | |
2646 | #ifdef CONFIG_VMPORT | |
2647 | pcms->vmport = ON_OFF_AUTO_AUTO; | |
2648 | #else | |
2649 | pcms->vmport = ON_OFF_AUTO_OFF; | |
2650 | #endif /* CONFIG_VMPORT */ | |
2651 | /* acpi build is enabled by default if machine supports it */ | |
2652 | pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build; | |
2653 | pcms->smbus_enabled = true; | |
2654 | pcms->sata_enabled = true; | |
2655 | pcms->pit_enabled = true; | |
2656 | pcms->smp_dies = 1; | |
2657 | ||
2658 | pc_system_flash_create(pcms); | |
2659 | } | |
2660 | ||
2661 | static void pc_machine_reset(MachineState *machine) | |
2662 | { | |
2663 | CPUState *cs; | |
2664 | X86CPU *cpu; | |
2665 | ||
2666 | qemu_devices_reset(); | |
2667 | ||
2668 | /* Reset APIC after devices have been reset to cancel | |
2669 | * any changes that qemu_devices_reset() might have done. | |
2670 | */ | |
2671 | CPU_FOREACH(cs) { | |
2672 | cpu = X86_CPU(cs); | |
2673 | ||
2674 | if (cpu->apic_state) { | |
2675 | device_reset(cpu->apic_state); | |
2676 | } | |
2677 | } | |
2678 | } | |
2679 | ||
2680 | static void pc_machine_wakeup(MachineState *machine) | |
2681 | { | |
2682 | cpu_synchronize_all_states(); | |
2683 | pc_machine_reset(machine); | |
2684 | cpu_synchronize_all_post_reset(); | |
2685 | } | |
2686 | ||
2687 | static CpuInstanceProperties | |
2688 | x86_cpu_index_to_props(MachineState *ms, unsigned cpu_index) | |
2689 | { | |
2690 | MachineClass *mc = MACHINE_GET_CLASS(ms); | |
2691 | const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); | |
2692 | ||
2693 | assert(cpu_index < possible_cpus->len); | |
2694 | return possible_cpus->cpus[cpu_index].props; | |
2695 | } | |
2696 | ||
2697 | static int64_t x86_get_default_cpu_node_id(const MachineState *ms, int idx) | |
2698 | { | |
2699 | X86CPUTopoInfo topo; | |
2700 | PCMachineState *pcms = PC_MACHINE(ms); | |
2701 | ||
2702 | assert(idx < ms->possible_cpus->len); | |
2703 | x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id, | |
2704 | pcms->smp_dies, ms->smp.cores, | |
2705 | ms->smp.threads, &topo); | |
2706 | return topo.pkg_id % ms->numa_state->num_nodes; | |
2707 | } | |
2708 | ||
2709 | static const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms) | |
2710 | { | |
2711 | PCMachineState *pcms = PC_MACHINE(ms); | |
2712 | int i; | |
2713 | unsigned int max_cpus = ms->smp.max_cpus; | |
2714 | ||
2715 | if (ms->possible_cpus) { | |
2716 | /* | |
2717 | * make sure that max_cpus hasn't changed since the first use, i.e. | |
2718 | * -smp hasn't been parsed after it | |
2719 | */ | |
2720 | assert(ms->possible_cpus->len == max_cpus); | |
2721 | return ms->possible_cpus; | |
2722 | } | |
2723 | ||
2724 | ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + | |
2725 | sizeof(CPUArchId) * max_cpus); | |
2726 | ms->possible_cpus->len = max_cpus; | |
2727 | for (i = 0; i < ms->possible_cpus->len; i++) { | |
2728 | X86CPUTopoInfo topo; | |
2729 | ||
2730 | ms->possible_cpus->cpus[i].type = ms->cpu_type; | |
2731 | ms->possible_cpus->cpus[i].vcpus_count = 1; | |
2732 | ms->possible_cpus->cpus[i].arch_id = | |
2733 | x86_cpu_apic_id_from_index(pcms, i); | |
2734 | x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id, | |
2735 | pcms->smp_dies, ms->smp.cores, | |
2736 | ms->smp.threads, &topo); | |
2737 | ms->possible_cpus->cpus[i].props.has_socket_id = true; | |
2738 | ms->possible_cpus->cpus[i].props.socket_id = topo.pkg_id; | |
2739 | if (pcms->smp_dies > 1) { | |
2740 | ms->possible_cpus->cpus[i].props.has_die_id = true; | |
2741 | ms->possible_cpus->cpus[i].props.die_id = topo.die_id; | |
2742 | } | |
2743 | ms->possible_cpus->cpus[i].props.has_core_id = true; | |
2744 | ms->possible_cpus->cpus[i].props.core_id = topo.core_id; | |
2745 | ms->possible_cpus->cpus[i].props.has_thread_id = true; | |
2746 | ms->possible_cpus->cpus[i].props.thread_id = topo.smt_id; | |
2747 | } | |
2748 | return ms->possible_cpus; | |
2749 | } | |
2750 | ||
2751 | static void x86_nmi(NMIState *n, int cpu_index, Error **errp) | |
2752 | { | |
2753 | /* cpu index isn't used */ | |
2754 | CPUState *cs; | |
2755 | ||
2756 | CPU_FOREACH(cs) { | |
2757 | X86CPU *cpu = X86_CPU(cs); | |
2758 | ||
2759 | if (!cpu->apic_state) { | |
2760 | cpu_interrupt(cs, CPU_INTERRUPT_NMI); | |
2761 | } else { | |
2762 | apic_deliver_nmi(cpu->apic_state); | |
2763 | } | |
2764 | } | |
2765 | } | |
2766 | ||
2767 | ||
2768 | static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp) | |
2769 | { | |
2770 | X86IOMMUState *iommu = x86_iommu_get_default(); | |
2771 | IntelIOMMUState *intel_iommu; | |
2772 | ||
2773 | if (iommu && | |
2774 | object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) && | |
2775 | object_dynamic_cast((Object *)dev, "vfio-pci")) { | |
2776 | intel_iommu = INTEL_IOMMU_DEVICE(iommu); | |
2777 | if (!intel_iommu->caching_mode) { | |
2778 | error_setg(errp, "Device assignment is not allowed without " | |
2779 | "enabling caching-mode=on for Intel IOMMU."); | |
2780 | return false; | |
2781 | } | |
2782 | } | |
2783 | ||
2784 | return true; | |
2785 | } | |
2786 | ||
2787 | static void pc_machine_class_init(ObjectClass *oc, void *data) | |
2788 | { | |
2789 | MachineClass *mc = MACHINE_CLASS(oc); | |
2790 | PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); | |
2791 | HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); | |
2792 | NMIClass *nc = NMI_CLASS(oc); | |
2793 | ||
2794 | pcmc->pci_enabled = true; | |
2795 | pcmc->has_acpi_build = true; | |
2796 | pcmc->rsdp_in_ram = true; | |
2797 | pcmc->smbios_defaults = true; | |
2798 | pcmc->smbios_uuid_encoded = true; | |
2799 | pcmc->gigabyte_align = true; | |
2800 | pcmc->has_reserved_memory = true; | |
2801 | pcmc->kvmclock_enabled = true; | |
2802 | pcmc->enforce_aligned_dimm = true; | |
2803 | /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported | |
2804 | * to be used at the moment, 32K should be enough for a while. */ | |
2805 | pcmc->acpi_data_size = 0x20000 + 0x8000; | |
2806 | pcmc->save_tsc_khz = true; | |
2807 | pcmc->linuxboot_dma_enabled = true; | |
2808 | pcmc->pvh_enabled = true; | |
2809 | assert(!mc->get_hotplug_handler); | |
2810 | mc->get_hotplug_handler = pc_get_hotplug_handler; | |
2811 | mc->hotplug_allowed = pc_hotplug_allowed; | |
2812 | mc->cpu_index_to_instance_props = x86_cpu_index_to_props; | |
2813 | mc->get_default_cpu_node_id = x86_get_default_cpu_node_id; | |
2814 | mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids; | |
2815 | mc->auto_enable_numa_with_memhp = true; | |
2816 | mc->has_hotpluggable_cpus = true; | |
2817 | mc->default_boot_order = "cad"; | |
2818 | mc->hot_add_cpu = pc_hot_add_cpu; | |
2819 | mc->smp_parse = pc_smp_parse; | |
2820 | mc->block_default_type = IF_IDE; | |
2821 | mc->max_cpus = 255; | |
2822 | mc->reset = pc_machine_reset; | |
2823 | mc->wakeup = pc_machine_wakeup; | |
2824 | hc->pre_plug = pc_machine_device_pre_plug_cb; | |
2825 | hc->plug = pc_machine_device_plug_cb; | |
2826 | hc->unplug_request = pc_machine_device_unplug_request_cb; | |
2827 | hc->unplug = pc_machine_device_unplug_cb; | |
2828 | nc->nmi_monitor_handler = x86_nmi; | |
2829 | mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; | |
2830 | mc->nvdimm_supported = true; | |
2831 | mc->numa_mem_supported = true; | |
2832 | ||
2833 | object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int", | |
2834 | pc_machine_get_device_memory_region_size, NULL, | |
2835 | NULL, NULL, &error_abort); | |
2836 | ||
2837 | object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", | |
2838 | pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, | |
2839 | NULL, NULL, &error_abort); | |
2840 | ||
2841 | object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, | |
2842 | "Maximum ram below the 4G boundary (32bit boundary)", &error_abort); | |
2843 | ||
2844 | object_class_property_add(oc, PC_MACHINE_SMM, "OnOffAuto", | |
2845 | pc_machine_get_smm, pc_machine_set_smm, | |
2846 | NULL, NULL, &error_abort); | |
2847 | object_class_property_set_description(oc, PC_MACHINE_SMM, | |
2848 | "Enable SMM (pc & q35)", &error_abort); | |
2849 | ||
2850 | object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", | |
2851 | pc_machine_get_vmport, pc_machine_set_vmport, | |
2852 | NULL, NULL, &error_abort); | |
2853 | object_class_property_set_description(oc, PC_MACHINE_VMPORT, | |
2854 | "Enable vmport (pc & q35)", &error_abort); | |
2855 | ||
2856 | object_class_property_add_bool(oc, PC_MACHINE_SMBUS, | |
2857 | pc_machine_get_smbus, pc_machine_set_smbus, &error_abort); | |
2858 | ||
2859 | object_class_property_add_bool(oc, PC_MACHINE_SATA, | |
2860 | pc_machine_get_sata, pc_machine_set_sata, &error_abort); | |
2861 | ||
2862 | object_class_property_add_bool(oc, PC_MACHINE_PIT, | |
2863 | pc_machine_get_pit, pc_machine_set_pit, &error_abort); | |
2864 | } | |
2865 | ||
2866 | static const TypeInfo pc_machine_info = { | |
2867 | .name = TYPE_PC_MACHINE, | |
2868 | .parent = TYPE_MACHINE, | |
2869 | .abstract = true, | |
2870 | .instance_size = sizeof(PCMachineState), | |
2871 | .instance_init = pc_machine_initfn, | |
2872 | .class_size = sizeof(PCMachineClass), | |
2873 | .class_init = pc_machine_class_init, | |
2874 | .interfaces = (InterfaceInfo[]) { | |
2875 | { TYPE_HOTPLUG_HANDLER }, | |
2876 | { TYPE_NMI }, | |
2877 | { } | |
2878 | }, | |
2879 | }; | |
2880 | ||
2881 | static void pc_machine_register_types(void) | |
2882 | { | |
2883 | type_register_static(&pc_machine_info); | |
2884 | } | |
2885 | ||
2886 | type_init(pc_machine_register_types) |