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1 | /* | |
2 | * QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms | |
3 | * | |
4 | * Copyright (c) 2003-2005, 2007 Jocelyn Mayer | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | #include "hw.h" | |
25 | #include "nvram.h" | |
26 | #include "qemu-timer.h" | |
27 | #include "sysemu.h" | |
28 | #include "sysbus.h" | |
29 | #include "isa.h" | |
30 | #include "exec/address-spaces.h" | |
31 | ||
32 | //#define DEBUG_NVRAM | |
33 | ||
34 | #if defined(DEBUG_NVRAM) | |
35 | #define NVRAM_PRINTF(fmt, ...) do { printf(fmt , ## __VA_ARGS__); } while (0) | |
36 | #else | |
37 | #define NVRAM_PRINTF(fmt, ...) do { } while (0) | |
38 | #endif | |
39 | ||
40 | /* | |
41 | * The M48T02, M48T08 and M48T59 chips are very similar. The newer '59 has | |
42 | * alarm and a watchdog timer and related control registers. In the | |
43 | * PPC platform there is also a nvram lock function. | |
44 | */ | |
45 | ||
46 | /* | |
47 | * Chipset docs: | |
48 | * http://www.st.com/stonline/products/literature/ds/2410/m48t02.pdf | |
49 | * http://www.st.com/stonline/products/literature/ds/2411/m48t08.pdf | |
50 | * http://www.st.com/stonline/products/literature/od/7001/m48t59y.pdf | |
51 | */ | |
52 | ||
53 | struct M48t59State { | |
54 | /* Hardware parameters */ | |
55 | qemu_irq IRQ; | |
56 | MemoryRegion iomem; | |
57 | uint32_t io_base; | |
58 | uint32_t size; | |
59 | /* RTC management */ | |
60 | time_t time_offset; | |
61 | time_t stop_time; | |
62 | /* Alarm & watchdog */ | |
63 | struct tm alarm; | |
64 | struct QEMUTimer *alrm_timer; | |
65 | struct QEMUTimer *wd_timer; | |
66 | /* NVRAM storage */ | |
67 | uint8_t *buffer; | |
68 | /* Model parameters */ | |
69 | uint32_t model; /* 2 = m48t02, 8 = m48t08, 59 = m48t59 */ | |
70 | /* NVRAM storage */ | |
71 | uint16_t addr; | |
72 | uint8_t lock; | |
73 | }; | |
74 | ||
75 | typedef struct M48t59ISAState { | |
76 | ISADevice busdev; | |
77 | M48t59State state; | |
78 | MemoryRegion io; | |
79 | } M48t59ISAState; | |
80 | ||
81 | typedef struct M48t59SysBusState { | |
82 | SysBusDevice busdev; | |
83 | M48t59State state; | |
84 | MemoryRegion io; | |
85 | } M48t59SysBusState; | |
86 | ||
87 | /* Fake timer functions */ | |
88 | ||
89 | /* Alarm management */ | |
90 | static void alarm_cb (void *opaque) | |
91 | { | |
92 | struct tm tm; | |
93 | uint64_t next_time; | |
94 | M48t59State *NVRAM = opaque; | |
95 | ||
96 | qemu_set_irq(NVRAM->IRQ, 1); | |
97 | if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 && | |
98 | (NVRAM->buffer[0x1FF4] & 0x80) == 0 && | |
99 | (NVRAM->buffer[0x1FF3] & 0x80) == 0 && | |
100 | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { | |
101 | /* Repeat once a month */ | |
102 | qemu_get_timedate(&tm, NVRAM->time_offset); | |
103 | tm.tm_mon++; | |
104 | if (tm.tm_mon == 13) { | |
105 | tm.tm_mon = 1; | |
106 | tm.tm_year++; | |
107 | } | |
108 | next_time = qemu_timedate_diff(&tm) - NVRAM->time_offset; | |
109 | } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && | |
110 | (NVRAM->buffer[0x1FF4] & 0x80) == 0 && | |
111 | (NVRAM->buffer[0x1FF3] & 0x80) == 0 && | |
112 | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { | |
113 | /* Repeat once a day */ | |
114 | next_time = 24 * 60 * 60; | |
115 | } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && | |
116 | (NVRAM->buffer[0x1FF4] & 0x80) != 0 && | |
117 | (NVRAM->buffer[0x1FF3] & 0x80) == 0 && | |
118 | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { | |
119 | /* Repeat once an hour */ | |
120 | next_time = 60 * 60; | |
121 | } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && | |
122 | (NVRAM->buffer[0x1FF4] & 0x80) != 0 && | |
123 | (NVRAM->buffer[0x1FF3] & 0x80) != 0 && | |
124 | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { | |
125 | /* Repeat once a minute */ | |
126 | next_time = 60; | |
127 | } else { | |
128 | /* Repeat once a second */ | |
129 | next_time = 1; | |
130 | } | |
131 | qemu_mod_timer(NVRAM->alrm_timer, qemu_get_clock_ns(rtc_clock) + | |
132 | next_time * 1000); | |
133 | qemu_set_irq(NVRAM->IRQ, 0); | |
134 | } | |
135 | ||
136 | static void set_alarm(M48t59State *NVRAM) | |
137 | { | |
138 | int diff; | |
139 | if (NVRAM->alrm_timer != NULL) { | |
140 | qemu_del_timer(NVRAM->alrm_timer); | |
141 | diff = qemu_timedate_diff(&NVRAM->alarm) - NVRAM->time_offset; | |
142 | if (diff > 0) | |
143 | qemu_mod_timer(NVRAM->alrm_timer, diff * 1000); | |
144 | } | |
145 | } | |
146 | ||
147 | /* RTC management helpers */ | |
148 | static inline void get_time(M48t59State *NVRAM, struct tm *tm) | |
149 | { | |
150 | qemu_get_timedate(tm, NVRAM->time_offset); | |
151 | } | |
152 | ||
153 | static void set_time(M48t59State *NVRAM, struct tm *tm) | |
154 | { | |
155 | NVRAM->time_offset = qemu_timedate_diff(tm); | |
156 | set_alarm(NVRAM); | |
157 | } | |
158 | ||
159 | /* Watchdog management */ | |
160 | static void watchdog_cb (void *opaque) | |
161 | { | |
162 | M48t59State *NVRAM = opaque; | |
163 | ||
164 | NVRAM->buffer[0x1FF0] |= 0x80; | |
165 | if (NVRAM->buffer[0x1FF7] & 0x80) { | |
166 | NVRAM->buffer[0x1FF7] = 0x00; | |
167 | NVRAM->buffer[0x1FFC] &= ~0x40; | |
168 | /* May it be a hw CPU Reset instead ? */ | |
169 | qemu_system_reset_request(); | |
170 | } else { | |
171 | qemu_set_irq(NVRAM->IRQ, 1); | |
172 | qemu_set_irq(NVRAM->IRQ, 0); | |
173 | } | |
174 | } | |
175 | ||
176 | static void set_up_watchdog(M48t59State *NVRAM, uint8_t value) | |
177 | { | |
178 | uint64_t interval; /* in 1/16 seconds */ | |
179 | ||
180 | NVRAM->buffer[0x1FF0] &= ~0x80; | |
181 | if (NVRAM->wd_timer != NULL) { | |
182 | qemu_del_timer(NVRAM->wd_timer); | |
183 | if (value != 0) { | |
184 | interval = (1 << (2 * (value & 0x03))) * ((value >> 2) & 0x1F); | |
185 | qemu_mod_timer(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) + | |
186 | ((interval * 1000) >> 4)); | |
187 | } | |
188 | } | |
189 | } | |
190 | ||
191 | /* Direct access to NVRAM */ | |
192 | void m48t59_write (void *opaque, uint32_t addr, uint32_t val) | |
193 | { | |
194 | M48t59State *NVRAM = opaque; | |
195 | struct tm tm; | |
196 | int tmp; | |
197 | ||
198 | if (addr > 0x1FF8 && addr < 0x2000) | |
199 | NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val); | |
200 | ||
201 | /* check for NVRAM access */ | |
202 | if ((NVRAM->model == 2 && addr < 0x7f8) || | |
203 | (NVRAM->model == 8 && addr < 0x1ff8) || | |
204 | (NVRAM->model == 59 && addr < 0x1ff0)) { | |
205 | goto do_write; | |
206 | } | |
207 | ||
208 | /* TOD access */ | |
209 | switch (addr) { | |
210 | case 0x1FF0: | |
211 | /* flags register : read-only */ | |
212 | break; | |
213 | case 0x1FF1: | |
214 | /* unused */ | |
215 | break; | |
216 | case 0x1FF2: | |
217 | /* alarm seconds */ | |
218 | tmp = from_bcd(val & 0x7F); | |
219 | if (tmp >= 0 && tmp <= 59) { | |
220 | NVRAM->alarm.tm_sec = tmp; | |
221 | NVRAM->buffer[0x1FF2] = val; | |
222 | set_alarm(NVRAM); | |
223 | } | |
224 | break; | |
225 | case 0x1FF3: | |
226 | /* alarm minutes */ | |
227 | tmp = from_bcd(val & 0x7F); | |
228 | if (tmp >= 0 && tmp <= 59) { | |
229 | NVRAM->alarm.tm_min = tmp; | |
230 | NVRAM->buffer[0x1FF3] = val; | |
231 | set_alarm(NVRAM); | |
232 | } | |
233 | break; | |
234 | case 0x1FF4: | |
235 | /* alarm hours */ | |
236 | tmp = from_bcd(val & 0x3F); | |
237 | if (tmp >= 0 && tmp <= 23) { | |
238 | NVRAM->alarm.tm_hour = tmp; | |
239 | NVRAM->buffer[0x1FF4] = val; | |
240 | set_alarm(NVRAM); | |
241 | } | |
242 | break; | |
243 | case 0x1FF5: | |
244 | /* alarm date */ | |
245 | tmp = from_bcd(val & 0x3F); | |
246 | if (tmp != 0) { | |
247 | NVRAM->alarm.tm_mday = tmp; | |
248 | NVRAM->buffer[0x1FF5] = val; | |
249 | set_alarm(NVRAM); | |
250 | } | |
251 | break; | |
252 | case 0x1FF6: | |
253 | /* interrupts */ | |
254 | NVRAM->buffer[0x1FF6] = val; | |
255 | break; | |
256 | case 0x1FF7: | |
257 | /* watchdog */ | |
258 | NVRAM->buffer[0x1FF7] = val; | |
259 | set_up_watchdog(NVRAM, val); | |
260 | break; | |
261 | case 0x1FF8: | |
262 | case 0x07F8: | |
263 | /* control */ | |
264 | NVRAM->buffer[addr] = (val & ~0xA0) | 0x90; | |
265 | break; | |
266 | case 0x1FF9: | |
267 | case 0x07F9: | |
268 | /* seconds (BCD) */ | |
269 | tmp = from_bcd(val & 0x7F); | |
270 | if (tmp >= 0 && tmp <= 59) { | |
271 | get_time(NVRAM, &tm); | |
272 | tm.tm_sec = tmp; | |
273 | set_time(NVRAM, &tm); | |
274 | } | |
275 | if ((val & 0x80) ^ (NVRAM->buffer[addr] & 0x80)) { | |
276 | if (val & 0x80) { | |
277 | NVRAM->stop_time = time(NULL); | |
278 | } else { | |
279 | NVRAM->time_offset += NVRAM->stop_time - time(NULL); | |
280 | NVRAM->stop_time = 0; | |
281 | } | |
282 | } | |
283 | NVRAM->buffer[addr] = val & 0x80; | |
284 | break; | |
285 | case 0x1FFA: | |
286 | case 0x07FA: | |
287 | /* minutes (BCD) */ | |
288 | tmp = from_bcd(val & 0x7F); | |
289 | if (tmp >= 0 && tmp <= 59) { | |
290 | get_time(NVRAM, &tm); | |
291 | tm.tm_min = tmp; | |
292 | set_time(NVRAM, &tm); | |
293 | } | |
294 | break; | |
295 | case 0x1FFB: | |
296 | case 0x07FB: | |
297 | /* hours (BCD) */ | |
298 | tmp = from_bcd(val & 0x3F); | |
299 | if (tmp >= 0 && tmp <= 23) { | |
300 | get_time(NVRAM, &tm); | |
301 | tm.tm_hour = tmp; | |
302 | set_time(NVRAM, &tm); | |
303 | } | |
304 | break; | |
305 | case 0x1FFC: | |
306 | case 0x07FC: | |
307 | /* day of the week / century */ | |
308 | tmp = from_bcd(val & 0x07); | |
309 | get_time(NVRAM, &tm); | |
310 | tm.tm_wday = tmp; | |
311 | set_time(NVRAM, &tm); | |
312 | NVRAM->buffer[addr] = val & 0x40; | |
313 | break; | |
314 | case 0x1FFD: | |
315 | case 0x07FD: | |
316 | /* date (BCD) */ | |
317 | tmp = from_bcd(val & 0x3F); | |
318 | if (tmp != 0) { | |
319 | get_time(NVRAM, &tm); | |
320 | tm.tm_mday = tmp; | |
321 | set_time(NVRAM, &tm); | |
322 | } | |
323 | break; | |
324 | case 0x1FFE: | |
325 | case 0x07FE: | |
326 | /* month */ | |
327 | tmp = from_bcd(val & 0x1F); | |
328 | if (tmp >= 1 && tmp <= 12) { | |
329 | get_time(NVRAM, &tm); | |
330 | tm.tm_mon = tmp - 1; | |
331 | set_time(NVRAM, &tm); | |
332 | } | |
333 | break; | |
334 | case 0x1FFF: | |
335 | case 0x07FF: | |
336 | /* year */ | |
337 | tmp = from_bcd(val); | |
338 | if (tmp >= 0 && tmp <= 99) { | |
339 | get_time(NVRAM, &tm); | |
340 | if (NVRAM->model == 8) { | |
341 | tm.tm_year = from_bcd(val) + 68; // Base year is 1968 | |
342 | } else { | |
343 | tm.tm_year = from_bcd(val); | |
344 | } | |
345 | set_time(NVRAM, &tm); | |
346 | } | |
347 | break; | |
348 | default: | |
349 | /* Check lock registers state */ | |
350 | if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1)) | |
351 | break; | |
352 | if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2)) | |
353 | break; | |
354 | do_write: | |
355 | if (addr < NVRAM->size) { | |
356 | NVRAM->buffer[addr] = val & 0xFF; | |
357 | } | |
358 | break; | |
359 | } | |
360 | } | |
361 | ||
362 | uint32_t m48t59_read (void *opaque, uint32_t addr) | |
363 | { | |
364 | M48t59State *NVRAM = opaque; | |
365 | struct tm tm; | |
366 | uint32_t retval = 0xFF; | |
367 | ||
368 | /* check for NVRAM access */ | |
369 | if ((NVRAM->model == 2 && addr < 0x078f) || | |
370 | (NVRAM->model == 8 && addr < 0x1ff8) || | |
371 | (NVRAM->model == 59 && addr < 0x1ff0)) { | |
372 | goto do_read; | |
373 | } | |
374 | ||
375 | /* TOD access */ | |
376 | switch (addr) { | |
377 | case 0x1FF0: | |
378 | /* flags register */ | |
379 | goto do_read; | |
380 | case 0x1FF1: | |
381 | /* unused */ | |
382 | retval = 0; | |
383 | break; | |
384 | case 0x1FF2: | |
385 | /* alarm seconds */ | |
386 | goto do_read; | |
387 | case 0x1FF3: | |
388 | /* alarm minutes */ | |
389 | goto do_read; | |
390 | case 0x1FF4: | |
391 | /* alarm hours */ | |
392 | goto do_read; | |
393 | case 0x1FF5: | |
394 | /* alarm date */ | |
395 | goto do_read; | |
396 | case 0x1FF6: | |
397 | /* interrupts */ | |
398 | goto do_read; | |
399 | case 0x1FF7: | |
400 | /* A read resets the watchdog */ | |
401 | set_up_watchdog(NVRAM, NVRAM->buffer[0x1FF7]); | |
402 | goto do_read; | |
403 | case 0x1FF8: | |
404 | case 0x07F8: | |
405 | /* control */ | |
406 | goto do_read; | |
407 | case 0x1FF9: | |
408 | case 0x07F9: | |
409 | /* seconds (BCD) */ | |
410 | get_time(NVRAM, &tm); | |
411 | retval = (NVRAM->buffer[addr] & 0x80) | to_bcd(tm.tm_sec); | |
412 | break; | |
413 | case 0x1FFA: | |
414 | case 0x07FA: | |
415 | /* minutes (BCD) */ | |
416 | get_time(NVRAM, &tm); | |
417 | retval = to_bcd(tm.tm_min); | |
418 | break; | |
419 | case 0x1FFB: | |
420 | case 0x07FB: | |
421 | /* hours (BCD) */ | |
422 | get_time(NVRAM, &tm); | |
423 | retval = to_bcd(tm.tm_hour); | |
424 | break; | |
425 | case 0x1FFC: | |
426 | case 0x07FC: | |
427 | /* day of the week / century */ | |
428 | get_time(NVRAM, &tm); | |
429 | retval = NVRAM->buffer[addr] | tm.tm_wday; | |
430 | break; | |
431 | case 0x1FFD: | |
432 | case 0x07FD: | |
433 | /* date */ | |
434 | get_time(NVRAM, &tm); | |
435 | retval = to_bcd(tm.tm_mday); | |
436 | break; | |
437 | case 0x1FFE: | |
438 | case 0x07FE: | |
439 | /* month */ | |
440 | get_time(NVRAM, &tm); | |
441 | retval = to_bcd(tm.tm_mon + 1); | |
442 | break; | |
443 | case 0x1FFF: | |
444 | case 0x07FF: | |
445 | /* year */ | |
446 | get_time(NVRAM, &tm); | |
447 | if (NVRAM->model == 8) { | |
448 | retval = to_bcd(tm.tm_year - 68); // Base year is 1968 | |
449 | } else { | |
450 | retval = to_bcd(tm.tm_year); | |
451 | } | |
452 | break; | |
453 | default: | |
454 | /* Check lock registers state */ | |
455 | if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1)) | |
456 | break; | |
457 | if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2)) | |
458 | break; | |
459 | do_read: | |
460 | if (addr < NVRAM->size) { | |
461 | retval = NVRAM->buffer[addr]; | |
462 | } | |
463 | break; | |
464 | } | |
465 | if (addr > 0x1FF9 && addr < 0x2000) | |
466 | NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval); | |
467 | ||
468 | return retval; | |
469 | } | |
470 | ||
471 | void m48t59_toggle_lock (void *opaque, int lock) | |
472 | { | |
473 | M48t59State *NVRAM = opaque; | |
474 | ||
475 | NVRAM->lock ^= 1 << lock; | |
476 | } | |
477 | ||
478 | /* IO access to NVRAM */ | |
479 | static void NVRAM_writeb(void *opaque, hwaddr addr, uint64_t val, | |
480 | unsigned size) | |
481 | { | |
482 | M48t59State *NVRAM = opaque; | |
483 | ||
484 | NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val); | |
485 | switch (addr) { | |
486 | case 0: | |
487 | NVRAM->addr &= ~0x00FF; | |
488 | NVRAM->addr |= val; | |
489 | break; | |
490 | case 1: | |
491 | NVRAM->addr &= ~0xFF00; | |
492 | NVRAM->addr |= val << 8; | |
493 | break; | |
494 | case 3: | |
495 | m48t59_write(NVRAM, NVRAM->addr, val); | |
496 | NVRAM->addr = 0x0000; | |
497 | break; | |
498 | default: | |
499 | break; | |
500 | } | |
501 | } | |
502 | ||
503 | static uint64_t NVRAM_readb(void *opaque, hwaddr addr, unsigned size) | |
504 | { | |
505 | M48t59State *NVRAM = opaque; | |
506 | uint32_t retval; | |
507 | ||
508 | switch (addr) { | |
509 | case 3: | |
510 | retval = m48t59_read(NVRAM, NVRAM->addr); | |
511 | break; | |
512 | default: | |
513 | retval = -1; | |
514 | break; | |
515 | } | |
516 | NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval); | |
517 | ||
518 | return retval; | |
519 | } | |
520 | ||
521 | static void nvram_writeb (void *opaque, hwaddr addr, uint32_t value) | |
522 | { | |
523 | M48t59State *NVRAM = opaque; | |
524 | ||
525 | m48t59_write(NVRAM, addr, value & 0xff); | |
526 | } | |
527 | ||
528 | static void nvram_writew (void *opaque, hwaddr addr, uint32_t value) | |
529 | { | |
530 | M48t59State *NVRAM = opaque; | |
531 | ||
532 | m48t59_write(NVRAM, addr, (value >> 8) & 0xff); | |
533 | m48t59_write(NVRAM, addr + 1, value & 0xff); | |
534 | } | |
535 | ||
536 | static void nvram_writel (void *opaque, hwaddr addr, uint32_t value) | |
537 | { | |
538 | M48t59State *NVRAM = opaque; | |
539 | ||
540 | m48t59_write(NVRAM, addr, (value >> 24) & 0xff); | |
541 | m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff); | |
542 | m48t59_write(NVRAM, addr + 2, (value >> 8) & 0xff); | |
543 | m48t59_write(NVRAM, addr + 3, value & 0xff); | |
544 | } | |
545 | ||
546 | static uint32_t nvram_readb (void *opaque, hwaddr addr) | |
547 | { | |
548 | M48t59State *NVRAM = opaque; | |
549 | uint32_t retval; | |
550 | ||
551 | retval = m48t59_read(NVRAM, addr); | |
552 | return retval; | |
553 | } | |
554 | ||
555 | static uint32_t nvram_readw (void *opaque, hwaddr addr) | |
556 | { | |
557 | M48t59State *NVRAM = opaque; | |
558 | uint32_t retval; | |
559 | ||
560 | retval = m48t59_read(NVRAM, addr) << 8; | |
561 | retval |= m48t59_read(NVRAM, addr + 1); | |
562 | return retval; | |
563 | } | |
564 | ||
565 | static uint32_t nvram_readl (void *opaque, hwaddr addr) | |
566 | { | |
567 | M48t59State *NVRAM = opaque; | |
568 | uint32_t retval; | |
569 | ||
570 | retval = m48t59_read(NVRAM, addr) << 24; | |
571 | retval |= m48t59_read(NVRAM, addr + 1) << 16; | |
572 | retval |= m48t59_read(NVRAM, addr + 2) << 8; | |
573 | retval |= m48t59_read(NVRAM, addr + 3); | |
574 | return retval; | |
575 | } | |
576 | ||
577 | static const MemoryRegionOps nvram_ops = { | |
578 | .old_mmio = { | |
579 | .read = { nvram_readb, nvram_readw, nvram_readl, }, | |
580 | .write = { nvram_writeb, nvram_writew, nvram_writel, }, | |
581 | }, | |
582 | .endianness = DEVICE_NATIVE_ENDIAN, | |
583 | }; | |
584 | ||
585 | static const VMStateDescription vmstate_m48t59 = { | |
586 | .name = "m48t59", | |
587 | .version_id = 1, | |
588 | .minimum_version_id = 1, | |
589 | .minimum_version_id_old = 1, | |
590 | .fields = (VMStateField[]) { | |
591 | VMSTATE_UINT8(lock, M48t59State), | |
592 | VMSTATE_UINT16(addr, M48t59State), | |
593 | VMSTATE_VBUFFER_UINT32(buffer, M48t59State, 0, NULL, 0, size), | |
594 | VMSTATE_END_OF_LIST() | |
595 | } | |
596 | }; | |
597 | ||
598 | static void m48t59_reset_common(M48t59State *NVRAM) | |
599 | { | |
600 | NVRAM->addr = 0; | |
601 | NVRAM->lock = 0; | |
602 | if (NVRAM->alrm_timer != NULL) | |
603 | qemu_del_timer(NVRAM->alrm_timer); | |
604 | ||
605 | if (NVRAM->wd_timer != NULL) | |
606 | qemu_del_timer(NVRAM->wd_timer); | |
607 | } | |
608 | ||
609 | static void m48t59_reset_isa(DeviceState *d) | |
610 | { | |
611 | M48t59ISAState *isa = container_of(d, M48t59ISAState, busdev.qdev); | |
612 | M48t59State *NVRAM = &isa->state; | |
613 | ||
614 | m48t59_reset_common(NVRAM); | |
615 | } | |
616 | ||
617 | static void m48t59_reset_sysbus(DeviceState *d) | |
618 | { | |
619 | M48t59SysBusState *sys = container_of(d, M48t59SysBusState, busdev.qdev); | |
620 | M48t59State *NVRAM = &sys->state; | |
621 | ||
622 | m48t59_reset_common(NVRAM); | |
623 | } | |
624 | ||
625 | static const MemoryRegionOps m48t59_io_ops = { | |
626 | .read = NVRAM_readb, | |
627 | .write = NVRAM_writeb, | |
628 | .impl = { | |
629 | .min_access_size = 1, | |
630 | .max_access_size = 1, | |
631 | }, | |
632 | .endianness = DEVICE_LITTLE_ENDIAN, | |
633 | }; | |
634 | ||
635 | /* Initialisation routine */ | |
636 | M48t59State *m48t59_init(qemu_irq IRQ, hwaddr mem_base, | |
637 | uint32_t io_base, uint16_t size, int model) | |
638 | { | |
639 | DeviceState *dev; | |
640 | SysBusDevice *s; | |
641 | M48t59SysBusState *d; | |
642 | M48t59State *state; | |
643 | ||
644 | dev = qdev_create(NULL, "m48t59"); | |
645 | qdev_prop_set_uint32(dev, "model", model); | |
646 | qdev_prop_set_uint32(dev, "size", size); | |
647 | qdev_prop_set_uint32(dev, "io_base", io_base); | |
648 | qdev_init_nofail(dev); | |
649 | s = sysbus_from_qdev(dev); | |
650 | d = FROM_SYSBUS(M48t59SysBusState, s); | |
651 | state = &d->state; | |
652 | sysbus_connect_irq(s, 0, IRQ); | |
653 | memory_region_init_io(&d->io, &m48t59_io_ops, state, "m48t59", 4); | |
654 | if (io_base != 0) { | |
655 | memory_region_add_subregion(get_system_io(), io_base, &d->io); | |
656 | } | |
657 | if (mem_base != 0) { | |
658 | sysbus_mmio_map(s, 0, mem_base); | |
659 | } | |
660 | ||
661 | return state; | |
662 | } | |
663 | ||
664 | M48t59State *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size, | |
665 | int model) | |
666 | { | |
667 | M48t59ISAState *d; | |
668 | ISADevice *dev; | |
669 | M48t59State *s; | |
670 | ||
671 | dev = isa_create(bus, "m48t59_isa"); | |
672 | qdev_prop_set_uint32(&dev->qdev, "model", model); | |
673 | qdev_prop_set_uint32(&dev->qdev, "size", size); | |
674 | qdev_prop_set_uint32(&dev->qdev, "io_base", io_base); | |
675 | qdev_init_nofail(&dev->qdev); | |
676 | d = DO_UPCAST(M48t59ISAState, busdev, dev); | |
677 | s = &d->state; | |
678 | ||
679 | memory_region_init_io(&d->io, &m48t59_io_ops, s, "m48t59", 4); | |
680 | if (io_base != 0) { | |
681 | isa_register_ioport(dev, &d->io, io_base); | |
682 | } | |
683 | ||
684 | return s; | |
685 | } | |
686 | ||
687 | static void m48t59_init_common(M48t59State *s) | |
688 | { | |
689 | s->buffer = g_malloc0(s->size); | |
690 | if (s->model == 59) { | |
691 | s->alrm_timer = qemu_new_timer_ns(rtc_clock, &alarm_cb, s); | |
692 | s->wd_timer = qemu_new_timer_ns(vm_clock, &watchdog_cb, s); | |
693 | } | |
694 | qemu_get_timedate(&s->alarm, 0); | |
695 | ||
696 | vmstate_register(NULL, -1, &vmstate_m48t59, s); | |
697 | } | |
698 | ||
699 | static int m48t59_init_isa1(ISADevice *dev) | |
700 | { | |
701 | M48t59ISAState *d = DO_UPCAST(M48t59ISAState, busdev, dev); | |
702 | M48t59State *s = &d->state; | |
703 | ||
704 | isa_init_irq(dev, &s->IRQ, 8); | |
705 | m48t59_init_common(s); | |
706 | ||
707 | return 0; | |
708 | } | |
709 | ||
710 | static int m48t59_init1(SysBusDevice *dev) | |
711 | { | |
712 | M48t59SysBusState *d = FROM_SYSBUS(M48t59SysBusState, dev); | |
713 | M48t59State *s = &d->state; | |
714 | ||
715 | sysbus_init_irq(dev, &s->IRQ); | |
716 | ||
717 | memory_region_init_io(&s->iomem, &nvram_ops, s, "m48t59.nvram", s->size); | |
718 | sysbus_init_mmio(dev, &s->iomem); | |
719 | m48t59_init_common(s); | |
720 | ||
721 | return 0; | |
722 | } | |
723 | ||
724 | static Property m48t59_isa_properties[] = { | |
725 | DEFINE_PROP_UINT32("size", M48t59ISAState, state.size, -1), | |
726 | DEFINE_PROP_UINT32("model", M48t59ISAState, state.model, -1), | |
727 | DEFINE_PROP_HEX32( "io_base", M48t59ISAState, state.io_base, 0), | |
728 | DEFINE_PROP_END_OF_LIST(), | |
729 | }; | |
730 | ||
731 | static void m48t59_init_class_isa1(ObjectClass *klass, void *data) | |
732 | { | |
733 | DeviceClass *dc = DEVICE_CLASS(klass); | |
734 | ISADeviceClass *ic = ISA_DEVICE_CLASS(klass); | |
735 | ic->init = m48t59_init_isa1; | |
736 | dc->no_user = 1; | |
737 | dc->reset = m48t59_reset_isa; | |
738 | dc->props = m48t59_isa_properties; | |
739 | } | |
740 | ||
741 | static TypeInfo m48t59_isa_info = { | |
742 | .name = "m48t59_isa", | |
743 | .parent = TYPE_ISA_DEVICE, | |
744 | .instance_size = sizeof(M48t59ISAState), | |
745 | .class_init = m48t59_init_class_isa1, | |
746 | }; | |
747 | ||
748 | static Property m48t59_properties[] = { | |
749 | DEFINE_PROP_UINT32("size", M48t59SysBusState, state.size, -1), | |
750 | DEFINE_PROP_UINT32("model", M48t59SysBusState, state.model, -1), | |
751 | DEFINE_PROP_HEX32( "io_base", M48t59SysBusState, state.io_base, 0), | |
752 | DEFINE_PROP_END_OF_LIST(), | |
753 | }; | |
754 | ||
755 | static void m48t59_class_init(ObjectClass *klass, void *data) | |
756 | { | |
757 | DeviceClass *dc = DEVICE_CLASS(klass); | |
758 | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); | |
759 | ||
760 | k->init = m48t59_init1; | |
761 | dc->reset = m48t59_reset_sysbus; | |
762 | dc->props = m48t59_properties; | |
763 | } | |
764 | ||
765 | static TypeInfo m48t59_info = { | |
766 | .name = "m48t59", | |
767 | .parent = TYPE_SYS_BUS_DEVICE, | |
768 | .instance_size = sizeof(M48t59SysBusState), | |
769 | .class_init = m48t59_class_init, | |
770 | }; | |
771 | ||
772 | static void m48t59_register_types(void) | |
773 | { | |
774 | type_register_static(&m48t59_info); | |
775 | type_register_static(&m48t59_isa_info); | |
776 | } | |
777 | ||
778 | type_init(m48t59_register_types) |