[mirror_qemu.git] / hw / mips / mips_jazz.c

/*
 * QEMU MIPS Jazz support
 *
 * Copyright (c) 2007-2008 Hervé Poussineau
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "qemu/osdep.h"
#include "hw/hw.h"
#include "hw/mips/mips.h"
#include "hw/mips/cpudevs.h"
#include "hw/i386/pc.h"
#include "hw/char/serial.h"
#include "hw/isa/isa.h"
#include "hw/block/fdc.h"
#include "sysemu/sysemu.h"
#include "sysemu/arch_init.h"
#include "hw/boards.h"
#include "net/net.h"
#include "hw/scsi/esp.h"
#include "hw/mips/bios.h"
#include "hw/loader.h"
#include "hw/timer/mc146818rtc.h"
#include "hw/timer/i8254.h"
#include "hw/display/vga.h"
#include "hw/audio/pcspk.h"
#include "hw/sysbus.h"
#include "exec/address-spaces.h"
#include "sysemu/qtest.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "qemu/help_option.h"

enum jazz_model_e
{
    JAZZ_MAGNUM,
    JAZZ_PICA61,
};

static void main_cpu_reset(void *opaque)
{
    MIPSCPU *cpu = opaque;

    cpu_reset(CPU(cpu));
}

static uint64_t rtc_read(void *opaque, hwaddr addr, unsigned size)
{
    uint8_t val;
    address_space_read(&address_space_memory, 0x90000071,
                       MEMTXATTRS_UNSPECIFIED, &val, 1);
    return val;
}

static void rtc_write(void *opaque, hwaddr addr,
                      uint64_t val, unsigned size)
{
    uint8_t buf = val & 0xff;
    address_space_write(&address_space_memory, 0x90000071,
                        MEMTXATTRS_UNSPECIFIED, &buf, 1);
}

static const MemoryRegionOps rtc_ops = {
    .read = rtc_read,
    .write = rtc_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static uint64_t dma_dummy_read(void *opaque, hwaddr addr,
                               unsigned size)
{
    /* Nothing to do. That is only to ensure that
     * the current DMA acknowledge cycle is completed. */
    return 0xff;
}

static void dma_dummy_write(void *opaque, hwaddr addr,
                            uint64_t val, unsigned size)
{
    /* Nothing to do. That is only to ensure that
     * the current DMA acknowledge cycle is completed. */
}

static const MemoryRegionOps dma_dummy_ops = {
    .read = dma_dummy_read,
    .write = dma_dummy_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

#define MAGNUM_BIOS_SIZE_MAX 0x7e000
#define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)

static CPUUnassignedAccess real_do_unassigned_access;
static void mips_jazz_do_unassigned_access(CPUState *cpu, hwaddr addr,
                                           bool is_write, bool is_exec,
                                           int opaque, unsigned size)
{
    if (!is_exec) {
        /* ignore invalid access (ie do not raise exception) */
        return;
    }
    (*real_do_unassigned_access)(cpu, addr, is_write, is_exec, opaque, size);
}

static void mips_jazz_init(MachineState *machine,
                           enum jazz_model_e jazz_model)
{
    MemoryRegion *address_space = get_system_memory();
    char *filename;
    int bios_size, n;
    MIPSCPU *cpu;
    CPUClass *cc;
    CPUMIPSState *env;
    qemu_irq *i8259;
    rc4030_dma *dmas;
    IOMMUMemoryRegion *rc4030_dma_mr;
    MemoryRegion *isa_mem = g_new(MemoryRegion, 1);
    MemoryRegion *isa_io = g_new(MemoryRegion, 1);
    MemoryRegion *rtc = g_new(MemoryRegion, 1);
    MemoryRegion *i8042 = g_new(MemoryRegion, 1);
    MemoryRegion *dma_dummy = g_new(MemoryRegion, 1);
    NICInfo *nd;
    DeviceState *dev, *rc4030;
    SysBusDevice *sysbus;
    ISABus *isa_bus;
    ISADevice *pit;
    DriveInfo *fds[MAX_FD];
    qemu_irq esp_reset, dma_enable;
    MemoryRegion *ram = g_new(MemoryRegion, 1);
    MemoryRegion *bios = g_new(MemoryRegion, 1);
    MemoryRegion *bios2 = g_new(MemoryRegion, 1);
    ESPState *esp;

    /* init CPUs */
    cpu = MIPS_CPU(cpu_create(machine->cpu_type));
    env = &cpu->env;
    qemu_register_reset(main_cpu_reset, cpu);

    /* Chipset returns 0 in invalid reads and do not raise data exceptions.
     * However, we can't simply add a global memory region to catch
     * everything, as memory core directly call unassigned_mem_read/write
     * on some invalid accesses, which call do_unassigned_access on the
     * CPU, which raise an exception.
     * Handle that case by hijacking the do_unassigned_access method on
     * the CPU, and do not raise exceptions for data access. */
    cc = CPU_GET_CLASS(cpu);
    real_do_unassigned_access = cc->do_unassigned_access;
    cc->do_unassigned_access = mips_jazz_do_unassigned_access;

    /* allocate RAM */
    memory_region_allocate_system_memory(ram, NULL, "mips_jazz.ram",
                                         machine->ram_size);
    memory_region_add_subregion(address_space, 0, ram);

    memory_region_init_ram(bios, NULL, "mips_jazz.bios", MAGNUM_BIOS_SIZE,
                           &error_fatal);
    memory_region_set_readonly(bios, true);
    memory_region_init_alias(bios2, NULL, "mips_jazz.bios", bios,
                             0, MAGNUM_BIOS_SIZE);
    memory_region_add_subregion(address_space, 0x1fc00000LL, bios);
    memory_region_add_subregion(address_space, 0xfff00000LL, bios2);

    /* load the BIOS image. */
    if (bios_name == NULL)
        bios_name = BIOS_FILENAME;
    filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
    if (filename) {
        bios_size = load_image_targphys(filename, 0xfff00000LL,
                                        MAGNUM_BIOS_SIZE);
        g_free(filename);
    } else {
        bios_size = -1;
    }
    if ((bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) && !qtest_enabled()) {
        error_report("Could not load MIPS bios '%s'", bios_name);
        exit(1);
    }

    /* Init CPU internal devices */
    cpu_mips_irq_init_cpu(cpu);
    cpu_mips_clock_init(cpu);

    /* Chipset */
    rc4030 = rc4030_init(&dmas, &rc4030_dma_mr);
    sysbus = SYS_BUS_DEVICE(rc4030);
    sysbus_connect_irq(sysbus, 0, env->irq[6]);
    sysbus_connect_irq(sysbus, 1, env->irq[3]);
    memory_region_add_subregion(address_space, 0x80000000,
                                sysbus_mmio_get_region(sysbus, 0));
    memory_region_add_subregion(address_space, 0xf0000000,
                                sysbus_mmio_get_region(sysbus, 1));
    memory_region_init_io(dma_dummy, NULL, &dma_dummy_ops, NULL, "dummy_dma", 0x1000);
    memory_region_add_subregion(address_space, 0x8000d000, dma_dummy);

    /* ISA bus: IO space at 0x90000000, mem space at 0x91000000 */
    memory_region_init(isa_io, NULL, "isa-io", 0x00010000);
    memory_region_init(isa_mem, NULL, "isa-mem", 0x01000000);
    memory_region_add_subregion(address_space, 0x90000000, isa_io);
    memory_region_add_subregion(address_space, 0x91000000, isa_mem);
    isa_bus = isa_bus_new(NULL, isa_mem, isa_io, &error_abort);

    /* ISA devices */
    i8259 = i8259_init(isa_bus, env->irq[4]);
    isa_bus_irqs(isa_bus, i8259);
    DMA_init(isa_bus, 0);
    pit = i8254_pit_init(isa_bus, 0x40, 0, NULL);
    pcspk_init(isa_bus, pit);

    /* Video card */
    switch (jazz_model) {
    case JAZZ_MAGNUM:
        dev = qdev_create(NULL, "sysbus-g364");
        qdev_init_nofail(dev);
        sysbus = SYS_BUS_DEVICE(dev);
        sysbus_mmio_map(sysbus, 0, 0x60080000);
        sysbus_mmio_map(sysbus, 1, 0x40000000);
        sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 3));
        {
            /* Simple ROM, so user doesn't have to provide one */
            MemoryRegion *rom_mr = g_new(MemoryRegion, 1);
            memory_region_init_ram(rom_mr, NULL, "g364fb.rom", 0x80000,
                                   &error_fatal);
            memory_region_set_readonly(rom_mr, true);
            uint8_t *rom = memory_region_get_ram_ptr(rom_mr);
            memory_region_add_subregion(address_space, 0x60000000, rom_mr);
            rom[0] = 0x10; /* Mips G364 */
        }
        break;
    case JAZZ_PICA61:
        isa_vga_mm_init(0x40000000, 0x60000000, 0, get_system_memory());
        break;
    default:
        break;
    }

    /* Network controller */
    for (n = 0; n < nb_nics; n++) {
        nd = &nd_table[n];
        if (!nd->model)
            nd->model = g_strdup("dp83932");
        if (strcmp(nd->model, "dp83932") == 0) {
            qemu_check_nic_model(nd, "dp83932");

            dev = qdev_create(NULL, "dp8393x");
            qdev_set_nic_properties(dev, nd);
            qdev_prop_set_uint8(dev, "it_shift", 2);
            qdev_prop_set_ptr(dev, "dma_mr", rc4030_dma_mr);
            qdev_init_nofail(dev);
            sysbus = SYS_BUS_DEVICE(dev);
            sysbus_mmio_map(sysbus, 0, 0x80001000);
            sysbus_mmio_map(sysbus, 1, 0x8000b000);
            sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 4));
            break;
        } else if (is_help_option(nd->model)) {
            error_report("Supported NICs: dp83932");
            exit(1);
        } else {
            error_report("Unsupported NIC: %s", nd->model);
            exit(1);
        }
    }

    /* SCSI adapter */
    esp = esp_init(0x80002000, 0, rc4030_dma_read, rc4030_dma_write, dmas[0],
                   qdev_get_gpio_in(rc4030, 5), &esp_reset, &dma_enable);
    scsi_bus_legacy_handle_cmdline(&esp->bus);

    /* Floppy */
    for (n = 0; n < MAX_FD; n++) {
        fds[n] = drive_get(IF_FLOPPY, 0, n);
    }
    /* FIXME: we should enable DMA with a custom IsaDma device */
    fdctrl_init_sysbus(qdev_get_gpio_in(rc4030, 1), -1, 0x80003000, fds);

    /* Real time clock */
    mc146818_rtc_init(isa_bus, 1980, NULL);
    memory_region_init_io(rtc, NULL, &rtc_ops, NULL, "rtc", 0x1000);
    memory_region_add_subregion(address_space, 0x80004000, rtc);

    /* Keyboard (i8042) */
    i8042_mm_init(qdev_get_gpio_in(rc4030, 6), qdev_get_gpio_in(rc4030, 7),
                  i8042, 0x1000, 0x1);
    memory_region_add_subregion(address_space, 0x80005000, i8042);

    /* Serial ports */
    if (serial_hds[0]) {
        serial_mm_init(address_space, 0x80006000, 0,
                       qdev_get_gpio_in(rc4030, 8), 8000000/16,
                       serial_hds[0], DEVICE_NATIVE_ENDIAN);
    }
    if (serial_hds[1]) {
        serial_mm_init(address_space, 0x80007000, 0,
                       qdev_get_gpio_in(rc4030, 9), 8000000/16,
                       serial_hds[1], DEVICE_NATIVE_ENDIAN);
    }

    /* Parallel port */
    if (parallel_hds[0])
        parallel_mm_init(address_space, 0x80008000, 0,
                         qdev_get_gpio_in(rc4030, 0), parallel_hds[0]);

    /* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */

    /* NVRAM */
    dev = qdev_create(NULL, "ds1225y");
    qdev_init_nofail(dev);
    sysbus = SYS_BUS_DEVICE(dev);
    sysbus_mmio_map(sysbus, 0, 0x80009000);

    /* LED indicator */
    sysbus_create_simple("jazz-led", 0x8000f000, NULL);
}

static
void mips_magnum_init(MachineState *machine)
{
    mips_jazz_init(machine, JAZZ_MAGNUM);
}

static
void mips_pica61_init(MachineState *machine)
{
    mips_jazz_init(machine, JAZZ_PICA61);
}

static void mips_magnum_class_init(ObjectClass *oc, void *data)
{
    MachineClass *mc = MACHINE_CLASS(oc);

    mc->desc = "MIPS Magnum";
    mc->init = mips_magnum_init;
    mc->block_default_type = IF_SCSI;
    mc->default_cpu_type = MIPS_CPU_TYPE_NAME("R4000");
}

static const TypeInfo mips_magnum_type = {
    .name = MACHINE_TYPE_NAME("magnum"),
    .parent = TYPE_MACHINE,
    .class_init = mips_magnum_class_init,
};

static void mips_pica61_class_init(ObjectClass *oc, void *data)
{
    MachineClass *mc = MACHINE_CLASS(oc);

    mc->desc = "Acer Pica 61";
    mc->init = mips_pica61_init;
    mc->block_default_type = IF_SCSI;
    mc->default_cpu_type = MIPS_CPU_TYPE_NAME("R4000");
}

static const TypeInfo mips_pica61_type = {
    .name = MACHINE_TYPE_NAME("pica61"),
    .parent = TYPE_MACHINE,
    .class_init = mips_pica61_class_init,
};

static void mips_jazz_machine_init(void)
{
    type_register_static(&mips_magnum_type);
    type_register_static(&mips_pica61_type);
}

type_init(mips_jazz_machine_init)
Commit	Line	Data
	1	/*
	2	* QEMU MIPS Jazz support
	3	*
	4	* Copyright (c) 2007-2008 Hervé Poussineau
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24
	25	#include "qemu/osdep.h"
	26	#include "hw/hw.h"
	27	#include "hw/mips/mips.h"
	28	#include "hw/mips/cpudevs.h"
	29	#include "hw/i386/pc.h"
	30	#include "hw/char/serial.h"
	31	#include "hw/isa/isa.h"
	32	#include "hw/block/fdc.h"
	33	#include "sysemu/sysemu.h"
	34	#include "sysemu/arch_init.h"
	35	#include "hw/boards.h"
	36	#include "net/net.h"
	37	#include "hw/scsi/esp.h"
	38	#include "hw/mips/bios.h"
	39	#include "hw/loader.h"
	40	#include "hw/timer/mc146818rtc.h"
	41	#include "hw/timer/i8254.h"
	42	#include "hw/display/vga.h"
	43	#include "hw/audio/pcspk.h"
	44	#include "hw/sysbus.h"
	45	#include "exec/address-spaces.h"
	46	#include "sysemu/qtest.h"
	47	#include "qapi/error.h"
	48	#include "qemu/error-report.h"
	49	#include "qemu/help_option.h"
	50
	51	enum jazz_model_e
	52	{
	53	JAZZ_MAGNUM,
	54	JAZZ_PICA61,
	55	};
	56
	57	static void main_cpu_reset(void *opaque)
	58	{
	59	MIPSCPU *cpu = opaque;
	60
	61	cpu_reset(CPU(cpu));
	62	}
	63
	64	static uint64_t rtc_read(void *opaque, hwaddr addr, unsigned size)
	65	{
	66	uint8_t val;
	67	address_space_read(&address_space_memory, 0x90000071,
	68	MEMTXATTRS_UNSPECIFIED, &val, 1);
	69	return val;
	70	}
	71
	72	static void rtc_write(void *opaque, hwaddr addr,
	73	uint64_t val, unsigned size)
	74	{
	75	uint8_t buf = val & 0xff;
	76	address_space_write(&address_space_memory, 0x90000071,
	77	MEMTXATTRS_UNSPECIFIED, &buf, 1);
	78	}
	79
	80	static const MemoryRegionOps rtc_ops = {
	81	.read = rtc_read,
	82	.write = rtc_write,
	83	.endianness = DEVICE_NATIVE_ENDIAN,
	84	};
	85
	86	static uint64_t dma_dummy_read(void *opaque, hwaddr addr,
	87	unsigned size)
	88	{
	89	/* Nothing to do. That is only to ensure that
	90	* the current DMA acknowledge cycle is completed. */
	91	return 0xff;
	92	}
	93
	94	static void dma_dummy_write(void *opaque, hwaddr addr,
	95	uint64_t val, unsigned size)
	96	{
	97	/* Nothing to do. That is only to ensure that
	98	* the current DMA acknowledge cycle is completed. */
	99	}
	100
	101	static const MemoryRegionOps dma_dummy_ops = {
	102	.read = dma_dummy_read,
	103	.write = dma_dummy_write,
	104	.endianness = DEVICE_NATIVE_ENDIAN,
	105	};
	106
	107	#define MAGNUM_BIOS_SIZE_MAX 0x7e000
	108	#define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
	109
	110	static CPUUnassignedAccess real_do_unassigned_access;
	111	static void mips_jazz_do_unassigned_access(CPUState *cpu, hwaddr addr,
	112	bool is_write, bool is_exec,
	113	int opaque, unsigned size)
	114	{
	115	if (!is_exec) {
	116	/* ignore invalid access (ie do not raise exception) */
	117	return;
	118	}
	119	(*real_do_unassigned_access)(cpu, addr, is_write, is_exec, opaque, size);
	120	}
	121
	122	static void mips_jazz_init(MachineState *machine,
	123	enum jazz_model_e jazz_model)
	124	{
	125	MemoryRegion *address_space = get_system_memory();
	126	char *filename;
	127	int bios_size, n;
	128	MIPSCPU *cpu;
	129	CPUClass *cc;
	130	CPUMIPSState *env;
	131	qemu_irq *i8259;
	132	rc4030_dma *dmas;
	133	IOMMUMemoryRegion *rc4030_dma_mr;
	134	MemoryRegion *isa_mem = g_new(MemoryRegion, 1);
	135	MemoryRegion *isa_io = g_new(MemoryRegion, 1);
	136	MemoryRegion *rtc = g_new(MemoryRegion, 1);
	137	MemoryRegion *i8042 = g_new(MemoryRegion, 1);
	138	MemoryRegion *dma_dummy = g_new(MemoryRegion, 1);
	139	NICInfo *nd;
	140	DeviceState dev, rc4030;
	141	SysBusDevice *sysbus;
	142	ISABus *isa_bus;
	143	ISADevice *pit;
	144	DriveInfo *fds[MAX_FD];
	145	qemu_irq esp_reset, dma_enable;
	146	MemoryRegion *ram = g_new(MemoryRegion, 1);
	147	MemoryRegion *bios = g_new(MemoryRegion, 1);
	148	MemoryRegion *bios2 = g_new(MemoryRegion, 1);
	149	ESPState *esp;
	150
	151	/* init CPUs */
	152	cpu = MIPS_CPU(cpu_create(machine->cpu_type));
	153	env = &cpu->env;
	154	qemu_register_reset(main_cpu_reset, cpu);
	155
	156	/* Chipset returns 0 in invalid reads and do not raise data exceptions.
	157	* However, we can't simply add a global memory region to catch
	158	* everything, as memory core directly call unassigned_mem_read/write
	159	* on some invalid accesses, which call do_unassigned_access on the
	160	* CPU, which raise an exception.
	161	* Handle that case by hijacking the do_unassigned_access method on
	162	* the CPU, and do not raise exceptions for data access. */
	163	cc = CPU_GET_CLASS(cpu);
	164	real_do_unassigned_access = cc->do_unassigned_access;
	165	cc->do_unassigned_access = mips_jazz_do_unassigned_access;
	166
	167	/* allocate RAM */
	168	memory_region_allocate_system_memory(ram, NULL, "mips_jazz.ram",
	169	machine->ram_size);
	170	memory_region_add_subregion(address_space, 0, ram);
	171
	172	memory_region_init_ram(bios, NULL, "mips_jazz.bios", MAGNUM_BIOS_SIZE,
	173	&error_fatal);
	174	memory_region_set_readonly(bios, true);
	175	memory_region_init_alias(bios2, NULL, "mips_jazz.bios", bios,
	176	0, MAGNUM_BIOS_SIZE);
	177	memory_region_add_subregion(address_space, 0x1fc00000LL, bios);
	178	memory_region_add_subregion(address_space, 0xfff00000LL, bios2);
	179
	180	/* load the BIOS image. */
	181	if (bios_name == NULL)
	182	bios_name = BIOS_FILENAME;
	183	filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
	184	if (filename) {
	185	bios_size = load_image_targphys(filename, 0xfff00000LL,
	186	MAGNUM_BIOS_SIZE);
	187	g_free(filename);
	188	} else {
	189	bios_size = -1;
	190	}
	191	if ((bios_size < 0 \|\| bios_size > MAGNUM_BIOS_SIZE) && !qtest_enabled()) {
	192	error_report("Could not load MIPS bios '%s'", bios_name);
	193	exit(1);
	194	}
	195
	196	/* Init CPU internal devices */
	197	cpu_mips_irq_init_cpu(cpu);
	198	cpu_mips_clock_init(cpu);
	199
	200	/* Chipset */
	201	rc4030 = rc4030_init(&dmas, &rc4030_dma_mr);
	202	sysbus = SYS_BUS_DEVICE(rc4030);
	203	sysbus_connect_irq(sysbus, 0, env->irq[6]);
	204	sysbus_connect_irq(sysbus, 1, env->irq[3]);
	205	memory_region_add_subregion(address_space, 0x80000000,
	206	sysbus_mmio_get_region(sysbus, 0));
	207	memory_region_add_subregion(address_space, 0xf0000000,
	208	sysbus_mmio_get_region(sysbus, 1));
	209	memory_region_init_io(dma_dummy, NULL, &dma_dummy_ops, NULL, "dummy_dma", 0x1000);
	210	memory_region_add_subregion(address_space, 0x8000d000, dma_dummy);
	211
	212	/* ISA bus: IO space at 0x90000000, mem space at 0x91000000 */
	213	memory_region_init(isa_io, NULL, "isa-io", 0x00010000);
	214	memory_region_init(isa_mem, NULL, "isa-mem", 0x01000000);
	215	memory_region_add_subregion(address_space, 0x90000000, isa_io);
	216	memory_region_add_subregion(address_space, 0x91000000, isa_mem);
	217	isa_bus = isa_bus_new(NULL, isa_mem, isa_io, &error_abort);
	218
	219	/* ISA devices */
	220	i8259 = i8259_init(isa_bus, env->irq[4]);
	221	isa_bus_irqs(isa_bus, i8259);
	222	DMA_init(isa_bus, 0);
	223	pit = i8254_pit_init(isa_bus, 0x40, 0, NULL);
	224	pcspk_init(isa_bus, pit);
	225
	226	/* Video card */
	227	switch (jazz_model) {
	228	case JAZZ_MAGNUM:
	229	dev = qdev_create(NULL, "sysbus-g364");
	230	qdev_init_nofail(dev);
	231	sysbus = SYS_BUS_DEVICE(dev);
	232	sysbus_mmio_map(sysbus, 0, 0x60080000);
	233	sysbus_mmio_map(sysbus, 1, 0x40000000);
	234	sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 3));
	235	{
	236	/* Simple ROM, so user doesn't have to provide one */
	237	MemoryRegion *rom_mr = g_new(MemoryRegion, 1);
	238	memory_region_init_ram(rom_mr, NULL, "g364fb.rom", 0x80000,
	239	&error_fatal);
	240	memory_region_set_readonly(rom_mr, true);
	241	uint8_t *rom = memory_region_get_ram_ptr(rom_mr);
	242	memory_region_add_subregion(address_space, 0x60000000, rom_mr);
	243	rom[0] = 0x10; /* Mips G364 */
	244	}
	245	break;
	246	case JAZZ_PICA61:
	247	isa_vga_mm_init(0x40000000, 0x60000000, 0, get_system_memory());
	248	break;
	249	default:
	250	break;
	251	}
	252
	253	/* Network controller */
	254	for (n = 0; n < nb_nics; n++) {
	255	nd = &nd_table[n];
	256	if (!nd->model)
	257	nd->model = g_strdup("dp83932");
	258	if (strcmp(nd->model, "dp83932") == 0) {
	259	qemu_check_nic_model(nd, "dp83932");
	260
	261	dev = qdev_create(NULL, "dp8393x");
	262	qdev_set_nic_properties(dev, nd);
	263	qdev_prop_set_uint8(dev, "it_shift", 2);
	264	qdev_prop_set_ptr(dev, "dma_mr", rc4030_dma_mr);
	265	qdev_init_nofail(dev);
	266	sysbus = SYS_BUS_DEVICE(dev);
	267	sysbus_mmio_map(sysbus, 0, 0x80001000);
	268	sysbus_mmio_map(sysbus, 1, 0x8000b000);
	269	sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 4));
	270	break;
	271	} else if (is_help_option(nd->model)) {
	272	error_report("Supported NICs: dp83932");
	273	exit(1);
	274	} else {
	275	error_report("Unsupported NIC: %s", nd->model);
	276	exit(1);
	277	}
	278	}
	279
	280	/* SCSI adapter */
	281	esp = esp_init(0x80002000, 0, rc4030_dma_read, rc4030_dma_write, dmas[0],
	282	qdev_get_gpio_in(rc4030, 5), &esp_reset, &dma_enable);
	283	scsi_bus_legacy_handle_cmdline(&esp->bus);
	284
	285	/* Floppy */
	286	for (n = 0; n < MAX_FD; n++) {
	287	fds[n] = drive_get(IF_FLOPPY, 0, n);
	288	}
	289	/* FIXME: we should enable DMA with a custom IsaDma device */
	290	fdctrl_init_sysbus(qdev_get_gpio_in(rc4030, 1), -1, 0x80003000, fds);
	291
	292	/* Real time clock */
	293	mc146818_rtc_init(isa_bus, 1980, NULL);
	294	memory_region_init_io(rtc, NULL, &rtc_ops, NULL, "rtc", 0x1000);
	295	memory_region_add_subregion(address_space, 0x80004000, rtc);
	296
	297	/* Keyboard (i8042) */
	298	i8042_mm_init(qdev_get_gpio_in(rc4030, 6), qdev_get_gpio_in(rc4030, 7),
	299	i8042, 0x1000, 0x1);
	300	memory_region_add_subregion(address_space, 0x80005000, i8042);
	301
	302	/* Serial ports */
	303	if (serial_hds[0]) {
	304	serial_mm_init(address_space, 0x80006000, 0,
	305	qdev_get_gpio_in(rc4030, 8), 8000000/16,
	306	serial_hds[0], DEVICE_NATIVE_ENDIAN);
	307	}
	308	if (serial_hds[1]) {
	309	serial_mm_init(address_space, 0x80007000, 0,
	310	qdev_get_gpio_in(rc4030, 9), 8000000/16,
	311	serial_hds[1], DEVICE_NATIVE_ENDIAN);
	312	}
	313
	314	/* Parallel port */
	315	if (parallel_hds[0])
	316	parallel_mm_init(address_space, 0x80008000, 0,
	317	qdev_get_gpio_in(rc4030, 0), parallel_hds[0]);
	318
	319	/* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */
	320
	321	/* NVRAM */
	322	dev = qdev_create(NULL, "ds1225y");
	323	qdev_init_nofail(dev);
	324	sysbus = SYS_BUS_DEVICE(dev);
	325	sysbus_mmio_map(sysbus, 0, 0x80009000);
	326
	327	/* LED indicator */
	328	sysbus_create_simple("jazz-led", 0x8000f000, NULL);
	329	}
	330
	331	static
	332	void mips_magnum_init(MachineState *machine)
	333	{
	334	mips_jazz_init(machine, JAZZ_MAGNUM);
	335	}
	336
	337	static
	338	void mips_pica61_init(MachineState *machine)
	339	{
	340	mips_jazz_init(machine, JAZZ_PICA61);
	341	}
	342
	343	static void mips_magnum_class_init(ObjectClass oc, void data)
	344	{
	345	MachineClass *mc = MACHINE_CLASS(oc);
	346
	347	mc->desc = "MIPS Magnum";
	348	mc->init = mips_magnum_init;
	349	mc->block_default_type = IF_SCSI;
	350	mc->default_cpu_type = MIPS_CPU_TYPE_NAME("R4000");
	351	}
	352
	353	static const TypeInfo mips_magnum_type = {
	354	.name = MACHINE_TYPE_NAME("magnum"),
	355	.parent = TYPE_MACHINE,
	356	.class_init = mips_magnum_class_init,
	357	};
	358
	359	static void mips_pica61_class_init(ObjectClass oc, void data)
	360	{
	361	MachineClass *mc = MACHINE_CLASS(oc);
	362
	363	mc->desc = "Acer Pica 61";
	364	mc->init = mips_pica61_init;
	365	mc->block_default_type = IF_SCSI;
	366	mc->default_cpu_type = MIPS_CPU_TYPE_NAME("R4000");
	367	}
	368
	369	static const TypeInfo mips_pica61_type = {
	370	.name = MACHINE_TYPE_NAME("pica61"),
	371	.parent = TYPE_MACHINE,
	372	.class_init = mips_pica61_class_init,
	373	};
	374
	375	static void mips_jazz_machine_init(void)
	376	{
	377	type_register_static(&mips_magnum_type);
	378	type_register_static(&mips_pica61_type);
	379	}
	380
	381	type_init(mips_jazz_machine_init)