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cuda: port POWERDOWN command to new framework
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1/*
2 * QEMU PowerMac CUDA device support
3 *
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25#include "qemu/osdep.h"
26#include "hw/hw.h"
27#include "hw/ppc/mac.h"
28#include "hw/input/adb.h"
29#include "qemu/timer.h"
30#include "sysemu/sysemu.h"
31
32/* XXX: implement all timer modes */
33
34/* debug CUDA */
35//#define DEBUG_CUDA
36
37/* debug CUDA packets */
38//#define DEBUG_CUDA_PACKET
39
40#ifdef DEBUG_CUDA
41#define CUDA_DPRINTF(fmt, ...) \
42 do { printf("CUDA: " fmt , ## __VA_ARGS__); } while (0)
43#else
44#define CUDA_DPRINTF(fmt, ...)
45#endif
46
47/* Bits in B data register: all active low */
48#define TREQ 0x08 /* Transfer request (input) */
49#define TACK 0x10 /* Transfer acknowledge (output) */
50#define TIP 0x20 /* Transfer in progress (output) */
51
52/* Bits in ACR */
53#define SR_CTRL 0x1c /* Shift register control bits */
54#define SR_EXT 0x0c /* Shift on external clock */
55#define SR_OUT 0x10 /* Shift out if 1 */
56
57/* Bits in IFR and IER */
58#define IER_SET 0x80 /* set bits in IER */
59#define IER_CLR 0 /* clear bits in IER */
60#define SR_INT 0x04 /* Shift register full/empty */
61#define SR_DATA_INT 0x08
62#define SR_CLOCK_INT 0x10
63#define T1_INT 0x40 /* Timer 1 interrupt */
64#define T2_INT 0x20 /* Timer 2 interrupt */
65
66/* Bits in ACR */
67#define T1MODE 0xc0 /* Timer 1 mode */
68#define T1MODE_CONT 0x40 /* continuous interrupts */
69
70/* commands (1st byte) */
71#define ADB_PACKET 0
72#define CUDA_PACKET 1
73#define ERROR_PACKET 2
74#define TIMER_PACKET 3
75#define POWER_PACKET 4
76#define MACIIC_PACKET 5
77#define PMU_PACKET 6
78
79
80/* CUDA commands (2nd byte) */
81#define CUDA_WARM_START 0x0
82#define CUDA_AUTOPOLL 0x1
83#define CUDA_GET_6805_ADDR 0x2
84#define CUDA_GET_TIME 0x3
85#define CUDA_GET_PRAM 0x7
86#define CUDA_SET_6805_ADDR 0x8
87#define CUDA_SET_TIME 0x9
88#define CUDA_POWERDOWN 0xa
89#define CUDA_POWERUP_TIME 0xb
90#define CUDA_SET_PRAM 0xc
91#define CUDA_MS_RESET 0xd
92#define CUDA_SEND_DFAC 0xe
93#define CUDA_BATTERY_SWAP_SENSE 0x10
94#define CUDA_RESET_SYSTEM 0x11
95#define CUDA_SET_IPL 0x12
96#define CUDA_FILE_SERVER_FLAG 0x13
97#define CUDA_SET_AUTO_RATE 0x14
98#define CUDA_GET_AUTO_RATE 0x16
99#define CUDA_SET_DEVICE_LIST 0x19
100#define CUDA_GET_DEVICE_LIST 0x1a
101#define CUDA_SET_ONE_SECOND_MODE 0x1b
102#define CUDA_SET_POWER_MESSAGES 0x21
103#define CUDA_GET_SET_IIC 0x22
104#define CUDA_WAKEUP 0x23
105#define CUDA_TIMER_TICKLE 0x24
106#define CUDA_COMBINED_FORMAT_IIC 0x25
107
108#define CUDA_TIMER_FREQ (4700000 / 6)
109
110/* CUDA returns time_t's offset from Jan 1, 1904, not 1970 */
111#define RTC_OFFSET 2082844800
112
113/* CUDA registers */
114#define CUDA_REG_B 0x00
115#define CUDA_REG_A 0x01
116#define CUDA_REG_DIRB 0x02
117#define CUDA_REG_DIRA 0x03
118#define CUDA_REG_T1CL 0x04
119#define CUDA_REG_T1CH 0x05
120#define CUDA_REG_T1LL 0x06
121#define CUDA_REG_T1LH 0x07
122#define CUDA_REG_T2CL 0x08
123#define CUDA_REG_T2CH 0x09
124#define CUDA_REG_SR 0x0a
125#define CUDA_REG_ACR 0x0b
126#define CUDA_REG_PCR 0x0c
127#define CUDA_REG_IFR 0x0d
128#define CUDA_REG_IER 0x0e
129#define CUDA_REG_ANH 0x0f
130
131static void cuda_update(CUDAState *s);
132static void cuda_receive_packet_from_host(CUDAState *s,
133 const uint8_t *data, int len);
134static void cuda_timer_update(CUDAState *s, CUDATimer *ti,
135 int64_t current_time);
136
137static void cuda_update_irq(CUDAState *s)
138{
139 if (s->ifr & s->ier & (SR_INT | T1_INT | T2_INT)) {
140 qemu_irq_raise(s->irq);
141 } else {
142 qemu_irq_lower(s->irq);
143 }
144}
145
146static uint64_t get_tb(uint64_t time, uint64_t freq)
147{
148 return muldiv64(time, freq, get_ticks_per_sec());
149}
150
151static unsigned int get_counter(CUDATimer *ti)
152{
153 int64_t d;
154 unsigned int counter;
155 uint64_t tb_diff;
156 uint64_t current_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
157
158 /* Reverse of the tb calculation algorithm that Mac OS X uses on bootup. */
159 tb_diff = get_tb(current_time, ti->frequency) - ti->load_time;
160 d = (tb_diff * 0xBF401675E5DULL) / (ti->frequency << 24);
161
162 if (ti->index == 0) {
163 /* the timer goes down from latch to -1 (period of latch + 2) */
164 if (d <= (ti->counter_value + 1)) {
165 counter = (ti->counter_value - d) & 0xffff;
166 } else {
167 counter = (d - (ti->counter_value + 1)) % (ti->latch + 2);
168 counter = (ti->latch - counter) & 0xffff;
169 }
170 } else {
171 counter = (ti->counter_value - d) & 0xffff;
172 }
173 return counter;
174}
175
176static void set_counter(CUDAState *s, CUDATimer *ti, unsigned int val)
177{
178 CUDA_DPRINTF("T%d.counter=%d\n", 1 + ti->index, val);
179 ti->load_time = get_tb(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
180 s->frequency);
181 ti->counter_value = val;
182 cuda_timer_update(s, ti, ti->load_time);
183}
184
185static int64_t get_next_irq_time(CUDATimer *s, int64_t current_time)
186{
187 int64_t d, next_time;
188 unsigned int counter;
189
190 /* current counter value */
191 d = muldiv64(current_time - s->load_time,
192 CUDA_TIMER_FREQ, get_ticks_per_sec());
193 /* the timer goes down from latch to -1 (period of latch + 2) */
194 if (d <= (s->counter_value + 1)) {
195 counter = (s->counter_value - d) & 0xffff;
196 } else {
197 counter = (d - (s->counter_value + 1)) % (s->latch + 2);
198 counter = (s->latch - counter) & 0xffff;
199 }
200
201 /* Note: we consider the irq is raised on 0 */
202 if (counter == 0xffff) {
203 next_time = d + s->latch + 1;
204 } else if (counter == 0) {
205 next_time = d + s->latch + 2;
206 } else {
207 next_time = d + counter;
208 }
209 CUDA_DPRINTF("latch=%d counter=%" PRId64 " delta_next=%" PRId64 "\n",
210 s->latch, d, next_time - d);
211 next_time = muldiv64(next_time, get_ticks_per_sec(), CUDA_TIMER_FREQ) +
212 s->load_time;
213 if (next_time <= current_time)
214 next_time = current_time + 1;
215 return next_time;
216}
217
218static void cuda_timer_update(CUDAState *s, CUDATimer *ti,
219 int64_t current_time)
220{
221 if (!ti->timer)
222 return;
223 if (ti->index == 0 && (s->acr & T1MODE) != T1MODE_CONT) {
224 timer_del(ti->timer);
225 } else {
226 ti->next_irq_time = get_next_irq_time(ti, current_time);
227 timer_mod(ti->timer, ti->next_irq_time);
228 }
229}
230
231static void cuda_timer1(void *opaque)
232{
233 CUDAState *s = opaque;
234 CUDATimer *ti = &s->timers[0];
235
236 cuda_timer_update(s, ti, ti->next_irq_time);
237 s->ifr |= T1_INT;
238 cuda_update_irq(s);
239}
240
241static void cuda_timer2(void *opaque)
242{
243 CUDAState *s = opaque;
244 CUDATimer *ti = &s->timers[1];
245
246 cuda_timer_update(s, ti, ti->next_irq_time);
247 s->ifr |= T2_INT;
248 cuda_update_irq(s);
249}
250
251static void cuda_set_sr_int(void *opaque)
252{
253 CUDAState *s = opaque;
254
255 CUDA_DPRINTF("CUDA: %s:%d\n", __func__, __LINE__);
256 s->ifr |= SR_INT;
257 cuda_update_irq(s);
258}
259
260static void cuda_delay_set_sr_int(CUDAState *s)
261{
262 int64_t expire;
263
264 if (s->dirb == 0xff) {
265 /* Not in Mac OS, fire the IRQ directly */
266 cuda_set_sr_int(s);
267 return;
268 }
269
270 CUDA_DPRINTF("CUDA: %s:%d\n", __func__, __LINE__);
271
272 expire = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 300 * SCALE_US;
273 timer_mod(s->sr_delay_timer, expire);
274}
275
276static uint32_t cuda_readb(void *opaque, hwaddr addr)
277{
278 CUDAState *s = opaque;
279 uint32_t val;
280
281 addr = (addr >> 9) & 0xf;
282 switch(addr) {
283 case CUDA_REG_B:
284 val = s->b;
285 break;
286 case CUDA_REG_A:
287 val = s->a;
288 break;
289 case CUDA_REG_DIRB:
290 val = s->dirb;
291 break;
292 case CUDA_REG_DIRA:
293 val = s->dira;
294 break;
295 case CUDA_REG_T1CL:
296 val = get_counter(&s->timers[0]) & 0xff;
297 s->ifr &= ~T1_INT;
298 cuda_update_irq(s);
299 break;
300 case CUDA_REG_T1CH:
301 val = get_counter(&s->timers[0]) >> 8;
302 cuda_update_irq(s);
303 break;
304 case CUDA_REG_T1LL:
305 val = s->timers[0].latch & 0xff;
306 break;
307 case CUDA_REG_T1LH:
308 /* XXX: check this */
309 val = (s->timers[0].latch >> 8) & 0xff;
310 break;
311 case CUDA_REG_T2CL:
312 val = get_counter(&s->timers[1]) & 0xff;
313 s->ifr &= ~T2_INT;
314 cuda_update_irq(s);
315 break;
316 case CUDA_REG_T2CH:
317 val = get_counter(&s->timers[1]) >> 8;
318 break;
319 case CUDA_REG_SR:
320 val = s->sr;
321 s->ifr &= ~(SR_INT | SR_CLOCK_INT | SR_DATA_INT);
322 cuda_update_irq(s);
323 break;
324 case CUDA_REG_ACR:
325 val = s->acr;
326 break;
327 case CUDA_REG_PCR:
328 val = s->pcr;
329 break;
330 case CUDA_REG_IFR:
331 val = s->ifr;
332 if (s->ifr & s->ier) {
333 val |= 0x80;
334 }
335 break;
336 case CUDA_REG_IER:
337 val = s->ier | 0x80;
338 break;
339 default:
340 case CUDA_REG_ANH:
341 val = s->anh;
342 break;
343 }
344 if (addr != CUDA_REG_IFR || val != 0) {
345 CUDA_DPRINTF("read: reg=0x%x val=%02x\n", (int)addr, val);
346 }
347
348 return val;
349}
350
351static void cuda_writeb(void *opaque, hwaddr addr, uint32_t val)
352{
353 CUDAState *s = opaque;
354
355 addr = (addr >> 9) & 0xf;
356 CUDA_DPRINTF("write: reg=0x%x val=%02x\n", (int)addr, val);
357
358 switch(addr) {
359 case CUDA_REG_B:
360 s->b = val;
361 cuda_update(s);
362 break;
363 case CUDA_REG_A:
364 s->a = val;
365 break;
366 case CUDA_REG_DIRB:
367 s->dirb = val;
368 break;
369 case CUDA_REG_DIRA:
370 s->dira = val;
371 break;
372 case CUDA_REG_T1CL:
373 s->timers[0].latch = (s->timers[0].latch & 0xff00) | val;
374 cuda_timer_update(s, &s->timers[0], qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
375 break;
376 case CUDA_REG_T1CH:
377 s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8);
378 s->ifr &= ~T1_INT;
379 set_counter(s, &s->timers[0], s->timers[0].latch);
380 break;
381 case CUDA_REG_T1LL:
382 s->timers[0].latch = (s->timers[0].latch & 0xff00) | val;
383 cuda_timer_update(s, &s->timers[0], qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
384 break;
385 case CUDA_REG_T1LH:
386 s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8);
387 s->ifr &= ~T1_INT;
388 cuda_timer_update(s, &s->timers[0], qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
389 break;
390 case CUDA_REG_T2CL:
391 s->timers[1].latch = (s->timers[1].latch & 0xff00) | val;
392 break;
393 case CUDA_REG_T2CH:
394 /* To ensure T2 generates an interrupt on zero crossing with the
395 common timer code, write the value directly from the latch to
396 the counter */
397 s->timers[1].latch = (s->timers[1].latch & 0xff) | (val << 8);
398 s->ifr &= ~T2_INT;
399 set_counter(s, &s->timers[1], s->timers[1].latch);
400 break;
401 case CUDA_REG_SR:
402 s->sr = val;
403 break;
404 case CUDA_REG_ACR:
405 s->acr = val;
406 cuda_timer_update(s, &s->timers[0], qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
407 cuda_update(s);
408 break;
409 case CUDA_REG_PCR:
410 s->pcr = val;
411 break;
412 case CUDA_REG_IFR:
413 /* reset bits */
414 s->ifr &= ~val;
415 cuda_update_irq(s);
416 break;
417 case CUDA_REG_IER:
418 if (val & IER_SET) {
419 /* set bits */
420 s->ier |= val & 0x7f;
421 } else {
422 /* reset bits */
423 s->ier &= ~val;
424 }
425 cuda_update_irq(s);
426 break;
427 default:
428 case CUDA_REG_ANH:
429 s->anh = val;
430 break;
431 }
432}
433
434/* NOTE: TIP and TREQ are negated */
435static void cuda_update(CUDAState *s)
436{
437 int packet_received, len;
438
439 packet_received = 0;
440 if (!(s->b & TIP)) {
441 /* transfer requested from host */
442
443 if (s->acr & SR_OUT) {
444 /* data output */
445 if ((s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) {
446 if (s->data_out_index < sizeof(s->data_out)) {
447 CUDA_DPRINTF("send: %02x\n", s->sr);
448 s->data_out[s->data_out_index++] = s->sr;
449 cuda_delay_set_sr_int(s);
450 }
451 }
452 } else {
453 if (s->data_in_index < s->data_in_size) {
454 /* data input */
455 if ((s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) {
456 s->sr = s->data_in[s->data_in_index++];
457 CUDA_DPRINTF("recv: %02x\n", s->sr);
458 /* indicate end of transfer */
459 if (s->data_in_index >= s->data_in_size) {
460 s->b = (s->b | TREQ);
461 }
462 cuda_delay_set_sr_int(s);
463 }
464 }
465 }
466 } else {
467 /* no transfer requested: handle sync case */
468 if ((s->last_b & TIP) && (s->b & TACK) != (s->last_b & TACK)) {
469 /* update TREQ state each time TACK change state */
470 if (s->b & TACK)
471 s->b = (s->b | TREQ);
472 else
473 s->b = (s->b & ~TREQ);
474 cuda_delay_set_sr_int(s);
475 } else {
476 if (!(s->last_b & TIP)) {
477 /* handle end of host to cuda transfer */
478 packet_received = (s->data_out_index > 0);
479 /* always an IRQ at the end of transfer */
480 cuda_delay_set_sr_int(s);
481 }
482 /* signal if there is data to read */
483 if (s->data_in_index < s->data_in_size) {
484 s->b = (s->b & ~TREQ);
485 }
486 }
487 }
488
489 s->last_acr = s->acr;
490 s->last_b = s->b;
491
492 /* NOTE: cuda_receive_packet_from_host() can call cuda_update()
493 recursively */
494 if (packet_received) {
495 len = s->data_out_index;
496 s->data_out_index = 0;
497 cuda_receive_packet_from_host(s, s->data_out, len);
498 }
499}
500
501static void cuda_send_packet_to_host(CUDAState *s,
502 const uint8_t *data, int len)
503{
504#ifdef DEBUG_CUDA_PACKET
505 {
506 int i;
507 printf("cuda_send_packet_to_host:\n");
508 for(i = 0; i < len; i++)
509 printf(" %02x", data[i]);
510 printf("\n");
511 }
512#endif
513 memcpy(s->data_in, data, len);
514 s->data_in_size = len;
515 s->data_in_index = 0;
516 cuda_update(s);
517 cuda_delay_set_sr_int(s);
518}
519
520static void cuda_adb_poll(void *opaque)
521{
522 CUDAState *s = opaque;
523 uint8_t obuf[ADB_MAX_OUT_LEN + 2];
524 int olen;
525
526 olen = adb_poll(&s->adb_bus, obuf + 2, s->adb_poll_mask);
527 if (olen > 0) {
528 obuf[0] = ADB_PACKET;
529 obuf[1] = 0x40; /* polled data */
530 cuda_send_packet_to_host(s, obuf, olen + 2);
531 }
532 timer_mod(s->adb_poll_timer,
533 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
534 (get_ticks_per_sec() / (1000 / s->autopoll_rate_ms)));
535}
536
537/* description of commands */
538typedef struct CudaCommand {
539 uint8_t command;
540 const char *name;
541 bool (*handler)(CUDAState *s,
542 const uint8_t *in_args, int in_len,
543 uint8_t *out_args, int *out_len);
544} CudaCommand;
545
546static bool cuda_cmd_autopoll(CUDAState *s,
547 const uint8_t *in_data, int in_len,
548 uint8_t *out_data, int *out_len)
549{
550 int autopoll;
551
552 if (in_len != 1) {
553 return false;
554 }
555
556 autopoll = (in_data[0] != 0);
557 if (autopoll != s->autopoll) {
558 s->autopoll = autopoll;
559 if (autopoll) {
560 timer_mod(s->adb_poll_timer,
561 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
562 (get_ticks_per_sec() / (1000 / s->autopoll_rate_ms)));
563 } else {
564 timer_del(s->adb_poll_timer);
565 }
566 }
567 return true;
568}
569
570static bool cuda_cmd_set_autorate(CUDAState *s,
571 const uint8_t *in_data, int in_len,
572 uint8_t *out_data, int *out_len)
573{
574 if (in_len != 1) {
575 return false;
576 }
577
578 /* we don't want a period of 0 ms */
579 /* FIXME: check what real hardware does */
580 if (in_data[0] == 0) {
581 return false;
582 }
583
584 s->autopoll_rate_ms = in_data[0];
585 if (s->autopoll) {
586 timer_mod(s->adb_poll_timer,
587 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
588 (get_ticks_per_sec() / (1000 / s->autopoll_rate_ms)));
589 }
590 return true;
591}
592
593static bool cuda_cmd_set_device_list(CUDAState *s,
594 const uint8_t *in_data, int in_len,
595 uint8_t *out_data, int *out_len)
596{
597 if (in_len != 2) {
598 return false;
599 }
600
601 s->adb_poll_mask = (((uint16_t)in_data[0]) << 8) | in_data[1];
602 return true;
603}
604
605static bool cuda_cmd_powerdown(CUDAState *s,
606 const uint8_t *in_data, int in_len,
607 uint8_t *out_data, int *out_len)
608{
609 if (in_len != 0) {
610 return false;
611 }
612
613 qemu_system_shutdown_request();
614 return true;
615}
616
617static const CudaCommand handlers[] = {
618 { CUDA_AUTOPOLL, "AUTOPOLL", cuda_cmd_autopoll },
619 { CUDA_SET_AUTO_RATE, "SET_AUTO_RATE", cuda_cmd_set_autorate },
620 { CUDA_SET_DEVICE_LIST, "SET_DEVICE_LIST", cuda_cmd_set_device_list },
621 { CUDA_POWERDOWN, "POWERDOWN", cuda_cmd_powerdown },
622};
623
624static void cuda_receive_packet(CUDAState *s,
625 const uint8_t *data, int len)
626{
627 uint8_t obuf[16] = { CUDA_PACKET, 0, data[0] };
628 int i, out_len = 0;
629 uint32_t ti;
630
631 for (i = 0; i < ARRAY_SIZE(handlers); i++) {
632 const CudaCommand *desc = &handlers[i];
633 if (desc->command == data[0]) {
634 CUDA_DPRINTF("handling command %s\n", desc->name);
635 out_len = 0;
636 if (desc->handler(s, data + 1, len - 1, obuf + 3, &out_len)) {
637 cuda_send_packet_to_host(s, obuf, 3 + out_len);
638 } else {
639 qemu_log_mask(LOG_GUEST_ERROR,
640 "CUDA: %s: wrong parameters %d\n",
641 desc->name, len);
642 obuf[0] = ERROR_PACKET;
643 obuf[1] = 0x5; /* bad parameters */
644 obuf[2] = CUDA_PACKET;
645 obuf[3] = data[0];
646 cuda_send_packet_to_host(s, obuf, 4);
647 }
648 return;
649 }
650 }
651
652 switch(data[0]) {
653 case CUDA_GET_6805_ADDR:
654 cuda_send_packet_to_host(s, obuf, 3);
655 return;
656 case CUDA_SET_TIME:
657 ti = (((uint32_t)data[1]) << 24) + (((uint32_t)data[2]) << 16) + (((uint32_t)data[3]) << 8) + data[4];
658 s->tick_offset = ti - (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / get_ticks_per_sec());
659 cuda_send_packet_to_host(s, obuf, 3);
660 return;
661 case CUDA_GET_TIME:
662 ti = s->tick_offset + (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / get_ticks_per_sec());
663 obuf[3] = ti >> 24;
664 obuf[4] = ti >> 16;
665 obuf[5] = ti >> 8;
666 obuf[6] = ti;
667 cuda_send_packet_to_host(s, obuf, 7);
668 return;
669 case CUDA_FILE_SERVER_FLAG:
670 case CUDA_SET_POWER_MESSAGES:
671 cuda_send_packet_to_host(s, obuf, 3);
672 return;
673 case CUDA_RESET_SYSTEM:
674 cuda_send_packet_to_host(s, obuf, 3);
675 qemu_system_reset_request();
676 return;
677 case CUDA_COMBINED_FORMAT_IIC:
678 obuf[0] = ERROR_PACKET;
679 obuf[1] = 0x5;
680 obuf[2] = CUDA_PACKET;
681 obuf[3] = data[0];
682 cuda_send_packet_to_host(s, obuf, 4);
683 return;
684 case CUDA_GET_SET_IIC:
685 if (len == 4) {
686 cuda_send_packet_to_host(s, obuf, 3);
687 } else {
688 obuf[0] = ERROR_PACKET;
689 obuf[1] = 0x2;
690 obuf[2] = CUDA_PACKET;
691 obuf[3] = data[0];
692 cuda_send_packet_to_host(s, obuf, 4);
693 }
694 return;
695 default:
696 break;
697 }
698
699 qemu_log_mask(LOG_GUEST_ERROR, "CUDA: unknown command 0x%02x\n", data[0]);
700 obuf[0] = ERROR_PACKET;
701 obuf[1] = 0x2; /* unknown command */
702 obuf[2] = CUDA_PACKET;
703 obuf[3] = data[0];
704 cuda_send_packet_to_host(s, obuf, 4);
705}
706
707static void cuda_receive_packet_from_host(CUDAState *s,
708 const uint8_t *data, int len)
709{
710#ifdef DEBUG_CUDA_PACKET
711 {
712 int i;
713 printf("cuda_receive_packet_from_host:\n");
714 for(i = 0; i < len; i++)
715 printf(" %02x", data[i]);
716 printf("\n");
717 }
718#endif
719 switch(data[0]) {
720 case ADB_PACKET:
721 {
722 uint8_t obuf[ADB_MAX_OUT_LEN + 3];
723 int olen;
724 olen = adb_request(&s->adb_bus, obuf + 2, data + 1, len - 1);
725 if (olen > 0) {
726 obuf[0] = ADB_PACKET;
727 obuf[1] = 0x00;
728 cuda_send_packet_to_host(s, obuf, olen + 2);
729 } else {
730 /* error */
731 obuf[0] = ADB_PACKET;
732 obuf[1] = -olen;
733 obuf[2] = data[1];
734 olen = 0;
735 cuda_send_packet_to_host(s, obuf, olen + 3);
736 }
737 }
738 break;
739 case CUDA_PACKET:
740 cuda_receive_packet(s, data + 1, len - 1);
741 break;
742 }
743}
744
745static void cuda_writew (void *opaque, hwaddr addr, uint32_t value)
746{
747}
748
749static void cuda_writel (void *opaque, hwaddr addr, uint32_t value)
750{
751}
752
753static uint32_t cuda_readw (void *opaque, hwaddr addr)
754{
755 return 0;
756}
757
758static uint32_t cuda_readl (void *opaque, hwaddr addr)
759{
760 return 0;
761}
762
763static const MemoryRegionOps cuda_ops = {
764 .old_mmio = {
765 .write = {
766 cuda_writeb,
767 cuda_writew,
768 cuda_writel,
769 },
770 .read = {
771 cuda_readb,
772 cuda_readw,
773 cuda_readl,
774 },
775 },
776 .endianness = DEVICE_NATIVE_ENDIAN,
777};
778
779static bool cuda_timer_exist(void *opaque, int version_id)
780{
781 CUDATimer *s = opaque;
782
783 return s->timer != NULL;
784}
785
786static const VMStateDescription vmstate_cuda_timer = {
787 .name = "cuda_timer",
788 .version_id = 0,
789 .minimum_version_id = 0,
790 .fields = (VMStateField[]) {
791 VMSTATE_UINT16(latch, CUDATimer),
792 VMSTATE_UINT16(counter_value, CUDATimer),
793 VMSTATE_INT64(load_time, CUDATimer),
794 VMSTATE_INT64(next_irq_time, CUDATimer),
795 VMSTATE_TIMER_PTR_TEST(timer, CUDATimer, cuda_timer_exist),
796 VMSTATE_END_OF_LIST()
797 }
798};
799
800static const VMStateDescription vmstate_cuda = {
801 .name = "cuda",
802 .version_id = 4,
803 .minimum_version_id = 4,
804 .fields = (VMStateField[]) {
805 VMSTATE_UINT8(a, CUDAState),
806 VMSTATE_UINT8(b, CUDAState),
807 VMSTATE_UINT8(last_b, CUDAState),
808 VMSTATE_UINT8(dira, CUDAState),
809 VMSTATE_UINT8(dirb, CUDAState),
810 VMSTATE_UINT8(sr, CUDAState),
811 VMSTATE_UINT8(acr, CUDAState),
812 VMSTATE_UINT8(last_acr, CUDAState),
813 VMSTATE_UINT8(pcr, CUDAState),
814 VMSTATE_UINT8(ifr, CUDAState),
815 VMSTATE_UINT8(ier, CUDAState),
816 VMSTATE_UINT8(anh, CUDAState),
817 VMSTATE_INT32(data_in_size, CUDAState),
818 VMSTATE_INT32(data_in_index, CUDAState),
819 VMSTATE_INT32(data_out_index, CUDAState),
820 VMSTATE_UINT8(autopoll, CUDAState),
821 VMSTATE_UINT8(autopoll_rate_ms, CUDAState),
822 VMSTATE_UINT16(adb_poll_mask, CUDAState),
823 VMSTATE_BUFFER(data_in, CUDAState),
824 VMSTATE_BUFFER(data_out, CUDAState),
825 VMSTATE_UINT32(tick_offset, CUDAState),
826 VMSTATE_STRUCT_ARRAY(timers, CUDAState, 2, 1,
827 vmstate_cuda_timer, CUDATimer),
828 VMSTATE_TIMER_PTR(adb_poll_timer, CUDAState),
829 VMSTATE_TIMER_PTR(sr_delay_timer, CUDAState),
830 VMSTATE_END_OF_LIST()
831 }
832};
833
834static void cuda_reset(DeviceState *dev)
835{
836 CUDAState *s = CUDA(dev);
837
838 s->b = 0;
839 s->a = 0;
840 s->dirb = 0xff;
841 s->dira = 0;
842 s->sr = 0;
843 s->acr = 0;
844 s->pcr = 0;
845 s->ifr = 0;
846 s->ier = 0;
847 // s->ier = T1_INT | SR_INT;
848 s->anh = 0;
849 s->data_in_size = 0;
850 s->data_in_index = 0;
851 s->data_out_index = 0;
852 s->autopoll = 0;
853
854 s->timers[0].latch = 0xffff;
855 set_counter(s, &s->timers[0], 0xffff);
856
857 s->timers[1].latch = 0xffff;
858
859 s->sr_delay_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, cuda_set_sr_int, s);
860}
861
862static void cuda_realizefn(DeviceState *dev, Error **errp)
863{
864 CUDAState *s = CUDA(dev);
865 struct tm tm;
866
867 s->timers[0].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, cuda_timer1, s);
868 s->timers[0].frequency = s->frequency;
869 s->timers[1].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, cuda_timer2, s);
870 s->timers[1].frequency = (SCALE_US * 6000) / 4700;
871
872 qemu_get_timedate(&tm, 0);
873 s->tick_offset = (uint32_t)mktimegm(&tm) + RTC_OFFSET;
874
875 s->adb_poll_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, cuda_adb_poll, s);
876 s->autopoll_rate_ms = 20;
877 s->adb_poll_mask = 0xffff;
878}
879
880static void cuda_initfn(Object *obj)
881{
882 SysBusDevice *d = SYS_BUS_DEVICE(obj);
883 CUDAState *s = CUDA(obj);
884 int i;
885
886 memory_region_init_io(&s->mem, obj, &cuda_ops, s, "cuda", 0x2000);
887 sysbus_init_mmio(d, &s->mem);
888 sysbus_init_irq(d, &s->irq);
889
890 for (i = 0; i < ARRAY_SIZE(s->timers); i++) {
891 s->timers[i].index = i;
892 }
893
894 qbus_create_inplace(&s->adb_bus, sizeof(s->adb_bus), TYPE_ADB_BUS,
895 DEVICE(obj), "adb.0");
896}
897
898static Property cuda_properties[] = {
899 DEFINE_PROP_UINT64("frequency", CUDAState, frequency, 0),
900 DEFINE_PROP_END_OF_LIST()
901};
902
903static void cuda_class_init(ObjectClass *oc, void *data)
904{
905 DeviceClass *dc = DEVICE_CLASS(oc);
906
907 dc->realize = cuda_realizefn;
908 dc->reset = cuda_reset;
909 dc->vmsd = &vmstate_cuda;
910 dc->props = cuda_properties;
911 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
912}
913
914static const TypeInfo cuda_type_info = {
915 .name = TYPE_CUDA,
916 .parent = TYPE_SYS_BUS_DEVICE,
917 .instance_size = sizeof(CUDAState),
918 .instance_init = cuda_initfn,
919 .class_init = cuda_class_init,
920};
921
922static void cuda_register_types(void)
923{
924 type_register_static(&cuda_type_info);
925}
926
927type_init(cuda_register_types)
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