]>
Commit | Line | Data |
---|---|---|
1 | /* omap_sx1.c Support for the Siemens SX1 smartphone emulation. | |
2 | * | |
3 | * Copyright (C) 2008 | |
4 | * Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | |
5 | * Copyright (C) 2007 Vladimir Ananiev <vovan888@gmail.com> | |
6 | * | |
7 | * based on PalmOne's (TM) PDAs support (palm.c) | |
8 | */ | |
9 | ||
10 | /* | |
11 | * PalmOne's (TM) PDAs. | |
12 | * | |
13 | * Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org> | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or | |
16 | * modify it under the terms of the GNU General Public License as | |
17 | * published by the Free Software Foundation; either version 2 of | |
18 | * the License, or (at your option) any later version. | |
19 | * | |
20 | * This program is distributed in the hope that it will be useful, | |
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
23 | * GNU General Public License for more details. | |
24 | * | |
25 | * You should have received a copy of the GNU General Public License | |
26 | * along with this program; if not, write to the Free Software | |
27 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
28 | * MA 02111-1307 USA | |
29 | */ | |
30 | #include "hw.h" | |
31 | #include "sysemu.h" | |
32 | #include "console.h" | |
33 | #include "omap.h" | |
34 | #include "boards.h" | |
35 | #include "arm-misc.h" | |
36 | #include "flash.h" | |
37 | ||
38 | /*****************************************************************************/ | |
39 | /* Siemens SX1 Cellphone V1 */ | |
40 | /* - ARM OMAP310 processor | |
41 | * - SRAM 192 kB | |
42 | * - SDRAM 32 MB at 0x10000000 | |
43 | * - Boot flash 16 MB at 0x00000000 | |
44 | * - Application flash 8 MB at 0x04000000 | |
45 | * - 3 serial ports | |
46 | * - 1 SecureDigital | |
47 | * - 1 LCD display | |
48 | * - 1 RTC | |
49 | */ | |
50 | ||
51 | /*****************************************************************************/ | |
52 | /* Siemens SX1 Cellphone V2 */ | |
53 | /* - ARM OMAP310 processor | |
54 | * - SRAM 192 kB | |
55 | * - SDRAM 32 MB at 0x10000000 | |
56 | * - Boot flash 32 MB at 0x00000000 | |
57 | * - 3 serial ports | |
58 | * - 1 SecureDigital | |
59 | * - 1 LCD display | |
60 | * - 1 RTC | |
61 | */ | |
62 | ||
63 | static uint32_t static_readb(void *opaque, target_phys_addr_t offset) | |
64 | { | |
65 | uint32_t *val = (uint32_t *) opaque; | |
66 | ||
67 | return *val >> ((offset & 3) << 3); | |
68 | } | |
69 | ||
70 | static uint32_t static_readh(void *opaque, target_phys_addr_t offset) | |
71 | { | |
72 | uint32_t *val = (uint32_t *) opaque; | |
73 | ||
74 | return *val >> ((offset & 1) << 3); | |
75 | } | |
76 | ||
77 | static uint32_t static_readw(void *opaque, target_phys_addr_t offset) | |
78 | { | |
79 | uint32_t *val = (uint32_t *) opaque; | |
80 | ||
81 | return *val >> ((offset & 0) << 3); | |
82 | } | |
83 | ||
84 | static void static_write(void *opaque, target_phys_addr_t offset, | |
85 | uint32_t value) | |
86 | { | |
87 | #ifdef SPY | |
88 | printf("%s: value %08lx written at " PA_FMT "\n", | |
89 | __FUNCTION__, value, offset); | |
90 | #endif | |
91 | } | |
92 | ||
93 | static CPUReadMemoryFunc *static_readfn[] = { | |
94 | static_readb, | |
95 | static_readh, | |
96 | static_readw, | |
97 | }; | |
98 | ||
99 | static CPUWriteMemoryFunc *static_writefn[] = { | |
100 | static_write, | |
101 | static_write, | |
102 | static_write, | |
103 | }; | |
104 | ||
105 | #define sdram_size 0x02000000 | |
106 | #define sector_size (128 * 1024) | |
107 | #define flash0_size (16 * 1024 * 1024) | |
108 | #define flash1_size ( 8 * 1024 * 1024) | |
109 | #define flash2_size (32 * 1024 * 1024) | |
110 | #define total_ram_v1 (sdram_size + flash0_size + flash1_size + OMAP15XX_SRAM_SIZE) | |
111 | #define total_ram_v2 (sdram_size + flash2_size + OMAP15XX_SRAM_SIZE) | |
112 | ||
113 | static struct arm_boot_info sx1_binfo = { | |
114 | .loader_start = OMAP_EMIFF_BASE, | |
115 | .ram_size = sdram_size, | |
116 | .board_id = 0x265, | |
117 | }; | |
118 | ||
119 | static void sx1_init(ram_addr_t ram_size, int vga_ram_size, | |
120 | const char *boot_device, DisplayState *ds, | |
121 | const char *kernel_filename, const char *kernel_cmdline, | |
122 | const char *initrd_filename, const char *cpu_model, | |
123 | const int version) | |
124 | { | |
125 | struct omap_mpu_state_s *cpu; | |
126 | int io; | |
127 | static uint32_t cs0val = 0x00213090; | |
128 | static uint32_t cs1val = 0x00215070; | |
129 | static uint32_t cs2val = 0x00001139; | |
130 | static uint32_t cs3val = 0x00001139; | |
131 | ram_addr_t phys_flash; | |
132 | int index; | |
133 | int fl_idx; | |
134 | uint32_t flash_size = flash0_size; | |
135 | ||
136 | if (version == 2) { | |
137 | flash_size = flash2_size; | |
138 | } | |
139 | ||
140 | cpu = omap310_mpu_init(sx1_binfo.ram_size, ds, cpu_model); | |
141 | ||
142 | /* External Flash (EMIFS) */ | |
143 | cpu_register_physical_memory(OMAP_CS0_BASE, flash_size, | |
144 | (phys_flash = qemu_ram_alloc(flash_size)) | IO_MEM_ROM); | |
145 | ||
146 | io = cpu_register_io_memory(0, static_readfn, static_writefn, &cs0val); | |
147 | cpu_register_physical_memory(OMAP_CS0_BASE + flash_size, | |
148 | OMAP_CS0_SIZE - flash_size, io); | |
149 | io = cpu_register_io_memory(0, static_readfn, static_writefn, &cs2val); | |
150 | cpu_register_physical_memory(OMAP_CS2_BASE, OMAP_CS2_SIZE, io); | |
151 | io = cpu_register_io_memory(0, static_readfn, static_writefn, &cs3val); | |
152 | cpu_register_physical_memory(OMAP_CS3_BASE, OMAP_CS3_SIZE, io); | |
153 | ||
154 | fl_idx = 0; | |
155 | ||
156 | if ((index = drive_get_index(IF_PFLASH, 0, fl_idx)) > -1) { | |
157 | if (!pflash_cfi01_register(OMAP_CS0_BASE, qemu_ram_alloc(flash_size), | |
158 | drives_table[index].bdrv, sector_size, flash_size / sector_size, | |
159 | 4, 0, 0, 0, 0)) { | |
160 | fprintf(stderr, "qemu: Error registering flash memory %d.\n", | |
161 | fl_idx); | |
162 | } | |
163 | fl_idx++; | |
164 | } | |
165 | ||
166 | if ((version == 1) && | |
167 | (index = drive_get_index(IF_PFLASH, 0, fl_idx)) > -1) { | |
168 | cpu_register_physical_memory(OMAP_CS1_BASE, flash1_size, | |
169 | (phys_flash = qemu_ram_alloc(flash1_size)) | | |
170 | IO_MEM_ROM); | |
171 | io = cpu_register_io_memory(0, static_readfn, static_writefn, &cs1val); | |
172 | cpu_register_physical_memory(OMAP_CS1_BASE + flash1_size, | |
173 | OMAP_CS1_SIZE - flash1_size, io); | |
174 | ||
175 | if (!pflash_cfi01_register(OMAP_CS1_BASE, qemu_ram_alloc(flash1_size), | |
176 | drives_table[index].bdrv, sector_size, flash1_size / sector_size, | |
177 | 4, 0, 0, 0, 0)) { | |
178 | fprintf(stderr, "qemu: Error registering flash memory %d.\n", | |
179 | fl_idx); | |
180 | } | |
181 | fl_idx++; | |
182 | } else { | |
183 | io = cpu_register_io_memory(0, static_readfn, static_writefn, &cs1val); | |
184 | cpu_register_physical_memory(OMAP_CS1_BASE, OMAP_CS1_SIZE, io); | |
185 | } | |
186 | ||
187 | if (!kernel_filename && !fl_idx) { | |
188 | fprintf(stderr, "Kernel or Flash image must be specified\n"); | |
189 | exit(1); | |
190 | } | |
191 | ||
192 | /* Load the kernel. */ | |
193 | if (kernel_filename) { | |
194 | /* Start at bootloader. */ | |
195 | cpu->env->regs[15] = sx1_binfo.loader_start; | |
196 | ||
197 | sx1_binfo.kernel_filename = kernel_filename; | |
198 | sx1_binfo.kernel_cmdline = kernel_cmdline; | |
199 | sx1_binfo.initrd_filename = initrd_filename; | |
200 | arm_load_kernel(cpu->env, &sx1_binfo); | |
201 | } else { | |
202 | cpu->env->regs[15] = 0x00000000; | |
203 | } | |
204 | ||
205 | dpy_resize(ds, 640, 480); | |
206 | } | |
207 | ||
208 | static void sx1_init_v1(ram_addr_t ram_size, int vga_ram_size, | |
209 | const char *boot_device, DisplayState *ds, | |
210 | const char *kernel_filename, const char *kernel_cmdline, | |
211 | const char *initrd_filename, const char *cpu_model) | |
212 | { | |
213 | sx1_init(ram_size, vga_ram_size, boot_device, ds, kernel_filename, | |
214 | kernel_cmdline, initrd_filename, cpu_model, 1); | |
215 | } | |
216 | ||
217 | static void sx1_init_v2(ram_addr_t ram_size, int vga_ram_size, | |
218 | const char *boot_device, DisplayState *ds, | |
219 | const char *kernel_filename, const char *kernel_cmdline, | |
220 | const char *initrd_filename, const char *cpu_model) | |
221 | { | |
222 | sx1_init(ram_size, vga_ram_size, boot_device, ds, kernel_filename, | |
223 | kernel_cmdline, initrd_filename, cpu_model, 2); | |
224 | } | |
225 | ||
226 | QEMUMachine sx1_machine_v2 = { | |
227 | .name = "sx1", | |
228 | .desc = "Siemens SX1 (OMAP310) V2", | |
229 | .init = sx1_init_v2, | |
230 | .ram_require = total_ram_v2 | RAMSIZE_FIXED, | |
231 | }; | |
232 | ||
233 | QEMUMachine sx1_machine_v1 = { | |
234 | .name = "sx1-v1", | |
235 | .desc = "Siemens SX1 (OMAP310) V1", | |
236 | .init = sx1_init_v1, | |
237 | .ram_require = total_ram_v1 | RAMSIZE_FIXED, | |
238 | }; |