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1 | /* | |
2 | * QEMU PC System Emulator | |
3 | * | |
4 | * Copyright (c) 2003-2004 Fabrice Bellard | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | #include "hw.h" | |
25 | #include "pc.h" | |
26 | #include "apic.h" | |
27 | #include "fdc.h" | |
28 | #include "pci.h" | |
29 | #include "vmware_vga.h" | |
30 | #include "monitor.h" | |
31 | #include "fw_cfg.h" | |
32 | #include "hpet_emul.h" | |
33 | #include "smbios.h" | |
34 | #include "loader.h" | |
35 | #include "elf.h" | |
36 | #include "multiboot.h" | |
37 | #include "mc146818rtc.h" | |
38 | #include "sysbus.h" | |
39 | #include "sysemu.h" | |
40 | ||
41 | /* output Bochs bios info messages */ | |
42 | //#define DEBUG_BIOS | |
43 | ||
44 | /* debug PC/ISA interrupts */ | |
45 | //#define DEBUG_IRQ | |
46 | ||
47 | #ifdef DEBUG_IRQ | |
48 | #define DPRINTF(fmt, ...) \ | |
49 | do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) | |
50 | #else | |
51 | #define DPRINTF(fmt, ...) | |
52 | #endif | |
53 | ||
54 | #define BIOS_FILENAME "bios.bin" | |
55 | ||
56 | #define PC_MAX_BIOS_SIZE (4 * 1024 * 1024) | |
57 | ||
58 | /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables. */ | |
59 | #define ACPI_DATA_SIZE 0x10000 | |
60 | #define BIOS_CFG_IOPORT 0x510 | |
61 | #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) | |
62 | #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) | |
63 | #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2) | |
64 | #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3) | |
65 | #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4) | |
66 | ||
67 | #define E820_NR_ENTRIES 16 | |
68 | ||
69 | struct e820_entry { | |
70 | uint64_t address; | |
71 | uint64_t length; | |
72 | uint32_t type; | |
73 | }; | |
74 | ||
75 | struct e820_table { | |
76 | uint32_t count; | |
77 | struct e820_entry entry[E820_NR_ENTRIES]; | |
78 | }; | |
79 | ||
80 | static struct e820_table e820_table; | |
81 | ||
82 | void isa_irq_handler(void *opaque, int n, int level) | |
83 | { | |
84 | IsaIrqState *isa = (IsaIrqState *)opaque; | |
85 | ||
86 | DPRINTF("isa_irqs: %s irq %d\n", level? "raise" : "lower", n); | |
87 | if (n < 16) { | |
88 | qemu_set_irq(isa->i8259[n], level); | |
89 | } | |
90 | if (isa->ioapic) | |
91 | qemu_set_irq(isa->ioapic[n], level); | |
92 | }; | |
93 | ||
94 | static void ioport80_write(void *opaque, uint32_t addr, uint32_t data) | |
95 | { | |
96 | } | |
97 | ||
98 | /* MSDOS compatibility mode FPU exception support */ | |
99 | static qemu_irq ferr_irq; | |
100 | ||
101 | void pc_register_ferr_irq(qemu_irq irq) | |
102 | { | |
103 | ferr_irq = irq; | |
104 | } | |
105 | ||
106 | /* XXX: add IGNNE support */ | |
107 | void cpu_set_ferr(CPUX86State *s) | |
108 | { | |
109 | qemu_irq_raise(ferr_irq); | |
110 | } | |
111 | ||
112 | static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data) | |
113 | { | |
114 | qemu_irq_lower(ferr_irq); | |
115 | } | |
116 | ||
117 | /* TSC handling */ | |
118 | uint64_t cpu_get_tsc(CPUX86State *env) | |
119 | { | |
120 | return cpu_get_ticks(); | |
121 | } | |
122 | ||
123 | /* SMM support */ | |
124 | ||
125 | static cpu_set_smm_t smm_set; | |
126 | static void *smm_arg; | |
127 | ||
128 | void cpu_smm_register(cpu_set_smm_t callback, void *arg) | |
129 | { | |
130 | assert(smm_set == NULL); | |
131 | assert(smm_arg == NULL); | |
132 | smm_set = callback; | |
133 | smm_arg = arg; | |
134 | } | |
135 | ||
136 | void cpu_smm_update(CPUState *env) | |
137 | { | |
138 | if (smm_set && smm_arg && env == first_cpu) | |
139 | smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg); | |
140 | } | |
141 | ||
142 | ||
143 | /* IRQ handling */ | |
144 | int cpu_get_pic_interrupt(CPUState *env) | |
145 | { | |
146 | int intno; | |
147 | ||
148 | intno = apic_get_interrupt(env); | |
149 | if (intno >= 0) { | |
150 | /* set irq request if a PIC irq is still pending */ | |
151 | /* XXX: improve that */ | |
152 | pic_update_irq(isa_pic); | |
153 | return intno; | |
154 | } | |
155 | /* read the irq from the PIC */ | |
156 | if (!apic_accept_pic_intr(env)) | |
157 | return -1; | |
158 | ||
159 | intno = pic_read_irq(isa_pic); | |
160 | return intno; | |
161 | } | |
162 | ||
163 | static void pic_irq_request(void *opaque, int irq, int level) | |
164 | { | |
165 | CPUState *env = first_cpu; | |
166 | ||
167 | DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); | |
168 | if (env->apic_state) { | |
169 | while (env) { | |
170 | if (apic_accept_pic_intr(env)) | |
171 | apic_deliver_pic_intr(env, level); | |
172 | env = env->next_cpu; | |
173 | } | |
174 | } else { | |
175 | if (level) | |
176 | cpu_interrupt(env, CPU_INTERRUPT_HARD); | |
177 | else | |
178 | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); | |
179 | } | |
180 | } | |
181 | ||
182 | /* PC cmos mappings */ | |
183 | ||
184 | #define REG_EQUIPMENT_BYTE 0x14 | |
185 | ||
186 | static int cmos_get_fd_drive_type(int fd0) | |
187 | { | |
188 | int val; | |
189 | ||
190 | switch (fd0) { | |
191 | case 0: | |
192 | /* 1.44 Mb 3"5 drive */ | |
193 | val = 4; | |
194 | break; | |
195 | case 1: | |
196 | /* 2.88 Mb 3"5 drive */ | |
197 | val = 5; | |
198 | break; | |
199 | case 2: | |
200 | /* 1.2 Mb 5"5 drive */ | |
201 | val = 2; | |
202 | break; | |
203 | default: | |
204 | val = 0; | |
205 | break; | |
206 | } | |
207 | return val; | |
208 | } | |
209 | ||
210 | static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd, | |
211 | ISADevice *s) | |
212 | { | |
213 | int cylinders, heads, sectors; | |
214 | bdrv_get_geometry_hint(hd, &cylinders, &heads, §ors); | |
215 | rtc_set_memory(s, type_ofs, 47); | |
216 | rtc_set_memory(s, info_ofs, cylinders); | |
217 | rtc_set_memory(s, info_ofs + 1, cylinders >> 8); | |
218 | rtc_set_memory(s, info_ofs + 2, heads); | |
219 | rtc_set_memory(s, info_ofs + 3, 0xff); | |
220 | rtc_set_memory(s, info_ofs + 4, 0xff); | |
221 | rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); | |
222 | rtc_set_memory(s, info_ofs + 6, cylinders); | |
223 | rtc_set_memory(s, info_ofs + 7, cylinders >> 8); | |
224 | rtc_set_memory(s, info_ofs + 8, sectors); | |
225 | } | |
226 | ||
227 | /* convert boot_device letter to something recognizable by the bios */ | |
228 | static int boot_device2nibble(char boot_device) | |
229 | { | |
230 | switch(boot_device) { | |
231 | case 'a': | |
232 | case 'b': | |
233 | return 0x01; /* floppy boot */ | |
234 | case 'c': | |
235 | return 0x02; /* hard drive boot */ | |
236 | case 'd': | |
237 | return 0x03; /* CD-ROM boot */ | |
238 | case 'n': | |
239 | return 0x04; /* Network boot */ | |
240 | } | |
241 | return 0; | |
242 | } | |
243 | ||
244 | static int set_boot_dev(ISADevice *s, const char *boot_device, int fd_bootchk) | |
245 | { | |
246 | #define PC_MAX_BOOT_DEVICES 3 | |
247 | int nbds, bds[3] = { 0, }; | |
248 | int i; | |
249 | ||
250 | nbds = strlen(boot_device); | |
251 | if (nbds > PC_MAX_BOOT_DEVICES) { | |
252 | error_report("Too many boot devices for PC"); | |
253 | return(1); | |
254 | } | |
255 | for (i = 0; i < nbds; i++) { | |
256 | bds[i] = boot_device2nibble(boot_device[i]); | |
257 | if (bds[i] == 0) { | |
258 | error_report("Invalid boot device for PC: '%c'", | |
259 | boot_device[i]); | |
260 | return(1); | |
261 | } | |
262 | } | |
263 | rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); | |
264 | rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); | |
265 | return(0); | |
266 | } | |
267 | ||
268 | static int pc_boot_set(void *opaque, const char *boot_device) | |
269 | { | |
270 | return set_boot_dev(opaque, boot_device, 0); | |
271 | } | |
272 | ||
273 | /* hd_table must contain 4 block drivers */ | |
274 | void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size, | |
275 | const char *boot_device, DriveInfo **hd_table, | |
276 | FDCtrl *floppy_controller, ISADevice *s) | |
277 | { | |
278 | int val; | |
279 | int fd0, fd1, nb; | |
280 | int i; | |
281 | ||
282 | /* various important CMOS locations needed by PC/Bochs bios */ | |
283 | ||
284 | /* memory size */ | |
285 | val = 640; /* base memory in K */ | |
286 | rtc_set_memory(s, 0x15, val); | |
287 | rtc_set_memory(s, 0x16, val >> 8); | |
288 | ||
289 | val = (ram_size / 1024) - 1024; | |
290 | if (val > 65535) | |
291 | val = 65535; | |
292 | rtc_set_memory(s, 0x17, val); | |
293 | rtc_set_memory(s, 0x18, val >> 8); | |
294 | rtc_set_memory(s, 0x30, val); | |
295 | rtc_set_memory(s, 0x31, val >> 8); | |
296 | ||
297 | if (above_4g_mem_size) { | |
298 | rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16); | |
299 | rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24); | |
300 | rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32); | |
301 | } | |
302 | ||
303 | if (ram_size > (16 * 1024 * 1024)) | |
304 | val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536); | |
305 | else | |
306 | val = 0; | |
307 | if (val > 65535) | |
308 | val = 65535; | |
309 | rtc_set_memory(s, 0x34, val); | |
310 | rtc_set_memory(s, 0x35, val >> 8); | |
311 | ||
312 | /* set the number of CPU */ | |
313 | rtc_set_memory(s, 0x5f, smp_cpus - 1); | |
314 | ||
315 | /* set boot devices, and disable floppy signature check if requested */ | |
316 | if (set_boot_dev(s, boot_device, fd_bootchk)) { | |
317 | exit(1); | |
318 | } | |
319 | ||
320 | /* floppy type */ | |
321 | ||
322 | fd0 = fdctrl_get_drive_type(floppy_controller, 0); | |
323 | fd1 = fdctrl_get_drive_type(floppy_controller, 1); | |
324 | ||
325 | val = (cmos_get_fd_drive_type(fd0) << 4) | cmos_get_fd_drive_type(fd1); | |
326 | rtc_set_memory(s, 0x10, val); | |
327 | ||
328 | val = 0; | |
329 | nb = 0; | |
330 | if (fd0 < 3) | |
331 | nb++; | |
332 | if (fd1 < 3) | |
333 | nb++; | |
334 | switch (nb) { | |
335 | case 0: | |
336 | break; | |
337 | case 1: | |
338 | val |= 0x01; /* 1 drive, ready for boot */ | |
339 | break; | |
340 | case 2: | |
341 | val |= 0x41; /* 2 drives, ready for boot */ | |
342 | break; | |
343 | } | |
344 | val |= 0x02; /* FPU is there */ | |
345 | val |= 0x04; /* PS/2 mouse installed */ | |
346 | rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); | |
347 | ||
348 | /* hard drives */ | |
349 | ||
350 | rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0)); | |
351 | if (hd_table[0]) | |
352 | cmos_init_hd(0x19, 0x1b, hd_table[0]->bdrv, s); | |
353 | if (hd_table[1]) | |
354 | cmos_init_hd(0x1a, 0x24, hd_table[1]->bdrv, s); | |
355 | ||
356 | val = 0; | |
357 | for (i = 0; i < 4; i++) { | |
358 | if (hd_table[i]) { | |
359 | int cylinders, heads, sectors, translation; | |
360 | /* NOTE: bdrv_get_geometry_hint() returns the physical | |
361 | geometry. It is always such that: 1 <= sects <= 63, 1 | |
362 | <= heads <= 16, 1 <= cylinders <= 16383. The BIOS | |
363 | geometry can be different if a translation is done. */ | |
364 | translation = bdrv_get_translation_hint(hd_table[i]->bdrv); | |
365 | if (translation == BIOS_ATA_TRANSLATION_AUTO) { | |
366 | bdrv_get_geometry_hint(hd_table[i]->bdrv, &cylinders, &heads, §ors); | |
367 | if (cylinders <= 1024 && heads <= 16 && sectors <= 63) { | |
368 | /* No translation. */ | |
369 | translation = 0; | |
370 | } else { | |
371 | /* LBA translation. */ | |
372 | translation = 1; | |
373 | } | |
374 | } else { | |
375 | translation--; | |
376 | } | |
377 | val |= translation << (i * 2); | |
378 | } | |
379 | } | |
380 | rtc_set_memory(s, 0x39, val); | |
381 | } | |
382 | ||
383 | static void handle_a20_line_change(void *opaque, int irq, int level) | |
384 | { | |
385 | CPUState *cpu = opaque; | |
386 | ||
387 | /* XXX: send to all CPUs ? */ | |
388 | cpu_x86_set_a20(cpu, level); | |
389 | } | |
390 | ||
391 | /***********************************************************/ | |
392 | /* Bochs BIOS debug ports */ | |
393 | ||
394 | static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val) | |
395 | { | |
396 | static const char shutdown_str[8] = "Shutdown"; | |
397 | static int shutdown_index = 0; | |
398 | ||
399 | switch(addr) { | |
400 | /* Bochs BIOS messages */ | |
401 | case 0x400: | |
402 | case 0x401: | |
403 | fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val); | |
404 | exit(1); | |
405 | case 0x402: | |
406 | case 0x403: | |
407 | #ifdef DEBUG_BIOS | |
408 | fprintf(stderr, "%c", val); | |
409 | #endif | |
410 | break; | |
411 | case 0x8900: | |
412 | /* same as Bochs power off */ | |
413 | if (val == shutdown_str[shutdown_index]) { | |
414 | shutdown_index++; | |
415 | if (shutdown_index == 8) { | |
416 | shutdown_index = 0; | |
417 | qemu_system_shutdown_request(); | |
418 | } | |
419 | } else { | |
420 | shutdown_index = 0; | |
421 | } | |
422 | break; | |
423 | ||
424 | /* LGPL'ed VGA BIOS messages */ | |
425 | case 0x501: | |
426 | case 0x502: | |
427 | fprintf(stderr, "VGA BIOS panic, line %d\n", val); | |
428 | exit(1); | |
429 | case 0x500: | |
430 | case 0x503: | |
431 | #ifdef DEBUG_BIOS | |
432 | fprintf(stderr, "%c", val); | |
433 | #endif | |
434 | break; | |
435 | } | |
436 | } | |
437 | ||
438 | int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) | |
439 | { | |
440 | int index = e820_table.count; | |
441 | struct e820_entry *entry; | |
442 | ||
443 | if (index >= E820_NR_ENTRIES) | |
444 | return -EBUSY; | |
445 | entry = &e820_table.entry[index]; | |
446 | ||
447 | entry->address = address; | |
448 | entry->length = length; | |
449 | entry->type = type; | |
450 | ||
451 | e820_table.count++; | |
452 | return e820_table.count; | |
453 | } | |
454 | ||
455 | static void *bochs_bios_init(void) | |
456 | { | |
457 | void *fw_cfg; | |
458 | uint8_t *smbios_table; | |
459 | size_t smbios_len; | |
460 | uint64_t *numa_fw_cfg; | |
461 | int i, j; | |
462 | ||
463 | register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL); | |
464 | register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL); | |
465 | register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL); | |
466 | register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL); | |
467 | register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL); | |
468 | ||
469 | register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL); | |
470 | register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL); | |
471 | register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL); | |
472 | register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL); | |
473 | ||
474 | fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0); | |
475 | ||
476 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); | |
477 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); | |
478 | fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables, | |
479 | acpi_tables_len); | |
480 | fw_cfg_add_bytes(fw_cfg, FW_CFG_IRQ0_OVERRIDE, &irq0override, 1); | |
481 | ||
482 | smbios_table = smbios_get_table(&smbios_len); | |
483 | if (smbios_table) | |
484 | fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES, | |
485 | smbios_table, smbios_len); | |
486 | fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, (uint8_t *)&e820_table, | |
487 | sizeof(struct e820_table)); | |
488 | ||
489 | fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, (uint8_t *)&hpet_cfg, | |
490 | sizeof(struct hpet_fw_config)); | |
491 | /* allocate memory for the NUMA channel: one (64bit) word for the number | |
492 | * of nodes, one word for each VCPU->node and one word for each node to | |
493 | * hold the amount of memory. | |
494 | */ | |
495 | numa_fw_cfg = qemu_mallocz((1 + smp_cpus + nb_numa_nodes) * 8); | |
496 | numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); | |
497 | for (i = 0; i < smp_cpus; i++) { | |
498 | for (j = 0; j < nb_numa_nodes; j++) { | |
499 | if (node_cpumask[j] & (1 << i)) { | |
500 | numa_fw_cfg[i + 1] = cpu_to_le64(j); | |
501 | break; | |
502 | } | |
503 | } | |
504 | } | |
505 | for (i = 0; i < nb_numa_nodes; i++) { | |
506 | numa_fw_cfg[smp_cpus + 1 + i] = cpu_to_le64(node_mem[i]); | |
507 | } | |
508 | fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg, | |
509 | (1 + smp_cpus + nb_numa_nodes) * 8); | |
510 | ||
511 | return fw_cfg; | |
512 | } | |
513 | ||
514 | static long get_file_size(FILE *f) | |
515 | { | |
516 | long where, size; | |
517 | ||
518 | /* XXX: on Unix systems, using fstat() probably makes more sense */ | |
519 | ||
520 | where = ftell(f); | |
521 | fseek(f, 0, SEEK_END); | |
522 | size = ftell(f); | |
523 | fseek(f, where, SEEK_SET); | |
524 | ||
525 | return size; | |
526 | } | |
527 | ||
528 | static void load_linux(void *fw_cfg, | |
529 | const char *kernel_filename, | |
530 | const char *initrd_filename, | |
531 | const char *kernel_cmdline, | |
532 | target_phys_addr_t max_ram_size) | |
533 | { | |
534 | uint16_t protocol; | |
535 | int setup_size, kernel_size, initrd_size = 0, cmdline_size; | |
536 | uint32_t initrd_max; | |
537 | uint8_t header[8192], *setup, *kernel, *initrd_data; | |
538 | target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr = 0; | |
539 | FILE *f; | |
540 | char *vmode; | |
541 | ||
542 | /* Align to 16 bytes as a paranoia measure */ | |
543 | cmdline_size = (strlen(kernel_cmdline)+16) & ~15; | |
544 | ||
545 | /* load the kernel header */ | |
546 | f = fopen(kernel_filename, "rb"); | |
547 | if (!f || !(kernel_size = get_file_size(f)) || | |
548 | fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != | |
549 | MIN(ARRAY_SIZE(header), kernel_size)) { | |
550 | fprintf(stderr, "qemu: could not load kernel '%s': %s\n", | |
551 | kernel_filename, strerror(errno)); | |
552 | exit(1); | |
553 | } | |
554 | ||
555 | /* kernel protocol version */ | |
556 | #if 0 | |
557 | fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); | |
558 | #endif | |
559 | if (ldl_p(header+0x202) == 0x53726448) | |
560 | protocol = lduw_p(header+0x206); | |
561 | else { | |
562 | /* This looks like a multiboot kernel. If it is, let's stop | |
563 | treating it like a Linux kernel. */ | |
564 | if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename, | |
565 | kernel_cmdline, kernel_size, header)) | |
566 | return; | |
567 | protocol = 0; | |
568 | } | |
569 | ||
570 | if (protocol < 0x200 || !(header[0x211] & 0x01)) { | |
571 | /* Low kernel */ | |
572 | real_addr = 0x90000; | |
573 | cmdline_addr = 0x9a000 - cmdline_size; | |
574 | prot_addr = 0x10000; | |
575 | } else if (protocol < 0x202) { | |
576 | /* High but ancient kernel */ | |
577 | real_addr = 0x90000; | |
578 | cmdline_addr = 0x9a000 - cmdline_size; | |
579 | prot_addr = 0x100000; | |
580 | } else { | |
581 | /* High and recent kernel */ | |
582 | real_addr = 0x10000; | |
583 | cmdline_addr = 0x20000; | |
584 | prot_addr = 0x100000; | |
585 | } | |
586 | ||
587 | #if 0 | |
588 | fprintf(stderr, | |
589 | "qemu: real_addr = 0x" TARGET_FMT_plx "\n" | |
590 | "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n" | |
591 | "qemu: prot_addr = 0x" TARGET_FMT_plx "\n", | |
592 | real_addr, | |
593 | cmdline_addr, | |
594 | prot_addr); | |
595 | #endif | |
596 | ||
597 | /* highest address for loading the initrd */ | |
598 | if (protocol >= 0x203) | |
599 | initrd_max = ldl_p(header+0x22c); | |
600 | else | |
601 | initrd_max = 0x37ffffff; | |
602 | ||
603 | if (initrd_max >= max_ram_size-ACPI_DATA_SIZE) | |
604 | initrd_max = max_ram_size-ACPI_DATA_SIZE-1; | |
605 | ||
606 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); | |
607 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1); | |
608 | fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA, | |
609 | (uint8_t*)strdup(kernel_cmdline), | |
610 | strlen(kernel_cmdline)+1); | |
611 | ||
612 | if (protocol >= 0x202) { | |
613 | stl_p(header+0x228, cmdline_addr); | |
614 | } else { | |
615 | stw_p(header+0x20, 0xA33F); | |
616 | stw_p(header+0x22, cmdline_addr-real_addr); | |
617 | } | |
618 | ||
619 | /* handle vga= parameter */ | |
620 | vmode = strstr(kernel_cmdline, "vga="); | |
621 | if (vmode) { | |
622 | unsigned int video_mode; | |
623 | /* skip "vga=" */ | |
624 | vmode += 4; | |
625 | if (!strncmp(vmode, "normal", 6)) { | |
626 | video_mode = 0xffff; | |
627 | } else if (!strncmp(vmode, "ext", 3)) { | |
628 | video_mode = 0xfffe; | |
629 | } else if (!strncmp(vmode, "ask", 3)) { | |
630 | video_mode = 0xfffd; | |
631 | } else { | |
632 | video_mode = strtol(vmode, NULL, 0); | |
633 | } | |
634 | stw_p(header+0x1fa, video_mode); | |
635 | } | |
636 | ||
637 | /* loader type */ | |
638 | /* High nybble = B reserved for Qemu; low nybble is revision number. | |
639 | If this code is substantially changed, you may want to consider | |
640 | incrementing the revision. */ | |
641 | if (protocol >= 0x200) | |
642 | header[0x210] = 0xB0; | |
643 | ||
644 | /* heap */ | |
645 | if (protocol >= 0x201) { | |
646 | header[0x211] |= 0x80; /* CAN_USE_HEAP */ | |
647 | stw_p(header+0x224, cmdline_addr-real_addr-0x200); | |
648 | } | |
649 | ||
650 | /* load initrd */ | |
651 | if (initrd_filename) { | |
652 | if (protocol < 0x200) { | |
653 | fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); | |
654 | exit(1); | |
655 | } | |
656 | ||
657 | initrd_size = get_image_size(initrd_filename); | |
658 | if (initrd_size < 0) { | |
659 | fprintf(stderr, "qemu: error reading initrd %s\n", | |
660 | initrd_filename); | |
661 | exit(1); | |
662 | } | |
663 | ||
664 | initrd_addr = (initrd_max-initrd_size) & ~4095; | |
665 | ||
666 | initrd_data = qemu_malloc(initrd_size); | |
667 | load_image(initrd_filename, initrd_data); | |
668 | ||
669 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); | |
670 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); | |
671 | fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); | |
672 | ||
673 | stl_p(header+0x218, initrd_addr); | |
674 | stl_p(header+0x21c, initrd_size); | |
675 | } | |
676 | ||
677 | /* load kernel and setup */ | |
678 | setup_size = header[0x1f1]; | |
679 | if (setup_size == 0) | |
680 | setup_size = 4; | |
681 | setup_size = (setup_size+1)*512; | |
682 | kernel_size -= setup_size; | |
683 | ||
684 | setup = qemu_malloc(setup_size); | |
685 | kernel = qemu_malloc(kernel_size); | |
686 | fseek(f, 0, SEEK_SET); | |
687 | if (fread(setup, 1, setup_size, f) != setup_size) { | |
688 | fprintf(stderr, "fread() failed\n"); | |
689 | exit(1); | |
690 | } | |
691 | if (fread(kernel, 1, kernel_size, f) != kernel_size) { | |
692 | fprintf(stderr, "fread() failed\n"); | |
693 | exit(1); | |
694 | } | |
695 | fclose(f); | |
696 | memcpy(setup, header, MIN(sizeof(header), setup_size)); | |
697 | ||
698 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); | |
699 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); | |
700 | fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); | |
701 | ||
702 | fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); | |
703 | fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); | |
704 | fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); | |
705 | ||
706 | option_rom[nb_option_roms] = "linuxboot.bin"; | |
707 | nb_option_roms++; | |
708 | } | |
709 | ||
710 | #define NE2000_NB_MAX 6 | |
711 | ||
712 | static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, | |
713 | 0x280, 0x380 }; | |
714 | static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; | |
715 | ||
716 | static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; | |
717 | static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 }; | |
718 | ||
719 | #ifdef HAS_AUDIO | |
720 | void pc_audio_init (PCIBus *pci_bus, qemu_irq *pic) | |
721 | { | |
722 | struct soundhw *c; | |
723 | ||
724 | for (c = soundhw; c->name; ++c) { | |
725 | if (c->enabled) { | |
726 | if (c->isa) { | |
727 | c->init.init_isa(pic); | |
728 | } else { | |
729 | if (pci_bus) { | |
730 | c->init.init_pci(pci_bus); | |
731 | } | |
732 | } | |
733 | } | |
734 | } | |
735 | } | |
736 | #endif | |
737 | ||
738 | void pc_init_ne2k_isa(NICInfo *nd) | |
739 | { | |
740 | static int nb_ne2k = 0; | |
741 | ||
742 | if (nb_ne2k == NE2000_NB_MAX) | |
743 | return; | |
744 | isa_ne2000_init(ne2000_io[nb_ne2k], | |
745 | ne2000_irq[nb_ne2k], nd); | |
746 | nb_ne2k++; | |
747 | } | |
748 | ||
749 | int cpu_is_bsp(CPUState *env) | |
750 | { | |
751 | /* We hard-wire the BSP to the first CPU. */ | |
752 | return env->cpu_index == 0; | |
753 | } | |
754 | ||
755 | /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE) | |
756 | BIOS will read it and start S3 resume at POST Entry */ | |
757 | void pc_cmos_set_s3_resume(void *opaque, int irq, int level) | |
758 | { | |
759 | ISADevice *s = opaque; | |
760 | ||
761 | if (level) { | |
762 | rtc_set_memory(s, 0xF, 0xFE); | |
763 | } | |
764 | } | |
765 | ||
766 | void pc_acpi_smi_interrupt(void *opaque, int irq, int level) | |
767 | { | |
768 | CPUState *s = opaque; | |
769 | ||
770 | if (level) { | |
771 | cpu_interrupt(s, CPU_INTERRUPT_SMI); | |
772 | } | |
773 | } | |
774 | ||
775 | static CPUState *pc_new_cpu(const char *cpu_model) | |
776 | { | |
777 | CPUState *env; | |
778 | ||
779 | env = cpu_init(cpu_model); | |
780 | if (!env) { | |
781 | fprintf(stderr, "Unable to find x86 CPU definition\n"); | |
782 | exit(1); | |
783 | } | |
784 | if ((env->cpuid_features & CPUID_APIC) || smp_cpus > 1) { | |
785 | env->cpuid_apic_id = env->cpu_index; | |
786 | /* APIC reset callback resets cpu */ | |
787 | apic_init(env); | |
788 | } else { | |
789 | qemu_register_reset((QEMUResetHandler*)cpu_reset, env); | |
790 | } | |
791 | return env; | |
792 | } | |
793 | ||
794 | void pc_cpus_init(const char *cpu_model) | |
795 | { | |
796 | int i; | |
797 | ||
798 | /* init CPUs */ | |
799 | if (cpu_model == NULL) { | |
800 | #ifdef TARGET_X86_64 | |
801 | cpu_model = "qemu64"; | |
802 | #else | |
803 | cpu_model = "qemu32"; | |
804 | #endif | |
805 | } | |
806 | ||
807 | for(i = 0; i < smp_cpus; i++) { | |
808 | pc_new_cpu(cpu_model); | |
809 | } | |
810 | } | |
811 | ||
812 | void pc_memory_init(ram_addr_t ram_size, | |
813 | const char *kernel_filename, | |
814 | const char *kernel_cmdline, | |
815 | const char *initrd_filename, | |
816 | ram_addr_t *below_4g_mem_size_p, | |
817 | ram_addr_t *above_4g_mem_size_p) | |
818 | { | |
819 | char *filename; | |
820 | int ret, linux_boot, i; | |
821 | ram_addr_t ram_addr, bios_offset, option_rom_offset; | |
822 | ram_addr_t below_4g_mem_size, above_4g_mem_size = 0; | |
823 | int bios_size, isa_bios_size; | |
824 | void *fw_cfg; | |
825 | ||
826 | if (ram_size >= 0xe0000000 ) { | |
827 | above_4g_mem_size = ram_size - 0xe0000000; | |
828 | below_4g_mem_size = 0xe0000000; | |
829 | } else { | |
830 | below_4g_mem_size = ram_size; | |
831 | } | |
832 | *above_4g_mem_size_p = above_4g_mem_size; | |
833 | *below_4g_mem_size_p = below_4g_mem_size; | |
834 | ||
835 | linux_boot = (kernel_filename != NULL); | |
836 | ||
837 | /* allocate RAM */ | |
838 | ram_addr = qemu_ram_alloc(below_4g_mem_size); | |
839 | cpu_register_physical_memory(0, 0xa0000, ram_addr); | |
840 | cpu_register_physical_memory(0x100000, | |
841 | below_4g_mem_size - 0x100000, | |
842 | ram_addr + 0x100000); | |
843 | ||
844 | /* above 4giga memory allocation */ | |
845 | if (above_4g_mem_size > 0) { | |
846 | #if TARGET_PHYS_ADDR_BITS == 32 | |
847 | hw_error("To much RAM for 32-bit physical address"); | |
848 | #else | |
849 | ram_addr = qemu_ram_alloc(above_4g_mem_size); | |
850 | cpu_register_physical_memory(0x100000000ULL, | |
851 | above_4g_mem_size, | |
852 | ram_addr); | |
853 | #endif | |
854 | } | |
855 | ||
856 | ||
857 | /* BIOS load */ | |
858 | if (bios_name == NULL) | |
859 | bios_name = BIOS_FILENAME; | |
860 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); | |
861 | if (filename) { | |
862 | bios_size = get_image_size(filename); | |
863 | } else { | |
864 | bios_size = -1; | |
865 | } | |
866 | if (bios_size <= 0 || | |
867 | (bios_size % 65536) != 0) { | |
868 | goto bios_error; | |
869 | } | |
870 | bios_offset = qemu_ram_alloc(bios_size); | |
871 | ret = rom_add_file_fixed(bios_name, (uint32_t)(-bios_size)); | |
872 | if (ret != 0) { | |
873 | bios_error: | |
874 | fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", bios_name); | |
875 | exit(1); | |
876 | } | |
877 | if (filename) { | |
878 | qemu_free(filename); | |
879 | } | |
880 | /* map the last 128KB of the BIOS in ISA space */ | |
881 | isa_bios_size = bios_size; | |
882 | if (isa_bios_size > (128 * 1024)) | |
883 | isa_bios_size = 128 * 1024; | |
884 | cpu_register_physical_memory(0x100000 - isa_bios_size, | |
885 | isa_bios_size, | |
886 | (bios_offset + bios_size - isa_bios_size) | IO_MEM_ROM); | |
887 | ||
888 | option_rom_offset = qemu_ram_alloc(PC_ROM_SIZE); | |
889 | cpu_register_physical_memory(PC_ROM_MIN_VGA, PC_ROM_SIZE, option_rom_offset); | |
890 | ||
891 | /* map all the bios at the top of memory */ | |
892 | cpu_register_physical_memory((uint32_t)(-bios_size), | |
893 | bios_size, bios_offset | IO_MEM_ROM); | |
894 | ||
895 | fw_cfg = bochs_bios_init(); | |
896 | rom_set_fw(fw_cfg); | |
897 | ||
898 | if (linux_boot) { | |
899 | load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size); | |
900 | } | |
901 | ||
902 | for (i = 0; i < nb_option_roms; i++) { | |
903 | rom_add_option(option_rom[i]); | |
904 | } | |
905 | } | |
906 | ||
907 | qemu_irq *pc_allocate_cpu_irq(void) | |
908 | { | |
909 | return qemu_allocate_irqs(pic_irq_request, NULL, 1); | |
910 | } | |
911 | ||
912 | void pc_vga_init(PCIBus *pci_bus) | |
913 | { | |
914 | if (cirrus_vga_enabled) { | |
915 | if (pci_bus) { | |
916 | pci_cirrus_vga_init(pci_bus); | |
917 | } else { | |
918 | isa_cirrus_vga_init(); | |
919 | } | |
920 | } else if (vmsvga_enabled) { | |
921 | if (pci_bus) | |
922 | pci_vmsvga_init(pci_bus); | |
923 | else | |
924 | fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__); | |
925 | } else if (std_vga_enabled) { | |
926 | if (pci_bus) { | |
927 | pci_vga_init(pci_bus, 0, 0); | |
928 | } else { | |
929 | isa_vga_init(); | |
930 | } | |
931 | } | |
932 | } | |
933 | ||
934 | static void cpu_request_exit(void *opaque, int irq, int level) | |
935 | { | |
936 | CPUState *env = cpu_single_env; | |
937 | ||
938 | if (env && level) { | |
939 | cpu_exit(env); | |
940 | } | |
941 | } | |
942 | ||
943 | void pc_basic_device_init(qemu_irq *isa_irq, | |
944 | FDCtrl **floppy_controller, | |
945 | ISADevice **rtc_state) | |
946 | { | |
947 | int i; | |
948 | DriveInfo *fd[MAX_FD]; | |
949 | PITState *pit; | |
950 | qemu_irq rtc_irq = NULL; | |
951 | qemu_irq *a20_line; | |
952 | ISADevice *i8042; | |
953 | qemu_irq *cpu_exit_irq; | |
954 | ||
955 | register_ioport_write(0x80, 1, 1, ioport80_write, NULL); | |
956 | ||
957 | register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL); | |
958 | ||
959 | if (!no_hpet) { | |
960 | DeviceState *hpet = sysbus_create_simple("hpet", HPET_BASE, NULL); | |
961 | ||
962 | for (i = 0; i < 24; i++) { | |
963 | sysbus_connect_irq(sysbus_from_qdev(hpet), i, isa_irq[i]); | |
964 | } | |
965 | rtc_irq = qdev_get_gpio_in(hpet, 0); | |
966 | } | |
967 | *rtc_state = rtc_init(2000, rtc_irq); | |
968 | ||
969 | qemu_register_boot_set(pc_boot_set, *rtc_state); | |
970 | ||
971 | pit = pit_init(0x40, isa_reserve_irq(0)); | |
972 | pcspk_init(pit); | |
973 | ||
974 | for(i = 0; i < MAX_SERIAL_PORTS; i++) { | |
975 | if (serial_hds[i]) { | |
976 | serial_isa_init(i, serial_hds[i]); | |
977 | } | |
978 | } | |
979 | ||
980 | for(i = 0; i < MAX_PARALLEL_PORTS; i++) { | |
981 | if (parallel_hds[i]) { | |
982 | parallel_init(i, parallel_hds[i]); | |
983 | } | |
984 | } | |
985 | ||
986 | a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 1); | |
987 | i8042 = isa_create_simple("i8042"); | |
988 | i8042_setup_a20_line(i8042, a20_line); | |
989 | vmmouse_init(i8042); | |
990 | ||
991 | cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1); | |
992 | DMA_init(0, cpu_exit_irq); | |
993 | ||
994 | for(i = 0; i < MAX_FD; i++) { | |
995 | fd[i] = drive_get(IF_FLOPPY, 0, i); | |
996 | } | |
997 | *floppy_controller = fdctrl_init_isa(fd); | |
998 | } | |
999 | ||
1000 | void pc_pci_device_init(PCIBus *pci_bus) | |
1001 | { | |
1002 | int max_bus; | |
1003 | int bus; | |
1004 | ||
1005 | max_bus = drive_get_max_bus(IF_SCSI); | |
1006 | for (bus = 0; bus <= max_bus; bus++) { | |
1007 | pci_create_simple(pci_bus, -1, "lsi53c895a"); | |
1008 | } | |
1009 | } |