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1 | #ifndef HW_PC_H | |
2 | #define HW_PC_H | |
3 | ||
4 | #include "qemu-common.h" | |
5 | #include "ioport.h" | |
6 | #include "isa.h" | |
7 | #include "fdc.h" | |
8 | #include "net.h" | |
9 | ||
10 | /* PC-style peripherals (also used by other machines). */ | |
11 | ||
12 | /* serial.c */ | |
13 | ||
14 | SerialState *serial_init(int base, qemu_irq irq, int baudbase, | |
15 | CharDriverState *chr); | |
16 | SerialState *serial_mm_init (target_phys_addr_t base, int it_shift, | |
17 | qemu_irq irq, int baudbase, | |
18 | CharDriverState *chr, int ioregister, | |
19 | int be); | |
20 | SerialState *serial_isa_init(int index, CharDriverState *chr); | |
21 | void serial_set_frequency(SerialState *s, uint32_t frequency); | |
22 | ||
23 | /* parallel.c */ | |
24 | static inline bool parallel_init(int index, CharDriverState *chr) | |
25 | { | |
26 | ISADevice *dev; | |
27 | ||
28 | dev = isa_try_create("isa-parallel"); | |
29 | if (!dev) { | |
30 | return false; | |
31 | } | |
32 | qdev_prop_set_uint32(&dev->qdev, "index", index); | |
33 | qdev_prop_set_chr(&dev->qdev, "chardev", chr); | |
34 | if (qdev_init(&dev->qdev) < 0) { | |
35 | return false; | |
36 | } | |
37 | return true; | |
38 | } | |
39 | ||
40 | bool parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, | |
41 | CharDriverState *chr); | |
42 | ||
43 | /* i8259.c */ | |
44 | ||
45 | typedef struct PicState2 PicState2; | |
46 | extern PicState2 *isa_pic; | |
47 | void pic_set_irq(int irq, int level); | |
48 | void pic_set_irq_new(void *opaque, int irq, int level); | |
49 | qemu_irq *i8259_init(qemu_irq parent_irq); | |
50 | int pic_read_irq(PicState2 *s); | |
51 | void pic_update_irq(PicState2 *s); | |
52 | uint32_t pic_intack_read(PicState2 *s); | |
53 | void pic_info(Monitor *mon); | |
54 | void irq_info(Monitor *mon); | |
55 | ||
56 | /* ISA */ | |
57 | #define IOAPIC_NUM_PINS 0x18 | |
58 | ||
59 | typedef struct isa_irq_state { | |
60 | qemu_irq *i8259; | |
61 | qemu_irq ioapic[IOAPIC_NUM_PINS]; | |
62 | } IsaIrqState; | |
63 | ||
64 | void isa_irq_handler(void *opaque, int n, int level); | |
65 | ||
66 | /* i8254.c */ | |
67 | ||
68 | #define PIT_FREQ 1193182 | |
69 | ||
70 | typedef struct PITState PITState; | |
71 | ||
72 | PITState *pit_init(int base, qemu_irq irq); | |
73 | void pit_set_gate(PITState *pit, int channel, int val); | |
74 | int pit_get_gate(PITState *pit, int channel); | |
75 | int pit_get_initial_count(PITState *pit, int channel); | |
76 | int pit_get_mode(PITState *pit, int channel); | |
77 | int pit_get_out(PITState *pit, int channel, int64_t current_time); | |
78 | ||
79 | void hpet_pit_disable(void); | |
80 | void hpet_pit_enable(void); | |
81 | ||
82 | /* vmport.c */ | |
83 | static inline void vmport_init(void) | |
84 | { | |
85 | isa_create_simple("vmport"); | |
86 | } | |
87 | void vmport_register(unsigned char command, IOPortReadFunc *func, void *opaque); | |
88 | void vmmouse_get_data(uint32_t *data); | |
89 | void vmmouse_set_data(const uint32_t *data); | |
90 | ||
91 | /* pckbd.c */ | |
92 | ||
93 | void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base); | |
94 | void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq, | |
95 | target_phys_addr_t base, ram_addr_t size, | |
96 | target_phys_addr_t mask); | |
97 | void i8042_isa_mouse_fake_event(void *opaque); | |
98 | void i8042_setup_a20_line(ISADevice *dev, qemu_irq *a20_out); | |
99 | ||
100 | /* pc.c */ | |
101 | extern int fd_bootchk; | |
102 | ||
103 | void pc_register_ferr_irq(qemu_irq irq); | |
104 | void pc_cmos_set_s3_resume(void *opaque, int irq, int level); | |
105 | void pc_acpi_smi_interrupt(void *opaque, int irq, int level); | |
106 | ||
107 | void pc_cpus_init(const char *cpu_model); | |
108 | void pc_memory_init(ram_addr_t ram_size, | |
109 | const char *kernel_filename, | |
110 | const char *kernel_cmdline, | |
111 | const char *initrd_filename, | |
112 | ram_addr_t *below_4g_mem_size_p, | |
113 | ram_addr_t *above_4g_mem_size_p); | |
114 | qemu_irq *pc_allocate_cpu_irq(void); | |
115 | void pc_vga_init(PCIBus *pci_bus); | |
116 | void pc_basic_device_init(qemu_irq *isa_irq, | |
117 | FDCtrl **floppy_controller, | |
118 | ISADevice **rtc_state); | |
119 | void pc_init_ne2k_isa(NICInfo *nd); | |
120 | void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size, | |
121 | const char *boot_device, | |
122 | BusState *ide0, BusState *ide1, | |
123 | FDCtrl *floppy_controller, ISADevice *s); | |
124 | void pc_pci_device_init(PCIBus *pci_bus); | |
125 | ||
126 | typedef void (*cpu_set_smm_t)(int smm, void *arg); | |
127 | void cpu_smm_register(cpu_set_smm_t callback, void *arg); | |
128 | ||
129 | /* acpi.c */ | |
130 | extern int acpi_enabled; | |
131 | extern char *acpi_tables; | |
132 | extern size_t acpi_tables_len; | |
133 | ||
134 | void acpi_bios_init(void); | |
135 | int acpi_table_add(const char *table_desc); | |
136 | ||
137 | /* acpi_piix.c */ | |
138 | ||
139 | i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, | |
140 | qemu_irq sci_irq, qemu_irq cmos_s3, qemu_irq smi_irq, | |
141 | int kvm_enabled); | |
142 | void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr); | |
143 | ||
144 | /* hpet.c */ | |
145 | extern int no_hpet; | |
146 | ||
147 | /* pcspk.c */ | |
148 | void pcspk_init(PITState *); | |
149 | int pcspk_audio_init(qemu_irq *pic); | |
150 | ||
151 | /* piix_pci.c */ | |
152 | struct PCII440FXState; | |
153 | typedef struct PCII440FXState PCII440FXState; | |
154 | ||
155 | PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix_devfn, qemu_irq *pic, ram_addr_t ram_size); | |
156 | void i440fx_init_memory_mappings(PCII440FXState *d); | |
157 | ||
158 | /* piix4.c */ | |
159 | extern PCIDevice *piix4_dev; | |
160 | int piix4_init(PCIBus *bus, int devfn); | |
161 | ||
162 | /* vga.c */ | |
163 | enum vga_retrace_method { | |
164 | VGA_RETRACE_DUMB, | |
165 | VGA_RETRACE_PRECISE | |
166 | }; | |
167 | ||
168 | extern enum vga_retrace_method vga_retrace_method; | |
169 | ||
170 | int isa_vga_init(void); | |
171 | int pci_vga_init(PCIBus *bus); | |
172 | int isa_vga_mm_init(target_phys_addr_t vram_base, | |
173 | target_phys_addr_t ctrl_base, int it_shift); | |
174 | ||
175 | /* cirrus_vga.c */ | |
176 | void pci_cirrus_vga_init(PCIBus *bus); | |
177 | void isa_cirrus_vga_init(void); | |
178 | ||
179 | /* ne2000.c */ | |
180 | static inline bool isa_ne2000_init(int base, int irq, NICInfo *nd) | |
181 | { | |
182 | ISADevice *dev; | |
183 | ||
184 | qemu_check_nic_model(nd, "ne2k_isa"); | |
185 | ||
186 | dev = isa_try_create("ne2k_isa"); | |
187 | if (!dev) { | |
188 | return false; | |
189 | } | |
190 | qdev_prop_set_uint32(&dev->qdev, "iobase", base); | |
191 | qdev_prop_set_uint32(&dev->qdev, "irq", irq); | |
192 | qdev_set_nic_properties(&dev->qdev, nd); | |
193 | qdev_init_nofail(&dev->qdev); | |
194 | return true; | |
195 | } | |
196 | ||
197 | /* e820 types */ | |
198 | #define E820_RAM 1 | |
199 | #define E820_RESERVED 2 | |
200 | #define E820_ACPI 3 | |
201 | #define E820_NVS 4 | |
202 | #define E820_UNUSABLE 5 | |
203 | ||
204 | int e820_add_entry(uint64_t, uint64_t, uint32_t); | |
205 | ||
206 | #endif |