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1 | #ifndef HW_PC_H | |
2 | #define HW_PC_H | |
3 | ||
4 | #include "qemu-common.h" | |
5 | #include "ioport.h" | |
6 | #include "isa.h" | |
7 | #include "fdc.h" | |
8 | ||
9 | /* PC-style peripherals (also used by other machines). */ | |
10 | ||
11 | /* serial.c */ | |
12 | ||
13 | SerialState *serial_init(int base, qemu_irq irq, int baudbase, | |
14 | CharDriverState *chr); | |
15 | SerialState *serial_mm_init (target_phys_addr_t base, int it_shift, | |
16 | qemu_irq irq, int baudbase, | |
17 | CharDriverState *chr, int ioregister, | |
18 | int be); | |
19 | SerialState *serial_isa_init(int index, CharDriverState *chr); | |
20 | void serial_set_frequency(SerialState *s, uint32_t frequency); | |
21 | ||
22 | /* parallel.c */ | |
23 | ||
24 | typedef struct ParallelState ParallelState; | |
25 | ParallelState *parallel_init(int index, CharDriverState *chr); | |
26 | ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr); | |
27 | ||
28 | /* i8259.c */ | |
29 | ||
30 | typedef struct PicState2 PicState2; | |
31 | extern PicState2 *isa_pic; | |
32 | void pic_set_irq(int irq, int level); | |
33 | void pic_set_irq_new(void *opaque, int irq, int level); | |
34 | qemu_irq *i8259_init(qemu_irq parent_irq); | |
35 | int pic_read_irq(PicState2 *s); | |
36 | void pic_update_irq(PicState2 *s); | |
37 | uint32_t pic_intack_read(PicState2 *s); | |
38 | void pic_info(Monitor *mon); | |
39 | void irq_info(Monitor *mon); | |
40 | ||
41 | /* ISA */ | |
42 | #define IOAPIC_NUM_PINS 0x18 | |
43 | ||
44 | typedef struct isa_irq_state { | |
45 | qemu_irq *i8259; | |
46 | qemu_irq ioapic[IOAPIC_NUM_PINS]; | |
47 | } IsaIrqState; | |
48 | ||
49 | void isa_irq_handler(void *opaque, int n, int level); | |
50 | ||
51 | /* i8254.c */ | |
52 | ||
53 | #define PIT_FREQ 1193182 | |
54 | ||
55 | typedef struct PITState PITState; | |
56 | ||
57 | PITState *pit_init(int base, qemu_irq irq); | |
58 | void pit_set_gate(PITState *pit, int channel, int val); | |
59 | int pit_get_gate(PITState *pit, int channel); | |
60 | int pit_get_initial_count(PITState *pit, int channel); | |
61 | int pit_get_mode(PITState *pit, int channel); | |
62 | int pit_get_out(PITState *pit, int channel, int64_t current_time); | |
63 | ||
64 | void hpet_pit_disable(void); | |
65 | void hpet_pit_enable(void); | |
66 | ||
67 | /* vmport.c */ | |
68 | static inline void vmport_init(void) | |
69 | { | |
70 | isa_create_simple("vmport"); | |
71 | } | |
72 | void vmport_register(unsigned char command, IOPortReadFunc *func, void *opaque); | |
73 | void vmmouse_get_data(uint32_t *data); | |
74 | void vmmouse_set_data(const uint32_t *data); | |
75 | ||
76 | /* pckbd.c */ | |
77 | ||
78 | void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base); | |
79 | void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq, | |
80 | target_phys_addr_t base, ram_addr_t size, | |
81 | target_phys_addr_t mask); | |
82 | void i8042_isa_mouse_fake_event(void *opaque); | |
83 | void i8042_setup_a20_line(ISADevice *dev, qemu_irq *a20_out); | |
84 | ||
85 | /* pc.c */ | |
86 | extern int fd_bootchk; | |
87 | ||
88 | void pc_register_ferr_irq(qemu_irq irq); | |
89 | void pc_cmos_set_s3_resume(void *opaque, int irq, int level); | |
90 | void pc_acpi_smi_interrupt(void *opaque, int irq, int level); | |
91 | ||
92 | void pc_cpus_init(const char *cpu_model); | |
93 | void pc_memory_init(ram_addr_t ram_size, | |
94 | const char *kernel_filename, | |
95 | const char *kernel_cmdline, | |
96 | const char *initrd_filename, | |
97 | ram_addr_t *below_4g_mem_size_p, | |
98 | ram_addr_t *above_4g_mem_size_p); | |
99 | qemu_irq *pc_allocate_cpu_irq(void); | |
100 | void pc_vga_init(PCIBus *pci_bus); | |
101 | void pc_basic_device_init(qemu_irq *isa_irq, | |
102 | FDCtrl **floppy_controller, | |
103 | ISADevice **rtc_state); | |
104 | void pc_init_ne2k_isa(NICInfo *nd); | |
105 | void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size, | |
106 | const char *boot_device, | |
107 | BusState *ide0, BusState *ide1, | |
108 | FDCtrl *floppy_controller, ISADevice *s); | |
109 | void pc_pci_device_init(PCIBus *pci_bus); | |
110 | ||
111 | typedef void (*cpu_set_smm_t)(int smm, void *arg); | |
112 | void cpu_smm_register(cpu_set_smm_t callback, void *arg); | |
113 | ||
114 | /* acpi.c */ | |
115 | extern int acpi_enabled; | |
116 | extern char *acpi_tables; | |
117 | extern size_t acpi_tables_len; | |
118 | ||
119 | void acpi_bios_init(void); | |
120 | int acpi_table_add(const char *table_desc); | |
121 | ||
122 | /* acpi_piix.c */ | |
123 | ||
124 | i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, | |
125 | qemu_irq sci_irq, qemu_irq cmos_s3, qemu_irq smi_irq, | |
126 | int kvm_enabled); | |
127 | void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr); | |
128 | ||
129 | /* hpet.c */ | |
130 | extern int no_hpet; | |
131 | ||
132 | /* pcspk.c */ | |
133 | void pcspk_init(PITState *); | |
134 | int pcspk_audio_init(qemu_irq *pic); | |
135 | ||
136 | /* piix_pci.c */ | |
137 | struct PCII440FXState; | |
138 | typedef struct PCII440FXState PCII440FXState; | |
139 | ||
140 | PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix_devfn, qemu_irq *pic, ram_addr_t ram_size); | |
141 | void i440fx_init_memory_mappings(PCII440FXState *d); | |
142 | ||
143 | /* piix4.c */ | |
144 | extern PCIDevice *piix4_dev; | |
145 | int piix4_init(PCIBus *bus, int devfn); | |
146 | ||
147 | /* vga.c */ | |
148 | enum vga_retrace_method { | |
149 | VGA_RETRACE_DUMB, | |
150 | VGA_RETRACE_PRECISE | |
151 | }; | |
152 | ||
153 | extern enum vga_retrace_method vga_retrace_method; | |
154 | ||
155 | int isa_vga_init(void); | |
156 | int pci_vga_init(PCIBus *bus); | |
157 | int isa_vga_mm_init(target_phys_addr_t vram_base, | |
158 | target_phys_addr_t ctrl_base, int it_shift); | |
159 | ||
160 | /* cirrus_vga.c */ | |
161 | void pci_cirrus_vga_init(PCIBus *bus); | |
162 | void isa_cirrus_vga_init(void); | |
163 | ||
164 | /* ne2000.c */ | |
165 | ||
166 | void isa_ne2000_init(int base, int irq, NICInfo *nd); | |
167 | ||
168 | /* e820 types */ | |
169 | #define E820_RAM 1 | |
170 | #define E820_RESERVED 2 | |
171 | #define E820_ACPI 3 | |
172 | #define E820_NVS 4 | |
173 | #define E820_UNUSABLE 5 | |
174 | ||
175 | int e820_add_entry(uint64_t, uint64_t, uint32_t); | |
176 | ||
177 | #endif |