]>
Commit | Line | Data |
---|---|---|
1 | /* | |
2 | * QEMU PREP PCI host | |
3 | * | |
4 | * Copyright (c) 2006 Fabrice Bellard | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
25 | #include "hw.h" | |
26 | #include "pci/pci.h" | |
27 | #include "pci/pci_host.h" | |
28 | #include "pc.h" | |
29 | #include "exec/address-spaces.h" | |
30 | ||
31 | #define TYPE_RAVEN_PCI_HOST_BRIDGE "raven-pcihost" | |
32 | ||
33 | #define RAVEN_PCI_HOST_BRIDGE(obj) \ | |
34 | OBJECT_CHECK(PREPPCIState, (obj), TYPE_RAVEN_PCI_HOST_BRIDGE) | |
35 | ||
36 | typedef struct PRePPCIState { | |
37 | PCIHostState parent_obj; | |
38 | ||
39 | MemoryRegion intack; | |
40 | qemu_irq irq[4]; | |
41 | } PREPPCIState; | |
42 | ||
43 | typedef struct RavenPCIState { | |
44 | PCIDevice dev; | |
45 | } RavenPCIState; | |
46 | ||
47 | static inline uint32_t PPC_PCIIO_config(hwaddr addr) | |
48 | { | |
49 | int i; | |
50 | ||
51 | for (i = 0; i < 11; i++) { | |
52 | if ((addr & (1 << (11 + i))) != 0) { | |
53 | break; | |
54 | } | |
55 | } | |
56 | return (addr & 0x7ff) | (i << 11); | |
57 | } | |
58 | ||
59 | static void ppc_pci_io_write(void *opaque, hwaddr addr, | |
60 | uint64_t val, unsigned int size) | |
61 | { | |
62 | PREPPCIState *s = opaque; | |
63 | PCIHostState *phb = PCI_HOST_BRIDGE(s); | |
64 | pci_data_write(phb->bus, PPC_PCIIO_config(addr), val, size); | |
65 | } | |
66 | ||
67 | static uint64_t ppc_pci_io_read(void *opaque, hwaddr addr, | |
68 | unsigned int size) | |
69 | { | |
70 | PREPPCIState *s = opaque; | |
71 | PCIHostState *phb = PCI_HOST_BRIDGE(s); | |
72 | return pci_data_read(phb->bus, PPC_PCIIO_config(addr), size); | |
73 | } | |
74 | ||
75 | static const MemoryRegionOps PPC_PCIIO_ops = { | |
76 | .read = ppc_pci_io_read, | |
77 | .write = ppc_pci_io_write, | |
78 | .endianness = DEVICE_LITTLE_ENDIAN, | |
79 | }; | |
80 | ||
81 | static uint64_t ppc_intack_read(void *opaque, hwaddr addr, | |
82 | unsigned int size) | |
83 | { | |
84 | return pic_read_irq(isa_pic); | |
85 | } | |
86 | ||
87 | static const MemoryRegionOps PPC_intack_ops = { | |
88 | .read = ppc_intack_read, | |
89 | .valid = { | |
90 | .max_access_size = 1, | |
91 | }, | |
92 | }; | |
93 | ||
94 | static int prep_map_irq(PCIDevice *pci_dev, int irq_num) | |
95 | { | |
96 | return (irq_num + (pci_dev->devfn >> 3)) & 1; | |
97 | } | |
98 | ||
99 | static void prep_set_irq(void *opaque, int irq_num, int level) | |
100 | { | |
101 | qemu_irq *pic = opaque; | |
102 | ||
103 | qemu_set_irq(pic[irq_num] , level); | |
104 | } | |
105 | ||
106 | static int raven_pcihost_init(SysBusDevice *dev) | |
107 | { | |
108 | PCIHostState *h = PCI_HOST_BRIDGE(dev); | |
109 | PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(dev); | |
110 | MemoryRegion *address_space_mem = get_system_memory(); | |
111 | MemoryRegion *address_space_io = get_system_io(); | |
112 | PCIBus *bus; | |
113 | int i; | |
114 | ||
115 | for (i = 0; i < 4; i++) { | |
116 | sysbus_init_irq(dev, &s->irq[i]); | |
117 | } | |
118 | ||
119 | bus = pci_register_bus(DEVICE(dev), NULL, | |
120 | prep_set_irq, prep_map_irq, s->irq, | |
121 | address_space_mem, address_space_io, 0, 4); | |
122 | h->bus = bus; | |
123 | ||
124 | memory_region_init_io(&h->conf_mem, &pci_host_conf_be_ops, s, | |
125 | "pci-conf-idx", 1); | |
126 | sysbus_add_io(dev, 0xcf8, &h->conf_mem); | |
127 | sysbus_init_ioports(&h->busdev, 0xcf8, 1); | |
128 | ||
129 | memory_region_init_io(&h->data_mem, &pci_host_data_be_ops, s, | |
130 | "pci-conf-data", 1); | |
131 | sysbus_add_io(dev, 0xcfc, &h->data_mem); | |
132 | sysbus_init_ioports(&h->busdev, 0xcfc, 1); | |
133 | ||
134 | memory_region_init_io(&h->mmcfg, &PPC_PCIIO_ops, s, "pciio", 0x00400000); | |
135 | memory_region_add_subregion(address_space_mem, 0x80800000, &h->mmcfg); | |
136 | ||
137 | memory_region_init_io(&s->intack, &PPC_intack_ops, s, "pci-intack", 1); | |
138 | memory_region_add_subregion(address_space_mem, 0xbffffff0, &s->intack); | |
139 | pci_create_simple(bus, 0, "raven"); | |
140 | ||
141 | return 0; | |
142 | } | |
143 | ||
144 | static int raven_init(PCIDevice *d) | |
145 | { | |
146 | d->config[0x0C] = 0x08; // cache_line_size | |
147 | d->config[0x0D] = 0x10; // latency_timer | |
148 | d->config[0x34] = 0x00; // capabilities_pointer | |
149 | ||
150 | return 0; | |
151 | } | |
152 | ||
153 | static const VMStateDescription vmstate_raven = { | |
154 | .name = "raven", | |
155 | .version_id = 0, | |
156 | .minimum_version_id = 0, | |
157 | .fields = (VMStateField[]) { | |
158 | VMSTATE_PCI_DEVICE(dev, RavenPCIState), | |
159 | VMSTATE_END_OF_LIST() | |
160 | }, | |
161 | }; | |
162 | ||
163 | static void raven_class_init(ObjectClass *klass, void *data) | |
164 | { | |
165 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
166 | DeviceClass *dc = DEVICE_CLASS(klass); | |
167 | ||
168 | k->init = raven_init; | |
169 | k->vendor_id = PCI_VENDOR_ID_MOTOROLA; | |
170 | k->device_id = PCI_DEVICE_ID_MOTOROLA_RAVEN; | |
171 | k->revision = 0x00; | |
172 | k->class_id = PCI_CLASS_BRIDGE_HOST; | |
173 | dc->desc = "PReP Host Bridge - Motorola Raven"; | |
174 | dc->vmsd = &vmstate_raven; | |
175 | dc->no_user = 1; | |
176 | } | |
177 | ||
178 | static const TypeInfo raven_info = { | |
179 | .name = "raven", | |
180 | .parent = TYPE_PCI_DEVICE, | |
181 | .instance_size = sizeof(RavenPCIState), | |
182 | .class_init = raven_class_init, | |
183 | }; | |
184 | ||
185 | static void raven_pcihost_class_init(ObjectClass *klass, void *data) | |
186 | { | |
187 | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); | |
188 | DeviceClass *dc = DEVICE_CLASS(klass); | |
189 | ||
190 | k->init = raven_pcihost_init; | |
191 | dc->fw_name = "pci"; | |
192 | dc->no_user = 1; | |
193 | } | |
194 | ||
195 | static const TypeInfo raven_pcihost_info = { | |
196 | .name = TYPE_RAVEN_PCI_HOST_BRIDGE, | |
197 | .parent = TYPE_PCI_HOST_BRIDGE, | |
198 | .instance_size = sizeof(PREPPCIState), | |
199 | .class_init = raven_pcihost_class_init, | |
200 | }; | |
201 | ||
202 | static void raven_register_types(void) | |
203 | { | |
204 | type_register_static(&raven_pcihost_info); | |
205 | type_register_static(&raven_info); | |
206 | } | |
207 | ||
208 | type_init(raven_register_types) |