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1 | /* | |
2 | * QEMU 16550A UART emulation | |
3 | * | |
4 | * Copyright (c) 2003-2004 Fabrice Bellard | |
5 | * Copyright (c) 2008 Citrix Systems, Inc. | |
6 | * | |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
25 | ||
26 | #include "serial.h" | |
27 | #include "qemu-char.h" | |
28 | #include "qemu-timer.h" | |
29 | #include "exec-memory.h" | |
30 | ||
31 | //#define DEBUG_SERIAL | |
32 | ||
33 | #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ | |
34 | ||
35 | #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ | |
36 | #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ | |
37 | #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ | |
38 | #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ | |
39 | ||
40 | #define UART_IIR_NO_INT 0x01 /* No interrupts pending */ | |
41 | #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ | |
42 | ||
43 | #define UART_IIR_MSI 0x00 /* Modem status interrupt */ | |
44 | #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ | |
45 | #define UART_IIR_RDI 0x04 /* Receiver data interrupt */ | |
46 | #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ | |
47 | #define UART_IIR_CTI 0x0C /* Character Timeout Indication */ | |
48 | ||
49 | #define UART_IIR_FENF 0x80 /* Fifo enabled, but not functionning */ | |
50 | #define UART_IIR_FE 0xC0 /* Fifo enabled */ | |
51 | ||
52 | /* | |
53 | * These are the definitions for the Modem Control Register | |
54 | */ | |
55 | #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ | |
56 | #define UART_MCR_OUT2 0x08 /* Out2 complement */ | |
57 | #define UART_MCR_OUT1 0x04 /* Out1 complement */ | |
58 | #define UART_MCR_RTS 0x02 /* RTS complement */ | |
59 | #define UART_MCR_DTR 0x01 /* DTR complement */ | |
60 | ||
61 | /* | |
62 | * These are the definitions for the Modem Status Register | |
63 | */ | |
64 | #define UART_MSR_DCD 0x80 /* Data Carrier Detect */ | |
65 | #define UART_MSR_RI 0x40 /* Ring Indicator */ | |
66 | #define UART_MSR_DSR 0x20 /* Data Set Ready */ | |
67 | #define UART_MSR_CTS 0x10 /* Clear to Send */ | |
68 | #define UART_MSR_DDCD 0x08 /* Delta DCD */ | |
69 | #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ | |
70 | #define UART_MSR_DDSR 0x02 /* Delta DSR */ | |
71 | #define UART_MSR_DCTS 0x01 /* Delta CTS */ | |
72 | #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ | |
73 | ||
74 | #define UART_LSR_TEMT 0x40 /* Transmitter empty */ | |
75 | #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ | |
76 | #define UART_LSR_BI 0x10 /* Break interrupt indicator */ | |
77 | #define UART_LSR_FE 0x08 /* Frame error indicator */ | |
78 | #define UART_LSR_PE 0x04 /* Parity error indicator */ | |
79 | #define UART_LSR_OE 0x02 /* Overrun error indicator */ | |
80 | #define UART_LSR_DR 0x01 /* Receiver data ready */ | |
81 | #define UART_LSR_INT_ANY 0x1E /* Any of the lsr-interrupt-triggering status bits */ | |
82 | ||
83 | /* Interrupt trigger levels. The byte-counts are for 16550A - in newer UARTs the byte-count for each ITL is higher. */ | |
84 | ||
85 | #define UART_FCR_ITL_1 0x00 /* 1 byte ITL */ | |
86 | #define UART_FCR_ITL_2 0x40 /* 4 bytes ITL */ | |
87 | #define UART_FCR_ITL_3 0x80 /* 8 bytes ITL */ | |
88 | #define UART_FCR_ITL_4 0xC0 /* 14 bytes ITL */ | |
89 | ||
90 | #define UART_FCR_DMS 0x08 /* DMA Mode Select */ | |
91 | #define UART_FCR_XFR 0x04 /* XMIT Fifo Reset */ | |
92 | #define UART_FCR_RFR 0x02 /* RCVR Fifo Reset */ | |
93 | #define UART_FCR_FE 0x01 /* FIFO Enable */ | |
94 | ||
95 | #define XMIT_FIFO 0 | |
96 | #define RECV_FIFO 1 | |
97 | #define MAX_XMIT_RETRY 4 | |
98 | ||
99 | #ifdef DEBUG_SERIAL | |
100 | #define DPRINTF(fmt, ...) \ | |
101 | do { fprintf(stderr, "serial: " fmt , ## __VA_ARGS__); } while (0) | |
102 | #else | |
103 | #define DPRINTF(fmt, ...) \ | |
104 | do {} while (0) | |
105 | #endif | |
106 | ||
107 | static void serial_receive1(void *opaque, const uint8_t *buf, int size); | |
108 | ||
109 | static void fifo_clear(SerialState *s, int fifo) | |
110 | { | |
111 | SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo; | |
112 | memset(f->data, 0, UART_FIFO_LENGTH); | |
113 | f->count = 0; | |
114 | f->head = 0; | |
115 | f->tail = 0; | |
116 | } | |
117 | ||
118 | static int fifo_put(SerialState *s, int fifo, uint8_t chr) | |
119 | { | |
120 | SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo; | |
121 | ||
122 | /* Receive overruns do not overwrite FIFO contents. */ | |
123 | if (fifo == XMIT_FIFO || f->count < UART_FIFO_LENGTH) { | |
124 | ||
125 | f->data[f->head++] = chr; | |
126 | ||
127 | if (f->head == UART_FIFO_LENGTH) | |
128 | f->head = 0; | |
129 | } | |
130 | ||
131 | if (f->count < UART_FIFO_LENGTH) | |
132 | f->count++; | |
133 | else if (fifo == RECV_FIFO) | |
134 | s->lsr |= UART_LSR_OE; | |
135 | ||
136 | return 1; | |
137 | } | |
138 | ||
139 | static uint8_t fifo_get(SerialState *s, int fifo) | |
140 | { | |
141 | SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo; | |
142 | uint8_t c; | |
143 | ||
144 | if(f->count == 0) | |
145 | return 0; | |
146 | ||
147 | c = f->data[f->tail++]; | |
148 | if (f->tail == UART_FIFO_LENGTH) | |
149 | f->tail = 0; | |
150 | f->count--; | |
151 | ||
152 | return c; | |
153 | } | |
154 | ||
155 | static void serial_update_irq(SerialState *s) | |
156 | { | |
157 | uint8_t tmp_iir = UART_IIR_NO_INT; | |
158 | ||
159 | if ((s->ier & UART_IER_RLSI) && (s->lsr & UART_LSR_INT_ANY)) { | |
160 | tmp_iir = UART_IIR_RLSI; | |
161 | } else if ((s->ier & UART_IER_RDI) && s->timeout_ipending) { | |
162 | /* Note that(s->ier & UART_IER_RDI) can mask this interrupt, | |
163 | * this is not in the specification but is observed on existing | |
164 | * hardware. */ | |
165 | tmp_iir = UART_IIR_CTI; | |
166 | } else if ((s->ier & UART_IER_RDI) && (s->lsr & UART_LSR_DR) && | |
167 | (!(s->fcr & UART_FCR_FE) || | |
168 | s->recv_fifo.count >= s->recv_fifo.itl)) { | |
169 | tmp_iir = UART_IIR_RDI; | |
170 | } else if ((s->ier & UART_IER_THRI) && s->thr_ipending) { | |
171 | tmp_iir = UART_IIR_THRI; | |
172 | } else if ((s->ier & UART_IER_MSI) && (s->msr & UART_MSR_ANY_DELTA)) { | |
173 | tmp_iir = UART_IIR_MSI; | |
174 | } | |
175 | ||
176 | s->iir = tmp_iir | (s->iir & 0xF0); | |
177 | ||
178 | if (tmp_iir != UART_IIR_NO_INT) { | |
179 | qemu_irq_raise(s->irq); | |
180 | } else { | |
181 | qemu_irq_lower(s->irq); | |
182 | } | |
183 | } | |
184 | ||
185 | static void serial_update_parameters(SerialState *s) | |
186 | { | |
187 | int speed, parity, data_bits, stop_bits, frame_size; | |
188 | QEMUSerialSetParams ssp; | |
189 | ||
190 | if (s->divider == 0) | |
191 | return; | |
192 | ||
193 | /* Start bit. */ | |
194 | frame_size = 1; | |
195 | if (s->lcr & 0x08) { | |
196 | /* Parity bit. */ | |
197 | frame_size++; | |
198 | if (s->lcr & 0x10) | |
199 | parity = 'E'; | |
200 | else | |
201 | parity = 'O'; | |
202 | } else { | |
203 | parity = 'N'; | |
204 | } | |
205 | if (s->lcr & 0x04) | |
206 | stop_bits = 2; | |
207 | else | |
208 | stop_bits = 1; | |
209 | ||
210 | data_bits = (s->lcr & 0x03) + 5; | |
211 | frame_size += data_bits + stop_bits; | |
212 | speed = s->baudbase / s->divider; | |
213 | ssp.speed = speed; | |
214 | ssp.parity = parity; | |
215 | ssp.data_bits = data_bits; | |
216 | ssp.stop_bits = stop_bits; | |
217 | s->char_transmit_time = (get_ticks_per_sec() / speed) * frame_size; | |
218 | qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); | |
219 | ||
220 | DPRINTF("speed=%d parity=%c data=%d stop=%d\n", | |
221 | speed, parity, data_bits, stop_bits); | |
222 | } | |
223 | ||
224 | static void serial_update_msl(SerialState *s) | |
225 | { | |
226 | uint8_t omsr; | |
227 | int flags; | |
228 | ||
229 | qemu_del_timer(s->modem_status_poll); | |
230 | ||
231 | if (qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags) == -ENOTSUP) { | |
232 | s->poll_msl = -1; | |
233 | return; | |
234 | } | |
235 | ||
236 | omsr = s->msr; | |
237 | ||
238 | s->msr = (flags & CHR_TIOCM_CTS) ? s->msr | UART_MSR_CTS : s->msr & ~UART_MSR_CTS; | |
239 | s->msr = (flags & CHR_TIOCM_DSR) ? s->msr | UART_MSR_DSR : s->msr & ~UART_MSR_DSR; | |
240 | s->msr = (flags & CHR_TIOCM_CAR) ? s->msr | UART_MSR_DCD : s->msr & ~UART_MSR_DCD; | |
241 | s->msr = (flags & CHR_TIOCM_RI) ? s->msr | UART_MSR_RI : s->msr & ~UART_MSR_RI; | |
242 | ||
243 | if (s->msr != omsr) { | |
244 | /* Set delta bits */ | |
245 | s->msr = s->msr | ((s->msr >> 4) ^ (omsr >> 4)); | |
246 | /* UART_MSR_TERI only if change was from 1 -> 0 */ | |
247 | if ((s->msr & UART_MSR_TERI) && !(omsr & UART_MSR_RI)) | |
248 | s->msr &= ~UART_MSR_TERI; | |
249 | serial_update_irq(s); | |
250 | } | |
251 | ||
252 | /* The real 16550A apparently has a 250ns response latency to line status changes. | |
253 | We'll be lazy and poll only every 10ms, and only poll it at all if MSI interrupts are turned on */ | |
254 | ||
255 | if (s->poll_msl) | |
256 | qemu_mod_timer(s->modem_status_poll, qemu_get_clock_ns(vm_clock) + get_ticks_per_sec() / 100); | |
257 | } | |
258 | ||
259 | static void serial_xmit(void *opaque) | |
260 | { | |
261 | SerialState *s = opaque; | |
262 | uint64_t new_xmit_ts = qemu_get_clock_ns(vm_clock); | |
263 | ||
264 | if (s->tsr_retry <= 0) { | |
265 | if (s->fcr & UART_FCR_FE) { | |
266 | s->tsr = fifo_get(s,XMIT_FIFO); | |
267 | if (!s->xmit_fifo.count) | |
268 | s->lsr |= UART_LSR_THRE; | |
269 | } else if ((s->lsr & UART_LSR_THRE)) { | |
270 | return; | |
271 | } else { | |
272 | s->tsr = s->thr; | |
273 | s->lsr |= UART_LSR_THRE; | |
274 | s->lsr &= ~UART_LSR_TEMT; | |
275 | } | |
276 | } | |
277 | ||
278 | if (s->mcr & UART_MCR_LOOP) { | |
279 | /* in loopback mode, say that we just received a char */ | |
280 | serial_receive1(s, &s->tsr, 1); | |
281 | } else if (qemu_chr_fe_write(s->chr, &s->tsr, 1) != 1) { | |
282 | if ((s->tsr_retry >= 0) && (s->tsr_retry <= MAX_XMIT_RETRY)) { | |
283 | s->tsr_retry++; | |
284 | qemu_mod_timer(s->transmit_timer, new_xmit_ts + s->char_transmit_time); | |
285 | return; | |
286 | } else if (s->poll_msl < 0) { | |
287 | /* If we exceed MAX_XMIT_RETRY and the backend is not a real serial port, then | |
288 | drop any further failed writes instantly, until we get one that goes through. | |
289 | This is to prevent guests that log to unconnected pipes or pty's from stalling. */ | |
290 | s->tsr_retry = -1; | |
291 | } | |
292 | } | |
293 | else { | |
294 | s->tsr_retry = 0; | |
295 | } | |
296 | ||
297 | s->last_xmit_ts = qemu_get_clock_ns(vm_clock); | |
298 | if (!(s->lsr & UART_LSR_THRE)) | |
299 | qemu_mod_timer(s->transmit_timer, s->last_xmit_ts + s->char_transmit_time); | |
300 | ||
301 | if (s->lsr & UART_LSR_THRE) { | |
302 | s->lsr |= UART_LSR_TEMT; | |
303 | s->thr_ipending = 1; | |
304 | serial_update_irq(s); | |
305 | } | |
306 | } | |
307 | ||
308 | ||
309 | static void serial_ioport_write(void *opaque, hwaddr addr, uint64_t val, | |
310 | unsigned size) | |
311 | { | |
312 | SerialState *s = opaque; | |
313 | ||
314 | addr &= 7; | |
315 | DPRINTF("write addr=0x%02x val=0x%02x\n", addr, val); | |
316 | switch(addr) { | |
317 | default: | |
318 | case 0: | |
319 | if (s->lcr & UART_LCR_DLAB) { | |
320 | s->divider = (s->divider & 0xff00) | val; | |
321 | serial_update_parameters(s); | |
322 | } else { | |
323 | s->thr = (uint8_t) val; | |
324 | if(s->fcr & UART_FCR_FE) { | |
325 | fifo_put(s, XMIT_FIFO, s->thr); | |
326 | s->thr_ipending = 0; | |
327 | s->lsr &= ~UART_LSR_TEMT; | |
328 | s->lsr &= ~UART_LSR_THRE; | |
329 | serial_update_irq(s); | |
330 | } else { | |
331 | s->thr_ipending = 0; | |
332 | s->lsr &= ~UART_LSR_THRE; | |
333 | serial_update_irq(s); | |
334 | } | |
335 | serial_xmit(s); | |
336 | } | |
337 | break; | |
338 | case 1: | |
339 | if (s->lcr & UART_LCR_DLAB) { | |
340 | s->divider = (s->divider & 0x00ff) | (val << 8); | |
341 | serial_update_parameters(s); | |
342 | } else { | |
343 | s->ier = val & 0x0f; | |
344 | /* If the backend device is a real serial port, turn polling of the modem | |
345 | status lines on physical port on or off depending on UART_IER_MSI state */ | |
346 | if (s->poll_msl >= 0) { | |
347 | if (s->ier & UART_IER_MSI) { | |
348 | s->poll_msl = 1; | |
349 | serial_update_msl(s); | |
350 | } else { | |
351 | qemu_del_timer(s->modem_status_poll); | |
352 | s->poll_msl = 0; | |
353 | } | |
354 | } | |
355 | if (s->lsr & UART_LSR_THRE) { | |
356 | s->thr_ipending = 1; | |
357 | serial_update_irq(s); | |
358 | } | |
359 | } | |
360 | break; | |
361 | case 2: | |
362 | val = val & 0xFF; | |
363 | ||
364 | if (s->fcr == val) | |
365 | break; | |
366 | ||
367 | /* Did the enable/disable flag change? If so, make sure FIFOs get flushed */ | |
368 | if ((val ^ s->fcr) & UART_FCR_FE) | |
369 | val |= UART_FCR_XFR | UART_FCR_RFR; | |
370 | ||
371 | /* FIFO clear */ | |
372 | ||
373 | if (val & UART_FCR_RFR) { | |
374 | qemu_del_timer(s->fifo_timeout_timer); | |
375 | s->timeout_ipending=0; | |
376 | fifo_clear(s,RECV_FIFO); | |
377 | } | |
378 | ||
379 | if (val & UART_FCR_XFR) { | |
380 | fifo_clear(s,XMIT_FIFO); | |
381 | } | |
382 | ||
383 | if (val & UART_FCR_FE) { | |
384 | s->iir |= UART_IIR_FE; | |
385 | /* Set RECV_FIFO trigger Level */ | |
386 | switch (val & 0xC0) { | |
387 | case UART_FCR_ITL_1: | |
388 | s->recv_fifo.itl = 1; | |
389 | break; | |
390 | case UART_FCR_ITL_2: | |
391 | s->recv_fifo.itl = 4; | |
392 | break; | |
393 | case UART_FCR_ITL_3: | |
394 | s->recv_fifo.itl = 8; | |
395 | break; | |
396 | case UART_FCR_ITL_4: | |
397 | s->recv_fifo.itl = 14; | |
398 | break; | |
399 | } | |
400 | } else | |
401 | s->iir &= ~UART_IIR_FE; | |
402 | ||
403 | /* Set fcr - or at least the bits in it that are supposed to "stick" */ | |
404 | s->fcr = val & 0xC9; | |
405 | serial_update_irq(s); | |
406 | break; | |
407 | case 3: | |
408 | { | |
409 | int break_enable; | |
410 | s->lcr = val; | |
411 | serial_update_parameters(s); | |
412 | break_enable = (val >> 6) & 1; | |
413 | if (break_enable != s->last_break_enable) { | |
414 | s->last_break_enable = break_enable; | |
415 | qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK, | |
416 | &break_enable); | |
417 | } | |
418 | } | |
419 | break; | |
420 | case 4: | |
421 | { | |
422 | int flags; | |
423 | int old_mcr = s->mcr; | |
424 | s->mcr = val & 0x1f; | |
425 | if (val & UART_MCR_LOOP) | |
426 | break; | |
427 | ||
428 | if (s->poll_msl >= 0 && old_mcr != s->mcr) { | |
429 | ||
430 | qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags); | |
431 | ||
432 | flags &= ~(CHR_TIOCM_RTS | CHR_TIOCM_DTR); | |
433 | ||
434 | if (val & UART_MCR_RTS) | |
435 | flags |= CHR_TIOCM_RTS; | |
436 | if (val & UART_MCR_DTR) | |
437 | flags |= CHR_TIOCM_DTR; | |
438 | ||
439 | qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_SET_TIOCM, &flags); | |
440 | /* Update the modem status after a one-character-send wait-time, since there may be a response | |
441 | from the device/computer at the other end of the serial line */ | |
442 | qemu_mod_timer(s->modem_status_poll, qemu_get_clock_ns(vm_clock) + s->char_transmit_time); | |
443 | } | |
444 | } | |
445 | break; | |
446 | case 5: | |
447 | break; | |
448 | case 6: | |
449 | break; | |
450 | case 7: | |
451 | s->scr = val; | |
452 | break; | |
453 | } | |
454 | } | |
455 | ||
456 | static uint64_t serial_ioport_read(void *opaque, hwaddr addr, unsigned size) | |
457 | { | |
458 | SerialState *s = opaque; | |
459 | uint32_t ret; | |
460 | ||
461 | addr &= 7; | |
462 | switch(addr) { | |
463 | default: | |
464 | case 0: | |
465 | if (s->lcr & UART_LCR_DLAB) { | |
466 | ret = s->divider & 0xff; | |
467 | } else { | |
468 | if(s->fcr & UART_FCR_FE) { | |
469 | ret = fifo_get(s,RECV_FIFO); | |
470 | if (s->recv_fifo.count == 0) | |
471 | s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); | |
472 | else | |
473 | qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock_ns (vm_clock) + s->char_transmit_time * 4); | |
474 | s->timeout_ipending = 0; | |
475 | } else { | |
476 | ret = s->rbr; | |
477 | s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); | |
478 | } | |
479 | serial_update_irq(s); | |
480 | if (!(s->mcr & UART_MCR_LOOP)) { | |
481 | /* in loopback mode, don't receive any data */ | |
482 | qemu_chr_accept_input(s->chr); | |
483 | } | |
484 | } | |
485 | break; | |
486 | case 1: | |
487 | if (s->lcr & UART_LCR_DLAB) { | |
488 | ret = (s->divider >> 8) & 0xff; | |
489 | } else { | |
490 | ret = s->ier; | |
491 | } | |
492 | break; | |
493 | case 2: | |
494 | ret = s->iir; | |
495 | if ((ret & UART_IIR_ID) == UART_IIR_THRI) { | |
496 | s->thr_ipending = 0; | |
497 | serial_update_irq(s); | |
498 | } | |
499 | break; | |
500 | case 3: | |
501 | ret = s->lcr; | |
502 | break; | |
503 | case 4: | |
504 | ret = s->mcr; | |
505 | break; | |
506 | case 5: | |
507 | ret = s->lsr; | |
508 | /* Clear break and overrun interrupts */ | |
509 | if (s->lsr & (UART_LSR_BI|UART_LSR_OE)) { | |
510 | s->lsr &= ~(UART_LSR_BI|UART_LSR_OE); | |
511 | serial_update_irq(s); | |
512 | } | |
513 | break; | |
514 | case 6: | |
515 | if (s->mcr & UART_MCR_LOOP) { | |
516 | /* in loopback, the modem output pins are connected to the | |
517 | inputs */ | |
518 | ret = (s->mcr & 0x0c) << 4; | |
519 | ret |= (s->mcr & 0x02) << 3; | |
520 | ret |= (s->mcr & 0x01) << 5; | |
521 | } else { | |
522 | if (s->poll_msl >= 0) | |
523 | serial_update_msl(s); | |
524 | ret = s->msr; | |
525 | /* Clear delta bits & msr int after read, if they were set */ | |
526 | if (s->msr & UART_MSR_ANY_DELTA) { | |
527 | s->msr &= 0xF0; | |
528 | serial_update_irq(s); | |
529 | } | |
530 | } | |
531 | break; | |
532 | case 7: | |
533 | ret = s->scr; | |
534 | break; | |
535 | } | |
536 | DPRINTF("read addr=0x%02x val=0x%02x\n", addr, ret); | |
537 | return ret; | |
538 | } | |
539 | ||
540 | static int serial_can_receive(SerialState *s) | |
541 | { | |
542 | if(s->fcr & UART_FCR_FE) { | |
543 | if(s->recv_fifo.count < UART_FIFO_LENGTH) | |
544 | /* Advertise (fifo.itl - fifo.count) bytes when count < ITL, and 1 if above. If UART_FIFO_LENGTH - fifo.count is | |
545 | advertised the effect will be to almost always fill the fifo completely before the guest has a chance to respond, | |
546 | effectively overriding the ITL that the guest has set. */ | |
547 | return (s->recv_fifo.count <= s->recv_fifo.itl) ? s->recv_fifo.itl - s->recv_fifo.count : 1; | |
548 | else | |
549 | return 0; | |
550 | } else { | |
551 | return !(s->lsr & UART_LSR_DR); | |
552 | } | |
553 | } | |
554 | ||
555 | static void serial_receive_break(SerialState *s) | |
556 | { | |
557 | s->rbr = 0; | |
558 | /* When the LSR_DR is set a null byte is pushed into the fifo */ | |
559 | fifo_put(s, RECV_FIFO, '\0'); | |
560 | s->lsr |= UART_LSR_BI | UART_LSR_DR; | |
561 | serial_update_irq(s); | |
562 | } | |
563 | ||
564 | /* There's data in recv_fifo and s->rbr has not been read for 4 char transmit times */ | |
565 | static void fifo_timeout_int (void *opaque) { | |
566 | SerialState *s = opaque; | |
567 | if (s->recv_fifo.count) { | |
568 | s->timeout_ipending = 1; | |
569 | serial_update_irq(s); | |
570 | } | |
571 | } | |
572 | ||
573 | static int serial_can_receive1(void *opaque) | |
574 | { | |
575 | SerialState *s = opaque; | |
576 | return serial_can_receive(s); | |
577 | } | |
578 | ||
579 | static void serial_receive1(void *opaque, const uint8_t *buf, int size) | |
580 | { | |
581 | SerialState *s = opaque; | |
582 | ||
583 | if (s->wakeup) { | |
584 | qemu_system_wakeup_request(QEMU_WAKEUP_REASON_OTHER); | |
585 | } | |
586 | if(s->fcr & UART_FCR_FE) { | |
587 | int i; | |
588 | for (i = 0; i < size; i++) { | |
589 | fifo_put(s, RECV_FIFO, buf[i]); | |
590 | } | |
591 | s->lsr |= UART_LSR_DR; | |
592 | /* call the timeout receive callback in 4 char transmit time */ | |
593 | qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock_ns (vm_clock) + s->char_transmit_time * 4); | |
594 | } else { | |
595 | if (s->lsr & UART_LSR_DR) | |
596 | s->lsr |= UART_LSR_OE; | |
597 | s->rbr = buf[0]; | |
598 | s->lsr |= UART_LSR_DR; | |
599 | } | |
600 | serial_update_irq(s); | |
601 | } | |
602 | ||
603 | static void serial_event(void *opaque, int event) | |
604 | { | |
605 | SerialState *s = opaque; | |
606 | DPRINTF("event %x\n", event); | |
607 | if (event == CHR_EVENT_BREAK) | |
608 | serial_receive_break(s); | |
609 | } | |
610 | ||
611 | static void serial_pre_save(void *opaque) | |
612 | { | |
613 | SerialState *s = opaque; | |
614 | s->fcr_vmstate = s->fcr; | |
615 | } | |
616 | ||
617 | static int serial_post_load(void *opaque, int version_id) | |
618 | { | |
619 | SerialState *s = opaque; | |
620 | ||
621 | if (version_id < 3) { | |
622 | s->fcr_vmstate = 0; | |
623 | } | |
624 | /* Initialize fcr via setter to perform essential side-effects */ | |
625 | serial_ioport_write(s, 0x02, s->fcr_vmstate, 1); | |
626 | serial_update_parameters(s); | |
627 | return 0; | |
628 | } | |
629 | ||
630 | const VMStateDescription vmstate_serial = { | |
631 | .name = "serial", | |
632 | .version_id = 3, | |
633 | .minimum_version_id = 2, | |
634 | .pre_save = serial_pre_save, | |
635 | .post_load = serial_post_load, | |
636 | .fields = (VMStateField []) { | |
637 | VMSTATE_UINT16_V(divider, SerialState, 2), | |
638 | VMSTATE_UINT8(rbr, SerialState), | |
639 | VMSTATE_UINT8(ier, SerialState), | |
640 | VMSTATE_UINT8(iir, SerialState), | |
641 | VMSTATE_UINT8(lcr, SerialState), | |
642 | VMSTATE_UINT8(mcr, SerialState), | |
643 | VMSTATE_UINT8(lsr, SerialState), | |
644 | VMSTATE_UINT8(msr, SerialState), | |
645 | VMSTATE_UINT8(scr, SerialState), | |
646 | VMSTATE_UINT8_V(fcr_vmstate, SerialState, 3), | |
647 | VMSTATE_END_OF_LIST() | |
648 | } | |
649 | }; | |
650 | ||
651 | static void serial_reset(void *opaque) | |
652 | { | |
653 | SerialState *s = opaque; | |
654 | ||
655 | s->rbr = 0; | |
656 | s->ier = 0; | |
657 | s->iir = UART_IIR_NO_INT; | |
658 | s->lcr = 0; | |
659 | s->lsr = UART_LSR_TEMT | UART_LSR_THRE; | |
660 | s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS; | |
661 | /* Default to 9600 baud, 1 start bit, 8 data bits, 1 stop bit, no parity. */ | |
662 | s->divider = 0x0C; | |
663 | s->mcr = UART_MCR_OUT2; | |
664 | s->scr = 0; | |
665 | s->tsr_retry = 0; | |
666 | s->char_transmit_time = (get_ticks_per_sec() / 9600) * 10; | |
667 | s->poll_msl = 0; | |
668 | ||
669 | fifo_clear(s,RECV_FIFO); | |
670 | fifo_clear(s,XMIT_FIFO); | |
671 | ||
672 | s->last_xmit_ts = qemu_get_clock_ns(vm_clock); | |
673 | ||
674 | s->thr_ipending = 0; | |
675 | s->last_break_enable = 0; | |
676 | qemu_irq_lower(s->irq); | |
677 | } | |
678 | ||
679 | void serial_init_core(SerialState *s) | |
680 | { | |
681 | if (!s->chr) { | |
682 | fprintf(stderr, "Can't create serial device, empty char device\n"); | |
683 | exit(1); | |
684 | } | |
685 | ||
686 | s->modem_status_poll = qemu_new_timer_ns(vm_clock, (QEMUTimerCB *) serial_update_msl, s); | |
687 | ||
688 | s->fifo_timeout_timer = qemu_new_timer_ns(vm_clock, (QEMUTimerCB *) fifo_timeout_int, s); | |
689 | s->transmit_timer = qemu_new_timer_ns(vm_clock, (QEMUTimerCB *) serial_xmit, s); | |
690 | ||
691 | qemu_register_reset(serial_reset, s); | |
692 | ||
693 | qemu_chr_add_handlers(s->chr, serial_can_receive1, serial_receive1, | |
694 | serial_event, s); | |
695 | } | |
696 | ||
697 | void serial_exit_core(SerialState *s) | |
698 | { | |
699 | qemu_chr_add_handlers(s->chr, NULL, NULL, NULL, NULL); | |
700 | qemu_unregister_reset(serial_reset, s); | |
701 | } | |
702 | ||
703 | /* Change the main reference oscillator frequency. */ | |
704 | void serial_set_frequency(SerialState *s, uint32_t frequency) | |
705 | { | |
706 | s->baudbase = frequency; | |
707 | serial_update_parameters(s); | |
708 | } | |
709 | ||
710 | const MemoryRegionOps serial_io_ops = { | |
711 | .read = serial_ioport_read, | |
712 | .write = serial_ioport_write, | |
713 | .impl = { | |
714 | .min_access_size = 1, | |
715 | .max_access_size = 1, | |
716 | }, | |
717 | .endianness = DEVICE_LITTLE_ENDIAN, | |
718 | }; | |
719 | ||
720 | SerialState *serial_init(int base, qemu_irq irq, int baudbase, | |
721 | CharDriverState *chr, MemoryRegion *system_io) | |
722 | { | |
723 | SerialState *s; | |
724 | ||
725 | s = g_malloc0(sizeof(SerialState)); | |
726 | ||
727 | s->irq = irq; | |
728 | s->baudbase = baudbase; | |
729 | s->chr = chr; | |
730 | serial_init_core(s); | |
731 | ||
732 | vmstate_register(NULL, base, &vmstate_serial, s); | |
733 | ||
734 | memory_region_init_io(&s->io, &serial_io_ops, s, "serial", 8); | |
735 | memory_region_add_subregion(system_io, base, &s->io); | |
736 | ||
737 | return s; | |
738 | } | |
739 | ||
740 | /* Memory mapped interface */ | |
741 | static uint64_t serial_mm_read(void *opaque, hwaddr addr, | |
742 | unsigned size) | |
743 | { | |
744 | SerialState *s = opaque; | |
745 | return serial_ioport_read(s, addr >> s->it_shift, 1); | |
746 | } | |
747 | ||
748 | static void serial_mm_write(void *opaque, hwaddr addr, | |
749 | uint64_t value, unsigned size) | |
750 | { | |
751 | SerialState *s = opaque; | |
752 | value &= ~0u >> (32 - (size * 8)); | |
753 | serial_ioport_write(s, addr >> s->it_shift, value, 1); | |
754 | } | |
755 | ||
756 | static const MemoryRegionOps serial_mm_ops[3] = { | |
757 | [DEVICE_NATIVE_ENDIAN] = { | |
758 | .read = serial_mm_read, | |
759 | .write = serial_mm_write, | |
760 | .endianness = DEVICE_NATIVE_ENDIAN, | |
761 | }, | |
762 | [DEVICE_LITTLE_ENDIAN] = { | |
763 | .read = serial_mm_read, | |
764 | .write = serial_mm_write, | |
765 | .endianness = DEVICE_LITTLE_ENDIAN, | |
766 | }, | |
767 | [DEVICE_BIG_ENDIAN] = { | |
768 | .read = serial_mm_read, | |
769 | .write = serial_mm_write, | |
770 | .endianness = DEVICE_BIG_ENDIAN, | |
771 | }, | |
772 | }; | |
773 | ||
774 | SerialState *serial_mm_init(MemoryRegion *address_space, | |
775 | hwaddr base, int it_shift, | |
776 | qemu_irq irq, int baudbase, | |
777 | CharDriverState *chr, enum device_endian end) | |
778 | { | |
779 | SerialState *s; | |
780 | ||
781 | s = g_malloc0(sizeof(SerialState)); | |
782 | ||
783 | s->it_shift = it_shift; | |
784 | s->irq = irq; | |
785 | s->baudbase = baudbase; | |
786 | s->chr = chr; | |
787 | ||
788 | serial_init_core(s); | |
789 | vmstate_register(NULL, base, &vmstate_serial, s); | |
790 | ||
791 | memory_region_init_io(&s->io, &serial_mm_ops[end], s, | |
792 | "serial", 8 << it_shift); | |
793 | memory_region_add_subregion(address_space, base, &s->io); | |
794 | ||
795 | serial_update_msl(s); | |
796 | return s; | |
797 | } |