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1 | /* | |
2 | * QEMU Sparc SLAVIO interrupt controller emulation | |
3 | * | |
4 | * Copyright (c) 2003-2005 Fabrice Bellard | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
25 | #include "sun4m.h" | |
26 | #include "monitor.h" | |
27 | #include "sysbus.h" | |
28 | #include "trace.h" | |
29 | ||
30 | //#define DEBUG_IRQ_COUNT | |
31 | ||
32 | /* | |
33 | * Registers of interrupt controller in sun4m. | |
34 | * | |
35 | * This is the interrupt controller part of chip STP2001 (Slave I/O), also | |
36 | * produced as NCR89C105. See | |
37 | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt | |
38 | * | |
39 | * There is a system master controller and one for each cpu. | |
40 | * | |
41 | */ | |
42 | ||
43 | #define MAX_CPUS 16 | |
44 | #define MAX_PILS 16 | |
45 | ||
46 | struct SLAVIO_INTCTLState; | |
47 | ||
48 | typedef struct SLAVIO_CPUINTCTLState { | |
49 | uint32_t intreg_pending; | |
50 | struct SLAVIO_INTCTLState *master; | |
51 | uint32_t cpu; | |
52 | uint32_t irl_out; | |
53 | } SLAVIO_CPUINTCTLState; | |
54 | ||
55 | typedef struct SLAVIO_INTCTLState { | |
56 | SysBusDevice busdev; | |
57 | uint32_t intregm_pending; | |
58 | uint32_t intregm_disabled; | |
59 | uint32_t target_cpu; | |
60 | #ifdef DEBUG_IRQ_COUNT | |
61 | uint64_t irq_count[32]; | |
62 | #endif | |
63 | qemu_irq cpu_irqs[MAX_CPUS][MAX_PILS]; | |
64 | SLAVIO_CPUINTCTLState slaves[MAX_CPUS]; | |
65 | } SLAVIO_INTCTLState; | |
66 | ||
67 | #define INTCTL_MAXADDR 0xf | |
68 | #define INTCTL_SIZE (INTCTL_MAXADDR + 1) | |
69 | #define INTCTLM_SIZE 0x14 | |
70 | #define MASTER_IRQ_MASK ~0x0fa2007f | |
71 | #define MASTER_DISABLE 0x80000000 | |
72 | #define CPU_SOFTIRQ_MASK 0xfffe0000 | |
73 | #define CPU_IRQ_INT15_IN (1 << 15) | |
74 | #define CPU_IRQ_TIMER_IN (1 << 14) | |
75 | ||
76 | static void slavio_check_interrupts(SLAVIO_INTCTLState *s, int set_irqs); | |
77 | ||
78 | // per-cpu interrupt controller | |
79 | static uint32_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr) | |
80 | { | |
81 | SLAVIO_CPUINTCTLState *s = opaque; | |
82 | uint32_t saddr, ret; | |
83 | ||
84 | saddr = addr >> 2; | |
85 | switch (saddr) { | |
86 | case 0: | |
87 | ret = s->intreg_pending; | |
88 | break; | |
89 | default: | |
90 | ret = 0; | |
91 | break; | |
92 | } | |
93 | trace_slavio_intctl_mem_readl(s->cpu, addr, ret); | |
94 | ||
95 | return ret; | |
96 | } | |
97 | ||
98 | static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr, | |
99 | uint32_t val) | |
100 | { | |
101 | SLAVIO_CPUINTCTLState *s = opaque; | |
102 | uint32_t saddr; | |
103 | ||
104 | saddr = addr >> 2; | |
105 | trace_slavio_intctl_mem_writel(s->cpu, addr, val); | |
106 | switch (saddr) { | |
107 | case 1: // clear pending softints | |
108 | val &= CPU_SOFTIRQ_MASK | CPU_IRQ_INT15_IN; | |
109 | s->intreg_pending &= ~val; | |
110 | slavio_check_interrupts(s->master, 1); | |
111 | trace_slavio_intctl_mem_writel_clear(s->cpu, val, s->intreg_pending); | |
112 | break; | |
113 | case 2: // set softint | |
114 | val &= CPU_SOFTIRQ_MASK; | |
115 | s->intreg_pending |= val; | |
116 | slavio_check_interrupts(s->master, 1); | |
117 | trace_slavio_intctl_mem_writel_set(s->cpu, val, s->intreg_pending); | |
118 | break; | |
119 | default: | |
120 | break; | |
121 | } | |
122 | } | |
123 | ||
124 | static CPUReadMemoryFunc * const slavio_intctl_mem_read[3] = { | |
125 | NULL, | |
126 | NULL, | |
127 | slavio_intctl_mem_readl, | |
128 | }; | |
129 | ||
130 | static CPUWriteMemoryFunc * const slavio_intctl_mem_write[3] = { | |
131 | NULL, | |
132 | NULL, | |
133 | slavio_intctl_mem_writel, | |
134 | }; | |
135 | ||
136 | // master system interrupt controller | |
137 | static uint32_t slavio_intctlm_mem_readl(void *opaque, target_phys_addr_t addr) | |
138 | { | |
139 | SLAVIO_INTCTLState *s = opaque; | |
140 | uint32_t saddr, ret; | |
141 | ||
142 | saddr = addr >> 2; | |
143 | switch (saddr) { | |
144 | case 0: | |
145 | ret = s->intregm_pending & ~MASTER_DISABLE; | |
146 | break; | |
147 | case 1: | |
148 | ret = s->intregm_disabled & MASTER_IRQ_MASK; | |
149 | break; | |
150 | case 4: | |
151 | ret = s->target_cpu; | |
152 | break; | |
153 | default: | |
154 | ret = 0; | |
155 | break; | |
156 | } | |
157 | trace_slavio_intctlm_mem_readl(addr, ret); | |
158 | ||
159 | return ret; | |
160 | } | |
161 | ||
162 | static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr, | |
163 | uint32_t val) | |
164 | { | |
165 | SLAVIO_INTCTLState *s = opaque; | |
166 | uint32_t saddr; | |
167 | ||
168 | saddr = addr >> 2; | |
169 | trace_slavio_intctlm_mem_writel(addr, val); | |
170 | switch (saddr) { | |
171 | case 2: // clear (enable) | |
172 | // Force clear unused bits | |
173 | val &= MASTER_IRQ_MASK; | |
174 | s->intregm_disabled &= ~val; | |
175 | trace_slavio_intctlm_mem_writel_enable(val, s->intregm_disabled); | |
176 | slavio_check_interrupts(s, 1); | |
177 | break; | |
178 | case 3: // set (disable; doesn't affect pending) | |
179 | // Force clear unused bits | |
180 | val &= MASTER_IRQ_MASK; | |
181 | s->intregm_disabled |= val; | |
182 | slavio_check_interrupts(s, 1); | |
183 | trace_slavio_intctlm_mem_writel_disable(val, s->intregm_disabled); | |
184 | break; | |
185 | case 4: | |
186 | s->target_cpu = val & (MAX_CPUS - 1); | |
187 | slavio_check_interrupts(s, 1); | |
188 | trace_slavio_intctlm_mem_writel_target(s->target_cpu); | |
189 | break; | |
190 | default: | |
191 | break; | |
192 | } | |
193 | } | |
194 | ||
195 | static CPUReadMemoryFunc * const slavio_intctlm_mem_read[3] = { | |
196 | NULL, | |
197 | NULL, | |
198 | slavio_intctlm_mem_readl, | |
199 | }; | |
200 | ||
201 | static CPUWriteMemoryFunc * const slavio_intctlm_mem_write[3] = { | |
202 | NULL, | |
203 | NULL, | |
204 | slavio_intctlm_mem_writel, | |
205 | }; | |
206 | ||
207 | void slavio_pic_info(Monitor *mon, DeviceState *dev) | |
208 | { | |
209 | SysBusDevice *sd; | |
210 | SLAVIO_INTCTLState *s; | |
211 | int i; | |
212 | ||
213 | sd = sysbus_from_qdev(dev); | |
214 | s = FROM_SYSBUS(SLAVIO_INTCTLState, sd); | |
215 | for (i = 0; i < MAX_CPUS; i++) { | |
216 | monitor_printf(mon, "per-cpu %d: pending 0x%08x\n", i, | |
217 | s->slaves[i].intreg_pending); | |
218 | } | |
219 | monitor_printf(mon, "master: pending 0x%08x, disabled 0x%08x\n", | |
220 | s->intregm_pending, s->intregm_disabled); | |
221 | } | |
222 | ||
223 | void slavio_irq_info(Monitor *mon, DeviceState *dev) | |
224 | { | |
225 | #ifndef DEBUG_IRQ_COUNT | |
226 | monitor_printf(mon, "irq statistic code not compiled.\n"); | |
227 | #else | |
228 | SysBusDevice *sd; | |
229 | SLAVIO_INTCTLState *s; | |
230 | int i; | |
231 | int64_t count; | |
232 | ||
233 | sd = sysbus_from_qdev(dev); | |
234 | s = FROM_SYSBUS(SLAVIO_INTCTLState, sd); | |
235 | monitor_printf(mon, "IRQ statistics:\n"); | |
236 | for (i = 0; i < 32; i++) { | |
237 | count = s->irq_count[i]; | |
238 | if (count > 0) | |
239 | monitor_printf(mon, "%2d: %" PRId64 "\n", i, count); | |
240 | } | |
241 | #endif | |
242 | } | |
243 | ||
244 | static const uint32_t intbit_to_level[] = { | |
245 | 2, 3, 5, 7, 9, 11, 13, 2, 3, 5, 7, 9, 11, 13, 12, 12, | |
246 | 6, 13, 4, 10, 8, 9, 11, 0, 0, 0, 0, 15, 15, 15, 15, 0, | |
247 | }; | |
248 | ||
249 | static void slavio_check_interrupts(SLAVIO_INTCTLState *s, int set_irqs) | |
250 | { | |
251 | uint32_t pending = s->intregm_pending, pil_pending; | |
252 | unsigned int i, j; | |
253 | ||
254 | pending &= ~s->intregm_disabled; | |
255 | ||
256 | trace_slavio_check_interrupts(pending, s->intregm_disabled); | |
257 | for (i = 0; i < MAX_CPUS; i++) { | |
258 | pil_pending = 0; | |
259 | ||
260 | /* If we are the current interrupt target, get hard interrupts */ | |
261 | if (pending && !(s->intregm_disabled & MASTER_DISABLE) && | |
262 | (i == s->target_cpu)) { | |
263 | for (j = 0; j < 32; j++) { | |
264 | if ((pending & (1 << j)) && intbit_to_level[j]) { | |
265 | pil_pending |= 1 << intbit_to_level[j]; | |
266 | } | |
267 | } | |
268 | } | |
269 | ||
270 | /* Calculate current pending hard interrupts for display */ | |
271 | s->slaves[i].intreg_pending &= CPU_SOFTIRQ_MASK | CPU_IRQ_INT15_IN | | |
272 | CPU_IRQ_TIMER_IN; | |
273 | if (i == s->target_cpu) { | |
274 | for (j = 0; j < 32; j++) { | |
275 | if ((s->intregm_pending & (1 << j)) && intbit_to_level[j]) { | |
276 | s->slaves[i].intreg_pending |= 1 << intbit_to_level[j]; | |
277 | } | |
278 | } | |
279 | } | |
280 | ||
281 | /* Level 15 and CPU timer interrupts are only masked when | |
282 | the MASTER_DISABLE bit is set */ | |
283 | if (!(s->intregm_disabled & MASTER_DISABLE)) { | |
284 | pil_pending |= s->slaves[i].intreg_pending & | |
285 | (CPU_IRQ_INT15_IN | CPU_IRQ_TIMER_IN); | |
286 | } | |
287 | ||
288 | /* Add soft interrupts */ | |
289 | pil_pending |= (s->slaves[i].intreg_pending & CPU_SOFTIRQ_MASK) >> 16; | |
290 | ||
291 | if (set_irqs) { | |
292 | for (j = MAX_PILS; j > 0; j--) { | |
293 | if (pil_pending & (1 << j)) { | |
294 | if (!(s->slaves[i].irl_out & (1 << j))) { | |
295 | qemu_irq_raise(s->cpu_irqs[i][j]); | |
296 | } | |
297 | } else { | |
298 | if (s->slaves[i].irl_out & (1 << j)) { | |
299 | qemu_irq_lower(s->cpu_irqs[i][j]); | |
300 | } | |
301 | } | |
302 | } | |
303 | } | |
304 | s->slaves[i].irl_out = pil_pending; | |
305 | } | |
306 | } | |
307 | ||
308 | /* | |
309 | * "irq" here is the bit number in the system interrupt register to | |
310 | * separate serial and keyboard interrupts sharing a level. | |
311 | */ | |
312 | static void slavio_set_irq(void *opaque, int irq, int level) | |
313 | { | |
314 | SLAVIO_INTCTLState *s = opaque; | |
315 | uint32_t mask = 1 << irq; | |
316 | uint32_t pil = intbit_to_level[irq]; | |
317 | unsigned int i; | |
318 | ||
319 | trace_slavio_set_irq(s->target_cpu, irq, pil, level); | |
320 | if (pil > 0) { | |
321 | if (level) { | |
322 | #ifdef DEBUG_IRQ_COUNT | |
323 | s->irq_count[pil]++; | |
324 | #endif | |
325 | s->intregm_pending |= mask; | |
326 | if (pil == 15) { | |
327 | for (i = 0; i < MAX_CPUS; i++) { | |
328 | s->slaves[i].intreg_pending |= 1 << pil; | |
329 | } | |
330 | } | |
331 | } else { | |
332 | s->intregm_pending &= ~mask; | |
333 | if (pil == 15) { | |
334 | for (i = 0; i < MAX_CPUS; i++) { | |
335 | s->slaves[i].intreg_pending &= ~(1 << pil); | |
336 | } | |
337 | } | |
338 | } | |
339 | slavio_check_interrupts(s, 1); | |
340 | } | |
341 | } | |
342 | ||
343 | static void slavio_set_timer_irq_cpu(void *opaque, int cpu, int level) | |
344 | { | |
345 | SLAVIO_INTCTLState *s = opaque; | |
346 | ||
347 | trace_slavio_set_timer_irq_cpu(cpu, level); | |
348 | ||
349 | if (level) { | |
350 | s->slaves[cpu].intreg_pending |= CPU_IRQ_TIMER_IN; | |
351 | } else { | |
352 | s->slaves[cpu].intreg_pending &= ~CPU_IRQ_TIMER_IN; | |
353 | } | |
354 | ||
355 | slavio_check_interrupts(s, 1); | |
356 | } | |
357 | ||
358 | static void slavio_set_irq_all(void *opaque, int irq, int level) | |
359 | { | |
360 | if (irq < 32) { | |
361 | slavio_set_irq(opaque, irq, level); | |
362 | } else { | |
363 | slavio_set_timer_irq_cpu(opaque, irq - 32, level); | |
364 | } | |
365 | } | |
366 | ||
367 | static int vmstate_intctl_post_load(void *opaque, int version_id) | |
368 | { | |
369 | SLAVIO_INTCTLState *s = opaque; | |
370 | ||
371 | slavio_check_interrupts(s, 0); | |
372 | return 0; | |
373 | } | |
374 | ||
375 | static const VMStateDescription vmstate_intctl_cpu = { | |
376 | .name ="slavio_intctl_cpu", | |
377 | .version_id = 1, | |
378 | .minimum_version_id = 1, | |
379 | .minimum_version_id_old = 1, | |
380 | .fields = (VMStateField []) { | |
381 | VMSTATE_UINT32(intreg_pending, SLAVIO_CPUINTCTLState), | |
382 | VMSTATE_END_OF_LIST() | |
383 | } | |
384 | }; | |
385 | ||
386 | static const VMStateDescription vmstate_intctl = { | |
387 | .name ="slavio_intctl", | |
388 | .version_id = 1, | |
389 | .minimum_version_id = 1, | |
390 | .minimum_version_id_old = 1, | |
391 | .post_load = vmstate_intctl_post_load, | |
392 | .fields = (VMStateField []) { | |
393 | VMSTATE_STRUCT_ARRAY(slaves, SLAVIO_INTCTLState, MAX_CPUS, 1, | |
394 | vmstate_intctl_cpu, SLAVIO_CPUINTCTLState), | |
395 | VMSTATE_UINT32(intregm_pending, SLAVIO_INTCTLState), | |
396 | VMSTATE_UINT32(intregm_disabled, SLAVIO_INTCTLState), | |
397 | VMSTATE_UINT32(target_cpu, SLAVIO_INTCTLState), | |
398 | VMSTATE_END_OF_LIST() | |
399 | } | |
400 | }; | |
401 | ||
402 | static void slavio_intctl_reset(DeviceState *d) | |
403 | { | |
404 | SLAVIO_INTCTLState *s = container_of(d, SLAVIO_INTCTLState, busdev.qdev); | |
405 | int i; | |
406 | ||
407 | for (i = 0; i < MAX_CPUS; i++) { | |
408 | s->slaves[i].intreg_pending = 0; | |
409 | s->slaves[i].irl_out = 0; | |
410 | } | |
411 | s->intregm_disabled = ~MASTER_IRQ_MASK; | |
412 | s->intregm_pending = 0; | |
413 | s->target_cpu = 0; | |
414 | slavio_check_interrupts(s, 0); | |
415 | } | |
416 | ||
417 | static int slavio_intctl_init1(SysBusDevice *dev) | |
418 | { | |
419 | SLAVIO_INTCTLState *s = FROM_SYSBUS(SLAVIO_INTCTLState, dev); | |
420 | int io_memory; | |
421 | unsigned int i, j; | |
422 | ||
423 | qdev_init_gpio_in(&dev->qdev, slavio_set_irq_all, 32 + MAX_CPUS); | |
424 | io_memory = cpu_register_io_memory(slavio_intctlm_mem_read, | |
425 | slavio_intctlm_mem_write, s, | |
426 | DEVICE_NATIVE_ENDIAN); | |
427 | sysbus_init_mmio(dev, INTCTLM_SIZE, io_memory); | |
428 | ||
429 | for (i = 0; i < MAX_CPUS; i++) { | |
430 | for (j = 0; j < MAX_PILS; j++) { | |
431 | sysbus_init_irq(dev, &s->cpu_irqs[i][j]); | |
432 | } | |
433 | io_memory = cpu_register_io_memory(slavio_intctl_mem_read, | |
434 | slavio_intctl_mem_write, | |
435 | &s->slaves[i], | |
436 | DEVICE_NATIVE_ENDIAN); | |
437 | sysbus_init_mmio(dev, INTCTL_SIZE, io_memory); | |
438 | s->slaves[i].cpu = i; | |
439 | s->slaves[i].master = s; | |
440 | } | |
441 | ||
442 | return 0; | |
443 | } | |
444 | ||
445 | static SysBusDeviceInfo slavio_intctl_info = { | |
446 | .init = slavio_intctl_init1, | |
447 | .qdev.name = "slavio_intctl", | |
448 | .qdev.size = sizeof(SLAVIO_INTCTLState), | |
449 | .qdev.vmsd = &vmstate_intctl, | |
450 | .qdev.reset = slavio_intctl_reset, | |
451 | }; | |
452 | ||
453 | static void slavio_intctl_register_devices(void) | |
454 | { | |
455 | sysbus_register_withprop(&slavio_intctl_info); | |
456 | } | |
457 | ||
458 | device_init(slavio_intctl_register_devices) |