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1 | /* | |
2 | * QEMU Sun4u/Sun4v System Emulator | |
3 | * | |
4 | * Copyright (c) 2005 Fabrice Bellard | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | #include "qemu/osdep.h" | |
25 | #include "qapi/error.h" | |
26 | #include "hw/hw.h" | |
27 | #include "hw/pci/pci.h" | |
28 | #include "hw/pci-host/apb.h" | |
29 | #include "hw/i386/pc.h" | |
30 | #include "hw/char/serial.h" | |
31 | #include "hw/timer/m48t59.h" | |
32 | #include "hw/block/fdc.h" | |
33 | #include "net/net.h" | |
34 | #include "qemu/timer.h" | |
35 | #include "sysemu/sysemu.h" | |
36 | #include "hw/boards.h" | |
37 | #include "hw/nvram/openbios_firmware_abi.h" | |
38 | #include "hw/nvram/fw_cfg.h" | |
39 | #include "hw/sysbus.h" | |
40 | #include "hw/ide.h" | |
41 | #include "hw/loader.h" | |
42 | #include "elf.h" | |
43 | #include "sysemu/block-backend.h" | |
44 | #include "exec/address-spaces.h" | |
45 | ||
46 | //#define DEBUG_IRQ | |
47 | //#define DEBUG_EBUS | |
48 | //#define DEBUG_TIMER | |
49 | ||
50 | #ifdef DEBUG_IRQ | |
51 | #define CPUIRQ_DPRINTF(fmt, ...) \ | |
52 | do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) | |
53 | #else | |
54 | #define CPUIRQ_DPRINTF(fmt, ...) | |
55 | #endif | |
56 | ||
57 | #ifdef DEBUG_EBUS | |
58 | #define EBUS_DPRINTF(fmt, ...) \ | |
59 | do { printf("EBUS: " fmt , ## __VA_ARGS__); } while (0) | |
60 | #else | |
61 | #define EBUS_DPRINTF(fmt, ...) | |
62 | #endif | |
63 | ||
64 | #ifdef DEBUG_TIMER | |
65 | #define TIMER_DPRINTF(fmt, ...) \ | |
66 | do { printf("TIMER: " fmt , ## __VA_ARGS__); } while (0) | |
67 | #else | |
68 | #define TIMER_DPRINTF(fmt, ...) | |
69 | #endif | |
70 | ||
71 | #define KERNEL_LOAD_ADDR 0x00404000 | |
72 | #define CMDLINE_ADDR 0x003ff000 | |
73 | #define PROM_SIZE_MAX (4 * 1024 * 1024) | |
74 | #define PROM_VADDR 0x000ffd00000ULL | |
75 | #define APB_SPECIAL_BASE 0x1fe00000000ULL | |
76 | #define APB_MEM_BASE 0x1ff00000000ULL | |
77 | #define APB_PCI_IO_BASE (APB_SPECIAL_BASE + 0x02000000ULL) | |
78 | #define PROM_FILENAME "openbios-sparc64" | |
79 | #define NVRAM_SIZE 0x2000 | |
80 | #define MAX_IDE_BUS 2 | |
81 | #define BIOS_CFG_IOPORT 0x510 | |
82 | #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00) | |
83 | #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01) | |
84 | #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02) | |
85 | ||
86 | #define IVEC_MAX 0x40 | |
87 | ||
88 | #define TICK_MAX 0x7fffffffffffffffULL | |
89 | ||
90 | struct hwdef { | |
91 | const char * const default_cpu_model; | |
92 | uint16_t machine_id; | |
93 | uint64_t prom_addr; | |
94 | uint64_t console_serial_base; | |
95 | }; | |
96 | ||
97 | typedef struct EbusState { | |
98 | PCIDevice pci_dev; | |
99 | MemoryRegion bar0; | |
100 | MemoryRegion bar1; | |
101 | } EbusState; | |
102 | ||
103 | void DMA_init(ISABus *bus, int high_page_enable) | |
104 | { | |
105 | } | |
106 | ||
107 | static void fw_cfg_boot_set(void *opaque, const char *boot_device, | |
108 | Error **errp) | |
109 | { | |
110 | fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); | |
111 | } | |
112 | ||
113 | static int sun4u_NVRAM_set_params(Nvram *nvram, uint16_t NVRAM_size, | |
114 | const char *arch, ram_addr_t RAM_size, | |
115 | const char *boot_devices, | |
116 | uint32_t kernel_image, uint32_t kernel_size, | |
117 | const char *cmdline, | |
118 | uint32_t initrd_image, uint32_t initrd_size, | |
119 | uint32_t NVRAM_image, | |
120 | int width, int height, int depth, | |
121 | const uint8_t *macaddr) | |
122 | { | |
123 | unsigned int i; | |
124 | uint32_t start, end; | |
125 | uint8_t image[0x1ff0]; | |
126 | struct OpenBIOS_nvpart_v1 *part_header; | |
127 | NvramClass *k = NVRAM_GET_CLASS(nvram); | |
128 | ||
129 | memset(image, '\0', sizeof(image)); | |
130 | ||
131 | start = 0; | |
132 | ||
133 | // OpenBIOS nvram variables | |
134 | // Variable partition | |
135 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start]; | |
136 | part_header->signature = OPENBIOS_PART_SYSTEM; | |
137 | pstrcpy(part_header->name, sizeof(part_header->name), "system"); | |
138 | ||
139 | end = start + sizeof(struct OpenBIOS_nvpart_v1); | |
140 | for (i = 0; i < nb_prom_envs; i++) | |
141 | end = OpenBIOS_set_var(image, end, prom_envs[i]); | |
142 | ||
143 | // End marker | |
144 | image[end++] = '\0'; | |
145 | ||
146 | end = start + ((end - start + 15) & ~15); | |
147 | OpenBIOS_finish_partition(part_header, end - start); | |
148 | ||
149 | // free partition | |
150 | start = end; | |
151 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start]; | |
152 | part_header->signature = OPENBIOS_PART_FREE; | |
153 | pstrcpy(part_header->name, sizeof(part_header->name), "free"); | |
154 | ||
155 | end = 0x1fd0; | |
156 | OpenBIOS_finish_partition(part_header, end - start); | |
157 | ||
158 | Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80); | |
159 | ||
160 | for (i = 0; i < sizeof(image); i++) { | |
161 | (k->write)(nvram, i, image[i]); | |
162 | } | |
163 | ||
164 | return 0; | |
165 | } | |
166 | ||
167 | static uint64_t sun4u_load_kernel(const char *kernel_filename, | |
168 | const char *initrd_filename, | |
169 | ram_addr_t RAM_size, uint64_t *initrd_size, | |
170 | uint64_t *initrd_addr, uint64_t *kernel_addr, | |
171 | uint64_t *kernel_entry) | |
172 | { | |
173 | int linux_boot; | |
174 | unsigned int i; | |
175 | long kernel_size; | |
176 | uint8_t *ptr; | |
177 | uint64_t kernel_top; | |
178 | ||
179 | linux_boot = (kernel_filename != NULL); | |
180 | ||
181 | kernel_size = 0; | |
182 | if (linux_boot) { | |
183 | int bswap_needed; | |
184 | ||
185 | #ifdef BSWAP_NEEDED | |
186 | bswap_needed = 1; | |
187 | #else | |
188 | bswap_needed = 0; | |
189 | #endif | |
190 | kernel_size = load_elf(kernel_filename, NULL, NULL, kernel_entry, | |
191 | kernel_addr, &kernel_top, 1, EM_SPARCV9, 0, 0); | |
192 | if (kernel_size < 0) { | |
193 | *kernel_addr = KERNEL_LOAD_ADDR; | |
194 | *kernel_entry = KERNEL_LOAD_ADDR; | |
195 | kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, | |
196 | RAM_size - KERNEL_LOAD_ADDR, bswap_needed, | |
197 | TARGET_PAGE_SIZE); | |
198 | } | |
199 | if (kernel_size < 0) { | |
200 | kernel_size = load_image_targphys(kernel_filename, | |
201 | KERNEL_LOAD_ADDR, | |
202 | RAM_size - KERNEL_LOAD_ADDR); | |
203 | } | |
204 | if (kernel_size < 0) { | |
205 | fprintf(stderr, "qemu: could not load kernel '%s'\n", | |
206 | kernel_filename); | |
207 | exit(1); | |
208 | } | |
209 | /* load initrd above kernel */ | |
210 | *initrd_size = 0; | |
211 | if (initrd_filename) { | |
212 | *initrd_addr = TARGET_PAGE_ALIGN(kernel_top); | |
213 | ||
214 | *initrd_size = load_image_targphys(initrd_filename, | |
215 | *initrd_addr, | |
216 | RAM_size - *initrd_addr); | |
217 | if ((int)*initrd_size < 0) { | |
218 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", | |
219 | initrd_filename); | |
220 | exit(1); | |
221 | } | |
222 | } | |
223 | if (*initrd_size > 0) { | |
224 | for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { | |
225 | ptr = rom_ptr(*kernel_addr + i); | |
226 | if (ldl_p(ptr + 8) == 0x48647253) { /* HdrS */ | |
227 | stl_p(ptr + 24, *initrd_addr + *kernel_addr); | |
228 | stl_p(ptr + 28, *initrd_size); | |
229 | break; | |
230 | } | |
231 | } | |
232 | } | |
233 | } | |
234 | return kernel_size; | |
235 | } | |
236 | ||
237 | void cpu_check_irqs(CPUSPARCState *env) | |
238 | { | |
239 | CPUState *cs; | |
240 | uint32_t pil = env->pil_in | | |
241 | (env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER)); | |
242 | ||
243 | /* TT_IVEC has a higher priority (16) than TT_EXTINT (31..17) */ | |
244 | if (env->ivec_status & 0x20) { | |
245 | return; | |
246 | } | |
247 | cs = CPU(sparc_env_get_cpu(env)); | |
248 | /* check if TM or SM in SOFTINT are set | |
249 | setting these also causes interrupt 14 */ | |
250 | if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) { | |
251 | pil |= 1 << 14; | |
252 | } | |
253 | ||
254 | /* The bit corresponding to psrpil is (1<< psrpil), the next bit | |
255 | is (2 << psrpil). */ | |
256 | if (pil < (2 << env->psrpil)){ | |
257 | if (cs->interrupt_request & CPU_INTERRUPT_HARD) { | |
258 | CPUIRQ_DPRINTF("Reset CPU IRQ (current interrupt %x)\n", | |
259 | env->interrupt_index); | |
260 | env->interrupt_index = 0; | |
261 | cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); | |
262 | } | |
263 | return; | |
264 | } | |
265 | ||
266 | if (cpu_interrupts_enabled(env)) { | |
267 | ||
268 | unsigned int i; | |
269 | ||
270 | for (i = 15; i > env->psrpil; i--) { | |
271 | if (pil & (1 << i)) { | |
272 | int old_interrupt = env->interrupt_index; | |
273 | int new_interrupt = TT_EXTINT | i; | |
274 | ||
275 | if (unlikely(env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt | |
276 | && ((cpu_tsptr(env)->tt & 0x1f0) == TT_EXTINT))) { | |
277 | CPUIRQ_DPRINTF("Not setting CPU IRQ: TL=%d " | |
278 | "current %x >= pending %x\n", | |
279 | env->tl, cpu_tsptr(env)->tt, new_interrupt); | |
280 | } else if (old_interrupt != new_interrupt) { | |
281 | env->interrupt_index = new_interrupt; | |
282 | CPUIRQ_DPRINTF("Set CPU IRQ %d old=%x new=%x\n", i, | |
283 | old_interrupt, new_interrupt); | |
284 | cpu_interrupt(cs, CPU_INTERRUPT_HARD); | |
285 | } | |
286 | break; | |
287 | } | |
288 | } | |
289 | } else if (cs->interrupt_request & CPU_INTERRUPT_HARD) { | |
290 | CPUIRQ_DPRINTF("Interrupts disabled, pil=%08x pil_in=%08x softint=%08x " | |
291 | "current interrupt %x\n", | |
292 | pil, env->pil_in, env->softint, env->interrupt_index); | |
293 | env->interrupt_index = 0; | |
294 | cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); | |
295 | } | |
296 | } | |
297 | ||
298 | static void cpu_kick_irq(SPARCCPU *cpu) | |
299 | { | |
300 | CPUState *cs = CPU(cpu); | |
301 | CPUSPARCState *env = &cpu->env; | |
302 | ||
303 | cs->halted = 0; | |
304 | cpu_check_irqs(env); | |
305 | qemu_cpu_kick(cs); | |
306 | } | |
307 | ||
308 | static void cpu_set_ivec_irq(void *opaque, int irq, int level) | |
309 | { | |
310 | SPARCCPU *cpu = opaque; | |
311 | CPUSPARCState *env = &cpu->env; | |
312 | CPUState *cs; | |
313 | ||
314 | if (level) { | |
315 | if (!(env->ivec_status & 0x20)) { | |
316 | CPUIRQ_DPRINTF("Raise IVEC IRQ %d\n", irq); | |
317 | cs = CPU(cpu); | |
318 | cs->halted = 0; | |
319 | env->interrupt_index = TT_IVEC; | |
320 | env->ivec_status |= 0x20; | |
321 | env->ivec_data[0] = (0x1f << 6) | irq; | |
322 | env->ivec_data[1] = 0; | |
323 | env->ivec_data[2] = 0; | |
324 | cpu_interrupt(cs, CPU_INTERRUPT_HARD); | |
325 | } | |
326 | } else { | |
327 | if (env->ivec_status & 0x20) { | |
328 | CPUIRQ_DPRINTF("Lower IVEC IRQ %d\n", irq); | |
329 | cs = CPU(cpu); | |
330 | env->ivec_status &= ~0x20; | |
331 | cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); | |
332 | } | |
333 | } | |
334 | } | |
335 | ||
336 | typedef struct ResetData { | |
337 | SPARCCPU *cpu; | |
338 | uint64_t prom_addr; | |
339 | } ResetData; | |
340 | ||
341 | static CPUTimer *cpu_timer_create(const char *name, SPARCCPU *cpu, | |
342 | QEMUBHFunc *cb, uint32_t frequency, | |
343 | uint64_t disabled_mask, uint64_t npt_mask) | |
344 | { | |
345 | CPUTimer *timer = g_malloc0(sizeof (CPUTimer)); | |
346 | ||
347 | timer->name = name; | |
348 | timer->frequency = frequency; | |
349 | timer->disabled_mask = disabled_mask; | |
350 | timer->npt_mask = npt_mask; | |
351 | ||
352 | timer->disabled = 1; | |
353 | timer->npt = 1; | |
354 | timer->clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | |
355 | ||
356 | timer->qtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL, cb, cpu); | |
357 | ||
358 | return timer; | |
359 | } | |
360 | ||
361 | static void cpu_timer_reset(CPUTimer *timer) | |
362 | { | |
363 | timer->disabled = 1; | |
364 | timer->clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | |
365 | ||
366 | timer_del(timer->qtimer); | |
367 | } | |
368 | ||
369 | static void main_cpu_reset(void *opaque) | |
370 | { | |
371 | ResetData *s = (ResetData *)opaque; | |
372 | CPUSPARCState *env = &s->cpu->env; | |
373 | static unsigned int nr_resets; | |
374 | ||
375 | cpu_reset(CPU(s->cpu)); | |
376 | ||
377 | cpu_timer_reset(env->tick); | |
378 | cpu_timer_reset(env->stick); | |
379 | cpu_timer_reset(env->hstick); | |
380 | ||
381 | env->gregs[1] = 0; // Memory start | |
382 | env->gregs[2] = ram_size; // Memory size | |
383 | env->gregs[3] = 0; // Machine description XXX | |
384 | if (nr_resets++ == 0) { | |
385 | /* Power on reset */ | |
386 | env->pc = s->prom_addr + 0x20ULL; | |
387 | } else { | |
388 | env->pc = s->prom_addr + 0x40ULL; | |
389 | } | |
390 | env->npc = env->pc + 4; | |
391 | } | |
392 | ||
393 | static void tick_irq(void *opaque) | |
394 | { | |
395 | SPARCCPU *cpu = opaque; | |
396 | CPUSPARCState *env = &cpu->env; | |
397 | ||
398 | CPUTimer* timer = env->tick; | |
399 | ||
400 | if (timer->disabled) { | |
401 | CPUIRQ_DPRINTF("tick_irq: softint disabled\n"); | |
402 | return; | |
403 | } else { | |
404 | CPUIRQ_DPRINTF("tick: fire\n"); | |
405 | } | |
406 | ||
407 | env->softint |= SOFTINT_TIMER; | |
408 | cpu_kick_irq(cpu); | |
409 | } | |
410 | ||
411 | static void stick_irq(void *opaque) | |
412 | { | |
413 | SPARCCPU *cpu = opaque; | |
414 | CPUSPARCState *env = &cpu->env; | |
415 | ||
416 | CPUTimer* timer = env->stick; | |
417 | ||
418 | if (timer->disabled) { | |
419 | CPUIRQ_DPRINTF("stick_irq: softint disabled\n"); | |
420 | return; | |
421 | } else { | |
422 | CPUIRQ_DPRINTF("stick: fire\n"); | |
423 | } | |
424 | ||
425 | env->softint |= SOFTINT_STIMER; | |
426 | cpu_kick_irq(cpu); | |
427 | } | |
428 | ||
429 | static void hstick_irq(void *opaque) | |
430 | { | |
431 | SPARCCPU *cpu = opaque; | |
432 | CPUSPARCState *env = &cpu->env; | |
433 | ||
434 | CPUTimer* timer = env->hstick; | |
435 | ||
436 | if (timer->disabled) { | |
437 | CPUIRQ_DPRINTF("hstick_irq: softint disabled\n"); | |
438 | return; | |
439 | } else { | |
440 | CPUIRQ_DPRINTF("hstick: fire\n"); | |
441 | } | |
442 | ||
443 | env->softint |= SOFTINT_STIMER; | |
444 | cpu_kick_irq(cpu); | |
445 | } | |
446 | ||
447 | static int64_t cpu_to_timer_ticks(int64_t cpu_ticks, uint32_t frequency) | |
448 | { | |
449 | return muldiv64(cpu_ticks, get_ticks_per_sec(), frequency); | |
450 | } | |
451 | ||
452 | static uint64_t timer_to_cpu_ticks(int64_t timer_ticks, uint32_t frequency) | |
453 | { | |
454 | return muldiv64(timer_ticks, frequency, get_ticks_per_sec()); | |
455 | } | |
456 | ||
457 | void cpu_tick_set_count(CPUTimer *timer, uint64_t count) | |
458 | { | |
459 | uint64_t real_count = count & ~timer->npt_mask; | |
460 | uint64_t npt_bit = count & timer->npt_mask; | |
461 | ||
462 | int64_t vm_clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - | |
463 | cpu_to_timer_ticks(real_count, timer->frequency); | |
464 | ||
465 | TIMER_DPRINTF("%s set_count count=0x%016lx (npt %s) p=%p\n", | |
466 | timer->name, real_count, | |
467 | timer->npt ? "disabled" : "enabled", timer); | |
468 | ||
469 | timer->npt = npt_bit ? 1 : 0; | |
470 | timer->clock_offset = vm_clock_offset; | |
471 | } | |
472 | ||
473 | uint64_t cpu_tick_get_count(CPUTimer *timer) | |
474 | { | |
475 | uint64_t real_count = timer_to_cpu_ticks( | |
476 | qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - timer->clock_offset, | |
477 | timer->frequency); | |
478 | ||
479 | TIMER_DPRINTF("%s get_count count=0x%016lx (npt %s) p=%p\n", | |
480 | timer->name, real_count, | |
481 | timer->npt ? "disabled" : "enabled", timer); | |
482 | ||
483 | if (timer->npt) { | |
484 | real_count |= timer->npt_mask; | |
485 | } | |
486 | ||
487 | return real_count; | |
488 | } | |
489 | ||
490 | void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit) | |
491 | { | |
492 | int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | |
493 | ||
494 | uint64_t real_limit = limit & ~timer->disabled_mask; | |
495 | timer->disabled = (limit & timer->disabled_mask) ? 1 : 0; | |
496 | ||
497 | int64_t expires = cpu_to_timer_ticks(real_limit, timer->frequency) + | |
498 | timer->clock_offset; | |
499 | ||
500 | if (expires < now) { | |
501 | expires = now + 1; | |
502 | } | |
503 | ||
504 | TIMER_DPRINTF("%s set_limit limit=0x%016lx (%s) p=%p " | |
505 | "called with limit=0x%016lx at 0x%016lx (delta=0x%016lx)\n", | |
506 | timer->name, real_limit, | |
507 | timer->disabled?"disabled":"enabled", | |
508 | timer, limit, | |
509 | timer_to_cpu_ticks(now - timer->clock_offset, | |
510 | timer->frequency), | |
511 | timer_to_cpu_ticks(expires - now, timer->frequency)); | |
512 | ||
513 | if (!real_limit) { | |
514 | TIMER_DPRINTF("%s set_limit limit=ZERO - not starting timer\n", | |
515 | timer->name); | |
516 | timer_del(timer->qtimer); | |
517 | } else if (timer->disabled) { | |
518 | timer_del(timer->qtimer); | |
519 | } else { | |
520 | timer_mod(timer->qtimer, expires); | |
521 | } | |
522 | } | |
523 | ||
524 | static void isa_irq_handler(void *opaque, int n, int level) | |
525 | { | |
526 | static const int isa_irq_to_ivec[16] = { | |
527 | [1] = 0x29, /* keyboard */ | |
528 | [4] = 0x2b, /* serial */ | |
529 | [6] = 0x27, /* floppy */ | |
530 | [7] = 0x22, /* parallel */ | |
531 | [12] = 0x2a, /* mouse */ | |
532 | }; | |
533 | qemu_irq *irqs = opaque; | |
534 | int ivec; | |
535 | ||
536 | assert(n < 16); | |
537 | ivec = isa_irq_to_ivec[n]; | |
538 | EBUS_DPRINTF("Set ISA IRQ %d level %d -> ivec 0x%x\n", n, level, ivec); | |
539 | if (ivec) { | |
540 | qemu_set_irq(irqs[ivec], level); | |
541 | } | |
542 | } | |
543 | ||
544 | /* EBUS (Eight bit bus) bridge */ | |
545 | static ISABus * | |
546 | pci_ebus_init(PCIBus *bus, int devfn, qemu_irq *irqs) | |
547 | { | |
548 | qemu_irq *isa_irq; | |
549 | PCIDevice *pci_dev; | |
550 | ISABus *isa_bus; | |
551 | ||
552 | pci_dev = pci_create_simple(bus, devfn, "ebus"); | |
553 | isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci_dev), "isa.0")); | |
554 | isa_irq = qemu_allocate_irqs(isa_irq_handler, irqs, 16); | |
555 | isa_bus_irqs(isa_bus, isa_irq); | |
556 | return isa_bus; | |
557 | } | |
558 | ||
559 | static void pci_ebus_realize(PCIDevice *pci_dev, Error **errp) | |
560 | { | |
561 | EbusState *s = DO_UPCAST(EbusState, pci_dev, pci_dev); | |
562 | ||
563 | if (!isa_bus_new(DEVICE(pci_dev), get_system_memory(), | |
564 | pci_address_space_io(pci_dev), errp)) { | |
565 | return; | |
566 | } | |
567 | ||
568 | pci_dev->config[0x04] = 0x06; // command = bus master, pci mem | |
569 | pci_dev->config[0x05] = 0x00; | |
570 | pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error | |
571 | pci_dev->config[0x07] = 0x03; // status = medium devsel | |
572 | pci_dev->config[0x09] = 0x00; // programming i/f | |
573 | pci_dev->config[0x0D] = 0x0a; // latency_timer | |
574 | ||
575 | memory_region_init_alias(&s->bar0, OBJECT(s), "bar0", get_system_io(), | |
576 | 0, 0x1000000); | |
577 | pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0); | |
578 | memory_region_init_alias(&s->bar1, OBJECT(s), "bar1", get_system_io(), | |
579 | 0, 0x4000); | |
580 | pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1); | |
581 | } | |
582 | ||
583 | static void ebus_class_init(ObjectClass *klass, void *data) | |
584 | { | |
585 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
586 | ||
587 | k->realize = pci_ebus_realize; | |
588 | k->vendor_id = PCI_VENDOR_ID_SUN; | |
589 | k->device_id = PCI_DEVICE_ID_SUN_EBUS; | |
590 | k->revision = 0x01; | |
591 | k->class_id = PCI_CLASS_BRIDGE_OTHER; | |
592 | } | |
593 | ||
594 | static const TypeInfo ebus_info = { | |
595 | .name = "ebus", | |
596 | .parent = TYPE_PCI_DEVICE, | |
597 | .instance_size = sizeof(EbusState), | |
598 | .class_init = ebus_class_init, | |
599 | }; | |
600 | ||
601 | #define TYPE_OPENPROM "openprom" | |
602 | #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM) | |
603 | ||
604 | typedef struct PROMState { | |
605 | SysBusDevice parent_obj; | |
606 | ||
607 | MemoryRegion prom; | |
608 | } PROMState; | |
609 | ||
610 | static uint64_t translate_prom_address(void *opaque, uint64_t addr) | |
611 | { | |
612 | hwaddr *base_addr = (hwaddr *)opaque; | |
613 | return addr + *base_addr - PROM_VADDR; | |
614 | } | |
615 | ||
616 | /* Boot PROM (OpenBIOS) */ | |
617 | static void prom_init(hwaddr addr, const char *bios_name) | |
618 | { | |
619 | DeviceState *dev; | |
620 | SysBusDevice *s; | |
621 | char *filename; | |
622 | int ret; | |
623 | ||
624 | dev = qdev_create(NULL, TYPE_OPENPROM); | |
625 | qdev_init_nofail(dev); | |
626 | s = SYS_BUS_DEVICE(dev); | |
627 | ||
628 | sysbus_mmio_map(s, 0, addr); | |
629 | ||
630 | /* load boot prom */ | |
631 | if (bios_name == NULL) { | |
632 | bios_name = PROM_FILENAME; | |
633 | } | |
634 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); | |
635 | if (filename) { | |
636 | ret = load_elf(filename, translate_prom_address, &addr, | |
637 | NULL, NULL, NULL, 1, EM_SPARCV9, 0, 0); | |
638 | if (ret < 0 || ret > PROM_SIZE_MAX) { | |
639 | ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); | |
640 | } | |
641 | g_free(filename); | |
642 | } else { | |
643 | ret = -1; | |
644 | } | |
645 | if (ret < 0 || ret > PROM_SIZE_MAX) { | |
646 | fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name); | |
647 | exit(1); | |
648 | } | |
649 | } | |
650 | ||
651 | static int prom_init1(SysBusDevice *dev) | |
652 | { | |
653 | PROMState *s = OPENPROM(dev); | |
654 | ||
655 | memory_region_init_ram(&s->prom, OBJECT(s), "sun4u.prom", PROM_SIZE_MAX, | |
656 | &error_fatal); | |
657 | vmstate_register_ram_global(&s->prom); | |
658 | memory_region_set_readonly(&s->prom, true); | |
659 | sysbus_init_mmio(dev, &s->prom); | |
660 | return 0; | |
661 | } | |
662 | ||
663 | static Property prom_properties[] = { | |
664 | {/* end of property list */}, | |
665 | }; | |
666 | ||
667 | static void prom_class_init(ObjectClass *klass, void *data) | |
668 | { | |
669 | DeviceClass *dc = DEVICE_CLASS(klass); | |
670 | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); | |
671 | ||
672 | k->init = prom_init1; | |
673 | dc->props = prom_properties; | |
674 | } | |
675 | ||
676 | static const TypeInfo prom_info = { | |
677 | .name = TYPE_OPENPROM, | |
678 | .parent = TYPE_SYS_BUS_DEVICE, | |
679 | .instance_size = sizeof(PROMState), | |
680 | .class_init = prom_class_init, | |
681 | }; | |
682 | ||
683 | ||
684 | #define TYPE_SUN4U_MEMORY "memory" | |
685 | #define SUN4U_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4U_MEMORY) | |
686 | ||
687 | typedef struct RamDevice { | |
688 | SysBusDevice parent_obj; | |
689 | ||
690 | MemoryRegion ram; | |
691 | uint64_t size; | |
692 | } RamDevice; | |
693 | ||
694 | /* System RAM */ | |
695 | static int ram_init1(SysBusDevice *dev) | |
696 | { | |
697 | RamDevice *d = SUN4U_RAM(dev); | |
698 | ||
699 | memory_region_init_ram(&d->ram, OBJECT(d), "sun4u.ram", d->size, | |
700 | &error_fatal); | |
701 | vmstate_register_ram_global(&d->ram); | |
702 | sysbus_init_mmio(dev, &d->ram); | |
703 | return 0; | |
704 | } | |
705 | ||
706 | static void ram_init(hwaddr addr, ram_addr_t RAM_size) | |
707 | { | |
708 | DeviceState *dev; | |
709 | SysBusDevice *s; | |
710 | RamDevice *d; | |
711 | ||
712 | /* allocate RAM */ | |
713 | dev = qdev_create(NULL, TYPE_SUN4U_MEMORY); | |
714 | s = SYS_BUS_DEVICE(dev); | |
715 | ||
716 | d = SUN4U_RAM(dev); | |
717 | d->size = RAM_size; | |
718 | qdev_init_nofail(dev); | |
719 | ||
720 | sysbus_mmio_map(s, 0, addr); | |
721 | } | |
722 | ||
723 | static Property ram_properties[] = { | |
724 | DEFINE_PROP_UINT64("size", RamDevice, size, 0), | |
725 | DEFINE_PROP_END_OF_LIST(), | |
726 | }; | |
727 | ||
728 | static void ram_class_init(ObjectClass *klass, void *data) | |
729 | { | |
730 | DeviceClass *dc = DEVICE_CLASS(klass); | |
731 | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); | |
732 | ||
733 | k->init = ram_init1; | |
734 | dc->props = ram_properties; | |
735 | } | |
736 | ||
737 | static const TypeInfo ram_info = { | |
738 | .name = TYPE_SUN4U_MEMORY, | |
739 | .parent = TYPE_SYS_BUS_DEVICE, | |
740 | .instance_size = sizeof(RamDevice), | |
741 | .class_init = ram_class_init, | |
742 | }; | |
743 | ||
744 | static SPARCCPU *cpu_devinit(const char *cpu_model, const struct hwdef *hwdef) | |
745 | { | |
746 | SPARCCPU *cpu; | |
747 | CPUSPARCState *env; | |
748 | ResetData *reset_info; | |
749 | ||
750 | uint32_t tick_frequency = 100*1000000; | |
751 | uint32_t stick_frequency = 100*1000000; | |
752 | uint32_t hstick_frequency = 100*1000000; | |
753 | ||
754 | if (cpu_model == NULL) { | |
755 | cpu_model = hwdef->default_cpu_model; | |
756 | } | |
757 | cpu = cpu_sparc_init(cpu_model); | |
758 | if (cpu == NULL) { | |
759 | fprintf(stderr, "Unable to find Sparc CPU definition\n"); | |
760 | exit(1); | |
761 | } | |
762 | env = &cpu->env; | |
763 | ||
764 | env->tick = cpu_timer_create("tick", cpu, tick_irq, | |
765 | tick_frequency, TICK_INT_DIS, | |
766 | TICK_NPT_MASK); | |
767 | ||
768 | env->stick = cpu_timer_create("stick", cpu, stick_irq, | |
769 | stick_frequency, TICK_INT_DIS, | |
770 | TICK_NPT_MASK); | |
771 | ||
772 | env->hstick = cpu_timer_create("hstick", cpu, hstick_irq, | |
773 | hstick_frequency, TICK_INT_DIS, | |
774 | TICK_NPT_MASK); | |
775 | ||
776 | reset_info = g_malloc0(sizeof(ResetData)); | |
777 | reset_info->cpu = cpu; | |
778 | reset_info->prom_addr = hwdef->prom_addr; | |
779 | qemu_register_reset(main_cpu_reset, reset_info); | |
780 | ||
781 | return cpu; | |
782 | } | |
783 | ||
784 | static void sun4uv_init(MemoryRegion *address_space_mem, | |
785 | MachineState *machine, | |
786 | const struct hwdef *hwdef) | |
787 | { | |
788 | SPARCCPU *cpu; | |
789 | Nvram *nvram; | |
790 | unsigned int i; | |
791 | uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry; | |
792 | PCIBus *pci_bus, *pci_bus2, *pci_bus3; | |
793 | ISABus *isa_bus; | |
794 | SysBusDevice *s; | |
795 | qemu_irq *ivec_irqs, *pbm_irqs; | |
796 | DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; | |
797 | DriveInfo *fd[MAX_FD]; | |
798 | DeviceState *dev; | |
799 | FWCfgState *fw_cfg; | |
800 | ||
801 | /* init CPUs */ | |
802 | cpu = cpu_devinit(machine->cpu_model, hwdef); | |
803 | ||
804 | /* set up devices */ | |
805 | ram_init(0, machine->ram_size); | |
806 | ||
807 | prom_init(hwdef->prom_addr, bios_name); | |
808 | ||
809 | ivec_irqs = qemu_allocate_irqs(cpu_set_ivec_irq, cpu, IVEC_MAX); | |
810 | pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, ivec_irqs, &pci_bus2, | |
811 | &pci_bus3, &pbm_irqs); | |
812 | pci_vga_init(pci_bus); | |
813 | ||
814 | // XXX Should be pci_bus3 | |
815 | isa_bus = pci_ebus_init(pci_bus, -1, pbm_irqs); | |
816 | ||
817 | i = 0; | |
818 | if (hwdef->console_serial_base) { | |
819 | serial_mm_init(address_space_mem, hwdef->console_serial_base, 0, | |
820 | NULL, 115200, serial_hds[i], DEVICE_BIG_ENDIAN); | |
821 | i++; | |
822 | } | |
823 | ||
824 | serial_hds_isa_init(isa_bus, MAX_SERIAL_PORTS); | |
825 | parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); | |
826 | ||
827 | for(i = 0; i < nb_nics; i++) | |
828 | pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL); | |
829 | ||
830 | ide_drive_get(hd, ARRAY_SIZE(hd)); | |
831 | ||
832 | pci_cmd646_ide_init(pci_bus, hd, 1); | |
833 | ||
834 | isa_create_simple(isa_bus, "i8042"); | |
835 | ||
836 | /* Floppy */ | |
837 | for(i = 0; i < MAX_FD; i++) { | |
838 | fd[i] = drive_get(IF_FLOPPY, 0, i); | |
839 | } | |
840 | dev = DEVICE(isa_create(isa_bus, TYPE_ISA_FDC)); | |
841 | if (fd[0]) { | |
842 | qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fd[0]), | |
843 | &error_abort); | |
844 | } | |
845 | if (fd[1]) { | |
846 | qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fd[1]), | |
847 | &error_abort); | |
848 | } | |
849 | qdev_prop_set_uint32(dev, "dma", -1); | |
850 | qdev_init_nofail(dev); | |
851 | ||
852 | /* Map NVRAM into I/O (ebus) space */ | |
853 | nvram = m48t59_init(NULL, 0, 0, NVRAM_SIZE, 1968, 59); | |
854 | s = SYS_BUS_DEVICE(nvram); | |
855 | memory_region_add_subregion(get_system_io(), 0x2000, | |
856 | sysbus_mmio_get_region(s, 0)); | |
857 | ||
858 | initrd_size = 0; | |
859 | initrd_addr = 0; | |
860 | kernel_size = sun4u_load_kernel(machine->kernel_filename, | |
861 | machine->initrd_filename, | |
862 | ram_size, &initrd_size, &initrd_addr, | |
863 | &kernel_addr, &kernel_entry); | |
864 | ||
865 | sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", machine->ram_size, | |
866 | machine->boot_order, | |
867 | kernel_addr, kernel_size, | |
868 | machine->kernel_cmdline, | |
869 | initrd_addr, initrd_size, | |
870 | /* XXX: need an option to load a NVRAM image */ | |
871 | 0, | |
872 | graphic_width, graphic_height, graphic_depth, | |
873 | (uint8_t *)&nd_table[0].macaddr); | |
874 | ||
875 | fw_cfg = fw_cfg_init_io(BIOS_CFG_IOPORT); | |
876 | fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); | |
877 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); | |
878 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); | |
879 | fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry); | |
880 | fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); | |
881 | if (machine->kernel_cmdline) { | |
882 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, | |
883 | strlen(machine->kernel_cmdline) + 1); | |
884 | fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline); | |
885 | } else { | |
886 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); | |
887 | } | |
888 | fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); | |
889 | fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); | |
890 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]); | |
891 | ||
892 | fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width); | |
893 | fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height); | |
894 | fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth); | |
895 | ||
896 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); | |
897 | } | |
898 | ||
899 | enum { | |
900 | sun4u_id = 0, | |
901 | sun4v_id = 64, | |
902 | niagara_id, | |
903 | }; | |
904 | ||
905 | static const struct hwdef hwdefs[] = { | |
906 | /* Sun4u generic PC-like machine */ | |
907 | { | |
908 | .default_cpu_model = "TI UltraSparc IIi", | |
909 | .machine_id = sun4u_id, | |
910 | .prom_addr = 0x1fff0000000ULL, | |
911 | .console_serial_base = 0, | |
912 | }, | |
913 | /* Sun4v generic PC-like machine */ | |
914 | { | |
915 | .default_cpu_model = "Sun UltraSparc T1", | |
916 | .machine_id = sun4v_id, | |
917 | .prom_addr = 0x1fff0000000ULL, | |
918 | .console_serial_base = 0, | |
919 | }, | |
920 | /* Sun4v generic Niagara machine */ | |
921 | { | |
922 | .default_cpu_model = "Sun UltraSparc T1", | |
923 | .machine_id = niagara_id, | |
924 | .prom_addr = 0xfff0000000ULL, | |
925 | .console_serial_base = 0xfff0c2c000ULL, | |
926 | }, | |
927 | }; | |
928 | ||
929 | /* Sun4u hardware initialisation */ | |
930 | static void sun4u_init(MachineState *machine) | |
931 | { | |
932 | sun4uv_init(get_system_memory(), machine, &hwdefs[0]); | |
933 | } | |
934 | ||
935 | /* Sun4v hardware initialisation */ | |
936 | static void sun4v_init(MachineState *machine) | |
937 | { | |
938 | sun4uv_init(get_system_memory(), machine, &hwdefs[1]); | |
939 | } | |
940 | ||
941 | /* Niagara hardware initialisation */ | |
942 | static void niagara_init(MachineState *machine) | |
943 | { | |
944 | sun4uv_init(get_system_memory(), machine, &hwdefs[2]); | |
945 | } | |
946 | ||
947 | static void sun4u_class_init(ObjectClass *oc, void *data) | |
948 | { | |
949 | MachineClass *mc = MACHINE_CLASS(oc); | |
950 | ||
951 | mc->desc = "Sun4u platform"; | |
952 | mc->init = sun4u_init; | |
953 | mc->max_cpus = 1; /* XXX for now */ | |
954 | mc->is_default = 1; | |
955 | mc->default_boot_order = "c"; | |
956 | } | |
957 | ||
958 | static const TypeInfo sun4u_type = { | |
959 | .name = MACHINE_TYPE_NAME("sun4u"), | |
960 | .parent = TYPE_MACHINE, | |
961 | .class_init = sun4u_class_init, | |
962 | }; | |
963 | ||
964 | static void sun4v_class_init(ObjectClass *oc, void *data) | |
965 | { | |
966 | MachineClass *mc = MACHINE_CLASS(oc); | |
967 | ||
968 | mc->desc = "Sun4v platform"; | |
969 | mc->init = sun4v_init; | |
970 | mc->max_cpus = 1; /* XXX for now */ | |
971 | mc->default_boot_order = "c"; | |
972 | } | |
973 | ||
974 | static const TypeInfo sun4v_type = { | |
975 | .name = MACHINE_TYPE_NAME("sun4v"), | |
976 | .parent = TYPE_MACHINE, | |
977 | .class_init = sun4v_class_init, | |
978 | }; | |
979 | ||
980 | static void niagara_class_init(ObjectClass *oc, void *data) | |
981 | { | |
982 | MachineClass *mc = MACHINE_CLASS(oc); | |
983 | ||
984 | mc->desc = "Sun4v platform, Niagara"; | |
985 | mc->init = niagara_init; | |
986 | mc->max_cpus = 1; /* XXX for now */ | |
987 | mc->default_boot_order = "c"; | |
988 | } | |
989 | ||
990 | static const TypeInfo niagara_type = { | |
991 | .name = MACHINE_TYPE_NAME("Niagara"), | |
992 | .parent = TYPE_MACHINE, | |
993 | .class_init = niagara_class_init, | |
994 | }; | |
995 | ||
996 | static void sun4u_register_types(void) | |
997 | { | |
998 | type_register_static(&ebus_info); | |
999 | type_register_static(&prom_info); | |
1000 | type_register_static(&ram_info); | |
1001 | ||
1002 | type_register_static(&sun4u_type); | |
1003 | type_register_static(&sun4v_type); | |
1004 | type_register_static(&niagara_type); | |
1005 | } | |
1006 | ||
1007 | type_init(sun4u_register_types) |