[mirror_qemu.git] / hw / timer / pl031.c

/*
 * ARM AMBA PrimeCell PL031 RTC
 *
 * Copyright (c) 2007 CodeSourcery
 *
 * This file is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Contributions after 2012-01-13 are licensed under the terms of the
 * GNU GPL, version 2 or (at your option) any later version.
 */

#include "qemu/osdep.h"
#include "hw/timer/pl031.h"
#include "hw/sysbus.h"
#include "qemu/timer.h"
#include "sysemu/sysemu.h"
#include "qemu/cutils.h"
#include "qemu/log.h"

//#define DEBUG_PL031

#ifdef DEBUG_PL031
#define DPRINTF(fmt, ...) \
do { printf("pl031: " fmt , ## __VA_ARGS__); } while (0)
#else
#define DPRINTF(fmt, ...) do {} while(0)
#endif

#define RTC_DR      0x00    /* Data read register */
#define RTC_MR      0x04    /* Match register */
#define RTC_LR      0x08    /* Data load register */
#define RTC_CR      0x0c    /* Control register */
#define RTC_IMSC    0x10    /* Interrupt mask and set register */
#define RTC_RIS     0x14    /* Raw interrupt status register */
#define RTC_MIS     0x18    /* Masked interrupt status register */
#define RTC_ICR     0x1c    /* Interrupt clear register */

static const unsigned char pl031_id[] = {
    0x31, 0x10, 0x14, 0x00,         /* Device ID        */
    0x0d, 0xf0, 0x05, 0xb1          /* Cell ID      */
};

static void pl031_update(PL031State *s)
{
    qemu_set_irq(s->irq, s->is & s->im);
}

static void pl031_interrupt(void * opaque)
{
    PL031State *s = (PL031State *)opaque;

    s->is = 1;
    DPRINTF("Alarm raised\n");
    pl031_update(s);
}

static uint32_t pl031_get_count(PL031State *s)
{
    int64_t now = qemu_clock_get_ns(rtc_clock);
    return s->tick_offset + now / NANOSECONDS_PER_SECOND;
}

static void pl031_set_alarm(PL031State *s)
{
    uint32_t ticks;

    /* The timer wraps around.  This subtraction also wraps in the same way,
       and gives correct results when alarm < now_ticks.  */
    ticks = s->mr - pl031_get_count(s);
    DPRINTF("Alarm set in %ud ticks\n", ticks);
    if (ticks == 0) {
        timer_del(s->timer);
        pl031_interrupt(s);
    } else {
        int64_t now = qemu_clock_get_ns(rtc_clock);
        timer_mod(s->timer, now + (int64_t)ticks * NANOSECONDS_PER_SECOND);
    }
}

static uint64_t pl031_read(void *opaque, hwaddr offset,
                           unsigned size)
{
    PL031State *s = (PL031State *)opaque;

    if (offset >= 0xfe0  &&  offset < 0x1000)
        return pl031_id[(offset - 0xfe0) >> 2];

    switch (offset) {
    case RTC_DR:
        return pl031_get_count(s);
    case RTC_MR:
        return s->mr;
    case RTC_IMSC:
        return s->im;
    case RTC_RIS:
        return s->is;
    case RTC_LR:
        return s->lr;
    case RTC_CR:
        /* RTC is permanently enabled.  */
        return 1;
    case RTC_MIS:
        return s->is & s->im;
    case RTC_ICR:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "pl031: read of write-only register at offset 0x%x\n",
                      (int)offset);
        break;
    default:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "pl031_read: Bad offset 0x%x\n", (int)offset);
        break;
    }

    return 0;
}

static void pl031_write(void * opaque, hwaddr offset,
                        uint64_t value, unsigned size)
{
    PL031State *s = (PL031State *)opaque;


    switch (offset) {
    case RTC_LR:
        s->tick_offset += value - pl031_get_count(s);
        pl031_set_alarm(s);
        break;
    case RTC_MR:
        s->mr = value;
        pl031_set_alarm(s);
        break;
    case RTC_IMSC:
        s->im = value & 1;
        DPRINTF("Interrupt mask %d\n", s->im);
        pl031_update(s);
        break;
    case RTC_ICR:
        /* The PL031 documentation (DDI0224B) states that the interrupt is
           cleared when bit 0 of the written value is set.  However the
           arm926e documentation (DDI0287B) states that the interrupt is
           cleared when any value is written.  */
        DPRINTF("Interrupt cleared");
        s->is = 0;
        pl031_update(s);
        break;
    case RTC_CR:
        /* Written value is ignored.  */
        break;

    case RTC_DR:
    case RTC_MIS:
    case RTC_RIS:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "pl031: write to read-only register at offset 0x%x\n",
                      (int)offset);
        break;

    default:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "pl031_write: Bad offset 0x%x\n", (int)offset);
        break;
    }
}

static const MemoryRegionOps pl031_ops = {
    .read = pl031_read,
    .write = pl031_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void pl031_init(Object *obj)
{
    PL031State *s = PL031(obj);
    SysBusDevice *dev = SYS_BUS_DEVICE(obj);
    struct tm tm;

    memory_region_init_io(&s->iomem, obj, &pl031_ops, s, "pl031", 0x1000);
    sysbus_init_mmio(dev, &s->iomem);

    sysbus_init_irq(dev, &s->irq);
    qemu_get_timedate(&tm, 0);
    s->tick_offset = mktimegm(&tm) -
        qemu_clock_get_ns(rtc_clock) / NANOSECONDS_PER_SECOND;

    s->timer = timer_new_ns(rtc_clock, pl031_interrupt, s);
}

static int pl031_pre_save(void *opaque)
{
    PL031State *s = opaque;

    /* tick_offset is base_time - rtc_clock base time.  Instead, we want to
     * store the base time relative to the QEMU_CLOCK_VIRTUAL for backwards-compatibility.  */
    int64_t delta = qemu_clock_get_ns(rtc_clock) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
    s->tick_offset_vmstate = s->tick_offset + delta / NANOSECONDS_PER_SECOND;

    return 0;
}

static int pl031_post_load(void *opaque, int version_id)
{
    PL031State *s = opaque;

    int64_t delta = qemu_clock_get_ns(rtc_clock) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
    s->tick_offset = s->tick_offset_vmstate - delta / NANOSECONDS_PER_SECOND;
    pl031_set_alarm(s);
    return 0;
}

static const VMStateDescription vmstate_pl031 = {
    .name = "pl031",
    .version_id = 1,
    .minimum_version_id = 1,
    .pre_save = pl031_pre_save,
    .post_load = pl031_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(tick_offset_vmstate, PL031State),
        VMSTATE_UINT32(mr, PL031State),
        VMSTATE_UINT32(lr, PL031State),
        VMSTATE_UINT32(cr, PL031State),
        VMSTATE_UINT32(im, PL031State),
        VMSTATE_UINT32(is, PL031State),
        VMSTATE_END_OF_LIST()
    }
};

static void pl031_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->vmsd = &vmstate_pl031;
}

static const TypeInfo pl031_info = {
    .name          = TYPE_PL031,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(PL031State),
    .instance_init = pl031_init,
    .class_init    = pl031_class_init,
};

static void pl031_register_types(void)
{
    type_register_static(&pl031_info);
}

type_init(pl031_register_types)
Commit	Line	Data
	1	/*
	2	* ARM AMBA PrimeCell PL031 RTC
	3	*
	4	* Copyright (c) 2007 CodeSourcery
	5	*
	6	* This file is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* Contributions after 2012-01-13 are licensed under the terms of the
	11	* GNU GPL, version 2 or (at your option) any later version.
	12	*/
	13
	14	#include "qemu/osdep.h"
	15	#include "hw/timer/pl031.h"
	16	#include "hw/sysbus.h"
	17	#include "qemu/timer.h"
	18	#include "sysemu/sysemu.h"
	19	#include "qemu/cutils.h"
	20	#include "qemu/log.h"
	21
	22	//#define DEBUG_PL031
	23
	24	#ifdef DEBUG_PL031
	25	#define DPRINTF(fmt, ...) \
	26	do { printf("pl031: " fmt , ## __VA_ARGS__); } while (0)
	27	#else
	28	#define DPRINTF(fmt, ...) do {} while(0)
	29	#endif
	30
	31	#define RTC_DR 0x00 /* Data read register */
	32	#define RTC_MR 0x04 /* Match register */
	33	#define RTC_LR 0x08 /* Data load register */
	34	#define RTC_CR 0x0c /* Control register */
	35	#define RTC_IMSC 0x10 /* Interrupt mask and set register */
	36	#define RTC_RIS 0x14 /* Raw interrupt status register */
	37	#define RTC_MIS 0x18 /* Masked interrupt status register */
	38	#define RTC_ICR 0x1c /* Interrupt clear register */
	39
	40	static const unsigned char pl031_id[] = {
	41	0x31, 0x10, 0x14, 0x00, /* Device ID */
	42	0x0d, 0xf0, 0x05, 0xb1 /* Cell ID */
	43	};
	44
	45	static void pl031_update(PL031State *s)
	46	{
	47	qemu_set_irq(s->irq, s->is & s->im);
	48	}
	49
	50	static void pl031_interrupt(void * opaque)
	51	{
	52	PL031State s = (PL031State )opaque;
	53
	54	s->is = 1;
	55	DPRINTF("Alarm raised\n");
	56	pl031_update(s);
	57	}
	58
	59	static uint32_t pl031_get_count(PL031State *s)
	60	{
	61	int64_t now = qemu_clock_get_ns(rtc_clock);
	62	return s->tick_offset + now / NANOSECONDS_PER_SECOND;
	63	}
	64
	65	static void pl031_set_alarm(PL031State *s)
	66	{
	67	uint32_t ticks;
	68
	69	/* The timer wraps around. This subtraction also wraps in the same way,
	70	and gives correct results when alarm < now_ticks. */
	71	ticks = s->mr - pl031_get_count(s);
	72	DPRINTF("Alarm set in %ud ticks\n", ticks);
	73	if (ticks == 0) {
	74	timer_del(s->timer);
	75	pl031_interrupt(s);
	76	} else {
	77	int64_t now = qemu_clock_get_ns(rtc_clock);
	78	timer_mod(s->timer, now + (int64_t)ticks * NANOSECONDS_PER_SECOND);
	79	}
	80	}
	81
	82	static uint64_t pl031_read(void *opaque, hwaddr offset,
	83	unsigned size)
	84	{
	85	PL031State s = (PL031State )opaque;
	86
	87	if (offset >= 0xfe0 && offset < 0x1000)
	88	return pl031_id[(offset - 0xfe0) >> 2];
	89
	90	switch (offset) {
	91	case RTC_DR:
	92	return pl031_get_count(s);
	93	case RTC_MR:
	94	return s->mr;
	95	case RTC_IMSC:
	96	return s->im;
	97	case RTC_RIS:
	98	return s->is;
	99	case RTC_LR:
	100	return s->lr;
	101	case RTC_CR:
	102	/* RTC is permanently enabled. */
	103	return 1;
	104	case RTC_MIS:
	105	return s->is & s->im;
	106	case RTC_ICR:
	107	qemu_log_mask(LOG_GUEST_ERROR,
	108	"pl031: read of write-only register at offset 0x%x\n",
	109	(int)offset);
	110	break;
	111	default:
	112	qemu_log_mask(LOG_GUEST_ERROR,
	113	"pl031_read: Bad offset 0x%x\n", (int)offset);
	114	break;
	115	}
	116
	117	return 0;
	118	}
	119
	120	static void pl031_write(void * opaque, hwaddr offset,
	121	uint64_t value, unsigned size)
	122	{
	123	PL031State s = (PL031State )opaque;
	124
	125
	126	switch (offset) {
	127	case RTC_LR:
	128	s->tick_offset += value - pl031_get_count(s);
	129	pl031_set_alarm(s);
	130	break;
	131	case RTC_MR:
	132	s->mr = value;
	133	pl031_set_alarm(s);
	134	break;
	135	case RTC_IMSC:
	136	s->im = value & 1;
	137	DPRINTF("Interrupt mask %d\n", s->im);
	138	pl031_update(s);
	139	break;
	140	case RTC_ICR:
	141	/* The PL031 documentation (DDI0224B) states that the interrupt is
	142	cleared when bit 0 of the written value is set. However the
	143	arm926e documentation (DDI0287B) states that the interrupt is
	144	cleared when any value is written. */
	145	DPRINTF("Interrupt cleared");
	146	s->is = 0;
	147	pl031_update(s);
	148	break;
	149	case RTC_CR:
	150	/* Written value is ignored. */
	151	break;
	152
	153	case RTC_DR:
	154	case RTC_MIS:
	155	case RTC_RIS:
	156	qemu_log_mask(LOG_GUEST_ERROR,
	157	"pl031: write to read-only register at offset 0x%x\n",
	158	(int)offset);
	159	break;
	160
	161	default:
	162	qemu_log_mask(LOG_GUEST_ERROR,
	163	"pl031_write: Bad offset 0x%x\n", (int)offset);
	164	break;
	165	}
	166	}
	167
	168	static const MemoryRegionOps pl031_ops = {
	169	.read = pl031_read,
	170	.write = pl031_write,
	171	.endianness = DEVICE_NATIVE_ENDIAN,
	172	};
	173
	174	static void pl031_init(Object *obj)
	175	{
	176	PL031State *s = PL031(obj);
	177	SysBusDevice *dev = SYS_BUS_DEVICE(obj);
	178	struct tm tm;
	179
	180	memory_region_init_io(&s->iomem, obj, &pl031_ops, s, "pl031", 0x1000);
	181	sysbus_init_mmio(dev, &s->iomem);
	182
	183	sysbus_init_irq(dev, &s->irq);
	184	qemu_get_timedate(&tm, 0);
	185	s->tick_offset = mktimegm(&tm) -
	186	qemu_clock_get_ns(rtc_clock) / NANOSECONDS_PER_SECOND;
	187
	188	s->timer = timer_new_ns(rtc_clock, pl031_interrupt, s);
	189	}
	190
	191	static int pl031_pre_save(void *opaque)
	192	{
	193	PL031State *s = opaque;
	194
	195	/* tick_offset is base_time - rtc_clock base time. Instead, we want to
	196	* store the base time relative to the QEMU_CLOCK_VIRTUAL for backwards-compatibility. */
	197	int64_t delta = qemu_clock_get_ns(rtc_clock) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
	198	s->tick_offset_vmstate = s->tick_offset + delta / NANOSECONDS_PER_SECOND;
	199
	200	return 0;
	201	}
	202
	203	static int pl031_post_load(void *opaque, int version_id)
	204	{
	205	PL031State *s = opaque;
	206
	207	int64_t delta = qemu_clock_get_ns(rtc_clock) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
	208	s->tick_offset = s->tick_offset_vmstate - delta / NANOSECONDS_PER_SECOND;
	209	pl031_set_alarm(s);
	210	return 0;
	211	}
	212
	213	static const VMStateDescription vmstate_pl031 = {
	214	.name = "pl031",
	215	.version_id = 1,
	216	.minimum_version_id = 1,
	217	.pre_save = pl031_pre_save,
	218	.post_load = pl031_post_load,
	219	.fields = (VMStateField[]) {
	220	VMSTATE_UINT32(tick_offset_vmstate, PL031State),
	221	VMSTATE_UINT32(mr, PL031State),
	222	VMSTATE_UINT32(lr, PL031State),
	223	VMSTATE_UINT32(cr, PL031State),
	224	VMSTATE_UINT32(im, PL031State),
	225	VMSTATE_UINT32(is, PL031State),
	226	VMSTATE_END_OF_LIST()
	227	}
	228	};
	229
	230	static void pl031_class_init(ObjectClass klass, void data)
	231	{
	232	DeviceClass *dc = DEVICE_CLASS(klass);
	233
	234	dc->vmsd = &vmstate_pl031;
	235	}
	236
	237	static const TypeInfo pl031_info = {
	238	.name = TYPE_PL031,
	239	.parent = TYPE_SYS_BUS_DEVICE,
	240	.instance_size = sizeof(PL031State),
	241	.instance_init = pl031_init,
	242	.class_init = pl031_class_init,
	243	};
	244
	245	static void pl031_register_types(void)
	246	{
	247	type_register_static(&pl031_info);
	248	}
	249
	250	type_init(pl031_register_types)